PRACTICAL NO: 1
Aim: Write VHDL code for basic gates: AND, OR, NOT
Resources:
Equipment/Instruments: PERSONAL COMPUTER
Software Required: XILINX 8.1
Theory:-
AND:
The AND gate is an electronic circuit that gives a high output (1) only if all its inputs are
high. A dot (.) is used to show the AND operation i.e. A.B.
OR:
The OR gate is an electronic circuit that gives a high output (1) if one or more of its
inputs are high. A plus (+) is used to show the OR operation.
NOT:
The NOT gate is an electronic circuit that produces an inverted version of the input at its
output. It is also known as an inverter. If the input variable is A, the inverted output is known as
NOT A. This is also shown as A', or A with a bar over the top.
Procedure:
1. Click on FPGA advantage icon on the desktop.
2. Click on file menuànewàproject.
3. Create a new path for the project workspace.
4. Then, go to Fileànewàdesign contentàVHDL fileàentity.
5. Now, give the name of the entity & click next, then an editor window opens,
6. Declare the input, output ports in the entity and save it.
7. Fileànewàdesign contentàVHDL fileàarchitecture.
8. Now, give the name of the entity you gave before and a architecture name and click next,
then a editor window opens, write the required style of code and save it.
9. Click the project file and verify the errors by CHECK button.
10. If no errors, click on simulate button, then modelsim gets started, select the ports and give
them to “select to wave” option and type the force commands and run command ,then the
graph is displayed.
11. After that, move to design manager window, select the project file and click on
synthesize button, then Leonardo Spectrum windows gets opened, in that, click on view
RTL schematic button, the required logic diagram is displayed.
Observations:
AND GATE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity AND1 is
port (a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC) ;
end AND1;
architecture
behavioral of AND1
is begin
process (a, b)
begin
if (a=‟1‟ and b=‟1‟)
then
c<=‟1‟;
else
c<=‟0‟;
End if;
End process;
End behavioral
OR GATE:
library IEEE;
use IEEE.std_logic_1164.all;
entity orGate is
port(A : in std_logic; -- OR gate input
B : in std_logic; -- OR gate input
Y : out std_logic); -- OR gate output
end orGate;
architecture orLogic of orGate is
begin
Y <= A OR B;
end orLogic;
NOT GATE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity NOT1 is
port (a : in STD_LOGIC; c : out STD_LOGIC) ;
end NOT1;
architecture
behavioral of NOT1
is begin
process (a)
begin
if (a=‟0‟)
then
c<=‟1‟;
else
c<=‟0‟;
end if;
end process;
end behavioral;
Results/Comments:
Snapshots of VHDL code of AND gate:
Snapshots of VHDL code of OR gate:
Snapshots of VHDL code of NOT gate
Conclusion:
The VHDL code for all basic gates is written, simulated and synthesized.
