© 2017 IJSRSET | Volume 3 | Issue 6 | Print ISSN: 2395-1990 | Online ISSN : 2394-4099

Themed Section: Engineering and Technology

Brief Introduction about VHDL Implementation of CVSD Codec

Neha Sharma, Amrita Soni, Piyush Gupta
Elex and Communication Department, Ujjain Engineering College, Ujjain, Madya Pradesh, India

ABSTRACT

In order for the signal to have good quality, the slope-overload error desires to be as small as possible. Adaptive
delta modulation reduces the slope over load error to a greater extent. One of the algorithms of ADM is CVSD
algorithm. CVSD (continuous variable slope delta) modulation is an effective scheme for audio signal. CVSD is
best coding technique for improving receiver sensitivity with low transmission rate as compare to PCM. Here in this
paper, we discuss the implementation of CVSD codec system using VHDL (Very High Speed Integrated Circuit
Hardware Description Language). VHDL provides structure to be modelled and simulated before synthesis tools
(XST tools). It allows the description of a concurrent system. It is portable and multipurpose. These paper is also
describes the various RTL schematic of each module of the CVSD codec and the connections of all RTL blocks in
Top level design.
Keywords: Register Transfer Level (RTL), DM, ADM, VHDL, Verilog, PIPO, SIPO.

I. INTRODUCTION adaptive DM scheme offering low hardware complexity,

improved noise performance and minimum transmission
Design of CVSD codec algorithm using VHDL (Very Bandwidth [2]. It is an attractive alternative to more
High Speed Integrated Circuit Hardware Description complex conventional analog to digital signal
Language) VHDL is commonly used to model the conversion techniques used in telecommunication and
digital system. signal processing. To implement CVSD, There are few
CVSD chip sets such as MC34115 from Motorola [1-4]
Continuously variable slope delta modulation but it works only at 16 kbps and it does not allow
(CVSD or CVSDM) is an audio encoding method. It is adding encryption to the algorithm, which is very
a delta modulation with variable step size [3]. Because important in defence systems for security purposes.
of variation in step size slope overload error is reduces CVSD is used in both commercial and military
as compare to delta modulation [6]. The CVSD communications where "toll quality" or
modulation is a method of digitizing a band-limited "communications quality" is required, yet low
audio signal. The CVSD modulator is many to one bit computation complexity and low memory requirements
compression technique, which compresses the 8 bit into are desirable. Two examples of this technique are U.S.
1 bit or 16 bit into 1 bit or 12 bit data into one single bit. MIL-STD-188-113 (16 kbps and 32kbps CVSD) and
It is a lossy compression technique. The output of this U.S. Federal Standard 1023 (12 kbs CVSD) [5]. In
1-bit encoder is a serial bit stream, where each bit addition, encoded CVSD data can be encrypted and
represents an incremental increase or decrease in signal made more secure (because of adaptive in nature),
steps amplitude level. The continuously variable slope which is desirable for many wireless communications
delta (CVSD) modulation is a nonlinear [1], sampled applications including speech and general-purpose
data, closed loop system which accepts a band-limited audio coding. Furthermore, to implement such
analog signal and encodes it into binary form for algorithms with encryption possible, software (i.e.
transmission in a digital channel. At the receiver, the programming in DSP/GPP) and hardware (i.e.
binary signal is decoded into a close approximation of programming in FPGA or ASIC i.e. programming in
the original amplitude level. Continuously Variable VHDL or Verilog) approaches are available.
slope Delta Modulation is a simple syllabically step

IJSRSET173630 | Received : 01 Sep 2017 | Accepted : 11 Sep 2017 | September-October-2017 [(3)6: 92-96] 92
 always 0. For every positive edge of the clock, the
comparator gives the output.
II. Various Modules and RTL Schematics

A. 8 bit comparator design

Data comparisons are mostly needed in digital systems

while performing arithmetic and logical operations. The
comparison determines whether one number is greater
than equal to, or less than the other number. A digital
comparator is widely used in combinational system and
is specially designed to compare the relative magnitudes
(decimal equivalent of binary numbers). These are also
available in IC form with different bit comparing
configurations such as 2-bit, 4-bit, 8-bit, etc. More than
one comparator can also be connected in cascading
Figure 2. Test-bench simulation of 8 bit comparator
arrangement to perform comparison of numbers of
created in Xilinx
longer lengths like 8 bit or more. Whenever we want to
compare the two binary numbers, first we have to
B. 8 bit PIPO register
compare the MSB of the inputs. Here, two binary
variables are used to indicate the outcome of the
Parallel in Parallel out (PIPO) shift registers are the
comparison as a ≥ b or a < b („a‟ and „b‟ are 8 bit input
type of storage device, which holds the data for 1 clock
array). The below figure shows the RTL Schematic of 8
cycle. Here PIPO register is used as an buffer to provide
bit comparator Module which is Created by VHDL code
1 clock cycle delay for providing comparison between
in Xilinx.
present input and previously selected output.

Figure 1. 8 bit Comparator RTL Schematic view in Figure 3. 8 bit PIPO RTL schematic view in Xilinx
Xilinx
Here in above RTL schematic two block connected to Here in above RTL schematic the input is D (7:0) is 8
one OR gate. If a>b the output of block one is high bit parallel input and Q(7:0) is 8 bit parallel output. The
otherwise low. If a=b then output of second block is clock signal is given by “clk” and reset is inverted and
high otherwise low. So if a<b then output of the OR connected to clear of the flip flops. “fdc” is the group of
gate is low otherwise output of OR gate us high. The 8 flip flops, whose output is Q(7:0) i.e. 8 bit parallel
output of OR gate is connected to D flip-flop. The D output.
flip- flop output is the output of the 8 bit comparator.
The Flip- flop is connected to the clock (clk), and Reset
input. If the reset is low then output of the comparator is

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 Figure 4. Test-bench simulation of 8 bit PIPO register
created in Xilinx Figure 6. Test-bench simulation of 3 bit SIPO register
Here shows in above figure, the first signal shows is created in Xilinx
system clock signal, second signal is reset given to
HIGH, third signal is 8 bit input signal and fourth signal The above figure shows the test-bench simulation of 3
is 8 bit output signal. There is one clock cycle delay bit SIPO register. The first signal is clock signal ,
between input and output signal as shown in above second is reset given to active HIGH, third signal is
figure. input signal and the fourth signal is 3 bit parallel output
signal.
C. 3 bit SIPO Register
D. CVSD Level select Algorithm
3 bit serial in parallel out shift register is used to store
the three output of the comparator. The 1 bit input The CVSD modulator consist an 8 bit comparator for
signal is din and the 3 bit output is given by dout (2:0). comparing i/p signal with reference signal, 3 bit sipo
The clock is given by clk input signal. The output of the (serial in parallel out) for detecting slope overload, 8 bit
SIPO register is come at every positive edge of clock pipo (parallel in parallel out) for providing 1 clock cycle
signal. delay , overload detect and level select algorithm is used
for selecting the variable step size. The present input
compared with previous level selected output in 8 bit
comparator. The comparator output is a digital encoded
output which is 1 bit compressed output of 8 bit A to D
input. If the output of the comparator is HIGH i.e. 1
then the 8 bit selected input is increased by one bit. If
the output of the comparator is 0 the 8 bit selected input
is decremented by 1 bit. If the output of comparator is
“111” or “000” the previously selected input is
incremented or decremented by some constant
respectively. The below figure is RTL schematic of
CVSD level select algorithm.

Figure 5. 3 bit SIPO RTL schematic view in Xilinx

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94
 Figure 7. RTL view of CVSD level select module
created in Xilinx

E. CVSD Top Module Figure 8. RTL view of CVSD TOP module created in
Xilinx
The CVSD top module is designed by stuctural
modeling in VHDL. The below figure is RTL schematic III. SNR CALCULATION
of combinations of all the modules. The CVSD encoder
consist an 8 bit comparator for comparing i/p signal
Signal to noise ratio (SNR) is one of the most
with reference signal, 3 bit SIPO (serial in parallel out)
fundamental metrics used in signal processing. It is
for detecting slope overload, 8 bit PIPO (parallel in
defined as the ratio of signal power to noise power
parallel out) for providing 1 clock cycle delay , overload
expressed in decibels (dB).
detect and level select algorithm is used for selecting the
variable step size. The present input compared with
previous level selected output in 8 bit comparator. The
comparator output is a digital encoded output which is 1
bit compressed output of 8 bit A to D input. This
encoded output is coming at every trailing edge or
falling edge of the CLOCK signal. Here in below figure
shows, each block is CLOCK dependent, so the data
rate of CVSD is defined by the CLOCK. So by varying
the CLOCK frequency we can vary the data rate.
Here,

X(n) = Samples of i/p signal

X^(n) = Samples of Reconstructed O/P signal

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 Conference on Research in Computational
Intelligence and Communication Networks.
[2] “Telemetry Standards, IRIG Standard 106-15 july
2015 Appendix-F”
[3] B.P. Lathi & Zing, Modern Digital & Analog
Communication System, Oxford University Press,
International Fourth edition 2010.
[4] MOTOROLA ANALOG IC DEVICE DATA
MC34115 Continuously Variable Slope Delta
Modulation
[5] MX.COM, Mixed Signal ICs Application
Continuously Variable Slope Delta Modulation:A
The SNR calculated at different data rates at different Tutorial.
frequencies. Here if we increase the data rate of the [6] Amrita Soni, Piyush Gupta, Digital Design and
CVSD system the signal to noise ratio is increases and if Simulation of CVSD Codec Algorithm using
we increase the sampling frequency of the input signal VHDL, International Journal of Research in
then comparison of the comparator is decreases so Engineering and Technology, IJRET Volume: 6,
signal quality at output of decoder is decreases so SNR Issue: 5, May-2017 eISSN: 2319-1163, pISSN:
is decreases. 2321-7308
[7] “Study of a Novel ADM Algorithm with Pre-
processing for Performance Improvement”B K
IV.CONCLUSION Sujatha1 , Dr. P S Satyanarayana2 , FIETE, Dr. K N
Haribhat3 1M S Ramaiah Institute of Technology,
The Digital design of CVSD codec algorithm is created using Bangalore 2 B M S College of Engineering.,
VHDL Codes. VHDL is commonly used to write text Bangalore 3Nagarjuna College of Engineering and
models that describe a logic level circuit. Here Various Technology, Bangalore
RTL Schematics of the Modules are designed in Xilinx.
In digital system design method, register-transfer- [8] “Implementation and performance of a delayed
level (RTL) schematic is a design perception, which continuously variable slope delta modulator”
models a synchronous digital circuit in terms of the flow 6.8.TOMBRAS and C.COURTI8 Inrtitutm of
of digital signals. CVSD soft core can be easily Informatics 8, Telecommunications. N.C.S.R.
implemented on any telemetry processor so that one can "Denokritos". GR-lS3 10 Athens. Grerce.
easily embedded digitized audio signal on a single
frame and send it to ground station.

CVSD can be used in tactical aircraft intercom system.

CVSD soft core has huge economical advantage for low
power audio signal processing.

CVSD is internationally acceptable algorithms for

digital transmission of audio signal. This soft core is
portable for defence system.

V. REFERENCES

[1] Hari Krishna Boyapati, Rajeev Kumar Elubudi,

Manoj Jain. “Efficient Implementation of Voice
Processing Module with CVSD Source Coding for
Tactical wireless system”.2015 IEEE International

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