Digital SIgnal Process.

SSUng
5.8
Data Bus

MemorY
Program Data Program Peripherals
ROM SARAM Serial Port 1
2K C50 9K
C50
8K C51 1K Data DARAM
C51
4K C52 Data Program
16K C53 3K B2(32 x 16) Serial Port 2
LC56 32K LC56 GK DARAM
C57S 2K C57S
LC57
6K
6K
BO(512 x 16)|| B1(512 x 16) TDM
LC57 32K
Serial Port
Buffered
Program Bus Serial Port

Timer

Program Host Port

Controller Interface
Program Memory-
Memory Control Counter Mapped CALU
Registers
Parallel Test Emulsion
Multiprocessing Status Control Logic
Registers Multiplier Unit
Intemupts |*Accumulator| | (PLU)
Hardware
Initialization Auxiliary ACC Buffer
Stack Register *Arithmetic
OscillatorTimer Address Arithmetic Logic
Unit Unit (ALU)
Generation Logi (ARAU)
Instruction Reg. CPU

Data BusS

Fig. 5.7: Architecture of TM$320C50

Parallel Logic Unit (PLU)
The CPU includes an separate PLU.It performs Boolean operations or the bit manipulations
required of high-speed controllers.The PLU can set, clear, test, or toggle bits in a status registet.
control register, or any data memory location.Results of a PLU function are written back to the

original data memory location.

Auxiliary Register Arithmetic Unit (ARAU)

The CPU includes an unsigned 16-bit arithmetic logic unit that calculates indirect addresses
by using inputs from the auxiliary registers (ARs), index register (INDX), and auxiliary regste
compare register (ARCR). The ARAU can autoindex the current AR while the data memuy
location is being addressed and can index either
by 1 or by the contents of the INDX.
Memory-Mapped Registers
The TMS320C50 has 96 registers mapped into page 0 of the data memory space. All Cx
 igital Signal Processors 5.9

DSPs have 28 CPU registers and put/output (1/0) port registers but have different numbers of
eripheral and reserved registers
peripheral h e memory-mapped registers are used for indirect data address
pointers,
ers, temi
mporary storage, CPU status and control, or integer arithmetic processing through the
ARAU.

Program Controller

The program controller contains logic circuitry that decodes the operational nstructions
managesthe Upipelime, stores the status of CPU operations, and decodes the conditional
mar

operations. The program controller consists of these élements:

ope

Program counter

Status and Control registers

.Hardware Stack
Address Generation logic
Instruction Register
On-Chip Memory
The C5x architecture contains a considerable amount of on-chip memory to aid in syster

performance and integration:

Program Read-Only Memory (ROM)

RAM (DARAM)
Data/Program Dual-Access
Data/Program Single-Access RAM (SARAM)
The memory space is divid
The 'C5x has atotal address range of 224K words X16 bits.
selectable segments: 64K-word program memory space, 64K-we
four individually memory
into and 32K-word global data memory spa
local data memory space, 64K-word input/output ports,

Program ROM
maskable programmable ROM.
All CSx DSPs carry a 16-bit on-chip
Dota/Program Dual-Access RAM
on-chip dual-access RAM (DARAM).
All 'C5x DSPs carry a
1056-word X16-bit
selectable menmory blocks:
DARAM is divided into three individually
DARAM block BO, 512-word data DARAM block B1, anc
512-word data or program
The DARAM is primarily intended to store data values but,
word data DARAM block B2.
as well. DARAM blocks
Bl and B2 are always config
ceded, can be used to store programs
as data memory.
5.10
Digital Signal Procesgsi
Data/Program Single-Access RAM
All CS DSPs except the 'C52 carry a 16-bit on-chip single-access RAM (SARAM

be config1red by software in one of three ways:

various sizes. The SARAM can

All SARAM configured as data memory

A l l SARAM configured as program memory

SARAM configured as both data memory and program memory

The SARAM is divided into 1K- and/or 2K-word blocks contiguous in address memoe
oy
space.SARAM supports more flexible address mapping than DARAM because SARAM Can
he
mapped to both program and data memory space simultaneously.
On-Chip Memory Protection
The 'CSx DSPs have a maskable option that protects the contents of on-chip memories

When the related bit is set, no externally originating instruction can access the on-chip memor

spaces
On-Chip Peripherals
All 'CSx DSPs have the same CPU structure; however, they have ditferent onchip peripherals
connected to their CPUs. The 'C5x DSP on-chip peripherals available are:

Clock Generator
Hardware Timer
Software-Programmable Wait-State Generators

Parallel /O ports
Host Port Interface (HPI)

Serial Port
.Buffered Serial Port (BSP)
.Time-Division Multiplexed (TDM) Serial Port
.User-maskable interrupts
Clock Generator
The clock generator consists of an internal oscillator and a phase-locked loop (PLL) circuit
The clock generator can be driven internally by a crystal resonator circuit or driven externaly by a

clock source. The PLL circuit generate internal CPU clock by multiplying the clock source
can an
PU.
by a specific factor, so you can use a clock source with a lower frequeney than that of theCPU
Hardware Timer
A 16-bit hardware timer with a 4-bit prescaler is available. This programmable timer
a rate that is between 1/2 and 1/32 of the machine cycle rate (CLKOUT), depending upon tne
clocksa
Digital Signal Processors
5.11
timer's divi ide-down ratio. The timer can
be
bits. stopped, restartarted, reset, or disabled by specific status
Goftware-Programmable Wait-State Generators
Software-programmable wait-state logic is incorporated in
oeneration without any external hardware
for
'C5x DSPs allowing wait-state
devices. This feature consists of interfacing with slower off-chip memory and
multiple waitstate
anngrammable to operate in different wait states for generating circuits. Each circuit 1s user
off-chip memory accesses.
Parallel 1/O Ports
A total of 64K 1/0
ports are
available, sixteen of these ports are
memory space. Each of the l/O
ports can be addressed
memory-mapped
in data

by the IN or the OUT instruction. The

memory-mapped /O ports can be
accessed with any instruction that reads from or writes to data
memory. The IS signal indicates a read or write operation
through
an I/O
port.
Host Port Interface (HPI)
The HPI available on the 'C57S and 'LC57 is 8-bit
an
parallel
VO port that provides an
interface to a host processor. Information is exchanged between the DSP and the host processor
through on-chip memory that is accessible to both the host processor and the C57.
Serial Port

Three different kinds of serial ports are available: a general-purpose serial port, a time-division
multiplexed (TDM) serial port, and a buffered serial port (BSP). Each C5x contains at least one
general-purpose, high-speed synchronous, full-duplexed serial port interface that provides direct
communication with serial devices such as codecs, serial analog-to-digital (A/D) converters, and
other serial systems. The serial port is capable of operating at up to onefourth the machine eyele

rate (CLKOUTI).
Buffered Serial Port (BSP)
buffered serial
The BSP available the 'C56 and 'C57 devices is a full-duplexed, double
on
on the data stream length.
The
port and an autobuffering unit (ABU). The BSP provides flexibility
latencies.
ABU supports high-speed data transfer and reduces interrupt

TDM Serial Port

'C53 devices is a ful-duplexed
serial
available on the 'C50, 'C51, and
The TDM serial port or for time-division
either for synchronous operations
port that can be configured by software
applications.
serial port is commonly used multiprocessor
in
utiplexed operations. The TDM

User-Maskable Interrupts
a timer interrupt and
five internal interrupts,
interrupt lines (INTI-INT4) and
four external routine (1SR) is executed,
user maskable.
When an interrupt service
ur serial port interrupts, are
 Digital Signal Proc
5.12
8-level hardware stack, and the
Processin
con
the contents of the program counter are saved on an

saved (shadowed) on a
ontents
l-level-deep stacl.k
eleven specific CPU registers are automatically
ADDRESSING MODESs
The different addressing modes of TMS320C 50 are:
Direct Addressing
Indirect Addressing
Immediate Addressing

Dedicated-Register Addressing
Memory-Mapped Register Addressing
Circular Addressing
Direct Addressing
In the direct memory addressing mode, the instruction contains the lower 7 bits of the data
memory address (dma). The 7-bit dma is concatenated with the 9 bits of the data memory Dage
pointer (DP) in status register 0 to form the full 16-bit data memory address. This 16-bit data
memory address is placed on an internal direct data memory address bus (DAB). The DP points to
one of S12 possible data memory pages and the 7-bit address in the instruction points to one of 128
words within that data memory page.

Indirect Addressing
Eight 16-bit auxiliary registers (AR0-AR7) provide flexible and powerful indirect addressing
In indirect addressing, any location in the 64K-word data
memory space can be accessed using a
16-bitaddress contained in an AR.To select a specific AR, load the
auxiliary register pointer (ARP
with a value from 0 through 7,
designating AR0 through AR7, respectively. The register pointed
to
by the ARP is referred to as the current auxiliary register (current AR).

Indirect Addressing Options

The 'CSx provides four indirect addressing options:
No increment or decrement.The instruction uses the content of the current AR as the dala
memory address, but neither increments nor decrements the content of the current AR.
Increment or decrement by one. The instruction uses the content of the current AR as tne
data memory address and then increments or decrements the content of the current AR DY
Increment or decrement by an index amount. The
value in INDX is the index amount
The instruction uses the content of the current AR as
the data memory address and tnc
increments or decrements the content of the current
AR by the index amount.
 fncrement or Decrement by an index amount using reverse carny

The value in INDX is the index amount. The instruction uses the content of the curent AR as
address and then increments or decrements the content of the current AR by the
the data memory
nfey amount. The addition or subtraction is done using reverse carry
propagatio
Indirect Addressing Opcode Format
Indirect addressing can be used with all instructions except those with immediate operands or

with no operands.

Bit-Reversed Addressing
In the bit-reversed addressing mode. INDX specifies one-half the size of the FFT. The value
2n. An
sontained in the current AR must be equal to 2n-1, where n is an integer, and the FFT size is
auxiliary register points to the physical location of a data value. When you add INDX to the
current

AR using bitreversed addressing. addresses are generated in a bit-reversed fashion.

Immediate Addressing
In immediate addressing, the instruction word(s) contains the value of the immediate operand.
The 'C5x has both 1-word (8-bit, 9-bit, and 13-bit constant) short immediate instructions and 2

word (i6-bit constant) long immediate instructions.

Short Immediate Addressing
contained within the instruction machine code
In short immediate instructions, the operand is

Long Immediate Addressing

word of a two-word
In longimmediate instructions. the operand is contained in the second
modes:
instruction. There are two long immediate addressing

One-operand instructions
Two-operand instructions
Dedicated-Register Addressing
mode,
modSe operates like the long immediate addressing
The dedicated-registered addressing in the
from of
onetwo special-purpose memory-mapped registers
except that the address comes
and the dynamic bit manipulation register (DBMR).
CPU: the block move address register (BMAR)
block of memory to be acted upon
mode is that the address otfthe
he advantage of this addressing
can be changed during execution of the program.

Memory-Mapped Register Addressing

can modify the memory mapped
registers
With memory-mapped register addressing, you scratch pad
value. In addition, you can modity any
wIthout affecting the current data page pointer
register addressing mode
0. The memory-mapped
KAM (DARAM B2) location or data page
 Digital Signal Processing
5.14
are forced to 0
that the 9 MSBs of the address
operates like the direct addressing mode, except
to address the memory.
instead of being loaded with the contents of the DP. This allows you
the DP or auxiliary
mapped registers of data page 0 directly without the overhead of changing
register.
The following instructions operate in the memory-mapped register addressing mode. Using

these instructions does not affect the contents of the DP:

LAMM-Load accumulator with memory-mapped register

LMMR Load memory-mapped register
SAMM-Store accumulator in memory-mapped register
SMMR-Store memory-mapped register
Circular Addressing
Many algorithms such convolution, correlation, and finite impulse response (FIR) filters
as

can use circular buffers in memory to implement a

sliding window, which contains the most recent
data to be processed. The 'C5x
supports two concurrent circular buffers operating via the ARs.
The following five
memory-mapped registers control the circular buffer operation:
CBSRI-Circular buffer 1 start register
CBSR2-Circular buffer 2 start register
CBER1- Circular buffer 1 end register
CBER2-Circular buffer 2 end register
CBCR-Circular buffer control register
Circular buffers can be used in increment-
Instruction Set
or
decrement-type updates
n +h:
 TULEsSing
ata bus 15 TMS320C5x ROUD Extemal
DMA
interface
Address bus A(15 0) FHOUDA
RD WE NMI4 Extemal
interrupt
INT(14) 4 interfac
Systern interfaca/
MPAMO Control signals
Atemy Contro Extemal
sipnals EO ffags
BR
TOUT Timer output
RAW
STRB RS Raset

READY
DR, DR(1-2)
CLKIN2 DX, DX(12)
CLKR, CLKR(1-2)
Serial
XCLKIN CLKX,CLKX(1-2) port
interface
CLKOUT1 FSR, FSR(1-2)

CLK MD 1-3) FSX, FSX(1-2)

BDR TDR

BDX TDX

Bufered BCLKR TCLKA

seria TDM
pon BCLKX TCLKX serial por
interface
BFSR TFSR/TADD

BFSX TFSR/TFRM

VpOA TDI
Vp0D TDO

VoOC TMS

Supply Vpo TCK Emulation

JTAG intertace
VssA TRST
ssD EMUO
Vssc
EMU1OFF

Fig 11.8: Functional grouping of TMS320C 5x pins (100 pin TQFP)

able 11.5:Pin
Description of TMS320C5x (100 pin TQFP)
stGNAL TYPE DESCRIPTION

PARALLEL INTERFACE BUS

A9Ai5 10, Tnstate 16-bit external address bus

D!5 O, Tistale T6-bit exiernal datä bus

PS, IDS, 1S Ouiput, Tristale Program, data and ) space select oulputs, respectively
STRB O, Tristale Timing strobe for external cycles and external DMA
R/W IO, Tistale Read/wiile select for extemal cycles and external iDMA

RD, WE Output, Iristate Read and write strobes, respectively, for extemal
cycles
Chapter 1l -DigitalSignal
Processors
11. 12
Table 11.5:Continued...

SIGNAL
TYPE
DESCRIPTION
READY Input External bus ready/wait-state control input
10. Tristate Bus request
BR

SYSTEM INTERFACE/CONTROL SIGNALS

RS
Input Reset

MP MC Input Microprocessor/microcomputer mode select

HOLD
Input Put parallel F bus in high-impedance state after current cycie

HOLDA
Output, Tristate Hold acknowledge

XF Output, Tristate External flag output

BIO Input 10 branch control input

TOUT Output, Tristate Timer output signal

Input External interrupt inputs

INTI- INT4
Nonmaskable external interrupt
Tnput
NMI
SERIAL PORT INTERFACE

Serial receive-data input

DR, DRI1, DR2 Input
Serial transmit-data output
DX, DX1, DX2 Output, Tristate
Serial receive-data clock input
CLKR, CLKRI, CLKR2| Input
Serial transmit-data clock
Tristate
CLKX, CLKX1, CLKX2 10, Serial receive-frame-synchronization input
FSR, FSR1, FSR2 Input Serial transmit-frame-synchronization signal
FSX, FSX1, FSX2 IO, Tristate
BUFFERED SERIAL PORT (BSP)

BSP receive-data input

BDR Input
BSP transmit-data output
Output, Tristate
BDX BSP receive-data clock input
Input
BCLKR BSP transmit-data clock
IO, Tristate
BCLKX frame-synchronization input
BSP receive
Input signal
BFSR frame-synchronization
BSP transmit
10, Tristate
BFSX PORT INTEREACE
TDM SERIAL

TDM serial receive-data input

Input
TDR transmit-data output
Output, Tristate TDM serial
TDX clock input
TDM serial receive-data
TCLKR Input
transmit-data clock
TDM serial
IO, Tristate
TCLKX receive-frame-synchronization
input
TDM serial
10, Tristate signal
TFSR/TADD t r a n s m i t - f r a m e - s y n c h r o n i z a t i o n

TDM serial
TFSX/TFRM Input
 Digilal S1gnal Processing
11. 13

Table 11.5: Continucd...

DESCRIPTION

TYPE
SIGNAL EMULATION/JTAG INTERFACE

JTAG-test-port scan data input

TDI Input
scan data output
Output, Tristate JTAG-test-port
TDO
select input
JTAG-test-port mode
TMS Input
JTAG-port clock input
TCK Tnput
JTAG-port reset (with pull-down resistor)
TRST
Input
I0, Tristate
Emulation control0
EMUO
Emulation control
I0, Tristate
EMU1/OFF
GENERATION AND CONTROL
CLOCK

Oscillator output
X1 Output
Clock/oscillator input
X2/CLKIN, CLKIN2 Input
Clock-mode select inputs
CLKMD1, CLKMD2 Input
Output, Tristate
Device system-clock output
CLKOUTI1
POWER SUPPLY CONNECTIONS

address-bus output
Supply Supply connection,
VDDA
Supply connection,
data-bus output
VDDD Supply
control output
Supply Supply connection,
VDDC
Supply connection, internal logic
VDDI Supply
address-bus output
Supply Supply connection,
VSSA
data-bus output
Supply Supply connection,
VSSD

Supply Supply connection, control output

VSSC
Supply connection, internal logic
VSSI Supply
Table 11.6: Device-Specific Pinouts for the 100 pin TQFP

TM$320C52 TMS320c53S
TMS320Ccs1
PIN TMS320Lcs2 TM$320LC53S TM$320Lc56
TMS320LCS1
CLKX2 BCLKX
TCLKX
CLKX CLKXI CLKX
CLKX
FSR2 BFSR
TFSRSTADD
TCLKR CLKR2 BCLKR
SS
DR DR DRI DR
46
DR2 BDR
47 TDR
48 FSR FSR FSRI FSR
CLKR CLKRI CLKR
49 CLKR
Chapter
11 -

Digial >ignal Proccssors 11. 14

Table 11.6: Continued...

TMS320C51 TMS320C52 TMS320C53S

PIN
TMS320LC51 TMS320LC52 TMS320LC53S TMS320LC56

83 CLKIN2 CLKIN2 CLKIN2 CLKMD3

91 FSX FSX FSXI FSX

92 TFSX/TFRM FSX2 BFSX

93 DX DX DX1 DX

94 TDX NC DX2 BDX