Physical Design – Floor Planning

Floor Planning
Floor-plan design is an important step in physical design of VLSI circuits to plan the positions of
a set of circuit modules on a chip in order to optimize the circuit performance. Floor planning is
the process of creating an area for macros and standard cells to be placed

Floor Planning Steps :

1. Decide core width and height for die size estimation.
2. Placement of IO pads/Ports .
3. Creating Voltage area.
4. Placement of macros.
5. Adding physical only cells
6. Power planning (pre routing)

1) Decide core width and height for die size estimation.

Core area depends upon :

1. Aspect ratio: Aspect ratio will decide the size and shape of the chip. ratio of height
and width of core.
Aspect ratio = width/height

2. Core utilization: - Utilization will define the area occupied by the standard cells,
macros, and other cells. If core utilization is 0.8 (80%) that means 80% of the core
area is used for placing the standard cells, macros, and other cells, and the remaining
20% is used for routing purposes.

core utilization = (macros area + std cell area )/ total core area
 Physical Design – Floor Planning

2) I/O Pad placement:

In ASIC design three types of IO Pads. Generally, pad placement and pin placement is
done by Top-Level people.

3) Voltage area Creation :

Multi voltage design is used to have trade-off between power consumption and
performance
In multi-voltage design different blocks operate with different voltages. We use level-
shifters when signals crossing one power domain to another.

Fig : Different power domain with level shifters

4) Macro Placement:
Macros may be memories, analog blocks. Proper placement of macros has a great impact
on the quality and performance of the ASIC design. Macro placement can be manual or
automatic. Generally manual macro placement is Preferred

Note :
Types of macros:
 Hard macros: The circuit is fixed. We can’t see the functionality
information about macros. Only we know the timing information.
 Soft macros: The circuit is not fixed and we can see the functionality and
which type of gates are using inside it. Also we know the timing information.
 Physical Design – Floor Planning

Guidelines to place macros:

1) Placement of macros are the based on the fly-lines (Fly-lines shows the connectivity b/w
macro to macro and macro to pins) so we can minimize the interconnect length between IO
pins and other cells.

2) Place the macros around to the boundary of the core, leaving some space between macro to
core edge so that during optimization this space will be used for buffer/inverter insertion

3) Place the macros of same hierarchy together.

 Physical Design – Floor Planning

4) Keep the sufficient channel between macros

channel width = (number of pins*pitch )/ number of layers either horizontal
or vertical
Eg. Let’s assume If there are two macros having 50 pins and the pitch values are 0.6 and
the total number of horizontal and vertical layers are 12. Means M0 M2 M4 M6 M8 M10
are horizontal layers and M1 M3 M5 M7 M9 M11are vertical layers.
Channel width = ((50+50)*0.6)/6 = 10

5) Avoid crisscross connection of macro placement.

6) Keep keep-out margin/Halo around the four sides of macros so no standard cells will not sit
near to Macro pins. This technique avoids the congestion.
 Physical Design – Floor Planning

7) Use Placement Blockages near macros to avoid congestion

Note : Blockages: Blockages are the specific location where the placing of cells is blocked.
If the macros moved from one place to another place, blockages will not move.

Blockages are of three types. a) Soft b) Hard c) Partial

a) Soft blockages:
 prevents from the placement of std cell and hard macro within the specified area
during coarse placement but allows placement of buffer/inv during optimization,
legalization and clock tree synthesis.
b) Hard blockages:
 No standard cells, macros and buffer/inv can be placed within the specified area
during coarse placement, optimization, and legalization.
 Used to avoid routing congestion at macros corners.
c) Partial blockages:
 Partial blockages limit the cell density in the specified area.
 Ex: If partial blockage is 40 % , Then in that area the cell density is 60%
(blocked % is 40)
 To allow unlimited usage of a partial blockage area specify a blockage percentage
to zero.
 Physical Design – Floor Planning

5) The standard cell rows created for standard cell placement.

 The area allotted for the standard cells on the core is divided into rows where standard
cells are placed.
 The height of the row is equal to the height of the standard cell and width varies. The height
varies according to multiple standard cell row height. there may be double-height cells,
triple-height cells, etc.
 The standard cells will sit in the row with proper orientation.
 The rows at the macro placement should be removed.

6) Physical-Only Cells :

a) Tap cells:
 A tap cell is a special nonlogic cell with a well tie, substrate tie, or both to avoid
latch-up Problem.
 Tap cells are placed in the regular intervals in standard cell row and distance
between two tap cells given in the design rule manual.
 Generally, the design rules specify the maximum distance allowed between every
transistor in a standard cell and a well or substrate tap.
 Before global placement (during the floorplanning stage), you can insert tap cells
in the block to form a two-dimensional array structure to ensure that all standard
 Physical Design – Floor Planning

cells placed subsequently comply with the maximum diffusion-to-tap distance

limit.

b) Tie –Cells
 These are special-purpose cells whose output is constant high or low.
 The input needs to be connected to the gate of the transistor and there are only two
types of input logic 1 and logic 0, but we do not connect them directly to gate of
the transistor as with supply glitches can damage the transistor so we used tie high
and tie low cells (these are nothing but resistors to make sure that PG network
connected through them ) and output of these cell are connected to the gate of the
transistor.
 Tie Cells are inserted during placement stage
c) Filler Cells
 To have n-well and Substrate continuity we Use filler cells
 If there is continuity b/w nwell and implant layer it is easier for foundry people to
generate them and the creation of a mask is a very costly process so it is better to
use only a single mask.
 If nwell is discontinuous the DRC rule will tell that place cells further apart i.e
maintain the minimum spacing because there is a well proximity effect.
 After routing and after timing sign-off we add Filler cells.

d) Decap Cells
 If standard cells and macros are not getting sufficient power due to IR-drom They
may go to metastable state.
 Decap filler cells are small capacitors which are placed between VDD and GND
all over the layout when the logic circuit draw a high amount of current, this
capacitor provides extra charge to that circuit. when logic circuit not drawing any
current, the de-cap is charged up to maximum capacitance.

e) Endcap Cells
 Before placing the standard cells, we can add boundary cells to the block. Boundary
cells consist of end-cap cells, which are added to the ends of the cell rows and
around the boundaries of objects such as the core area, hard macros, blockages, and
voltage areas, and corner cells
 End-cap Cells are used to protect the gate of a standard cell placed near the
boundary from damage during manufacturing and to avoid the base layer DRC
(Nwell and Implant layer) at the boundary.
 Physical Design – Floor Planning

7) Power planning (pre routing):

 Rings: It Carries VDD and VSS around the chip

 Stripes: It Carries VDD and VSS from Rings across the chip
 Rails: It connects VDD and VSS to the standard cell VDD and VSS.
 Trunk: The connection between Pad and Ring
 Pad: Interface from IC to the outside world.