Introduction to Semiconductor

Manufacturing Technology

Chapter 1, Introduction
Hong Xiao, Ph. D.
[email protected]
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 1
 Objective
After taking this course, you will able to

• Use common semiconductor terminology

• Describe a basic IC fabrication sequence
• Briefly explain each process step
• Relate your job or products to semiconductor
manufacturing process
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 2
 Topics

• Introduction
• IC Device and Design
• Semiconductor Manufacturing Processes
• Future Trends

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 3

 Introduction

• First Transistor, AT&T Bell Labs, 1947

• First Single Crystal Germanium, 1952
• First Single Crystal Silicon, 1954
• First IC device, TI, 1958
• First IC product, Fairchild Camera, 1961

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 4

 First Transistor, Bell Lab, 1947

Photo courtesy:
AT&T Archive

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 5

 First Transistor and Its Inventors

John Bardeen, William Shockley and Walter Brattain

Photo courtesy: Lucent Technologies Inc.
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 6
First IC Device Made by Jack Kilby
of Texas Instrument in 1958

Photo courtesy: Texas Instruments

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 7

First Silicon IC Chip Made by Robert
Noyce of Fairchild Camera in 1961

Photo courtesy: Fairchild Semiconductor International

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 8
 Moore’s Law
• Intel co-founder Gorden Moore notice in 1964
• Number of transistors doubled ever 12 months
while price keeping unchanged
• Slowed down in the 1980s to every 18 months
• Amazingly still correct, likely to keep until
2010.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 9

 Moore’s Law, Intel’s Version
Transistors
Pentium III

10M
80486
Pentium
1M
80386
100K 8086 80286

10K 4040 8080

1K
1975 1980 1985 1990 1995 2000

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 10

 IC Scales
Integration level Abbreviation Number of devices on a chip

Small Scale Integration SSI 2 to 50

Medium Scale Integration MSI 50 to 5,000
Large Scale Integration LSI 5,000 to 100,000
Very Large Scale Integration VLSI 100,000 to 10,000,000
Ultra Large Scale Integration ULSI 10,000,000 to 1,000,000,000
Super Large Scale Integration SLSI over 1,000,000,000

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 11

 Road Map Semiconductor Industry
1995 1997 1999 2001 2004 2007
Minimum feature size (µm) 0.35 0.25 0.18 0.13 0.10 0.07
DRAM
Bits/chip 64 M 256 M 1G 4G 16 G 64 G
Cost/bits @ volume
(millicents) 0.017 0.007 0.003 0.001 0.0005 0.0002
Microprocessor
Transistors/cm2 4M 7M 13 M 25 M 50 M 90 M
Cost/Transistor @ volume
(millicents) 1 0.5 0.2 0.1 0.05 0.02
ASIC
Transistors/cm2 2M 4M 7M 13 M 25 M 40 M
Cost/Transistor @ volume
(millicents) 0.3 0.1 0.05 0.03 0.02 0.01
Wafer size (mm) 200 200 200 - 300 300 300 –
300 400 (?)

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 12

 Feature Size and Wafer Size
Chip
or die
Chip made with 0.35 µm
technology 300 mm
with 0.25 µm
technology
200 mm
with 0.18 µm
technology
150 mm

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 13

 Smallest Known Transistor Made
by NEC in 1997
Upper gate
Lower gate
Dielectric
Source Drain

n+ n+

Ultra shallow junctions

P-type substrate

0.014 micron lower gate width Photo courtesy: NEC Corporation

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 14

 Limit of the IC Geometry
Size of the atom

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 15

 Limit of the IC device
• Atom size: several Å
• Need some atoms to form a device
• Likely the final limit is around 100 Å or
0.01 micron.
• About 30 silicon atoms

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 16

 IC Design: First IC

Photo courtesy: Texas Instruments

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 17

 V in

IC Design:
V dd
(a)
CMOS Inverter
NMOS PMOS
V ss
V out

Shallow trench isolation (STI)

N-channel active region P-channel active region
•N-channel Vt •P-channel Vt
•N-channel LDD •P-channel LDD
•N-channel S/D •P-channel S/D

(b)
P-well
Metal 1 Polycide gate and local N-well
interconnection Contact
Metal 1, AlCu

W
PMD

n+ n+ STI p+ p+
P-Well
P-Epi
N-Well
(c)
P-Wafer

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 18

 IC Design: Layout and Masks of CMOS Inverter

CMOS inverter layout Mask 1, N-well Mask 2, P-well

Mask 3, shallow trench isolation Mask 4, 7, 9, N-Vt, LDD, S/D Mask 5, 8, 10, P-Vt, LDD, S/D

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 19

Mask 6, gate/local interconnection Mask 11, contact Mask 12, metal 1
 Mask/Reticle

Pellicle Chrome pattern Phase shift coating

Quartz substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 20

 A Mast and a Reticle

Photo courtesy: SGS Thompson

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 21

 Wafer Process Flow
Materials IC Fab

Dielectric Test
Metallization CMP
deposition
Wafers

Thermal Etch Packaging

Implant
Processes PR strip PR strip
Masks

Photo- Final Test

lithography

Design

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 22

 Chapter 2
Introduction of IC
Fabrication
Hong Xiao, Ph. D.
[email protected]

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 1

 Objectives
• Define yield and explain its importance
• Describe the basic structure of a cleanroom.
• Explain the importance of cleanroom protocols
• List four basic operations of IC processing
• Name at least six process bays in an IC fab
• Explain the purposes of chip packaging
• Describe the standard wire bonding and flip-chip
bump bonding processes
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 2
 Wafer Process Flow
Materials IC Fab

Dielectric Test
Metallization CMP
deposition
Wafers

Thermal Etch Packaging

Implant
Processes PR strip PR strip
Masks

Photo- Final Test

lithography

Design

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 3

 Fab Cost
• Fab cost is very high, > $1B for 8” fab
• Clean room
• Equipment, >$1M per tool
• Materials, high purity, ultra high purity
• Facilities
• People, training and pay

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 4

 Wafer Yield

Wafers good
YW =
Waferstotal

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 5

 Die Yield

Dies
YD =
good

Dies total

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 6

 Packaging Yield

Chips good
YC =
Chipstotal

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 7

 Overall Yield

YT = YW×YD×YC

Overall Yield determines whether a fab is

making profit or losing money

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 8

 How Does Fab Make Money
• Cost:
– Wafer (8”): ~$150/wafer*
– Processing: ~$200 (1$/wafer, 200 process steps)
– Packing: ~$1/chip
• Sale:
– ~100 chips/wafer
– ~$50/chip (low-end microprocessor in 2000)
*Cost of wafer and price of chip are changing daily, numbers
are choosing randomly based on general information.
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 9
How Does a Fab Make (Loss) Money
• 100% yield: 150+200+100 = $450/wafer
Cost: • 50% yield: 150+200+50 = $400/wafer
• 0% yield: 150+200 = $350/wafer
• 100% yield: 100××50 = $5,000/wafer
Sale: • 50% yield: 50×50 = $2,500/wafer
• 0% yield: 0×50 = $0.00/wafer
• 100% yield: 5000 - 450 = $4550/wafer
Profit
• 50% yield : 2500 - 400 = $2100/wafer
Margin:
• 0% yield : 0 - 350 = − $350/wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 10
 Throughput
• Number of wafers able to process
– Fab: wafers/month (typically 10,000)
– Tool: wafers/hour (typically 60)
• At high yield, high throughput brought

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 11

 Defects and Yield

1
Y∝
(1 + DA) n

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 12

 Yield and Die Size
Killer Defects

Y = 28/32 = 87.5% Y = 2/6 = 33.3%

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 13

Illustration of a Production Wafer

Die

Test die

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 14

Illustration of a Production Wafer
Scribe Lines
Test
Structures

Dies

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 15

 Clean Room
• Particles kills yield
• IC fabrication must in a clean room

• Artificial environment with low particle counts

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 16

 Clean Room
• First used for surgery room to avoid bacteria
contamination
• Adopted in semiconductor industry in 1950
• Smaller device needs higher grade clean room
• Less particle, more expensive to build

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 17

 Clean Room Class
• Class 10 is defined as less than 10 particles
with diameter larger than 0.5 µm per cubic
foot.
• Class 1 is defined as less than 1 such particles
per cubic foot.
• 0.18 mm device require higher than Class 1
grade clean room.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 18

 Cleanroom Classes
100000

10000 Cl
as
s1
00
Cl ,0
# of particles / ft3

1000 as 00
s1
0,
Cl 00
100 Cl as 0
Cl as s1
as s1 ,0
s1 00 00
10 Cl 0
as
s1
Cl
1 as
sM
-1
0.1
0.1 1.0 10
Particle size in micron
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 19
 Definition of Airborne Particulate
Cleanliness Class per Fed. Std. 209E
Particles/ft3
Class
0.1 µm 0.2 µm 0.3 µm 0.5 µm 5 µm

M-1 9.8 2.12 0.865 0.28

1 35 7.5 3 1

10 350 75 30 10

100 750 300 100

1000 1000 7

10000 10000 70

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 20

 Effect of Particles on Masks

Particles
on Mask

Stump Hole on
on +PR −PR
Film Film

Substrate Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 21

 Effect of Particle Contamination
Ion Beam
Dopant in PR
Particle

Photoresist

Screen Oxide
Partially Implanted Junctions

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 22

 Cleanroom Structure
Makeup Air Makeup Air
Fans

Equipment Area HEPA Filter Equipment Area

Class 1000 Class 1000
Process Process
Process Area
Tool Tool

Return Air Raised Floor Pump, RF

with Grid Panels and etc.
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 23
 Gowning Area
Shelf of Gloves, Hair
and Shoe Covers Gown Racks Disposal Bins

Entrance Shelf of
Gloves
To
Cleanroom
Wash/Clean
Stations
Shelf of
Gloves
Storage

Benches
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 24
 IC Fabrication Process Module
Thin film growth,
dep. and/or CMP

Photolithography

Etching Ion Implantation

PR Stripping PR Stripping

RTA or Diffusion

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 25

 Illustration of Fab Floor
Equipment Areas Process Bays

Corridor

Service Area

Sliding Doors Gowning Area

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 Wet Processes

Etch, PR strip, or clean Rinse Dry

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 Horizontal Furnace
Wafers
Heating Coils

Quartz
Tube
Gas flow

Temperature Center Zone

Flat Zone

Distance
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 28
 Vertical Furnace
Process
Chamber
Heaters

Wafers

Tower

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 29

 Schematic of a Track Stepper
Integrated System
Prep
Chamber Spin Coater Chill Plates
Wafer

Stepper

Wafer
Chill Plates Hot Plates
Developer Movement
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 30
 Cluster Tool with Etch and Strip
Chambers
PR Strip PR Strip
Chamber Chamber

Etch Etch
Chamber Chamber

Transfer
Robot
Chamber

Loading Station Unloading Station

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 31
Cluster Tool with Dielectric CVD
and Etchback Chambers
O3-TOES Ar Sputtering
Chamber Chamber

PECVD
Chamber

Transfer
Robot
Chamber

Loading Station Unloading Station

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 32
Cluster Tool with PVD Chambers
Al⋅Cu Al⋅Cu
Chamber Chamber

Ti/TiN Ti/TiN
Chamber Chamber

Transfer
Robot
Chamber

Loading Station Unloading Station

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 33
 Dry-in Dry-out CMP System

Wafer Loading Polishing

and Standby Pad

Post-CMP Clean Polishing

Heads
Rinse
Multi-head Polisher
Dryer and Wafer
Unloading
Clean Station
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 34
Process Bay and Equipment Areas
Sliding Doors Process Tools

Tables For PC and

Metrology Tools
Equipment Area

Equipment Area
Process Area

Service Area
Wafer Loading Doors
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 35
 Test Results

Failed die

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 36

 Chip-Bond Structure

Microelectronics Devices and Circuits

Chip Backside Chip (Silicon)

Metallization
Melt and
Solder Condense
Substrate
Metallization Substrate (Metal or Ceramic)

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 37

 Wire Bonding
Metal Wire Wire Clamp

Bonding Pad Bonding Pad Bonding Pad

Formation of Press to make Head retreat

molten metal ball contact
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 38
 Wire Bonding

Bonding Pad Lead Bonding Pad Lead

Lead contact with Clamp closed with heat

pressure and heat on to break the wire

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 39

 IC Chip with Bonding Pads
Bonding Pads

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 40

 IC Chip Packaging
Chip
Bonding
Pad

Pins

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 41

 Chip with Bumps

Bumps

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 42

 Flip Chip Packaging
Bumps

Chip

Socket Pins
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 43
 Bump Contact

Bumps
Chip

Socket Pins
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 44
 Heating and Bumps Melt

Bumps
Chip

Socket Pins
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 45
 Flip Chip Packaging

Chip

Socket Pins
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 46
Molding Cavity for Plastic Packaging
Top Chase Molding Cavity

Bonding Wires IC Chip

Lead Frame
Chip Bond Metallization
Pins

Bottom Chase

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 47

 Ceramic Seal

Bonding Wires IC Chip

Ceramic Cap
Cap Seal
Metallization Layer 2 Layer 2

Lead Frame, Layer 1

Pins

Chip Bond Metallization

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 48
 Summary
• Overall yield
• Yield determines losing money or making
profit
• Cleanroom and cleanroom protocols
• Process bays
• Process, equipment, and facility areas
• Die test, wafer thinning, die separation, chip
packaging, and final test
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 49
 Chapter 3
Basics Semiconductor
Devices and Processing
Hong Xiao, Ph. D.
www2.austin.cc.tx.us/HongXiao/Book.htm

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 1

 Objectives
• Identify at least two semiconductor materials from
the periodic table of elements
• List n-type and p-type dopants
• Describe a diode and a MOS transistor
• List three kinds of chips made in the
semiconductor industry
• List at least four basic processes required for a
chip manufacturing

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 2

 Topics

• What is semiconductor
• Basic semiconductor devices
• Basics of IC processing

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 3

 What is Semiconductor
• Conductivity between conductor and insulator
• Conductivity can be controlled by dopant
• Silicon and germanium
• Compound semiconductors
– SiGe, SiC
– GaAs, InP, etc.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 4

 Periodic Table
of the Elements

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 5

Semiconductor Substrate and Dopants
Substrate

P-type
Dopant

N-type Dopants
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 6
 Orbital and Energy Band
Structure of an Atom
Valence shells
Conducting band, Ec

Nuclei Band gap, Eg

Valence band, Ev

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 Band Gap and Resistivity

Eg = 1.1 eV Eg = 8 eV

Aluminum Sodium Silicon Silicon dioxide

2.7 µΩ•cm 4.7 µΩ•cm ~ 1010 µΩ•cm > 1020 µΩ•cm

Conductors Semiconductor Insulator

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 8
 Crystal Structure of Single
Crystal Silicon
Shared electrons

Si
Si Si Si
Si

Si
Si Si Si

Si

Si Si
Si - Si

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 Why Silicon
• Abundant, inexpensive
• Thermal stability
• Silicon dioxide is a strong dielectric and
relatively easy to form
• Silicon dioxide can be used as diffusion
doping mask

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 N-type (Arsenic) Doped Silicon
and Its Donor Energy Band
Conducting band, Ec
Si Si Si
Extra
Ed ~ 0.05 eV
Electron
Si As Si Eg = 1.1 eV

Si Si - Si
Valence band, Ev

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 11

 P-type (Boron) Doped Silicon
and Its Donor Energy Band
Conducting band,
Si Ec
Si Si
Hole
Eg = 1.1 eV
Si B Si

Ea ~ 0.05 eV
Si Si - Si
Valence band, Ev
Electron

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 12

 Illustration of Hole Movement

Conducting band, Ec Conducting band, Ec Conducting band, Ec

Electron Eg = 1.1 eV Electron Eg = 1.1 eV Electron Eg = 1.1 eV

Ea ~ 0.05 eV

Valence band, Ev Valence band, Ev Valence band, Ev Hole

Hole Hole

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 13

Dopant Concentration and Resistivity

Resistivity

P-type, Boron

N-type,
Phosphorus

Dopant concentration
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 14
 Dopant Concentration and
Resistivity
• Higher dopant concentration, more carriers
(electrons or holes)
• Higher conductivity, lower resistivity
• Electrons move faster than holes
• N-type silicon has lower resistivity than p-
type silicon at the same dopant concentration

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 15

 Basic Devices

• Resistor
• Capacitor
• Diode
• Bipolar Transistor
• MOS Transistor

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 16

 Resistor
ρ
l h
w

l
R=ρ
wh
ρ: Resistivity

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 Resistor
• Resistors are made by doped silicon or
polysilicon on an IC chip
• Resistance is determined by length, line
width, height, and dopant concentration

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 18

 Capacitors

κ l

hl
h C =κ
d d
κ: Dielectric Constant

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 19

 Capacitors
• Charge storage device
• Memory Devices, esp. DRAM
• Challenge: reduce capacitor size while
keeping the capacitance
• High-κ dielectric materials

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 Capacitors
Dielectric Layer
Dielectric Poly 2
Layer
Poly
Si Si
Poly Si
Oxide
Si Poly 1
Heavily
Doped Si

Parallel plate Stacked Deep Trench

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 21
Metal Interconnection and RC Delay

Dielectric, κ Metal, ρ

I
l

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 22

 Diode

• P-N Junction
• Allows electric current go through only
when it is positively biased.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 23

 Diode

V1 V2
P1 P2

current
• V1 > V2 , • P1 > P2, current

• V1 < V2 , no current • P1 < P2, no current

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 24

 Figure 3.14

Transition region
−− ++
−− ++
−−
P −−
++
++
N
−− ++

Vn
V0
Vp
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 25
 Intrinsic Potential

kT Na Nd
V0 = ln 2
q ni

• For silicon V0 ~ 0.7 V

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 26
 I-V Curve of Diode

V
-I 0

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 27

 Bipolar Transistor

• PNP or NPN
• Switch
• Amplifier
• Analog circuit
• Fast, high power device

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 28

 NPN and PNP Transistors
E B
E C
B N P N

C
C
B
E C
B
P N P
E

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 29

 NPN Bipolar Transistor
Emitter Base Collector
Al•Cu•Si
SiO2
n+ p n+
p+ p+
n-epi
Electron flow
n+ buried layer
P-substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 30

 Sidewall Base Contact NPN
Bipolar Transistor
Metal
CVD
oxide CVD CVD
Base oxide oxide
Emitter
Collector
Poly p n+ p
Field Field Field
oxide n Epi n+
oxide oxide
n+ Buried Layer

P-substrate
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 31
 MOS Transistor
• Metal-oxide-semiconductor
• Also called MOSFET (MOS Field Effect
Transistor)
• Simple, symmetric structure
• Switch, good for digital, logic circuit
• Most commonly used devices in the
semiconductor industry
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 32
 NMOS Device
Basic Structure

VG VD

VG
“Metal” Gate

Ground VD
n+ n+
p-Si
Source Drain

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 33

 NMOS Device
Positive charges

VG = 0 Electron flow VG > V T > 0 VD > 0

VD

“Metal” Gate
+++++++
SiO2 SiO2 −−−−−−−
n+ n+ n+ n+
p-Si p-Si
Source Drain Source Drain

No current Negative charges

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 34

 PMOS Device
Negative charges
VG = 0 Hole flow VG < V T < 0 VD > 0
VD

“Metal” Gate

SiO2 −−−−−−−
SiO2 +++++++
p+ p+ p+ p+
n-Si n-Si
Source Drain Source Drain

No current Positive charges

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 35

 MOSFET

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 36

 MOSFET and Drinking Fountain
MOSFET Drinking Fountain

• Source, drain, gate • Source, drain, gate valve

• Source/drain biased • Pressurized source
• Voltage on gate to • Pressure on gate (button)
turn-on to turn-on
• Current flow between • Current flow between
source and drain source and drain
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 37
 Basic Circuits

• Bipolar
• PMOS
• NMOS
• CMOS
• BiCMOS

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 38

Devices with Different Substrates
• Bipolar
Dominate
Silicon • MOSFET
IC industry
• BiCMOS
Germanium • Bipolar: high speed devices

• GaAs: up to 20 GHz device

Compound
• Light emission diode (LED)

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 39

Market of Semiconductor Products

}
Compound
100% }
4%
} 8%
Bipolar

50%
MOSFET 88%

1980 1990 2000

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 40
 Bipolar IC
• Earliest IC chip
• 1961, four bipolar transistors, $150.00
• Market share reducing rapidly
• Still used for analog systems and power
devices
• TV, VCR, Cellar phone, etc.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 41

 PMOS
• First MOS field effect transistor, 1960
• Used for digital logic devices in the 1960s
• Replaced by NMOS after the mid-1970s

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 42

 NMOS
• Faster than PMOS
• Used for digital logic devices in 1970s and
1980s
• Electronic watches and hand-hold calculators
• Replaced by CMOS after the 1980s

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 43

 CMOS
• Most commonly used circuit in IC chip
since 1980s
• Low power consumption
• High temperature stability
• High noise immunity
• Symmetric design

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 44

 CMOS Inverter
Vdd

PMOS

V in Vout

NMOS
Vss
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 45
 CMOS IC

n+ Source/Drain p+ Source/Drain
Gate Oxide

Polysilicon

p-Si STI n-Si USG

Balk Si

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 46

 BiCMOS
• Combination of CMOS and bipolar circuits
• Mainly in 1990s
• CMOS as logic circuit
• Bipolar for input/output
• Faster than CMOS
• Higher power consumption
• Likely will have problem when power
supply voltage dropping below one volt
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 47
 IC Chips

• Memory
• Microprocessor
• Application specific IC (ASIC)

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 48

 Memory Chips
• Devices store data in the form of electric charge
• Volatile memory
– Dynamic random access memory (DRAM)
– S random access memory (SRAM)
• Non-volatile memory
– Erasable programmable read only memory (EPROM)
– FLASH

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 49

 DRAM
• Major component of computer and other
electronic instruments for data storage
• Main driving force of IC processing development
• One transistor, one capacitor

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 50

 Basic DRAM Memory Cell

Word line

NMOS

Capacitor

Bit line Vdd

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 51

 SRAM

• Fast memory application such as computer cache

memory to store commonly used instructions
• Unit memory cell consists of six transistors
• Much faster than DRAM
• More complicated processing, more expensive

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 52

 EPROM

• Non-volatile memory
• Keeping data ever without power supply
• Computer bios memory which keeps boot
up instructions
• Floating gate
• UV light memory erase

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 53

 EPROM
Passivation
Dielectric VG VD

Inter-poly Poly 2 Control Gate

Dielectric
Poly 1 Floating Gate
Gate
n+ n+
Oxide p-Si
Source Drain

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 54

 EPROM Programming
Passivation
Dielectric VG>VT>0 VD > 0

Inter-poly Poly 2 Control Gate

Dielectric
e- e- e- e- e- e- Floating Gate
Gate e-
n+ n+
Oxide p-Si
Source Drain Electron
Tunneling

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 55

 EPROM Programming
Passivation UV light
Dielectric VG>VT>0 VD > 0

Inter-poly Poly 2 Control Gate

Dielectric
e- e- Floating Gate
Gate
n+ n+
Oxide p-Si
Source Drain Electron
Tunneling

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 56

 IC Fabrication Processes
Ion implantation,
Diffusion
Epi, Poly
Adding Grown thin film, SiO 2 CV Dielectri
Deposited thin film PVD Meta
Electrical

Wafer Clean Patterned etch

Removing Etch Blanket
IC Strip
Dielectri
CMP
Fab. Meta Meta
Annealing Oxid
Heating Reflow Implantati
Alloying
Exposure (heating)

Patterning Photolithography PR coating (adding)

Baking (heating,
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 57
Developing
 Basic Bipolar Process Steps
• Buried layer doping
• Epitaxial silicon growth
• Isolation and transistor doping
• Interconnection
• Passivation

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 58

 Buried Layer Implantation

SiO2

n+
P-silicon

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 59

 Epitaxy Grow

n-epi
n+ buried layer

P-silicon

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 60

 Isolation Implantation

p+ p+
n-epi
n+ buried layer

P-silicon

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 61

 Emitter/Collector and Base
Implantation

n+ p n+
p+ p+
n-epi
n+ buried layer

P-silicon

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 62

 Metal Etch
SiO2
Emitter Base Collector
Al•Cu•Si

n+ p n+
p+ p+
n-epi
n+ buried layer

P-silicon

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 63

 Passivation Oxide Deposition
SiO2 Emitter Base Collector Al•Cu•Si
CVD
oxide
n+ p n+
p+ p+
n-epi
n+ buried layer

P-silicon

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 64

 MOSFET
• Good for digital electronics
• Major driving forces:
– Watches
– Calculators
– PC
– Internet
– Telecommunication

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 65

 1960s: PMOS Process
• Bipolar dominated
• First MOSFET made in Bell Labs
• Silicon substrate
• Diffusion for doping
– Boron diffuses faster in silicon
– PMOS

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 66

 PMOS Process Sequence (1960s)
Wafer clean (R) Etch oxide (R)
Field oxidation (A) Strip photo resist (R)
Mask 1. (Source/Drain) (P) Al deposition (A)
Etch oxide (R) Mask 4. (Metal) (P)
Strip photo resist/Clean (R) Etch Aluminum (R)
S/D diffusion (B)/Oxidation (A) Strip photo resist (R)
Mask 2. (Gate) (P) Metal Anneal (H)
Etch oxide (R) CVD oxide (A)
Strip photo resist/Clean (R) Mask 5. (Bonding pad) (P)
Gate oxidation (A) Etch oxide (R)
Mask 3. (Contact) (P) Test and packaging
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 67
 Wafer clean, field oxidation, and
photoresist coating
Native Oxide

N-Silicon N-Silicon

Primer Field Oxide

Field Oxide

Photoresist

N-Silicon N-Silicon

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 68

 Photolithography and etch
Source/Drain Mask UV Light
Source/Drain Mask Field Oxide

Photoresist PR

N-Silicon N-Silicon

Field Oxide Field Oxide

PR PR

N-Silicon N-Silicon

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 69

 Source/drain doping and gate
oxidation
Field Oxide Field Oxide

p+ p+
N-Silicon N-Silicon

Field Oxide Gate Oxide Field Oxide

p+ p+
p+ p+
N-Silicon N-Silicon

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 70

 Contact, Metallization, and
Passivation
Gate Oxide Al·Si Field Oxide
Gate Oxide Field Oxide

p+ p+ p+ p+
N-Silicon N-Silicon

Gate Oxide Field Oxide Gate Oxide CVD Cap Oxide

p+ p+ p+ p+
N-Silicon N-Silicon

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 71

 Illustration of a PMOS

Gate Oxide CVD Cap Oxide

p+ p+
N-Silicon
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 72
 NMOS Process after mid-1970s
• Doping: ion implantation replaced diffusion
• NMOS replaced PMOS
– NMOS is faster than PMOS
• Self-aligned source/drain

• Main driving force: watches and calculators

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 73

 Self-aligned S/D Implantation
Phosphorus Ions, P+

e
id
n
co

ox
ili

eld
lys

Fi
Po
Gate
n+ n+
p-silicon

Source/Drain Gate oxide

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 74

NMOS Process Sequence (1970s)
Wafer clean PSG reflow
Grow field oxide Mask 3. Contact
Mask 1. Active Area Etch PSG/USG
Etch oxide Strip photo resist/Clean
Strip photo resist/Clean Al deposition
Grow gate oxide Mask 4. Metal
Deposit polysilicon Etch Aluminum
Mask 2. Gate Strip photo resist
Etch polysilicon Metal anneal
Strip photo resist/Clean CVD oxide
S/D and poly dope implant Mask 5. Bonding pad
Anneal and poly reoxidation Etch oxide
CVD USG/PSG Test and packaging
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 75
 NMOS Process Sequence
Field
Clean p-Si p-Si Oxidation

Oxide Gate
Etch p-Si
p-Si Oxidation

Poly Dep. poly poly

Poly Etch
p-Si p-Si

P+ Ion poly poly

n+ n+ Annealing
Implant p-Si p-Si

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 76

 NMOS Process Sequence
PSG PSG PSG
PSG Dep. poly poly
Reflow
p-Si p-Si

Al·Si
PSG PSG PSG Metal
poly poly
Etch Dep.
p-Si p-Si

Al·Si
Al·Si SiN

Metal PSG PSG Nitride

Etch poly poly Dep.
p-Si n+ p-Si n+

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 77

 CMOS
• In the 1980s MOSFET IC surpassed bipolar
• LCD replaced LED
• Power consumption of circuit
• CMOS replaced NMOS
• Still dominates the IC market

• Backbone of information revolution

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 78
 Advantages of CMOS
• Low power consumption
• High temperature stability
• High noise immunity

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 79

 CMOS Inverter, Its Logic
Symbol and Logic Table
Vdd
Vin Vout
PMOS
Vin Vout

NMOS In Out
Vss 0 1
1 0
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 80
CMOS Chip with 2 Metal Layers
PD2 Nitride
PD1 Oxide
Metal 2, Al·Cu·Si
IMD USG dep/etch/dep
Al·Cu·Si
PMD BPSG
LOCOS
SiO2
n+ n+ p+ p+
p+ p+
Poly Si Gate N-well
P-type substrate
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 81
CMOS Chip
with 4 Metal Passivation 2, nitride
Lead-tin
alloy bump
Passivation 1, USG
Layers Metal 4 Copper
Tantalum
barrier layer
FSG

Metal 3 Copper FSG Nitride etch

stop layer
FSG
Nitride
Metal 2 Copper seal layer

FSG
Tungsten plug Tantalum
M1 Cu Cu FSG
barrier layer
FSG
T/TiN barrier &
Tungsten local PSG Tungsten adhesion layer
Interconnection
STI n+ n+ USG p+ p+
P-well PMD nitride
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm N-well 82 layer
barrier
P-epi
P-wafer
 Summary
• Semiconductors are the materials with
conductivity between conductor and
insulator
• Its conductivity can be controlled by dopant
concentration and applied voltage
• Silicon, germanium, and gallium arsenate
• Silicon most popular: abundant and stable
oxide
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 83
 Summary
• Boron doped semiconductor is p-type,
majority carriers are holes
• P, As, or Sb doped semiconductor is p-type,
the majority carriers are electrons
• Higher dopant concentration, lower resistivity
• At the same dopant concentration, n-type has
lower resistivity than p-type

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 84

 Summary
• R=ρ l/A
• C=κ A/d
• Capacitors are mainly used in DRAM
• Bipolar transistors can amplify electric signal,
mainly used for analog systems
• MOSFET electric controlled switch, mainly
used for digital systems
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 85
 Summary
• MOSFETs dominated IC industry since 1980s
• Three kinds IC chips microprocessor,
memory, and ASIC
• Advantages of CMOS: low power, high
temperature stability, high noise immunity,
and clocking simplicity

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 86

 Summary
• The basic CMOS process steps are transistor
making (front-end) and
interconnection/passivation (back-end)
• The most basic semiconductor processes are
adding, removing, heating, and patterning
processes.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 87

 Chapter 4
Wafer Manufacturing
and Epitaxy Growing
Hong Xiao, Ph. D.
[email protected]

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 1

 Objectives
• Give two reasons why silicon dominate
• List at least two wafer orientations
• List the basic steps from sand to wafer
• Describe the CZ and FZ methods
• Explain the purpose of epitaxial silicon
• Describe the epi-silicon deposition process.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 2

 Crystal Structures
• Amorphous
– No repeated structure at all
• Polycrystalline
– Some repeated structures
• Single crystal
– One repeated structure

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 3

 Amorphous Structure

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 4

 Polycrystalline Structure

Grain
Boundary

Grain

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 5

 Single Crystal Structure

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 6

 Why Silicon?
• Abundant, cheap
• Silicon dioxide is very stable, strong
dielectric, and it is easy to grow in thermal
process.
• Large band gap, wide operation temperature
range.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 7

 Name Silicon
Symbal Si
Atomic number 14
Atomic weight 28.0855
Discoverer Jöns Jacob Berzelius
Discovered at Sweden
Discovery date 1824
Origin of name From the Latin word "silicis" meaning "flint"
Bond length in single crystal Si 2.352 Å
Density of solid 2.33 g/cm3
Molar volume 12.06 cm3
Velocity of sound 2200 m/sec
Electrical resistivity 100,000 µΩ⋅cm
Reflectivity 28%
Melting point 1414 °C
Boiling point 2900 °C
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 8
Source: http://www.shef.ac.uk/chemistry/web-elements/nofr-key/Si.html
Unit Cell of Single Crystal Silicon

Si

Si

Si

Si

Si

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 9

 Crystal Orientations: <100>
z

<100> plane

x
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 10
 Crystal Orientations: <111>
z

<111> plane
<100> plane

x
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 11
 Crystal Orientations: <110>
z

<110> plane

x
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 12
 <100> Orientation Plane
Basic lattice cell Atom

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 13

 <111> Orientation Plane
Basic lattice cell Silicon atom

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 14

 <100> Wafer Etch Pits

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 15

 <111> Wafer Etch Pits

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 16

 Illustration of the Defects
Impurity on substitutional site Silicon Atom

Impurity in
Interstitial Site
Silicon
Interstitial

Vacancy or Schottky Defect Frenkel Defect

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 17
 Dislocation Defects

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 18

 From Sand to Wafer
• Quartz sand: silicon dioxide
• Sand to metallic grade silicon (MGS)
• React MGS powder with HCl to form TCS
• Purify TCS by vaporization and condensation
• React TCS to H2 to form polysilicon (EGS)
• Melt EGS and pull single crystal ingot

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 19

 From Sand to Wafer (cont.)
• Cut end, polish side, and make notch or flat
• Saw ingot into wafers
• Edge rounding, lap, wet etch, and CMP
• Laser scribe

• Epitaxy deposition

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 20

 From Sand to Silicon

Heat (2000 °C)

SiO2 + C → Si + CO2
Sand Carbon MGS Carbon Dioxide

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 21

 Silicon Purification I
Hydrochloride Reactor,
300 °C

Si + HCl Silicon
→ TCS Powder
Condenser
Filters

Pure TCS with

Purifier
99.9999999%

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 22

 Polysilicon Deposition, EGS

Heat (1100 °C)

SiHCl3 + H2 → Si + 3HCl
TCS Hydrogen EGS Hydrochloride

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 23

 Silicon Purification II
Process
Chamber EGS
H2

H2 and TCS
Liquid
TCS TCS+H2→EGS+HCl

Carrier gas
bubbles
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 24
 Electronic Grade Silicon

Source: http://www.fullman.com/semiconductors/_polysilicon.html

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 25

 Crystal Pulling: CZ method
Single Crystal Silicon Seed
Quartz Crucible Single Crystal
silicon Ingot

Molten Silicon Heating Coils

1415 °C

Graphite Crucible

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 26

 CZ Crystal Pullers

Mitsubish Materials Silicon

Source: http://www.fullman.com/semiconductors/_crystalgrowing.html
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 27
 CZ Crystal Pulling

Source: http://www.fullman.com/semiconductors/_crystalgrowing.html
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 28
 Floating Zone Method

Poly Si Molten Silicon

Rod
Heating Coils
Movement Heating
Coils

Single Crystal
Silicon

Seed Crystal

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 29

 Comparison of the Two Methods
• CZ method is more popular
– Cheaper
– Larger wafer size (300 mm in production)
– Reusable materials
• Floating Zone
– Pure silicon crystal (no crucible)
– More expensive, smaller wafer size (150 mm)
– Mainly for power devices.
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 30
 Ingot Polishing, Flat, or Notch

Flat, 150 mm and smaller Notch, 200 mm and larger

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 31
 Wafer Sawing

Orientation Coolant
Notch
Crystal Ingot
Saw Blade Ingot
Movement

Diamond Coating

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 32

 Parameters of Silicon Wafer

Wafer Size (mm) Thickness (µm) Area (cm2) Weight (grams)

50.8 (2 in) 279 20.26 1.32
76.2 (3in) 381 45.61 4.05
100 525 78.65 9.67
125 625 112.72 17.87
150 675 176.72 27.82
200 725 314.16 52,98
300 775 706.21 127.62

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 33

 Wafer Edge Rounding
Wafer movement
Wafer

Wafer Before Edge Rounding

Wafer After Edge Rounding

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 34

 Wafer Lapping
• Rough polished
• conventional, abrasive, slurry-lapping
• To remove majority of surface damage
• To create a flat surface

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 35

 Wet Etch
• Remove defects from wafer surface
• 4:1:3 mixture of HNO3 (79 wt% in H2O),
HF (49 wt% in H2O), and pure CH3COOH.
• Chemical reaction:

3 Si + 4 HNO3 + 6 HF → 3 H2SiF6 + 4 NO + 8 H2O

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 36

 Chemical Mechanical Polishing

Pressure
Slurry
Wafer Holder
Wafer

Polishing Pad

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 37

 200 mm Wafer Thickness and
Surface Roughness Changes
76 µm
After Wafer Sawing
914 µm

76 µm
After Edge Rounding 914 µm
12.5 µm
After Lapping 814 µm
<2.5 µm
After Etch 750 µm

Virtually Defect Free

After CMP 725 µm
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 38
 Epitaxy Grow

•Definition
•Purposes
•Epitaxy Reactors
•Epitaxy Process

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 39

 Epitaxy: Definition
• Greek origin
• epi: upon
• taxy: orderly, arranged

• Epitaxial layer is a single crystal layer on a

single crystal substrate.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 40

 Epitaxy: Purpose
• Barrier layer for bipolar transistor
– Reduce collector resistance while keep high
breakdown voltage.
– Only available with epitaxy layer.
• Improve device performance for CMOS and
DRAM because much lower oxygen,
carbon concentration than the wafer crystal.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 41

 Epitaxy Application, Bipolar
Transistor
Emitter Base Collector
Al•Cu•Si
SiO2
n+ p n+
p+ p+
n-Epi
Electron flow
n+ Buried Layer
P-substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 42

 Epitaxy Application: CMOS

Metal 1, Al•Cu

W
BPSG

STI n+ n+ USG p+ p+
P-Well N-Well
P-type Epitaxy Silicon
P-Wafer

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 43

 Silicon Source Gases

Silane SiH4
Dichlorosilane DCS SiH2Cl2
Trichlorosilane TCS SiHCl3
Tetrachlorosilane SiCl4

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 44

 Dopant Source Gases

Diborane B2H6
Phosphine PH3
Arsine AsH3

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 45

DCS Epitaxy Grow, Arsenic Doping

Heat (1100 °C)

SiH2Cl2 → Si + 2HCl
DCS Epi Hydrochloride

Heat (1100 °C)

AsH3 → As + 3/2 H2

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 46

Schematic of DCS Epi Grow and
Arsenic Doping Process

SiH2Cl2
AsH3

H2
HCl
Si AsH3

As H

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 47

Epitaxial Silicon Growth Rate Trends
Temperature (°C)
1300 1200 1100 1000 900 800 700
1.0

0.5
SiH4
0.2 Mass transport
limited
0.1 SiHCl 3

0.05
Growth

Surface reaction limited

0.02 SiH2Cl2

0.01
0.7 0.8 0.9 1.0 1.1
Hong Xiao, Ph. D. 1000/T(K)
www2.austin.cc.tx.us/HongXiao/Book.htm 48
 Barrel Reactor
Radiation
Heating
Coils Wafers

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 49

 Vertical Reactor

Wafers

Reactants
Heating
Coils

Reactants and
byproducts
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 50
 Horizontal Reactor
Heating Coils

Wafers
Reactants
Reactants and
byproducts

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 51

 Epitaxy Process, Batch System
• Hydrogen purge, temperature ramp up
• HCl clean
• Epitaxial layer grow
• Hydrogen purge, temperature cool down
• Nitrogen purge
• Open Chamber, wafer unloading, reloading

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 52

 Single Wafer Reactor

•Sealed chamber, hydrogen ambient

•Capable for multiple chambers on a mainframe
•Large wafer size (to 300 mm)
•Better uniformity control

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 53

 Single Wafer Reactor
Heat Heating Lamps
Radiation
Wafer

Reactants

Reactants &
byproducts

Susceptor Quartz Quartz

Lift Window
Fingers
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 54
 Epitaxy Process, Single Wafer
System
• Hydrogen purge, clean, temperature ramp up
• Epitaxial layer grow
• Hydrogen purge, heating power off
• Wafer unloading, reloading

• In-situ HCl clean,

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 55

 Why Hydrogen Purge
• Most systems use nitrogen as purge gas
• Nitrogen is a very stable abundant
• At > 1000 °C, N2 can react with silicon
• SiN on wafer surface affects epi deposition
• H2 is used for epitaxy chamber purge
• Clean wafer surface by hydrides formation

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 56

 Properties of Hydrogen
Name Hydrogen
Symbol H
Atomic number 1
Atomic weight 1.00794
Discoverer Henry Cavendish
Discovered at England
Discovery date 1766
Origin of name From the Greek words "hydro" and "genes" meaning
"water" and "generator"
Molar volume 11.42 cm 3
Velocity of sound 1270 m/sec
Refractive index 1.000132
Melting point -258.99 C
Boiling point -252.72 C
Thermal conductivity 0.1805 W m-1 K-1

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 57

 Defects in Epitaxy Layer
Stacking Fault from Stacking Fault form
Surface Nucleation Substrate Stacking Fault

Dislocation Impurity Particle

Hillock
Epi Layer

Substrate

After S.M. Zse’s VLSI Technology

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 58

 Future Trends
• Larger wafer size
• Single wafer epitaxial grow
• Low temperature epitaxy
• Ultra high vacuum (UHV, to 10-9 Torr)
• Selective epitaxy

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 59

 Summary
• Silicon is abundant, cheap and has strong,
stable and easy grown oxide.
• <100> and <111>
• CZ and floating zone, CZ is more popular
• Sawing, edging, lapping, etching and CMP

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 60

 Summary
• Epitaxy: single crystal on single crystal
• Needed for bipolar and high performance
CMOS, DRAM.
• Silane, DCS, TCS as silicon precursors
• B2H6 as P-type dopant
• PH3 and AsH3 as N-type dopants
• Batch and single wafer systems
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 61
 Chapter 5
Thermal Processes

Hong Xiao, Ph. D.

[email protected]

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 1

 Objective

• List four thermal processes

• Describe thermal process in IC fabrication
• Describe thermal oxidation process
• Explain the advantage of RTP over furnace
• Relate your job or products to the processes

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 2

 Topics
• Introduction • High Temp CVD
• Hardware – Epi
• Oxidation – Poly
– Silicon Nitride
• Diffusion
• RTP
• Annealing
– RTA
– Post-Implantation
– RTP
– Alloying
– Reflow • Future Trends
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 3
 Definition
• Thermal processes are the processes operate
at high temperature, which is usually higher
than melting point of aluminum.
• They are performed in the front-end of the
semiconductor process, usually in high
temperature furnace commonly called
diffusion furnace.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 4

 Introduction

• Advantages of Silicon
– Abundant, cheap
– Stable and useful oxide

• Oxidation and Diffusion are the backbone

processes in early IC fabrications

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 5

Thermal Processes in IC Fabrication
Materials IC Fab

Dielectric Test
Metallization CMP
Thin Film
Wafers

Thermal Etch Packaging

Implant
Processes PR strip PR strip
Masks

Photo- Final Test

lithography

Design

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 6

 Hardware Overview

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 7

 Horizontal Furnace

• Commonly used tool for thermal processes

• Often be called as diffusion furnace
• Quartz tube inside a ceramic liner called muffle
• Multi-tube system

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 8

 Layout of a Horizontal Furnace
Exhaust

Gas Process Loading

Deliver Tubes System
System

Control System

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 9

 Control System
Computer

Micro- Micro- Micro- Micro- Micro-

controller controller controller controller controller

Loading Vacuum
Process Tube Exhaust Gas Panel
Station System
Interface Interface Interface
Interface Interface
Board Board Board
Board Board

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 10

 Gas Deliver System
MFC To
MFC Process
Tube
MFC

Control Valve
Regulator

Gas cylinders

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 11

 Source Cabinet
• Source Gases
– Oxygen
– Water Vapor
– Nitrogen
– Hydrogen
• Gas control panel
• Gas flow controller
• Gas flow meter
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 12
 Oxidation Sources
• Dry Oxygen
• Water vapor sources
– Bubblers
– Flash systems
• Hydrogen and oxygen, H2 + O2 → H2O
• Chlorine sources, for minimized mobile ions
in gate oxidation
– Anhydrous hydrogen chloride HCl
– Trichloroethylene (TCE), Trichloroethane (TCA)
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 13
 Diffusion Sources
• P-type dopant
– B2H6, burnt chocolate, sickly sweet odor
– Poisonous, flammable, and explosive
• N-type dopants
– PH3, rotten fish smell
– AsH3, garlic smell
– Poisonous, flammable, and explosive
• Purge gas
– N2
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 14
 Deposition Sources
• Silicon source for poly and nitride deposition:
– Silane, SiH4, pyrophoric, toxic and explosive
– DCS, SiH2Cl2, extremely flammable
• Nitrogen source for nitride deposition:
– NH3, pungent, irritating odor, corrosive
• Dopants for polysilicon deposition
– B2H6, PH3 and AsH3
• Purge gas
– N2

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 15

 Anneal Sources

• High purity N2, is used for most anneal

processes.
• H2O sometimes used as ambient for PSG or
BPSG reflow.
• O2 is used for USG anneal after USG CMP in
STI formation process.
• Lower grade N2 is used for idle purge.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 16

 Exhaust System
• Removal of hazardous gases before release
• Poisonous, flammable, explosive and corrosive
gases.
• Burn box removes most poisonous, flammable
and explosive gases
• Scrubber removes burned oxide and corrosive
gases with water.
• Treated gases exhaust to the atmosphere.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 17

 Wafer Loading, Horizontal System

Wafers

Process
gases To
Exhaust

Process Tube Wafer Boat

Paddle

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 18

 Wafer Loading, Vertical System

Wafers

Suscepter
Tower

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 19

 Temperature Control

• Thermal processes are very sensitive to the

temperature
• Precisely temperature control is vital
• ±0.5 °C at central zone
• ±0.05% at 1000 °C!

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 20

 Temperature Control System

• Thermocouples touching the reaction tube

• Proportional band controllers feed the power
to the heating coils
• The heating power is proportional to
difference between setting point and
measured value

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 21

 Reaction Chamber
• High-purity Quartz
– Stability at high temperature
– Basic Cleanliness
• Drawback
– Fragility
– Some metallic ions
– Not a sodium barrier
– Small flakes at > 1200 °C, devitrification
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 22
 Horizontal Furnace
Wafers
Heating Coils

Quartz
Tube
Gas flow

Temperature Center Zone

Flat Zone

Distance
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 23
Vertical Furnace, Process Position
Process
Chamber
Heaters
Wafers

Suscepter Tower

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 24

 Quartz Tube
• Electric Fused
• Flame Fused
• Both of them as trace amount of metals
• Flame-fused tubes produced devices have
better characteristics.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 25

 Quartz Tube Clean
• Very important especially for deposition
furnace to prevent particle contamination
• Out side fab, ex-situ
– Hydrofluoric acid (HF) tank
– Remove a thin layer of quartz every time
– limited tube lifetime
• In-situ clean
– Plasma generator inside tube
– Free fluorine from NF3 etch away contaminant
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 26
 Silicon Carbide Tube
• Pro
– Higher thermal stability
– Better metallic ion barrier
• Con
– Heavier
– More expensive

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 27

 Temperature Control
Anti-Warp Methods
• Ramping
– Load wafer slowly at a lower temperature (idle
temperature, ~ 800 °C)
– Ramp temperature to process point after a short
stabilization period
• Slow loading
– 1 inch/min
– thermal capacity of 200 six-inch wafers can
drop temperature as much as 50 °C
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 28
 Horizontal Furnace
• Contain 3 or 4 tubes (reaction chambers)
• Separate temperature control system for
each tube

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 29

 Horizontal Furnace
Wafers
Heating Coils

Quartz
Tube
Gas flow

Temperature Center Zone

Flat Zone

Distance
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 30
 Furnace
• Wafer Clean Station
• Wafer Loading Station
– Manual wafer loading
– Automatic wafer loading
• Oxidation Process Automation

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 31

 Vertical Furnaces
• Place the process tube in vertical direction
• Smaller footprint
• Better contamination control
• Better wafer handling
• Lower maintenance cost and higher uptime

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 32

 Vertical Furnace, Loading and
Unloading Position
Process
Chamber
Heaters

Wafers

Suscepter Tower

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 33

 Smaller Footprint

• Clean room footage becomes very expensive

• Small footprint reduces cost of ownership (COO)

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 34

 Better Contamination Control

• Gas flow from top to bottom

• Better uniformity for Laminar gas flow control
• Particles has less chance to fall at the center of
the wafers

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 35

 Better Wafer Handling
• High torque on paddle of horizontal when it
handle large amount of large diameter wafers
• Zero torque for wafer tower in vertical system

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 36

 Summery of Hardware
• Furnaces are commonly used in thermal processes
• Furnaces usually consist with control system, gas
delivery system, process tube or chamber, wafer
loading system, and exhaust system.
• Vertical furnace is more widely used due to it
smaller footprint, better contamination control,
and lower maintenance.
• Precise temperature and its uniformity is vital for
the success of the thermal processes.
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 37
 Oxidation

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 38

 Oxidation
• Introduction
• Applications
• Mechanism
• Process
• System
• RTO

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 39

 Introduction
• Silicon reacts with oxygen
• Stable oxide compound
• Widely used in IC manufacturing

Si + O2 → SiO2

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 40

 Oxidation
Original Silicon Surface

Silicon Silicon
O2 Dioxide
O2 O2 O2
O2
O2 O2 O2
O2
O2
O2 O2
O2 O2
O2
55% 45%
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 41
 Some Facts About Silicon
Name Silicon
Symbol Si
Atomic number 14
Atomic weight 28.0855
Discoverer Jöns Jacob Berzelius
Discovered at Sweden
Discovery date 1824
Origin of name From the Latin word "silicis" meaning "flint"
Bond length in single crystal Si 2.352 Å
Density of solid 2.33 g/cm 3
Molar volume 12.06 cm 3
Velocity of sound 2200 m/sec
Hardness 6.5
Electrical resistivity 100,000 µΩ ⋅cm
Reflectivity 28%
Melting point 1414 °C
Boiling point 2900 °C
Thermal conductivity 150 W m -1 K -1
Coefficient of linear thermal 2.6×10 -6 K -1
expansion
Etchants (wet) HNO 4 and HF, KOH, etc.
Etchants (dry) HBr, Cl 2, NF3 , etc.
Hong Xiao,
CVDPh.Precursor
D. www2.austin.cc.tx.us/HongXiao/Book.htm
SiH 4, SiH 2 Cl 2, SiHCl3 , and SiCl4 42
 Fact About Oxygen
Name Oxygen
Symbol O
Atomic number 8
Atomic weight 15.9994
Discoverer Joseph Priestley, Carl Scheele
Discovered at England, Sweden
Discovery date 1774
Origin of name From the Greek words "oxy genes" meaning
"acid" (sharp) and "forming" (acid former)
Molar volume 17.36 cm3
Velocity of sound 317.5 m/sec
Refractivity 1.000271
Melting point 54.8 K = -218.35 °C
Boiling point 90.2 K = -182.95 °C
Thermal conductivity 0.02658 W m-1 K-1
Applications Thermal oxidation, oxide CVD, reactive
sputtering and photoresist stripping
Main sources O2, H 2 O, N2 O, O3
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 43
 Application of Oxidation
• Diffusion Masking Layer
• Surface Passivation
– Screen oxide, pad oxide, barrier oxide
• Isolation
– Field oxide and LOCOS
• Gate oxide

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 44

 Diffusion Barrier
• Much lower B and P diffusion rates in SiO2
than that in Si
• SiO2 can be used as diffusion mask

Dopant

SiO2 SiO2

Si
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 45
 Application, Surface Passivation
Pad Oxide Screen Oxide
Sacrificial Oxide Barrier Oxide

SiO2

Si

Normally thin oxide layer (~150Å) to protect

silicon defects from contamination and over-stress.
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 46
 Screen Oxide

Dopant Ions

Photoresist Photoresist

Si Substrate

Screen Oxide
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 47
Pad and Barrier Oxides in STI Process
Nitride
Pad Oxide
Silicon
Trench Etch

Nitride USG
Pad Oxide
Silicon
Trench Fill
Barrier Oxide USG

Silicon
USG CMP; USG Anneal; Nitride and Pad Oxide Strip

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 48

 Application, Pad Oxide
• Relieve strong tensile stress of the nitride
• Prevent stress induced silicon defects
Pad Oxide

Silicon nitride

Silicon Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 49

 Application, Device Isolation

• Electronic isolation of neighboring devices

• Blanket field oxide
• Local oxidation of silicon (LOCOS)
• Thick oxide, usually 3,000 to 10,000 Å

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 50

 Blanket Field Oxide Isolation
Silicon
Wafer Clean

Silicon Dioxide

Silicon
Activation Area Field Oxidation

Field Oxide

Silicon
Oxide Etch
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 51
 LOCOS Process
Pad Oxide
Silicon nitride
P-type substrate

Pad oxidation, nitride deposition and patterning

Silicon nitride SiO2

p+ P-type substrate p+ Isolation Doping p +

LOCOS oxidation
Bird’s Beak
SiO2
p+ P-type substrate p+ Isolation Doping p
+

Nitride and pad oxide strip

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 52
 LOCOS
• Compare with blanket field oxide
– Better isolation
– Lower step height
– Less steep sidewall
• Disadvantage
– rough surface topography
– Bird’s beak
• Replacing by shallow trench isolation (STI)
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 53
 Application, Sacrificial Oxide
• Defects removal from silicon surface
Sacrificial Oxide
STI USG
P-Well N-Well
Sacrificial Oxidation

STI USG
P-Well N-Well
Strip Sacrificial Oxide
Gate Oxide
STI USG
P-Well N-Well
Gate Oxidation
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 54
 Application, Device Dielectric
• Gate oxide: thinnest and most critical layer
• Capacitor dielectric
VG VD > 0
Poly Si

Gate

Thin oxide
n+ n+
p-Si
Source Drain

Electrons
Si Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 55

 Oxide and Applications
Name of the Oxide Thickness Application Time in application

Native 15 - 20 Å undesirable -

Screen ~ 200 Å Implantation Mid-70s to present

Masking ~ 5000 Å Diffusion 1960s to mid-1970s

Field and LOCOS 3000 - 5000 Å Isolation 1960s to 1990s

Pad 100 - 200 Å Nitride stress buffer 1960s to present

Sacrificial <1000 Å Defect removal 1970s to present

Gate 30 - 120 Å Gate dielectric 1960s to present

Barrier 100 - 200 Å STI 1980s to present

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 56

Silicon Dioxide Grown on Improperly
Cleaned Silicon Surface

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 57

 Pre-oxidation Wafer Clean

• Particulates
• Organic residues
• Inorganic residues
• Native oxide layers

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 58

 RCA Clean
• Developed by Kern and Puotinen in 1960 at RCA
• Most commonly used clean processes in IC fabs
• SC-1-- NH4OH:H2O2:H2O with 1:1:5 to 1:2:7 ratio
at 70 to 80 °C to remove organic contaminants.
• SC-2-- HCl:H2O2:H2Owith 1:1:6 to 1:2:8 ratio at
70 to 80 °C to remove inorganic contaminates.
• DI water rinse
• HF dip or HF vapor etch to remove native oxide.
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 59
 Pre-oxidation Wafer Clean
Particulate Removal

• High purity deionized (DI) water or

H2SO4:H2O2 followed by DI H2O rinse.
• High pressure scrub or immersion in heated
dunk tank followed by rinse, spin dry and/or
dry bake (100 to 125 °C).

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 60

 Pre-oxidation Wafer Clean
Organic Removal

• Strong oxidants remove organic residues.

• H2SO4:H2O2 or NH3OH:H2O2 followed by
DI H2O rinse.
• High pressure scrub or immersion in heated
dunk tank followed by rinse, spin dry and/or
dry bake (100 to 125 °C).

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 61

 Pre-oxidation Wafer Clean
Inorganic Removal

• HCl:H2O.
• Immersion in dunk tank followed by rinse,
spin dry and/or dry bake (100 to 125 °C).

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 62

 Pre-oxidation Wafer Clean
Native Oxide Removal

• HF:H2O.
• Immersion in dunk tank or single wafer
vapor etcher followed by rinse, spin dry
and/or dry bake (100 to 125 °C).

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 63

 Oxidation Mechanism

• Si + O2 SiO2
• Oxygen comes from gas
• Silicon comes from substrate
• Oxygen diffuse cross existing silicon
dioxide layer and react with silicon
• The thicker of the film, the lower of the
growth rate
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 64
 Oxide Growth Rate Regime

Linear Growth Regime

B
Oxide Thickness

X= t
A

Diffusion-limited Regime

X = √B t

Oxidation Time
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 65
 <100> Silicon Dry Oxidation
1.2
Oxide Thickness (micron)

<100> Silicon Dry Oxidation 1200 °C

1.0

0.8 1150 °C

1100 °C
0.6
1050 °C
0.4 1000 °C
950 °C
0.2
900 °C

0 2 4 6 8 10 12 14 16 18 20
Oxidation Time (hours)
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 66
 Wet (Steam) Oxidation
• Si + 2H2O SiO2 + 2H2
• At high temperature H2O is dissociated to H
and H-O
• H-O diffuses faster in SiO2 than O2
• Wet oxidation has higher growth rate than
dry oxidation.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 67

<100> Silicon Wet Oxidation Rate
1150 °C
<100> Silicon Wet Oxidation
3.0 1100 °C
Oxide Thickness (micron)

1050 °C
2.5
1000 °C
2.0
950 °C
1.5 900 °C

1.0

0.5

0 2 4 6 8 10 12 14 16 18 20
Oxidation Time (hours)
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 68
 Oxidation Rate

• Temperature
• Chemistry, wet or dry oxidation
• Thickness
• Pressure
• Wafer orientation (<100> vs. <111>)
• Silicon dopant

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 69

 Oxidation Rate
Temperature
• Oxidation rate is very sensitive
(exponentially related) to temperature
• Higher temperature will have much higher
oxidation rate.
• The higher of temperature is, the higher of
the chemical reaction rate between oxygen
and silicon is and the higher diffusion rate
of oxygen in silicon dioxide is.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 70

 Oxidation Rate
Wafer Orientation

• <111> surface has higher oxidation rate

than <100> surface.
• More silicon atoms on the surface.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 71

 Wet Oxidation Rate
1.8
Oxide Thickness (micron)
1200 °C
1.6 <111> Orientation
1.4
95 °C Water 1100 °C
1.2
1.0 1000 °C
0.8
0.6
0.4 920 °C
0.2

0 1 2 3 4
Oxidation Time (hours)
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 72
 Oxidation Rate
Dopant Concentration
• Dopant elements and concentration
• Highly phosphorus doped silicon has higher
growth rate, less dense film and etch faster.
• Generally highly doped region has higher
grow rate than lightly doped region.
• More pronounced in the linear stage (thin
oxides) of oxidation.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 73

 Oxidation: Dopants
Pile-up and Depletion Effects
•N-type dopants (P, As, Sb) have higher
solubility in Si than in SiO2, when SiO2
grow they move into silicon, it is call
pile-up or snowplow effect.

•Boron tends to go to SiO2, it is called

depletion effect.
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 74
 Depletion and Pile-up Effects
Original Si Surface Original Si Surface

Si-SiO2 interface Si-SiO2 interface

Dopant Concentration
Dopant Concentration

Original Distribution

SiO2 Si SiO2 Si

P-type Dopant Depletion N-type dopant Pile-up

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 75
 Oxidation Rate
Doped oxidation (HCl)

• HCl is used to reduce mobile ion contamination.

• Widely used for gate oxidation process.
• Growth rate can increase from 1 to 5 percent.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 76

 Oxidation Rate
Differential Oxidation
• The thicker of the oxide film is, the slower of
the oxidation rate is.
• Oxygen need more time to diffuse cross the
existing oxide layer to react with substrate
silicon.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 77

 Pre-oxidation Clean
• Thermally grown SiO2 is amorphous.
• Tends to cross-link to form a crystal
• In nature, SiO2 exists as quartz and sand
• Defects and particles can be the nucleation sites
• Crystallized SiO2 with poor barrier capability.

• Need clean silicon surface before oxidation.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 78
 Oxidation Process
• Dry Oxidation, thin oxide
– Gate oxide
– Pad oxide, screen oxide, sacrificial oxide, etc.

• Wet Oxidation, thick oxide

– Field oxide
– Diffusion masking oxide

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 79

 Dry Oxidation System
MFC
To
MFC
Process
MFC Tube
MFC

Control Valves
Process N2

Purge N2

Regulator
HCl

O2

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 80

 Dry Oxidation
• Dry O2 as the main process gas
• HCl is used to remove mobile ions for
gate oxidation
• High purity N2 as process purge gas
• Lower grade N2 as idle purge gas

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 81

 Gate Oxidation Steps

• Idle with purge N2 flow

• Idle with process N2 flow
• Wafer boats push-in with process N2 flow
• Temperature ramp-up with process N2 flow
• Temperature stabilization with process N2 flow
• Oxidation with O2, HCl, stop N2 flow

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 82

Dangling Bonds and Interface Charge
Interface State Charge (Positive)

Dangling
Bond
SiO2
+ + + + +

Si-SiO2 Si
Interface

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 83

 Gate Oxidation Steps, Continue
• Oxide annealing, stop O2, start process flow N2
• Temperature cool-down with process N2 flow
• Wafer boats pull-out with process N2 flow
• Idle with process N2 flow
• Next boats and repeat process
• Idle with purge N2 flow

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 84

 Wet Oxidation Process
• Faster, higher throughput
• Thick oxide, such as LOCOS
• Dry oxide has better quality

Process Temperature Film Thickness Oxidation Time

Dry oxidation 1000 °C 1000 Å ~ 2 hours

Wet oxidation 1000 °C 1000 Å ~ 12 minutes

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 85

 Water Vapor Sources

• Boiler
• Bubbler
• Flush
• Pyrogenic

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 86

 Boiler System
Heated Gas line Heated Fore line

Process
MFC Exhaust
Tube

Vapor Bubbles
Water
Heater
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 87
 Bubbler System

N2 + H2O Process
N2 MFC
Tube
Heated Gas Line
Exhaust
Water N2 Bubbles

Heater
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 88
 Flush System

Water
Hot Plate

Process
N2 MFC
Tube

Heater
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 89
 Pyrogenic Steam System

Hydrogen Flame, 2 H2 + O2 → 2 H2O

O2
H2 To
Exhaust

Process Tube Wafer Boat

Thermal Couple Paddle

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 90

 Pyrogenic System
• Advantage
– All gas system
– Precisely control of flow rate
• Disadvantage
– Introducing of flammable, explosive hydrogen

• Typical H2:O2 ratio is between 1.8:1 to 1.9:1.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 91

 Pyrogenic Wet Oxidation System

MFC Process Tube

MFC
MFC
MFC Wafers Burn Box

Control Valves
Process N2

Purge N2

Regulator
Scrubbier
O2
H2

Exhaust

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 92

 Wet Oxidation Process Steps
• Idle with purge N2 flow
• Idle with process N2 flow
• Ramp O2 with process N2 flow
• Wafer boat push-in with process N2 and O2 flows
• Temperature ramp-up with process N 2 and O2 flows
• Temperature stabilization with process N2 and O2 flows
• Ramp O2, turn-off N2 flow
• Stabilize the O2 flow

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 93

 Wet Oxidation Process Steps
• Turn-on H2 flow, ignition and H2 flow stabilization
• Steam oxidation with O2 and H2 flow
• Hydrogen termination, turn-off H2 while keeping O2 flow
• Oxygen termination, turn-off O2 start process N2 flow
• Temperature ramp-down with process N2 flow
• Wafer boat pull-out with process N2 flow
• Idle with process N2 flow
• Next boats and repeat process
• Idle with purge N2 flow

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 94

 Rapid Thermal Oxidation

• For gate oxidation of deep sub-micron device

• Very thin oxide film, < 30 Å
• Need very good control of temperature
uniformity, WIW and WTW.
• RTO will be used to achieve the device
requirement.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 95

 RTP Process Diagram
Load Ramp RTO RTA Cool Unload
wafer up 1& 2 down wafer

O2 flow Temperature

HCl flow

N2 flow

Time
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 96
 High Pressure Oxidation

• Faster growth rate

• Reducing oxidation temperature:
– 1 amt. = –30 °C
• Higher dielectric strength

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 97

 High Pressure Oxidation

Stainless Steel Jacket

High Pressure
Inert Gas
High Pressure
Oxidant Gas

Quartz Process Chamber

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 98

 High Pressure Oxidation

Oxidation time to grow 10,000 Å wet oxide

Temperature Pressure Time

1 atmosphere 5 hours

1000 °C 5 atmosphere 1 hour

25 atmosphere 12 minutes

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 99

 High Pressure Oxidation

Oxidation temperature to grow 10,000 Å wet oxide in 5 hours

Time Pressure Temperature

1 atmosphere 1000 °C

5 hours 10 atmosphere 700 °C

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 100

 High Pressure Oxidation

• Complex system
• Safety issues

• Not widely used in IC production

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 101

 Oxide Measurement
• Thickness • Gate oxide
• Uniformity • Break down
voltage
• Color chart • C-V
• Ellipsometry characteristics
• Reflectometry

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 102

 Ellipsometry
Elliptically Polarized
Reflected Light
Linearly Polarized Incident Light

p
s

n1, k 1, t1
n2, k 2

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 103

 Reflectometry
Human eye or
photodetector
Incident light
1
2

t Dielectric film, n(λ)

Substrate
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 104
 C-V Test Configuration
Large Resistor
Capacitor
Meter

Oxide Aluminum

Silicon
Metal Platform

Heater Heater

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 105

 Summary of Oxidation
• Oxidation of silicon
• High stability and relatively easy to get.
• Application
– Isolation, masking, pad, barrier, gate, and etc.
• Wet and Dry
• More dry processes for advanced IC chips
• Rapid thermal oxidation and annealing for
ultra-thin gate oxide
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 106
 Diffusion

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 107

 Diffusion
• Most common physics phenomena
• Materials disperse from higher concentration
to lower concentration region
• Silicon dioxide as diffusion mask
• Was widely used for semiconductor doping
• “Diffusion Furnace” and “Diffusion Bay”

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 108

 Illustration of Diffusion Doping

Dopant

Silicon

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 109

 Illustration of Diffusion Doping

Dopant

Junction Depth
Silicon

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 110

 Definition of Junction depth
Junction Depth, xj

Background dopant concentration

Dopant Concentration

Distance from the wafer surface

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 111
 Diffusion

Masking Oxide Masking Oxide

p+ p+
N-Silicon N-Silicon

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 112

 Diffusion
• Replaced by ion implantation due to the less
process control
• Still being used in drive-in for well formation

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 113

 Thermal Budget
• Dopant atoms diffuse fast at high temperature
D = D0 exp (–EA/kT)
• Smaller device geometry, less room for dopant
thermal diffusion, less thermal budget
• Thermal budget determines the time and
temperature of the post-implantation thermal
processes

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 114

 Illustration of Thermal Budget

Gate

As S/D Implantation Over Thermal Budget

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 115

 Thermal Budget
1100 1000 900 800 T (°C)
1 µm 0.5 µm
2 µm
1000
Thermal Budget (sec)

0.25 µm Source: Chang

100 and Sze, ULSI
Technology
10

7 8 9 10
104/T (K)
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 116
 Diffusion Doping Process
• Both dopant concentration and junction depth
are related to temperature.
• No way to independently to control both factor
• Isotropic dopant profile
• Replaced by ion implantation after the mid-
1970s.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 117

 Diffusion Doping Process
• Silicon dioxide as hard mask
• Deposit dopant oxide
• Cap oxidation
– prevent dopant diffusion into gas phase
• Drive-in

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 118

 Diffusion Doping Process
• Oxidation, photolithography and oxide etch
• Pre-deposition:
B2H6 + 2 O2 → B2O3 + 3 H2O
• Cap oxidation:
2 B2O3 + 3 Si → 3 SiO2 + 4 B
2 H2O + Si → SiO2 + 2 H2
• Drive-in
– Boron diffuses into silicon substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 119

 Diffusion Doping Process
• Oxidation, photolithography and oxide etch
• Deposit dopant oxide:
4POCl3 + 3O2 → 2P2O5 + 3Cl2
• Cap oxidation
2P2O5 + 5Si → 5SiO2 + 4P
– Phosphorus concentrates on silicon surface
• Drive-in
– Phosphorus diffuses into silicon substrate
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 120
 Phosphorus Diffusion System

MFC Process Tube

MFC
MFC
MFC Wafers Burn Box

Control Valves
Process N2

Purge N 2
POCl 3

Regulator
Scrubbier
O2

Exhaust

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 121

 Wafer Clean

Si Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 122

 Oxidation

SiO2

Si Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 123

 Doped Area Patterning

PR
SiO2

Si Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 124

 Etch Silicon Dioxide

PR
SiO2

Si Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 125

 Strip Photoresist

SiO2

Si Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 126

 Wafer Clean

SiO2

Si Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 127

 Dopant Oxide Deposition

Deposited Dopant Oxide

SiO2

Si Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 128

 Cap Oxidation

SiO2

Si Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 129

 Phosphoric Oxide Deposition and
Cap Oxidation
Push Temp Temp. Dopant Deposition Cap N2 Ramp Pull
Ramp Stab. Oxide Vent Down

Temperature

N2 Flow

POCl3 Flow

O2 Flow

Wafer
Position

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 130

 Drive-in

SiO2

Si Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 131

Strip Oxide, Ready for Next Step

SiO2

Si Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 132

 Phosphorus Drive-in
Push Stab. Temp Temp. Drive-in Ramp Pull
Ramp Stab. Down

Temperature

N2 Flow

O2 Flow

Wafer
Position

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 133

 Limitations and Applications
• Diffusion is isotropic process and always
dope underneath masking oxide
• Can’t independently control junction depth
and dopant concentration
• Used for well implantation drive-in
• R&D for ultra shallow junction (USJ)
formation

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 134

Application of Diffusion: Drive-in
• Wells have the deepest junction depth
• Need very high ion implantation energy
• Cost of MeV ion implanters is very high
• Diffusion can help to drive dopant to the
desired junction depth while annealing

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 135

 Well Implantation and Drive-in

P+
Photoresist
N-Well
P-Epi

N-Well
P-Epi

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 136

Diffusion for Boron USJ Formation
• Small devices needs ultra shallow junction
• Boron is small and light, implanter energy
could be too high for it goes too deep
• Controlled thermal diffusion is used in
R&D for shallow junction formation

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 137

 Surface Clean

Silicide

Sidewall Spacer Sidewall Spacer

STI STI
Si Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 138

 BSG CVD

Silicide

Sidewall Spacer Sidewall Spacer

Boro-Silicate Glass

STI STI
Si Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 139

 RTP Dopant Drive-in

Silicide
Polysilicon

Gate Oxide
Boro-Silicate Glass

STI STI
Si Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 140

 Strip BSG

Polysilicon Silicide
Gate Oxide

STI STI
Si Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 141

 Doping Measurement
• Four-point probe

Rs = ρ/t

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 142

 Four-Point Probe Measurement

P1 P2 P3 P4

S1 S2 S3

Doped Region

Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 143

 Summary of Diffusion
• Physics of diffusion is well understood
• Diffusion was widely used in doping
processes in early IC manufacturing
• Replaced by ion implantation since the mid-
1970s

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 144

 Annealing and RTP Processes

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 145

 Post-implantation Annealing
• Energetic ions damage crystal structure
• Amorphous silicon has high resistivity
• Need external energy such as heat for atoms
to recover single crystal structure
• Only in single crystal structure dopants can
be activated

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 146

 Post-implantation Annealing
• Single crystal structure has lowest potential
energy
• Atoms tend to stop on lattice grid
• Heat can provide energy to atoms for fast
thermal motion
• Atoms will find and settle at the lattice grid
where has the lowest potential energy position
• Higher temperature, faster annealing
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 147
 Before Ion Implantation

Lattice Atoms
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 148
 After Ion Implantation

Lattice Atoms Dopant Atom

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 149
 Thermal Annealing

Lattice Atoms Dopant Atom

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 150
 Thermal Annealing

Lattice Atoms Dopant Atoms

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 151
 Annoy Annealing
• A thermal process in which different atoms
chemically bond with each other to form a
metal alloy.
• Widely used in silicide formation
• Self aligned silicide (salicide)
– Titanium silicide, TiSi2
– Cobalt silicide, CoSi2
• Furnace and RTP
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 152
 Silicide
• Much lower resistivity than polysilicon
• Used as gate and local interconnection
• Used as capacitor electrodes
• Improving device speed and reduce heat
generation
• TiSi2, WSi2 are the most commonly used
silicide
• CoSi2, MoSi2, and etc are also used
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 153
 Titanium Silicide Process
• Argon sputtering clean
• Titanium PVD
• RTP Anneal, ~700 °C
• Strip titanium, H2O2:H2SO2

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 154

 Titanium Silicide Process
Titanium

Polysilicon

STI n+ n+ USG p+ p+
Ti Deposition

Titanium Silicide

STI n+ n+ USG
USG p+ p+
Annealing
Sidewall Spacer Titanium Silicide

STI n+ n+ USG
USG p+ p+
Ti Strip
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 155
 Aluminum-silicon Alloy
• Form on silicon surface
• Prevent junction spiking due to silicon
dissolving in aluminum

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 156

 Junction Spike

Al Al Al
SiO2
p+ p+
n-type Silicon

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 157

 Reflow
• Flowed surface is smoother and flatter
• Easier for photolithography and metallization
• Higher temperature, better flow result
• Reflow time and temperature are determined by
the thermal budget
• Higher dopant concentration requires lower
flow temperature

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 158

 Illustration of BPSG Reflow
PSG
As SiO2
LOCOS
n+ n+ p+ p+
Deposit p+ p+ N-well
P-type substrate

PSG
After SiO2
LOCOS
n+ n+ p+ p+
Reflow p+ p+
N-well
P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 159

 Reflow
• Undoped silicate glass (USG) becomes soften
at very high temperature T > 1500 °C, will flow
due to the surface tension
• PSG and BPSG become soften at significant
lower temperature (< 1100 °C down to 850 °C)
• Phosphorus also can trap sodium
• PSG and BPSG is commonly used as pre-metal
dielectric (PMD)
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 160
 Reflow Process

• Wafer loading
• Temperature rump-up
• Temperature stabilization
• Reflow
• Temperature rump-down
• Wafer unloading

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 161

 Reflow Process

• Reflow usually used N2 ambient

• Sometimes H2O vapor is also used
• H2O helps to filly oxidize dopant atoms

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 162

 Reflow Process

• Smaller device, less thermal budget

• No enough thermal budget for reflow
for sub-0.25 µm devices
• PSG anneal (~750 °C) instead of reflow

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 163

 Summary of Anneal
• The most commonly used anneal processes are
post-implantation annealing, alloy annealing and
reflow
• Thermal anneal is required after ion implantation
for recover crystal structure and activation
dopant atoms
• Thermal anneal helps metal to react with silicon
to form silicides
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 164
 Summary of Anneal
• Metal anneal helps to form larger grain size and
reduces the resistivity
• PSG or BPSG reflow smoothens and flattens the
dielectric surface and helps photolithography
and metallization processes
• RTP becomes more commonly used in annealing
processes

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 165

 Summary of Anneal
• Advantages of RTP
– Much faster ramp rate (75 to 150 °C/sec)
– Higher temperature (up to 1200 °C)
– Faster process
– Minimize the dopant diffusion
– Better control of thermal budget
– Better wafer to wafer uniformity control

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 166

 High Temperature
Deposition Processes

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 167

 What is CVD
Chemical Vapor Deposition
• Gas(es) or vapor(s) chemically react on
substrate surface and form solid byproduct on
the surface as deposited thin film.
• Other byproducts are gases and leave the
surface.
• Widely used in IC processing for metal,
dielectric and silicon thin film deposition.
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 168
 High Temperature CVD

• Epitaxy
• Polysilicon
• Silicon Nitride

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 169

 Epitaxy

• Monocrystralline layer
• Epitaxy silicon
• Epitaxy silicon-germanium
• Epitaxy GaAs

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 170

 Epitaxy Silicon

• Provide high quality silicon substrate without

trace amount of oxygen and carbon.
• Required for bipolar devices.
• Needed for high performance CMOS devices.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 171

 Epitaxy Silicon
• High temperature (~1000 °C) processes.
• Silane (SiH4), DCS (SiH2Cl2) or TCS
(SiHCl3) as silicon source gases.
• Hydrogen as process gas and purge gas
• Arsine (AsH3), Phosphine (PH3), and
Diborane (B2H6) are used as dopant gases.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 172

 Epitaxy Silicon Deposition
• Silane process
Heat (1000 °C)

SiH4 → Si + H2
Silane Epi-Si Hydrogen

• DCS process
Heat (1150 °C)

SiH2Cl2 → Si + 2HCl
Silane Epi-Si Hydrochloride

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 173

 Epitaxy Silicon Doping
• N-type Dopant

Heat (1000 °C)

AsH3 → As + 3/2 H2
Arsine As Hydrogen

Heat (1000 °C)

PH3 → P + 3/2 H2
Arsine Phosphorus Hydrogen

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 174

 Epitaxy Silicon Doping
• P-type Dopant

Heat (1000 °C)

B2H6 → 2 B + 3 H2
Diborane Boron Hydrogen

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 175

 Epitaxy Silicon
• Usually deposited (“grown”) by wafer
manufacturer instead by IC fab.
• In fab epi process: special needs such as
usually dopant concentration and epi
thickness.
• Selective epi for raised source/drain.
• Single wafer epitaxy process.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 176

 Polysilicon
• High temperature stability.
• Reasonable good conductivity.
• Widely used for the gate and local
interconnection in MOS devices.
• Also widely used as the capacitor electrodes
in memory devices, especially DRAM.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 177

Polysilicon Applications in DRAM
Poly 5
Ta2O5 or BST
Poly 4

Poly 3
TiSi2

Sidewall
Spacer Poly 2
Poly 1
n+ n+ n+
p-Silicon

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 178

 Polysilicon
• High temperature (~700 °C) furnace
LPCVD processes.
• Silane (SiH4) or DCS (SiH2Cl2) as silicon
source gases.
• Nitrogen as purge gas
• Arsine (AsH3), Phosphine (PH3), and
Diborane (B2H6) are used as dopant gases.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 179

 Polysilicon Deposition
• Silane process
Heat (750 °C)

SiH4 → Si + H2
Silane Poly-Si Hydrogen

• DCS process
Heat (750 °C)

SiH2Cl2 → Si + 2HCl
Silane Poly-Si Hydrochlride

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 180

 Polysilicon Doping
• N-type Dopant

Heat (750 °C)

AsH3 → As + 3/2 H2
Arsine As Hydrogen

Heat (750 °C)

PH3 → P + 3/2 H2
Phosphine Phosphorus Hydrogen

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 181

 Polysilicon Doping
• P-type Dopant

Heat (750 °C)

B2H6 → 2 B + 3 H2
Diborane Boron Hydrogen

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 182

 Temperature Relationship of
Silane Process
• On single crystal silicon substrate
• Silane as source gases
• T > 900 °C deposit single crystal silicon
• 900 °C > T > 550 °C deposit polysilicon
• T < 550 °C deposit amorphous silicon

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 183

 Temperature and Crystal Structure
for Silane Processes

Grain
Boundary

Grain

T<550 °C 550 °C <T< 900 °C T > 900 °C

Amorphous Si Polysilicon Single Crystal Si

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 184

 Polysilicon LPCVD System
MFC Process Tube

MFC
MFC
Wafers Burn Box
Control Valves
Process N2

Purge N2

Regulator
SiH4

Scrubbier

Exhaust

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 185

 Polysilicon Deposition Process
• Idle with purge N2 flow • Set up process pressure (~250 mTorr)
• Idle with process N2 flow and with N 2 flow
• Wafer load into tower with • Turn-on SiH4 flow and turn-off N2,
process N2 flow start deposition
• Tower raises into process • Close gate valve, fill N2 and ramp-up
chamber (bell jar) with process N2 pressure to atmospheric pressure
flow • Tower lowed and wafer temperature
• Pump down chamber to base cooled down, with process N2 flow
pressure (< 2 mTorr) by turning- • Unload wafer with process N2 flow
off N2 flow • Idle with purge N2 flow
• Stabilize wafer temperature with
N2 flow and leak check

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 186

 Polysilicon Deposition Process
Load Raise Pump Temp. Pump Press. Si 3N4 Pump N2 Lower Unload
Wafer Tower Down Stab. Down Stab. Dep. Down Vent Tower Wafer
Chamber
Temperature

Wafer
Temperature
N2 Flow

Silane Flow

Chamber
Pressure

Wafer Tower
Position
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 187
 Polycide Deposition System
Polysilicon Deposition Chambers

WSi x WSi x
Deposition Deposition
Chamber Chamber

Wafer
Transfer Cooldown
Robot Chamber

Wafer Loading
Stations
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 188
 Polycide Deposition System
WSix Deposition Chamber RTA Chamber

Poly Si
Deposition
Chamber

Wafer Transfer
Cool down
Robot
Chamber
Wafer Loading
Stations
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 189
 Silicon Nitride

• Dense material
• Widely used as diffusion barrier layer and
passivation layer
• LPCVD (front-end) and PECVD (back-end)
• LPCVD nitride usually is deposited in a furnace

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 190

 Application of Silicon Nitride

• LOCOS formation as oxygen diffusion barrier

• STI formation as oxide CMP stop
• PMD barrier layer
• Etch stop layer

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 191

 LOCOS Process
Pad Oxide
Silicon nitride
P-type substrate

Pad oxidation, nitride deposition and patterning

Silicon nitride SiO2

p+ P-type substrate p+ Isolation Doping p
+

LOCOS oxidation
Bird’s Beak
SiO2
p+ P-type substrate p+ Isolation Doping p
+

Nitride and pad oxide strip

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 192
 STI Process
Nitride Pad Oxidation and LPCVD Nitride
Pad Oxide
Silicon

Etch Nitride and Pad Oxide

Nitride Photoresist Photoresist

Pad Oxide
Silicon

Nitride Strip Photoresist

Pad Oxide
Silicon

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 193

 STI Process
Nitride Trench Trench on Silicon
Pad Oxide
Silicon

Barrier oxidation, CVD USG Trench Fill

Nitride USG
Pad Oxide
Silicon

Barrier Oxide USG CMP; Nitride,

USG Pad Oxide Strip
Silicon
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 194
 Self-aligned Contact Etch Stop

Photoresist Photoresist

BPSG BPSG Sidewall

Oxide Spacer
Nitride TiSi2 Poly
Gate
n+ n+ n+
p-Silicon

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 195

 Nitride Breakthrough

Photoresist Photoresist

BPSG BPSG Sidewall

Oxide Spacer
Nitride TiSi2 Poly
Gate
n+ n+ n+
p-Silicon

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 196

 Strip Photoresist

BPSG BPSG Sidewall

Oxide Spacer
Nitride TiSi2 Poly
Gate
n+ n+ n+
p-Silicon

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 197

 Deposit Ti/TiN and Tungsten
Ti/TiN

BPSG W BPSG Sidewall

Oxide Spacer
Nitride TiSi2 Poly
Gate
n+ n+ n+
p-Silicon

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 198

 CMP Tungsten and TiN/Ti

BPSG W BPSG Sidewall

Oxide Spacer
Nitride TiSi2 Poly
Gate
n+ n+ n+
p-Silicon

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 199

 Silicon Nitride Applications
PD Silicon Nitride
PD Silicon Oxide

IMD Seal M2 FSG Cu

Nitride
FSG IMD Etch
Stop Nitride
M1 FSG Cu

FSG
PSG W Sidewall
PMD
Spacer
Barrier PSG W
Nitride
STI n+ n+ USG p+ p+
P-Well N-Well

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 200

 Silicon Nitride Deposition
• Silane or DCS as silicon source
• NH3 as nitrogen source
• N2 as purge gas

3 SiH2Cl2 + 4 NH3 → Si3N4 + 6 HCl + 6 H2

or
3 SiH4 + 4 NH3 → Si3N4 + 12 H2
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 201
 Silicon Nitride LPCVD System
Heaters
Process Chamber
Wafers

Tower
MFC
MFC

MFC
MFC

Pump Burn Box

Control Valves
Process N 2

NH 3

Purge N2
SiH2Cl 2

Scrubbier
Regulator

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm Exhaust

202
Nitride Deposition Process Sequence
Load Raise Pump Temp. Pump Press. Si 3N4 Pump N2 Lower Unload
Wafer Tower Down Stab. Down Stab. Dep. Down Vent Tower Wafer
Chamber
Temperature

Wafer
Temperature
N2 Flow

NH3 Flow

DCS Flow
Chamber
Pressure

Wafer Tower
Position
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 203
 Future Trends of HT-CVD

• More single wafer rapid thermal CVD

• Integrated processes in cluster tools

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 204

 Summary of Furnace Deposition
• Polysilicon and silicon nitride are the two
most commonly film deposited in high
temperature furnace
• Silane and DCS are the two most commonly
used silicon sources.
• Polysilicon can be doped while deposition
by flowing phosphine, arsine or diborane

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 205

 Rapid Thermal Process

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 206

 Rapid Thermal Processing (RTP)
• Mainly used for post-implantation rapid
thermal anneal (RTA) process.
• Fast temperature ramp-up, 100 to 150 °C/sec
compare with 15 °C/min in horizontal furnace.
• Reduce thermal budge and easier process
control.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 207

 Rapid Thermal Processing (RTP)
• Single wafer rapid thermal CVD (RTCVD)
chamber can be used to deposit polysilicon and
silicon nitride.
• RTCVD chamber can be integrated with other
process chamber in a cluster tool for in-line
process.
• Thin oxide layer (< 40 Å) is likely to be grown
with RTO for WTW uniformity control.
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 208
 Schematic of RTP Chamber

Wafer External Chamber

Process Quartz
Gases Chamber

Tungsten-Halogen Lamp IR Pyrometer

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 209

 Lamp Array

Top
Lamps
Bottom
Lamps
Wafer

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 210

 RTP Chamber

Photo courtesy of
Applied Materials, Inc

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 211

 Annealing and Dopant Diffusion
• At higher temperature >1100 °C anneal is
faster than diffusion
• Post implantation prefer high temperature
and high temperature ramp rate.
• Single wafer rapid thermal process tool has
been developed initially for this application

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 212

 Annealing and Dopant Diffusion
• Dopant atoms diffuse at high temperature
• Furnace has low temperature ramp rate
(~10 °C/min) due to large thermal capacity
• Furnace annealing is a long process which
causes more dopant diffusion
• Wafer at one end gets more anneal than
wafer at another end

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 213

 Anneal Rate and Diffusion Rate

Anneal Rate

Diffusion Rate

Temperature
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 214
 Dopant Diffusion After Anneal

Gate

RTA Furnace anneal

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 215

 Advantage of RTP over Furnace
• Much faster ramp rate (75 to 150 °C/sec)
• Higher temperature (up to 1200 °C)
• Faster process
• Minimize the dopant diffusion
• Better control of thermal budget
• Better wafer to wafer uniformity control

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 216

 RTP Temperature Change

Load Ramp Anneal Cool down Unload

wafer up wafer
Temperature

N2 Flow

Time
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 217
 Thermal Nitridization
• Titanium PVD
• Thermal nitridization with NH3

NH3 + Ti → TiN + 3/2 H2

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 218

 Titanium Nitridization
Ti

SiO2

Ti TiN

SiO2

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 219

 RTO Process
• Ultra thin silicon dioxide layer < 30Å
• Better WTW uniformity
• Better thermal budget control

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 220

 RTP Process Diagram
Load Ramp RTO RTA Cool Unload
wafer up 1& 2 down wafer

O2 flow Temperature

HCl flow

N2 flow

Time
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 221
 Future Tends
• Rapid thermal process (RTP)
• In-situ process monitoring
• Cluster tools

• Furnace will still be used

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 222

 RTCVD Chamber
Lamp Housing Heating Lamps
Wafer

Reactants

Reactants &
byproducts

Water Cooled Quartz

Chamber Wall Window IR Pyrometer

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 223

 Temperature of RTP & Furnace

Furnace
Temperature

RTP

Room
Temp.
Time

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 224

 Cluster Tool

RTO/RTP RTCVD
α-Si

HF Vapor Transfer Cool

Clean Chamber down

Loading Station Unloading Station

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 225
 Summary of RTP
• Fast
• Better process control
– Thermal budget
– Wafer to wafer uniformity
• Minimized dopant diffusion
• Cluster tool, easy process integration

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 226

 Summary of Thermal Process
• Oxidation, diffusion, annealing, and deposition
• Wet oxidation is faster, dry oxidation has better
film quality. Advanced fab: mainly dry oxidation.
• Diffusion doping with oxide mask, used in lab
• LPCVD polysilicon and front-end silicon nitride
• Annealing recovers crystal and activates dopants
• RTP: better control, faster and less diffusion
• Furnaces: high throughput and low cost, will
continue to be used in the future fabs
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 227
 Chapter 6
Photolithography
Hong Xiao, Ph. D.
[email protected]
www2.austin.cc.tx.us/HongXiao/Book.htm

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 1

 Objectives
• List the four components of the photoresist
• Describe the difference between +PR and −PR
• Describe a photolithography process sequence
• List four alignment and exposure systems
• Describe the wafer movement in a track-stepper
integrated system.
• Explain relationships of resolution and depth of
focus to wavelength and numerical aperture.
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 2
 Introduction
Photolithography
• Temporarily coat photoresist on wafer
• Transfers designed pattern to photoresist
• Most important process in IC fabrication
• 40 to 50% total wafer process time
• Determines the minimum feature size

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 3

 Applications of Photolithography
• Main application: IC patterning process
• Other applications: Printed electronic board,
nameplate, printer plate, and et al.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 4

 IC Fabrication

e-Beam or Photo
Ion Implant
Mask or
EDA PR Chip
Reticle Etch
Photolithography

EDA: Electronic Design Automation

PR: Photoresist

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 5

 IC Processing Flow
Materials IC Fab

Dielectric Test
Metallization CMP
deposition
Wafers

Thermal Etch Packaging

Implant
Processes PR strip PR strip
Masks

Photo- Final Test

lithography

IC Design

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 6

 Photolithography Requirements
• High Resolution
• High PR Sensitivity
• Precision Alignment
• Precise Process Parameters Control
• Low Defect Density

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 7

 Photoresist
• Photo sensitive material
• Temporarily coated on wafer surface
• Transfer design image on it through
exposure
• Very similar to the photo sensitive
coating on the film for camera

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 8

 Photoresist

Negative Photoresist Positive Photoresist

• Becomes insoluble • Becomes soluble
after exposure after exposure
• When developed, • When developed,
the unexposed parts the exposed parts
dissolved. dissolved
• Cheaper • Better resolution
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 9
Negative and Positive Photoresists
Photoresist
Substrate

UV light
Mask/reticle
Photoresist Exposure
Substrate
Negative
Photoresist
Substrate After
Positive Development
Photoresist
Substrate
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 10
 Photoresist Chemistry

• Start with printed circuit

• Adapted in 1950 in semiconductor industry
• Critical to the patterning process
• Negative and positive photoresist

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 11

 Photoresist Composition

• Polymer
• Solvents
• Sensitizers
• Additives

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 12

 Polymer
• Solid organic material
• Transfers designed pattern to wafer surface
• Changes solubility due to photochemical
reaction when exposed to UV light.
• Positive PR: from insoluble to soluble
• Negative PR: from soluble to insoluble

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 13

 Solvent

• Dissolves polymers into liquid

• Allow application of thin PR layers by spinning.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 14

 Sensitizers
• Controls and/or modifies photochemical
reaction of resist during exposure.
• Determines exposure time and intensity

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 15

 Additives
• Various added chemical to achieve desired
process results, such as dyes to reduce
reflection.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 16

 Negative Resist

• Most negative PR are polyisoprene type

• Exposed PR becomes cross-linked polymer
• Cross-linked polymer has higher chemical
etch resistance.
• Unexposed part will be dissolved in
development solution.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 17

 Negative Photoresist

Mask
Negative
Photoresist
Expose

Development

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 18

 Negative Photoresist
Disadvantages

• Polymer absorbs the development solvent

• Poor resolution due to PR swelling
• Environmental and safety issues due to the
main solvents xylene.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 19

 Comparison of Photoresists

− PR + PR
Film Film

Substrate Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 20

 Positive Photoresist
• Exposed part dissolve in developer solution
• Image the same that on the mask
• Higher resolution
• Commonly used in IC fabs

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 21

 Positive Photoresist
• Novolac resin polymer
• Acetate type solvents
• Sensitizer cross-linked within the resin
• Energy from the light dissociates the
sensitizer and breaks down the cross-links
• Resin becomes more soluble in base solution

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 22

 Question
• Positive photoresist can achieve much higher
resolution than negative photoresist, why
didn’t people use it before the 1980s?

• Positive photoresist is much more expensive

therefore negative photoresist was used until
it had to be replaced when the minimum
feature size was shrunk to smaller than 3 µm.
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 23
Chemically Amplified Photoresists
• Deep ultraviolet (DUV), λ ≤ 248 nm
• Light source: excimer lasers
• Light intensity is lower than I-line (365 nm)
from high-pressure mercury lamp
• Need different kind of photoresist

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 24

Chemically Amplified Photoresists
• Catalysis effect is used to increase the effective
sensitivity of the photoresist
• A photo-acid is created in PR when it exposes to
DUV light
• During PEB, head-induced acid diffusion causes
amplification in a catalytic reaction
• Acid removes protection groups
• Exposed part will be removed by developer

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 25

Chemically Amplified Photoresist

Before PEB After PEB

Exposed PR Exposed PR
Heat
+ H+ + + H+

Protecting Groups Protecting Groups

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 26

 Requirement of Photoresist
• High resolution
– Thinner PR film has higher the resolution
– Thinner PR film, the lower the etching and ion
implantation resistance
• High etch resistance
• Good adhesion
• Wider process latitude
– Higher tolerance to process condition change
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 27
 Photoresist Physical Properties
• Photoresist must be able to withstand
process conditions

• Coating, spinning, baking, developing.

• Etch resistance
• Ion implantation blocking

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 28

 Photoresist Performance Factor
• Resolution
• Adhesion
• Expose rate, Sensitivity and Exposure Source
• Process latitude
• Pinholes
• Particle and Contamination Levels
• Step Coverage
• Thermal Flow
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 29
 Resolution Capability
• The smallest opening or space that can
produced in a photoresist layer.
• Related to particular processes including expose
source and developing process.
• Thinner layer has better resolution.
• Etch and implantation barrier and pinhole-free
require thicker layer
• Positive resist has better resolution due to the
smaller size of polymer.
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 30
 Photoresist Characteristics
Summary
Parameter Negative Positive
Polymer Polyisoprene Novolac Resin
Photo-reaction Polymerization Photo-solubilization
Provide free radicals Changes film
Sensitizer for polymer cross-
to base soluble
link
Additives Dyes Dyes

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 31

 Photolithography Process

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 32

 Basic Steps of Photolithography
• Photoresist coating
• Alignment and exposure
• Development

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 33

 Basic Steps, Old Technology
• Wafer clean
• Dehydration bake
PR coating
• Spin coating primer and PR
• Soft bake
• Alignment and exposure
• Development
• Pattern inspection Development
• Hard bake
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 34
 Basic Steps, Advanced Technology
• Wafer clean
• Pre-bake and primer coating
PR coating
• Photoresist spin coating
Track- • Soft bake
stepper • Alignment and exposure
integrated
• Post exposure bake
system
• Development Development
• Hard bake
• Pattern inspection
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 35
 Figure 6.5

Previous
Process Clean Surface
PR coating Soft bake
preparation Alignment
&
Hard bake Development Exposure
PEB
Track system
Photo cell
Rejected
Strip
PR Inspection
Photo Bay
Approved

Etch Ion
Implant
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 36
 Wafer Clean
Gate Oxide

Polysilicon
STI USG
P-Well
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 37
 Pre-bake and Primer Vapor
Primer

Polysilicon
STI USG
P-Well
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 38
 Photoresist Coating
Primer

Photoresist
Polysilicon
STI USG
P-Well
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 39
 Soft Bake

Photoresist
Polysilicon
STI USG
P-Well
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 40
 Alignment and Exposure
Gate Mask

Photoresist
Polysilicon
STI USG
P-Well
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 41
 Alignment and Exposure
Gate Mask

Photoresist
Polysilicon
STI USG
P-Well
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 42
 Post Exposure Bake

Photoresist
Polysilicon
STI USG
P-Well
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 43
 Development

PR
Polysilicon
STI USG
P-Well
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 44
 Hard Bake

PR
Polysilicon
STI USG
P-Well
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 45
 Pattern Inspection

PR
Polysilicon
STI USG
P-Well
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 46
 Wafer Clean
• Remove contaminants
• Remove particulate
• Reduce pinholes and other defects
• Improve photoresist adhesion
• Basic steps
– Chemical clean
– Rinse
– Dry
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 47
Photolithography Process, Clean

• Older ways
– High-pressure nitrogen blow-off
– Rotating brush scrubber
– High-pressure water stream

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 48

 Wafer Clean Process

Chemical Clean Rinse Dry

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 49

Photolithography Process, Prebake

• Dehydration bake
• Remove moisture from wafer surface
• Promote adhesion between PR and surface
• Usually around 100 °C
• Integration with primer coating

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 50

 Photolithography Process, Primer

• Promotes adhesion of PR to wafer surface

• Wildly used: Hexamethyldisilazane (HMDS)
• HMDS vapor coating prior to PR spin coating
• Usually performed in-situ with pre-bake
• Chill plate to cool down wafer before PR coating

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 51

Pre-bake and Primer Vapor Coating

Prep Chamber Primer Layer

Wafer
Wafer HMDS
Vapor

Hot Plate Hot Plate

Dehydration Bake Primer Vapor Coating

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 52

 Wafer Cooling
• Wafer need to cool down
• Water-cooled chill plate
• Temperature can affect PR viscosity
– Affect PR spin coating thickness

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 53

 Spin Coating
• Wafer sit on a vacuum chuck
• Rotate at high speed
• Liquid photoresist applied at center of
wafer
• Photoresist spread by centrifugal force
• Evenly coat on wafer surface

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 54

 Viscosity
• Fluids stick on the solid surface
• Affect PR thickness in spin coating
• Related to PR type and temperature
• Need high spin rate for uniform coating

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 55

Relationship of Photoresist Thickness
to Spin Rate and Viscosity
3.5
100 cst
3.0
50 cst
2.5
Thickness (mm)

2.0
27 cst
20 cst
1.5

1.0 10 cst

5 cst
0.5

0
2k 3k 4k 5k 6k 7k

Spin Rate (rpm)

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 56
 Dynamic Spin Rate
nipS

Time
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 57
 PR Spin Coater

Ÿ Photoresist spread on spinning wafer surface

Ÿ Wafer held on a vacuum chuck
Ÿ Slow spin ~ 500 rpm
Ÿ Ramp up to ~ 3000 - 7000 rpm

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 58

 Spin Coater
• Automatic wafer loading system from
robot of track system
• Vacuum chuck to hold wafer
• Resist containment and drain
• Exhaust features
• Controllable spin motor
• Dispenser and dispenser pump
• Edge bead removal
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 59
 Photoresist Spin Coater
PR
Wafer

EBR
Water
Sleeve
Chuck
Drain Exhaust
Vacuum

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 60

 Photoresist Applying

PR dispenser
nozzle
Wafer

Chuck
Spindle

To vacuum
pump
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 61
 Photoresist Suck Back

PR dispenser
PR suck back nozzle
Wafer

Chuck
Spindle

To vacuum
pump
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 62
 Photoresist Spin Coating

PR dispenser
PR suck back nozzle
Wafer

Chuck
Spindle

To vacuum
pump
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 63
 Photoresist Spin Coating

PR dispenser
PR suck back nozzle
Wafer

Chuck
Spindle

To vacuum
pump
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 64
 Photoresist Spin Coating

PR dispenser
PR suck back nozzle
Wafer

Chuck
Spindle

To vacuum
pump
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 65
 Photoresist Spin Coating

PR dispenser
PR suck back nozzle
Wafer

Chuck
Spindle

To vacuum
pump
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 66
 Photoresist Spin Coating

PR dispenser
PR suck back nozzle
Wafer

Chuck
Spindle

To vacuum
pump
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 67
 Photoresist Spin Coating

PR dispenser
PR suck back nozzle
Wafer

Chuck
Spindle

To vacuum
pump
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 68
 Photoresist Spin Coating

PR dispenser
PR suck back nozzle
Wafer

Chuck
Spindle

To vacuum
pump
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 69
 Photoresist Spin Coating

PR dispenser
PR suck back nozzle
Wafer

Chuck
Spindle

To vacuum
pump
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 70
 Photoresist Spin Coating

PR dispenser
PR suck back nozzle
Wafer

Chuck
Spindle

To vacuum
pump
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 71
 Edge Bead Removal (EBR)

• PR spread to the edges and backside

• PR could flakes off during mechanical
handling and causes particles
• Front and back chemical EBR
• Front optical EBR

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 72

 Edge Bead Removal

Solvent
Wafer

Chuck
Spindle

To vacuum
pump
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 73
 Edge Bead Removal

Solvent
Wafer

Chuck
Spindle

To vacuum
pump
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 74
 Ready For Soft Bake

Wafer

Chuck
Spindle

To vacuum
pump
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 75
 Optical Edge Bead Removal
• After alignment and exposure
• Wafer edge expose (WEE)
• Exposed photoresist at edge dissolves
during development

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 76

 Optical Edge Bead Removal

Photoresist

Wafer

Chuck
Spindle

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 77

 Developer Spin Off

Edge PR removed Patterned photoresist

Wafer

Chuck
Spindle

To vacuum
pump

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 78

 Soft Bake
• Evaporating most of solvents in PR
• Solvents help to make a thin PR but absorb
radiation and affect adhesion
• Soft baking time and temperature are determined
by the matrix evaluations
• Over bake: polymerized, less photo-sensitivity
• Under bake: affect adhesion and exposure

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 79

 Soft Bake
• Hot plates
• Convection oven
• Infrared oven
• Microwave oven

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 80

 Baking Systems

Wafer MW Source
Heated N 2 Photoresist
Heater

Chuck
Wafers

Vacuum Wafer
Heater Vacuum

Hot plate Convection oven Microwave oven

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 81

 Hot Plates

• Widely used in the

industry Wafer

• Back side heating, no Heater

surface “crust”
• In-line track system

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 82

 Wafer Cooling
• Need to cool down to ambient temperature
• Water-cooled chill plate
• Silicon thermal expansion rate: 2.5×10−6/°C
• For 8 inch (200 mm) wafer, 1 °C change
causes 0.5 µm difference in diameter

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 83

 Alignment and Exposure
• Most critical process for IC fabrication
• Most expensive tool (stepper) in an IC fab.
• Most challenging technology
• Determines the minimum feature size
• Currently 0.18 µm and pushing to 0.13 µm

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 84

 Alignment and Exposure Tools

• Contact printer
• Proximity printer
• Projection printer
• Stepper

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 85

 Contact Printer
• Simple equipment
• Use before mid-70s
• Resolution: capable for sub-micron
• Direct mask-wafer contact, limited mask
lifetime
• Particles

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 86

 Contact Printer
Light Source

Lenses

Mask

Photoresist
Wafer

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 87

 Contact Printing

UV Light Mask

PR

N-Silicon
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 88
 Proximity Printer
• ~ 10 µm from wafer surface
• No direct contact
• Longer mask lifetime
• Resolution: > 3 µm

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 89

 Proximity Printer
Light Source

Lenses

Mask

~10 µm
Photoresist
Wafer

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 90

 Proximity Printing

~10 µm UV Light Mask

PR

N-Silicon
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 91
 Projection Printer

• Works like an overhead projector

• Mask to wafer, 1:1
• Resolution to about 1 µm

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 92

 Projection System

Light Source

Lenses

Mask

Photoresist
Wafer

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 93

 Scanning Projection System
Light Source Slit

Lens

Synchronized Mask
mask and wafer
movement Lens

Photoresist

Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 94
 Stepper
• Most popular used photolithography tool in
the advanced IC fabs
• Reduction of image gives high resolution
• 0.25 µm and beyond
• Very expensive

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 95

 Q&A
• Why does the 5:1 shrink ratio is more
popular than the 10:1 shrink ratio?

• 10:1 image shrink has better resolution than

5:1 image shrink. However, it only exposes
a quarter of the area, which means total
exposure time will be quadrupled.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 96

Step-&-Repeat Alignment/Exposure
Light
Source

Projection
Lens

Reticle

Projection
Lens

Wafer
Wafer Stage

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 97

 Step&Repeat Alignment System
Light Source Reference Mark

Alignment Laser
Reticle Stage
Reticle

Interferometer
Laser Projection Lens

X
Interferometer
Mirror Set
Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 98
Wafer Stage
 Exposure Light Source
• Short wavelength
• High intensity
• Stable

• High-pressure mercury lamp

• Excimer laser

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 99

 Spectrum of the Mercury Lamp

I-line G-line
(365) (436)
Intensity (a.u)

H-line
(405)

Deep UV
(<260)

300 400 500 600

Wavelength (nm)

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 100

 Photolithography Light Sources
Name Wavelength (nm) Application feature
size (µ m)
G-line 436 0.50
Mercury Lamp H-line 405
I-line 365 0.35 to 0.25
XeF 351
XeCl 308
Excimer Laser KrF (DUV) 248 0.25 to 0.15
ArF 193 0.18 to 0.13
Fluorine Laser F2 157 0.13 to 0.1

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 101

 Exposure Control
• Exposure controlled by production of light
intensity and exposure time
• Very similar to the exposure of a camera
• Intensity controlled by electrical power
• Adjustable light intensity
• Routine light intensity calibration

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 102

 Question
• Someone did a routine illuminator intensity
calibration with a reticle still on the stage.
What kind of problem will it induce?

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 103

 Answer
• Since the reticle can block some light,
photodetector on wafer stage will receive
less photons than it should receive.
Therefore, it will give a lower reading. To
calibrate, the applied power will be
increased and the light intensity will be
higher than it should be. It could cause
overexposure and CD loss.
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 104
 Standing Wave Effect

•Interference of the incident and reflection lights

•Periodically overexposure and underexposure
•Affects photolithography resolution.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 105

 Standing Wave Intensity
Constructive Destructive
Average Interference, Interference,
Intensity Overexpose Underexpose
Light Intensity

Surface Surface of
the of PR λ/nPR the substrate
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 106
Standing Wave Effect on Photoresist

λ/nPR
Photoresist
Substrate

Overexposure
Underexposure
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 107
 Post Exposure Bake
• Photoresist glass transition temperature Tg
• Baking temperature higher than Tg
• Thermal movement of photoresist molecules
• Rearrangement of the overexposed and
underexposed PR molecules
• Average out standing wave effect,
• Smooth PR sidewall and improve resolution
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 108
 Post Exposure Bake
• For DUV chemical amplified photoresist, PEB
provides the heat needed for acid diffusion
and amplification.
• After the PEB process, the images of the
exposed areas appear on the photoresist, due
to the significant chemical change after the
acid amplification

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 109

 Post Exposure Bake
• PEB normally uses hot plate at 110 to 130 °C
for about 1 minute.
• For the same kind of PR, PEB usually requires
a higher temperature than soft bake.
• Insufficient PEB will not completely eliminate
the standing wave pattern,
• Over-baking will cause polymerization and
affects photoresist development
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 110
PEB Minimizes Standing Wave Effect

Photoresist

Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 111

 Wafer Cooling
• After PEB the wafer is put on a chill plate
to cool down to the ambient temperature
before sent to the development process
• High temperature can accelerate chemical
reaction and cause over-development,
• PR CD loss

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 112

 Development
• Developer solvent dissolves the softened
part of photoresist
• Transfer the pattern from mask or reticle to
photoresist
• Three basic steps:
– Development
– Rinse
– Dry
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 113
 Development: Immersion

Develop Rinse Spin Dry

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 114
 Developer Solution
• +PR normally uses weak base solution
• The most commonly used one is the
tetramethyl ammonium hydride, or TMAH
((CH3)4NOH).

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 115

 Development
Mask

PR PR
Film Film
Substrate Substrate
PR Coating Exposure

PR PR
Film Film
Substrate Substrate
Etching Development
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 116
 Development Profiles

PR PR

Substrate Substrate

Normal Development Incomplete Development

PR PR

Substrate Substrate

Under Development Over Development

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 117
 Developer Solutions

Positive PR Negative PR
Developer TMAH Xylene

Rinse DI Water n-Butylacetate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 118

 Schematic of a Spin Developer
DI water Developer
Wafer

Water
sleeve
Chuck
Drain
Vacuum

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 119

Optical Edge Bead Removal Exposure
Light source
Light beam Photoresist

Wafer

Chuck
Spindle

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 120

Optical Edge Bead Removal Exposure
Light source
Light beam Photoresist

Wafer

Exposed Chuck
Photoresist Spindle

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 121

 Applying Development Solution

Exposed Development solution

Photoresist dispenser nozzle
Wafer

Chuck
Spindle

To vacuum
pump
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 122
 Applying Development Solution

Exposed
Photoresist
Wafer

Chuck
Spindle

To vacuum
pump
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 123
 Development Solution Spin Off

Edge PR Patterned
removed photoresist

Wafer

Chuck
Spindle

To vacuum
pump
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 124
 DI Water Rinse

DI water
dispenser
nozzle
Wafer

Chuck
Spindle

To vacuum
pump
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 125
 Spin Dry

Wafer

Chuck
Spindle

To vacuum
pump
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 126
 Ready For Next Step

Wafer

Chuck
Spindle

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 127

 Development
Developer
puddle

Wafer

Form puddle Spin spray Spin rinse

and dry
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 128
 Hard Bake
• Evaporating all solvents in PR
• Improving etch and implantation resistance
• Improve PR adhesion with surface
• Polymerize and stabilize photoresist
• PR flow to fill pinhole

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 129

 PR Pinhole Fill by Thermal Flow

Pinhole

PR PR

Substrate Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 130

 Hard Bake
• Hot plate is commonly used
• Can be performed in a oven after inspection
• Hard bake temperature: 100 to 130 °C
• Baking time is about 1 to 2 minutes
• Hard bake temperature normally is higher than
the soft bake temperature for the same kind of
photoresist
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 131
 Hard Bake
• Under-bake
– Photoresist is not filly polymerized
– High photoresist etch rate
– Poor adhesion
• Over-baking
– PR flow and bad resolution

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 132

 Photoresist Flow
• Over baking can causes too much PR flow,
which affects photolithography resolution.

PR PR
Substrate Substrate
Normal Baking Over Baking

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 133

 Q&A
• If wrong PR is refilled in the spinner, what
could be the consequence?
• Each PR has its own sensitivity & viscosity,
require its own spin rates, ramp rates, and
time, baking times and temperature,
exposure intensities and times, developer
solutions and development conditions.
• Pattern transfer will fail.
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 134
 Pattern Inspection
• Fail inspection, stripped PR and rework
– Photoresist pattern is temporary
– Etch or ion implantation pattern is permanent.
• Photolithography process can rework
• Can’t rework after etch or implantation.
• Scanning electron microscope (SEM)
• Optical microscope
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 135
 Q&A
• Why can’t optical microscope be used for
the 0.25 µm feature inspection?

• Because the feature size (0.25 µm = 2500

Å) is smaller than the wavelength of the
visible light, which is from 3900 Å (violet)
to 7500 Å (red)..

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 136

 Electron Microscope

Electron Beam

More secondary
electrons on the
Less secondary
corners
electrons on the PR
sidewall and plate
surface Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 137

 Pattern Inspection
• Overlay or alignment
– run-out, run-in, reticle rotation, wafer rotation,
misplacement in X-direction, and misplacement
in Y-direction
• Critical dimension (CD)
• Surface irregularities such as scratches, pin
holes, stains, contamination, etc.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 138

 Misalignment Cases
Run-out

Run-in

θ Reticle rotation
Wafer rotation

Misplacement in x-direction

Misplacement in y-direction

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 139

 Critical Dimension
PR PR PR
Substrate Substrate Substrate

Good CD CD Loss Sloped Edge

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 140

 Pattern Inspection
• If the wafers pass the inspection, they will
move out of photo bay and go to the next
process step

• Either etch or ion implantation

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 141

Track-Stepper System or Photo Cell
• Integrated process system of photoresist
coating, exposure and development
• Center track robot
• Higher throughput
• Improves process yield

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 142

 Wafer In
Hot Plate Spin Station

Stepper

Track Robot

Developer Hot Plate Track

dispenser
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 143
Pre-bake and Primer Vapor Coating
Hot Plate Spin Station

Stepper

Track Robot

Developer Hot Plate Track

dispenser
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 144
 Photoresist Spin Coating
Hot Plate Spin Station

Stepper

Track Robot

Developer Hot Plate Track

dispenser
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 145
 Soft Bake
Hot Plate Spin Station

Stepper

Track Robot

Developer Hot Plate Track

dispenser
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 146
 Alignment and Exposure
Hot Plate Spin Station

Stepper

Track Robot

Developer Hot Plate Track

dispenser
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 147
 Post Exposure Bake (PEB)
Hot Plate Spin Station

Stepper

Track Robot

Developer Hot Plate Track

dispenser
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 148
 Development
Hot Plate Spin Station

Stepper

Track Robot

Developer Hot Plate Track

dispenser
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 149
 Hard Bake
Hot Plate Spin Station

Stepper

Track Robot

Developer Hot Plate Track

dispenser
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 150
 Wafer out
Hot Plate Spin Station

Stepper

Track Robot

Developer Hot Plate Track

dispenser
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 151
 Schematic of a Photo Cell
Prep
Chamber Spin Coater Chill Plates
Wafer

Center Track Robot Stepper

Wafer
Chill Plates Developer Hot Plates Movement
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 152
 Stacked Track System

• Smaller footprint
• Lower cost of ownership (COO)

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 153

 Stacked Track System

Developers
Hot Plates
Chill Plates

Spin
Coaters
Prep Chamber

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 154

 Future Trends

• Smaller feature size

• Higher resolution
• Reducing wavelength
• Phase-shift mask

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 155

 Optical Lithography

• Optics
• Light diffraction
• Resolution
• Depth of focus (DOF)

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 156

 Diffraction
• Basic property of optics
• Light is a wave
• Wave diffracts
• Diffraction affects resolution

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 157

 Light Diffraction Without Lens

Diffracted light Mask

Intensity of the
projected light

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 158

 Diffraction Reduction
• Short wavelength waves have less diffraction
• Optical lens can collect diffracted light and
enhance the image

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 159

 Light Diffraction With Lens

Strayed
refracted light D Mask

Lens ro
Diffracted light
collected by the Less diffraction after
lens focused by the lens

Ideal light
Intensity pattern

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 160

 Numerical Aperture
• NA is the ability of a lens to collect diffracted
light
• NA = 2 r0 / D
– r0 : radius of the lens
– D = the distance of the object from the lens
• Lens with larger NA can capture higher order
of diffracted light and generate sharper image.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 161

 Resolution
• The achievable, repeatable minimum
feature size
• Determined by the wavelength of the light
and the numerical aperture of the system.
The resolution can be expressed as

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 162

 Resolution
K1λ
R=
NA

• K1 is the system constant, λ is the

wavelength of the light, NA = 2 ro/D, is the
numerical aperture
• NA: capability of lens to collect diffraction
light
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 163
 Exercise 1, K1 = 0.6

K 1λ
R=
NA
λ ΝΑ R
G-line 436 nm 0.60 ___ µm
I-line 365 nm 0.60 ___ µm
DUV 248 nm 0.60 ___ µm
193 nm 0.60 ___ µm
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 164
 To Improve Resolution
• Increase NA
– Larger lens, could be too expensive and unpractical
– Reduce DOF and cause fabrication difficulties
• Reduce wavelength
– Need develop light source, PR and equipment
– Limitation for reducing wavelength
– UV to DUV, to EUV, and to X-Ray
• Reduce K1
– Phase shift mask
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 165
 Wavelength and Frequency of
Electromagnetic Wave
Visible
RF MW IR UV X-ray γ-ray

4 6 8 10 12 14 16 18 20
10 10 10 10 10 10 10 10 10 f (Hz)

10−2 10−4 10−6 10−8 10−10 10−12 λ (meter)

4 2 0
10 10 10

RF: Radio frequency; MW: Microwave; IR: infrared; and UV: ultraviolet

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 166

 Depth of focus
• The range that light is in focus and can
achieve good resolution of projected image
• Depth of focus can be expressed as:

K 2λ
DOF = 2
2 ( NA )

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 167

 Depth of Focus

K2 λ
DOF = Focus
2 ( NA ) 2

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 168

 Exercise 2, K2 = 0.6

K 2λ
DOF =
2 ( NA ) 2
λ ΝΑ DOF
G-line 436 nm 0.60 ___ µm
I-line 365 nm 0.60 ___ µm
DUV 248 nm 0.60 ___ µm
193 nm 0.60 ___ µm
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 169
 Depth of Focus
• Smaller numerical aperture, larger DOF
– Disposable cameras with very small lenses
– Almost everything is in focus
– Bad resolution
• Prefer reduce wavelength than increase NA
to improve resolution
• High resolution, small DOF
• Focus at the middle of PR layer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 170
 Focus on the Mid-Plain to
Optimize the Resolution

Center of focus Depth of focus

Photoresist
Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 171

 Surface Planarization Requirement

• Higher resolution requires

– Shorter λ
– Larger NA.
• Both reduces DOF
• Wafer surface must be highly planarized.
• CMP is required for 0.25 µm feature patterning.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 172

 I-line and DUV
• Mercury i-line, 365 nm
– Commonly used in 0.35 µm lithography
• DUV KrF excimer laser, 248 nm
– 0.25 µm, 0.18 µm and 0.13 µm lithography
• ArF excimer laser,193 nm
– Application: < 0.13 µm
• F2 excimer laser 157 nm
– Still in R&D, < 0.10 µm application
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 173
 I-line and DUV
• SiO2 strongly absorbs UV when λ < 180 nm
• Silica lenses and masks can’t be used
• 157 nm F2 laser photolithography
– Fused silica with low OH concentration, fluorine
doped silica, and calcium fluoride (CaF2),
– With phase-shift mask, even 0.035 µm is possible
• Further delay next generation lithography

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 174

Next Generation Lithography (NGL)
• Extreme UV (EUV) lithography
• X-Ray lithography
• Electron beam (E-beam) lithography

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 175

 Future Trends
Photolithography
1.6
1.5
1.4
Maybe photo-
1.2
Feature Size (mm)

1.0 lithography
1
0.8 0.8 Next Generation
0.6 0.5 Lithography
0.35
0.4 0.25
0.18 0.13
0.2 0.10 0.07
0
84 88 90 93 95 98 01 04 07 10 14
Year

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 176

 Phase Shift Mask

Pellicle Chrome pattern Phase shift coating

nf Quartz substrate

d(nf − 1) = λ/2
nf : Refractive index of phase shift coating
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 177
 Phase Shift Mask
Pellicle Chrome pattern Phase-shifting etch

d ng
Quartz substrate

d(ng − 1) = λ/2
ng: refractive index of the quartz substrate
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 178
 Phase Shift Mask Patterning
Normal Mask Phase Shift Mask

Constructive Phase shift

Interference coating Total Light
Intensity
Total Light
Intensity Destructive
Interference

PR PR
Substrate Substrate
Final Pattern Final Pattern

PR PR
Substrate Substrate
Designed Pattern Designed Pattern
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 179
 Future Trends
• Even shorter wavelength
– 193 nm
– 157 nm
• Silicate glass absorbs UV light when λ < 180 nm
• CaF2 optical system
• Next generation lithography (NGL)
– Extreme UV (EVU)
– Electron Beam
– X-ray (?)

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 180

 EUV
• λ = 10 to 14 nm
• Higher resolution
• Mirror based
• Projected application ~ 2010
• 0.1 µm and beyond

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 181

 EUV Lithography

Mask
Wafer
Mirror 2 Mirror 1

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 182

 X-ray lithography
• Similar to proximity printer
• Difficult to find pure X-ray source
• Challenge on mask making
• Unlikely will be used in production

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 183

 X-ray Printing

Beryllium X-ray

Gold

Photoresist

Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 184

 Optical Mask and X-ray Mask

Glass Beryllium
Gold
Chromium

Photo Mask X-ray Mask

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 185

 E-Beam
• Used for making mask and reticles
• Smallest geometry achieved: 0.014 µm
• Direct print possible, no mask is required
– Low throughput
• Scattering exposure system (SCALPEL)
looks promising
– Tool development
– Reticle making
– Resist development
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 186
Electron Beam Lithography System
Electron Gun

Lens
Blanking Plate

Lens

Stigmator
Deflection
Coils
Lens

Wafer

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 187

 SCALPEL

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 188

 Ion Beam Lithography
• Can achieve higher resolution
– Direct writing and projection resist exposing
– Direct ion implantation and ion beam sputtering
patterned etch, save some process steps
• Serial writing, low throughput
• Unlikely will be used in the mass production
• Mask and reticle repairing
• IC device defect detection and repairing
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 189
 Safety
• Chemical
• Mechanical
• Electrical
• Radiation

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 190

 Chemical Safety
• Wet clean
– Sulfuric acid (H2SO4): corrosive
– Hydrogen peroxide (H2O2): strong oxidizer
• Xylene (solvent and developer of −PR):
flammable and explosive
• HMDS (primer): flammable and explosive
• TMAH (+PR development solution): poisonous
and corrosive
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 191
 Chemical Safety

• Mercury (Hg, UV lamp) vapor

– highly toxic;
• Chlorine (Cl2, excimer laser )
– toxic and corrosive
• Fluorine (F2, excimer laser)
– toxic and corrosive

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 192

 Mechanical Safety

• Moving Parts
• Hot surface
• High pressure lump

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 193

 Electrical Safety

• High voltage electric power supply

• Power off
• Ground static charges
• Tag-out and lock-out

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 194

 Radiation Safety
• UV light can break chemical bonds
• Organic molecules have long-chain structure
• More vulnerable to the UV damage
• UV light can be used to kill bacteria for
sterilization
• Can cause eye injury if direct look at UV source
• UV protection goggle sometimes is required.
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 195
 Summary
• Photolithography: temporary patterning process
• Most critical process steps in IC processing
• Requirement: high resolution, low defect density
• Photoresist, positive and negative
• Process steps: Pre-bake and Primer coating, PR
spin coating, soft bake, exposure, PEB,
development, hard bake, and inspection
• NGL: EUV and e-beam lithography
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 196
 Chapter 7
Plasma Basic
Hong Xiao, Ph. D.
[email protected]
www2.austin.cc.tx.us/HongXiao/Book.htm

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 1

 Objectives
• List at least three IC processes using plasma
• Name three important collisions in plasma
• Describe mean free path
• Explain how plasma enhance etch and CVD
processes
• Name two high density plasma sources

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 2

 Topics of Discussion

• What is plasma?
• Why use plasma?
• Ion bombardment
• Application of plasma process

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 3

 Applications of Plasma

• CVD
• Etch
• PVD
• Ion Implantation
• Photoresist strip
• Process chamber dry clean

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 4

 What Is Plasma
• A plasma is a ionized gas with equal numbers
of positive and negative charges.

• A more precise definition: a plasma is a quasi-

neutral gas of charged and neutral particles
which exhibits collective behavior.

• Examples: Sun, flame, neon light, etc.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 5

 Components of Plasma
• A plasma consists of neutral atoms or
molecules, negative charges (electrons) and
positive charges (ions)

• Quasi-neutral: ni ≈ ne

• Ionization rate: η ≈ ne/(ne + nn)

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 6

 Ionization Rate
• Ionization rate is mainly determined by
electron energy in plasma
• In most plasma processing chambers, the
ionization rate is less than 0.001%.
• The ionization rate of high density plasma
(HDP) source is much higher, about 1%.
• Ionization rate in the core of sun is ~100%.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 7

 Neutral Gas Density
• Idea gas
– 1 mole = 22.4 Litter = 2.24×104 cm3
– 1 mole = 6.62 ×1023 molecules
• At 1 atm, gas density is 2.96×1019 cm−3
• At 1 Torr, gas density is 3.89×1016 cm−3
• At 1 mTorr, gas density is 3.89×1013 cm−3
• RF plasma has very low ionization rate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 8

 Parallel Plate Plasma System
RF power

Dark
Electrodes Plasma spaces or
sheath
layers

To Vacuum Pump

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 9

 Generation of a Plasma
• External power is needed
• Radio frequency (RF) power is the most
commonly used power source
• Vacuum system is required to generate a
stable RF plasma

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 10

 Ionization

• Electron collides with neutral atom or molecule

• Knock out one of orbital electron

e+A A+ + 2 e

• Ionization collisions generate electrons and ions

• It sustains the stable plasma

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 11

 Illustration of Ionization

Nucleus Nucleus

Free Orbital Free

Electron Electron Electrons

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 12

 Excitation-Relaxation
e+A A* + e

A* A + hν (Photos)

• Different atoms or molecules have difference

frequencies, that is why different gases have
different glow colors.

• The change of the glow colors is used for etch

and chamber clean process endpoint.
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 13
 Excitation Collision
Impact
Excited electron
Grounded
electron
electron

Impact
electron
Nucleus Nucleus

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 14

 Relaxation
h: Planck Constant
ν: Frequency of Light
hν
Excited State
hν

Ground State
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 15
 Dissociation
• Electron collides with a molecule, it can
break the chemical bond and generate free
radicals:
e + AB A+B+ e
• Free radicals have at least one unpaired
electron and are chemically very reactive.
• Increasing chemical reaction rate
• Very important for both etch and CVD.
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 16
 Dissociation

e-
Free Radicals
B
A B A
Molecule e-

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 17

 Plasma Etch
• CF4 is used in plasma to generate fluorine
free radical (F) for oxide etch
e− + CF4 → CF3 + F + e−
4F + SiO2 → SiF4 + 2O
• Enhanced etch chemistry

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 18

 Plasma Enhanced CVD
• PECVD with SiH4 and NO2 (laughing gas)
e− + SiH4 → SiH2 + 2H + e−
e− + N2O → N2 + O + e−
SiH2 + 3O → SiO2 + H2O
• Plasma enhanced chemical reaction
• PECVD can achieve high deposition rate at
relatively lower temperature
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 19
 Q&A
• Why are dissociation not important in the
aluminum and copper PVD processes?

• Aluminum and copper sputtering processes

only use argon. Argon is a noble gas, which
exist in the form of atoms instead of
molecules. Thus there is no dissociation
process in argon plasma
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 20
 Q&A
• Is there any dissociation collision in PVD
processes?
• Yes. In TiN deposition process, both Ar and
N2 are used. In plasma, N2 is dissociated to
generate free radical N, which reacts with
Ti target to from TiN on the surface. Ar+
ions sputter TiN molecules from the surface
and deposit them on wafer surface.
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 21
 Table 7.1 Silane Dissociation
Collisions Byproducts Energy of Formation

e- + SiH4 SiH2 + H2 + e- 2.2 eV

SiH3 + H + e- 4.0 eV
Si + 2 H2 + e- 4.2 eV
SiH + H2 + H + e- 5.7 eV
SiH2* + 2H + e- 8.9 eV
Si* + 2H2 + e- 9.5 eV
SiH2+ + H2 + 2 e- 11.9 eV
SiH3+ + H + 2 e- 12.32 eV
Si+ + 2H2 + 2 e- 13.6 eV
+ -
Hong Xiao, Ph. D. SiH + H 2 + H + 2 e
www2.austin.cc.tx.us/HongXiao/Book.htm 15.3 eV 22
 Q&A
• Which one of collisions in Table 7.1 is most
likely to happen? Why?

• The one that requires the least energy is the

one most likely to happen.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 23

 Mean Free Path (MFP)
• The average distance a particle can travel
before colliding with another particle.
1
λ =
nσ
• n is the density of the particle
• σ is the collision cross-section of the particle

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 24

 MFP Illustration

Large Large
particle particle

Small Small
particle particle

(a) (b)

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 25

 Mean Free Path (MFP)
• Effect of pressure:

λ∝ 1
p

• Higher pressure, shorter MFP

• Lower pressure, longer MFP

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 26

 Q&A
• Why does one need a vacuum chamber to
generate a stable plasma?
• At atmospheric pressure (760 Torr), MFP of an
electron is very short. Electrons are hard to get
enough energy to ionize gases molecules.
• Extremely strong electric field can create
plasma in the form of arcing (lightening)
instead of steady state glow discharge.
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 27
 Movement of Charged Particle
• Electron is much lighter than ion
me << mi
me:mHydrogen =1:1836
• Electric forces on electrons and ions are the same
F = qE
• Electron has much higher acceleration
a = F/m
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 28
 Movement of Charged Particle

• RF electric field varies quickly, electrons are

accelerated very quickly while ions react slowly
• Ions have more collisions due to their larger
cross-section that further slowing them down
• Electrons move much faster than ions in plasma

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 29

 Thermal Velocity

• Electron thermal velocity

v = (kTe/me)1/2
• RF plasma, Te is about 2 eV
ve ≈ 5.93×107 cm/sec = 1.33×107 mph

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 30

Magnetic Force and Gyro-motion

• Magnetic force on a charged particle:

F = qv×B
• Magnetic force is always perpendicular to the
particle velocity
• Charged particle will spiral around the
magnetic field line.
• Gyro-motion.
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 31
 Gyro-motion

Magnetic Field Line Trajectory of charged particle

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 32

 Gyrofrequency
• Charged particle in gyro motion in magnetic field

qB
Ω=
m

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 33

 Gyro radius
• Gyroradius of charged particle in a magnetic
field, ρ, can be expressed as:

ρ = v⊥/Ω

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 34

 Boltzmann Distribution
f(E)

Electrons with
enough energy
for ionization

Energy, E
2 - 3 eV
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 35
 Ion Bombardment
• Anything close to plasma gets ion bombardment
• Very important for sputtering, etch and PECVD
• Mainly determined by RF power
• Pressure also can affect bombardment

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 36

 Ion Bombardment
• Electrons reach electrodes and chamber wall first
• Electrodes charged negatively, repel electrons
and attract ions.
• The sheath potential accelerates ions towards the
electrode and causes ion bombardment.
• Ion bombardment is very important for etch,
sputtering and PECVD processes.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 37

 Sheath Potential
+ + + + + + + + + + + + + +
- - - - - - - - -
+ + + + + + + + + + + + + +

Electrode
- - - - - - - - - - -
+ + + + + + + + + + + + + +
- - - - - - - - - - - - -
+ + + + + + + + + + + + + +
- - - - - - - - - - - -
+ + + + + + + + + + + + + +
- - - - - - - - - -
+ + + + + + + + + + + + + +
- - - - - - - -
+ + + + + + + + + + x
+ + + +

Bulk plasma Sheath Region

Vp

Sheath Potential
Vf
Dark space

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 38

Applications of Ion bombardment
•Help to achieve anisotropic etch profile
−Damaging mechanism
−Blocking mechanism
•Argon sputtering
−Dielectric etch for gap fill
−Metal deposition
•Help control film stress in PECVD processes
−Heavier bombardment, more compressive film
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 39
 Plasma Potential & DC Bias
Plasma Potential
Volt

DC Bias RF potential
Time
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 40
 DC biases and RF powers
Plasma potential

Plasma potential

DC bias
DC bias time
0 0
time

RF potentials

• Lower RF power • Higher RF power

• Smaller DC bias • Larger DC bias
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 41
 Ion Bombardment

•Ion energy
•Ion density
•Both controlled by RF power

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 42

 Ion Bombardment Control
• Increasing RF power, DC bias increases, ion
density also increases.
• Both ion density and ion bombardment energy
are controlled by RF power.
• RF power is the most important knob controlling
ion bombardment
• RF power also used to control film stress for
PECVD processes
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 43
DC Bias of CVD Chamber Plasma

Grounded
RF hot
Vp = 10 − 20 V

Dark spaces or sheath regions

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 44
 DC Bias of Etch Chamber Plasma
Plasma potential

0 time
Wafer Potential
DC bias

Self bias

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 45

 DC Bias of Etch Chamber Plasma

V2
A1
A2

DC bias V1
V1 = 200 to 1000 V

4
V1/V2 =(A2/A1)
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 46
 Question and Answer
• If the electrode area ratio is 1:3, what is the
difference between the DC bias and the self-
bias compare with the DC bias?

• The DC bias is V1, the self-bias is V1 − V2,

therefore, the difference is

[V1 − (V1 − V2)]/V1 = V2/V1 = (A1/A2)4 = (1/3)4 = 1/81 = 1.23%

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 47

 Question and Answer
• Can we insert a fine metal probe into the
plasma to measure the plasma potential V2?
• Yes, we can. However, it is not very accurate
because of sheath potential near probe surface
• Measurement results are determined by the
theoretical models of the sheath potential,
which have not been fully developed, yet.
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 48
Ion Bombardment and Electrode Size
• Smaller electrode has more energetic ion
bombardment due to self-bias
• Etch chambers usually place wafer on
smaller electrode

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 49

 Advantages of Using Plasma
• Plasma processes in IC fabrication:
– PECVD
• CVD chamber dry clean
– Plasma Etch
– PVD
– Ion implantation

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 50

 Benefits of Using Plasma For
CVD Process

• High deposition rate at relatively lower

temperature.

• Independent film stress control

• Chamber dry clean

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 51
 Comparison of PECVD and LPCVD

Processes LPCVD (150 mm) PECVD (150 mm)

Chemical reaction SiH4+ O 2 → SiO2 + … SiH4+ N2O → SiO2 + …

Process parameters p =3 Torr, T=400 °C p=3 Torr, T=400 °C and
RF=180 W
Deposition rate 100 to 200 Å/min ≥ 8000 Å/min
Process systems Batch system Single-wafer system
Wafer to wafer uniformity Difficult to control Easier to control

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 52

 Gap Fill by HDP-CVD

• Simultaneously deposition and sputtering

• Tapering the gap opening

• Fill gap between metal lines bottom up

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 53

 HDP CVD Void-free Gap Fill

Hong Xiao, Ph. D. 0.25 µm, A/R 4:1

www2.austin.cc.tx.us/HongXiao/Book.htm 54
 Benefits of Using Plasma For
Etch Process

• High etch rate

• Anisotropic etch profile
• Optical endpoint
• Less chemical usage and disposal
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 55
 Benefits of Using Plasma For
PVD Process
• Argon sputtering
• Higher film quality
– Less impurity and higher conductivity
• Better uniformity
• Better process control
• Higher process integration capability.
• Easier to deposit metal alloy films
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 56
PECVD and Plasma Etch Chambers
• CVD: Adding materials on wafer surface
– Free radicals
– Some bombardment for stress control
• Etch: Removing materials from wafer surface
– Free radicals
– Heavy bombardment
– Prefer low pressure, better directionality of ions

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 57

 PECVD Chambers
• Ion bombardment control film stress
• Wafer is placed grounded electrode
• Both RF hot and grounded electrodes have
about the same area
• It has very little self-bias
• The ion bombardment energy is about 10 to
20 eV, mainly determined by the RF power
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 58
Schematic of a PECVD Chamber

RF

Chuck Plasma Wafer

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 59

 Plasma Etch Chambers
• Ion bombardment
– Physically dislodge
– break chemical bonds
• Wafer on smaller electrode
• Self-bias
• Ion bombardment energy
– on wafer (RF hot electrode): 200 to 1000 eV
– on lid (ground electrode): 10 to 20 eV.
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 60
 Plasma Etch Chambers
• Heat generation by heavy ion bombardment
• Need control temperature to protect masking PR
• Water-cool wafer chuck (pedestal, cathode)
• Lower pressure not good to transfer heat from
wafer to chuck
• Helium backside cooling required
• Clamp ring or electrostatic chuck (E-chuck) to
hold wafer www2.austin.cc.tx.us/HongXiao/Book.htm
Hong Xiao, Ph. D. 61
 Plasma Etch Chambers
• Etch prefer lower pressure
– longer MFP, more ion energy and less scattering
• Low pressure, long MFP, less ionization
collision
– hard to generate and sustain plasma
• Magnets are used to force electron spin and
travel longer distance to increase collisions

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 62

 Schematic of an Etch Chamber
Process gases

Process
chamber Plasma Magnet coils
Wafer

Chuck
By-products to
the pump RF power
Backside
cooling helium
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 63
 Remote Plasma Processes
• Need free radicals
– Enhance chemical reactions
• Don’t want ion bombardment
– Avoid plasma-induced damage
• Remote plasma systems

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 64

 Remote Plasma System
MW or RF Remote
plasma
chamber
Process
gases Plasma

Process
chamber Free radicals

Heated plate
By-products to
the pump
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 65
 Photoresist Strip
• Remove photoresist right after etch
• O2 and H2O chemistry
• Can be integrated with etch system
• In-situ etch and PR strip
• Improve both throughput and yield

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 66

 Photoresist Strip Process
Microwave Remote plasma
chamber
H2O, O2 Plasma

Process chamber
Wafer with O H O O H O H O
photoresist

H2O, CO2, … Heated plate

To the pump
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 67
 Remote Plasma Etch
• Applications: isotropic etch processes:
– LOCOS or STI nitride strip
– wineglass contact hole etch
• Can be integrated with plasma etch system
– improve throughput
• Part of efforts to replace wet process

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 68

 Remote Plasma Etch System
Microwave Remote plasma
chamber

NF3 Plasma

Wafer
Process F F F
N2 F
chamber F N2

N2, SiF4, … Heated plate

To pump
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 69
 Remote Plasma Clean
• Deposition not only on wafer surface
• CVD chamber need clean routinely
– Prevent particle contamination due to film crack
• Plasma clean with fluorocarbon gases is
commonly used
– Ion bombardment affects parts lifetime
– Low dissociation rate of fluorocarbon
– Environmental concern of fluorocarbon releases
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 70
 Remote Plasma Clean
• Microwave high-density plasma
• The free radicals flow into CVD chamber
• React and remove deposited film
• Clean the chamber while
– gentle process, prolonged part lifetime
– high dissociation, little fluorocarbon releases

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 71

 Remote Plasma Clean System
Microwave Remote plasma
chamber

NF3 Plasma

CVD F F
N2 F
chamber F N2 F

N2, SiF4, … Heated plate

To pump
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 72
 Remote Plasma CVD (RPCVD)
• Epitaxial Si-Ge for high-speed BiCMOS
• Still in R&D
• Gate dielectric: SiO2, SiON, and Si3N4
• High-κ dielectrics: HfO2, TiO2, and Ta2O5
• PMD barrier nitride
– LPCVD: budget limitations
– PECVD: plasma induced damage
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 73
 High-density Plasma
• High-density at low pressure are desired
• Lower pressure longer MFP, less ion scattering,
enhances etch profile control.
• Higher density, more ions and free radicals
– Enhance chemical reaction
– Increase ion bombardment
• For CVD processes, HDP in-situ, simultaneous
dep/etch/dep enhance gap fill
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 74
 Limitation of Parallel Plate
Plasma Source
• Capacitively coupled plasma source
• Can not generate high-density plasma
• Hard to generate plasma even with magnets at
low pressure, about a few mTorr.
– electron MFP too long, no enough ionization
collisions.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 75

 Limitation of Parallel Plate
Plasma Source
• Cannot independently control ion flux and ion
energy
• Both are directly related to RF power
• Better process control requires a plasma source
that capable to independently control both of
them

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 76

 ICP and ECR
• Most commonly used in IC industry
• Inductively coupled plasma, ICP
– also called transformer coupled plasma, or TCP
• Electron cyclotron resonance, ECR,
• Low press at few mTorr
• Independently control ion flux and ion energy

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 77

Inductively Coupled Plasma (ICP)
• RF current flows in the coils generates a
changing electric field via inductive coupling
• The angular electric field accelerates electrons
in angular direction.
• Electrons to travel a long distance without
collision with the chamber wall or electrode.
• Ionization collisions generate high-density
plasma at low pressure
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 78
Inductively Coupled Plasma (ICP)
• Bias RF power controls the ion energy
• Source RF power controls the ion flux
• Helium backside cooling system with E-chuck
controls wafer temperature

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 79

Illustration of Inductive Coupling

RF current in coil

Induced electric field

RF magnetic field

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 80

 Schematic of ICP Chamber
Inductive coils Ceramic cover
Source RF

Plasma Wafer
Chamber body

E-chuck Bias RF
Helium

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 81

 Application of ICP
• Dielectric CVD
• All patterned etch processes
• Sputtering clean prior to metal deposition
• Metal plasma PVD
• Plasma immersion ion implantation

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 82

 ECR
• Gyro-frequency or cyclotron frequency:

qB
Ω=
m
• Determined by magnetic field

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 83

 ECR
• Electron cyclotron resonance when ωMW = Ωe
• Electrons get energy from MW
• Energetic electrons collide with other atoms
or molecules
• Ionization collisions generate more electrons
• Electrons are spiraling around the field line
• Many collisions even at very low pressure
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 84
 Illustration of ECR
Electron trajectory

Mic
row
ave
Pow
er

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 85

 Illustration of ECR
Microwave

Magnetic
Coils ECR
Plasma
Magnetic
field line Wafer

E-chuck Bias RF

Helium
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 86
 ECR
• Bias RF power controls the ion energy
• Microwave power controls the ion flux
• Magnet coil current controls plasma position
and process uniformity
• Helium backside cooling system with E-chuck
controls wafer temperature

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 87

 Application of ECR
• Dielectric CVD
• All patterned etch processes
• Plasma immersion ion implantation

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 88

 Summary

• Plasma is ionized gas with n– = n+

• Plasma consist of n, e, and i
• Ionization, excitation-relaxation, dissociation
• Ion bombardment help increase etch rate and
achieve anisotropic etch
• Light emission can be used for etch end point
• MFP and its relationship with pressure
• Ions from plasma always bombard electrodes
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 89
 Summary
• Increasing RF power increases both ion flux
and ion energy in capacitive coupled plasmas
• Low frequency RF power gives ions more
energy, causes heavier ion bombardment
• The etch processes need much more ion
bombardment than the PECVD
• Low pressure, high density plasma are desired
• ICP and ECR are two HDP systems used in IC
fabrication
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 90
 Chapter 8
Ion Implantation
Hong Xiao, Ph. D.
[email protected]
www2.austin.cc.tx.us/HongXiao/Book.htm

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 1

 Objectives
• List at least three commonly used dopants
• Identify three doped areas
• Describe the advantages of ion implantation
• Describe major components of an implanter
• Explain the channeling effect
• Relationship of ion range and ion energy
• Explain the post-implantation annealing
• Identify safety hazards
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 2
 Ion Implantation

• Introduction
• Safety
• Hardware
• Processes
• Summary

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 3

 Wafer Process Flow
Materials IC Fab

Dielectric Test
Metalization CMP
deposition
Wafers

Thermal Etch Packaging

Implant
Processes PR strip PR strip
Masks

Photo- Final Test

lithography

Design

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 4

Introduction: Dope Semiconductor
• What is Semiconductor?
• Why semiconductor need to be doped?
• What is n-type dopant?
• What is p-type dopant?

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 5

 Introduction
• Dope semiconductor
• Two way to dope
– Diffusion
– Ion implantation
• Other application of ion implantation

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 6

 Dope Semiconductor: Diffusion
• Isotropic process
• Can’t independently control dopant profile
and dopant concentration
• Replaced by ion implantation after its
introduction in mid-1970s.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 7

 Dope Semiconductor: Diffusion
• First used to dope semiconductor
• Performed in high temperature furnace
• Using silicon dioxide mask
• Still used for dopant drive-in
• R&D on ultra shallow junction formation.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 8

 Dopant Oxide Deposition

Deposited Dopant Oxide

SiO2

Si Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 9

 Oxidation

SiO2

Si Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 10

 Drive-in

SiO2
Doped junction
Si Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 11

 Strip and Clean

SiO2
Doped junction
Si Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 12

Dope Semiconductor: Ion Implantation
• Used for atomic and nuclear research
• Early idea introduced in 1950’s
• Introduced to semiconductor manufacturing
in mid-1970s.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 13

Dope Semiconductor: Ion Implantation
• Independently control dopant profile (ion
energy) and dopant concentration (ion
current times implantation time)
• Anisotropic dopant profile
• Easy to achieve high concentration dope of
heavy dopant atom such as phosphorus and
arsenic.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 14

 Misalignment of the Gate

Gate Oxide
Metal Gate Metal Gate

p+ S/D n-Si p+ S/D

n-Si

Aligned Misaligned

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 15

 Ion Implantation, Phosphorus

SiO2 Poly Si P+

n+ n+

P-type Silicon

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 16

 Comparison of
Implantation and Diffusion
Doped region

SiO2 PR

Si Si

Junction depth
Diffusion Ion implantation

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 17

 Comparison of
Implantation and Diffusion
Diffusion Ion Implantation

High temperature, hard mask Low temperature, photoresist mask

Isotropic dopant profile Anisotropic dopant profile

Cannot independently control of the dopant Can independently control of the dopant
concentration and junction depth concentration and junction depth

Batch process Both Batch and single wafer process

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 18

 Ion Implantation Control
• Beam current and implantation time control
dopant concentration
• Ion energy controls junction depth
• Dopant profile is anisotropic

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 19

 Applications of Ion Implantation

Applications Doping Pre-amorphous Buried oxide Poly barrier

Ions n-type: P, As, Sb Si or Ge O N
p-type: B

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 20

 Other Applications
• Oxygen implantation for silicon-on-
insulator (SOI) device
• Pre-amorphous silicon implantation on
titanium film for better annealing
• Pre-amorphous germanium implantation on
silicon substrate for profile control
• …...

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 21

 Some Fact about Phosphorus
Name Phosphorus
Symbol P
Atomic number 15
Atomic weight 30.973762
Discoverer Hennig Brand
Discovered at Germany
Discovery date 1669
Origin of name From the Greek word "phosphoros" meaning
"bringer of light" (an ancient name for the
planet Venus)
Density of solid 1.823 g/cm3
Molar volume 17.02 cm3
Velocity of sound N/A
Electrical resistivity 10 µΩ cm
Refractivity 1.001212
Reflectivity N/A
Melting point 44.3 C
Boiling point 277 C
Thermal conductivity 0.236 W m-1 K-1
Coefficient of linear thermal expansion N/A
Applications N-type dopant in diffusion, ion implantation,
epitaxial grow and polysilicon deposition.
Dopant of CVD silicate glass (PSG and BPSG).22
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm
Main sources P (red), PH3, POCl 3
 Some Fact about Arsenic
Name Arsenic
Symbol As
Atomic number 33
Atomic weight 74.9216
Discoverer Known since ancient times
Discovered at not known
Discovery date not known
Origin of name From the Greek word "arsenikon" meaning
"yellow orpiment"
Density of solid 5.727 g/cm3
Molar volume 12.95 cm 3
Velocity of sound N/A
Electrical resistivity 30.03 µΩ cm
Refractivity 1.001552
Reflectivity N/A
Melting point 614 C
Boiling point 817 C
Thermal conductivity 50.2 W m -1 K-1
Coefficient of linear thermal expansion N/A
Applications N-type dopant in diffusion, ion implantation,
epitaxial grow and polysilicon deposition.
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 23
Main sources As, AsH3
 Some Fact about Boron
Name Boron
Symbol B
Atomic number 5
Atomic weight 10.811
Discoverer Sir Humphrey Davy, Joseph-Louis Gay-Lussac,

Discovered at England, France

Discovery date 1808
Origin of name From the Arabic word "buraq" and the Persian
word "burah"
Density of solid 2.460 g/cm3
Molar volume 4.39 cm3
Velocity of sound 16200 m/sec
Electrical resistivity > 10 12 µΩ cm
Refractivity N/A
Reflectivity N/A
Melting point 2076 C
Boiling point 3927 C
Thermal conductivity 27 W m-1 K-1
Coefficient of linear thermal expansion 6 10-6 K-1
Applications P-type dopant in diffusion, ion implantation,
epitaxial grow and polysilicon deposition.
Dopant of CVD silicate glass (BPSG)
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 24
Main sources B, B2H6, BF3
 Stopping Mechanism
• Ions penetrate into substrate
• Collide with lattice atoms
• Gradually lose their energy and stop
• Two stop mechanisms

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 25

 Two Stopping Mechanism
• Nuclear stopping
– Collision with nuclei of the lattice atoms
– Scattered significantly
– Causes crystal structure damage.
• electronic stopping
– Collision with electrons of the lattice atoms
– Incident ion path is almost unchanged
– Energy transfer is very small
– Crystal structure damage is negligible
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 26
 Stopping Mechanism
• The total stopping power
Stotal = Sn + Se
• Sn: nuclear stopping, Se: electronic stopping
• Low E, high A ion implantation: mainly
nuclear stopping
• High E, low A ion implantation, electronic
stopping mechanism is more important

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 27

 Stopping Mechanisms
Ion Random Collisions
(S=Sn+Se)

Channeling
(S≈Se)

Back Scattering (S≈Sn)

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 28

Stopping Power and Ion Velocity

I II III
Stopping Power

Nuclear
Stopping
Electronic
Stopping

Ion Velocity
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 29
Ion Trajectory and Projected Range

Vacuum Substrate Collision

Ion Trajectory
Ion Beam

Projected Range

Distance to the Surface

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 30

 Ion Projection Range

ln (Concentration)

Projected
Range

Substrate Surface Depth from the Surface

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 31
 Projected Range in Silicon
1.000

Projected Range (µm)

P
B

0.100
As
Sb

0.010
10 100 1000
Implantation Energy (keV)
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 32
 Barrier Thickness to Block
200 keV Ion Beam
1.20

1.00
Mask Thickness (micron)

0.80 B

0.60
P
0.40
As
0.20
Sb
0.00
Si SiO2 Si3N4 Al PR

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 33

Implantation Processes: Channeling
• If the incident angle is right, ion can travel long
distance without collision with lattice atoms
• It causes uncontrollable dopant profile

Lots of collisions

Very few collisions

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 34
 Channeling Effect
Lattice Atoms

Channeling Ion

Collisional Ion

Wafer
Surface
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 35
 Post-collision Channeling
Collisional Channeling Collisional

Wafer
Surface

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 36

 Post-collision Channeling
Collisional Channeling Collisional
Dopant Concentration

Distance from surface

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 37

Implantation Processes: Channeling

• Ways to avoid channeling effect

– Tilt wafer, 7° is most commonly used
– Screen oxide
– Pre-amorphous implantation, Germanium
• Shadowing effect
– Ion blocked by structures
• Rotate wafer and post-implantation diffusion
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 38
 Shadowing Effect
Ion Beam

Polysilicon

Doped Region
Substrate

Shadowed Region
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 39
 Shadowing Effect

After Annealing and Diffusion

Polysilicon

Doped Region
Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 40

 Q&A
• Why don’t people use channeling effect to
create deep junction without high ion energy?
• Ion beam is not perfectly parallel. Many ions
will start to have a lot of nuclear collisions
with lattice atoms after they penetrating into
the substrate. Some ions can channel deep into
the substrate, while many others are stopped
as the normal Gaussian distribution.
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 41
 Damage Process
• Implanted ions transfer energy to lattice atoms
– Atoms to break free
• Freed atoms collide with other lattice atoms
– Free more lattice atoms
– Damage continues until all freed atoms stop
• One energetic ion can cause thousands of
displacements of lattice atoms

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 42

 Lattice Damage With One Ion

Light Ion

Damaged Region

Heavy Ion

Single Crystal Silicon

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 43

 Implantation Processes: Damage
• Ion collides with lattice atoms and knock them
out of lattice grid
• Implant area on substrate becomes amorphous
structure

Before Implantation After Implantation

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 44
 Implantation Processes: Anneal

• Dopant atom must in single crystal structure

and bond with four silicon atoms to be activated
as donor (N-type) or acceptor (P-type)

• Thermal energy from high temperature helps

amorphous atoms to recover single crystal
structure.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 45

 Thermal Annealing

Lattice Atomswww2.austin.cc.tx.us/HongXiao/Book.htmDopant Atom

Hong Xiao, Ph. D. 46
 Thermal Annealing

Lattice Atomswww2.austin.cc.tx.us/HongXiao/Book.htmDopant Atom

Hong Xiao, Ph. D. 47
 Thermal Annealing

Lattice Atomswww2.austin.cc.tx.us/HongXiao/Book.htmDopant Atom

Hong Xiao, Ph. D. 48
 Thermal Annealing

Lattice Atomswww2.austin.cc.tx.us/HongXiao/Book.htmDopant Atom

Hong Xiao, Ph. D. 49
 Thermal Annealing

Lattice Atomswww2.austin.cc.tx.us/HongXiao/Book.htmDopant Atom

Hong Xiao, Ph. D. 50
 Thermal Annealing

Lattice Atomswww2.austin.cc.tx.us/HongXiao/Book.htmDopant Atom

Hong Xiao, Ph. D. 51
 Thermal Annealing

Lattice Atomswww2.austin.cc.tx.us/HongXiao/Book.htmDopant Atom

Hong Xiao, Ph. D. 52
 Thermal Annealing

Lattice Atomswww2.austin.cc.tx.us/HongXiao/Book.htmDopant Atoms

Hong Xiao, Ph. D. 53
Implantation Processes: Annealing

Before Annealing After Annealing

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 54

 Rapid Thermal Annealing (RTA)

• At high temperature, annealing out pace

diffusion
• Rapid thermal process (RTP) is widely used
for post-implantation anneal
• RTA is fast (less than a minute), better
WTW uniformity, better thermal budget
control, and minimized the dopant diffusion
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 55
 RTP and Furnace Annealing

Gate
Poly Si Poly Si
Gate
SiO2

Si Si
Source/Drain

RTP Annealing Furnace Annealing

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 56

 Question and Answer
• Why can’t the furnace temperature be
ramped-up and cooled-down as quickly as
RTP system ?
• A furnace has very large thermal capacity, it
needs very high heating power to ramp-up
temperature rapidly. It is very difficult to ramp
up temperature very fast without large
temperature oscillation due to the temperature
overshoot and undershoot .
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 57
 Ion Implantation: Hardware
• Gas system
• Electrical system
• Vacuum system
• Ion beamline

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 58

 Ion Implanter

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 59

 Implantation Process
Gases and Vapors:
P, B, BF3, PH3, and AsH3

Next Step
Implanter

Select Ion: Select Ion Select Beam

B, P, As Energy Current
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 60
 Ion Implanter
Electrical
Gas Cabin Analyzer
System
Magnet

Vacuum
Ion Beam
Pump
Source Line

Electrical Vacuum
System Pump
Plasma Flooding Wafers
System
End Analyzer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 61
 Ion Implantation: Gas System
• Special gas deliver system to handle
hazardous gases
• Special training needed to change gases
bottles
• Argon is used for purge and beam
calibration

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 62

Ion Implantation: Electrical System
• High voltage system
– Determine ion energy that controls junction depth
• High voltage system
– Determine ion energy that controls junction depth
• RF system
– Some ion sources use RF to generate ions

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 63

Ion Implantation: Vacuum System
• Need high vacuum to accelerate ions and
reduce collision
• MFP >> beamline length
• 10-5 to 10-7 Torr
• Turbo pump and Cryo pump

• Exhaust system
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 64
Ion Implantation: Control System
• Ion energy, beam current, and ion species.
• Mechanical parts for loading and unloading
• Wafer movement to get uniform beam scan
• CPU board control boards
– Control boards collect data from the systems,
send it to CPU board to process,
– CPU sends instructions back to the systems
through the control board.
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 65
 Ion Implantation: Beamline
• Ion source
• Extraction electrode
• Analyzer magnet
• Post acceleration
• Plasma flooding system
• End analyzer

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 66

 Ion Beam Line
Suppression Electrode Analyzer
Magnet

Vacuum
Ion Beam
Pump
Source Line

Extraction Post Acceleration

Electrode Electrode Vacuum
Plasma Flooding Pump
System Wafers
End Analyzer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 67
 Ion implanter: Ion Source
• Hot tungsten filament emits thermal electron
• Electrons collide with source gas molecules
to dissociate and ionize
• Ions are extracted out of source chamber and
accelerated to the beamline
• RF and microwave power can also be used to
ionize source gas

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 68

 Ion Source
Source Gas or Vapor
Arc Power Tungsten Anti-cathode
~ 120 V Filament
+
-
Filament
Power, 0-5V, Plasma
up to 200A
Magnetic Field Line Source
Magnet

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 69

 RF Ion Source
Dopant Gas

RF Coils
+ RF Plasma
-

Extraction
Electrode
Ion Beam
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 70
 Microwave Ion Source

Microwave

Magnetic
Coils ECR
Plasma

Magnetic
Field Line
Extraction
Electrode
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 71
 Ion Implantation: Extraction

• Extraction electrode accelerates ions up to

50 keV
• High energy is required for analyzer magnet
to select right ion species.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 72

 Extraction Assembly
Suppression Electrode Extraction Electrode
Top View
Ion Source
Plasma

Ion Beam

+ –
Extraction Suppression Slit Extracting
Power, up Power, up to Ion Beam
to 60 kV 10 kV
– + Terminal Chassis

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 73

Ion Implantation: Analyzer Magnet
• Gyro radius of charge particle in magnetic field
relate with B-field and mass/charge ratio
• Used for isotope separation to get enriched U235
• Only ions with right mass/charge ratio can go
through the slit
• Purified the implanting ion beam

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 74

 Analyzer
Magnetic Field (Point Outward)

Ion Beam Larger m/q Ratio

Flight Tube

Smaller m/q Ratio

Right m/q Ratio

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 75

 Ions in BF3 Plasma
Ions Atomic or molecule weight
10B 10
11B 11
10BF 29
11BF 30
F2 38
10BF 48
2
11BF 49
2
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 76
 Question and Answer
10B+is lighter and can penetrate deeper than 11B+,
why don’t use 10B+ in deep junction implantation?

• Only 20% of boron atoms are 10B

• 10B+ ion concentration is only 1/4 of 11B+
• 10B+ beam current is 1/4 of 11B+ beam current
• Quadruple implantation time, lower throughput
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 77
Ion Implantation: Post Acceleration
• Increasing (sometimes decreasing) ion
energy for ion to reach the required junction
depth determined by the device
• Electrodes with high DC voltage
• Adjustable vertical vanes control beam
current

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 78

Ion Implantation: Plasma Flooding
System
• Ions cause wafer charging
• Wafer charging can cause non-uniform
doping and arcing defects
• Elections are “flooding” into ion beam and
neutralized the charge on the wafer
• Argon plasma generated by thermal
electrons emit from hot tungsten filament

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 79

 Post Acceleration
Suppression Electrode Acceleration Electrode

Ion Beam

– –
Suppression Post Accel.
Power, up to Power, up
10 kV + to 60 kV
Terminal Chassis
+
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 80
 Ion Beam Current Control
Fixed Defining Aperture

Ion Beam

Adjustable Vertical Vanes

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 81
 Bending Ion Trajectory

Neutral Atom Trajectory

Bias Electrode Ion Trajectory

Wafer

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 82

 Charge Neutralization System
• Implanted ions charge wafer positively
• Cause wafer charging effect
• Expel positive ion, cause beam blowup and
result non-uniform dopant distribution
• Discharge arcing create defects on wafer
• Breakdown gate oxide, low yield
• Need eliminate or minimize charging effect
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 83
 Charging Effect

Ions trajectory

Wafer ++++

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 84

 Charge Neutralization System
• Need to provide electrons to neutralize ions
• Plasma flooding system
• Electron gun
• Electron shower are used to

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 85

 Plasma Flooding System

DC Power Tungsten Ar
Ion
Filament Beam
+
−
Filament
Current Plasma

Electrons
Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 86
 Electron Gun
Secondary Electron Target

Secondary
Electrons Electrons

Ion Beam

Electron
Gun Thermal
Filament
Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 87
 Wafer Handling
• Ion beam diameter: ~25 mm (~1”),
• Wafer diameter: 200 mm (8”) or larger
• Needs to move beam or wafer, or both, to
scan ion beam across the whole wafer
– Spin wheel
– Spin disk
– Single wafer scan

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 88

 Spin Wheel
Wafers
Spin arm

Spin rate: to
2400 rpm Ion beam

Swing period: ~10 sec Implanted stripe

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 89
 Spin Disk
Ion Beam
Wafers

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 90

 Single Wafer Scanning System

Scanning
Ion Beam
Wafer
Movement
Ion Beam

Scanning Electrodes

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 91

 Ion Implantation: Beam Stop
• absorb the ion beam energy,
• ion beam detector
– beam current, beam energy, and beam shape
measurement
• Water cooled metal plate carries away the
heat and blocks the X-ray radiation

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 92

 Ion Implantation: End Analyzer
• Faraday charge detector
• Used to calibrate beam current, energy and
profile

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 93

 Beam Stop
Graphite
Top View

Ion Beam

Magnets

Faraday
Water Cooled Current
Base Plate Detectors

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 94

 Ion Implantation: The Process
• CMOS applications
• CMOS ion implantation requirements
• Implantation process evaluations

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 95

CMOS Implantation Requirements
Implant Step 0.35 µm, 64 Mb 0.25 µm, 256 Mb 0.18 µm, 1 Gb

N-well
Well P/600/2×1013 P/400/2×1013 P/300/1×1013
Anti-punch through P/100/5×1013 As/100/5×1012 As/50/2×1012
Threshold B/10/7×1012 B/5/3×1012 B/2/4×1012
Poly dope P/30/2×1015 B/20/2×1015 B/20/3×1015
Poly diffusion block - - N2/20/3×1015
Lightly doped drain (LDD) B/7/5×1013 B/5/1×1014 B/2/8×1013

Halo (45° implant) - - As/30/5×1013

Source/drain contact B/10/2×1015 B/7/2×1015 B/6/2×1015
P-well
Well B/225/3×1013 B/200/1×1013 B/175/1×1013
Anti-punch through B/30/2×1013 B/50/5×1012 B/45/5×1012
Threshold B/10/7×1012 B/5/3×1012 B/2/4×1012
Poly dope P/30/5×1015 P/20/2×1015 As/40/3×1015
Poly diffusion block - - N2/20/3×1015
Lightly doped drain (LDD) P/20/5×1013 P/12/5×1013 P/5/3×1013

Halo (45° implant) B/30/3×1012 B/20/3×1012 B/7/2×1013

Source/drain contact As/30/3×1015 As/20/3×1015 As/15/3×1015
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 96
 Implantation Process: Well
Implantation
• High energy (to MeV), low current (1013/cm2)
P+

Photoresist
N-Well

P-Epi
P-Wafer

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 97

 Implantation Process: VT Adjust
Implantation
Low Energy , Low Current

B+
Photoresist
STI USG
P-Well N-Well
P-Epi
P-Wafer

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 98

Lightly Doped Drain (LDD) Implantation

• Low energy (10 keV), low current (1013/cm2)

P+

Photoresist

STI USG
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 99
Implantation Process: S/D Implantation
• Low energy (20 keV), high current (>1015/cm2)

P+

Photoresist

STI n+ n+ USG
P-Well N-Well
P-Epi
P-Wafer

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 100

 Ion Implantation Processes

Ion Implantation Energy Current

Well High energy low current
Source/Drain Low energy high current
VT Adjust Low energy low current
LDD Low energy low current

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 101

 Process Issues
• Wafer charging
• Particle contamination
• Elemental contamination
• Process evaluation

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 102

 Wafer Charging
• Break down gate oxide
• Dielectric strength of SiO2: ~10 MV/cm
• 100 Å oxide breakdown voltage is 10 V
• Gate oxide: 30 to 35 Å for 0.18 µm device
• Require better charge neutralization

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 103

 Wafer Charging Monitoring
• Antenna capacitor changing test structure
• The ratio of polysilicon pad area and thin
oxide area is called antenna ratio
• Can be as high as 100,000:1
• The larger antenna ratio, the easier to
breakdown the thin gate oxide

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 104

 Antenna Ratio

Top View

Polysilicon
Side View Field Oxide Gate Oxide
Silicon Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 105

 Particle Contamination
• Large particles can block the ion beam
especially for the low energy processes,
• VT adjust, LDD and S/D implantations,
• Cause incomplete dopant junction.
• Harmful to yield

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 106

 Effect of Particle Contamination
Ion Beam
Dopant in PR
Particle

Photoresist

Screen Oxide
Partially Implanted Junctions

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 107

 Elemental Contamination
• Co-implantation other elements with intended dopant
• 94Mo++ and 11BF +, same mass/charge ratio (A/e = 49)
2
• Mass analyzer can’t separate these two
• 94Mo++ causes heavy metal contamination

• Ion source can’t use standard stainless steel

• Other materials such as graphite and tantalum are
normally used

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 108

 Process Evaluation
• Four-point probe
• Thermal wave
• Optical measurement system (OMS)

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 109

 Four-Point Probe
• Perform after anneal
• Measure sheet resistance
• Sheet resistant is a function of dopant
concentration and junction depth
• Commonly used to monitor doping process

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 110

 Four-Point Probe Measurement
I
V
P1 P2 P3 P4

S1 S2 S3

Dope Region

Substrate

For a typical four-point probe, S1 = S2 = S3 = 1mm,

If current is applied between P1 and P4, Rs = 4.53 V/I
If current is applied between P1 and P3, Rs = 5.75 V/I
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 111
 Thermal Wave System
• Argon “pump” laser generates thermal pulses on
wafer surface
• He-Ne probe laser measures DC reflectivity (R)
and reflectivity modulation induced by the pump
laser (∆R) at the same spot
• Ratio ∆R/R is called thermal wave (TW) signal,
– TW signal ∆R/R related to the crystal damage
– crystal damage is a function of the implant dose

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 112

 Thermal Wave System

Pump
I ∆R Thermal Waver Laser
R Signal Detector

t I

t
Probe Laser

∆R/R: Thermal Wave Signal

Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 113
 Thermal Wave System
• Performed immediately after the implant process
– Four-point probe needs anneal first
• Non-destructive, can measure production wafers
– Four-point probe is only good for test wafers
• Low sensitivity at low dosage
• Drift of the TW signal over time
– needs to be taken as soon as the implantation finished
• Don’t have very high measurement accuracy
– Laser heating relax crystal damage

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 114

Optical Measurement System (OMS)
• transparent wafer coated a with a thin layer of
copolymer, which contains energy sensitive dye
• During ion implantation, energetic ions collide with
dye molecules and break them down
• Makes the copolymer becomes more transparent
• The higher the dosage, the higher the transparency
• Photon count change before and after implantation
• Determine dosage of certain ion at certain energy
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 115
Optical Measurement System (OME)
Quartz Halogen Lamp
600 nm Filter

Photo Detector

PDI Count PDI Count

Before Implantation After Implantation

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 116
 Ion Implantation: Safety
• One of most hazardous process tools in
semiconductor industry
• Chemical
• Electro-magnetic
• Mechanical

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 117

Ion Implantation: Chemical Safety
• Most dopant materials are highly toxic,
flammable and explosive.
• Poisonous and explosive: AsH3, PH3, B2H6
• Corrosive: BF3
• Toxic: P, B, As, Sb

• Common sense: get out first, let the trained

people to do the investigation.
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 118
 Ion Implantation:
Electro-magnetic Safety
• High voltage: from facility 208 V to
acceleration electrode up to 50 kV.
• Ground strip, Work with buddy!
• Lock & tag

• Magnetic field: pacemaker, etc.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 119

Ion Implantation: Radiation Safety
• High energy ions cause strong X-ray
radiation
• Normally well shield

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 120

 Ion Implantation:
Corrosive by-products
• BF3 as dopant gas
• Fluorine will react with hydrogen to from
HF
• Anything in the beamline could have HF
• Double glove needed while wet clean those
parts

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 121

Ion Implantation: Mechanical Safety
• Moving parts, doors, valves and robots
• Spin wheel
• Hot surface
• ……

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 122

 Technology Trends
• Ultra shallow junction (USJ)
• Silicon on insulator (SOI)
• Plasma immersion ion implantation (PIII)

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 123

 Ultra Shallow Junction (USJ)
• USJ (xj ≤ 0.05 µm) for sub-0.1 µm devices
– p-type junction, boron ion beam at extremely low
energy, as low as 0.2 keV
• The requirements for the USJ
– Shallow
– Low sheet resistance
– Low contact resistance
– Minimal impact on channel profile
– Compatible with polysilicon gate
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 124
 Soft Error
• Electron-hole pairs generated by α-decay
• Electrons from substrate overwrite the
messages in memory capacitors
– Storage capacitors need large capacitance
– Limit further shrinking device feature size
• Silicon-on-insulator (SOI) complete isolate
device from bulk substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 125

α-particle Induced Electron-hole Pairs

+ −
Electron-hole pair −
+
+ −
− +
+ −
− +
+ −
Silicon substrate
− +
α-particle

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 126

 CMOS on SOI Substrate

n+ source/drain p+ source/drain
Gate oxide

Polysilicon

p-Si STI n-Si USG

Buried oxide
Balk Si

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 127

 SOI Formation
• Implanted wafers
– Heavy oxygen ion implantation
– High temperature annealing
• Bonded wafers
– Two wafers
– Grow oxide on one wafer
– High temperature bond wafer bonding
– Polish one wafer until thousand Å away from SiO2
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 128
 Oxygen Ion Implantation

Silicon with lattice damage

Oxygen rich silicon
Balk Si

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 129

 High Temperature Annealing

Single crystal silicon

Silicon dioxide
Balk Si

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 130

Plasma Immersion Ion Implantation
• Deep trench capacitor for DRAM
• Deeper and narrower
• Very difficult to heavily dope both sidewall
and bottom by ion implantation
• Plasma immersion ion implantation (PIII)
• An ion implantation process without precise
ion species and ion energy selection
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 131
 Deep Trench Capacitor
Polysilicon

Dielectric
Layer
Heavily
doped Si

Silicon
Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 132

 ECR Plasma Immersion System
Microwave

Magnet
Coils
ECR
plasma
Magnetic
field line Wafer

Bias RF
E-chuck
Helium

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 133

 Summary of Ion Implantation
• Dope semiconductor
• Better doping method than diffusion
• Easy to control junction depth (by ion
energy) and dopant concentration ( by ion
current and implantation time).
• Anisotropic dopant profile.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 134

 Summary of Ion Implantation
• Ion source
• Extraction
• Analyzer magnets
• Post acceleration
• Charge neutralization system
• Beam stop

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 135

 Summary of Ion Implantation

• Well High energy, low current

• Source/Drain Low energy, high current
• Vt Adjust Low energy, low current
• LDD Low energy, low current

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 136

 Chapter 9, Etch

Hong Xiao, Ph. D.

[email protected]
www2.austin.cc.tx.us/HongXiao/Book.htm

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 1

 Objectives

Upon finishing this course, you should able to:

• Familiar with etch terminology
• Compare wet and dry etch processes
• List four materials need to be etched during IC
processing and list the main dry etch etchants
• Describe etch process in IC fabrication
• Become aware of hazards in etch processes
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 2
 Outline

• Introduction
• Terminology
• Wet and dry etch
• Plasma basics
• Plasma etch processes

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 3

 Definition of Etch
• Process that removes material from surface
• Chemical, physical or combination of the two
• Selective or blanket etch
• Selective etch transfers IC design image on the
photoresist to the surface layer on wafer
• Other applications: Mask making, Printed
electronic board, Artwork, etc.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 4

 Gate Mask Alignment
Gate Mask

Photoresist
Polysilicon
STI USG
P-Well
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 5
 Gate Mask Exposure
Gate Mask

Photoresist
Polysilicon
STI USG
P-Well
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 6
Development/Hard Bake/Inspection

PR
Polysilicon
STI USG
P-Well
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 7
 Etch Polysilicon
Polysilicon

PR

STI USG
P-Well
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 8
 Etch Polysilicon, Continue
Gate Oxide Polysilicon

PR

STI USG
P-Well
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 9
 Strip Photoresist
Gate Oxide Polysilicon

STI USG
P-Well
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 10
 Ion Implantation
Dopant Ions, As+
Gate Oxide Polysilicon

STI n+ n+ USG
P-Well
Hong Xiao, Ph. D.
Source/Drain
www2.austin.cc.tx.us/HongXiao/Book.htm 11
 Rapid Thermal Annealing
Gate Oxide Polysilicon Gate

STI n+ n+ USG
P-Well
Hong Xiao, Ph. D.
Source/Drain
www2.austin.cc.tx.us/HongXiao/Book.htm 12
 Wafer Process Flow
Materials IC Fab

Dielectric Test
Metallization CMP
deposition
Wafers

Thermal Etch Packaging

Implant
Processes PR strip PR strip
Masks

Photo- Final Test

lithography

Design

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 13

 Applications of Etch
• IC Fabrication
• Mask making
• Printed electronic board
• Art work
• Nameplate
• Glassware

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 14

 Wet Etch Profiles
7 - 8 µm 3 µm
Etch
Photoresist Bias PR
Film 3µm Film
Substrate Substrate

•Can’t be used for feature size is smaller than 3 µm

•Replaced by plasma etch for all patterned etch
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 15
 CMOS Cross-Section

Passivation 2 Nitride
Passivation 1 M2 Oxide Al•Cu

W ILD-2, USG
Metal 1, Al•Cu
ILD-1, W-Plug
BPSG
USG n+ n+ STI p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. n-, LDD
www2.austin.cc.tx.us/HongXiao/Book.htm 16
 Etch Terminology
• Etch rate
• Selectivity
• Etch uniformity
• Etch profile
• Wet etch
• Dry etch
• RIE
• Endpoint

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 17

 Etch Rate
Etch rate measures of the how fast the material is
removed from wafer surface.
∆d
d0 d1
Before etch After etch
∆d
Etch Rate = (Å/min)
t

∆d = d0 - d1 (Å) is thickness change and t is etch time (min)

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 18

 Etch Rate
thickness change after etch
Etch rate =
etch time

PE-TEOS PSG film, 1 minute in 6:1 BOE at 22 °C,

Before etch, t = 1.7 µm, After wet etch, t = 1.1 µm

17000-11000
ER = ----------------- = 6000 Å/min
1
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 19
 Etch Uniformity
• Etch uniformity is a measure of the process
repeatability within the wafer (WIW) and wafer
to wafer (WTW)
• Thickness measurements are made before and
after etch at different points
• More measure points, higher the accuracy
• Standard deviation definition are normally used
• Different definitions give different results
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 20
Standard Deviation Non-uniformity
N points measurements

( x1 − x ) 2 + ( x2 − x ) 2 + ( x3 − x ) 2 + ⋅ ⋅ ⋅ + ( x N − x ) 2
σ=
N −1

x1 + x 2 + x3 + ⋅ ⋅ ⋅ + x N
x=
N

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 21

 Max-Min Uniformity
Etch non-uniformity (NU) can be calculated
by using following equation (called Max-Min
uniformity, good for classroom exercise):

NU(%) = (Emax - Emin)/ 2Eave

Emax = Maximum etch rate measured

Emin = Minimum etch rate measured
Eave = Average etch rate
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 22
 Selectivity
• Selectivity is the ratio of etch rates of different
materials.
• Very important in patterned etch
• Selectivity to underneath layer and to photoresist

E1
S=
E2

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 23

 Selectivity
E1
• Selectivity of BPSG to Poly-Si: S =
E2

E2 PR
BPSG

Poly-Si E1
Gate SiO2
Si
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 24
 Selectivity

Etch rate 1
Selectivity =
Etch rate 2

Etch rate for PE-TEOS PSG film is 6000 Å/min,

etch rate for silicon is 30 Å/min, PSG to silicon

6000
Selectivity = ----------------- = 200: 1
30
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 25
 Etch Profiles

PR PR PR PR
Film Film Film
Substrate Substrate

Anisotropic Isotropic

PR PR PR PR
Film Film Film
Substrate Substrate

Anisotropic, tapered Anisotropic, Undercut

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 26
 Etch Profiles

PR PR PR PR
Film Film Film
Substrate Substrate

Anisotropic, Foot Undercut, reversed foot

PR PR PR
Film Film Film
Substrate Substrate

Undercut, reversed tapered Undercut, I-beam

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 27
 Loading Effects: Macro Loading
• ER of a wafer with a larger open area is
different from the wafer with a smaller open
area
• Mainly affects the batch etch process,
• Has a minimal effect on the single wafer
process

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 28

 Loading Effects: Micro Loading
• Smaller hole has a lower etch rate than the
larger holes
• Etchants are more difficult to pass through the
smaller hole
• Etch byproducts are harder to diffuse out
• Lower pressure can minimize the effect.
• Longer MFP, easier for etchants reaching the
film and for etch byproducts to get out
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 29
 Micro Loading

PR PR

Film

Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 30

 Profile Micro Loading

Ion scattering removes

the sidewall PR

Caused by PR
PR sidewall
deposition

Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 31

 Over Etch
• Film thickness and etch rate is not uniform
• Over etch: removes the leftover film
• Selectivity of etched film and substrate
• RIE uses optical endpoint to switch from
main etch to over etch

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 32

 Start Etch Process
PR
∆d
Film

Substrate

Start main etch

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 33

 Main Etch Endpoint
PR Endpoint signal out

Film ∆d

Substrate

Before over etch

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 34

 After Overetch
PR

∆d’
Film

Substrate

After over etch

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 35

 Residues
• Unwanted leftovers
• Causes
– insufficient over etch
– non-volatile etch byproducts

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 36

 Insufficient Over Etch
Film Sidewall
residue

Substrate Substrate

Before etch Insufficient over etch

Film 2 line A

Film 2 line B

Residue from film 2

FilmPh.1 D.
Hong Xiao, www2.austin.cc.tx.us/HongXiao/Book.htm 37
 Non-volatile Residue on Surface

PR Residues PR PR

Film Film Film

Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 38

 Residues
• Adequate over etch
• Removal of non-volatile residues
– Sufficient ion bombardment to dislodge
– Right amount of chemical etch to scoop
• Oxygen plasma ashing: Organic residues
• Wet chemical clean: inorganic residues

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 39

 Wet Etch

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 40

 Wet Etch
• Chemical solution to dissolve the materials on
the wafer surface
• The byproducts are gases, liquids or materials
that are soluble in the etchant solution.
• Three basic steps, etch, rinse and dry

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 41

 Basic Wet Etch Process Steps
Etchant Sink Spin Dryer

D.I. Wafer Rinse

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 42

 Wet Etch
• Pure chemical process, isotropic profile
• Was widely used in IC industry when
feature size was larger than 3 micron
• Still used in advanced IC fabs
– Wafer clean
– Blanket film strip
– Test wafer film strip and clean

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 43

 Wet Etch Profiles
7 - 8 µm 3 µm
Etch
Photoresist Bias PR
Film 3µm Film
Substrate Substrate

•Can’t be used for feature size is smaller than 3 µm

•Replaced by plasma etch for all patterned etch
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 44
 Applications of Wet Etch
• Wet etch can not be used for patterned etch
when CD < 3 µm
• High selectivity
• It is widely used for strip etch process, such
as nitride strip and titanium strip, etc.
• Also widely used for CVD film quality
control (buffered oxide etch or BOE)
• Test wafers strip, clean, and reuse
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 45
 Wet Etching Silicon Dioxide
• Hydrofluoric Acid (HF) Solution
• Normally diluted in buffer solution or DI
water to reduce etch rate.
SiO2 + 6HF → H2SiF6 + 2H2O

• Widely used for CVD film quality control

• BOE: Buffered oxide etch
• WERR: wet etch rate ratio
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 46
 Wide Glass Contact

Photoresist
Wet etch
Dry etch Oxide

Metal

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 47

 Wet Etching Silicon or Poly
• Silicon etch normally use mixture of nitric
acid (HNO3) and hydrofluoric acid (HF)
• HNO3 oxidizes the silicon and HF removes
the oxide at the same time.
• DI water or acetic acid can be used to dilute
the etchant, and reduces the etch rate.

Si + 2HNO3 + 6HF → H2SiF6 + 2HNO2 + 2H2O

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 48

 Isolation Formation
Nitride Pad oxidation,
Silicon LPCVD nitride
Pad oxide
Etch nitride
Silicon & pad oxide

Wet etch
Silicon silicon

Grown SiO2
Silicon

Strip nitride,
Silicon pad oxide
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 49
 Wet Etching Silicon Nitride

• Hot (150 to 200 °C) phosphoric acid H3PO4

Solution
• High selectivity to silicon oxide
• Used for LOCOS and STI nitride strip

Si3N4 + 4 H3PO4 → Si3(PO4)4 + 4NH3

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 50

 Wet Etching Aluminum
• Heated (42 to 45°C) solution
• One example: 80% phosphoric acid, 5%
acetic acid, 5% nitric acid, and 10 % water
• Nitric acid oxidizes aluminum and
phosphoric acid removes aluminum oxide at
the same time.
• Acetic acid slows down the oxidation of the
nitric acid.
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 51
 Wet Etching Titanium
• 1:1 mixture of hydrogen peroxide (H2O2) and
sulfuric acid (H2SO4)
• H2O2 oxidizes titanium to form TiO2
• H2SO4 reacts with TiO2 and removes it
simultaneously
• H2O2 oxidizes silicon and silicide to form SiO2
• H2SO4 doesn’t react with SiO2
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 52
 Self-aligned Titanium Silicide
Formation

Ti Ti
TiSi2 TiSi2 TiSi2 TiSi2
Polysilicon gate Polysilicon gate Polysilicon gate

n- n- n- n- n- n-
n+ Gate oxide n+ Gate oxide n+ Gate oxide
n+ n+ n+

Titanium Silicide annealing Titanium wet

deposition striping
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 53
Factors that Affect Wet Etch Rate

• Temperature
• Chemical concentration
• Composition of film to be etched

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 54

 Wet Chemical Hazards
• HF
• H3PO3
• HNO4

• Corrosive
• Oxidizer
• Special hazard
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 55
 Wet Chemical Hazards
• HF
• Don’t feel when contact
• Attack bone and neutralize by calcium
• Acute pain

• Never assume. Treat all unknown clear

liquid as HF in IC fab.
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 56
 Advantages of Wet Etch
• High selectivity
• Relatively inexpensive equipment
• Batch system, high throughput

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 57

 Disadvantages of Wet Etch
• Isotropic Profile
• Can’t pattern sub-3µm feature

• High chemical usage

• Chemical hazards
– Direct exposure to liquids
– Direct and indirect exposure to fumes
– Potential for explosion
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 58
 Plasma Etch

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 59

 Introduction

• Gas in, gas out

• Plasma generates free radicals and ion
bombardment
• RIE (Reactive Ion Etch)
– combined chemical and physical etch
• Most patterned etches are RIEs

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 60

 Comparison of Wet and Dry Etch

Wet Etch Dry Etch

Etch Bias Unacceptable for < 3µm Minimum
Etch Profile Isotropic Anisotropic to isotropic, controllable
Etch rate High Acceptable, controllable
Selectivity High Acceptable, controllable
Equipment cost Low High
Throughput High (batch) Acceptable, controllable
Chemical usage High Low

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 61

 Plasma Basics
• A plasma is an ionized gas with equal
numbers of positive and negative charges.
• Three important collisions:
– Ionization generates and sustains the plasma
– Excitation-relaxation causes plasma glow
– Disassociation creates reactive free radicals

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 62

 Components of Plasma
• A plasma consists of neutral atoms or
molecules, negative charges (electrons) and
positive charges (ions)

• Quasi-neutral: ni ≈ ne

• Ionization rate: η ≈ ne/(ne + nn)

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 63

 Ionization Rate
• Ionization rate is mainly determined by
electron energy in plasma
• In most plasma processing chambers, the
ionization rate is less than 0.001%.
• The ionization rate of high density plasma
(HDP) source is much higher, about 1%.
• Ionization rate in the core of sun is ~100%.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 64

 Mean Free Path (MFP)
• The average distance a particle can travel
before colliding with another particle.
1
λ =
nσ
• n is the density of the particle
• σ is the collision cross-section of the particle

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 65

 Mean Free Path (MFP)
• Effect of pressure:

λ∝ 1
p

• Higher pressure, shorter MFP

• Lower pressure, longer MFP

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 66

 Vacuum and Plasma
• Pressure too high, MFP will be too short
• Ionization usually require at least 15 eV
• Electrons can’t get enough energy to ionize if
MFP is too short
• Need vacuum and RF to start and maintain
stabilize plasma

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 67

 Ion Bombardment

• Anything close to plasma gets ion bombardment

• Very important for sputtering, RIE and PECVD
• Mainly determined by RF power
• Pressure also affects ion bombardment

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 68

 Ion Bombardment
• Electrons are moving much faster than ions
• Electrons reach electrodes and chamber wall first
• Electrodes are charged negatively, repel electrons
and attract ions
• Charge difference near the surface forms sheath
potential
• Sheath potential accelerates ions towards the
electrode and causes ion bombardment

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 69

 Ion Bombardment

•Ion energy
•Ion density
•Both controlled by RF power

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 70

 Applications of Ion Bombardment
• Help to achieve anisotropic etch profile
− Damaging mechanism
− Blocking mechanism
• Argon sputtering
− Dielectric etch for gap fill
− Metal deposition
• Help control film stress in PECVD processes
− Heavier bombardment, more compressive film
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 71
 Ion Bombardment Control

• Increasing RF power, DC bias increases, ion

density also increases.
• Both ion density and ion bombardment energy
are controlled by RF power.
• RF power is the most important knob controlling
ion bombardment

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 72

 Ion Bombardment Control
• RF power is the main knob to control etch rate
– Increasing RF power, increases etch rate
– usually reduces selectivity
• RF power also used to control film stress for
PECVD processes
– Increasing RF power increase compressive stress

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 73

 Self-Bias
• Different size electrodes
• No net charge build up in plasma
• Charge fluxes on both electrodes are the same
• Smaller electrode has higher charge density
• Larger DC bias between plasma and smaller
electrode

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 74

 Etch Processes

Chemical RIE Physical

Blocking Mechanism Damaging Mechanism

Silicon Etch Oxide Etch
Poly Etch Nitride Etch
Metal Etch
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 75
 Chemical Etch
• Purely chemical reaction
• By products are gases or soluble in etchants
• High selectivity
• Isotropic etch profile
• Examples:
– Wet etch
– Dry strip
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 76
 Physical Etch
• Bombardment with inert ions such as Ar+
• Physically dislodging material from surface
• Plasma process
• Anisotropic profile
• Low selectivity
• Example:
– Argon sputtering etch
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 77
 Reactive Ion Etch (RIE)
• Combination of chemical and physical etch
• Plasma process, ion bombardment plus free radicals
• Misleading name, should be called ion assistant etch
(IAE)
• High and controllable etch rate
• Anisotropic and controllable etch profile
• Good and controllable selectivity
• All patterned etches are RIE processes in 8” fabs
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 78
 RIE Experiment
XeF2
Ar+ ion source Only XeF 2 + Ar+ Ar+ Only

Silicon Etch Rate (Å/min)

XeF2 70
60
50
Shutoff valve
40
30
20
10
Silicon sample
0
Time

Experiment arrangement Experiment results

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 79

 Three Etch Processes

Chemical Etch RIE Physical Etch

Examples Wet etch, strip, RP etch Plasma patterned etches Argon sputtering

Etch rate High to low High, controllable Low

Selectivity Very good Reasonable, controllable Very poor

Etch profile Isotropic Anisotropic, controllable Anisotropic

Endpoint By time or visual Optical By time

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 80

 Etch Process Sequence
Plasma

1 Generation of
Etchant Species Gas Flow

2 Diffusion to Surface
Ion Diffusion into
Bombardment 6
convection flow Sheath
3 Adsorption Boundary layer
layer
5 Desorption
Byproducts

4 Reaction
Film
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 81
 Etch Profile Control
Damaging Blocking

Oxide Epi-silicon
Nitride Polysilicon
Metal

Anisotropic profile control can be achieved by

using ion bombardment from plasma
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 82
 Damaging Mechanism
• Heavy ion bombardment damages chemical bonds
• Exposed surface atoms are easier to react with
etchant free radicals
• Ion bombardment is mainly in vertical direction
• Etch rate on vertical direction is much higher than
on horizontal direction → anisotropic etch

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 83

 Damage Mechanism

PR PR
Exposed Ions
atom Broken
bonds

Etched Atom Etchant free

or molecule Etch Byproduct
radical
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 84
 Blocking Mechanism
• Chemicals deposit on the surface
• Sputtered photoresist and/or byproducts of etch
chemical reaction
• Ion bombardment is mainly in vertical direction
• It prevents deposition to buildup on bottom
• Deposition on sidewall blocks etch process
• Etch process is mainly in vertical direction
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 85
 Blocking Mechanism
PR PR

Knocked Ions
away bottom
deposition Sidewall
deposition

Etched Atom Etchant free

or molecule radical Etch Byproduct
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 86
 Etch Mechanisms and Their
Applications
Pure Reactive Ion Etch (RIE) Pure Physical
Chemical Etch
Etch Blocking mechanism Damaging mechanism

No ion Light ion bombardment Heavy ion bombardment Only ion

bombardment bombardment

PR strip Single crystal silicon etch

Ti strip Polysilicon etch Oxide etch Sputtering etch

Nitride strip Metal etch Nitride etch

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 87

 Benefits of Using Plasma For
Etch Process

• High etch rate

• Anisotropic etch profile

• Optical endpoint

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 88

 Plasma Etch Chambers
• Batch system
• Single wafer system
• High density plasma system
– IPC
– ECR
– Helicon

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 89

 Batch Systems
• High throughput
• Older systems
• Smaller diameter, <150 mm or 6 inch
• Downstream etcher and barrel etch system
– Both are pure chemical etch, no ion bombardment

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 90

 Etch Chamber
• Lower pressure, longer MFP, less collisions
• High ion energy, less ion scattering and better
anisotropy etch profile
• Lower pressure also helps to remove the etch
byproducts
• Etch chambers usually operate at lower pressure

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 91

 Down Stream Plasma Etcher

Microwave Byproducts to
or RF Free Radicals Vacuum Pump

Process
gases Plasma

Remote Plasma Etch Chamber Wafers

Chamber

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 92

 Barrel Etch System

RF RF
Plasma

Etch Wafer
Gas
In To Pump

Etch
RF RF
Tunnel
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 93
 Batch RIE System
Chamber Lid

Wafers

Plasma

To Vacuum Pump
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 94
 Schematic of an RIE System
Process
gases

Process
chamber Plasma Magnet
Wafer coils

Chuck
By-products to
the pump RF Power

Helium For
backside cooling
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 95
 Purpose of Magnets
• Long MFP, insufficient ionization collisions
• In a magnetic field, electron is forced to spin
with very small gyro-radius
• Electrons have to travel longer distance
• More chance to collide
• Increasing plasma density at low pressure

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 96

Effect of Magnetic Field on DC Bias
• Magnetic field increasing electron density
in sheath layer
• Less charge difference in sheath region
• Lower DC Bias
• Effects on ion bombardment
– increasing ion density
– reducing ion energy

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 97

Effect of Magnetic Field on DC Bias

Plasma

B E e Sheath
Wafer

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 98

 Wafer Cooling
• Ion bombardment generate large amount heat
• High temperature can cause PR reticulation
• Need cool wafer to control temperature
• Helium backside cooling is commonly used
• Helium transfer heat from wafer to water
cooled chuck

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 99

 Clamp Ring

Clamp Ring

Wafer
Seal
O-ring

Water-cooled pedestal,
cathode, or chuck

Helium
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 100
 Electrostatic Chuck (E-chuck)
• Helium needs to be pressurized
• Wafer has high pressure at backside because low
chamber pressure
• Need mechanisms to hold wafer
• Either mechanical clamp or E-chuck
• Clamp ring causes particles and shadowing effect
• E-chuck is rapidly replacing clamp ring
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 101
 Electrostatic Chuck

Plasma
Thermal
Conducting,
Wafer
Electrical
Insulating
Layer
Chuck
Bias Voltage

Helium

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 102

 Facts of Helium
Name Helium
Symbol He
Atomic number 2
Atomic weight 4.002602
Discoverer Sir William Ramsay and independently by N. A.
Langley and P. T. Cleve
Discovered at London, England and Uppsala, Sweden
Discovery date 1895
Origin of name From the Greek word "helios" meaning "sun". Its line
radiation (a yellow line at 587.49 nm) was first
detected from the solar spectrum during in solar
eclipse of 1868 in India by French astronomer,

Molar volume 21.0cm 3

Velocity of sound 970 m/sec
Refractive index 1.000035
Melting point 0.95 K or -272.05 C
Boiling point 4.22 K or -268.78 C
Thermal conductivity 0.1513 W m-1 K-1
Applications Cooling gas and carrier gas in CVD and etch
processes
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 103
High Density Plasma (HDP) Sources
• Low pressure is desired for etch process
• Electrons are easily lost due to long MFP by
collide with electrodes or chamber wall
• Hard to generate plasma
• Parallel plate system or capacitive coupled
system can not generate high density plasma
• Different plasma systems are needed to
generate HDP at low pressure
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 104
 HDP Systems
• Inductively coupled plasma (ICP)
• Electron cyclotron resonance (ECR)
• Helicon

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 105

 ICP
• Inductively couple RF power to plasma
• Like a transformer, also called TCP
• Changing magnetic field cause electric field
• Electrons are accelerated in angular direction
• Could achieve high plasma density at low
pressure

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 106

 ICP Chamber
• Upper part of chamber: ceramic or quartz
• Source RF inductively couple with plasma
• Source RF generates plasma and controls ion
density
• Bias RF controls ion bombardment energy
• Ion energy and density independently controlled

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 107

 Schematic of ICP Chamber
Process gases Source RF

Process
chamber Plasma RF coils
Wafer

E-Chuck
Byproducts
to the pump Bias RF

Helium backside cooling

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 108
 ECR
• In magnetic field, electron gyro-frequency
Ωe (MHz) = 2.80 B (Gauss)
• If incident microwave frequency equals to
Ωe
ωMW = Ωe
• Resonance
• Electrons get energy from microwave
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 109
 ECR
• Resonance condition won’t change with fixed
ωMW and B
• Electrons gyro-radius, ρ = vt/Ωe is very small
• Electron can be accelerated to high energy for
ionization collision
• Generate high density plasma at low pressure

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 110

 Illustration of ECR
Electron trajectory

Mic
row
ave
Pow
er

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 111

 Schematic of ECR Chamber
Microwave

Magnetic
Coils ECR
Plasma
Magnetic
field line Wafer

E-chuck Bias RF

Helium
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 112
 Endpoint
• Each atom has its own emission wavelength
• Color of plasma changes when etch
different materials
• Optical sensors can be used to detect the
change and indicate the endpoint for plasma
etch processes

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 113

 Etch Endpoint Wavelengths
Film Etchant Wavelength (Å) Emitter
Al Cl2, BCl3 2614 AlCl
3962 Al
Poly Si Cl2 2882 Si
6156 O
3370 N2
Si3N4 CF4/O2 3862 CN
7037 F
6740 N
7037 F
SiO2 CF4 and CHF3 4835 CO
6156 O
PSG, BPSG CF4 and CHF3 2535 P
W SF6 7037 F
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 114
 Plasma Etch Processes

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 115

 Advantage of the Plasma Etch
• High, controllable etch rate
• Good selectivity
• Anisotropic etch profile

• Disadvantage: expensive, complicated system

– Vacuum, RF, robot, E-chuck and etc.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 116

Etch Mechanisms and Requirements
• Oxide etch using damaging mechanism
• More physical than chemical
• Higher RF power and lower pressure
• Silicon and metal etches using blocking
mechanism
• Chemical than physical
• Usually require less RF power
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 117
 PLASMA ETCH
• Etch dielectric
• Etch single crystal silicon
• Etch polysilicon
• Etch metal
• Summary

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 118

 Dielectric Etch
• Etch oxide
– Doped and undoped silicate glass
– Contact (PSG or BPSG)
– Via (USG, FSG or low-κ dielectric)
• Etch nitride
– STI
– Bonding pad

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 119

 Dielectric Etch
• Fluorine chemistry

4F + SiO2 → SiF4 +2O

• CF4 is commonly used as fluorine source

• NF3 and SF6 have also been used

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 120

 Some Facts About Fluorine
Name Fluorine
Symbol F
Atomic number 9
Atomic weight 18.9984032
Discoverer Henri Moissan
Discovered at France
Discovery date 1886
Origin of name From the Latin word "fluere" meaning "to flow"
Molar volume 11.20 cm3
Velocity of sound No data
Refractive index 1.000195
Melting point 53.53 K or -219.47 C
Boiling point 85.03 K or -187.97 C
Thermal conductivity 0.0277 W m-1 K-1
Applications Free fluorine as the main etchant for silicon oxide and
silicon nitride etching processes
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 121
 Contact Etch
• Holes connect silicon to metal lines
• Doped silicate glass, PSG for BPSG
• Fluorine form CF4 as the main etchant
• CHF3 as polymer precursor to improve
selectivity to silicon and silicide
• Ar to improve damaging effect
• Some people also use O2 or H2
• High selectivity to Si or silicide is required
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 122
 Contact Etch
• Etch PSG or BPSG
• Open contact hole for silicon to metal
interconnections
• Need high selectivity over silicide and
photoresist
• Fluorine chemistry
F + SiO2 SiF4 + O
gas solid gas gas
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 123
 CMOS Cross-section
Contact Etch
Titanium/Titanium Nitride TiN ARC Titanium

Al-Cu Alloy

W BPSG

STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 124
 Challenge for Contact Etch
• Contact holes to polyside gate and local
interconnection are about half of the depth
of source/drain contact holes
• Require high (B)PSG to silicide selectivity

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 125

 Contact Etch

Photoresist

BPSG
∆t
t
STI n+
TiSi2
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 126
 Contact Etch
• F/C ratio F/C > 3, etch dominant
F/C < 2, polymerization
• When etching oxide, oxygen byproduct can
react with C to free more fluorine
• When etching silicon or silicide, no oxygen
releasing, fluorine is consumed, F/C ratio
drop below 2 and start polymer deposition
• Polymer blocks further etch process
• High BPSG-to-TiSi2 selectivity
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 127
 Dielectric Etch
plasma

CF4 → CF3 + F

plasma

4F + SiO2 → SiF4 + 2O

plasma

12F + TiSi2 → TiF4 + 2SiF4

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 128
F/C Ratio, DC Bias and Polymerization
C2F4 C2F6 CF4

-200
Bias (Volts)

Etching
-100

Polymerization

0
1 2 3 4 F/C Ratio
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 129
 Via Etch
• Etch USG
• Open via hole for metal to metal interconnections
• Need high selectivity over metal and photoresist
• Fluorine chemistry

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 130

 CMOS Cross-section
Via Etch
Metal 2 Al-Cu Alloy

IMD 1 USG

M1 Al-Cu Alloy

W BPSG

STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 131
 Etch Via
• PR mask
• Fluorine as the main etchant
• CF4, CHF3 and Ar are used for the etch
process. O2 or H2 also can be used
• High selectivity over metal
• Avoiding metal sputtering
• Dual damascene etch
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 132
 Summary of Dielectric Etch

Name of etch Hard mask Contact Via Bonding pad

Materials Si3N4 or SiO2 PSG or BPSG USG or FSG Nitride and oxide

Etchants CF4, CHF 3 CF4, CHF3, ... CF4, CHF3, ... CF4, CHF3, ...

Underneath layer Si, Cu, Au, Poly or silicide Metal Metal

Endpoints CN, N or O P, O, and F O, Al and F O, Al and F

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 133

 Single Crystal Silicon Etch
• Shallow trench isolation (STI)
• Deep trench for capacitor
• Hard mask, silicon nitride and oxide
• PR may cause substrate contamination
• Bromine chemistry
• HBr as the main etchant

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 134

 CMOS Cross-Section
Single Crystal
Silicon Etch TiN ARC Titanium

Al-Cu Alloy

W BPSG

STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 135
 Deep Trench Capacitor
Heavily Doped Silicon
PR Poly-Si
SiO2 SiO2

SiO2

Si Si Si
Etch hard mask Etch silicon Capacitor Formation
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 136
 Some Facts About Bromine
Name Bromine
Symbol Br
Atomic number 35
Atomic weight 79.904
Discoverer Antoine-J. Balard
Discovered at France
Discovery date 1826
Origin of name From the Greek word "bromos" meaning "stench"
Molar volume 19.78 cm 3
Velocity of sound No data
Resistivity > 1018 µΩ cm
Refractive index 1.001132
Melting point -7.2 C
Boiling point 59 C
Thermal conductivity 0.12 W m-1 K-1
Applications Free bromine as the main etchant for single crystal
silicon etching processes
Source HBr
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 137
Single Crystal Silicon Etch Chemistry
plasma

HBr → H + Br
Br + Si → SiBr4

• Small amount O2 for sidewall passivation

• A little NF3 for preventing black silicon
• Endpoint by time
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 138
 Polysilicon Etch
• Gates and local interconnections
– Most critical etch process, smallest CD
• Capacitor electrodes for DRAM
• Require high selectivity over silicon dioxide
• Cl2 chemistry
Cl + Si SiCl4
gas solid gas
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 139
 Some Facts About Chlorine
Name Chlorine
Symbol Cl
Atomic number 17
Atomic weight 35.4527
Discoverer Carl William Scheele
Discovered at Sweden
Discovery date 1774
Origin of name From the Greek word "chloros" meaning "pale green"
Molar volume 17.39 cm3
Velocity of sound 206 m/sec
Resistivity > 1010 µΩ cm
Refractive index 1.000773
Melting point -101.4 C or 171.6 K
Boiling point -33.89 C or 239.11 K
Thermal conductivity 0.0089 W m-1 K-1
Applications Used as the main etchant for poly silicon and metal
etching processes. Polysilicon, epitaxy silicon
deposition chamber clean.
Sources Cl2, HCl
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 140
 Gate etch

Polysilicon gate

STI USG
P-Well N-Well
P-Epi
P-Wafer

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 141

 Polysilicon Etch
• Cl2 as the main etchant
• HBr for sidewall passivation, blocking
mechanism
• Add O2 in over etch step to improve
selectivity to SiO2.
• High selectivity over SiO2 is required

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 142

 Polysilicon Etch

Photoresist

Gate Oxide SiCl4

Cl Polysilicon Cl

Single Crystal Silicon Substrate

•High poly-to-oxide selectivity is required
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 143
 Polysilicon Etch
Poly-Si on
Poly-Si on Gate sidewall
sidewall PR oxide

SiO 2 Poly

p+
N-well

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 144

 Polysilicon Etch
Process steps:
• Breakthrough
– Removal of native oxide, energetic Ar+ bombardment
• Main etch
– High poly etch rate, Cl and HBr chemistry
– Endpoint on O line
• Over etch
– Reduce power, add O 2 for high selectivity over SiO 2
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 145
 Metal Etch
• Etch TiN/Al·Cu/Ti metal stack to form
metal interconnection
• Usually use Cl2 + BCl3 chemistry
• Need etch away Cu in Al either physically
or chemically
• Need strip photoresist before wafer
exposure to moisture in atmosphere

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 146

 CMOS Cross-section
Metal Etch
Titanium/Titanium Nitride TiN ARC Titanium

Al-Cu Alloy

W BPSG

STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 147
 Etch Metal
• For metal interconnection
• Metal stack: TiN/Al•Cu/Ti
• Cl2 as the main etchant
• BCl3, N2 are used for sidewall passivation
• O2 is used to improve selectivity to oxide
• Main challenges: etch profile and avoiding
etch residue
• Metal grain size can affect etch process
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 148
 Metal Etch Chemistries
plasma

Cl2 → Cl + Cl
plasma

Cl + Al → AlCl3
plasma

Cl + TiN → TiCl4 + N
plasma

Cl + Ti → TiCl4
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 149
 Photoresist Dry Strip
• Remote plasma source
– Free radicals without ion bombardment
• High pressure, microwave plasma
• Very important to strip chlorine containing
PR after metal etch to avoid metal corrosion
• In-situ with etch process in a cluster tool
• Improve throughput and yield

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 150

 Photoresist Dry Strip
• O2, H2O chemistry
plasma

H2O → 2H + O

H + Cl → HCl

O + PR → H2O + CO + CO2 +
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 151
 Photoresist Strip Process
Microwave Remote plasma
chamber
H2O, O2 Plasma

Process chamber
Wafer with O H O O H O H O
photoresist

H2O, CO2, HCl… Heated plate

To the pump
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 152
 Dry Chemical Etch
• Unstable gases, such as XeF2 and O3
• Remote plasma source free radicals
• Free from ion bombardment
• Thin film strip and wineglass contact etch
• In-situ with RIE chambers on one frame
• Nitride strip in both LOCOS and STI
• Nitride and Poly-Si strip in PBL
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 153
 Blanket Dry Etch
• No photoresist. Etchback and film strip.
• Argon sputtering etch
– Dielectric thin film applications
– native oxide clean prior to metal deposition
• RIE etchback system
– Can be used in-line with dielectric CVD tools
– Sidewall spacer formation
– PR or SOG planarization etchback
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 154
 CVD O3-TEOS USG

Polysilicon Gate

n- LDD n- LDD
Gate Oxide

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 155

 O3-TEOS USG Etchback

Polysilicon Gate

n- LDD n- LDD
Gate Oxide

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 156

 O3-TEOS USG Etchback

Polysilicon Gate

n- LDD n- LDD
Gate Oxide

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 157

 O3-TEOS USG Etchback

Polysilicon Gate

n- LDD n- LDD
Gate Oxide

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 158

 O3-TEOS USG Etchback

Polysilicon Gate

n- LDD n- LDD
Gate Oxide

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 159

 O3-TEOS USG Etchback

Polysilicon Gate

n- LDD n- LDD
Gate Oxide

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 160

 O3-TEOS USG Etchback

Polysilicon Gate

n- LDD n- LDD
Gate Oxide

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 161

 O3-TEOS USG Etchback

Sidewall Sidewall
Polysilicon Gate Spacer
Spacer

n- LDD n- LDD
Gate Oxide

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 162

 Etch Safety
• Corrosive and toxic gases
– Cl2, BCl3, SiF4 and HBr
– Could be fatal if inhalation at a high
concentration (>1000 ppm)
• RF power can cause electric shock
• Can be lethal at high power

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 163

 Etch Safety
• All moving parts, are mechanical hazards
• May cause injury if one does not stay clear
• Lock-out, tag-out

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 164

 RF Power
• Increasing RF power increases ion density,
ion bombardment energy, and number of
free radicals
• Etch rate will increase significantly
• The most important “knob” that controls
etch rate
• Check RF system first if etch rate is out of
specifications
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 165
 Plasma Etch Trends

Selectivity
Etch Rate

ER Selectivity

RF Power

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 166

 Pressure
• Pressure affects plasma density and shape
• Has strong effects on etch uniformity

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 167

 Etch Trends
More Physical

RF ↑
More Chemical

B↑
Pressure ↑

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 168

 Future Trends for Etch Processes
• High density plasma (HDP) at low pressure
– Improve profile control
– Increasing plasma density
– Ion bombardment flux
• Independent ion flux and ion energy control
• HDP etchers in IC processing: ICP & ECR
• Helicon plasma source: ~100% ionization,
candidate for future etch chamber design
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 169
 Helicon Plasma Source

Antenna
Source RF

Magnetic
Coils plasma

Magnetic Wafer
field line
Bias RF
E-chuck
Helium

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 170

 Future Trends for Etch Processes
• 300 mm system
• Plasma uniformity control
• Plasma position control

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 171

 Copper Etch?
• Cl2 chemistry
• Low pressure (< 5 mTorr)
• High temperature (>250 °C)
– Cannot use photoresist
– Need CVD oxide hard mask
• Competition with dual damascene process
• Very unlike can be used in IC production

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 172

Direct Hard Masking Photolithography
PECVD Si-PR
Substrate

UV Mask
Exposure, partially
oxidation of Si-PR
Substrate

Cl2 plasma removes

Substrate unexposed Si-PR
SiO2
Down Stream O2 fully
Substrate oxidation of Si-PR
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 173
 Future Trends
• Challenges ahead:
• Etch high-κ materials of gate dielectric and
capacitor dielectric
• Etch low-κ materials of inter-metal
dielectric

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 174

 Summary
• Plasma etch is widely used for patterned etch
process to transfer image on photoresist to
surface materials.
• Epi, poly, oxide and metal
• Fluorine for oxide etch
• HBr for single crystal silicon etch
• Chlorine for polysilicon and metal etch
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 175
 Summary
• Certain vacuum and constant RF power are
need to strike and maintain a stable plasma
• RF power is main knob to control etch rate
• Pressure affects uniformity and etch profile
• High plasma density at low pressure are
desired for etch deep sub-micron features.
• Dry chemical etch can be achieved with
remote plasma source
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 176
 Chapter 10
CVD and Dielectric
Thin Film
Hong Xiao, Ph. D.
[email protected]
www2.austin.cc.tx.us/HongXiao/Book.htm

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 1

 Objectives
• Identify at least four CVD applications
• Describe CVD process sequence
• List the two deposition regimes and
describe their relation to temperature
• List two dielectric thin films
• Name the two most commonly used silicon
precursors for dielectric CVD
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 2
 CVD Oxide vs. Grown Oxide

SiO2
SiO2
Si Si Si

Grown film Bare silicon Deposited film

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 3

 CVD Oxide vs. Grown Oxide
Grow CVD

• Oxygen is from gas • Both oxygen and

phase silicon are from gas
• Silicon from substrate phase
• Oxide grow into • Deposit on substrate
silicon surface
• Higher quality • Lower temperature
• Higher growth rate
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 4
Dielectric Thin Film Applications
• Multi-level metal interconnection
• CVD and SOG plus CVD dielectrics
• Shallow trench isolation (STI)
• Sidewall spacer for salicide, LDD, and the
source/drain diffusion buffer
• The passivation dielectric (PD)
• Dielectric ARC for feature size < 0.25 µm
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 5
Dielectric Thin Film Applications
• Inter layer dielectric, or ILD, include PMD
and IMD
• Pre-metal dielectric: PMD
– normally PSG or BPSG
– Temperature limited by thermal budget
• Inter-metal dielectric: IMD
– USG or FSG
– Normally deposited around 400 °C
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 6
 Figure 10.2
Nitride PD2
Oxide
Metal 2, Al•Cu Al•Cu
PD1
ARC
W USG
IMD or
ILD2
Metal 1, Al•Cu
PMD or
W WCVD
ILD1 BPSG

STI n+ n+ p+ p+ STI
USG
P-well N-well
Sidewall
spacer P-epi TiN
P-wafer CVD

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 7

 Dielectric Processes

An N-layer metal interconnection IC chip with

STI, the minimum number of dielectric process is:

Dielectric layer = 1 +1 + 1 + (N−1) + 1 = N + 3

STI spacer PMD IMD PD

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 8

 CVD
• Chemical Vapor Deposition

• Chemical gases or vapors react on the surface

of solid, produce solid byproduct on the
surface in the form of thin film. Other
byproducts are volatile and leave the surface.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 9

 CVD Applications
FILMS PRECURSORS

Si (poly) SiH 4 (silane)

Semiconductor SiCl2H 2 (DCS)
Si (epi) SiCl3H (TCS)
SiCl4 (Siltet)
LPCVD SiH 4, O 2
SiO 2 (glass) PECVD SiH4, N 2O
Dielectrics PECVD Si(OC2H 5) 4 (TEOS), O2
LPCVD TEOS
APCVD&SACVDTM TEOS, O 3 (ozone)
Oxynitride SiH 4, N 2O, N 2, NH3
PECVD SiH 4, N2 , NH3
Si3N4 LPCVD SiH 4, N2 , NH3
LPCVD C8H 22N2Si (BTBAS)
W (Tungsten) WF6 (Tungsten hexafluoride), SiH4, H 2
WSi2 WF6 (Tungsten hexafluoride), SiH4, H 2
Conductors TiN Ti[N (CH 3) 2]4 (TDMAT)
Ti TiCl4
Cu
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 10
 CVD
• Gas or vapor phase precursors are introduced into the reactor
• Precursors across the boundary layer and reach the surface
• Precursors adsorb on the substrate surface
• Adsorbed precursors migrate on the substrate surface
• Chemical reaction on the substrate surface
• Solid byproducts form nuclei on the substrate surface
• Nuclei grow into islands
• Islands merge into the continuous thin film
• Other gaseous byproducts desorb from the substrate surface
• Gaseous byproducts diffuse across the boundary layer
• Gaseous byproducts flow out of the reactor.
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 11
 Figure 10.3
Precursors
Showerhead

Forced
convection
region

Boundary
Byproducts Reactants
layer
Pedestal
Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 12
 Deposition Process

Precursor arrives surface Migrate on the surface

Nucleation:
React on the surface
Island formation
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 13
 Deposition Process

Islands grow,
Islands grow cross-section

Islands merge Continuous thin film

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 14
 CVD Processes

• APCVD

• LPCVD

• PECVD

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 15

 Atmospheric Pressure CVD
• CVD process taking place at atmospheric
pressure
• APCVD process has been used to deposit
silicon oxide and silicon nitride
• APCVD O3-TEOS oxide process is widely
used in the semiconductor industry,
especially in STI and PMD applications
• Conveyor belt system with in-situ belt clean
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 16
 APCVD Reactor
N2 Process Gas N2

Wafers
Wafers

Heater

Belt Clean Conveyor

Station Exhaust Belt
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 17
 Question
• A semiconductor manufacturer has its R&D
lab on the coast near sea level and one of its
manufacturing fabs on a high altitude
plateau. It was found that the APCVD
processes developed in the R&D lab
couldn’t directly apply in that particular fab.
Why?

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 18

 Answer
• On a high-altitude plateau, the atmospheric
pressure is significantly lower than at sea
level. Because earlier APCVD reactor
didn’t have a pressure-control system, a
process that worked fine in the R&D lab at
sea level might not work well in the high
altitude fab because of pressure difference

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 19

 LPCVD

• Longer MFP
• Good step coverage & uniformity
• Vertical loading of wafer
• Fewer particles and increased productivity
• Less dependence on gas flow
• Vertical and horizontal furnace

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 20

 Horizontal Conduction-
Convection-heated LPCVD
• Adaptation of horizontal tube furnace

– Low pressure: from 0.25 to 2 Torr

– Used mainly for polysilicon, silicon dioxide
and silicon nitride films
– Can process 200 wafers per batch

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 21

 LPCVD System
Pressure
Sensor Wafers

Heating Coils
Loading To Pump
Door

Quartz
Process Gas Inlet Wafer Boat Tube

Center Zone
Temperature
Flat Zone
Distance
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 22
 PECVD
• Developed when silicon nitride replaced
silicon dioxide for passivation layer.

• High deposition rate at relatively low temp.

• RF induces plasma field in deposition gas
• Stress control by RF
• Chamber plasma clean.
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 23
 Plasma Enhanced CVD System
Process RF power
gases
Process
chamber
Plasma
Wafer

By-products to Heated plate

the pump

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 24

 Step Coverage
• A measurement of the deposited film
reproducing the slope of a step on the
substrate surface
• One of the most important specifications
– Sidewall step coverage
– Bottom step coverage
– Conformality
– Overhang

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 25

 Step Coverage and Conformity
CVD thin film a
c

Structure h
b
d
w
Substrate

Sidewall step coverage = b/a Bottom step coverage = d/a

Conformity = b/c Overhang = (c - b)/b
Aspect ratio = h/w
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 26
 Factors Affect Step Coverage
• Arriving angle of precursor
• Surface mobility of adsorbed precursor

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 27

 Arriving Angles

180° 270°
B A
90°
C

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 28

 Arriving Angle
• Corner A: 270°, corner C: 90°
• More precursors at corner A
• More deposition
• Form the overhang
• Overhang can cause voids or keyholes

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 29

 Void Formation Process

Metal Dielectric

Metal Dielectric

Void
Metal Dielectric
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 30
 Control of Arriving Angle
• |Changing pressure
• Tapering opening

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 31

 Step Coverage, Pressure and
Surface Mobility

APCVD LPCVD
High mobility
No mobility No mobility

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 32

 Arriving Angles, Contact Holes
Larger Smaller
arriving arriving
angle angle

PSG

Nitride
Silicon

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 33

 Gap Fill
• Fill a gap without voids
• Voids: cause defect and reliability problems
• Deposition/Etchback/Deposition
– Silane and PE-TEOS film
• Conformal deposition
– O3-TEOS and tungsten CVD
• High density plasma CVD
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 34
 Gap Fill
• PMD: zero tolerance voids
– Tungsten can be deposited into these voids
– Causing shorts
• IMD: voids below metal may tolerable
– reducing κ
– process gas could come out later and cause
reliability problem

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 35

 Void in PMD
Top view Void
Before W CVD

Silicide

Silicide

Sidewall spacers Contact

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 36
Unwanted W Line Between Gates
Top view Tungsten
After W CVD

Silicide

Silicide

Sidewall spacers W plug

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 37
 Deposition/Etchback/Deposition
USG
Dep.
Al·Cu

Etch USG
Al·Cu

Dep.
USG

Al·Cu

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 38

 Conformal Deposition Gap Fill

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 39

 Conformal Deposition Gap Fill

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 40

 Conformal Deposition Gap Fill

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 41

 HDP CVD Gap Fill

Metal Metal Metal

Metal Metal Metal

Metal Metal Metal

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 42

 Surface Adsorption
• Determine precursors surface mobility
• Affect step coverage and gap fill

• Physical adsorption (physisorption)

• Chemical adsorption (chemisorption)

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 43

 Chemisorption
• Actual chemical bonds between surface atom
and the adsorbed precursor molecule
• Bonding energy usually exceeding 2 eV
• Low surface mobility
• Ion bombardment with10 to 20 eV energy in
PECVD processes can cause some surface
migration of chemisorbed precursors

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 44

 Physisorption
• Weak bond between surface and precursor
• Bonding energy usually less than 0.5 eV
– Hydrogen bonding
– Van der Waals forces
• Ion bombardment and thermal energy at 400 °C
can cause migration of physisorbed precursors
• High surface mobility
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 45
Bonding Adsorptions
energy

Distance
from surface

Physisorbed precursor

Chemisorbed precursor

Substrate Surface
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 46
 Dielectric CVD Precursors
• Silane (SiH4)
• TEOS (tetra-ethyl-oxy-silane, Si(OC2H5)4)

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 47

 CVD Precursor: Silane
• Dielectric CVD
– PECVD passivation dielectric depositions
– PMD barrier nitride layer
– Dielectric anti reflective coating (DARC)
– High density plasma CVD oxide processes
• LPCVD poly-Si and silicon nitride
• Metal CVD
– W CVD process for nucleation step
– Silicon source for WSix deposition
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 48
 Dielectric CVD Precursor: Silane
• Pyrophoric (ignite itself), explosive, and toxic
• Open silane line without thoroughly purging
can cause fire or minor explosion and dust line

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 49

 Structure of Silane Molecule

H
H
H
H Si H
Si

H H

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 50

 CVD Precursor Adsorption: Silane
• Silane molecule is perfectly symmetrical
• Neither chemisorb nor physisorb
• Fragments of silane, SiH3, SiH2, or SiH, can
easily form chemical bonds with surface
• Low surface mobility, overhangs and poor step
coverage

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 51

 CVD Precursor Adsorption: TEOS
• TEOS (tetra-ethyl-oxy-silane, Si(OC2H5)4)
• Big organic molecule
• TEOS molecule is not perfectly symmetric
• Can form hydrogen bond and physisorb
• High surface mobility
• Good step coverage, conformality, and gap fill
• Widely used for oxide deposition
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 52
 H

H C H
TEOS Molecule
H C H

H H O H H

H C C O Si O C C H

H H O H H

H C H

H C H

Hong Xiao, Ph. D. H

www2.austin.cc.tx.us/HongXiao/Book.htm 53
 TEOS Applications
• STI, sidewall spacer, PMD, and IMD
• Most dielectric CVD processes are TEOS
based oxide processes

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 54

 TEOS Vapor Pressure
100 100
Vapor Pressure (Torr)

30 30

10 10

3 3

1 1
10 20 30 40 50 60 70 80 90 100 110
Temperature (°C)
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 55
 TEOS Delivery
• A liquid at room temperature with boiling
point at the sea level is 168 °C
– As a reference, boiling point of water (H2O) at sea
level is 100 °C
• Need delivery system to send its vapor to
process chamber
• Boiler, bubbler, and injection systems

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 56

 Boiler System
Heated gas line Heated foreline

Process
MFC Pump
chamber

TEOS

Thermostatic oven

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 57

 Bubbler System
Heated gas line

Carrier gas Process

MFC MFM
chamber

Liquid
TEOS
Pump

Thermostatic
oven Carrier gas
bubbles
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 58
 Injection System
Carrier
gas MFC

Pressurize
gas
Injection Process
LFC
valve chamber

Liquid TEOS
flow Heated gas
line, TEOS Pump
Liquid TEOS vapor and
carrier gas
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 59
 Sticking Coefficient
• The probability that precursor atom forms
chemical bond with surface atom in one
collision
• Can be calculated by comparing the calculated
deposition rate with 100% sticking coefficient
and the measured actual deposition rate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 60

 Sticking Coefficient
Precursors Sticking Coefficient

SiH4 3 ×10-4 to 3 ×10-5

SiH3 0.04 to 0.08

SiH2 0.15

SiH 0.94

TEOS 10-3

WF6 10-4

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 61

Step Coverage of TEOS and Silane Oxide

TEOS

Silane

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 62

 Question
• Why don’t people apply TEOS as the
silicon source gas for the silicon nitride
deposition to get better step coverage for the
nitride film

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 63

 Answer
• In the TEOS molecule, the silicon atom is
bonded with four oxygen atoms. It is almost
impossible to strip all oxygen atoms and
have silicon bonded only with nitrogen.
Therefore, TEOS is mainly used for the
oxide deposition and the nitride deposition
normally uses silane as the silicon source
gas
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 64
 Chemical Reaction Rate

C.R. = A exp (-Ea/kT)

Ea
Precursor

∆Η Byproduct

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 65

 Deposition Regimes
Mass-transport-limited Surface-reaction-
regime limited regime
ln D.R.

Slope = −Ea /k

Gas-phase-nucleation
regime

1/T
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 66
 Surface-Reaction-Limited Regime
• Chemical reaction rate can’t match precursor
diffusion and adsorption rates; precursors pile
up on the substrate surface and wait their turn
to react.
D.R. = C.R. [B] [C] []…
• Deposition rate is very sensitive to temperature

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 67

 Mass-Transport-Limited Regime
• When the surface chemical reaction rate is high
enough, the chemical precursors react
immediately when they adsorb on the substrate
surface.
• Deposition rate = D dn/dx [B] [C] []…
• Deposition rate is insensitive to temperature
• Mainly controlled by gas flow rates

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 68

 Deposition Rage Regimes
Deposition rate

Dep. rate
insensitive to
temperature
Dep. rate
sensitive to
temperature

Temperature
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 69
 CVD Reactor Deposition Regime
• Most single wafer process reactors are
designed in mass-transport-limited regime
• It is easier to control the gas flow rate
• Plasma or unstable chemicals such as ozone
are used to achieve mass-transport-limited-
regime at relatively low temperature

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 70

Applications of Dielectric Thin film

• Shallow trench isolation (STI, USG)

• Sidewall Spacer (USG)
• Pre-metal dielectric (PMD, PSG or BPSG)
• Inter-metal dielectric (IMD, USG or FSG)
• Anti-reflection coating (ARC, SiON)
• Passivation dielectric (PD, Oxide/Nitride)

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 71

Dielectric CVD, Oxide and Nitride
Oxide (SiO 2) Nitride (Si3N4)

Similar dielectric strength, > 1×10 7 Similar dielectric strength, > 1×107 V/cm
V/cm

Lower dielectric constant, κ = 3.9 Higher dielectric constant, κ = 7.0

Not a good barrier for moisture and Good barrier for moisture and mobile ion
mobile ion (Na+) (Na+)

Transparent to UV Conventional nitride opaque to UV

Can be doped with P and B

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 72

 Shallow Trench Isolation (STI)
Grow pad oxide Etch nitride, Grow barrier CMP USG Strip nitride
Deposition nitride oxide and oxide Anneal USG and oxide
silicon
CVD USG
trench fill

USG USG USG

Si Si Si Si Si

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 73

 Shallow Trench Isolation (STI)

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 74

 Sidewall Spacer Formation
Sidewall spacer
Oxide

Poly gate Poly gate

Substrate Substrate

•Lightly doped drain (LDD)

•Self aligned silicide (Salicide)

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 75

 PMD

• Doped oxide
• PSG or BPSG
• Phosphorus: gettering sodium and reduce flow
temperature.
• Boron: further reduces flow temperature without
excessive phosphorus

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 76

 Sodium Ion Turn-on the MOSFET
Sodium ions
VG = 0 VD VG = 0
Electron flow VD > 0

“Metal” Gate “Metal” Gate

SiO2 Thin oxide −+−+−+−+−+−+−+−+

n+ n+ n+ n+
p-Si p-Si
Source Drain Source Drain

Electrons
Normal off Turn on by Na +

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 77

 PMD
• More phosphorus, lower reflow temperature
• >7wt% phosphorus, hygroscope
P2O5 + 3H2O → 2H3PO4
• H3PO4 etches aluminum causes metal corrosion
• Too much boron will cause crystallization of
boric acid. H3BO3.
• Limit, P% + B% < 10%
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 78
 Question
• Silicon nitride is a better sodium barrier
layer than silicon oxide. Why don’t people
just use nitride for PMD layer?

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 79

 Answer
• Silicon nitride has higher dielectric constant
• Using nitride can cause longer RC time
delay and reduce circuit speed
• A thin layer of nitride (~ 200 Å) is
commonly used as a diffusion barrier layer
in the PMD application
• Prevent diffusion of phosphorus and boron
from BPSG diffusing into source/drain
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 80
PSG Reflow at 1100 °C, N2, 20 min.

0% 2.2%

4.6% 7.2%

Source: VLSI Technology, by S.M. Sze

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 81
 Some Facts about Sodium
Name Sodium
Symbol Na
Atomic number 11
Atomic weight 22.989770
Discoverer Sir Humphrey Davy
Discovered at England
Discovery date 1807
Origin of name From the English word "soda" (the origin of the
symbol Na comes from the Latin word "natrium")
Density of solid 0.968 g/cm3
Molar volume 23.78 cm3
Velocity of sound 3200 m/sec
Electrical resistivity 4.7 µΩ⋅ cm
Reflectivity No data
Melting point 97.72 °C
Boiling point 882.85 °C
Thermal conductivity 140 W m-1 K-1
Coefficient of linear thermal 71×10-6 K-1
expansion
Applications Major contaminant, needs to be strictly controlled
Main removal agent HCl
Barrier materials used Silicon nitride and PSG
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 82
 4×4 BPSG Reflow at 850 °C, 30
Minutes in N2 Ambient

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 83

 Development of PMD Processes

Dimension PMD Planarization Reflow temperature

> 2 µm PSG Reflow 1100°C

2 - 0.35 µm BPSG Reflow 850 - 900 °C

0.25 µm BPSG Reflow + CMP 750°C

0.18 µm PSG CMP -

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 84

 PMD Applications Roadmap
Feature 0.8 0.5 0.35 0.25 0.18
Size (µm)
Year 1989 1992 1995 1998 2000
Wafer 150 200 300
Size (mm)
O3-TEOS BPSG
Thermal Flow or RTP/CMP

O3-TEOS PSG + PE-PSG

APCVD Silane BPSG CMP
PE-TEOS BPSG
HDP PSG + PE-PSG
LPCVD BPSG
CMP
Thermal Flow Low-k Dielectric
CMP

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 85

 IMD

• Inter-metal dielectric
• Undoped silicate glass (USG) or FSG
• SOG
• Gap fill and planarization
• Temperature limited by metal melting
– Normally 400 °C
• PE-TEOS, O3-TEOS, and HDP
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 86
 TEOS
H

• Tetraethyloxysilane, H C H

Si(OC2H5)4 H C H

O
• Liquid silicon source H H H H

H C C O Si O C C H
• Commonly used for
H H O H H
SiO2 deposition
H C H
• Good step coverage
H C H
and gap fill
H

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 87

 PE-TEOS
• Plasma-enhanced TEOS CVD processes
• TEOS and O2
• Most commonly used dielectric CVD process
• Deposit USG at ~400 °C
• Mainly for IMD

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 88

 Spin-on Glass (SOG) Processes

METAL 4

IMD 3

METAL 3

IMD 2

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 89

 PE-TEOS

• PE-TEOS
Photo courtesy:
Applied Materials • Sputtering
etchback

• PE-TEOS

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 90

 O3-TEOS
• TEOS and Ozone

• O3 → O2 + O (half-life time: 86 hours at 22 °C,

< 1ms at 400 °C)
• O + TEOS → USG + other volatile byproducts

• Excellent step coverage and gap fill.

• Applied for IMD and PMD
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 91
 O3-TEOS vs PE-TEOS
PE-TEOS Ozone-TEOS

Step coverage: 50% Step coverage: 90%

Conformality: 87.5% Conformality: 100%
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 92
 High Density Plasma CVD
• HDP-CVD: deposition and sputtering etch at
the same time.
• USG for STI application
• USG and FSG for IMD applications
• PMD for PMD application

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 93

 HDP-CVD, IMD Application

Metal Metal Metal

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 94

 Oxide CMP

Metal Metal Metal

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 95

 Passivation
• Nitride and oxide
• Nitride is very good barrier layer, oxide help
nitride stick with metal
• Silane process
• NH3, N2 and nitrogen precursors, N2O as
oxygen precursor
• In-situ CVD process

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 96

 Dielectric Thin Film
Characteristics
• Refractive index
• Thickness
• Uniformity
• Stress
• Particles

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 97

 Refractive Index

Speed of light in vacuum

Refractive index, n =
Speed of light in the film

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 98

 Refractive Index
Incident light

θ1 n1 sin θ1 = n2 sin θ2
Vacuum
n1

Film
n2
θ2 Refractive light

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 99

 Film Information from R.I.
Refractive index

Oxygen rich
Nitrogen rich 4.0 Polysilicon

Oxygen rich
Nitrogen rich 2.01 Si3N4 Silicon rich
Oxynitride
1.46 SiO2 Nitrogen rich
Oxygen rich Silicon rich
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 100
 Ellipsometry R.I. Measurement
Elliptically Polarized
Reflected Light
Linearly Polarized Incident Light

p
s

n1, k1, t1
n2, k2

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 101

 Illustration of Prism Coupler

Laser light Photo detector

Thin film θ

Substrate

Coupling head

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 102

 Reflected Light Intensity vs.
Incidence Angle
Reflected

Modes

20° 10° 0° -10° -20° θ

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 103

 Metricon Model 2010 Prism
Coupler

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 104

 Comparison of the Two Methods
Ellipsometry Prism coupler

• Need know rough film • Need certain thickness

thickness before hand of the film, > 3000 Å
• Can measure thickness • Can measure thickness
if R.I. is know if film thick enough to
support enough modes

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 105

 Thickness Measurement
• One of the most important measurements
for dielectric thin film processes.
• Determines
– Film deposition rate
– Wet etch rate
– Shrinkage

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 106

 Dielectric Thin Film Thickness
Measurement
Human eye or
Incident light photodetector
1
2

t Dielectric film, n(λ)

Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 107

 Dielectric Thin Film Thickness
Measurement

• Different thickness has different color

• Tilting wafer also changes the color

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 108

 Question

• If you see some beautiful color rings on a wafer

with a CVD dielectric layer, what is your
conclusion?

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 109

 Answer

• Color change indicates the dielectric thin film

thickness change, thus we know the film with
the color rings must have problem with
thickness uniformity, which is most likely
caused by a non-uniform thin film deposition
process.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 110

 Question

• Why does the thin film color change when one

look at the wafer from different angle?

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 111

 Answer
• When one looking at wafer from a different
angle, phase shift will change, thus wavelength
for constructive interference will change, which
causes color change
• It is important to hold the wafer straight when
using the color chart to measure film thickness
• Tilt wafer makes the film thickness thicker than
it actually is
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 112
 Spectroreflectometry
• Measure the reflected light intensity at different
wavelengths
• Calculate thin film thickness from the
relationship between reflected light intensity and
wavelength.
• Photodetector is more sensitive than human eyes
• Spectroreflectometry can obtain much higher
resolution and accuracy for the film thickness
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 113
Relation of Reflectance and Wavelength
50
45 Constructive interference
Reflectance (%)
40 Destructive interference
35
30
25
20
15
10
λ1 λ2 λ3
5
0
358 417 476 535 594 653 712 771
Wavelength (nm)

1 1 1
− =
Hong Xiao, Ph. D.
λ m λ m +1 2nt
www2.austin.cc.tx.us/HongXiao/Book.htm 114
 Spectroreflectometry System

Detectors

UV lamp

Film
Substrate
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 115
 Question
• Many advance thin film thickness
measurement tools allows user to choose
the refractive index of the film. If someone
mistakenly chooses the PE-TEOS USG film
refractive index to measure O3-TEOS USG
films thickness, what will be the effect on
the measurement result?

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 116

 Answer
• Since the nt always coupled together
• A wrong n will cause wrong t measurement
• O3-TEOS USG is a porous film and has a
R.I., about 1.44
• Slightly lower than 1.46 of PE-TEOS USG
• Measured O3-TEOS film thickness will be
slightly thinner than its actual value
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 117
 Deposition Rate

Thickness of deposited film

Deposition Rate =
Deposition time

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 118

 Wet Etch Rate

Thickness change after etch

Wet Etch Rate =
Etch time

Thickness change of the CVD film

Wet etch rate ratio =
Thickness change of the thermal oxide film

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 119

 Uniformity
• Multi-point measurement
• Definition
x1 + x2 + x3 + ⋅ ⋅ ⋅ + x N
• Average: x=
N
• Standard deviation:

( x1 − x ) 2 + ( x 2 − x ) 2 + ( x3 − x ) 2 + ⋅ ⋅ ⋅ + ( x N − x ) 2
σ=
N −1

• Standard deviation non-uniformity: σ/x

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 120
 Stress
• Mismatch between different materials
• Two kinds of stresses, intrinsic and extrinsic
• Intrinsic stress develops during the film
nucleation and growth process.
• The extrinsic stress results from differences
in the coefficients of thermal expansion
• Tensile stress: cracking film if too high
• Compressive stress: hillock if too strong
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 121
 Film Stress

Bare Wafer After Thin Film Deposition

Substrate Substrate
Substrate

Compressive Stress Tensile Stress

Negative curvature Positive curvature

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 122

 Illustration of Thermal Stress
At 400 °C
SiO2
L
Si

SiO2
Si At Room Temperature
∆L

∆L = α ∆T L
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 123
Coefficients of Thermal Expansion

α(SiO2) = 0.5×10−6 °C−1

α(Si) = 2.5×10−6 °C−1
α(Si3N4) = 2.8×10−6 °C−1
α(W) = 4.5×10−6 °C−1
α(Al) = 23.2×10−6 °C−1

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 124

 Stress Measurement
2
E h 1 1
σ= ( − )
1 − ν 6t R2 R1

Wafer curvature change before and after thin

film deposition

Laser beam scans wafer surface, reflection

light indicates the wafer curvature
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 125
 Stress Measurement
Detector
Mirror
Laser

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 126

 Dielectric CVD Processes
• Thermal Silane CVD Process
• Thermal TEOS CVD Process
• PECVD Silane Processes
• PECVD TEOS Processes
• Dielectric Etchback Processes
• O3-TEOS Processes
• Spin-on Glass
• High Density Plasma CVD
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 127
 Thermal Silane CVD Process
• Silane has been commonly used for silicon
dioxide deposition with both APCVD and
LPCVD process
heat

SiH4 + 2 O2 → SiO2 + 2 H2O

• APCVD normally uses diluted silane (3% in
nitrogen) and LPCVD uses pure silane
• Not commonly used in the advanced fab
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 128
 Thermal TEOS CVD Process
• TEOS: physisorption, high surface mobility
• TEOS film has better step coverage
• LPCVD TEOS dissociates at high temp:
700 °C
Si(OC2H5)4 → SiO2 + volatile organics
• BPSG with TMB and TMP for PMD
• Temperature is too high for IMD
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 129
 PECVD Silane Processes
• Silane and N2O (laughing gas)
• Dissociation in plasma form SiH2 and O
• Radicals react rapidly to form silicon oxide
plasma
SiH4 + N2O → SiOxHy + H2O + N2 + NH3 + …
heat
• Overflow N2O, using SiH4 flow to control
deposition rate
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 130
 Question
• Can we overflow silane and use nitrous
oxide flow rate to controlled deposition
rate?

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 131

 Answer
• Theoretically we can, but practically no one
should even try this
• It is very dangerous and not cost effective
• Overflowing silane will create a big safety
hazard: fire and explosion
• Silane is more expensive than nitrous oxide

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 132

 Passivation: Silicon Nitride
• Barrier layer for moisture and mobile ions
• The PECVD nitride
– Low deposition temperature (<450ºC)
– High deposition rate
– Silane, ammonia, and nitrogen
plasma
SiH4 + N2 + NH3 → SiNxHy + H2 + N2 + NH3 + …
heat

• Requires good step coverage, high dep. rate, good

uniformity, and stress control

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 133

Passivation Dielectric Deposition
• Stabilization 1 (stabilize pressure)
• Oxide deposition (stress buffer for nitride)
• Pump
• Stabilization 2 (stabilize pressure)
• Nitride deposition (passivation layer)
• Plasma purging (eliminate SiH4)
• Pump
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 134
 EPROM Passivation Dielectric
• Need UV transparent passivation layer
• UV light can erase EPROM memory
• Oxynitride (SiOxNy) is commonly used
• Source gases: SiH4, N2, NH3, and N2O
plasma

SiH4 + N2 + NH3 + N2O → SiOxNy + H2O + N2 + …

heat

• Properties in between oxide and nitride

– UV transparent, and a fairly good barrier layer

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 135

 PMD Barrier Layer
• PSG or BPSG need a diffusion barrier layer
– USG (need 1000 Å)
– LPCVD nitride at ~700 ºC (~ 300 Å)
– PECVD nitride at <550 ºC (< 200 Å)
• At higher temperature, PECVD nitride film has
higher deposition rate, lower hydrogen
concentration, and better film quality
• Possible in future: remote plasma CVD
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 136
 Dielectric Anti-Reflective Coating
• High resolution for photolithography
• ARC layer is required to reduce the reflection
• Metallic ARC: TiN, 30% to 40% reflection
• No longer good enough for < 0.25 µm
• Dielectric ARC layer is used
– Spin-on before photoresist coating
– CVD

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 137

Dielectric Anti-Reflective Coating
UV light (λ) ∆φ = 2nt = λ/2
1
2
Photoresist

t Dielectric ARC, n, k

Aluminum alloy
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 138
 Dielectric ARC
• PECVD silane process
• N2O as oxygen and nitrogen source
plasma
SiH4 + N2O + He → SiOxNy + H2O + N2 + NH3 +
He + · · ·
heat

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 139

 PE-TEOS
• Most widely used dielectric CVD process
• Fast
• Good uniformity
• Good step coverage

• Mainly used for IMD

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 140

 PE-TEOS
• USG process
Plasma
Si(OC2H5)4 + O2 → SiO2 + other volatiles
400 ºC

• FGS process
plasma
FSi(OC2H5)3 + Si(OC2H5)4 + O2 → SiOxFy + other volatile
(FTES) (TEOS) heat (FSG)

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 141

 FSG Process Trends

SiO2 SiOxFy (FSG) SiF4

solid solid gas

κ = 3.9 3.8 < κ < 3.2 κ~ 1

higher k less F more F lower k, F outgassing

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 142

 Dielectric Etchback Processes
• Gap fill and planarization
• Performed in thin film bay with DCVD
• Cluster tool
• In-situ dep/etch/dep process

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 143

 In-situ Dep/Etch/Dep Process
CVD chambers

A B Dep.

Etch
C D
Sputter etch Sputter etch
Robot

chamber chamber

Transfer Dep.
chamber

Cassette Metal
handler

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 144

 Sputtering Corner Chopping
+ +
Ar Ar

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 145

 Question
• Why does sputtering etch process usually
use argon as the process gas?

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 146

 Answer
• It is inert, heavy, and relative inexpensive
• The atomic weight of argon is 40, compared
with silicon’s 28 and helium’s 4
• Argon is the third most abundant element in
earth atmosphere (~ 1%) only after nitrogen
(78%) and oxygen (20%)
• Can be purified directly from condensed air

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 147

 Schematic of Sputtering Etch
Chamber
Process gases

Process Plasma Magnet coils

chamber

Chuck
By-products to
the pump RF power

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 148

 Reactive Etch Back
• CF4 and O2
• Heavy bombardment with chemical reaction
• Applications
– Planarize dielectric surface
– SOG etch back

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 149

Reactive Etch Back Planarization

2 µm PE-TEOS oxide deposition

1 µm planarization etchback
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 150
 O3-TEOS Processes
• Ozone is a very unstable molecule,
O3 → O2 + O
• At 400 °C, half-lifetime of O3: < 1ms
• Used as carrier of free oxygen radicals
• Ozone reacts with TEOS form silicon oxide
• Excellent conformality and gap fill capability
• Sub-micron IC chip applications
• APCVD and SA-CVD
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 151
 Ozone Generation

Lighting, corona discharge

plasma

O2 → O+O

O + O2 + M → O3 + M (M = O2, N2, Ar, He, etc.)

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 152

 Illustration of Ozonator
RF

O2 + N2 O2 + O3 + N2+ N2O + …

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 153

 Ozone Concentration Monitoring
Monitored by UV absorption (Beer-Lambert law):

I = I0 exp(-XCL)

Mechanical
chopper L UV sensor

Ozone cell

UV Lamp Analyzer
O3/O2 O3/O2

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 154

 O3-TEOS USG Process
• TEOS + O3 → SiO2 + volatile organics
heat

• Main applications
– STI (higher temperature, ~ 550 °C)
– IMD (~ 400 °C)

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 155

 O3-TEOS USG

Step coverage Gap fill

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 156
O3-TEOS BPSG and PSG Process
O3 → O2 + O

O + TEB + TEPO + TEOS → BPSG + volatile organics

heat

O + TEPO + TEOS → PSG + volatile organics

heat

• Main application
– PMD
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 157
 O3-TEOS BPSG
O 3 -TEOS
BPSG

Barrier
Nitride

Silicide

Poly Si

SACVD BPSG for 0.25 µm gap and 4:1 A/R.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 158
 Spin-on Glass (SOG)
• Similar to PR coating and baking process
• People in fab like familiar technologies
• IMD gap fill and planarization
• Two kinds of spin-on glass:
– Silicate
– Siloxane

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 159

Spin-on Glass: Silicate and Siloxane
H
R
O
H O Si O H
H O Si O H
R’
O
R = CH3, R’ = R or OH
H
Si(OH)4 RnSi(OH)4-n, n = 1, 2
Silicate Siloxane
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 160
 Spin-on Glass Process Steps
PECVD USG
barrier layer

Spin-on glass

SOG cure

SOG
etchback

PECVD
USG cap
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 161
 High-Density Plasma CVD
• Dep/etch/dep gap fill needs two chambers
• Narrower gaps may need more dep/etch
cycles to fill
• A tool can deposit and sputtering etch
simultaneously would be greatly helpful
• The solution: HDP-CVD

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 162

 Question
• With the feature size shrinking, metal line
width and gap between metal lines becomes
smaller. However the metal line height
doesn't shrink accordingly, which causes
larger gap aspect ratio.
• Why doesn’t shrink metal line height
accordingly to keep the same aspect ratio
and easier for dielectric gap fill?
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 163
 Answer
• Metal line resistance R = ρ l/wh.
• If h also reduces accordingly to l and w,
resistance will increase accordingly
• Therefore, line has to keep the same height

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 164

Inductively Coupled Plasma Chamber
Inductive coils Ceramic cover
Source RF

Plasma Wafer
Chamber body

E-chuck Bias RF
Helium

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 165

 ECR Chamber
Microwave

Magnet
coils Plasma

Wafer
Magnetic
field line

E-chuck Bias RF

Helium
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 166
 HDP-CVD, IMD Application

Metal Metal Metal

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 167

 HDP-CVD, Deposition

Metal Metal Metal

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 168

 HDP-CVD, Deposition

Metal Metal Metal

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 169

 HDP-CVD, Deposition

Metal Metal Metal

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 170

 PE-TEOS Deposition

Metal Metal Metal

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 171

 Oxide CMP

Metal Metal Metal

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 172

 HDP-CVD Processes
• For IMD Applications

• USG SiH4 + O2 + Ar → USG + H2O + Ar +…

• FSG SiH4 + SiF4 + O2 + Ar → FSG + volatiles

• For PMD Applications

• PSG SiH4 + PH 3 + O2 + Ar → PSG + volatiles

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 173

 Question
• Why is silane instead of TEOS used as the
silicon source gas for the HDP CVD oxide
process?

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 174

 Answer
• For HDP CVD processes, step coverage is
no longer an important factor for the gap fill
• Heavy ion bombardment always keeps gap
tapered and deposition is bottom up.
• Using silane can save the costs and hassles
related with vapor delivery system of the
liquid TEOS source.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 175

 Dielectric CVD Chamber Clean
• During dielectric CVD process, dielectric
thin film will be deposited on everything
inside chamber
• Need to routinely clean the chamber to
prevent particulate contamination problems.
• For DCVD, more time for clean than dep.
• RF plasma clean and remote plasma clean

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 176

 RF Plasma Clean
• Plasma clean process remove dielectric film
on the process kits and chamber wall
• Fluorocarbon such as CF4, C2F6 and C3F8
• In some case NF3 is also used
• In plasma, fluorocarbon will be dissociated
• Free fluorine, F, will be generated
• F removes silicon oxide and silicon nitride
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 177
 RF Clean Chemistry
plasma

CF4 → CF3 + F
plasma

F + SiO2 → SiF4 + O
heat

plasma

F + Si3N4 → SiF4 + N
heat

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 178

 RF Clean Chemistry
• In plasma clean processes, oxygen source
gases such as N2O and O2 are used with
fluorocarbon to react with carbon and free
more fluorine radicals
• Increase F/C ratio, keep it > 2
• Prevent carbon fluoride polymerization, and
increases the clean efficiency

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 179

 CF2 and Reconnection
F
F C F F C F
C F F
F F F
F C C
C C C

F F F
F F F F C

F C F

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 180

Polymerization, Teflon Deposition

F F F F F F F F F

C C C C C C C C C

F F F F F F F F F

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 181

 RF Clean Endpoint
• Excitation-relaxation cause glow
• Different gases have different colors of light
• Information of chemical components in plasma
• Monitor line emission to control clean process

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 182

 Fluorine Peak (407 nm) Intensity Endpoint Signal
9
8
7
6
5 Endpoint
4
3
2
1
00 20 40 60 80 90 110
Hong Xiao, Ph. D.
Clean Time (sec)
www2.austin.cc.tx.us/HongXiao/Book.htm 183
 Remote Plasma Clean
• RF Plasma clean
– Ion bombardment
– Cause damage on chamber parts
• Remote plasma clean
– No ion bombardment
– More gentle on chamber parts
– Longer part lifetime
– Less “green house” gas emission

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 184

Illustration of Remote Plasma Clean
Microwave
Remote plasma
chamber
NF3 Plasma

Process F F
N2 F
chamber F N2 F

Heated plate
N2, SiF4,O2… To pump
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 185
 Remote Plasma Clean
• Microwave (MW) power, NF3 as fluorine source
• 99% of NF3 dissociated in MW plasma
• Free fluorine reacts with the film in chamber
– No plasma inside process chamber
– No ion bombardment
– Prolongs their lifetime
• Disadvantages:
– Less maturity, higher cost, and using NF3
– Can not use optical endpoint system, may need FTIR
system to achieve the automatic process endpoint.
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 186
Process Trends and Troubleshooting
• Process response to input parameters
change
• Help to determine the root cause if some
wrong

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 187

 Silane PECVD Process Trends
• Increasing temperature increases deposition
rate
– Higher diffusion rate of precursors in boundary
layer
• Increasing temperature improves deposited
step coverage and film quality
• PMD uses a higher temperature
• IMD and PD, normally not exceed 400 ºC
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 188
 t
i
Deposition Rate and Temperature
s
o
p
e

Process
D

window

Temperature
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 189
 Stress and RF Power

Process
Compressive

window

RF Power

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 190

 Silane PECVD Process Trends

Process
n o i t i s o p eD

window

c a r f eR
Silane flow
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 191
 Silane PECVD Process Trends
S

WERR
t

Process
window
r
e

Silane flow
s

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 192

s
 Relationship of Deposition Rate
and RF Power

Ion bombardment
reduce adsorption
Depositon

Free radicals
enhance reaction
RF power
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 193
 Relationship of Deposition Rate
and Temperature

Dep. Rate
insensitive to
Deposition

temperature
Dep. Rate
sensitive to
temperature

Temperature
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 194
 PE-TEOS Trends
• RF power↑: dep rate↑↓, compressive stress↑
– In process window, dep rate go down
• Temperature↑: dep rate↑↓
– In process window, dep rare go down
• TEOS flow↑: dep rate↑, compressive stress↓

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 195

PE-TEOS Trends: TEOS Flow Rate

Process
s o p e D

window

c a r f eR
TEOS Flow
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 196
PE-TEOS Trends: TEOS Flow Rate

WERR
Process
window
ev i s s e r pmoC

TEOS Flow
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 197
 PE-TEOS Trends: Temperature
Increasing Reducing
chemical adsorption rate
reaction
rate
Deposition

400 to 550 °C Temperature

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 198
 O3-TEOS Trends
• Temperature↑: dep rate↑↓
– In process window, dep rare go down
• TEOS flow↑: dep rate↑

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 199

 Question
• For both PE- and O3- TEOS processes, the
maximum deposition rate can be achieved at
about 250 ºC. Why do the IMD TEOS
processes normally operate about 400 ºC and
PMD and STI processes deposited even
higher temperature (~ 550 ºC)?

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 200

 Answer
• At higher deposition temperature, film quality
is higher and step coverage is better

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 201

 Troubleshooting
• Learned from hand-on experience
• Sudden process change, either suddenly goes
wrong, or gradually goes wrong and suddenly
comes back,
• Someone should check what has changed
between good process and the bad process, or
vice versa.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 202

 Troubleshooting
• Check metrology tool first and make sure the
right recipe is used.
• If one measure PE-TEOS film with nitride
recipe, measured thickness would be
significantly thinner
• If nothing is wrong with metrology tool, then
check whether the process recipe has been
changed.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 203

 Troubleshooting
• Process always has problems at end of shift
• Someone should work cross shifts to find out
what had been changed during shift change
• Something must be changed that put the process
back to normal at the beginning of the next shift
• It most likely is the source of problems as the
process gradually goes wrong at end of the shift

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 204

 Troubleshooting
• Most dielectric CVD processes operate in
mass-transport-limited regime
• Deposition rate is mainly determined by gas
flow rate, usually silane and TEOS flow rate
• Very likely that deposition rate problems are
related with silane or TEOS flow rate
• Mass flow controller and liquid flow
controller
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 205
 Troubleshooting: Non-uniformity
• Uniformity is determined by flow pattern
• If non-uniformity pattern is center symmetric
– Adjusted spacing of the wafer and showerhead
– Or changing the carrier gas flow rate
• Helium flow for TEOS processes
• Nitrogen flow for nitride process

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 206

 Spacing and Film Profile
Showerhead
Smaller spacing
Higher dep. rate
Center thin profile
Normal spacing
Normal dep. rate
Normal profile

Larger spacing
Lower dep. rate
Wafer Center thick profile
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 207
 Troubleshooting: Non-uniformity
• If the non-uniformity is side-to-side
• Check wafer leveling or centering
• Leak check of slip valve of the chamber

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 208

Leveling and Side-to-side Profile

Showerhead Thickness profile

Wafer
0 Radius

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 209

 Future Trends
• HDP-CVD USG for STI
• Nitride or O3-TEOS oxide for sidewall spacer
• PECVD or RPCVD for PMD barrier nitride
• HDP-CVD PSG for PMD
• CMP for planarization
• Low-κ dielectric for IMD
• Silicon oxide/nitride as passivation dielectric
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 210
 Future Trends
• High-κ gate dielectric
• Possible candidates: TiO2, Ta2O5, and HfO2
• CVD and RTA

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 211

 Future Trends: Low-κ Dielectrics
• Need to reduce RC time delay
– low-κ reduces C and copper reduces R
• Require high thermal stability, high thermal
conductivity, and process integration capability
– CVD
• CSG (CxSiyO, κ ~ 2.5 - 3.0) and α-CF (CxFy, κ ~ 2.5 – 2.7)
– Spin-on dielectrics (SOD)
• Hydrogen silsequioxane (HSQ, κ ~ 3.0),
• Porous SOD such as xerogels (κ ~ 2.0 - 2.5)

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 212

 Future Trends: Low-κ Dielectrics
• Damascene process
• Copper metallization

• No gap fill, no planarization problem

• Main challenge: Integrate low-κ with copper
metallization

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 213

 Interconnection Processes

Dielectric deposition/planarization Dielectric deposition/planarization

Via etch Via etch

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 214
 Interconnection Processes

Via fill and polish Trench etch

Metal deposition Metal deposition

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 215
 Interconnection Processes

Metal etch Metal polish

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 216

 Summary
• Applications of dielectric thin film are STI,
sidewall spacer, PMD, IMD and PD, in which
IMD application is the dominant one

• Silicon oxide and silicon nitride are the two

most commonly used dielectric materials

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 217

 Summary
• Basic CVD process sequence: introducing
precursor, precursor diffusion and
adsorption, chemical reaction, gaseous
byproducts desorption and diffusion
• Surface-reaction-limited regime
• Mass-transport-limited (MTL) regime
– Most dielectric CVD reactors operate in MTL
regime

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 218

 Summary
• PMD uses PSG or BPSG, temperature are
limited by thermal budget

• IMD mainly uses USG or FSG, temperature

is limited by aluminum melting point

• PD usually uses both oxide and nitride

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 219

 Summary
• Silane and TEOS are the two silicon sources
for dielectric CVD processes
• O2, N2O, and O3 are main oxygen precursors
• NH3 and N2 are the main nitrogen sources
• Fluorine chemistry is commonly used for
dielectric CVD chamber dry clean
– CF4, C2F6, C3F8 and NF3 are the most commonly
used fluorine source gases

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 220

 Summary
• Argon sputtering process is used for
dep/etch/dep gap fill application
• CF4/O2 etchback is used for planarization
• Compressive stress (~100 MPa) is favored
for the dielectric thin film

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 221

 Summary
• HDP CVD
– SiH4 and O2 to deposit oxide
– Ar for sputtering
– High aspect ratio gap fill
– ICP and ECR: most commonly used HDP sources
• Low-κ and copper for future interconnection
• High-κ dielectric for gate or DRAM capacitor

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 222

 Chapter 11
Metallization
Hong Xiao, Ph. D.
[email protected]
www2.austin.cc.tx.us/HongXiao/Book.htm

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 1

 Objectives
• Explain device application of metallization
• List three most commonly used metals
• List three different metallization methods
• Describe the sputtering process
• Explain the purpose of high vacuum in
metal deposition processes

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 2

 Metallization
• Definition
• Applications
• PVD vs. CVD
• Methods
• Vacuum
• Metals
• Processes
• Future Trends
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 3
 Metallization
• Processes that deposit metal thin film on
wafer surface.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 4

 Applications

• Interconnection
• Gate and electrodes
• Micro-mirror
• Fuse

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 5

 CMOS: Standard Metallization

Ti/TiN TiN, ARC TiSi2

Metal 1, Al•Cu

W
BPSG

STI n+ n+ USG p+ p+
P-Well N-Well
P-epi
P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 6
 Applications: Interconnection

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 7

 Applications: Interconnection
• Dominate the metallization processes
• Al-Cu alloy is most commonly used
• W plug, technology of 80s and 90s
• Ti, welding layer
• TiN, barrier, adhesion and ARC layers
• The future is --- Cu!

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 8

 Copper Metallization
Ti/TiN SiN CoSi2 Ta or TaN

M1 Cu Cu Cu
FSG

FSG
W

PSG W

STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 9
 Wafer Process Flow
Materials IC Fab

Dielectric Test
Metalization CMP
deposition
Wafers

Thermal Etch Packaging

Implant
Processes PR strip PR strip
Masks

Photo- Final Test

lithography

Design

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 10

Applications: Gate and Electrode
• Al gate and electrode
• Polysilicon replace Al as gate material
• Silicide
– WSi2
– TiSi2
– CoSi2, MoSi2, TaSi2, …
• Pt, Au, …as electrode for DRAM capacitors
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 11
 Q&A
• Can we reduce all dimensions of metal
interconnection line at the same ratio?

• R=ρ l/wh. When we shrink all dimensions

(length l, width w, and height h) accordingly
to the shrinking of the device feature size,
resistance R increases,
• Slower circuit and more power consumption
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 12
 Applications: Micro-mirror
• Digital projection display
• Aluminum-Titanium Alloy
• Small grain, high reflectivity
• “Home Theater”

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 13

 Applications: Fuse
• For programmable read-only memory (PROM)
• High current generates heat which melt thin Al
line and open the circuit
• Polysilicon also being used as fuse materials

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 14

 Conducting Thin Films

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 15

 Conducting Thin Films
• Polysilicon
• Silicides
• Aluminum alloy
• Titanium
• Titanium Nitride
• Tungsten
• Copper
• Tantalum
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 16
 Polysilicon
• Gates and local interconnections
• Replaced aluminum since mid-1970s
• High temperature stability
– Required for post implantation anneal process
– Al gate can not use form self-aligned source/drain
• Heavily doped
• LPCVD in furnace
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 17
 Silicide
• Much lower resistivity than polysilicon
• TiSi2, WSi2, and CoSi2 are commonly used

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 18

 Salicide
• TiSi2 and CoSi2
– Argon sputtering removes the native oxide
– Ti or Co deposition
– Annealing process forms silicide
– Ti or Co don’t react with SiO2, silicide is formed
at where silicon contacts with Ti or Co
– Wet strips unreacted Ti or Co
– Optional second anneal to increase conductivity
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 19
 Self-aligned Titanium Silicide
Formation

Ti Ti
TiSi2 TiSi2 TiSi2 TiSi2
Polysilicon gate Polysilicon gate Polysilicon gate

n- n- n- n- n- n-
n+ Gate oxide n+ Gate oxide n+ Gate oxide
n+ n+ n+

Titanium Silicide annealing Titanium wet

deposition striping
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 20
 Tungsten Silicide
• Thermal CVD process
– WF6 as the tungsten precursor
– SiH4 as the silicon precursor.
• Polycide stack is etched
– Fluorine chemistry etches WSix
– Chlorine chemistry etches polysilicon
• Photoresist stripping
• RTA increases grain size and conductivity
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 21
 Aluminum
• Most commonly used metal
• The fourth best conducting metal
– Silver 1.6 µΩ⋅cm
– Copper 1.7 µΩ⋅cm
– Gold silver 2.2 µΩ⋅cm
– Aluminum 2.65 µΩ⋅cm
• It was used for gate before mid-1970

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 22

 Aluminum-Silicon Alloy
• Al make direct contact with Si at source/drain
• Si dissolves in Al and Al diffuses into Si
• Junction spike
– Aluminum spikes punctuate doped junction
– Short source/drain with the substrate
• ~1% of Si in Al saturates it
• Thermal anneal at 400 °C to form Si-Al alloy
at the silicon-aluminum interface
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 23
 Junction Spike

Al Al Al
SiO2
p+ p+
n-type Silicon

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 24

 Electromigration
• Aluminum is a polycrystalline material
• Many mono-crystalline grains
• Current flows through an aluminum line
• Electrons constantly bombards the grains
• Smaller grains will start to move
• This effect is called electromigration

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 25

 Electromigration
• Electromigration tear the metal line apart
• Higher current density in the remaining line
– Aggravates the electron bombardment
– Causes further aluminum grain migration
– Eventually will break of the metal line
• Affect the IC chip reliability
• Aluminum wires: fire hazard of old houses
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 26
 Electromigration Prevention
• When a small percent of copper is alloyed
with aluminum, electromigration resistance
of aluminum significantly improved
• Copper serves as “glue” between the
aluminum grains and prevent them from
migrating due to the electron bombardment
• Al-Si-Cu alloy was used
• Al-Cu (0.5%) is very commonly
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 27
 Aluminum Alloy Deposition
• PVD
– Sputtering
– Evaporation
• Thermal
• Electron beam
• CVD
– Dimethylaluminum hydride [DMAH, Al(CH3)2H]
– Thermal process
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 28
 PVD vs. CVD
• CVD: Chemical reaction on the surface
• PVD: No chemical reaction on the surface

• CVD: Better step coverage (50% to ~100%)

and gap fill capability
• PVD: Poor step coverage (~ 15%) and gap
fill capability
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 29
 PVD vs. CVD
• PVD: higher quality, purer deposited film,
higher conductivity, easy to deposit alloys

• CVD: always has impurity in the film,

lower conductivity, hard to deposit alloys

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 30

 Some Facts About Aluminum
Name Aluminum
Symbol Al
Atomic number 13
Atomic weight 26.981538
Discoverer Hans Christian Oersted
Discovered at Denmark
Discovery date 1825
Origin of name From the Latin word "alumen" meaning "alum"
Density of solid 2.70 g/cm3
Molar volume 10.00 cm3
Velocity of sound 5100 m/sec
Hardness 2.75
Electrical resistivity 2.65 µΩ cm
Reflectivity 71%
Melting point 660 C
Boiling point 2519 C
Thermal conductivity 235 W m-1 K-1
Coefficient of linear thermal expansion 23.1 10-6 K-1
Etchants (wet) H3PO4, HNO4, CH 3COOH
Etchants (dry) Cl2, BCl3
Hong Xiao, Ph.
CVDD. Precursorwww2.austin.cc.tx.us/HongXiao/Book.htm
Al(CH3)2H 31
 Titanium
• Applications
– Silicide formation
– Titanium nitridation
– Wetting layer
– Welding layer

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 32

 Welding Layer
• Reduce contact resistance.
– Titanium scavenges oxygen atoms
– Prevent forming high resistivity WO4 and
Al2O3.
• Use with TiN as diffusion barrier layer
– Prevent tungsten from diffusing into substrate
–

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 33

 Applications of Titanium

Al-Cu
Ti

W
PSG
Ti

n+
TiSi 2

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 34

 Some Face About Titanium
Name Titanium
Symbol Ti
Atomic number 22
Atomic weight 47.867
Discoverer William Gregor
Discovered at England
Discovery date 1791
Origin of name Named after the "Titans", (the sons of the Earth
goddess in Greek mythology)
Density of solid 4.507 g/cm3
Molar volume 10.64 cm3
Velocity of sound 4140 m/sec
Hardness 6.0
Electrical resistivity 40 µΩ cm
Melting point 1668 C
Boiling point 3287 C
Thermal conductivity 22 W m-1 K-1
Coefficient of linear thermal expansion 8.6 10-6 K-1
Etchants (wet) H2O2, H2SO4
Etchants (dry) Cl2, NF3
CVD
Hong Xiao, Ph. D. Precursorwww2.austin.cc.tx.us/HongXiao/Book.htm TiCl4 35
 Titanium Nitride
• Barrier layer
– prevents tungsten diffusion
• Adhesion layer
– help tungsten to stick on silicon oxide surface
• Anti-reflection coating (ARC)
– reduce reflection and improve photolithography
resolution in metal patterning process
– prevent hillock and control electromigration
• Both PVD and CVD
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 36
 Titanium Nitride PVD
• Barrier layer, adhesion layer and ARC
• Reactive sputtering a Ti target with Ar and N2
– N2 molecules dissociate in plasma
– Nitrogen free radials (N)
– N reacts with Ti and form TiN layer on Ti surface
– Ar ions sputter TiN off and deposit them on the
wafer surface

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 37

 Titanium Nitride CVD
• Barrier layer and adhesion layer
• Better step coverage than PVD
• Metal organic process (MOCVD)
– ~350 °C
– TDMAT, Ti[N(CH3)2]4
– Via application

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 38

 Titanium Nitridation
• Titanium PVD
• Nitridation of titanium surface with
ammonia
• Rapid thermal process

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 39

 Tungsten
• Metal plug in contact and via holes
• contact holes become smaller and narrower
• PVD Al alloy: bad step coverage and void
• CVD W: excellent step coverage and gap fill
• higher resistivity: 8.0 to 12 µΩ⋅cm compare
to PVD Al alloy (2.9 to 3.3 µΩ⋅cm)
• only used for local interconnections and plugs
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 40
 Evolution of Contact Processes

Al·Si·Cu Al·Si·Cu Void

Al·Cu
SiO2 SiO2 W SiO2
Si Si Si

Widely tapered Narrow contact Narrow contact

contact hole, hole, void with hole, WCVD for
PVD metal fill PVD metal fill tungsten plug

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 41

 Tungsten CVD
• WF6 as the tungsten precursor
• React with SiH4 to form nucleation layer
• React with H2 for bulk tungsten deposition
• Needed a TiN layer to adhere on oxide

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 42

 Some Facts About Tungsten
Name Tungsten
Symbol W
Atomic number 74
Atomic weight 183.84
Discoverer Fausto and Juan Jose de Elhuyar
Discovered at Spain
Discovery date 1783
Origin of name From the Swedish words "tung sten" meaning
"heavy stone". W comes from "wolfram",
named after the tungsten mineral wolframite.
Density of solid 19.25 g/cm 3
Molar volume 9.47 cm 3
Velocity of sound 5174 m/sec
Hardness 7.5
Reflectivity 62%
Electrical resistivity 5 µΩ⋅cm
Melting point 3422 °C
Boiling point 5555 °C
Thermal conductivity 170 W m-1 K-1
Coefficient of linear thermal expansion 4.5×10-6 K-1
Etchants (wet) KH2PO4, KOH, and K3Fe(CN)6; boiling H2O
Etchants (dry) SF6, NF3, CF4, etc.
CVD Precursor WF6
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 43
 W Plug and TiN/Ti
Barrier/Adhesion Layer
Tungsten

TiN/Ti

Oxide

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 44

 Copper
• Low resistivity (1.7 µΩ⋅cm),
– lower power consumption and higher IC speed
• High electromigration resistance
– better reliability
• Poor adhesion with silicon dioxide
• Highly diffusive, heavy metal contamination
• Very hard to dry etch
– copper-halogen have very low volatility
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 45
 Copper Deposition
• PVD of seed layer
• ECP or CVD bulk layer
• Thermal anneal after bulk copper deposition
– increase the grain size
– improving conductivity

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 46

 Some Facts About Copper
Name Copper
Symbol Cu
Atomic number 29
Atomic weight 63.546
Discoverer Copper had been used by human being since
Discovered at ancient time, long before any written history.
Discovery date
Origin of name From the Latin word "cuprum" meaning the
island of "Cyprus"
Density of solid 8.92 g/cm 3
Molar volume 7.11 cm3
Velocity of sound 3570 m/sec
Hardness 3.0
Reflectivity 90%
Electrical resistivity 1.7 µΩ⋅cm
Melting point 1084.77 °C
Boiling point 5555 °C
Thermal conductivity 400 W m-1 K-1
Coefficient of linear thermal expansion 16.5×10-6 K-1
Etchants (wet) HNO4, HCl, H2SO4
Etchants (dry) Cl2, needs low pressure and high temperature
Hong Xiao, Ph.CVD
D. Precursorwww2.austin.cc.tx.us/HongXiao/Book.htm
(hfac)Cu(tmvs) 47
 Tantalum
• Barrier layer
• Prevent copper diffusion
• Sputtering deposition

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 48

 Some Facts About Tantalum
Name Tantalum
Symbol Ta
Atomic number 73
Atomic weight 180.9479
Discoverer Anders Ekeberg
Discovered at Sweden
Discovery date 1802
Origin of name From the Greek word "Tantalos" meaning
"father of Niobe" due it close relation to
niobium in the Periodic Table
Density of solid 16.654g/cm3
Molar volume 7.11 cm3
Velocity of sound 3400 m/sec
Hardness 3.0
Reflectivity 90%
Electrical resistivity 12.45µΩ⋅cm
Melting point 2996 °C
Boiling point 5425°C
Thermal conductivity 57.5 W m-1 K-1
Hong Xiao, Ph. D.
Coefficient of linear thermalwww2.austin.cc.tx.us/HongXiao/Book.htm
expansion 6.3×10-6 K-1 49
 Cobalt
• Mainly used for cobalt silicide (CoSi2).
• Normally deposited with a sputtering
process

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 50

 Cobalt Silicide

• Titanium silicide grain size: ~ 0.2 µm

• Can’t be used for 0.18 mm gate
• Cobalt silicide will be used
• Salicide process

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 51

 Cobalt Silicide: Process
• Pre-deposition argon sputtering clean
• Cobalt sputtering deposition
• First anneal, 600 °C
Co + Si → CoSi
• Strip Unreacted cobalt
• Second anneal, 700 °C
Co + Si → CoSi2

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 52

 Some Facts About Cobalt
Name Tantalum
Symbol Co
Atomic number 27
Atomic weight 180.9479
Discoverer Georg Brandt
Discovered at Sweden
Discovery date 1735
Origin of name From the German word "kobald" meaning
"goblin" or evil spirit
Density of solid 8.900 g/cm3
Molar volume 6.67 cm3
Velocity of sound 4720 m/sec
Hardness 6.5
Reflectivity 67%
Electrical resistivity 13 µΩ⋅cm
Melting point 1768 K or 1495 °C
Boiling point 3200 K or 2927 °C
Thermal conductivity 100 W m-1 K-1
Coefficient of linear thermal expansion 13.0×10-6 K-1
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 53
 Metal Thin Film Characteristics

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 54

 Metal Thin Film Measurements
• Thickness.
• Stress
• Reflectivity
• Sheet resistance

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 55

 Metal Thin Film Thickness
• TEM and SEM
• Profilometer
• 4-point probe
• XRF
• Acoustic measurement

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 56

 TEM and SEM
• Cross section
• TEM: very thin film, few hundred Å
• SEM: film over thousand Å

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 57

 Q&A
• Why is SEM photo is always in black and
white?

• Intensity of the secondary electron emission

– strong or weak signals
– photo image: bright and dim, black and white
• SEM photo can be painted after it has been
analyzed
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 58
 Profilometer
• Thicker film (> 1000 Å),
• Patterned etch process prior to measurement
• Stylus probe senses and records microscopic
surface profile

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 59

 Schematic of Stylus Profilometer

Stylus

Film
Substrate
Stage

Profile Signal Film Thickness

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 60

 Four-point Probe
• Measure sheet resistance
• Commonly used to monitor the metal film
thickness by assuming the resistivity of the
metal film is a constant all over the wafer
surface

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 61

 Acoustic Measurement
• New technique
• Directly measure opaque thin film thickness
• Non-contact process, can be used for
production wafer

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 62

 Acoustic Measurement
• Laser shots on thin film surface
• Photo-detector measures reflected intensity
• 0.1 ps laser pulse heat the spot up 5 to 10 °C
• Thermal expansion causes a sound wave
• It propagates in the film and reflects at the
interface of the different materials
• The echo causes reflectivity change when it
reaches the thin film surface.
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 63
 Acoustic Measurement
• Acoustic wave echoes back and forth in film
• The film thickness can be calculated by
d = Vs ∆t/2
• Vs is speed of sound and ∆t is time between
reflectivity peaks
• The decay rate the echo is related to the film
density.
• Multi-layer film thickness
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 64
 Acoustic Method Measurement
Pump laser Reflection detector

Echoing First echo

Change of reflectivity
acoustic wave

Second echo
TiN d = vs·∆t/2
Third echo

TEOS SiO2 ∆t ∆t
10 20 30 40 50 60 70 80 90
Time (psec)

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 65

 TiN Thickness
• d = Vs·∆t/2
• Sound velocity in TiN film Vs = 95 Å/ps
• ∆t ≈ 25.8 ps

• d = 1225 Å

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 66

 Uniformity
• The uniformity, in fact it is non-uniformity,
of the thickness, sheet resistance, and
reflectivity are routinely measured during
the process development and for the process
maintenance.
• It can be calculated by measuring at
multiple locations on a wafer

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 67

 Mapping Patterns for Uniformity
Measurement

27 26 49
2 6 29
28 48
47
11 10 25
30 12 46
24
2 31 13 3
2
9 23 45
32 14 4 1
22 448
3 1 5 7 3 1 5 9 5 7 21 43
33 15 6
34 16 20
42
4 35
17
18
19
41
36 40
4 8 37 38 39

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 68

 Uniformity
• Most commonly used non-uniformity
definition: 49-point, 3σ standard deviation
• Clearly define non-uniformity
– For the same set of data, different definitions
causes different results
• 5-point and 9-point are commonly used in
production

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 69

 Stress
• Caused by mismatching between film and
substrate
• Compressive and tensile
• High compressive stress causes hillocks
– short metal wires between different layers
• High tensile stress causes cracks or peels

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 70

Compressive Stress Causes Hillock

Force Force
Metal

Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 71

 Tensile Stress Causes Crack

Force Force
Metal

Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 72

 Favorable Stress
• Aluminum has higher thermal expansion
rate than silicon
αAl = 23.6×10−6 K−1, αSi = 2.6×10−6 K−1
• It favor tensile stress at room temperature
• Stress becomes less tensile when wafer is
heated up later
– metal annealing (~ 450 °C)
– dielectric deposition (~ 400 °C)
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 73
 Q&A
• Why does silicon oxide film favor
compressive stress at room temperature?

• Silicon oxide has lower thermal expansion

rate (αSiO2 = 0.5×10−6 Κ−1) than the silicon
• If it has tensile stress at room temperature, it
will become more tensile when the wafer is
heated up in later processes
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 74
 Reflectivity
• Reflectivity change indicates drift of process
• A function of film grain size and surface
smoothness
• Larger grain size film has lower reflectivity
• Smoother metal surface has higher reflectivity
• Easy, quick and non-destructive
• Frequently performed in semiconductor fabs
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 75
 Sheet Resistance
• 4-point probe
• Widely used to determine film thickness
• Assuming resistivity is the same on wafer
• Faster and cheaper than the profilometer,
SEM, and acoustic measurement

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 76

 Sheet Resistance
• Sheet resistance (Rs) is a defined parameter

Rs = ρ/t

• By measuring Rs, one can calculate film

resistivity (ρ) if film thickness t is known,
or film thickness if its resistivity is known
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 77
 Resistance of a Metal Line
L
A
ρ I

L
R=ρ
A
R = Resistance, ρ = Resistivity
L = Length, A = Area of line cross-section
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 78
 Sheet Resistance Concepts

L
t w I

Apply current I and measure voltage V,

Resistance: R = V/I = ρL/(wt)
For a square sheet, L = w, so R = ρ/t = Rs
Unit of Rs: ohms per square (Ω/r)
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 79
 Sheet Resistance

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 80

 Sheet Resistance
Are you sure
their resistance
is the same?
I
I

Rs=ρ/t Rs =ρ/t

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 81

 Sheet Resistance
For this two conducting lines patterned from the
same metal thin film with the same length-to-
width ratios, are their line resistance the same?

Yes.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 82

 Four-point Probe
• Commonly used tool for sheet resistance
• A current is applied between two pins and
voltage is measured between other two pins
– If current I is between P 1 and P4, Rs = 4.53 V/I,
V is voltage between P 2 and P3
– If current I is between P 1 and P3, Rs = 5.75 V/I,
V is voltage between R 2 and R4
• Both configurations are used in measurement
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 83
 Four-Point Probe Measurement

I
V

P1 P2 P3 P4

S1 S2 S3

Film
Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 84

 Metal CVD
• Widely used to deposit metal
• Good step coverage and gap fill capability
– can fill tiny contact holes to make connections
between metal layers.
• Poorer quality and higher resistivity than
PVD metal thin films.
– Used for plugs and local interconnections
– Not applied for global interconnections
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 85
 Metal CVD Chamber
RF Power
Process Gases

Process
Chamber Wafer

Heated plate
To pump

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 86

 Metal CVD
• W, WSix, Ti, and TiN
• Thermal process, heat provides free energy
needed for the chemical reaction
• RF system is used for plasma dry clean of
the process chamber

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 87

 Metal CVD Process Steps
• Wafer into the chamber
• Slip valve closes
• Set up pressure and temperature, with secondary process
gas(es)
• All process gases flow in, start deposition
• Termination of the main process gas. Secondary process
gas(es) remain on
• Termination of all process gases
• Purge chamber with nitrogen
• Slip valve opens and robot pull wafer out
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 88
 Metal CVD Chamber Clean Steps
• Chamber pumps down
• Set up pressure and temperature
• RF turns on. Start plasma and clean process
• RF turns off. Chamber is purged
• Set up pressure and temperature, with secondary process gas(es)
• Flows main process gas to deposit the seasoning layer
• Terminate the main process gas
• Terminate all process gases
• Purge chamber with nitrogen
• Chamber is ready for the next deposition
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 89
Vertical and Tapered Contact Holes

Area = A A << B Area = B

Tapered
Straight Sidewall
Sidewall

Area = A
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 90
 Tungsten CVD Basics
Tungsten source gas: tungsten hexafluoride (WF6)

Additional reactant: hydrogen (H2)

Temperature: 400 - 475 °C

Step Coverage is 100 %

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 91

 Typical W CVD Process
•Wafer transferred to chamber
•Pressure and gas flows (H2, SiH4) established
•Nucleation takes place (silane reduction of WF6)
•Pressure and gas flows changed for bulk deposit
•Bulk deposit takes place (H2 reduction of WF6)
•Chamber pumped and purged
•Wafer transferred out of chamber

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 92

 W CVD Reactions
Nucleation on silicon
2 WF6 + 3 Si → 2 W (s) + 3 SiF4
Nucleation on glue layer
2 WF6 + 3 SiH4 → 2 W (s) + 3 SiF4 + 6 H2
Bulk deposit
WF6 + 3 H2 → W (s) + 6 HF
WF6 reaction with moisture
WF6 + 3 H2O → WO3 + 6 HF
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 93
 Tungsten Seed and Bulk Layers

Bulk tungsten layer

Ti/TiN barrier &

Tungsten
adhesion layer
seed layer

Metal Oxide

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 94

 Tungsten Silicide

• CVD and RTP

• WF6 and SiH4 as CVD source gases
• Anneal after gate etch
• Less popular than TiS2 due to higher resistivity

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 95

 Tungsten Silicide
• Sate and local interconnection applications
• Silicon sources: SiH4 and SiH2Cl2 (DCS)
• Tungsten precursor is WF6
• SiH4/WF6: lower temperature, ~ 400 °C,
• DCS/WF6: higher temperature, ~ 575 °C

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 96

 Tungsten Silicide: CVD
300 to 400 °C
WF6 + 2 SiH4 → WSi2 + 6 HF + H2

• Wider process window, more matured process

500 to 600 °C
WF6 + 3.5 SiH2Cl2 → WSi2 + 1.5 SiF4 + 7 HCl

• Better step coverage

• Less fluorine integration
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 97
 Silane-Based WSix
WF6 + 2 SiH4 → WSi2(s) + 6 HF + H2
• Very similar to the nucleation step of the
tungsten CVD process.
• Different flow rate ratio of SiH4/WF6
– lower than 3:1, tungsten deposition
– larger than 10:1 tungsten silicide deposition

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 98

 DCS-Based WSix
2 WF6+7 SiH2Cl2 → 2 WSi2 +3 SiF4+14 HCl
• Requires higher deposition temperature,
• Higher deposition rate
• Better step coverage
• Lower fluorine concentration
• Less tensile stress
– less film peeling and cracking
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 99
 Titanium CVD
• High temperature (~ 600 °C)
• CVD Ti can react with Si to form TiSi2
simultaneously during the Ti deposition

TiCl4 + 2 H2 → Ti + 4 HCl
Ti + Si → TiSi2

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 100

 Titanium Nitride CVD
• Barrier/glue layer for the tungsten plug
• Better sidewall step coverage
• A thin layer of (~200 Å) usually is applied
for the contact/via holes after PVD Ti and
TiN deposition

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 101

 CVD PVD and CVD TiN Layers
PVD TiN Layer CVD TiN Layer

Ti Layer

Metal Oxide

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 102

 CVD TiN
• Inorganic chemistry: TiCl4 and NH3 at 400
to 700 °C:
6TiCl4 + 8 NH3 → 6 TiN + 24 HCl + N2

• MOCVD at 350 °C and 300 mTorr:

Ti[N(CH3)2]4 → TiN + organics

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 103

 CVD Aluminum
• R&D to replace tungsten plug
• Dimethylaluminum hydride (DMAH),
Al(CH3)2H
• At about 350 °C, DMAH dissociates and
deposits aluminum
Al(CH3)2H → Al + volatile organics
• Difficult to incorporate ~1% Cu needed for
electromigration resistance
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 104
Cluster Tool, Aluminum CVD/PVD
Pre-clean Ti/TiN PVD

Wafer TiN CVD

Loading
Transfer Transfer
Chamber Chamber
Wafer
Unloading Al CVD

Cooldown Al-Cu PVD

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 105

 Aluminum CVD/PVD
• Ti/TiN barrier/glue layer deposition
• Al CVD via fill, Al alloy PVD, TiN PVD
– No need for W and W etch back

• Not a matured technology

• Hard to compete with copper metallization

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 106

 Physical Vapor Deposition

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 107

 PVD
• Vaporizing solid materials
• Heating or sputtering
• Condensing vapor on the substrate surface
• Very important part of metallization

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 108

 PVD vs. CVD

• PVD Start with P

• CVD Start with C

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 109

 PVD vs. CVD: Sources

• PVD Solid materials

• CVD Gases or vapors

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 110

 CVD vs. PVD
Chemical Reaction Target
Precursor Deposited
Gases Film
Plasma
Wafer

Heated
Susceptor

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 111

 PVD Methods

• Evaporation
• Sputtering

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 112

 PVD Methods: Evaporation

• Filaments
• Flash hot plate
• Electron beam

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 113

 Thermal Evaporator

Wafers

Aluminum
Charge Aluminum Vapor

10-6 Torr

To Pump High Current Source

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 114
 Electron Beam Evaporator

Wafers

Aluminum Aluminum Vapor

Charge Electron
Beam
10-6 Torr

To Pump Power Supply

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 115
 PVD Methods: Sputtering

• DC Diode
• RF Diode
• Magnetron

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 116

 Sputtering

Ar+
Momentum transfer will dislodge surface
atoms off
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 117
 DC Diode Sputtering
-V

Target

Argon Plasma

Wafer Chuck

Metal film Wafer

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 118

Schematic of Magnetron Sputtering

Magnets

Target

Higher plasma Magnetic field Erosion

density line grove

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 119

 Magnetron Sputtering
• Most widely used PVD system
• More sputter from grove
• Better uniformity cross wafer

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 120

 PVD Chamber with Shield

Shield,
Liner Target

Wafer
Wafer Chuck

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 121

 Applications of Argon
• Sputtering deposition
• Sputtering etch
– pre-clean to remove native oxide before metal
deposition
– Taper opening for dielectric gap fill
• Patterned etch
– dielectric to enhance bombardment and
damaging effect
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 122
 Properties of Argon
• Inert
• Relatively heavy
• Abundance
– about 1% in atmosphere
– low cost

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 123

 Some Facts About Argon
Name Argon
Symbol Ar
Atomic number 18
Atomic weight 39.948
Discoverer Sir William Ramsay, Lord Rayleigh
Discovered at Scotland
Discovery date 1894
Origin of name From the Greek word "argos" meaning
"inactive"
Molar volume 22.56 cm3
Speed of sound 319 m /sec
Refractive index 1.000281
Electrical resistivity N/A
Melting point -189.2 °C
Boiling point -185.7 °C
Thermal conductivity 0.01772 W m-1 K-1

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 124

 Sputtering vs. Evaporator
Sputtering Evaporator

• Purer film • More impurities

• Better uniformity • Batch process
• Single wafer, • Cheaper tool
better process
control
• Larger size wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 125
 PVD Vacuum Requirement
• Residue gases on the vacuum chamber wall
– H2O, …
• Water can react with Al to form Al2O3
• Affects conductivity of interconnections
• Only way to get rid of H2O: reach ultra high
vacuum, 10-9 Torr

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 126

 PVD Vacuum Requirement
• Cluster tool
• Staged vacuum
• Loading station: 10−6 Torr
• Transfer chamber: 10−7 to 10−8 Torr
• Deposition chamber: 10−9 Torr

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 127

 PVD Vacuum: Pumps
• Wet pump (oil diffusion pump): atm to 10-3
Torr, phasing out from fabs.
• Rough pump: atm to 10-5 Torr
• Turbo pump: 10-2 to 10-7 Torr
• Cryo pump: to 10-10 Torr
• Ion pump: to 10-11 Torr

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 128

 Endura® PVD System
PVD
Target

PVD
Chamber
CVD
Chamber

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 129

 Contact/Via Process
• Degas
• Pre-clean
• Ti PVD
• TiN PVD
• TiN CVD
• N2-H2 plasma treatment
• W CVD
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 130
Aluminum Interconnection Process
• Degas
• Pre-clean
• Ti PVD
• Al-Cu PVD
• TiN PVD

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 131

 Copper Interconnection Process
• Degas
• Pre-clean
• Ta PVD
• Cu seed PVD

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 132

 Degas
• Heat wafer to drive away gases and
moisture on wafer surface
• Outgassing can cause contamination and
high resistivity of deposited metal film

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 133

 Pre-clean
• Remove the native oxide
• Reduce the contact resistance
• Sputtering with argon ions
• RF plasma

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 134

 Pre-clean Process
Argon Plasma

Native Oxide
Ar+

Metal

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 135

 Titanium PVD
• Reduce contact resistance
• Larger grain size with low resistivity
• Wafer normally is heated to about 350 °C
during the deposition process to
• Improve the surface mobility
• Improve step coverage

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 136

 Collimated Sputtering
• Used for Ti and TiN deposition
• Collimator allows metal atoms or molecules to
move mainly in vertical direction
• Reach the bottom of narrow contact/via holes
• Improves bottom step coverage

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 137

 Collimated Sputtering
Magnets

Target

Plasma

Collimator

Film

Via holes

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 138

 Metal Plasma System
• Ti, TiN, Ta, and TaN deposition
• Ionize metal atoms through inductive
coupling of RF power in the RF coil
• Positive metal ions impact with the
negatively charged wafer surface vertically
• Improving bottom step coverage
• Reduce contact resistance
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 139
 Ionized Metal Plasma
−V

Target

Inductive Plasma
Coils

RF
Via Hole

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 140

 Titanium Nitride PVD
• Reactive sputtering process
• Ar and N2
• N2 molecules dissociate in plasma
• Free nitrogen radicals react with Ti to form
a thin layer of TiN on target surface.
• Argon ions sputter the TiN from the target
surface and deposit it on the wafer surface
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 141
 Three Applications of TiN
TiN ARC, PVD
Al-Cu
TiN, PVD

W TiN glue layer,

PVD & CVD
PSG

TiSi2
n+

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 142

 Al-Cu PVD
• Ultra high vacuum to remove moisture and
achieve low film resistivity.
• Cluster tool with staged vacuum
• dry pumps, turbo pumps and cryopump
• A cryopump can help a PVD chamber to
reach up to 10-10 Torr base pressure by
freezing the residue gases in a frozen trap

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 143

 Al-Cu PVD
• Standard process and hot aluminum process
• Standard process: Al-Cu over tungsten plug
after Ti and TiN deposition
• Normally deposit at ~ 200 °C
• Smaller grain size, easier to etch
• Metal annealing to form larger grain size
– lower resistivity
– high EMR
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 144
 Al-Cu PVD
• Hot aluminum process
• fill contact and via holes, reduces contact
resistance
• Several process steps:
– Ti deposition
– Al-Cu seed layer is deposited at low <200°C
– Bulk Al-Cu layer is deposited at higher
temperatures (450°C to 500°C)
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 145
 Copper Metallization

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 146

 Copper
• Better conductor than aluminum
• Higher speed and less power consumption
• Higher electromigration resistance
• Diffusing freely in silicon and silicon
dioxide, causing heavy metal
contamination, need diffusion barrier layer
• Hard to dry etch, no simple gaseous
chemical compounds
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 147
 Copper
• Damascene process with CMP
• Ta and/or TaN as barrier layer
• Start using in IC fabrication

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 148

 Copper
• Pre-deposition clean
• PVD barrier layer (Ta or TaN, or both)
• PVD copper seed layer
• Electrochemical plating bulk copper layer

• Thermal anneal to improve conductivity

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 149

 Etch trenches and via holes

FSG
SiN FSG
FSG Cu Cu

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 150

 Tantalum Barrier Layer and
Copper Seed Layer Deposition

Cu
Ta FSG
SiN FSG
FSG Cu Cu

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 151

 Electrochemical Plating Copper

Cu

Ta
FSG
SiN FSG
FSG Cu Cu

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 152

CMP Copper and Tantalum, CVD
Nitride

SiN
Ta
FSG Cu
SiN

FSG Cu Cu

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 153

 Pre-clean
• Argon sputtering pre-deposition clean
– Commonly used
– Possible copper contamination due to sputtering
• Chemical pre-clean
– H2 and He plasma
– H radicals react with CuO2
4 H + CuO2 → Cu + 2 H 2O

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 154

 Barrier Layer
• Copper diffusion into silicon can cause
device damaging
• Need barrier layer
• Ti, TiN, Ta, TaN, W, WN,
• Few hundred Å Ta is commonly used
• Combination of Ta and TaN in near future

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 155

 Copper Seed Layer
• PVD copper layer (500 to 2000 Å)
• Nucleation sites for bulk copper grain and
film formation.
• Without seed layer
– No deposition
– or deposition with very poor quality and
uniformity

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 156

 Copper Seed Layer
• Copper vapor can be easily ionized
• Low pressure, long MFP
• Copper ions throw into via and trench
– good step coverage and smooth film surface
• Very narrow via hole, PVD copper will be
in trouble due to its poor step coverage
• CVD copper process may be needed
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 157
 Electrochemical Plating (ECP)
• Old technology
• Still used in hardware, glass, auto, and
electronics industries.
• Recently introduced in IC industry
• Bulk copper deposition
• Low-temperature process
• Compatible with low-κ polymeric dielectric
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 158
 Electrochemical Plating (ECP)
• CuSO4 solution
• Copper anode
• Wafer with copper seed layer as cathode
• Fixed electric current
• Cu2+ ion diffuse and deposit on wafer

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 159

 Copper Electrochemical Plating
Wafer Conducting ring, cathode

Wafer holder, plastic

Solution Cu2+ Cu2+

with CuSO4 Cu2+ Copper film
Cu2+
Current
Anode, Cu

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 160

 Via and Trench Fill
• To achieve better gap-fill, pulse current
with large forward amperage and small
reversed amperage is used.
• Reversed current removes copper, which
reduces overhang of the gap.
• Similar to dep/etch/dep process
• Additives reduces deposition on the corner
to improve the via fill capability
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 161
 Electrochemical Plating Via Fill
Copper
Solution with CuSO 4
Cu2+ Cu2+
Cu2+

Cu2+
Tantalum
Cu2+

USG Cu2+ USG

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 162

 Copper CVD
• bis-hexafluoroacetyl-acetonate copper, or
Cu(hfac)2

Cu(hfac)2 + H2 → Cu + 2 H(hfac)

• 350 to 450 °C
• Too high for polymeric low-κ dielectric

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 163

 CuII(hfac)2

F3 C CF3
C O O C
HC Cu CH
C O O C
F3 C CF3

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 164

 Copper CVD
• Organiometallic compound
• Cu(hfac)(tmvs): C10H13CuF6O2Si

2 Cu(hfac)(tmvs) → Cu + Cu(hfac)2 + 2 tmvs

• Thermal process ~ 175 °C, 1 to 3 Torr

• Excellent step coverage and gap fill
capability
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 165
 Copper CVD
• Cu(hfac)(vtms) process is the the more
promising copper CVD process.
• Tough competition from the production-
proven copper ECP process
• PVD/CVD copper seed layer deposition

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 166

 Summary
• Mainly application: interconnection
• CVD (W, TiN, Ti) and PVD (Al-Cu, Ti, TiN)
• Al-Cu alloy is still dominant
• Need UHV for Al-Cu PVD
• W used as plug
• Ti used as welding layer
• TiN: barrier, adhesion and ARC layers
• The future: Cu and Ta/TaN
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 167
 Chapter 12
Chemical Mechanical
Polishing
Hong Xiao, Ph. D.
[email protected]
www2.austin.cc.tx.us/HongXiao/Book.htm

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 1

 Objectives
• List applications of CMP
• Describe basic structure of a CMP system
• Describe slurries for oxide and metal CMP
• Describe oxide CMP process.
• Describe metal polishing process.
• Explain the post-CMP clean

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 2

 Overview
• Multi layer metal interconnection
• Planarization of dielectric layers
• Depth of focus require flat surface to
achieve high resolution
• The rough dielectric surface can also cause
problems in metallization

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 3

 Wafer Process Flow
Materials IC Fab

Dielectric Test
Metalization CMP
deposition
Wafers

Thermal Etch Packaging

Implant
Processes PR strip PR strip
Masks

Photo- Final Test

lithography

Design

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 4

 Tungsten CMP
• Tungsten has been used to form metal plugs
• CVD tungsten fills contact/via holes and
covers the whole wafer.
• Need to remove the bulk tungsten film from
the surface
• Fluorine based plasma etchback processes
• Tungsten CMP replaced etchback
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 5
CMOS IC Passivation 2 Silicon Nitride

Passivation 1
Al•Cu Alloy Al•Cu USG
CMP USG Metal 4 Ti/TiN
IMD33
IMD USG
TiN ARC
Metal 3 Al•Cu Alloy
CMP USG, W Ti
IMD 2 USG W
Ti/TiN

M2 Al•Cu
CMP USG, W
IMD 1 W USG W TiSi2

M1 Al•Cu Alloy Sidewall

CMP PSG, W
PMD BPSG Spacer, USG
W
CMP USG PMD Barrier
STI n+ n+ USG p+ p+
Nitride
P-Well N-Well
P-Epi
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 6
P-Wafer
 Definition of Planarization
• Planarization is a process that removes the
surface topologies, smoothes and flattens
the surface
• The degree of planarization indicates the
flatness and the smoothness of the surface

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 7

 Definition of Planarization

Completely Conformal Film, No Planarization

Conformal and Smooth, No Planarization

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 8

 Definition of Planarization

Partial Planarization

Global Planarization

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 9

 Degrees of Planarity

Planarity R(µm) θ
Surface Smoothing 0.1 to 2.0 > 30
Local Planarization 2.0 to 100 30 to 0.5
Global Planarization > 100 < 0.5

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 10

 Definition of Planarity

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 11

 Planarization
• Smoothing and local planarization can be
achieved by thermal flow or etchback
• Global planarization is required for the
feature size smaller than 0.35 µm, which
can only be achieved by CMP

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 12

 Other Planarization Methods
• Thermal flow
• Sputtering etchback
• Photoresist etchback,
• Spin-on glass (SOG) etchback

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 13

 Thermal Flow
• Dielectric planarization
• Pre-metal dielectric
• High temperature, ~1000 °C
• PSG or BPSG, become soft and start to flow
due to the surface tension
• Smooth and local planarization

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 14

 As Deposited

BPSG
SiO2
n+ n+ p+ p+
p+ p+
N-well
P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 15

 After Thermal Flow

BPSG
SiO2
n+ n+ p+ p+
p+ p+
N-well
P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 16

 Etch Back
• Reflow temperature is too high for IMD
– can melt aluminum
• Other planarization method is needed for
IMD
• Sputtering etch back and reactive etch back

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 17

 Etch Back
• Argon sputtering etchback chip off dielectric
at corner of the gap and taper the openings
• Subsequent CVD process easily fills the gap
with a reasonable planarized surface
• Reactive ion etchback process with CF4/O2
chemistry further planarizes the surface

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 18

 CVD USG

USG
Al·Cu·Si
BPSG
SiO2
n+ n+ p+ p+
p+ p+
N-well
P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 19

 Sputtering Etch Back of USG

USG
Al·Cu·Si
BPSG
SiO2
n+ n+ p+ p+
p+ p+
N-well
P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 20

 CVD USG

USG
Al·Cu·Si
BPSG
SiO2
n+ n+ p+ p+
p+ p+
N-well
P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 21

 Reactive Etch Back of USG

USG
Al·Cu·Si
BPSG
SiO2
n+ n+ p+ p+
p+ p+
N-well
P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 22

 Photoresist Etchback
• PR spin-coats can baking
• Planarized solid thin film on wafer surface
• Plasma etch process with CF4/O2 chemistry
• Oxide etched by F and PR by O
• Adjusting CF4/O2 flow ratio allows 1:1 of
oxide to PR selectivity.
• Oxide could be planarized after etchback
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 23
 After Oxide Deposited

Oxide

Metal Metal

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 24

 Photoresist Coating and Baking

Photoresist

Oxide

Metal Metal

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 25

 Photoresist Etchback

Oxide

Metal Metal

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 26

 Photoresist Etchback

Oxide

Metal Metal

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 27

 Photoresist Etchback

Oxide

Metal Metal

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 28

 Photoresist Etchback
• When F etch oxide, O will be released
• Higher PR etch rate due to extra oxygen
• PR etchback can’t planarize very well
• After the PR etchback, dielectric film
surface is flatter than it is just deposited.
• In some cases, more than one PR etchback
is needed to achieve required flatness
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 29
 SOG Etchback
• SOG replaces PR
• Advantage: some SOG can stay on the wafer
surface to fill the narrow gaps
• PECVD USG liner and cap layer
• USG/SOG/USG gap fill and surface
planarization
• Sometimes, two SOG coat, cure and etchback
processes are used
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 30
 SOG Etchback

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 31

 Necessity of CMP
• Photolithography resolution R = K1λ/NA
• To improve resolution, NA ↑ or λ ↓
• DOF = K2λ/2(NA)2, both approaches to
improve resolution reduce DOF
• DOF is about 2,083 Å for 0.25 µm and
1,500 Å for 0.18 µm resolution.
• Here we assumed K1=K2, λ=248 nm
(DUV), and NA=0.6
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 32
 Necessity of CMP
• 0.25 µm pattern require roughness < 2000 Å
• Only CMP can achieve this planarization
• When feature size > 0.35 µm, other methods
can be used

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 33

 Advantages of CMP
• Planarized surface allows higher resolution of
photolithography process
• The planarized surface eliminates sidewall
thinning because of poor PVD step coverage

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 34

 Metal Line Thinning Due to the
Dielectric Step

Sidewall Thinning Metal 2

IMD 1

Metal 1
PMD
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 35
 Planarized Dielectric Surface, no
Metal Line Thinning Effect

Metal 2
IMD 1
Metal 1
PMD
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 36
 Advantages of CMP
• Eliminate the requirement of excessive
exposure and development to clear the thicker
photoresist regions due to the dielectric steps
– This improves the resolution of via hole and
metal line pattering processes
• Uniform thin film deposition
– Reduce required over etch time
– Reduce chance of undercut or substrate loss
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 37
 Over Exposure and Over
Development
Possible CD loss due to more
exposure and development
Needs more exposure
PR and development PR

PR Metal 2

Metal 2

IMD 1

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 38

 Rough Surface, Long Over Etch

PR Need a long over PR

etch to remove
Metal 2

Metal 2

IMD 1

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 39

 Flat Surface, Short Over Etch

PR Very litter over PR

etch is required
Metal 2 Metal 2

IMD 1

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 40

 Advantages of CMP
• CMP reduce defect density, improve yield
– Reducing the process problems in thin film
deposition, photolithography, and etch.
• CMP also widens IC chip design parameters
• CMP can introduce defects of its own
• Need appropriate post-CMP cleaning

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 41

 Applications of CMP
• STI formation
• Dielectric layer planarization
– PMD and IMD
• Tungsten plug formation
• Deep trench capacitor

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 42

 Applications of CMP

CMP USG

CMP USG

CMP W

CMP USG CMP W

CMP PSG, W
CMP PSG, W
CMP USG
STI

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 43

 Deep Trench Capacitor

Heavily
doped Si Pad
Oxide

Silicon
Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 44

 Deep Trench Capacitor
Nitride
Heavily
doped Si Pad
Oxide

Silicon
Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 45

 Deep Trench Capacitor
Nitride
Heavily
doped Si Pad
Oxide

Silicon
Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 46

 Deep Trench Capacitor
Nitride
Heavily
doped Si Pad
Oxide

Silicon
Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 47

 Deep Trench Capacitor
Nitride
Heavily
doped Si Pad
Oxide

Silicon
Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 48

 Deep Trench Capacitor
Nitride
Heavily
doped Si Pad
Oxide

Silicon
Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 49

 Deep Trench Capacitor

Dielectric Nitride
Layer
Pad
Oxide
Heavily
doped Si

Silicon
Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 50

 Deep Trench Capacitor

Dielectric Nitride
Layer
Pad
Oxide
Heavily
doped Si

Silicon
Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 51

 Deep Trench Capacitor
Polysilicon
Dielectric Nitride
Layer
Pad
Oxide
Heavily
doped Si

Silicon
Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 52

 Deep Trench Capacitor
Polysilicon
Dielectric Nitride
Layer
Pad
Oxide
Heavily
doped Si

Silicon
Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 53

 Deep Trench Capacitor
Polysilicon
Dielectric Nitride
Layer
Pad
Oxide
Heavily
doped Si

Silicon
Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 54

 Deep Trench Capacitor
Polysilicon
Dielectric
Layer
Pad
Oxide
Heavily
doped Si

Silicon
Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 55

 Deep Trench Capacitor
Polysilicon
Dielectric
Layer

Heavily
doped Si

Silicon
Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 56

 Applications of CMP
• Copper interconnection.
• Copper is very difficult to dry etch,
• Dual damascene: process of choice
• Tungsten plug is a damascene process

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 57

 Applications of CMP
• It uses two dielectric etch processes,
– one via etch and one trench etch
• Metal layers are deposition into via holes
and trenches.
• A metal CMP process removes copper and
tantalum barrier layer
• Leave copper lines and plugs imbedded
inside the dielectric layer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 58
 PECVD Nitride

Nitride

PSG W

STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 59
 PECVD USG

Nitride

USG

PSG W

STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 60
 PECVD Etch Stop Nitride

Nitride

USG

PSG W

STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 61
 PECVD USG

USG
USG

PSG W

STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 62
 Photoresist Coating
Photoresist
USG
USG

PSG W

STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 63
 Via 1 Mask

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 64

Via 1 Mask Exposure and Development
Photoresist
USG
USG

PSG W

STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 65
 Etch USG, Stop on Nitride
Photoresist
USG
USG

PSG W

STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 66
 Strip Photoresist

USG
USG

PSG W

STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 67
 Photoresist Coating
Photoresist
USG
USG

PSG W

STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 68
 Metal 1 Mask

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 69

 Metal 1 Mask Exposure and
Development
Photoresist
USG
USG

PSG W

STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 70
 Etch USG and Nitride
Photoresist
USG
USG

PSG W

STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 71
 Strip Photoresist

USG
USG

PSG W

STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 72
 Deposit Tantalum Barrier Layer

USG
USG

PSG W

STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 73
 Deposit Copper
Copper
USG
USG

PSG W

STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 74
 CMP Copper and Tantalum

M1 USG Cu
USG

PSG W

STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 75
 PECVD Seal Nitride

M1 USG Cu
USG

PSG W

STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 76
 CMP Hardware
• Polishing pad
• Wafer carrier
• Slurry dispenser

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 77

 Chemical Mechanical Polishing
Slurry Dispenser
Pressure
Membrane
Wafer Holder
Wafer
Retaining Ring Slurry

Polishing Pad

Platen

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 78

 Linear Polishing System
Pressure Slurry Dispenser
Membrane
Wafer Carrier Pad
Wafer
Retaining Ring Slurry Conditioner

Support Fluid Bearing

Belt and Polishing Pad

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 79

 Orbital Polishing
ωc Down Force
Carrier
Film

Wafer
Polish
Pad

Orbital Motion, ωp
Slurry

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 80

 Polishing Pad
• Porous, flexible polymer material
– cast, sliced polyurethane or urethane coated
polyester felt
• Pad directly affects quality of CMP process
• Pad materials: durable, reproducible,
compressible at process temperature
• Process requirement: high topography
selectivity to achieve surface planarization
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 81
 Polishing Pad Hardness
• Harder polishing pad: higher removal rate
and better within die (WID) uniformity
• Softer pad: better within wafer (WIW)
uniformity.
• Hard pads easier to cause scratches.
• The hardness is controlled by pad chemical
compositions or by cellular structure.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 82

 Polishing Pad
• Cells absorb polishing slurry
• Filler improve mechanical properties
• Polishing pad surface roughness determines
the conformality range.
– Smoother pad has poorer topographical
selectivity less planarization effect.
– Rougher pad has longer conformality range and
better planarization polishing result
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 83
 Hard Rough Pad

Wafer

Film

Polishing Pad Pad Movement

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 84

 Soft Smooth Pad

Wafer

Film

Polishing Pad
Pad Movement

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 85

 Pad Conditioning
• Pad becomes smoother due to the polishing
• Need to recreate rough pad surface
• In-situ pad conditioner for each pad
• The conditioner resurfaces the pad
• Removes the used slurry
• Supplies the surface with fresh slurry

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 86

Polishing Pad and Pad Conditioner

Slurry
Wafer Dispenser
Carrier

Polishing
Pad Pad
Conditioner

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 87

 Polishing Head
• Polishing head is also called wafer carrier
• It consists of a polishing head body
• Retaining ring
• Carrier membrane
• Down force driving system

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 88

 Polishing Head
Retaining Ring

Carrier
Membrane

Polishing Head Body

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 89
 Schematic of Polishing Head
Vacuum Chuck
Downforce
Pressure

Carrier Restraining Ring

Chamber Positioning

Restraining
Ring Membrane Restraining
Ring
Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 90
 Pad Conditioner
• Sweeps across the pad to increase surface
roughness required by planarization and
removes the used slurry
• Conditioner is a stainless steel plate coated
with nickel-plated diamond grits
• Diabond CMP conditioner: stainless steel
plate coated with CVD diamond film plated
diamond grids
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 91
 Surface of CMP Conditioners

Diamond Grits Diamond Grits (~ 20 µm)

Nickel Film Diamond Film

Silicon Substrate
Stainless Steel Plate Stainless Steel Plate

Conventional Diabond

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 92

 CMP Slurries
• Chemicals in the slurry react with surface
materials, form chemical compounds that
can be removed by abrasive particles
• Particulate in slurry mechanically abrade
the wafer surface and remove materials
• Additives in CMP slurries help to achieve
desired polishing results

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 93

 CMP Slurries
• CMP slurries work just like toothpaste
• Chemicals kill gems, remove tartar, and
form protection layer on the teeth
• Particles abrade away unwanted coating
from tooth surface during tooth brushing

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 94

 CMP Slurries
• Water-based chemicals with abrasive particles and
chemical additives
• Different polishing processes require different
slurries
• Slurry can impact removal rate, selectivity,
planarity and uniformity
• Slurries always are engineered and formulated for
a specific application.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 95

 CMP Slurries
• Oxide slurry: alkaline solution with silica
• Metal slurry: acidic solution with alumina
• Additives control the pH value of slurries
– oxide, pH at 10 to 12
– metal, pH at 6 to 2

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 96

 pH Values

Neutral

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14

More Acidic pH More Basic

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 97

 Slurry Delivery
• Slurry components are stored separately
– DI water with particulate
– additives for pH control
– oxidants for metal oxidation
• Flow to a mixer to mix at required ratio

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 98

 Slurry Flow

DI + Suspensions LFC

CMP
pH Adjuster LFC Mixer
Tool

Oxidant LFC

LFC: liquid flow controller

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 99

 Oxide Slurry
• Based on experience of optical industry,
which polish silicate glass to make lenses
and mirrors for a long time
• Oxide slurry is a colloidal suspension of
fine fumed silica (SiO2) particles in water
• KOH is used to adjust the pH at 10 to 12
• NH4OH can also be used

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 100

 Oxide Slurry
• Abrasives: fumed silica particles
• Normally contain ~ 10% solids
• Shelf lifetime of up to 1 year with proper
temperature control

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 101

 Fumed Silica
• Fumed silica particles are formed in a vapor
phase hydrolysis of SiCl4 in a hydrogen-
oxygen flame
2 H2 + O2 → 2 H2O
SiCl4 + 2 H2O → SiO2 + 4HCl ↑
• Overall reaction
SiCl4 + 2 H2 + O2 → SiO2 + 4HCl ↑
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 102
 Fumed Silica Particle Formation
Collection
Cooling System

<1710 °C Agglomerates

Aggregates
>1800 °C

O2 SiCl4
H2
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 103
 Fumed Silica Particles

Courtesy of Fujimi Corporation

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 104
 Metal Polishing Slurry
• Metal CMP process is similar to the metal
wet etch process
– Oxidant reacts with metal to form oxide
– Metal oxide is removed
– Repeat metal oxidation and oxide removal

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 105

 Metal Polishing Slurry
• The metal CMP slurries usually are pH-
adjusted suspensions of alumina (Al2O3)
• The slurry pH controls the two competing
metal removal mechanisms
– metal corrosive wet etching
– metal oxidation passivation

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 106

 Metal Polishing Slurry
• Different metal oxides have different solubility
• If oxide is soluble, wet etch will dominate
– Not favored: isotropic with no topographic selectivity
• If oxide is insoluble, it blocks further oxidation
– Particles mechanically abrade oxide layer
– Repeating metal oxidation and oxide abrasion
– favorable: high surface topographic selectivity
• The pH value controls oxidation process
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 107
 Tungsten Slurry
• Pourbaix diagram
• When pH < 2, tungsten is in passivation regime
• Tungsten can form passivation oxide WO3 with
pH lower than 4 in the presence of an oxidant
– Oxidants: potassium ferricyanid (K 3Fe(CN)6), ferric
nitrade (Fe(NO3)3), and H2O2
• For a higher pH, the soluble W12O4110−, WO42−,
and W12O396− ions can be formed, cause wet etch
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 108
 Pourbaix Diagram for Tungsten
2 W12O396- Stable
Potential (Eh) Volts

1
W12O4110-
WO3
WO42-
0
WO2 Corrosive

-1
W

-2
0 2 4 6 8 10 12 14
pH
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 109
 Tungsten Slurry
• Adjusting slurry pH allows low wet etch rates
and chemical-mechanical polish removal
• Tungsten slurries normally are quite acidic with
pH level from 4 to 2.
• Tungsten slurries have lower solid contents and
much shorter shelf lifetime.
• Tungsten slurries require mechanical agitation
prior to and during delivery to the CMP tools
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 110
 Aluminum Slurry
• Water-based acidic solutions
• H2O2 as oxidant,
• Alumina as abrasives.
• Limited shelf lifetime
• H2O2 molecule is unstable
• Aluminum CMP is not popularly used
– Hard to compete with copper metallization
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 111
 Copper Slurry
• Acidic solutions
• Oxidants: hydrogen peroxide (H2O2),
ethanol (HOC2H5) with nitric acid (HNO4),
ammonium hydroxide (NH4OH) with
potassium ferri- and ferro-cyanide, or nitric
acid with benzotriazole
• Alumina as abrasives

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 112

 Pourbaix Diagram for Copper
2
CuO CuO22-

Corrosive
Corrosive
Potential (Eh) Volts

1 Passivation
Cu2+
Cu2O
0 Cu+ Cu

-1 Passivation
regime with Immunity
stable alumina
-2
0 2 4 6 8 10 12 14
pH
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 113
 Copper Slurry
• Need colloidally stable slurry to achieve
consistent polishing process results
• A colloidally stable alumina suspension can
be achieved at pH just below 7.
• Only a small window for copper slurries to
achieve both electrochemical passivation
and colloidally stable suspension of
aqueous alumina particles
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 114
 CMP Basics
• Removal rate
• Uniformity
• Selectivity
• Defects

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 115

 Removal Rate
• Mechanical removal rate R was found by
Preston
• The Preston equation can be expressed as
R = Kp⋅p⋅∆v
• p is the polishing pressure
• Kp is the Preston coefficient
• ∆v is relative velocity of wafer and pad
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 116
 Removal Rate
• Preston equation works very well for the
bulk film polishing processes
• The protruding portions on a rough surface
have higher polishing pressure
• Removal rate of protruding parts is higher
• This helps to remove surface topography
and planarize the surface

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 117

Protruding Parts with Higher Pressure

Wafer No Pressure, No Removal

High Pressure, Fast Removal Film

Polishing Pad

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 118

 Removal Rate
• Thickness difference before and after CMP
divided by CMP time
• Multiple measurement for uniformity
• Test wafer, blanket film
• Daily tool qualification

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 119

 Uniformity
• Usually 49-point, 3σ standard deviation as
the definition of the uniformity for the CMP
process qualifications
• Changes of the film thickness before and
after CMP process is monitored
• For the production wafers, uniformity after
CMP process is monitored
• Normally use 9 or 13 points measurement
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 120
 Uniformity
• Both WIW and WTW uniformity can be affected
by the polish pad condition, down force pressure
distribution, relative speed, restraining ring
positioning, and the shape of the wafers.
• By using harder pad and lower pressure a good
global uniformity can be achieved
• Lower pressure, lower removal rate, affect
throughput
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 121
 Selectivity
• Ratio of removal rates of different materials
• Affect CMP defects, such as erosion or dishing
• The slurry chemistry is the primary factor that
affects removal selectivity of CMP process
• STI oxide CMP require high oxide to nitride
selectivity, from 100:1 to 300:1
• Because only polish oxide, selectivity is not
important in PMD and IMD CMP processes
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 122
 Selectivity
• For tungsten CMP process, selectivity to oxide
and titanium nitride is very important.
• Usually tungsten to TEOS oxide selectivity is
very high, from 50 to 200
• Slurry chemistry, oxidant
• Selectivity is also related to the pattern density
• higher pattern density, lower removal selectivity
– lead to erosion of the tungsten and oxide film
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 123
 Erosion Caused by High Pattern
Density

W Oxide W W

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 124

 IC Layout and Erosion
• IC design layout can directly affect the
erosion problems
• By designing opening area less than 30% of
the chip surface, it can help to solve the
erosion problem

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 125

 Defects
• CMP removes defects and improves yield
• Introduce some new defects
– scratches, residual slurry, particles, erosion, and
dishing.
• Large foreign particles and hard polish pad
can cause scratches
– Tungsten fill the scratches in oxide surface
cause short circuit and reduce the IC yield.
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 126
 Defects
• Improper down force pressure, worn pad,
inadequate pad conditioning, particle
surface attraction, and slurry drying
• Slurry residue on the wafer surface and
cause contamination
• Post-CMP clean is very important to
remove slurry residue and improve process
yield
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 127
 Erosion
• Increases depth of via holes
• Incomplete via hole etch
• Open loop between the different layers in
the next dual damascene interconnection

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 128

Circuit Opening Caused by Erosion
Via Etch Stop Open Caused by Erosion

Cu Oxide Cu Cu

W Oxide W W

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 129

 Dishing Effect
• Usually happens at a larger opening area
– large metal pads
– STI oxide in the trenches.
• More materials are removed from the center
• Cross-section view looks like a dish

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 130

 Dishing Effect

USG Tungsten

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 131

 Dishing/Erosion and Selectivity
• Both dishing and erosion effects are related
to the removal selectivity
• Tungsten CMP process,
– If tungsten to oxide selectivity is too high, more
tungsten removal, cause dishing and recessing
– If the selectivity is not high enough, both oxide
and tungsten will be polished, causes erosion

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 132

 Dishing/Erosion and Selectivity
• Oxide CMP with high selectivity of oxide to
nitride can cause oxide dishing during the
oxide overpolishing step of the oxide CMP
in the STI formation

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 133

 Dishing Effect of STI USG

Pad Oxide Nitride

USG USG

Silicon Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 134

 Particles and Defects
• Particles and defects cause irregular
topography on wafer surface
• Scattering incident light
• Monitor particles and defects by detecting
the scattered light

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 135

Particle Detection By Light Scattering
Incident Light

Reflected Light
Scattered light
Photodetector

Scattered light

Particle
or Defect Scattered light

Substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 136

 Particle Measurement
• Intensity of the scattered light is very weak
• Elliptical mirror is used to collect the light
• Elliptical curve has two focuses
• Light from one focus reflects to another focus

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 137

 Particle Measurement
• Laser beam scans wafer surface vertically at
one focus of elliptical mirror and a photo-
detector is placed at another focus
• Moving wafer, and collecting scattered light
to detect tiny particles and defects
• Mapping particle/defect locations on the
wafer surface

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 138

 Laser Scan

Elliptical Mirror
Reflected Light

Scanning Laser Beam

Wafer Photodetector

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 139

 Particle Measurement

Elliptical Mirror
Reflected Light

Scanning Laser Beam

Wafer Photodetector

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 140

 Particle Measurement

Elliptical Mirror
Reflected Light

Scanning Laser Beam

Wafer Photodetector

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 141

 Particle Measurement: Particle 1

Elliptical Mirror

Scanning Laser Beam

Wafer Photodetector

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 142

 Particle Measurement

Elliptical Mirror
Reflected Light

Scanning Laser Beam

Wafer Photodetector

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 143

 Particle Measurement

Elliptical Mirror
Reflected Light

Scanning Laser Beam

Wafer Photodetector

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 144

 Particle Measurement

Elliptical Mirror
Reflected Light

Scanning Laser Beam

Wafer Photodetector

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 145

 Particle Measurement

Elliptical Mirror
Reflected Light

Scanning Laser Beam

Wafer Photodetector

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 146

 Particle Measurement

Elliptical Mirror
Reflected Light

Scanning Laser Beam

Wafer Photodetector

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 147

 Particle Measurement

Elliptical Mirror
Reflected Light

Scanning Laser Beam

Wafer Photodetector

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 148

 Particle Measurement

Elliptical Mirror
Reflected Light

Scanning Laser Beam

Wafer Photodetector

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 149

 Particle Measurement

Elliptical Mirror
Reflected Light

Scanning Laser Beam

Wafer Photodetector

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 150

 Particle Measurement

Elliptical Mirror
Reflected Light

Scanning Laser Beam

Wafer Photodetector

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 151

 Particle Measurement

Elliptical Mirror
Reflected Light

Scanning Laser Beam

Wafer Photodetector

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 152

 Particle Measurement

Elliptical Mirror
Reflected Light

Scanning Laser Beam

Wafer Photodetector

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 153

 Particle Measurement

Elliptical Mirror
Reflected Light

Scanning Laser Beam

Wafer Photodetector

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 154

 Particle Measurement, Particle 2

Elliptical Mirror

Scanning Laser Beam

Wafer Photodetector

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 155

 Particle Measurement

Elliptical Mirror
Reflected Light

Scanning Laser Beam

Wafer Photodetector

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 156

 Particle Measurement

Elliptical Mirror
Reflected Light

Scanning Laser Beam

Wafer Photodetector

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 157

 CMP Processes
• Oxide removal mechanism
• Metal removal mechanisms
• Endpoint methods

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 158

 Oxide CMP
• Early development in the mid-1980s in IBM
• Combined knowledge and experience of
glass polishing and silicon wafer polishing

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 159

 Oxide CMP
• Hydroxyls on both film and silica surfaces
• Form hydrogen bonds of silica and surface
• Form molecular bonds of silica and surface
• Mechanical removal of the particles bonded
with wafer surface
• Tear away atoms or molecule from film on
wafer surface
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 160
 Oxide CMP

Abrasive Particle
Si
O
H
H H H H H H H H H H H H H H H

O O O O O O O O O O O O O O O
Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si
O O O O O O O O O O O O O O O
Silicon Oxide Surface
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 161
 Oxide CMP, Hydrogen Bond

Abrasive Particle
Si
O
H
H H H H H H H H H H H H H H H

O O O O O O O O O O O O O O O
Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si
O O O O O O O O O O O O O O O
Silicon Oxide Surface
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 162
 Oxide CMP, Molecule Bond

Abrasive Particle O H
H
H H H H H H H H H Si H H H H H

O O O O O O O O O O O O O O O
Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si
O O O O O O O O O O O O O O O
Silicon Oxide Surface
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 163
 Oxide CMP, Removal of Oxide

O H
Abrasive Particle Si
O H
Si

H H H H H H H H H H H H H H

O O O O O O O O O O O O O O
Si Si Si Si Si Si Si Si Si Si Si Si Si Si
O O O O O O O O O O O O O O O
Silicon Oxide Surface
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 164
 Tungsten CMP
• Form plugs to connect metal lines between
different layers
• Tungsten etch back and Tungsten CMP
– Fluorine based tungsten RIE etchback
• In-situ with tungsten CVD process in a cluster tool
• Recessing of the Ti/TiN barrier/adhesion layer due
to the aggressive fluorine chemical etch of Ti/TiN
and affects the chip yield
– Tungsten CMP: winner for higher yield
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 165
Recess of Ti/TiN due to W Etchback

Ti/TiN Barrier & Recess Caused

Adhesion Layer Tungsten by Etchback
Plug

USG

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 166

 Tungsten CMP
• Two completing removal mechanisms
• Wet etch: a pure chemical process
– Unfavorable
• Passivation oxidation and oxide abrading:
chemical and mechanical process
– Favorable
• Controlled by pH value of slurry
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 167
 Tungsten CMP
• Potassium ferricyanide, K3Fe(CN)6, is used as
both etchant and oxidant
• The wet etch chemistry can be expressed
W+6Fe(CN)6-3+4H2O → WO4-2+6Fe(CN)6-4+8H+
• The competing passivation oxidation reaction
W+6Fe(CN)6-3+3H2O → WO3+6Fe(CN)6-3+6H+

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 168

 Tungsten CMP
• Normally tungsten CMP uses two step process
• The first step remove bulk W with slurry pH < 4,
• The second step remove TiN/Ti stacked
barrier/adhesion layer with slurry pH > 9

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 169

 Metal CMP Process

Polishing Pad

Passivation Oxide Slurry

Metal Oxide
Wet Etch of Abrasive
“Soft Oxide” Alumina
Particle

Metal

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 170

 Copper CMP
• Difficult to plasma etch copper
– Lack of volatile inorganic copper compounds
• Copper CMP key process in copper
metallization process
• H2O2, or HNO4 can be used as oxidant
• Alumina particulate is used for abrasion

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 171

 Copper CMP
• CuO2 is porous and can’t form a passivation
layer to stop further copper oxidation
• Additive is needed to enhance passivation
• NH3 is one of additives used in slurry
• Other additives such as NH4OH, ethanol or
benzotriazole can also be used as complexing
agents to reduce wet etch effect

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 172

 Copper CMP
• Dual-damascene copper metallization
• Both bulk Cu and barrier Ta layer need to be
removed by the CMP process.
• Cu slurry can’t effectively remove Ta, the
lengthy over polishing step for Ta removal
can cause copper recess and dishing effects

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 173

 Copper Deposition

Copper Tantalum
USG Barrier
Layer

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 174

 Copper CMP

Copper Tantalum
USG Barrier
Layer

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 175

 Over Polish to Remove Tantalun

Copper Tantalum
USG Barrier
Layer

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 176

 Copper Dishing and Recessing

Copper Tantalum
USG Barrier
Layer

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 177

 Copper CMP
• Two-slurry polishing
• The first slurry remove bulk copper layer
• The second slurry remove Ta barrier layer
• The two-slurry CMP process reduces
– Copper recessing and dishing
– Oxide erosion
• Multiple polishing platens greatly simplifies
multi-slurry CMP processing
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 178
 CMP Endpoint Detection
• Monitoring the motor current
• Optical measurement

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 179

 Motor Current CMP Endpoint
• When CMP process closing to end, polish pad
start to contact and polish underneath layer
• Friction force start to change
• Current of the polish head rotary motor will
change to keep constant pad rotation rate
• Monitoring the change of motor current can
find endpoint of the CMP process

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 180

Motor Current During Copper CMP
Oxide Exposed
Sensor Output (Arbitrary Unit)

Cu Ta Exposed

0 60 120 180 240 300 360

Time (sec)

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 181

 Optical Endpoint: Dielectric
• Endpoint by either thickness measurement
• Reflected lights interfere with each other
• Constructive and destructive interference
• Change of the film thickness causes the
periodically changes of interference state
• Dielectric film thickness change can be
monitored by the change of reflection light
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 182
 Endpoint of Dielectric CMP

Substrate
Dielectric Film

Laser
Photodetector

Light
Intensity

Time
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 183
 Optical Endpoint: Metal
• The change of reflectivity can be used for
metal CMP process endpoint
• Usually metal surface has high reflectivity
• Reflectivity significantly reduces when
metal film is removed
• Trigger endpoint

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 184

 Endpoint of Metal CMP
USG USG
Metal Film

Laser Laser

Photodetector Photodetector

Reflective
Intensity

time
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 185
 Post CMP Clean
• Post-CMP cleaning need remove both particles
and other chemical contaminants
• Otherwise, defect generation and low yield
• Mechanical scrubbing cleaners with DI water
• Larger DI water volume, higher brush pressure
high cleaning efficiency
• Three basic steps: clean, rinse, and dry
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 186
 Post CMP Clean
• Usually brush is made of porous polymers,
allows chemicals to penetrate through it and
deliver to wafer surface
• Double-sided scrubbers are used in the post-
CMP clean process

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 187

 Brush System

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 188

 Post CMP Clean
• Slurry particles can chemically bond to atoms
on wafer surface if slurry dried
• Chemical additives, such as NH4OH, HF or
surfactants is needed to remove bonded
particles by weakening or breaking the bonds
• Additives also help particles diffuse away
from the surface

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 189

 Post CMP Clean
• Chemical solution is also used to adjust the
wafer and particle surface charges so that
electrostatic repulsion keeps particles from re-
deposition on the surface
• Acidic solutions can be used to oxidize and
dissolve organic or metal particles

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 190

 Particle Removal Mechanisms

Acidic Solution:
Oxidation and
Dissolution

Alkaline Solution:
Surface Etch and
Electrostatic
Repulsion

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 191

 Post Oxide CMP Clean
• Silica particles adhere to or embedded in
oxide surface
• Usually an alkaline chemical, NH4OH, is
used for post oxide CMP clean
• The alkaline solution charges both silica
particles and oxide surface negatively
• Electrostatic force expels particles from the
surface
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 192
 Post Oxide CMP Clean
• HF is used to remove particles with strong
molecule bonds with surface,
• Breaking the bonds, dissolving silica particles
and some oxide surface
• Megasonics (MHz ultrasound wave) is
commonly used to release shock waves that
help dislodge the particles
• DI water rinse
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 193
 Post Tungsten CMP Clean
• Tungsten slurries are much harder to remove
than oxide slurries.
• DI wafer with NH4OH is commonly used
• Fe(NO3)3 as the oxidant results in high Fe3+
ion concentration in the solution.
• The Fe3+ ion interacts with OH− to form
Fe(OH)3 particulate that grow to 1 micron

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 194

 Post Tungsten CMP Clean
• The Fe(OH)3 particles can cause high surface
defect density and contaminates the brush
• Commonly called brush loading
• The defect caused by Fe(OH)3 particles can
be reduced by using 100:1 HF clean
• DI water rinse

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 195

 Wafer Drying
• Residue-free drying process
• Physically removal, without water evaporation
– Evaporation drying cause contamination by leaving
dissolved chemicals in DI water behind
• Most commonly used technique: spin-drying
– Centrifugal force drives water out the wafer
• Ultra-clean dry air or nitrogen flow remove
water from wafer center
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 196
 Wafer Drying
• Vapor drying
– Ultra-pure solvent with high vapor pressure
– Most commonly used: isopropyl alcohol (C3H8O,
IPA)
– Displace water from the wafer surface

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 197

 Dry-in Dry-out CMP
• Integrated CMP and post-CMP clean systems
• Allow so-called “dry-in dry-out” process
• CMP, post-CMP clean, and wafer drying
processes in one sequence
• Improve process through put and yield

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 198

 Process Issues
• CMP process is a relatively new process
• Very limited process details are available
• The main concerns for CMP processes
– Polishing rate, planarization capability, within die
uniformity, within wafer uniformity, wafer to wafer
uniformity, removal selectivity, defects and
contamination control

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 199

 Process Issues: Polish Rate
• Polish rate affected by
– Downforce pressure
– Pad hardness
– Pad condition
– Applied slurry
– Rotation speed

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 200

 Process Issues: Planarization
• Planarization capability is mainly determined
by the stiffness and surface condition of the
polish pad.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 201

 Process Issues: Uniformity
• Uniformity affected by
– Polish pad condition,
– Down force pressure,
– Relative speed of the wafer to the polish pad,
– Curvature of wafers, which is related to film stress
• Downforce pressure distribution is the most
important knob to control the CMP uniformity

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 202

Process Issues: Removal Selectivity
• Mainly controlled by the slurry chemistry
• Also related to the pattern density
– determined by the design layout.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 203

 Process Issues: Defects
• There are many different kinds of defects,
which relate with many different process
parameters

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 204

 Process Issues: Contamination
Control
• Contamination Control:
– Isolate CMP bay from other processing areas
– Restrict movement between CMP bay and other
area
• Dedicate copper CMP tools
– Avoid copper contamination of the silicon wafer
– Copper contamination can cause unstable
performance of MOSFETs and ruin the IC chips
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 205
 Process Issues: Contamination
Control
• IF slurry has spilled, it is very important to
immediately wash and clean it thoroughly
• Dried slurry leaves huge amount of tiny
particles, which is easy to airborne can become
a source of particle contamination.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 206

 Future Trends
• More widely used copper CMP
• Copper and low-κ dielectric interconnection
– low-κ dielectric CMP
– Copper and barrier layer CMP processes with
high selectivity to low-κ dielectric
• DRAM applications: CMP processes involve
with polysilicon and high-κ dielectric

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 207

 Summary
• Main applications of CMP are dielectric
planarization and bulk film removal
– STI, PMD and IMD planarization, tungsten plugs,
and dual damascene copper interconnections.
• Need CMP for <0.25 µm features patterning due
to depth-of-focus requirement
• Advantages of CMP: high-resolution patterning,
higher yield, lower defect density
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 208
 Summary
• A CMP system usually consists of wafer carrier,
a polishing pad on a rotating platen, a pad
conditioner, and a slurry delivery system
• Oxide slurries: alkaline solutions at 10< pH < 12
with colloidal suspension silica abrasives
• Tungsten slurries are acidic solutions at 4< pH <
7 with alumina abrasives
• Copper slurries: acidic with alumina abrasives
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 209
 Summary
• The important factors of CMP processes:
– Polish rate, planarization capability, selectivity,
uniformities, defects and contamination controls
• Polish rate affects by: downforce pressure, pad
stiffness, pad surface condition, relative speed
between pad and wafer, and slurry type.
• CMP uniformity affects by down force pressure
distribution, pad stiffness, and pad condition

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 210

 Summary
• The removal selectivity is mainly determined by
the slurry chemistry
• Oxide CMP process: silica particles form
chemical bonds with surface atoms and abrade
removal of materials from the surface
• Two metal removal mechanisms in metal CMP
process: wet etch and passivation/abrade

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 211

 Summary
• Endpoint detections
– Optical
• Thickness measurement for dielectric film
• Reflectivity measurement for metal film
– Motor current
• Post-CMP clean reduce defects and improve
yield

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 212

 Chapter 13
Process Integration
Hong Xiao, Ph. D.
[email protected]
www2.austin.cc.tx.us/HongXiao/Book.htm

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 1

 Objectives
• List three isolation methods
• Describe sidewall spacer process and application
• Explain the VT adjustment implantation
• Name three conductors used for MOSFET gate
• List three metals used for interconnection process
• List basic steps for copper metallization process
• Identify the material most commonly used as final
passivation layer for an IC chip
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 2
 Introduction
• It takes up to 30 masks and several hundreds
process steps to finish an IC chip fabrication.
• Every step is related to other steps.
• CMOS processes
– Front-end:
• well formation, isolation, and transistor making
– Back-end
• Interconnection and passivation
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 3
 Wafer Preparation
• CMOS IC chips commonly used <100> wafer
• Bipolar and BiCMOS chips usually use with
<111> wafers orientation.
• 1960 to mid-1970s, mainly PMOS, n-type wafer
• After mid-1970s, mainly NMOS, p-type wafer
• CMOS developed from NMOS process, for
historical reason more fabs use p-type wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 4
 NMOS and CMOS Processes
• The simplest NMOS IC processing had five
mask steps: activation, gate, contact, metal, and
bonding pad
• The early CMOS IC processing added three
more mask steps: n-well (for p-type substrate),
activation, gate, n-source/drain, p-source/drain,
contact, metal, and bonding pad
• Both processes used p-type wafers
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 5
 NMOS
Aluminum Silicon Alloy

Nitride

PSG PSG PSG

Field Field
Poly Si Oxide
Oxide
n+ n+
p-Silicon
Gate Oxide
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 6
 CMOS of the Early 1980s

Nitride
USG
Poly Si Al·Cu·Si
Gate BPSG Nitride
n+ n+ SiO 2 p+ p+
p+ p+ LOCOS
N-well
P-type substrate
Gate
Oxide Isolation Implantation

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 7

 Epitaxy Silicon Layer
• Bipolar transistors and BiCMOS chips require
epitaxial silicon layer to form a buried layer
– Some power devices even require wafers made by
floating zone method
• When CMOS chip speed is not very high, it
doesn’t need the epitaxy layer
• High-speed CMOS chips need epitaxy layer

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 8

 Epitaxy Silicon Layer
• Silicon wafers made by the CZ method always
have some oxygen because quartz crucible
• Oxygen can reduce carrier lifetime and slow
down the device
• The epitaxy silicon layer creates an oxygen-free
substrate and help to achieve high device speed

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 9

 Epitaxy Silicon Layer
• RCA clean to remove contaminants
• Anhydrate HCl dry clean helps to remove
mobile ions and the native oxide
• Epitaxy growth: high temperature CVD
– silicon source: SiH4 or SiH2Cl2, or SiHCl3
– H2 as process, carrier, and purge gas
– AsH3 or PH3 as n-type dopant gas,
– B2H6 as p-type dopant gas
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 10
 Wafers Used for IC fabrication
• Advanced CMOS IC chips normally use p-type
<100> single crystal silicon wafers with p-type
epitaxial layer
• Bipolar IC chips usually use <111> wafers

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 11

 Well Formation
• Single well
• Self-aligned twin well
• Double photo twin well

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 12

 Single Well
• Early CMOS IC processing
• N-well on p-type wafer
• P-well on n-type wafer
• High energy, low current ion implantation
• Thermal anneal and drive-in

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 13

 N-well Formation

Phosphorus Ions
Wafer clean Photoresist

n-well
Screen oxide grow (a) P-type Silicon

Well mask
n-well
Ion implantation (a) (b) P-type Silicon

Photoresist strip
Anneal and drive-in (b) (c)
n-well
Screen oxide strip (c) P-type Silicon

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 14

 CMOS with P-well

Poly Si Field Oxide Gate Oxide

n+ p-well n+ p+ p+

N-type Silicon

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 15

 CMOS with N-well

Poly Si
Gate

n+ n+ SiO2 p+ p+
p+ p+ LOCOS
N-well
P-type substrate
Gate
Oxide Isolation Implantation

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 16

 Self-aligned Twin Well
• More flexibility for the designers
• Self-aligned process save a mask step
• LPCVD Si3N4 is a very dense layer
• Block ion implantation on p-well
• Prevent oxidation on p-wee
• Oxide grown on n-well block p-well ion
implantation
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 17
 Self-aligned Twin Well
•Wafer clean Nitride

(a)
•Grow pad oxide Silicon

•Deposit nitride (a)

Phosphorus Ions
•N-well mask Nitride
(b)
•Etch nitride
Silicon
•Strip photoresist
Nitride
Silicon Dioxide
•N-well implantation (b)
N-well
(c) Silicon
•Anneal/drive-in and oxidation (c)

•Strip nitride Boron Ion Implantation

Silicon Dioxide
•P-well implantation (d) (d)
N-well
Silicon
•Anneal and drive

•Strip pad oxide (e) N-well P-well

(e) Silicon
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 18
 Self-aligned Twin Well
• Advantage: reduce a photo mask step
– Reduce cost
– Improve IC chip yield.
• Disadvantage: wafer surface is not flat
– n-well always has lower level than p-well
– Affect photolithography resolution
– Affect thin film deposition

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 19

 Self-aligned Twin Well
• N-well implant first
• Phosphorus diffuses slower than boron in
single silicon
• If p-well implant first, boron in p-well could
diffuse out of control during n-well anneal
and drive-in

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 20

 Twin Well
• Two mask steps
• Flat surface
• Common used in advanced CMOS IC chip

• High energy, low current implanters

• Furnaces annealing and driving-in

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 21

 Twin Well

Phosphorus Ions Boron Ions

Photoresist Photoresist
N-Well P-Well
P-Epi N-Well
P-Epi
P-Wafer P-Wafer

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 22

 Isolations
• Blanket field oxide
• Local oxidation of silicon (LOCOS)
• Shallow trench isolation (STI)

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 23

 Blanket Field Oxide
• Early years of IC industry
• Simple and strait forward
• Oxidation and etch
• Thickness is determined by VFT,
• VFT >> V to prevent cross-talking

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 24

 LOCOS Formation
Pad oxide

Silicon nitride

Wafer clean (a)

P-type substrate
Grow pad oxide

LPCVD nitride (a) Silicon nitride

p+ p+
(b)
Mask 1, LOCOS
P-type substrate

Etch nitride
Silicon nitride
SiO2
Strip photoresist (c) p+ p+

Isolation implantation, boron (b) P-type substrate

Wet oxidation, LOCOS formation (c)

SiO2
p+ p+
Strip nitride and pad oxide (d) (d)
P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 25

 Wafer Clean

P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 26

 Pad Oxidation

Pad oxide

P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 27

 LPCVD Nitride

Pad oxide

Silicon nitride

P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 28

 Photoresist Coating

Pad oxide

Photoresist
Silicon nitride

P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 29

 LOCOS Mask

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 30

 LOCOS Mask

Photoresist
Silicon nitride

P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 31

 LOCOS Mask Exposure

Photoresist
Silicon nitride

P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 32

 Development

Photoresist
Silicon nitride

P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 33

 Etch Nitride

Photoresist
Silicon nitride

P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 34

 Strip Photoresist

Silicon nitride

P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 35

 Isolation Implantation

Silicon nitride
p+ p+

P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 36

 Thermal Oxidation

Silicon nitride SiO2

p+ p+

P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 37

 Strip Nitride

SiO2
p+ p+

P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 38

 Problem of LOCOS
• Bird’s beak
– Oxygen diffuse isotropically in silicon dioxide
– Oxide grow underneath nitride
– Waste surface area
• Uneven surface
– Oxide grow above the silicon surface
– Affect photolithography and thin film deposition

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 39

 Bird’s Beak of LOCOS
Activation Area
LOCOS LOCOS

Bird’s Beak

Activation Area

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 40

 Poly Buffered LOCOS (PBL)
• Reducing “bird’s beak”
• Deposit polysilicon before LPCVD nitride
• Poly-Si consumes lateral diffusing oxygen
• Reduce “bird’s beak” to 0.1 to 0.2 µm.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 41

 Poly Buffered LOCOS
Polysilicon Polysilicon
Silicon nitride Silicon nitride
p+ p+

P-type substrate P-type substrate

Pad oxidation, poly and nitride LPCVD Nitride, poly, and oxide etch, B implantation

Silicon nitride
SiO2 SiO2
p+ p+ p+ p+

P-type substrate P-type substrate

Oxidation Strip pad oxidation, poly and nitride

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 42

 Shallow Trench Isolation (STI)
• LOCOS and PBL work fine when feature
size > 0.5 µm
• Intolerable when feature < 0.35 µm
• Silicon etch and oxidation of trench was
researched to reduce oxide encroachment
• Process was then developed with CVD
oxide trench fill

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 43

 STI and LOCOS
• STI
– No bird’s beak
– Smoother surface
– More process steps
• LOCOS
– Simpler, cheaper, and production proven
– Used in IC fabrication until feature < 0.35 µm

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 44

 STI and LOCOS
• Early STI process
– Oxide etch back
– CF4/O2 chemistry
– Endpoint by C-N line
• Advanced STI process: oxide CMP
– Better process control
– Higher yield

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 45

 Early STI: Wafer Clean

P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 46

 Early STI: Grow Pad Oxide

Pad oxide

P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 47

 Early STI: LPCVD Silicon
Nitride

Pad oxide

Silicon nitride

P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 48

 Early STI: Photoresist Coating

Pad oxide

Photoresist
Silicon nitride

P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 49

 Early STI: STI Mask

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 50

 Early STI: STI Mask Alignment

Photoresist
Silicon nitride

P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 51

 Early STI: STI Mask Exposure

Photoresist
Silicon nitride

P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 52

 Early STI: Development

Photoresist
Silicon nitride

P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 53

 Early STI: Etch Nitride and Pad
Oxide

Photoresist
Silicon nitride

P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 54

 Early STI: Strip Photoresist

Silicon nitride

P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 55

 Early STI: Etch Silicon

Silicon nitride

P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 56

 Early STI: Grow Barrier Oxide

Silicon nitride

P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 57

 Early STI: Channel Stop
Implantation, Boron

Silicon nitride

Channel Stop
P-type substrate Implantation

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 58

 Early STI: CVD Oxide

CVD Oxide
Silicon nitride

Channel Stop
P-type substrate Implantation

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 59

 Early STI: Photoresist Coating

PR
CVD Oxide
Silicon nitride

Channel Stop
P-type substrate Implantation

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 60

 Early STI: Oxide Etch Back,
Stop on Nitride

Silicon nitride
CVD Oxide

Channel Stop
P-type substrate Implantation

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 61

 Early STI: Strip Nitride

CVD Oxide

Channel Stop
P-type substrate Implantation

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 62

 Early STI: Photoresist Coating

Photoresist
CVD Oxide

Channel Stop
P-type substrate Implantation

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 63

 Early STI: Oxide Etch Back

CVD Oxide
Channel Stop
P-type substrate Implantation

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 64

 Early STI: Oxide Annealing

CVD Oxide
Channel Stop
P-type substrate Implantation

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 65

 Advanced STI
• No need for channel stop ion implantation
to raise the field threshold voltage.
• Trench fill can also be achieved with O3-
TEOS process
– Need anneal at > 1000 °C to densify the film
• HDP oxide does not require thermal anneal

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 66

 Advanced STI: Pad Oxidation
and LPCVD Nitride

Nitride

P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 67
 Advanced STI: STI Mask

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 68

Advanced STI: Etch Nitride, Oxide,
and Silicon, Strip Photoresist

Nitride Nitride

P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 69
Advanced STI: HDP CVD Oxide

USG

Nitride Nitride
USG
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 70
Advanced STI: CMP Oxide, Stop
on Nitride

Nitride Nitride
USG
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 71
 Advanced STI: Nitride Strip

STI USG
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 72
 Transistor Making
• Metal gate
• Self-aligned gate
• Lightly doped drain (LDD)
• Threshold adjustment
• Anti punch-through
• Metal and high-κ gate MOS

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 73

 Transistor Making: Metal Gate
• Form source/drain first
– Diffusion doping with silicon dioxide mask
• Align gates with source/drain, then gate
area was etched and gate oxide is grown
• The third mask define the contact holes
• The fourth mask form metal gates and
interconnections.
• Last mask defined the bonding pad
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 74
 Wafer Clean, Field Oxidation,
and Photoresist Coating
Native Oxide

N-Silicon N-Silicon

Primer Field Oxide

Field Oxide

Photoresist

N-Silicon N-Silicon

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 75

Photolithography and Oxide Etch
Source/Drain Mask UV Light
Source/Drain Mask Field Oxide

Photoresist PR

N-Silicon N-Silicon

Field Oxide Field Oxide

PR PR

N-Silicon N-Silicon

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 76

 Source/drain Doping and Gate
Oxidation
Field Oxide Field Oxide

p+ p+
N-Silicon N-Silicon

Field Oxide Gate Oxide Field Oxide

p+ p+
p+ p+
N-Silicon N-Silicon

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 77

 Contact, Metallization, and
Passivation
Gate Oxide Al·Si Field Oxide
Gate Oxide Field Oxide

p+ p+ p+ p+
N-Silicon N-Silicon

Gate Oxide Field Oxide Gate Oxide CVD Cap Oxide

p+ p+ p+ p+
N-Silicon N-Silicon

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 78

 Self-aligned Gate
• Introduction of ion implantation
• NMOS instead of PMOS
• Polysilicon replaced aluminum for gate
– Al alloy can’t sustain the high temperature
post-implantation anneal

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 79

 Self-aligned Gate
• Activation area for transistors making
• Gate oxidation and polysilicon deposition
• Gate mask defines the gate and local
interconnection.
• Transistors are made after ion implantation
and thermal annealing
• Advanced MOSFET are made in this way
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 80
 Transistor Making:
Self-aligned Gate
Phosphorus Ions

Polysilicon
Gate
n+ n+
Gate oxide
p-Si

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 81

 Hot Electron Effect
• Gate width is < 2 microns,
• Vertical electric field accelerates electrons
tunneling through the thin gate oxide layer
• Hot electron effect
– gate leakage affect transistor performance
– trapping of electrons in the gate oxide cause
reliability problems for the IC chips
• LDD is used to prevent hot electron effect
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 82
 Hot Electron Effect
VG>VT>0 VD > 0

Poly Si
Gate oxide
n+ e− n+
p-Si Electron
Source Drain
injection

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 83

 LDD Formation
• Low energy, low current ion implantation
– very low dopant concentration and shallow
junction just extended underneath the gate
• Sidewall spacers can be formed by
depositing and etching back dielectric layers
• High current, low energy ion implantation
forms the heavily doped source/drain
– Source/drain are kept apart from the gate
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 84
 LDD Formation
• Reduce the vertical electric field of the
source/drain bias
• Reduce the available electrons for tunneling
• Suppress the hot electron effect

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 85

Poly Etch, PR Strip and Poly Anneal

Gate oxide Polysilicon

Gate

p-Si

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 86

 LDD implantation

Gate oxide Polysilicon

Gate
n- n-

p-Si LDD, n–

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 87

 Nitride Deposition

Nitride
Gate oxide Polysilicon Layer
Gate
n- n-

p-Si LDD, n–

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 88

 Nitride Etch Back

Sidewall
Gate oxide Polysilicon Spacer
Gate
n- n-

p-Si LDD, n–

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 89

 Source Drain Implantation

Sidewall
Gate oxide Polysilicon Spacer
Gate
n+ n+

p-Si LDD, n–

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 90

 Implantation Anneal

Sidewall
Gate oxide Polysilicon Spacer
Gate
n+ n+

p-Si LDD, n–

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 91

 Dopant Diffusion Buffer
• Sub-0.18 µm, and <1.5 V, hot electron
effect may not be so important anymore
• The LDD implantation process probably is
no longer needed.
• Sidewall spacers are still needed to provide
a diffusion buffer for the dopant in the
source/drain junction.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 92

 Dopant Diffusion Buffer
Poly-Si Sidewall Poly-Si
gate spacer gate

Gate oxide Gate oxide

Poly-Si Sidewall Poly-Si

gate spacer gate
Source/drain Source/drain
Gate oxide Gate oxide

(a) (b)
After anneal, source/drain are just right After anneal, source/drain are too close
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 93
 VT Adjustment Implantation
• Controls threshold voltage of MOSFET
– Ensure supply voltage can turn-on or turn-off
the MOSFET in IC chip
• Low energy, low current implantation
• Usually before the gate oxide growth
• Two implantations: a p-type and an n-type

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 94

 VT Adjust Implantation
STI STI
• Wafer clean (a)

• Grow sacrificial oxide (a)

• Activation mask

• Threshold adjustment implantation (b)

VT Adjust
(b) STI STI
• Strip photoresist

• Anneal

STI VT Adjust STI

• Strip sacrificial oxide (c)
(c)

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 95

Anti-punch-through Implantation
• Punch-through effect
– The depletion regions of the source and drain
short each other under the influence of both
gate-substrate bias and source-drain bias
• Anti punch-through implantation
– Medium energy, low current
– Protects transistors against punch-through
– Normally performed with well implantation
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 96
 Anti Punch-through Implantation

Phosphorus Ions
PR PR

N-well
Anti Punch-through

P-type Silicon
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 97
 Halo Implantation
• Another implantation process commonly
used to suppress punch through effect
• Low energy and low current
• Large incident angle, 45°

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 98

 Halo Implantation

45° Photoresist 45°

Polysilicon
PR Gate PR

STI
n+ n+
p p

p-Si Halo Junction VT Adjust

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 99

 High-κ Gate Dielectric
• Device sizes shrinking, tox is too thin for
MOSFET to operate reliably even at 1 V
• Need high-κ dielectric to replace SiO2 as gate
dielectric material for < 0.1 µm device
– High-κ, thicker gate dielectric, better prevention
of tunneling and breakdown
– Large enough gate capacitance to hold enough
charges to turn-on the MOSFET
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 100
 Metal Gate
• Lower resistivity
• Help to improve device speed

• A possible future transistor making process

• Metal and high-κ dielectric gate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 101

 Strip Photoresist

Polysilicon

STI STI

P-well

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 102

 Extension Ion Implantation

STI STI

P-well

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 103

 Oxide/Nitride Etch Back,

STI STI

P-well

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 104

 RPCVD Nitride

STI STI

P-well

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 105

 CVD PSG

PSG PSG

STI STI

P-well

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 106

 Strip Nitride

PSG PSG

STI STI

P-well

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 107

 Strip Polysilicon

PSG PSG

STI STI

P-well

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 108

 Strip Oxide

PSG PSG

STI STI

P-well

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 109

 Deposit (Ta2O5) and RTA

Ta2O5

PSG PSG

STI STI

P-well

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 110

 CVD Tungsten

Tungsten
PSG W PSG

STI STI

P-well

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 111

 CMP Tantalum Pentaoxide

Silicon Nitride Tungsten Gate

PSG W PSG

STI n+ n+ STI

P-well Ta2O5 Gate Dielectric

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 112

 Metal and High-κ Gate MOSFET
Dummy Gate Process
• For < 0.1 µm IC device
• PSG CMP, polysilicon and oxide stripping,
and high-κ dielectric deposition.
• Ta2O5, κ ~ 25, TiO2 κ up to 80, and HfO2
• CVD plus RTA process
• It may never be used due to complexity
• Advantage: can used Ta2O5 hard hard to etch.
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 113
 Metal and High-κ Gate MOSFET
Traditional Process
• Traditional MOSFET making process in R&D
– Dielectric deposition and annealing
– Metal deposition
– Photolithography
– Metal etch
– Ion implantation
– Rapid thermal annealing.
• Too early to predict which method will win
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 114
 Interconnection
• Making transistor: front-end
• Interconnection: back-end
– Multi metal layers with dielectric in between
– Local interconnection: silicide
– PMD: doped oxide, PSG or BPSG
– W and Al alloy metallization
– IMD: USG and FSG
– Transition to copper and low-κ interconnection
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 115
 Local Interconnection
• Connection between neighboring transistors
• Usually polysilicon or polycide stack
• WSi2, TiSi2, and CoSi2 are commonly used
– WSix: CVD process with WF6 and SiH4
• TiSi2: PVD Ti on Si then thermal anneal

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 116

 Tungsten Silicide Process
• Wafer clean Tungsten silicide
(a) Amorphous silicon
• Grow gate oxide STI STI

P-well
• Deposited amorphous silicon

• Deposited tungsten silicide (a) Photoresist

Tungsten silicide
• Gate and local interconnection mask (b) Amorphous silicon
STI STI

• Etch tungsten silicide (fluorine chemistry) (b) P-well Gate oxide

• Etch amorphous silicon (chlorine chemistry)

Tungsten Silicide
• Strip photoresist Polysilicon
(c) STI STI
• Polysilicon and silicide annealing (c) P-well Gate oxide

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 117

 Self-aligned Silicide (Salicide)
• TiSi2 and CoSi2
• Lower resistivity than WSi2
• TiSi2 when gate size > 0.2 µm
• CoSi2 when gate size < 0.2 µm
• Metal (Ti or Co) PVD
• Thermal anneal to form silicide
• Strip unreacted metal
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 118
Cobalt Self-aligned Silicide Process
Cobalt Deposition Sidewall Spacer

STI Silicon

Cobalt
RTP Silicide Alloying

Silicon
Strip Unreact Cobalt
Cobalt Silicide
Polysilicon

Silicon
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 119
Gate Oxide
 Tungsten Local Interconnection
• Lower resistance, higher speed, less power
• Damascene: similar to W plug formation
– Etched trenches are in silicate glass layer
– Deposit Ti and TiN barrier/adhesion layers
– CVD W fill trenches
– CMP to remove bulk W from wafer surface
– W left in trenches to form local interconnection

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 120

 Tungsten Local Interconnection
• CMP PSG
• Wafer clean (a)
• Local interconnection mask (a)
• Etch PSG
• Strip photoresist
• Wafer clean (b) PSG
STI n+ n+ USG p+ p+
• Argon sputtering clean (b) P-Well N-Well
P-Epi
P-Wafer
• Sputtering Ti
• Sputtering TiN Ti/TiN Barrier and Adhesion Layer

• CVD TiN PSG Tungsten

STI n+ n+ USG p+ p+
• TiN treatment (c) P-Well N-Well
P-Epi
• CVD Tungsten (c) P-Wafer

• CMP Tungsten Ti/TiN Barrier and Adhesion Layer

• CMP titanium and titanium nitride (d) PSG Tungsten
n+
n+ USG p+ p+
• Wafer clean (d) STI P-Well N-Well
P-Epi
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm P-Wafer 121
 Mask 10: Local Interconnection

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 122

 Strip Photoresist/Clean

PSG
STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 123
 PVD Ti/TiN and CVD TiN/W

Ti/TiN Barrier and Adhesion Layer

PSG Tungsten

STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 124
 CMP W/TiN/Ti, Clean

Ti/TiN Barrier and Adhesion Layer

PSG Tungsten

STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 125
 Early Global Interconnection
• Oxide CVD
• Photolithography, oxide etch, and PR strip
• Metal PVD
• Photolithography, metal etch, and PR strip
– Oxide etch forms contact or via holes
– metal etch forms interconnection lines

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 126

 Early Aluminum PSG

Interconnection (a) p+
n+ n+ SiO2
p+
p+
N-well
p+

P-type substrate
• CVD PSG (a)
PSG
• PSG reflow (b) SiO2
(b) p+ n+ n+
p+
p+ p+

• Wafer clean P-type substrate

N-well

• Contact hole mask PSG

SiO2
• Etch PSG (c) p +
n+ n+
p+
p+ p+
N-well
• Strip photoresist (c) P-type substrate

• Wafer clean Al ·Si

PSG
SiO2
• Deposit Al alloy (d) (d) p+
n+ n+
p+
p+ p+
N-well
• Metal interconnection mask P-type substrate

• Etch metal Al ·Si

PSG
• Strip photoresist (e) (e) p+
n+ n+ SiO2
p+
p+ p+
N-well
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 127
• Metal anneal P-type substrate
 Multi-level Interconnection
• Earlier interconnection has rough surface
• problems in photolithography and metal PVD
• Tungsten to fill narrow contact and via holes

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 128

 Multi-level Interconnection
• The basics interconnection process steps:
– Dielectric CVD and planarization
– Photolithography, oxide etch, and PR strip
– W CVD, bulk W removal
– Metal stack PVD,
– Photolithography, oxide etch, and PR strip
• PSG or BPSG for PMD and USG for IMD

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 129

 Multi-level Interconnection
• Dielectric CMP for planarization
• W CMP to removal bulk tungsten
• Metal stack: Ti welding layer, Al·Cu alloy,
and TiN ARC
• Metal etch defines metal interconnection lines

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 130

PE-TEOS USG Dep/Etch/Dep/CMP

IMD 1 USG Dep/Etch/Dep/CMP

Al-Cu Alloy

W BPSG

STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 131
 Via Etch, Etch USG

IMD 1 USG

Al-Cu Alloy

W BPSG

STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 132
 Tungsten CVD and CMP

IMD 1 USG W
Al-Cu Alloy

W BPSG

STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 133
 Via Etch, Etch USG
Metal 2 Al-Cu Alloy

IMD 1 USG

M1 Al-Cu Alloy

W BPSG

STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 134
 Etch Metal 2
M2 Al•Cu

IMD 1 USG

M1 Al•Cu Alloy

W BPSG

STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 135
 Copper Interconnection
• Lower resistivity and higher resistance
toelectromigration than aluminum alloy
• Faster and reliable interconnection
• Hard to dry etch delayed copper application
• CMP developed and matured in the 1990s
• Used in bulk W removal for plug formation
• Copper process is similar to W plug process
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 136
 Copper Interconnection
• Trenches are etched on dielectric surface
• Copper is deposited into the trenches
• CMP removes bulk copper layer on surface
• Copper lines embedded in dielectric layer
• No need for metal etch

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 137

 Copper Interconnection
• Dual damascene process
• Most commonly used method for the copper
metallization
– Photolithography, etch via, and PR strip
– Photolithography, etch trench, and PR strip
– Metal depositions and anneal
– Metal CMP

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 138

 Basic Differences
• Traditional process: one dielectric etch and
one metal etch
• Dual damascene copper process: two
dielectric etches, no metal etch
• The main challenges of the dual damascene
copper process are dielectric etch, metal
deposition and metal CMP

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 139

PECVD Nitride/USG/nitride/USG

USG
USG

PSG W

STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 140
Via Mask, Etch Via, and Strip PR

USG
USG

PSG W

STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 141
Trench Mask, Etch Trench, Strip PR

USG
USG

PSG W

STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 142
PVD Ta and Cu, ECP Bulk Cu, Anneal
Copper
USG
USG

PSG W

STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 143
CMP Cu and Ta, PECVD Nitride

M1 USG Cu
USG

PSG W

STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 144
 Copper Metallization
• Nitride seal layer prevent copper diffusion
and oxidation
• Etch stop nitride separate via and trench etch
• Tantalum used as copper barrier layer
• PVD copper seed layer
• ECP bulk copper

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 145

 Copper and Low-κ
• Further increase IC chip speed
• low-κ dielectric still in R&D
• α-CF, κ = 2.5 to 2.7
• Can’t be etched with fluorine chemistry
• It needs oxygen chemistry to etch
• New challenges for the process integration

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 146

 PECVD α-CF, USG, Via Mask,
and Etch USG Hard Mask

Photoresist
α-CF

PSG Tungsten

STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 147
 PECVD α-CF and USG

α-CF
α-CF

PSG Tungsten

STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 148
 Etch α-CF and Seal Nitride

α-CF
α-CF

PSG Tungsten

STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 149
 PVD Ta, Cu Seed, and ECP Cu
Tantalum
Copper

Cu Cu α-CF
α-CF

PSG Tungsten

STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 150
 CMP Copper and Tantalum

Tantalum

Cu Cu α-CF
α-CF

PSG Tungsten

STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 151
 Copper and Low-κ
• Oxygen plasma is used to etch α-CF
• PR can’t last long in oxygen plasma
• SiO2 hard mask is needed
• Oxygen can’t etch oxide and nitride
• Trench and via can be etched at the same time
– High selectivity of α-CF to oxide and nitride
• PR is removed when oxygen plasma etch α-CF
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 152
 Passivation
• Protect IC chip from moisture and other
contaminants such as sodium
• Silicon nitride is the most commonly used
• Usually oxide layer is used as a stress buffer
• SiH4 based PECVD for both oxide and nitride
• Bonding pad mask or connecting bump mask
• Fluorine based nitride/oxide etch
• Strip PR to finish wafer processing
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 153
 Metal Anneal

Metal 4, Al•Cu
USG

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 154

 PECVD Oxide

Oxide
Metal 4, Al•Cu
USG

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 155

 PECVD Nitride

Nitride
Oxide
Metal 4, Al•Cu
USG

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 156

 Photoresist Coating

Photoresist
Nitride
Oxide
Metal 4, Al•Cu
USG

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 157

Bonding Pad Mask Exposure and
Development
Photoresist
Nitride
Oxide
Metal 4, Al•Cu
USG

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 158

 Etch Nitride and Oxide

Photoresist
Nitride
Oxide
Metal 4, Al•Cu
USG

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 159

 Strip Photoresist

Nitride
Oxide
Metal 4, Al•Cu
USG

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 160

 Summary
• Well formation process
• Isolations: field oxide, LOCOS, and STI
• Sidewall spacer for LDD and salicide
• Al, poly-Si and silicide for gate and local
interconnections
• W, Ti and Al alloy are commonly used in
traditional interconnection process.
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 161
 Summary
• Basic process steps for copper metallization
are dielectric deposition, dielectric etches,
metal deposition, and metal polishing
• Silicon nitride is the most commonly used
passivation materials in IC processing

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 162

 Chapter 14
CMOS Processes
Hong Xiao, Ph. D.
[email protected]
www2.austin.cc.tx.us/HongXiao/Book.htm

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 1

 Objectives
• List the major process technology changes
from the 1980 to the 1990s
• Explain the differences between copper
metallization and traditional metallization

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 2

 From 1960s to 1970s
• 1960s • 1970s
– PMOS – NMOS
– Diffusion – Ion implantation
– Metal gate – Polysilicon gate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 3

 1980’s Technology
• LCD replacing LED as indicators for
electronic watches and calculators
• CMOS IC replacing NMOS IC for lower
power consumption
• Minimum feature size: from 3 µm to 0.8 µm
• Wafer size: 100 mm (4 in) to 150 mm (6 in)

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 4

 1980’s CMOS Technology
• LOCOS
• PSG and reflow
• Evaporator for metal deposition
• Positive photoresist
• Projection printer
• Plasma etch and wet etch

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 5

1980’s Technology, Wafer Clean

P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 6

 Pad Oxidation

Pad oxide

P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 7

 LPCVD Nitride

Pad oxide

Silicon nitride

P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 8

 Photoresist Coating

Pad oxide

Photoresist
Silicon nitride

P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 9

 Mask 1, LOCOS

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 10

 Mask 1, LOCOS

Photoresist
Silicon nitride

P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 11

 Alignment and Exposure

Photoresist
Silicon nitride

P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 12

 Development

Photoresist
Silicon nitride

P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 13

 Etch Nitride

Photoresist
Silicon nitride

P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 14

 Strip Photoresist

Silicon nitride

P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 15

 Isolation Implantation

Silicon nitride
p+ p+

P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 16

 LOCOS Oxidation

Silicon nitride SiO2

p+ p+

P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 17

Strip Nitride and Pad Oxide, Clean

SiO2
p+ p+

P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 18

 Screen Oxidation

SiO2
p+ p+ p+

P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 19

 Photoresist Coating

Photoresist
SiO2
p+ p+ p+

P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 20

 Mask 2, N-well

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 21

 Mask 2, N-well

Photoresist
SiO2
p+ p+ p+

P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 22

 Exposure

Photoresist
SiO2
p+ p+ p+

P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 23

 Development

Photoresist
SiO2
p+ p+ p+

P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 24

 N-well Implantation

Phosphorus Ions

Photoresist
SiO2
N-well
p+ p+ p+

P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 25

 Strip Photoresist

SiO2
N-well
p+ p+ p+

P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 26

 N-well Drive-in

SiO2
p+ p+
N-well
P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 27

 Strip Screen Oxide

SiO2
p+ p+
N-well
P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 28

 Grow Sacrificial Oxide

SiO2
p+ p+
N-well
P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 29

 Strip Sacrificial Oxide

SiO2
p+ p+
N-well
P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 30

 Grow Gate Oxide

SiO2
p+ p+
N-well
P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 31

 Deposit Polysilicon

Gate Oxide Polysilicon

SiO2
p+ p+
N-well
P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 32

 Photoresist Coating

Polysilicon

SiO2
p+ p+
N-well
P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 33

 Mask 3, Gate and Local
Interconnection

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 34

 Mask 3, Gate and Local
Interconnection
Polysilicon

SiO2
p+ p+
N-well
P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 35

 Exposure

Polysilicon

SiO2
p+ p+
N-well
P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 36

 Development

Polysilicon

SiO2
p+ p+
N-well
P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 37

 Etch Polysilicon

Polysilicon Gate
PR
SiO2
p+ p+
N-well
P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 38

 Strip Photoresist

Polysilicon

SiO2
p+ p+
N-well
P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 39

 Photoresist Coating

Polysilicon

Photoresist
SiO2
p+ p+
N-well
P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 40

 Mask 4, n-Source/Drain

Photoresist
SiO2
p+ p+
N-well
P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 41

 Exposure

Photoresist
SiO2
p+ p+
N-well
P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 42

 Development

Photoresist
SiO2
p+ p+
N-well
P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 43

 N-Source/Drain Ion Implantation

P+ implantation
Photoresist
SiO2
p+ p+
N-well
P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 44

 Strip Photoresist

Photoresist
SiO2
p+ p+
N-well
P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 45

 Photoresist Coating

SiO2
p+ p+
N-well
P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 46

Mask 5, P-Source/Drain Exposure

SiO2
p+ p+
N-well
P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 47

 Development

SiO2
p+ p+
N-well
P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 48

 P-Source/Drain Implantation

B+ implantation

SiO2
p+ p+
N-well
P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 49

 Strip Photoresist

SiO2
p+ p+
N-well
P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 50

 Anneal

SiO2
n+ n+ p+ p+
p+ p+
N-well
P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 51

 LPCVD Barrier Nitride

SiO2
n+ n+ p+ p+
p+ p+
N-well
P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 52

 CVD BPSG

BPSG
SiO2
n+ n+ p+ p+
p+ p+
N-well
P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 53

 BPSG Reflow

BPSG
SiO2
n+ n+ p+ p+
p+ p+
N-well
P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 54

 Photoresist Coating

BPSG
SiO2
n+ n+ p+ p+
p+ p+
N-well
P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 55

 Mask 6, Contact Exposure

BPSG
SiO2
n+ n+ p+ p+
p+ p+
N-well
P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 56

 Development

BPSG
SiO2
n+ n+ p+ p+
p+ p+
N-well
P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 57

 Contact Etch

BPSG
SiO2
n+ n+ p+ p+
p+ p+
N-well
P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 58

 Strip Photoresist

BPSG
SiO2
n+ n+ p+ p+
p+ p+
N-well
P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 59

 Metal Deposition

Al·Cu·Si
BPSG
SiO2
n+ n+ p+ p+
p+ p+
N-well
P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 60

 Photoresist Coating

Al·Cu·Si
BPSG
SiO2
n+ n+ p+ p+
p+ p+
N-well
P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 61

 Mask 7, Metal Interconnection
Exposure

Al·Cu·Si
BPSG
SiO2
n+ n+ p+ p+
p+ p+
N-well
P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 62

 Development

Al·Cu·Si
BPSG
SiO2
n+ n+ p+ p+
p+ p+
N-well
P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 63

 Etch Metal

Al·Cu·Si
BPSG
SiO2
n+ n+ p+ p+
p+ p+
N-well
P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 64

 Strip Photoresist

Al·Cu·Si
BPSG
SiO2
n+ n+ p+ p+
p+ p+
N-well
P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 65

 CVD USG

USG
Al·Cu·Si
BPSG
SiO2
n+ n+ p+ p+
p+ p+
N-well
P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 66

 CVD Nitride

Nitride
USG
Al·Cu·Si
BPSG
SiO2
n+ n+ p+ p+
p+ p+
N-well
P-type substrate

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 67

 1990’s Technology
• Driving force: digital logic electronics
– PC, telecommunication, and internet.
• Feature size: from 0.8 µm to 0.18 µm
• Wafer size: from 150 mm to 300 mm

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 68

 1990’s CMOS Technology
• Epitaxy silicon
• Shallow trench isolation
• The sidewall spacer for LDD and salicide
• Polycide gates and local interconnections
reduce resistance and improve device speed
– Tungsten silicide and titanium silicide.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 69

 1990’s CMOS Technology
• Photolithography
– G-line, I-line (365 nm), and DUV 248 nm
– Positive photoresist
– Steppers replaced projection printer
– Track-stepper integrated systems
• Plasma etches for patterned etch
• Wet etches for blanket film stripping

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 70

 1990’s CMOS Technology
• Vertical furnaces
– smaller footprints, better contamination control.
• RTP systems
– post-implantation annealing
– silicide formation,
– faster, better process and thermal budget control.
• DC magnetron sputtering replaced evaporation

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 71

 1990’s CMOS Technology
• Multi-layer metal interconnection
• W CVD and CMP (or etch back) to form plugs
• Ti and TiN barrier/adhesion layer for W
• Ti welding layer for Al-Cu to reduce contact
resistance
• TiN ARC

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 72

 1990’s CMOS Technology
• BPSG was popularly used as PMD.
• DCVD: PE-TEOS and O3-TEOS
– STI, sidewall spacer, PMD, and IMD
• DCVD: PE-silane
– PMD barrier nitride, dielectric ARC, and PD nitride
• Tungsten CMP to form plug
• Dielectric CMP for planarization
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 73
 1990’s CMOS Technology
• Cluster tools became very popular
• Single wafer processing systems improve
wafer-to-wafer uniformity control
• Batch systems is still commonly employed
in many non-critical processes for their high
throughput.

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 74

 Epitaxy Deposition

P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 75
 Mask 1: N-well

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 76

 N-well Implantation

Phosphorus Ions

Photoresist
N-Well

P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 77
 Mask 2: P-well

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 78

 P-well Implantation

Boron Ions

Photoresist

P-Well
N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 79
Strip PR, Strip Nitride/Pad Oxide

P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 80
 Pad Oxidation, LPCVD Nitride

Nitride

P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 81
Mask 3: Shallow Trench Isolation

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 82

Etch Nitride, Pad Oxide and Silicon

Nitride Nitride

P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 83
 HDP-CVD USG Trench Fill

USG

Nitride Nitride
USG
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 84
 CMP USG, Stop on Nitride

Nitride Nitride
USG
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 85
Strip Nitride and Pad Oxide, Clean

STI USG
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 86
 Mask 4: N-channel VT Adjust

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 87

 Phosphorus Ions
Photoresist
STI USG
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 88
 Mask 5: P-channel VT Adjust

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 89

 Boron Ions
Photoresist
STI USG
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 90
Gate Oxidation, LPCVD Polysilicon

Polysilicon
STI USG
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 91
Mask 6: Gate & Local Interconnection

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 92

 Etch Polysilicon

Gate Oxide Photoresist

Polysilicon gate
STI USG
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 93
 Mask 7: N-channel LDD

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 94

N-channel LDD Implantation, Arsenic

Arsenic Ions

Photoresist

STI USG
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 95
 Mask 8: P-channel LDD

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 96

P-channel LDD Implantation, BF2+

BF2+ Ions

Photoresist

STI USG
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 97
 Sidewall Spacer

Sidewall Sidewall
Polysilicon gate Spacer Polysilicon gate Spacer

n- LDD n- LDD n- LDD Gate oxide n- LDD

Gate oxide

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 98

 Mask 9: N-channel Source/Drain

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 99

N-channel Source/Drain Implantation

Phosphorus Ions
Photoresist

n+ n+ USG p- p-
STI
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 100
 Mask 9: P-channel Source/Drain

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 101

P-channel Source/Drain Implantation

Boron Ions

Photoresist

STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 102
 Titanium Salicide Process
Ar + Ar +
Ti
Sidewall Sidewall
spacer Polysilicon gate spacer Polysilicon gate

n- n- n- n-
n+ Gate oxide Gate oxide
n+ n+ n+

Ti
TiSi2 TiSi 2 TiSi2
TiSi2
Polysilicon gate Polysilicon gate

n- n- n- n-
n+ Gate oxide n+ Gate oxide
n+ n+

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 103

Titanium Self-aligned silicide Process
Titanium Deposition Sidewall Spacer

STI Silicon

Titanium
RTP Silicide Alloying

Silicon
Strip Unreact Titanium
Titanium Silicide
Polysilicon

Silicon
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 104
Gate Oxide
 BPSG Deposition and Reflow

BPSG

STI n+ n+ USG p+ p+

BPSG

STI n+ n+ USG p+ p+
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 105
 Mask 10: Contact Hole

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 106

 Contact Hole Etch, BPSG Etch

BPSG

STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 107
 Contact Hole Etch, BPSG Etch

Titanium/Titanium Nitride
Tungsten

BPSG

STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 108
 Contact Hole Etch, BPSG Etch

Titanium/Titanium Nitride TiN ARC Titanium

Aluminum Copper Alloy

W BPSG

STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 109
 Mask 11: Metal 1 Interconnect

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 110

 Metal Etch

Titanium/Titanium Nitride TiN ARC Titanium

Al-Cu Alloy

W BPSG

STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 111
PE-TEOS USG Dep/Etch/Dep/CMP

IMD 1 USG Dep/Etch/Dep/CMP

Al-Cu Alloy

W BPSG

STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 112
 Mask 12: Via 1

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 113

 Via Etch, Etch USG

IMD 1 USG

Al-Cu Alloy

W BPSG

STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 114
 Via Etch, Etch USG
Metal 2 Al-Cu Alloy

IMD 1 USG

M1 Al-Cu Alloy

W BPSG

STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 115
 Mask 13: Metal 2 Interconnect

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 116

 Etch Metal 2
M2 Al•Cu

IMD 1 USG

M1 Al•Cu Alloy

W BPSG

STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 117
 USG Dep/Etch/Dep/CMP
IMD 2 USG

M2 Al•Cu

IMD 1 USG

M1 Al•Cu Alloy

W BPSG

STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 118
 Mask 14: Via 2

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 119

 Via 2 Etch, Etch USG
IMD 2 USG

M2 Al•Cu

IMD 1 USG

M1 Al•Cu Alloy

W BPSG

STI n+ n+ USG p+ p+
P-Well N-Well
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 120
 Metallization of Metal 3
Metal 3 Al•Cu Alloy

IMD 2 USG W

M2 Al•Cu

IMD 1 USG

M1 Al•Cu Alloy

W BPSG

STI n+ n+ USG p+ p+
P-Well N-Well
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 121
 Mask 15: Metal 3 Interconnects

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 122

Metal Etch, PR Strip and Metal Anneal
Metal 3 Al•Cu Alloy

IMD 2 USG W

M2 Al•Cu

IMD 1 USG

M1 Al•Cu Alloy

W BPSG

STI n+ n+ USG p+ p+
P-Well N-Well
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 123
PE-TEOS USG Dep/Etch/Dep/CMP

IMD 3 USG

Metal 3 Al•Cu Alloy

IMD 2 USG W

M2 Al•Cu

IMD 1 USG

Hong Xiao, Ph. D.

M1 Al•Cu Alloy
www2.austin.cc.tx.us/HongXiao/Book.htm 124
 Mask 16: Via 3

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 125

 Via 3 Etch and PR Strip
IMD 3 USG

Metal 3 Al•Cu Alloy

IMD 2 USG W

M2 Al•Cu

IMD 1 USG

Hong Xiao, Ph. D.

M1 Al•Cu Alloy
www2.austin.cc.tx.us/HongXiao/Book.htm 126
 Metal 4 Deposition
Al•Cu
Metal 4
IMD 3 USG

Metal 3 Al•Cu Alloy

IMD 2 USG W

M2 Al•Cu

IMD 1 USG

Hong Xiao, Ph. D.

M1 Al•Cu Alloy
www2.austin.cc.tx.us/HongXiao/Book.htm 127
 Mask 17: Metal 4 Interconnects

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 128

 Etch Metal 4

Al•Cu Alloy Al•Cu

Metal 4
IMD 3 USG

Metal 3 Al•Cu Alloy

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 129

Passivation Dielectric Deposition
Silicon Nitride

USG
Al•Cu Alloy Al•Cu
Metal 4
IMD 3 USG

Metal 3 Al•Cu Alloy

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 130

 Mask 18: Bonding Pad

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 131

 Etch Bonding Pad, Strip PR
Silicon Nitride

USG
Al•Cu Alloy Al•Cu
Metal 4
IMD 3 USG

Metal 3 Al•Cu Alloy

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 132

 Passivation 2 Silicon Nitride

Passivation 1
Al•Cu Alloy Al•Cu USG
Metal 4
IMD33
IMD USG
Ti/TiN
TiN ARC
Metal 3 Al•Cu Alloy
Ti
IMD 2 USG W
Ti/TiN

M2 Al•Cu

IMD 1 USG W TiSi2

M1 Al•Cu Alloy Sidewall

PMD BPSG Spacer, USG
W
Poly-Si
PMD Barrier
STI n+ n+ USG p+ p+
Nitride
P-Well N-Well
P-Epi
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 133
P-Wafer
 State-of-art Technology
• The 2000’s Technology
• Feature size 0.13 µm or smaller
• Wafer size 200 mm or 300 mm

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 134

 State-of-art Technology
• Silicon on isolator (SOI) with STI
– Completely isolate the transistor on the silicon
surface from the bulk silicon substrate
– Eliminate radiation-induced soft error.
• Increase the packing density of IC chip.
• High radiation resistance
• SOI chips will become the mainstream for
the high-performance electronics
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 135
 State-of-art Technology
• Copper and low-κ to reduce RC delay,
• Lower power consumption, higher IC speed
• Dual damascene process
– Two dielectric etches, no metal etch
– Uses metal CMP instead of metal etch
• Main challenges: dielectric etch, metal
deposition, and metal polish
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 136
 State-of-art Technology
• Copper metallization: Cu seed, Ta/TaN
barrier, Cu ECP, anneal, and metal CMP
• Low-κ dielectric: still in development
– CVD and spin-on dielectric (SOD).
– CVD: familiar technologies, existing process
equipment and experience
– SOD: extendibility to very low dielectric
constant (κ<2) with porous silica
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 137
 Lead-tin alloy
Nitride

State-of-Art Copper 5 SOD

PSG

SOI CMOS IC SOD

Copper 4

with Copper SOD

SOD

and Low-κ Cu 3 SOD Cu 3

SOD

Interconnection Copper 2 SOD

SOD

Cu 1 Cu 1 SOD Cu 1 Cu 1
SOD

W Tungsten PSG
Hong Xiao, Ph. D. n+
www2.austin.cc.tx.us/HongXiao/Book.htm
STI n+ USG p+ p+ 138
USG
P-well N-well
Buried SiO 2 P-wafer
 Bare wafer

P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 139
 High Current Oxygen Ion
Implantation

Oxygen ions, O+

P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 140
 Oxide Anneal

Buried SiO2 P-wafer

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 141
 Wafer Clean

Buried SiO2 P-wafer

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 142
 Epitaxial Silicon Deposition

P-epi
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 143
 Wafer Clean

P-epi
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 144
 Oxidation, Screen Oxide

P-epi
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 145
 Photoresist Coating and Baking

Photoresist
P-epi
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 146
 Mask 0, Alignment Mark

Photoresist
P-epi
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 147
 Exposure

Photoresist
P-epi
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 148
PEB, Development, and Inspection

Photoresist
P-epi
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 149
 Etch Oxide, Etch silicon

Photoresist
P-epi
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 150
 Strip Photoresist

P-epi
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 151
 Strip Screen Oxide

P-epi
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 152
 Wafer Clean

P-epi
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 153
 Oxidation, Pad Oxide

P-epi
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 154
 LPCVD Silicon Nitride

Nitride
P-epi
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 155
 Photoresist Coating and Baking

Photoresist
Nitride
P-epi
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 156
 Mask 1: Shallow Trench Isolation

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 157

 Alignment and Exposure

Photoresist
Nitride
P-epi
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 158
PEB, Development, and Inspection

Photoresist
Nitride
P-epi
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 159
 Etch Nitride and Pad Oxide

Photoresist
Nitride
P-epi
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 160
 Strip Photoresist

Nitride
P-epi
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 161
 Etch Silicon

Nitride
P-epi P-epi
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 162
 Wafer Clean

Nitride
P-epi P-epi
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 163
 Oxidation, Barrier Oxide

Nitride
P-epi P-epi
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 164
 HDP CVD USG

Nitride
P-epi USG P-epi USG
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 165
 CMP USG

Nitride
P-epi USG P-epi USG
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 166
 Strip Nitride

P-epi USG P-epi USG

Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 167
 Strip Pad Oxide

STI P-epi USG P-epi USG

Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 168
 Wafer Clean

STI P-epi USG P-epi USG

Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 169
 Oxidation, Sacrificial Oxide

STI P-epi USG P-epi USG

Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 170
 Photoresist Coating and Baking

Photoresist

STI P-epi USG P-epi USG

Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 171
 Mask 2: N-well

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 172

 Alignment and Exposure

Photoresist

STI P-epi USG P-epi USG

Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 173
PEB, Development, and Inspection

Photoresist

STI P-epi USG P-epi USG

Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 174
 N-well Implantations

Phosphorus ions, P+

Photoresist

STI P-epi USG USG

N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 175
 PMOS VT Adjust Implantation

Boron ions, B+

Photoresist

STI P-epi USG USG

N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 176
 Strip Photoresist

STI P-epi USG USG

N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 177
 Photoresist Coating and Baking

Photoresist

STI P-epi USG USG

N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 178
 Mask 3: P-well

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 179

 Alignment and Exposure

Photoresist

STI P-epi USG USG

N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 180
PEB, Development, and Inspection

Photoresist

STI P-epi USG USG

N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 181
 P-well Implantations

Boron ions, B+

Photoresist

STI USG USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 182
 NMOS VT Adjust Implantation

Phosphorus ions, P+

Photoresist

STI USG USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 183
 Strip Photoresist

STI USG USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 184
 Strip Sacrificial Oxide

STI USG USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 185
 Wafer Clean

STI USG USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 186
 Gate Oxidation

STI USG USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 187
 LPCVD Amorphous Silicon

Gate oxide

α-Si
STI USG USG
P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 188
 Photoresist Coating and Baking

Photoresist
α-Si
STI USG USG
P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 189
 Mask 4, Gate and Local
Interconnection

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 190

 Alignment and Exposure

Photoresist
α-Si
STI USG USG
P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 191
PEB, Development, and Inspection

Photoresist
α-Si
STI USG USG
P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 192
 Etch Amorphous Silicon

Photoresist
α-Si Gate oxide

STI USG USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 193
 Strip Photoresist

α-Si
STI USG USG
P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 194
 Wafer Clean

α-Si
STI USG USG
P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 195
Polysilicon Annealing and Oxidation

Poly Si

STI USG USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 196
 Photoresist Coating and Baking

Photoresist
Poly
STI USG USG
P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 197
Mask 5, NMOS LDD Implantation

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 198

 Alignment and Exposure

Photoresist
Poly
STI USG USG
P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 199
PEB, Development, and Inspection

Photoresist

STI USG USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 200
 NMOS LDD Implantation

Antimony ions, Sb+

Photoresist

STI USG USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 201
 Strip Photoresist

STI USG USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 202
 Photoresist Coating and Baking

Photoresist
Poly
STI USG USG
P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 203
Mask 6: PMOS LDD Implantation

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 204

 Alignment and Exposure

Photoresist
Poly
STI USG USG
P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 205
PEB, Development, and Inspection

Photoresist
Poly
STI USG USG
P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 206
 PMOS LDD Implantation

Boron ions, BF2+

Photoresist
Poly
STI USG USG
P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 207
 Strip Photoresist

STI USG USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 208
 CVD USG, CVD Nitride

STI USG USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 209
 Nitride and USG Etchback

Polysilicon gate Sidewall spacers

STI USG USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 210
 Photoresist Coating and Baking

Photoresist

STI USG USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 211
Mask 7, NMOS S/D Implantation

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 212

 Alignment and Exposure

Photoresist

STI USG USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 213
PEB, Development, and Inspection

Photoresist

STI USG USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 214
 NMOS S/D Implantation

Arsenic ions, As +

Photoresist

STI USG USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 215
 Strip Photoresist

STI n+ n+ USG USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 216
 Photoresist Coating and Baking

Photoresist

STI n+ n+ USG USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 217
Mask 8, PMOS S/D Implantation

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 218

 Alignment and Exposure

Photoresist

STI n+ n+ USG USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 219
PEB, Development, and Inspection

Photoresist

STI n+ n+ USG USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 220
 PMOS S/D Implantation

Boron ions, B+
Photoresist

STI n+ n+ USG USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 221
 Strip Photoresist

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 222
 Rapid Thermal Annealing

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 223
 Argon Sputtering Etch

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 224
Co and TiN Sputtering Deposition

TiN
Co

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 225
 Rapid Thermal Annealing

TiN
Co
CoSi2

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 226
Strip Titanium Nitride and Cobalt

CoSi2

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 227
 PECVD Nitride

CoSi2

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 228
 HDP CVD PSG

PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 229
 CMP PSG

PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 230
 Photoresist Coating and Baking

Photoresist

PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 231
 Mask 9, Contact and Local
Interconnection

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 232

 Alignment and Exposure

Photoresist

PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 233
PEB, Development, and Inspection

PR

PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 234
 Etch PSG

PR

PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 235
 Strip Photoresist

PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 236
 Argon Sputtering Etch

PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 237
Ti and TiN Sputtering Deposition

Ti/TiN glue and barrier layers

PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 238
 Tungsten CVD

Ti/TiN glue and barrier layers

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 239
 W, TiN, and Ti CMP

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 240
PECVD Silicon Carbide Seal Layer

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 241
Spin-on Dielectric (SOD) Coating

SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 242
 SOD Cure

SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 243
 PECVD SiC Etch Stop Layer

SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 244
 SOD Coating and Curing

SOD
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 245
 PE-TEOS Cap

SOD
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 246
 Photoresist Coating and Baking

Photoresist
SOD
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 247
 Mask 10, Via 1

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 248

 Alignment and Exposure

Photoresist
SOD
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 249
PEB, Development, and Inspection

Photoresist
SOD
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 250
Etch PE-TEOS&SOD, Stop on SiC

Photoresist
SOD
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 251
 Strip Photoresist

SOD
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 252
 Photoresist Coating and Baking

Photoresist
SOD
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 253
 Mask 11, Metal Trench 1

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 254

 Alignment and Exposure

Photoresist
SOD
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 255
PEB, Development, and Inspection

Photoresist
SOD
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 256
 Etch Trench

Photoresist
SOD
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 257
 Strip Photoresist

SOD
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 258
 Argon Sputtering Clean

SOD
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 259
 Ta and TaN Barrier Layer PVD

SOD
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 260
 Cu Seed Layer PVD

SOD
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 261
Bulk Copper Electrochemical Plating

Cu 1 Cu 1 SOD Cu 1 Cu 1
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 262
 Copper Anneal

Cu 1 Cu 1 SOD Cu 1 Cu 1
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 263
 Cu, Ta, and TaN CMP

Cu 1 Cu 1 SOD Cu 1 Cu 1
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 264
 PECVD SiC Seal Layer

Cu 1 Cu 1 SOD Cu 1 Cu 1
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 265
Spin-on Dielectric (SOD) Coating

SOD

Cu 1 Cu 1 SOD Cu 1 Cu 1
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 266
 SOD Curing

SOD

Cu 1 Cu 1 SOD Cu 1 Cu 1
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 267
 PECVD SiC Etch Stop Layer

SOD

Cu 1 Cu 1 SOD Cu 1 Cu 1
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 268
 SOD Coating and Curing

SOD
SOD

Cu 1 Cu 1 SOD Cu 1 Cu 1
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 269
 PE-TEOS Cap

SOD
SOD

Cu 1 Cu 1 SOD Cu 1 Cu 1
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 270
 Photoresist Coating and Baking

SOD
SOD

Cu 1 Cu 1 SOD Cu 1 Cu 1
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 271
 Mask 12, Metal Trench 2

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 272

 Alignment and Exposure

SOD
SOD

Cu 1 Cu 1 SOD Cu 1 Cu 1
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 273
PEB, Development, and Inspection

SOD
SOD

Cu 1 Cu 1 SOD Cu 1 Cu 1
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 274
 Etch Trench, Stop on SiC Layer

Photoresist
SiC SOD
SOD

Cu 1 Cu 1 SOD Cu 1 Cu 1
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 275
 Strip Photoresist

SiC SOD
SOD

Cu 1 Cu 1 SOD Cu 1 Cu 1
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 276
 Photoresist Coating and Baking

Photoresist
SOD
SOD

Cu 1 Cu 1 SOD Cu 1 Cu 1
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 277
 Mask 13, Via 2

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 278

 Alignment and Exposure

Photoresist
SOD
SOD

Cu 1 Cu 1 SOD Cu 1 Cu 1
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 279
PEB, Development, and Inspection

Photoresist
SOD
SOD

Cu 1 Cu 1 SOD Cu 1 Cu 1
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 280
 Via2 Etch

Photoresist
SOD
SOD

Cu 1 Cu 1 SOD Cu 1 Cu 1
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 281
 Strip Photoresist

SOD
SOD

Cu 1 Cu 1 SOD Cu 1 Cu 1
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 282
 Hydrogen Plasma Clean

SOD
SOD

Cu 1 Cu 1 SOD Cu 1 Cu 1
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 283
 Ta and TaN Barrier Layer PVD

SOD
SOD

Cu 1 Cu 1 SOD Cu 1 Cu 1
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 284
 Cu Seed Layer PVD

SOD
SOD

Cu 1 Cu 1 SOD Cu 1 Cu 1
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 285
 Bulk Cu ECP

Copper 2 SOD
SOD

Cu 1 Cu 1 SOD Cu 1 Cu 1
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 286
 Copper Anneal

Copper 2 SOD
SOD

Cu 1 Cu 1 SOD Cu 1 Cu 1
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 287
 Cu, Ta, and TaN CMP

Copper 2 SOD
SOD

Cu 1 Cu 1 SOD Cu 1 Cu 1
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 288
PECVD SiC, SOD Coating and Curing

SOD
Copper 2 SOD
SOD

Cu 1 Cu 1 SOD Cu 1 Cu 1
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 289
 PECVD SiC Etch Stop Layer

SOD
Copper 2 SOD
SOD

Cu 1 Cu 1 SOD Cu 1 Cu 1
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 290
 Photoresist Coating and Baking
Photoresist

SOD
Copper 2 SOD
SOD

Cu 1 Cu 1 SOD Cu 1 Cu 1
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 291
 Mask 14, Via 3

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 292

 Alignment and Exposure
Photoresist

SOD
Copper 2 SOD
SOD

Cu 1 Cu 1 SOD Cu 1 Cu 1
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 293
PEB, Development, and Inspection
Photoresist

SOD
Copper 2 SOD
SOD

Cu 1 Cu 1 SOD Cu 1 Cu 1
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 294
 Etch SiC
Photoresist

SOD
Copper 2 SOD
SOD

Cu 1 Cu 1 SOD Cu 1 Cu 1
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 295
 Strip Photoresist

SOD
Copper 2 SOD
SOD

Cu 1 Cu 1 SOD Cu 1 Cu 1
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 296
SOD Coating & Curing, PE-TEOS Cap
SOD

SOD
Copper 2 SOD
SOD

Cu 1 Cu 1 SOD Cu 1 Cu 1
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 297
 Photoresist Coating and Baking
SOD

SOD
Copper 2 SOD
SOD

Cu 1 Cu 1 SOD Cu 1 Cu 1
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 298
 Mask 15, Metal Trench 3

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 299

 Alignment and Exposure
SOD

SOD
Copper 2 SOD
SOD

Cu 1 Cu 1 SOD Cu 1 Cu 1
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 300
PEB, Development, and Inspection
SOD

SOD
Copper 2 SOD
SOD

Cu 1 Cu 1 SOD Cu 1 Cu 1
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 301
 Dielectric Etch
SOD

SOD
Copper 2 SOD
SOD

Cu 1 Cu 1 SOD Cu 1 Cu 1
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 302
 Strip Photoresist
SOD

SOD
Copper 2 SOD
SOD

Cu 1 Cu 1 SOD Cu 1 Cu 1
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 303
 Hydrogen Plasma Clean
SOD

SOD
Copper 2 SOD
SOD

Cu 1 Cu 1 SOD Cu 1 Cu 1
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 304
Cu, Ta, and TaN Deposition and CMP
Cu 3 SOD Cu 3

SOD
Copper 2 SOD
SOD

Cu 1 Cu 1 SOD Cu 1 Cu 1
SOD

W Tungsten PSG

STI n+ n+ USG p+ p+ USG

P-well N-well
Buried SiO2 P-wafer
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 305
SiC, SOD, SiC, SOD, and PE-TEOS

SOD

SOD

Cu 3 SOD Cu 3

SOD
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 306
 PR Coating, Alignment and
Exposure, PEB, and Development

SOD

SOD

Cu 3 SOD Cu 3

SOD
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 307
 Via 4 Etch

SOD

SOD

Cu 3 SOD Cu 3

SOD
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 308
 Strip Photoresist

SOD

SOD

Cu 3 SOD Cu 3

SOD
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 309
 PR Coating, Alignment and
Exposure, PEB, and Development

SOD

SOD

Cu 3 SOD Cu 3

SOD
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 310
 Etch Trench

SOD

SOD

Cu 3 SOD Cu 3

SOD
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 311
 Strip Photoresist

SOD

SOD

Cu 3 SOD Cu 3

SOD
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 312
 Hydrogen Plasma Clean

SOD

SOD

Cu 3 SOD Cu 3

SOD
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 313
Cu, Ta, and TaN Deposition and CMP

Copper 4
SOD

SOD

Cu 3 SOD Cu 3

SOD
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 314
SiC, SOD, SiC, SOD, and PE-TEOS

SOD

SOD

Copper 4
SOD

SOD

Cu 3 SOD Cu 3

SOD
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 315
PR Coating, A&E, PEB, and Develop

SOD

SOD

Copper 4
SOD

SOD

Cu 3 SOD Cu 3

SOD
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 316
 Etch Via5

SOD

SOD

Copper 4
SOD

SOD

Cu 3 SOD Cu 3

SOD
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 317
 Strip Photoresist

SOD

SOD

Copper 4
SOD

SOD

Cu 3 SOD Cu 3

SOD
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 318
PR Coating, A&E, PEB, and Develop

SOD

SOD

Copper 4
SOD

SOD

Cu 3 SOD Cu 3

SOD
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 319
 Dielectric Etch

SOD

SOD

Copper 4
SOD

SOD

Cu 3 SOD Cu 3

SOD
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 320
 Strip Photoresist

SOD

SOD

Copper 4
SOD

SOD

Cu 3 SOD Cu 3

SOD
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 321
 Hydrogen Plasma Clean

SOD

SOD

Copper 4
SOD

SOD

Cu 3 SOD Cu 3

SOD
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 322
Cu, Ta, and TaN Deposition and CMP
Copper 5 SOD

SOD

Copper 4
SOD

SOD

Cu 3 SOD Cu 3

SOD
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 323
 PECVD Passivation Layers:
Nitride, PSG, and Nitride

Nitride
PSG

Copper 5 SOD

SOD

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 324

PR Coating, A&E, PEB, and Develop

Nitride
PSG

Copper 5 SOD

SOD

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 325

 Etch Passivation Layers

Nitride
PSG

Copper 5 SOD

SOD

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 326

 Strip Photoresist

Nitride
PSG

Copper 5 SOD

SOD

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 327

 Polyamide Coating

Polyamide

Nitride
PSG

Copper 5 SOD

SOD

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 328

 Ship to Test and Package

Polyamide

Nitride
PSG

Copper 5 SOD

SOD

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 329

 Strip Polyamide

Nitride
PSG

Copper 5 SOD

SOD

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 330

 Argon Sputtering Etch

Nitride
PSG

Copper 5 SOD

SOD

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 331

 Cr, Cu, and Au Liner Coating

Nitride
PSG

Copper 5 SOD

SOD

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 332

 Lead-Tin Alloy Coating

Lead-tin alloy
Nitride
PSG

Copper 5 SOD

SOD

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 333

PR Coating, A&E, PEB, and Develop
Photoresist

Lead-tin alloy
Nitride
PSG

Copper 5 SOD

SOD

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 334

 Metal Etch
Photoresist

Lead-tin alloy
Nitride
PSG

Copper 5 SOD

SOD

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 335

 Strip Photoresist

Lead-tin alloy
Nitride
PSG

Copper 5 SOD

SOD

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 336

 Lead-Tin Alloy Reflow

Lead-tin alloy
Nitride
PSG

Copper 5 SOD

SOD

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 337

 Cr, Cu, and
Lead-tin alloy
Au liners
Nitride
PSG SiN seal
layer
Copper 5 SOD

SOD

Copper 4
SOD

SiC etch SOD

Ta/TaN
stop layers barrier layer
Cu 3 SOD Cu 3

SOD
Copper 2 SOD SiC seal layer
SOD
PE-TEOS cap
Cu 1 Cu 1 SOD Cu 1 Cu 1
CoSi2 SOD
SiC seal layer
W Tungsten PSG
Poly Si gate SiN barrier
Hong Xiao, Ph. D. n+ n+ USG p+
www2.austin.cc.tx.us/HongXiao/Book.htm
STI p+ USG 338
P-well N-well layer
Buried SiO 2 P-wafer
 Summary
• CMOS IC chips dominate semiconductor
industry
– Demands for digital electronics, such as
electronic watches, calculators, and personal
computers

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 339

 Summary
• In the 1980s
– 3 micron to sub-micron
– Multi-layer metallization
– Tungsten CVD, dielectric CVD and metal sputtering
– Sidewall spacer for LDD
– Plasma etch gradually replaced wet etch in all
patterning etch processes.
– Steppers became popular for alignment and exposure
while projection systems were widely used

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 340

 Summary
• In the 1990s,
– 0.8 micron to 0.18 micron
– Silicides used for the gate and local interconnection
– CMP widely used for tungsten polishing and dielectric
planarization
– RTP is widely used for anneal processes
– HDP sources are used for etch, CVD, sputtering clean,
and sputtering deposition
– O3-TEOS oxide CVD processes commonly used for
STI, PMD and IMD depositions.
– ECP is used for copper metallization process
Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 341