Scribd
Upload
40 views

DSP Da3

This document provides details for an M.Tech VLSI Design course offered during the Summer Special Semester of 2021-2022 at Vellore Institute of Technology. It includes the course code and name, as well as registration information for a student named Amit Verma enrolled in the course.

Uploaded by

AMIT VERMA
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
40 views

DSP Da3

This document provides details for an M.Tech VLSI Design course offered during the Summer Special Semester of 2021-2022 at Vellore Institute of Technology. It includes the course code and name, as well as registration information for a student named Amit Verma enrolled in the course.

Uploaded by

AMIT VERMA
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 6

Summer Special Semester 2021-2022

ECE5022- VLSI Digital Signal Processing

M.Tech VLSI Design

School of Electronics Engineering


Vellore Institute of Technology

Name: Amit Verma


Registration Number: 21MVD0142

Slot: C1 + C2 + TC1 + TC2


Que1. For the 8th order 4-stage pipelined lattice all-pole lattice filter, assume
that addition and multiplication require 1 and 2 u.t, respectively.
a.) Use retiming to minimize the critical path of the DFG,
b.) determine the minimum unfolding factor j such that the J-unfolded DFG
can be retimed so that the critical path if this unfolded and retimed DFG is
J𝑻∞ where 𝑻∞ is the iteration bound of the original DFG.

Solutions:
(a). The retimed DFG is shown as

The computation time for critical path for the retimed graph is 2 u.t.

(b) The iteration bound of the retimed graph is 1.75u.t.


Jmin = 4
The minimum unfolding factor J such that the J-unfolded DFG can be retimed
to achieve a critical path computation time equal to J X T∞, or a sample
period equal to T∞, is J=4. This can be verified by solving the retiming
problems for the original
DFG:
• For all edges
U e V in the DFG, r(U)-r(V) ≤ w(e);
• If D (U, V) ≥ c, then r (U) - r (V) ≤ W(U, V) - J , with increasing J until
coming to a solution (note that c = J x 7
2

Que2 a.) Apply the MCM iterative matching algorithm to the multiplier set of
problem having values a=54, b=45, c=43, d=21. For each iteration, find the
number of bit-wise matches among all constant pairs in the set. Determine the
number of shifts and additions required the algorithm. How many shifts and
additions are saved?

Sol. a = 54 = 110110
b = 45 = 101101
c = 43 = 101011
d = 21 = 010101

For a standard implementation, 12 shifters and 11 adders are needed.

By Inspection we see that the number of bit-wise matches between all the
constant are:

a, b→2; a, c→2; a, d→2;


b, c→3; b, d→2; d→1;
The match between b and c is selected. Table 1 below shows the set of
constant after this redundancy is removed.

Constant Unsigned
a 110110
Rem.b 000100
Rem. c 000010
d 010101
Red. of b, c 101001
Table.1
we select the match between a and d which has 2 bit-wise matches. Table 2
below shows the set of constants after the second iteration.
Constant Unsigned
Rem. a 100010
Rem. b 000100
Rem. c 000010
Rem.d 000001
Red. of b, c 101001
Red. of a, d 010100
Table.2
After this step, no more redundancy can be found. Now 8 shifters and 4 adders
are needed to implement the multiplications. 4 shifters and 7 adders are saved.

Que2 b.) Repeat above problem for the multiplier set a=93, b = 59, c = 55,
d=73?
Sol. a=93= 1011101
b = 59 = 111011
c = 55 = 110111
d = 73 = 1001001
First, let us repeat the binary representation of all the four constants in Table

Constant Unsigned
a 1011101
b 0111011
c 0110111
d 1001001
Table.3
The bit-wise matches between constants are:
a, b→3; a, c→3; a, d→3;
b, c→4; b, d→2; c, d→ 1;

Remove the redundancy of b and c, we have updated constant set as in Table3.

Updated Set of constants after 1st Iteration,

Constant Unsigned
a 1011101
Rem. b 0001000
Rem. c 0000100
d 1001001
Red. of bandc 0110011
Table.4
Then the largest match number is a and d→3, Removing this redundancy, the
constant will be updated as in table.4 and table.5

Constant Unsigned
Rem. a 0010100
Rem. b 0001000
Rem. c 0000100
Rem.d 0000000
Red. of bandc 0110011
Red. of a and d 1001001
Table.5

No more redundancy can be removed after this step. The hardware required to
implement these multiplications are 9 shifters and 6 adders. 5 shifters and 8
adders are saved.

You might also like