BCA: 3

BCA-S203: Computer Architecture & Assembly Language

Dr. Aditya Kumar Gupta
Associate Professor
 Unit – II
RISC and CISC Processors
In the Early 80’s computer designer recommended that the computer must use fewer instructions
with simple constructors so they can be executed faster This type of computer is known as Reduced
Instruction Set Computer or RISC. Before that Complex Instruction Set Computer was used
however the name CISC given after RICS was introduced. In fact, when programming was done
using assembly language, a need was felt to make instruction do more task because programming
in assembly was tedious and error pro due to which CISC architecture evolved but with upraise of
high level language dependency RISC architecture found better in order to reduce computing
overheads.

Reduced Set Instruction Set Architecture (RISC):

The main idea behind is to make hardware simpler by using an instruction set composed of a few
basic steps for loading, evaluating and storing operations just like a load command will load data,
store command will store the data. Reduce the cycles per instruction at the cost of the number of
instructions per program.

Complex Instruction Set Architecture (CISC):

The main idea is that a single instruction will do all loading, evaluating and storing operations just
like a multiplication command will do stuff like loading data, evaluating and storing it, hence it’s
complex. The CISC approach attempts to minimize the number of instructions per program but at
the cost of increase in number of cycles per instruction.

Example – Suppose we have to add two 8-bit number:

 CISC approach: There will be a single command or instruction for this like ADD which
will perform the task.

 RISC approach: Here programmer will write first load command to load data in registers
then it will use suitable operator and then it will store result in desired location.

So, add operation is divided into parts i.e. load, operate, store due to which RISC programs are
longer and require more memory to get stored but require less transistors due to less complex
command.

BCA-S203: Computer Architecture & Assembly Language

 Characteristic of RISC:

1. Simpler instruction, hence simple instruction decoding.

2. Instruction come under size of one word.
3. Instruction take single clock cycle to get executed.
4. More number of general purpose register.
5. Simple Addressing Modes.
6. Less Data types.
7. Pipeling can be achieved.

Characteristic of CISC:

1. Complex instruction, hence complex instruction decoding.

2. Instruction are larger than one-word size.
3. Instruction may take more than single clock cycle to get executed.
4. Less number of general purpose register as operation get performed in memory itself.
5. Complex Addressing Modes.
6. More Data types.

Difference Between CISC and RISC

Architectural Reduced Instruction Set

Complex Instruction Set Computer(CISC)
Characteristics Computer(RISC)
Instruction size and Large set of instructions with variable formats Small set of instructions with
format (16-64 bits per instruction). fixed format (32 bit).
Data transfer Memory to memory. Register to register.

Most micro coded using control memory Mostly hardwired without

CPU control
(ROM) but modern CISC use hardwired control. control memory.

Instruction type Not register based instructions. Register based instructions.

Memory access More memory access. Less memory access.
Clocks Includes multi-clocks. Includes single clock.
Instructions are reduced and
Instruction nature Instructions are complex.
simple.

BCA-S203: Computer Architecture & Assembly Language

Vector Processing

A vector processor is a central processing unit that can work on an entire vector in one instruction.
The instruction to the processor is in the form of one complete vector instead of its element. Vector
processors are used because they reduce the draw and interpret bandwidth owing to the fact that
fewer instructions must be fetched.

Vector processing means Processing of sequences of data in a uniform manner, a common

occurrence in manipulation of matrices (whose elements are vectors) or other arrays of data. A
vector processor will process sequences of input data as a result of obeying a single vector
instruction and generate a result data sequence. This orderly progression of data can capitalize on
the use of pipeline processing. According to from where the operands are retrieved in a vector
processor, pipe lined vector computers are classified into two architectural configurations:

Memory to Memory Architecture

In memory to memory architecture, source operands, intermediate and final results are retrieved
(read) directly from the main memory. For memory to memory vector instructions, the information
of the base address, the offset, the increment, and the vector length must be specified in order to
enable streams of data transfers between the main memory and pipelines. The processors like TI-
ASC, CDC STAR-100, and Cyber-205 have vector instructions in memory to memory formats. The
main points about memory to memory architecture are:

 There is no limitation of size

 Speed is comparatively slow in this architecture

Register to Register Architecture

In register to register architecture, operands and results are retrieved indirectly from the main
memory through the use of large number of vector registers or scalar registers. The processors
like Cray-1 and the Fujitsu VP-200 use vector instructions in register to register formats. The main
points about register to register architecture are:

 Register to register architecture has limited size.

 Speed is very high as compared to the memory to memory architecture.
 The hardware cost is high in this architecture.

A block diagram of a modern multiple pipeline vector computer is shown below:

BCA-S203: Computer Architecture & Assembly Language

 Figure: Typical pipelined vector processor

Applications of Vector Processors

Computer with vector processing capabilities are in demand in specialized applications. The
following are some areas where vector processing is used:

1. Petroleum exploration.
2. Medical diagnosis.
3. Data analysis.
4. Weather forecasting.
5. Aerodynamics and space flight simulations.
6. Image processing.
7. Artificial intelligence.

BCA-S203: Computer Architecture & Assembly Language

Array Processors

An array processor is a processor that performs computational on large arrays of data. It is a

computer/processor that has an architecture especially designed for processing arrays (e.g.
matrices) of numbers. The architecture includes a number of processors (say 64 by 64) working
simultaneously, each handling one element of the array, so that a single operation can apply to all
elements of the array in parallel. To obtain the same effect in a conventional processor, the
operation must be applied to each element of the array sequentially, and so consequently much
more slowly.

An array processor may be built as a self-contained unit attached to a main computer via an I/O
port or internal bus; alternatively, it may be a distributed array processor where the processing
elements are distributed throughout, and closely linked to, a section of the computer's memory.
Array processors are very powerful tools for handling problems with a high degree of parallelism.
They do however demand a modified approach to programming. The conversion of conventional
(sequential) programs to serve array processors is not a trivial task, and it is sometimes necessary
to select different (parallel) algorithms to suit the parallel approach.

Array processors are also known as multiprocessors or vector processors. They perform
computations on large arrays of data. Thus, they are used to improve the performance of the
computer.

Types of Array Processors

There are basically two types of array processors:

1. Attached Array Processors

2. SIMD Array Processors

Attached Array Processors

An attached array processor is a processor which is attached to a general purpose computer and its
purpose is to enhance and improve the performance of that computer in numerical computational
tasks. The purpose of the attached array processor is to enhance the performance of the computer
by providing vector processing for complex scientific operations. It achieves high performance by
means of parallel processing with multiple functional units. The array processor can be programed
by the user to accommodate variety of complex arithmetic operations. Following figure shows the
interconnection of an attached array processor to a host computer.

BCA-S203: Computer Architecture & Assembly Language

 Figure: Attached array processor with host computer

SIMD Array Processors

SIMD is the organization of a single computer containing multiple processors operating in parallel.
The processing units are made to operate under the control of a common control unit, thus
providing a single instruction stream and multiple data streams.
A general block diagram of an array processor is shown below. It contains a set of identical
processing elements (PE's), each of which is having a local memory M. Each processor element
includes an ALU and registers. The master control unit controls all the operations of the processor
elements. It also decodes the instructions and determines how the instruction is to be executed.
The main memory is used for storing the program. The control unit is responsible for fetching the
instructions. Vector instructions are send to all PE's simultaneously and results are returned to the
memory.
The best known SIMD array processor is the ILLIAC IV computer developed by the Burroughs
corps. SIMD processors are highly specialized computers. They are only suitable for numerical
problems that can be expressed in vector or matrix form and they are not suitable for other types
of computations.

BCA-S203: Computer Architecture & Assembly Language

 Figure: SIMD Array Processor organization

Advantages of using Array Processor

 Array processors increases the overall instruction processing speed.
 As most of the Array processors operates asynchronously from the host CPU, hence it
improves the overall capacity of the system.
 Array Processors has its own local memory, hence providing extra memory for systems
with low memory.

References: Mano, M. Morris. 1984. Digital Design. Pearson

BCA-S203: Computer Architecture & Assembly Language