SAFETY PRECAUTIONS

(Always read these cautions before using the product)

Before using this product, please read this manual and the related manuals introduced in this manual,
and pay full attention to safety to handle the product correctly.

Please store this manual in a safe place and make it accessible when required. Always forward a copy of
the manual to the end user.

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 CONDITIONS OF USE FOR THE PRODUCT
(1) Mitsubishi programmable controller ("the PRODUCT") shall be used in conditions;
i) where any problem, fault or failure occurring in the PRODUCT, if any, shall not lead to any
major or serious accident; and
ii) where the backup and fail-safe function are systematically or automatically provided
outside of the PRODUCT for the case of any problem, fault or failure occurring in the
PRODUCT.

(2) The PRODUCT has been designed and manufactured for the purpose of being used in
general industries.
MITSUBISHI SHALL HAVE NO RESPONSIBILITY OR LIABILITY (INCLUDING, BUT NOT
LIMITED TO ANY AND ALL RESPONSIBILITY OR LIABILITY BASED ON CONTRACT,
WARRANTY, TORT, PRODUCT LIABILITY) FOR ANY INJURY OR DEATH TO PERSONS OR
LOSS OR DAMAGE TO PROPERTY CAUSED BY the PRODUCT THAT ARE OPERATED OR
USED IN APPLICATION NOT INTENDED OR EXCLUDED BY INSTRUCTIONS, PRECAUTIONS,
OR WARNING CONTAINED IN MITSUBISHI'S USER, INSTRUCTION AND/OR SAFETY
MANUALS, TECHNICAL BULLETINS AND GUIDELINES FOR the PRODUCT.
("Prohibited Application")
Prohibited Applications include, but not limited to, the use of the PRODUCT in;
• Nuclear Power Plants and any other power plants operated by Power companies, and/or
any other cases in which the public could be affected if any problem or fault occurs in the
PRODUCT.
• Railway companies or Public service purposes, and/or any other cases in which
establishment of a special quality assurance system is required by the Purchaser or End
User.
• Aircraft or Aerospace, Medical applications, Train equipment, transport equipment such
as Elevator and Escalator, Incineration and Fuel devices, Vehicles, Manned transportation,
Equipment for Recreation and Amusement, and Safety devices, handling of Nuclear or
Hazardous Materials or Chemicals, Mining and Drilling, and/or other applications where
there is a significant risk of injury to the public or property.

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REVISIONS
*The manual number is given on the bottom left of the back cover.

Print Date *Manual Number Revision

Dec., 2008 SH (NA)-080809ENG-A First edition

Mar., 2009 SH (NA)-080809ENG-B Partial corrections

Section 3.3, 3.8, 5.1.3, 6.1.7, 6.2.14, 7.3.3, 7.11.18, 7.11.19, 7.12.1.5,12.7, 7.12.11, 7.12.25,
7.12.26, 7.13.4, 7.13.5, 7.15.7, 7.15.8

Jul., 2009 SH (NA)-080809ENG-C Revision because of function support by the Universal model QCPU having a
serial number "11043" or later
Partial corrections
Section 2.1, 2.5.6, 2.5.18, 2.5.20, 7.6.9, 7.12.7, 7.12.11, 12.1.3, 12.1.4, APPENDIX 1.2, 1.3, 1.4.2,
3, 5.1
Additions
Section 2.5.16, 7.16, 7.18.10
Modification
Section 2.5.21 2.5.22, Section 2.5.22 2.5.21, Section 9.13 7.6.10,
Section 9.14 7.6.1, Section 9.15 7.16, Section 9.15.1 7.16.1, Section 9.15.2 7.16.2,
Section 9.15.3 7.16.3, Section 9.1 7.18.9, Section 9.2 7.18.11, Section 9.3 7.18.12,
Section 9.4 7.18.13, Section 9.5 7.18.14, Section 9.6 7.18.15, Section 9.7 7.18.16,
Section 9.8 7.18.17, Section 9.9 7.18.18, Section 9.10 7.18.19, Section 9.11 9.1,
Section 9.11.1 9.1.1, Section 9.11.2 9.1.2, Section 9.12 9.2, Section 9.12.1 9.2.1,
Chapter 10 11, Chapter 11 10

Jan., 2010 SH (NA)-080809ENG-D Model Additions

L02CPU, L26CPU-BT
Partial corrections
SAFETY PRECAUTIONS, INTRODUCTION, MANUALS, Chapter 1, Section 2.3.2, 2.4.1, 2.4.2,
2.4.3, 2.4.4, 2.5.1, 2.5.6, 2.5.18, 3.2.4, 3.3, 3.4, 3.5.1, 3.5.2, 3.6, 3.8, 3.10, Chapter 4, 5, 6, 7, 8, 9,
10, 11, 12, APPENDIX 1.1, 2.1, 3, 4, INDEX, Warranty
Additions
CONDITIONS OF USE FOR THE PRODUCT, Section 2.6.1, 2.6.2, 2.7.1, 2.7.2, 2.8.1, 2.9.1,
7.18.20, 7.18.21, APPENDIX 1.5
Modification
Section 2.5.19 2.6, Section 2.5.20 2.7, Section 2.5.21 2.8, Section 2.5.22 2.9

Japanese Manual Version SH-080804-D

This manual confers no industrial property rights or any rights of any other kind, nor does it confer any patent licenses.
Mitsubishi Electric Corporation cannot be held responsible for any problems involving industrial property rights which may
occur as a result of using the contents noted in this manual.
© 2008 MITSUBISHI ELECTRIC CORPORATION

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 INTRODUCTION
This document is the MELSEC-Q/L Programming Manual (Common Instructions). It describes the common
instructions required for programming of the QCPU and LCPU.

• "Common instructions" are all instructions except for dedicated instructions for such intelligent function
modules as QJ71C24N and QJ71E71-100; PID control instructions; SFC instructions; ST instructions;
instructions for socket communication features; trigger logging instructions; and dedicated instructions for
LPCU positioning/counter functionality.

Please read this manual and other relevant manuals carefully before using this product. Please familiarize
yourself with the functions and performance of the Q series and L series sequencers in order to handle this
product correctly.

■ Relevant CPU module

CPU module Model
Basic model QCPU Q00JCPU, Q00CPU, Q01CPU
High Perfomance model QCPU Q02CPU, Q02HCPU, Q06HCPU, Q12HCPU, Q25HCPU
Process CPU Q02PHCPU, Q06PHCPU, Q12PHCPU, Q25PHCPU
Redundant CPU Q12PRHCPU, Q25PRHCPU
Q00UJCPU, Q00UCPU, Q01UCPU, Q02UCPU, Q03UDCPU,
Q04UDHCPU, Q06UDHCPU, Q10UDHCPU, Q13UDHCPU,
Universal model QCPU Q20UDHCPU, Q26UDHCPU, Q03UDECPU, Q04UDEHCPU,
Q06UDEHCPU, Q10UDEHCPU, Q13UDEHCPU,
Q20UDEHCPU
LCPU L02CPU, L26CPU-BT

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MEMO

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 CONTENTS
SAFETY PRECAUTIONS ..................................................................................................................A - 1
CONDITIONS OF USE FOR THE PRODUCT ..................................................................................A - 2
REVISIONS .......................................................................................................................................A - 3
INTRODUCTION ...............................................................................................................................A - 4
CONTENTS .......................................................................................................................................A - 6
MANUALS........................................................................................................................................A - 17

Common Instructions 1/2

1. GENERAL DESCRIPTION 1 - 1 to 1 - 8
1.1 Related Programming Manuals 1-2
1.2 Abbreviations and Generic Names 1-5

2. INSTRUCTION TABLES 2 - 1 to 2 - 62
2.1 Types of Instructions 2-2
2.2 How to Read Instruction Tables 2-4
2.3 Sequence Instructions 2-6
2.3.1 Contact instructions ...................................................................................................... 2 - 6
2.3.2 Association instructions ................................................................................................ 2 - 7
2.3.3 Output instructions........................................................................................................ 2 - 8
2.3.4 Shift instructions ........................................................................................................... 2 - 8
2.3.5 Master control instructions............................................................................................ 2 - 9
2.3.6 Termination instructions ............................................................................................... 2 - 9
2.3.7 Other instructions ......................................................................................................... 2 - 9
2.4 Basic instructions 2 - 10
2.4.1 Comparison operation instructions ............................................................................. 2 - 10
2.4.2 Arithmetic operation instructions ................................................................................ 2 - 16
2.4.3 Data conversion instructions ...................................................................................... 2 - 22
2.4.4 Data transfer instructions............................................................................................ 2 - 24
2.4.5 Program branch instructions....................................................................................... 2 - 27
2.4.6 Program execution control instructions ...................................................................... 2 - 27
2.4.7 I/O refresh instructions ............................................................................................... 2 - 27
2.4.8 Other convenient instructions ..................................................................................... 2 - 28
2.5 Application Instructions 2 - 29
2.5.1 Logical operation instructions ..................................................................................... 2 - 29
2.5.2 Rotation instructions ................................................................................................... 2 - 32
2.5.3 Shift instructions ......................................................................................................... 2 - 33
2.5.4 Bit processing instructions.......................................................................................... 2 - 34
2.5.5 Data processing instructions ...................................................................................... 2 - 35
2.5.6 Structure creation instructions .................................................................................... 2 - 38
2.5.7 Data table operation instructions ................................................................................ 2 - 40
2.5.8 Buffer memory access instructions............................................................................. 2 - 41
2.5.9 Display instructions..................................................................................................... 2 - 41
2.5.10 Debugging and failure diagnosis instructions ............................................................. 2 - 42

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 2.5.11 Character string processing instructions .................................................................... 2 - 43
2.5.12 Special function instructions ....................................................................................... 2 - 46
2.5.13 Data control instructions ............................................................................................. 2 - 49
2.5.14 Switching instructions ................................................................................................. 2 - 51
2.5.15 Clock instructions ....................................................................................................... 2 - 52
2.5.16 Expansion clock instruction ........................................................................................ 2 - 55
2.5.17 Program control instructions....................................................................................... 2 - 56
2.5.18 Other instructions ....................................................................................................... 2 - 57
2.6 Instructions for Data Link 2 - 59
2.6.1 Instructions for Network refresh.................................................................................. 2 - 59
2.6.2 Instructions for Reading/Writing Routing Information ................................................. 2 - 59
2.7 Multiple CPU dedicated instruction 2 - 60
2.7.1 Instructions for Writing to the CPU Shared Memory of Host CPU.............................. 2 - 60
2.7.2 Instructions for Reading from the CPU Shared Memory of Another CPU .................. 2 - 60
2.8 Multiple CPU high-speed transmission dedicated instruction 2 - 61
2.8.1 Instructions for Multiple CPU high-speed transmission dedicated ............................. 2 - 61
2.9 Redundant system instructions (For Redundant CPU) 2 - 62
2.9.1 Instructions for Redundant system (For Redundant CPU) ......................................... 2 - 62

3. CONFIGURATION OF INSTRUCTIONS 3 - 1 to 3 - 48
3.1 Configuration of Instructions 3-2
3.2 Designating Data 3-3
3.2.1 Using bit data................................................................................................................ 3 - 3
3.2.2 Using word (16 bits) data.............................................................................................. 3 - 4
3.2.3 Using double word data (32 bits).................................................................................. 3 - 6
3.2.4 Using real number data ................................................................................................ 3 - 8
3.2.5 Using character string data......................................................................................... 3 - 11
3.3 Indexing 3 - 12
3.4 Indirect Specification 3 - 23
3.5 Reducing Instruction Processing Time 3 - 25
3.5.1 Subset Processing...................................................................................................... 3 - 25
3.5.2 Operation processing with standard device registers (Z) (Universal model QCPU and
LCPU only) ................................................................................................................. 3 - 26
3.6 Cautions on Programming (Operation Errors) 3 - 27
3.7 Conditions for Execution of Instructions 3 - 33
3.8 Counting Step Number 3 - 34
3.9 Operation when the OUT, SET/RST, or PLS/PLF Instructions Use the Same Device 3 - 40
3.10 Precautions for Use of File Registers 3 - 45

4. HOW TO READ INSTRUCTIONS 4 - 1 to 4 - 4

5. SEQUENCE INSTRUCTIONS 5 - 1 to 5 - 60
5.1 Contact Instructions 5-2
5.1.1 Operation start, series connection, parallel connection (LD,LDI,AND,ANI,OR,ORI).... 5 - 2

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 5.1.2 Pulse operation start, pulse series connection, pulse parallel connection
(LDP,LDF,ANDP,ANDF,ORP,ORF) ............................................................................. 5 - 5
5.1.3 Pulse NOT operation start, pulse NOT series connection, pulse NOT parallel connection
(LDPI,LDFI,ANDPI,ANDFI,ORPI,ORFI) ....................................................................... 5 - 7
5.2 Association Instructions 5 - 10
5.2.1 Ladder block series connection and parallel connection (ANB,ORB) ........................ 5 - 10
5.2.2 Operation results push,read,pop (MPS,MRD,MPP) ................................................... 5 - 12
5.2.3 Operation results inversion (INV) ............................................................................... 5 - 15
5.2.4 Operation result conversions (MEP,MEF) .................................................................. 5 - 17
5.2.5 Pulse conversions of edge relay operation results (EGP,EGF).................................. 5 - 18
5.3 Output Instructions 5 - 20
5.3.1 Out instruction (excluding timers, counters, and annunciators) (OUT)....................... 5 - 20
5.3.2 Timers (OUT T,OUTH T) ............................................................................................ 5 - 22
5.3.3 Counter (OUT C) ........................................................................................................ 5 - 26
5.3.4 Annunciator output (OUT F) ....................................................................................... 5 - 28
5.3.5 Setting devices (except for annunciators) (SET) ........................................................ 5 - 30
5.3.6 Resetting devices (except for annunciators) (RST).................................................... 5 - 32
5.3.7 Setting and resetting the annunciators (SET F,RST F) .............................................. 5 - 35
5.3.8 Leading edge and trailing edge outputs (PLS,PLF).................................................... 5 - 37
5.3.9 Bit device output reverse (FF) .................................................................................... 5 - 40
5.3.10 Pulse conversions of direct outputs (DELTA(P)) ........................................................ 5 - 42
5.4 Shift Instructions 5 - 44
5.4.1 Bit device shifts (SFT(P))............................................................................................ 5 - 44
5.5 Master Control Instructions 5 - 47
5.5.1 Setting and resetting the master control (MC,MCR)................................................... 5 - 47
5.6 Termination Instructions 5 - 51
5.6.1 End main routine program (FEND)............................................................................. 5 - 51
5.6.2 End sequence program (END) ................................................................................... 5 - 53
5.7 Other instructions 5 - 55
5.7.1 Sequence program stop (STOP) ................................................................................ 5 - 55
5.7.2 No operations (NOP,NOPLF,PAGE n) ....................................................................... 5 - 57

6. BASIC INSTRUCTIONS 6 - 1 to 6 - 172

6.1 Comparison Operation Instructions 6-2
6.1.1 BIN 16-bit data comparisons (=,<>,>,<=,<,>=) ............................................................. 6 - 2
6.1.2 BIN 32-bit data comparisons (D=,D<>,D>,D<=,D<,D>=) ............................................. 6 - 4
6.1.3 Floating decimal point data comparisons (Single precision)
(E=,E<>,E>,E<=,E<,E>=) ............................................................................................. 6 - 6
6.1.4 Floating decimal point data comparisons (Double precision)
(ED=,ED<>,ED>,ED<=,ED<,ED>=) ............................................................................. 6 - 8
6.1.5 Character string data comparisons ($=,$<>,$>,$<=,$<,$>=) ..................................... 6 - 11
6.1.6 BIN block data comparisons (BKCMP … ,BKCMP … P) ............................................ 6 - 15
6.1.7 BIN 32-bit block data comparisons (DBKCMP … ,DBKCMP … P) ............................ 6 - 18
6.2 Arithmetic Operation Instructions 6 - 22
6.2.1 BIN 16-bit addition and subtraction operations (+(P),-(P)) ......................................... 6 - 22
6.2.2 BIN 32-bit addition and subtraction operations (D+(P),D-(P)) .................................... 6 - 26

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 6.2.3 BIN 16-bit multiplication and division operations (*(P),/(P))........................................ 6 - 30
6.2.4 BIN 32-bit multiplication and division operations (D*(P),D/(P)) .................................. 6 - 32
6.2.5 BCD 4-digit addition and subtraction operations (B+(P),B-(P)) .................................. 6 - 34
6.2.6 BCD 8-digit addition and subtraction operations (DB+(P),DB-(P)) ............................. 6 - 38
6.2.7 BCD 4-digit multiplication and division operations (B*(P),B/(P)) ................................ 6 - 42
6.2.8 BCD 8-digit multiplication and division operations (DB*(P),DB/(P)) ........................... 6 - 44
6.2.9 Addition and subtraction of floating decimal point data
(Single precision) (E+(P),E-(P)).................................................................................. 6 - 46
6.2.10 Addition and subtraction of floating decimal point data
(Double precision) (ED+(P),ED-(P)) ........................................................................... 6 - 50
6.2.11 Multiplication and division of floating decimal point data
(Single precision) (E*(P),E/(P))................................................................................... 6 - 54
6.2.12 Multiplication and division of floating decimal point data
(Double precision) (ED*(P),ED/(P)) ............................................................................ 6 - 56
6.2.13 Block addition and subtraction (BK+(P),BK-(P))......................................................... 6 - 59
6.2.14 BIN 32-bit data block addition and subtraction operations (DBK+(P),DBK-(P)) ........ 6 - 62
6.2.15 Linking character strings ($+(P)) ................................................................................ 6 - 66
6.2.16 Incrementing and decrementing 16-bit BIN data (INC(P),DEC(P)) ............................ 6 - 70
6.2.17 Incrementing and decrementing 32-bit BIN data (DINC(P),DDEC(P)) ....................... 6 - 72
6.3 Data conversion instructions 6 - 74
6.3.1 Conversion from BIN data to 4-digit and 8-digit BCD (BCD(P),DBCD(P)) ................. 6 - 74
6.3.2 Conversion from BCD 4-digit and 8-digit data to BIN data (BIN(P),DBIN(P)) ............ 6 - 76
6.3.3 Conversion from BIN 16 and 32-bit data to floating decimal point (Single precision)
(FLT(P),DFLT(P)) ....................................................................................................... 6 - 79
6.3.4 Conversion from BIN 16 and 32-bit data to floating decimal point (Double precision)
(FLTD(P),DFLTD(P)) .................................................................................................. 6 - 82
6.3.5 Conversion from floating decimal point data to BIN16- and 32-bit data (Single precision)
(INT(P),DINT(P)) ........................................................................................................ 6 - 84
6.3.6 Conversion from floating decimal point data to BIN16- and 32-bit data (Double precision)
(INTD(P),DINTD(P)) ................................................................................................... 6 - 87
6.3.7 Conversion from BIN 16-bit to BIN 32-bit data (DBL(P)) ............................................ 6 - 89
6.3.8 Conversion from BIN 32-bit to BIN 16-bit data (WORD(P))........................................ 6 - 90
6.3.9 Conversion from BIN 16 and 32-bit data to Gray code (GRY(P),DGRY(P)) .............. 6 - 91
6.3.10 Conversion of Gray code to BIN 16 and 32-bit data (GBIN(P),DGBIN(P))................. 6 - 93
6.3.11 Complement of 2 of BIN 16- and 32-bit data (sign reversal) (NEG(P),DNEG(P)) ...... 6 - 95
6.3.12 Floating-point sign invertion (Single precision) (ENEG(P)) ........................................ 6 - 97
6.3.13 Floating-point sign invertion (Double precision) (EDNEG(P)) .................................... 6 - 98
6.3.14 Conversion from block BIN 16-bit data to BCD 4-digit data (BKBCD(P))................... 6 - 99
6.3.15 Conversion from block BCD 4-digit data to block BIN 16-bit data (BKBIN(P)) ......... 6 - 101
6.3.16 Single precision to Double precision conversion (ECON(P)) ................................... 6 - 103
6.3.17 Double precision to Single precision conversion (EDCON(P))................................. 6 - 105
6.4 Data Transfer Instructions 6 - 107
6.4.1 16-bit and 32-bit data transfers (MOV(P),DMOV(P))................................................ 6 - 107
6.4.2 Floating-point data transfer (Single precision) (EMOV(P)) ....................................... 6 - 109
6.4.3 Floating-point data transfer (Double precision) (EDMOV(P)) ................................... 6 - 111
6.4.4 Character string transfers ($MOV(P))....................................................................... 6 - 113
6.4.5 16-bit and 32-bit negation transfers (CML(P),DCML(P)) .......................................... 6 - 115
6.4.6 Block 16-bit data transfers (BMOV(P)) ..................................................................... 6 - 118
6.4.7 Identical 16-bit data block transfers (FMOV(P)) ....................................................... 6 - 122

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 6.4.8 Identical 32-bit data block transfers (DFMOV(P))..................................................... 6 - 125
6.4.9 16-bit and 32-bit data exchanges (XCH(P),DXCH(P)) ............................................. 6 - 127
6.4.10 Block 16-bit data exchanges (BXCH(P)) .................................................................. 6 - 129
6.4.11 Upper and lower byte exchanges (SWAP(P)) .......................................................... 6 - 131
6.5 Program Branch Instructions 6 - 132
6.5.1 Pointer branch instructions (CJ,SCJ,JMP) ............................................................... 6 - 132
6.5.2 Jump to END (GOEND)............................................................................................ 6 - 135
6.6 Program Execution Control Instructions 6 - 136
6.6.1 Interrupt disable/enable instructions, interrupt program mask (DI,EI,IMASK) .......... 6 - 136
6.6.2 Recovery from interrupt programs (IRET) ................................................................ 6 - 143
6.7 I/O Refresh Instructions 6 - 145
6.7.1 I/O refresh (RFS(P)) ................................................................................................. 6 - 145
6.8 Other Convenient Instructions 6 - 147
6.8.1 Counter 1-phase input up or down (UDCNT1) ......................................................... 6 - 147
6.8.2 Counter 2-phase input up or down (UDCNT2) ......................................................... 6 - 150
6.8.3 Teaching timer (TTMR) ............................................................................................ 6 - 153
6.8.4 Special function timer (STMR).................................................................................. 6 - 155
6.8.5 Rotary table shortest direction control (ROTC) ........................................................ 6 - 158
6.8.6 Ramp signal (RAMP)................................................................................................ 6 - 161
6.8.7 Pulse density measurement (SPD) .......................................................................... 6 - 164
6.8.8 Fixed cycle pulse output (PLSY) .............................................................................. 6 - 166
6.8.9 Pulse width modulation (PWM) ................................................................................ 6 - 168
6.8.10 Matrix input (MTR).................................................................................................... 6 - 170

7. APPLICATION INSTRUCTIONS 7 - 1 to 7 - 460

7.1 Logical operation instructions 7-2
7.1.1 Logical products with 16-bit and 32-bit data (WAND(P),DAND(P)).............................. 7 - 3
7.1.2 Block logical products (BKAND(P)) .............................................................................. 7 - 9
7.1.3 Logical sums of 16-bit and 32-bit data (WOR(P),DOR(P))......................................... 7 - 11
7.1.4 Block logical sum operations (BKOR(P)).................................................................... 7 - 17
7.1.5 16-bit and 32-bit exclusive OR operations (WXOR(P),DXOR(P)) .............................. 7 - 19
7.1.6 Block exclusive OR operations (BKXOR(P)) .............................................................. 7 - 25
7.1.7 16-bit and 32-bit data exclusive NOR operations (WXNR(P),DXNR(P)).................... 7 - 27
7.1.8 Block exclusive NOR operations (BKXNR(P))............................................................ 7 - 33
7.2 Rotation instruction 7 - 35
7.2.1 Right rotation of 16-bit data (ROR(P),RCR(P)) .......................................................... 7 - 35
7.2.2 Left rotation of 16-bit data (ROL(P),RCL(P)) .............................................................. 7 - 38
7.2.3 Right rotation of 32-bit data (DROR(P),DRCR(P)) ..................................................... 7 - 41
7.2.4 Left rotation of 32-bit data (DROL(P),DRCL(P))......................................................... 7 - 44
7.3 Shift instruction 7 - 46
7.3.1 n-bit shift to right or left of 16-bit data (SFR(P),SFL(P)) ............................................. 7 - 46
7.3.2 1-bit shift to right or left of n-bit data (BSFR(P),BSFL(P)) .......................................... 7 - 49
7.3.3 n-bit shift to right or left of n-bit data (SFTBR(P),SFTBL(P)) ...................................... 7 - 51
7.3.4 1-word shift to right or left of n-word data (DSFR(P),DSFL(P)) .................................. 7 - 54
7.3.5 n-bit shift to right or left of n-word data (SFTWR(P),SFTWL(P)) ................................ 7 - 56
7.4 Bit processing instructions 7 - 59

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 7.4.1 Bit set and reset for word devices (BSET(P),BRST(P)) ............................................. 7 - 59
7.4.2 Bit tests (TEST(P),DTEST(P)).................................................................................... 7 - 61
7.4.3 Batch reset of bit devices (BKRST(P)) ....................................................................... 7 - 64
7.5 Data processing instructions 7 - 66
7.5.1 16-bit and 32-bit data searches (SER(P),DSER(P))................................................... 7 - 66
7.5.2 16-bit and 32-bit data checks (SUM(P),DSUM(P))..................................................... 7 - 69
7.5.3 Decoding from 8 to 256 bits (DECO(P)) ..................................................................... 7 - 71
7.5.4 Encoding from 256 to 8 bits (ENCO(P)) ..................................................................... 7 - 73
7.5.5 7-segment decode (SEG(P)) ...................................................................................... 7 - 75
7.5.6 4-bit dissociation of 16-bit data (DIS(P))..................................................................... 7 - 77
7.5.7 4-bit linking of 16-bit data (UNI(P)) ............................................................................. 7 - 79
7.5.8 Dissociation or linking of random data (NDIS(P),NUNI(P)) ........................................ 7 - 81
7.5.9 Data dissociation and linking in byte units (WTOB(P),BTOW(P)) .............................. 7 - 85
7.5.10 Maximum value search for 16- and 32-bit data (MAX(P),DMAX(P)) .......................... 7 - 89
7.5.11 Minimum value search for 16- and 32-bit data (MIN(P),DMIN(P)) ............................. 7 - 92
7.5.12 BIN 16 and 32 bits data sort operations (SORT,DSORT) .......................................... 7 - 95
7.5.13 Calculation of totals for 16-bit data (WSUM(P)) ......................................................... 7 - 99
7.5.14 Calculation of totals for 32-bit data (DWSUM(P))..................................................... 7 - 101
7.5.15 Calculation of averages for 16-bit or 32-bit data (MEAN(P),DMEAN(P)) ................. 7 - 103
7.6 Structure creation instructions 7 - 105
7.6.1 FOR to NEXT instruction loop (FOR,NEXT)............................................................. 7 - 105
7.6.2 Forced end of FOR to NEXT instruction loop (BREAK(P))....................................... 7 - 108
7.6.3 Subroutine program calls (CALL(P)) ........................................................................ 7 - 110
7.6.4 Return from subroutine programs (RET) .................................................................. 7 - 115
7.6.5 Subroutine program output OFF calls (FCALL(P)) ................................................... 7 - 116
7.6.6 Subroutine calls between program files (ECALL(P)) ................................................ 7 - 120
7.6.7 Subroutine output OFF calls between program files (EFCALL(P))........................... 7 - 125
7.6.8 Subroutine program call (XCALL)............................................................................. 7 - 129
7.6.9 Refresh instruction (COM)........................................................................................ 7 - 134
7.6.10 Select Refresh Instruction (COM)............................................................................. 7 - 137
7.6.11 Select Refresh Instruction (CCOM(P)) ..................................................................... 7 - 142
7.6.12 Index modification of entire ladder (IX,IXEND)......................................................... 7 - 143
7.6.13 Designation of modification values in index modification of entire ladders
(IXDEV,IXSET) ......................................................................................................... 7 - 147
7.7 Data Table Operation Instructions 7 - 150
7.7.1 Writing data to the data table (FIFW(P))................................................................... 7 - 150
7.7.2 Reading oldest data from tables (FIFR(P))............................................................... 7 - 152
7.7.3 Reading newest data from data tables (FPOP(P)) ................................................... 7 - 154
7.7.4 Deleting and inserting data from and in data tables (FDEL(P),FINS(P)).................. 7 - 156
7.8 Buffer memory access instruction 7 - 159
7.8.1 Reading 1-/2-word data from the intelligent function module
(FROM(P),DFRO(P))................................................................................................ 7 - 159
7.8.2 Writing 1-/2-word data to intelligent function module (TO(P),DTO(P)) ..................... 7 - 162
7.9 Display instructions 7 - 165
7.9.1 Print ASCII code instruction (PR) ............................................................................. 7 - 165
7.9.2 Print comment instruction (PRC) .............................................................................. 7 - 168
7.9.3 Error display and annunciator reset instruction (LEDR) ........................................... 7 - 171

A-11
 7.10 Debugging and failure diagnosis instructions 7 - 174
7.10.1 Special format failure checks (CHKST,CHK) ........................................................... 7 - 174
7.10.2 Changing check format of CHK instruction (CHKCIR,CHKEND) ............................. 7 - 178
7.11 Character string processing instructions 7 - 182
7.11.1 Conversion from BIN 16-bit or 32-bit to decimal ASCII (BINDA(P),DBINDA(P))...... 7 - 182
7.11.2 Conversion from BIN 16-bit or 32-bit data to hexadecimal ASCII
(BINHA(P),DBINHA(P)) ............................................................................................ 7 - 185
7.11.3 Conversion from BCD 4-digit and 8-digit to decimal ASCII data
(BCDDA(P),DBCDDA(P))......................................................................................... 7 - 188
7.11.4 Conversion from decimal ASCII to BIN 16-bit and 32-bit data
(DABIN(P),DDABIN(P)) ............................................................................................ 7 - 191
7.11.5 Conversion from hexadecimal ASCII to BIN 16-bit and 32-bit data
(HABIN(P),DHABIN(P)) ............................................................................................ 7 - 194
7.11.6 Conversion from decimal ASCII to BCD 4-digit or 8-digit data
(DABCD(P),DDABCD(P))......................................................................................... 7 - 197
7.11.7 Reading device comment data (COMRD(P)) ........................................................... 7 - 200
7.11.8 Character string length detection (LEN(P)) .............................................................. 7 - 203
7.11.9 Conversion from BIN 16-bit or 32-bit to character string (STR(P),DSTR(P)) ........... 7 - 205
7.11.10 Conversion from character string to BIN 16-bit or 32-bit data (VAL(P),DVAL(P)) .... 7 - 211
7.11.11 Conversion from floating decimal point to character string data (ESTR(P))............. 7 - 216
7.11.12 Conversion from character string to floating decimal point data (EVAL(P)) ............. 7 - 223
7.11.13 Conversion from hexadecimal BIN to ASCII (ASC(P)) ............................................. 7 - 227
7.11.14 Conversion from ASCII to hexadecimal BIN (HEX(P)) ............................................. 7 - 229
7.11.15 Extracting character string data from the right or left (RIGHT(P),LEFT(P)).............. 7 - 231
7.11.16 Random selection from and replacement in character strings
(MIDR(P),MIDW(P)) ................................................................................................. 7 - 234
7.11.17 Character string search (INSTR(P)) ......................................................................... 7 - 238
7.11.18 Insertion of character string (STRINS(P))................................................................. 7 - 240
7.11.19 Deletion of character string (STRDEL(P)) ................................................................ 7 - 242
7.11.20 Floating decimal point to BCD (EMOD(P)) ............................................................... 7 - 244
7.11.21 From BCD format data to floating decimal point (EREXP(P)) .................................. 7 - 247
7.12 Special function instructions 7 - 249
7.12.1 SIN operation on floating-point data (Single precision) (SIN(P)) .............................. 7 - 249
7.12.2 SIN operation on floating-point data (Double precision) (SIND(P)) .......................... 7 - 251
7.12.3 COS operation on floating-point data (Single precision) (COS(P)) .......................... 7 - 253
7.12.4 COS operation on floating-point data (Double precision) (COSD(P)) ...................... 7 - 255
7.12.5 TAN operation on floating-point data (Single precision) (TAN(P))............................ 7 - 257
7.12.6 TAN operation on floating-point data (Double precision) (TAND(P))........................ 7 - 259
7.12.7 SIN-1 operation on floating point data (Single precision) (ASIN(P)) ......................... 7 - 261
7.12.8 SIN-1 operation on floating-point data (Double precision) (ASIND(P)) ..................... 7 - 264
7.12.9 COS -1 operation on floating-point data (Single precision) (ACOS(P)) .................... 7 - 266
7.12.10 COS -1 operation on floating-point data (Double precision) (ACOSD(P)) ................ 7 - 268
7.12.11 TAN -1 operation on floating-point data (Single precision) (ATAN(P))...................... 7 - 270
7.12.12 TAN -1 operation on floating-point data (Double precision) (ATAND(P)).................. 7 - 272
7.12.13 Conversion from floating-point angle to radian (Single precision) (RAD(P)) ............ 7 - 274
7.12.14 Conversion from floating-point angle to radian (Double precision) (RADD(P)) ........ 7 - 276
7.12.15 Conversion from floating-point radian to angle (Single precision) (DEG(P)) ............ 7 - 278
7.12.16 Conversion from floating-point radian to angle (Double precision) (DEGD(P)) ........ 7 - 280

A-12
 7.12.17 Exponentiation operation on floating-point data (Single precision) (POW(P)).......... 7 - 282
7.12.18 Exponentiation operation on floating-point data (Single precision) (POWD(P)) ....... 7 - 284
7.12.19 Square root operation for floating-point data (Single precision) (SQR(P)) ............... 7 - 286
7.12.20 Square root operation for floating-point data (Double precision) (SQRD(P)) ........... 7 - 288
7.12.21 Exponent operation on floating-point data (Single precision) (EXP(P)).................... 7 - 290
7.12.22 Exponent operation on floating-point data (Double precision) (EXPD(P))................ 7 - 293
7.12.23 Natural logarithm operation on floating-point data (Single precision) (LOG(P)) ....... 7 - 295
7.12.24 Natural logarithm operation on floating-point data (Double precision)
(LOGD(P)) ................................................................................................................ 7 - 297
7.12.25 Common logarithm operation on floating-point data (Single precision)
(LOG10(P))............................................................................................................... 7 - 299
7.12.26 Common logarithm operation on floating-point data (Double precision)
(LOG10D(P)) ............................................................................................................ 7 - 301
7.12.27 Random number generation and series updates (RND(P),SRND(P)) ..................... 7 - 303
7.12.28 BCD 4-digit and 8-digit square roots (BSQR(P),BDSQR(P)) ................................... 7 - 305
7.12.29 BCD type SIN operation (BSIN(P))........................................................................... 7 - 308
7.12.30 BCD type COS operations (BCOS(P)) ..................................................................... 7 - 310
7.12.31 BCD type TAN operation (BTAN(P)) ........................................................................ 7 - 312
7.12.32 BCD type SIN -1 operations (BASIN(P)) ................................................................... 7 - 314
7.12.33 BCD type COS -1 operation (BACOS(P)) ................................................................. 7 - 316
7.12.34 BCD type TAN -1 operations (BATAN(P)) ................................................................ 7 - 318
7.13 Data Control Instructions 7 - 320
7.13.1 Upper and lower limit controls for BIN 16-bit and BIN 32-bit data
(LIMIT(P),DLIMIT(P))................................................................................................ 7 - 320
7.13.2 BIN 16-bit and 32-bit dead band controls (BAND(P),DBAND(P)) ............................ 7 - 323
7.13.3 Zone control for BIN 16-bit and BIN 32-bit data (ZONE(P),DZONE(P))................... 7 - 326
7.13.4 Scaling (Point-by-point coordinate data) (SCL(P),DSCL(P)).................................... 7 - 329
7.13.5 Scaling (Point-by-point coordinate data) (SCL2(P),DSCL2(P))................................ 7 - 333
7.14 File register switching instructions 7 - 336
7.14.1 Switching file register numbers (RSET(P))............................................................... 7 - 336
7.14.2 Setting files for file register use (QDRSET(P)) ......................................................... 7 - 338
7.14.3 File setting for comments (QCDSET(P)) .................................................................. 7 - 341
7.15 Clock instructions 7 - 343
7.15.1 Reading clock data (DATERD(P)) ............................................................................ 7 - 343
7.15.2 Writing clock data (DATEWR(P)) ............................................................................. 7 - 345
7.15.3 Clock data addition operation (DATE+(P)) ............................................................... 7 - 347
7.15.4 Clock data subtraction operation (DATE-(P)) ........................................................... 7 - 349
7.15.5 Time data conversion (from Hour/Minute/Second to Second) (SECOND(P)) .......... 7 - 351
7.15.6 Time data conversion (from Second to Hour/Minute/Second) (HOUR(P))............... 7 - 353
7.15.7 Date comparison (DT=,DT<>,DT>,DT<=,DT<,DT>=) .............................................. 7 - 355
7.15.8 Clock comparison (TM=,TM<>,TM>,TM<=,TM<,TM>=).......................................... 7 - 360
7.16 Expansion Clock Instructions 7 - 365
7.16.1 Reading expansion clock data (S(P).DATERD) ....................................................... 7 - 365
7.16.2 Expansion clock data addition operation (S(P).DATE+)........................................... 7 - 368
7.16.3 Expansion clock data subtraction operation (S(P).DATE-)....................................... 7 - 371
7.17 Program control instructions 7 - 374
7.17.1 Program standby instruction (PSTOP(P)) ................................................................ 7 - 376

A-13
 7.17.2 Program output OFF standby instruction (POFF(P))................................................ 7 - 377
7.17.3 Program scan execution registration instruction (PSCAN(P)) .................................. 7 - 379
7.17.4 Program low speed execution registration instruction (PLOW(P)) ........................... 7 - 381
7.17.5 Program execution status check instruction (PCHK)................................................ 7 - 383
7.18 Other instructions 7 - 385
7.18.1 Resetting watchdog timer (WDT(P))......................................................................... 7 - 385
7.18.2 Timing pulse generation (DUTY) .............................................................................. 7 - 387
7.18.3 Time check instruction (TIMCHK)............................................................................. 7 - 389
7.18.4 Direct 1-byte read from file register (ZRRDB(P))...................................................... 7 - 390
7.18.5 File register direct 1-byte write (ZRWRB(P)) ............................................................ 7 - 392
7.18.6 Indirect address read operations (ADRSET(P)) ....................................................... 7 - 394
7.18.7 Numerical key input from keyboard (KEY) ............................................................... 7 - 395
7.18.8 Batch save or recovery of index register (ZPUSH(P),ZPOP(P)) .............................. 7 - 399
7.18.9 Reading Module Information (UNIRD(P))................................................................. 7 - 401
7.18.10 Reading module model name (TYPERD(P))............................................................ 7 - 408
7.18.11 Trace Set/Reset (TRACE,TRACER) ........................................................................ 7 - 413
7.18.12 Writing Data to Designated File (SP.FWRITE)......................................................... 7 - 415
7.18.13 Reading Data from Designated File (SP.FREAD) .................................................... 7 - 427
7.18.14 Writing Data to Standard ROM (SP.DEVST)............................................................ 7 - 439
7.18.15 Read Data from Standard ROM (S(P).DEVLD)........................................................ 7 - 441
7.18.16 Load Program from Memory Card (PLOADP).......................................................... 7 - 443
7.18.17 Unload Program from Program Memory (PUNLOADP) ........................................... 7 - 446
7.18.18 Load + Unload (PSWAPP) ....................................................................................... 7 - 448
7.18.19 High-speed Block Transfer of File Register (RBMOV(P)) ........................................ 7 - 451
7.18.20 User Message (UMSG) ............................................................................................ 7 - 456

Common Instructions 2/2

8. INSTRUCTIONS FOR DATA LINK 8 - 1 to 8 - 10

8.1 Network refresh instructions 8-2
8.1.1 Refresh instruction for the designated module (S(P).ZCOM)....................................... 8 - 2
8.2 Reading/Writing Routing Information 8-6
8.2.1 Reading routing information (S(P).RTREAD) ............................................................... 8 - 6
8.2.2 Registering routing information (S(P).RTWRITE)......................................................... 8 - 8

9. Multiple CPU dedicated instruction 9 - 1 to 9 - 18

9.1 Writing to the CPU Shared Memory of Host CPU 9-2
9.1.1 Write to Host CPU Shared Memory (S(P).TO) ............................................................. 9 - 4
9.1.2 Writing to host station CPU shared memory (TO(P), DTO(P))..................................... 9 - 7
9.2 Reading from the CPU Shared Memory of another CPU 9 - 11
9.2.1 Reading from Other CPU Shared Memory (FROM(P), DFRO(P)) ............................. 9 - 12

10. QCPU INSTRUCTIONS 10 - 1 to 10 - 20

10.1 Overview 10 - 2
10.2 Writing Devices to Another CPU (D(P).DDWR) 10 - 13
10.3 Reading Devices from Another CPU (D(P).DDRD) 10 - 17

A-14
11. QCPU INSTRUCTIONS 11 - 1 to 11 - 4
11.1 System Switching Instruction (SP.CONTSW) 11 - 2

12. ERROR CODES 12 - 1 to 12 - 88

12.1 Error Code List 12 - 2
12.1.1 Error codes ................................................................................................................. 12 - 3
12.1.2 Reading an error code................................................................................................ 12 - 3
12.1.3 Error code list (1000 to 1999) ..................................................................................... 12 - 4
12.1.4 Error code list (2000 to 2999) ................................................................................... 12 - 21
12.1.5 Error code list (3000 to 3999) ................................................................................... 12 - 42
12.1.6 Error code list (4000 to 4999) ................................................................................... 12 - 58
12.1.7 Error code list (5000 to 5999) ................................................................................... 12 - 72
12.1.8 Error code list (6000 to 6999) ................................................................................... 12 - 74
12.1.9 Error code list (7000 to 10000) ................................................................................. 12 - 82
12.2 Canceling of Errors 12 - 87

APPENDICES App - 1 to App - 274

Appendix 1 OPERATION PROCESSING TIME App - 2
Appendix 1.1 Definition .....................................................................................................App - 2
Appendix 1.2 Operation Processing Time of Basic Model QCPU.....................................App - 3
Appendix 1.3 Operation Processing Time of High Performance Model QCPU/Process CPU/
Redundant CPU ........................................................................................App - 21
Appendix 1.4 Operation Processing Time of Universal Model QCPU.............................App - 50
Appendix 1.4.1 Subset instruction processing time............................................................App - 50
Appendix 1.4.2 Processing time of instructions other than subset instruction ...................App - 66
Appendix 1.5 Operation Processing Time of LCPU .....................................................App - 114
Appendix 1.5.1 Subset instruction processing time..........................................................App - 114
Appendix 1.5.2 Processing time of instructions other than subset instruction .................App - 121
Appendix 2 CPU PERFORMANCE COMPARISON App - 141
Appendix 2.1 Comparison of Q, LCPU with AnNCPU, AnACPU, and AnUCPU...........App - 141
Appendix 2.1.1 Usable devices ........................................................................................App - 141
Appendix 2.1.2 I/O control mode......................................................................................App - 142
Appendix 2.1.3 Data that can be used by instructions .....................................................App - 143
Appendix 2.1.4 Timer comparison....................................................................................App - 144
Appendix 2.1.5 Comparison of counters ..........................................................................App - 145
Appendix 2.1.6 Comparison of display instructions..........................................................App - 145
Appendix 2.1.7 Instructions whose designation format has been changed (Except dedicated
instructions for AnACPU and AnUCPU)..................................................App - 146
Appendix 2.1.8 AnACPU and AnUCPU dedicated instructions........................................App - 147
Appendix 3 SPECIAL RELAY LIST App - 148
Appendix 4 SPECIAL REGISTER LIST App - 195
Appendix 5 APPLICATION PROGRAM EXAMPLES App - 274
n
Appendix 5.1 Concept of Programs which Perform Operations of X , X ....................App - 274
n

A-15
 INDEX Index - 1 to Index - 10
INDEX Index- 2
INSTRUCTION INDEX Index- 7

A-16
 MANUALS

To understand the main specifications, functions, and usage of the CPU module, refer to the basic manuals.
Read other manuals as well when using a different type of CPU module and its functions.
Order each manual as needed, referring to the following list.

The numbers in the "CPU module" and the respective modules are as follows.
Nunber CPU module
1) Basic model QCPU
2) High Perfomance model QCPU
3) Process CPU
4) Redundant CPU
5) Universal model QCPU
6) LCPU

:Basic manual, :Other CPU module manuals

Manual name CPU module
Description
< Manual number (model code) > 1) 2) 3) 4) 5) 6)
■User’s manual
Specifications of the hardware (CPU modules,
QCPU User's Manual
power supply modules, base units, extension cables,
(Hardware design, Maintenance and Inspection)
and memory cards), system maintenance and
< SH-080483ENG (13JR73) >
inspection, troubleshooting, and error codes
QnUCPU User’s Manual
(Function Explanation, Program Fundamentals) Functions, methods, and devices for programming
< SH-080807ENG (13JZ27) >
Qn(H)/QnPH/QnPRHCPU User's Manual
(Function Explanation, Program Fundamentals) Functions, methods, and devices for programming
< SH-080808ENG (13JZ28) >
QnUCPU User's Manual
Functions for the communication via built-in Ethernet
(Communication via Built-in Ethernet Port)
port of the CPU module
< SH-080811ENG (13JZ29) >
Specifications of the hardware (CPU modules,
MELSEC-L CPU Module User's Manual
power supply modules, and memory cards), system
(Hardware design, Maintenance and Inspection)
maintenance and inspection, troubleshooting, and
< SH-080890ENG (13JRZ36) >
error codes
MELSEC-L CPU Module User's Manual
(Function Explanation, Program Fundamentals) Functions, methods, and devices for programming
< SH-080889ENG (13JZ35) >
MELSEC-L CPU Module User's Manual
(Built-In I/O Function) Built-in I/O Functionality of the CPU
< SH-080892ENG (13JZ38) >
MELSEC-L CPU Module User's Manual
Functions for the communication via built-in Ethernet
(Communication via Built-in Ethernet Port)
port of the CPU module
< SH-080891ENG (13JZ37) >
MELSEC-L CPU Module User's Manual
(Data Logging Function) Data Logging Functionality of the CPU Module
< SH-080893ENG (13JZ39) >

A-17
 :Basic manual, :Other CPU module manuals
Manual name CPU module
Description
< Manual number (model code) > 1) 2) 3) 4) 5) 6)
■Programming Manual
MELSEC-Q /L Programming Manual (Common How to use sequence instructions, basic instructions,
Instructions) and application instructions
< SH-080809ENG (13JW10) >
System configuration, performance specifications,
MELSEC-Q /L/QnA Programming Manual (SFC)
functions, programming, debugging, and error codes
< SH-080041 (13JF60) >
for SFC (MELSAP3) programs
MELSEC-Q /L Programming Manual (MELSAP-L) Programming methods, specifications, and functions
< SH-080072 (13JC03) > for SFC (MELSAP-L) programs
MELSEC-Q /L Programming Manual
(Structured Text) Programming methods using structured languages
< SH-080366E (13JF68) >
MELSEC-Q /L/QnA Programming Manual
(PID Control Instructions) Dedicated instructions for PID control
< SH-080040 (13JF59) >
QnPH/QnPRHCPU Programming Manual
Describes the dedicated instructions for performing
(Process Control Instructions)
process control.
< SH-080316E (13JF59) >

Related Manuals

Manual name
Description
< Manual number (model code) >
CC-Link IE Controller Network Reference Manual Specifications, procedures and settings before system operation, parameter
< SH-080668ENG (13JV16) > setting, programming, and troubleshooting of the CC-Link IE controller network module
Q Corresponding MELSECNET/H Network System Reference Explains the specifications for a MELSECNET/H network system for PLC to PLC
Manual (PLC to PLC network) network. It explains the procedures and settings up to operation, setting the
< SH-080049 (13JF92) > parameters, programming and troubleshooting.
Q Corresponding MELSECNET/H Network System Refer- Explains the specifications for a MELSECNET/H network system for remote I/O
ence Manual (Remote I/O network) network. It explains the procedures and settings up to operation, setting the
< SH-080124 (13JF96) > parameters, programming and troubleshooting.
Type MELSECNET, MELSECNET/B Data Link System
Describes the general concept, specifications, and part names and settings for
Reference Manual
MELSECNET (II) and MELSECNET/B.
< IB-66530 (13JF70) >
Describes various functions of the Ethernet module: e-mail function, PLC CPU
Q Corresponding Ethernet Interface Module
status monitoring, communication via MELSECNET/H or MELSECNET/10
User's Manual (Application)
network system, communication using data link instructions, file transfer (using
< SH-080010 (13JF70) >
FTP) and other functions.

A-18
1
1
GENERAL
DESCRIPTION

1-1
 This manual describes the common instructions required for programming of the QCPU and
LCPU.
"Common instructions" are all instructions except for dedicated instructions for such intelligent
function modules as QJ71C24N and QJ71E71-100; PID control instructions; SFC instructions;
ST instructions; instructions for socket communication features; trigger logging instructions for
the LCPU; and dedicated instructions for LPCU positioning/counter functionality.

1.1 Related Programming Manuals

Before reading this manual, check the functions, programming methods, devices and others that
are necessary to create programs with the CPU in the manuals below:
• QnUCPU User's Manual (Function Explanation, Program Fundamentals)
• Qn(H)/QnPH/QnPRHCPU User's Manual (Function Explanation, Program Fundamentals)
• MELSEC-L CPU Module User's Manual (Function Explanation, Program Fundamentals)

(1) Basic model QCPU

Qn(H)/QnPH/
QnPRHCPU Explains the functions,
User's Manual programming methods,
(Function Explanation, devices and others that
are necessary to create
Program
programs with the CPU.
Fundamentals)

This manual

MELSEC-Q/L MELSEC-Q/L/ MELSEC-Q/L/ MELSEC-Q/L MELSEC-Q/L

Programming QnA Programming QnA Programming Programming Programming
Manual (Common Manual Manual (SFC) Manual Manual
Instructions) (PID Control (MELSAP-L) (Structured Text)
Instructions)

Describes the instructions Describes the instructions Describes SFC. Describes MELSAP-L. Describes the ST language.
other than those described to perform PID control.
in the manuals on the right.

1-2
 (2) High Performance model QCPU

1
Qn(H)/QnPH/
QnPRHCPU
User's Manual Explains the functions,
programming methods,
2
(Function Explanation,
devices and others that
Program
are necessary to create
Fundamentals)
3
programs with the CPU.

4
This manual

MELSEC-Q/L MELSEC-Q/L/ MELSEC-Q/L/ MELSEC-Q/L MELSEC-Q/L

Programming
Manual (Common
QnA Programming
Manual
QnA Programming
Manual (SFC)
Programming
Manual
Programming
Manual
4
Instructions) (PID Control (MELSAP-L) (Structured Text)
Instructions)

6
Describes the instructions Describes the instructions Describes SFC. Describes MELSAP-L. Describes the ST language.
other than those described to perform PID control.
in the manuals on the right.
7
(3) Process CPU and Redundant CPU

8
Qn(H)/QnPH/
QnPRHCPU Explains the functions,
User's Manual programming methods,
(Function Explanation, devices and others that
Program are necessary to create
programs with the CPU.

1.1 Related Programming Manuals

Fundamentals)

This manual

MELSEC-Q/L MELSEC-Q/L/ MELSEC-Q/L/ MELSEC-Q/L MELSEC-Q/L

Programming QnA Programming QnA Programming Programming Programming
Manual (Common Manual Manual (SFC) Manual Manual
Instructions) (PID Control (MELSAP-L) (Structured Text)
Instructions)

Describes the instructions Describes the instructions Describes SFC. Describes MELSAP-L. Describes the ST language.
other than those described to perform process control.
in the manuals on the right.

1-3
 (4) Universal model QCPU

QnUCPU
User's Manual Explains the functions,
(Function Explanation, programming methods,
devices and others that
Program
are necessary to create
Fundamentals) programs with the CPU.

This manual

MELSEC-Q/L MELSEC-Q/L/ MELSEC-Q/L/ MELSEC-Q/L MELSEC-Q/L

Programming QnA Programming QnA Programming Programming Programming
Manual (Common Manual Manual (SFC) Manual Manual
Instructions) (PID Control (MELSAP-L) (Structured Text)
Instructions)

Describes the instructions Describes the instructions Describes SFC. Describes MELSAP-L. Describes the ST language.
other than those described to perform PID control.
in the manuals on the right.

(5) LCPU

MELSEC-L CPU
Module User's Manual Explains the functions,
(Function Explanation, programming methods,
devices and others that
Program
are necessary to create
Fundamentals) programs with the CPU.

This manual

MELSEC-Q/L MELSEC-Q/L/ MELSEC-Q/L/ MELSEC-Q/L MELSEC-Q/L

Programming QnA Programming QnA Programming Programming Programming
Manual (Common Manual Manual (SFC) Manual Manual
Instructions) (PID Control (MELSAP-L) (Structured Text)
Instructions)

Describes the instructions Describes the instructions Describes SFC. Describes MELSAP-L. Describes the ST language.
other than those described to perform PID control.
in the manuals on the right.

1-4
1.2 Abbreviations and Generic Names
1
This manual uses the generic names and abbreviations shown below to refer to Q/L series CPU
modules, unless otherwise specified.
* indicates a part of the model or version.
2
Generic term/Abbreviation Description of Generic Name/Abbreviation

■ Series
3
Q series Abbreviation for Mitsubishi MELSEC-Q series programmable controller

L series Abbreviation for Mitsubishi MELSEC-L series programmable controller 4

■ CPU module type

CPU module
Generic term for Basic model QCPU, High Performance model QCPU, Process CPU, 4
Redundant CPU, Universal model QCPU and LCPU

Basic model QCPU Generic term for Q00JCPU, Q00CPU and Q01CPU
6
High Performance model
Generic term for Q02CPU, Q02HCPU, Q06HCPU, Q12HCPU and Q25HCPU
QCPU

Process CPU Generic term for Q02PHCPU, Q06PHCPU, Q12PHCPU and Q25PHCPU 7
Redundant CPU Generic term for Q12PRHCPU and Q25PRHCPU

Generic term for Q00UJCPU, Q00UCPU, Q01UCPU, Q02UCPU, Q03UDCPU, 8

Q04UDHCPU, Q06UDHCPU, Q10UDHCPU, Q13UDHCPU, Q20UDHCPU, Q26UDHCPU,
Universal model QCPU
Q03UDECPU, Q04UDEHCPU, Q06UDEHCPU, Q10UDEHCPU, Q13UDEHCPU,
Q20UDEHCPU and Q26UDEHCPU

■ CPU module model

1.2 Abbreviations and Generic Names

QnCPU Generic term for Q00JCPU, Q00CPU, Q01CPU and Q02CPU

QnHCPU Generic term for Q02HCPU, Q06HCPU, Q12HCPU and Q25HCPU

QnPHCPU Generic term for Q02PHCPU, Q06PHCPU, Q12PHCPU and Q25PHCPU

QnPRHCPU Generic term for Q12PRHCPU and Q25PRHCPU

Generic temr for Q00UJCPU, Q00UCPU, Q01UCPU, Q02UCPU, Q03UDCPU,

Q04UDHCPU, Q06UDHCPU, Q10UDHCPU, Q13UDHCPU, Q20UDHCPU, Q26UDHCPU,
QnUCPU
Q03UDECPU, Q04UDEHCPU, Q06UDEHCPU, Q10UDEHCPU, Q13UDEHCPU,
Q20UDEHCPU and Q26UDEHCPU

Generic temr for Q02UCPU, Q03UDCPU, Q04UDHCPU, Q06UDHCPU, Q10UDHCPU,

QnU(D)(H)CPU
Q13UDHCPU, Q20UDHCPU and Q26UDHCPU

Generic name for Q03UDCPU, Q04UDHCPU, Q06UDHCPU, Q10UDHCPU,

QnUD(H)CPU
Q13UDHCPU, Q20UDHCPU and Q26UDHCPU

Generic name for Q03UDECPU, Q04UDEHCPU, Q06UDEHCPU, Q10UDEHCPU,

QnUDE(H)CPU
Q13UDEHCPU,Q20UDEHCPU and Q26UDEHCPU

LCPU Generic name for L02CPU and L26CPU-BT

1-5
 (Continued)

Generic Name/Abbreviation Description of Generic Name/Abbreviation

■ Base unit model

Generic term for Q33B, Q35B, Q38B and Q312B main base units on which CPU module
Q3 B (except Q00JCPU), Q series power supply module, Q series I/O module, and intelligent
function module can be mounted.

Generic term for Q32SB, Q33SB and Q35SB slim type main base units on which Basic
Q3 SB model QCPU (except Q00JCPU), High Performance model QCPU, slim type power supply
module, Q series I/O module, and intelligent function module can be mounted.

Other name for Q38RB redundant power supply main base unit on which CPU module
Q3 RB (except Q00JCPU), redundant power supply module, Q series I/O module, and intelligent
function module can be mounted.

Generic term for the Q38DB and Q312DB type Multiple CPU high speed main base unit on
Q3 DB which CPU module (except the Q00JCPU), Q series power supply module, Q series I/O
module, and intelligent function module can be mounted.

Generic term for Q52B and Q55B extension base unit on which the Q Series I/O and
Q5 B intelligent function module can be mounted.

Generic term for Q63B, Q65B, Q68B and Q612B extension base unit on which Q Series
Q6 B power supply module, I/O module, intelligent function module can be mounted.

Other name for Q68RB redundant power supply extension base unit on whichredundant
Q6 RB power supply module, Q series I/O module, and intelligent function module can be mounted.

Other name for Q65WRB extension base unit for redundant system on which redundant
Q6 WRB power supply module, Q series I/O module, and intelligent function module can be mounted.

Generic term for QA1S65B and QA1S68B extension base units on which AnS Series power
QA1S6 B supply module, I/O module, special function module can be mounted.

Generic term for QA65B and QA68B extension base units on which the A series power
QA6 B supply module, A series I/O modules and special function modules can be mounted.

Generic term for A52B, A55B, and A58B extension base units on which A series I/O module
A5 B and special function module can be mounted without power supply.

Generic term for A62B, A65B, and A68B extension base units on which A series I/O module
A6 B and special function module can be mounted.

QA6ADP Abbreviation for QA6ADP QA conversion adapter module.

QA6ADP+A5 B/A6 B Abbreviation for A large type extension base unit on which QA6ADP is mounted.

■ Network

MELSECNET/H Abbreviation for MELSECNET/H network system

MELSECNET/10 Abbreviation for MELSECNET/10 network system

MELSECNET(II/,B) Abbreviation for MELSECNET and MELSECNET/B data link system

Ethernet Abbreviation for Ethernet network system

CC-Link Abbreviation for Control & Communication Link

1-6
 (Continued)

Generic Name/Abbreviation Description of Generic Name/Abbreviation 1

■ Others

Programing Tool This is a generic name for GX Developer and GX Works2. 2

Product name of Q/L series Corresponding SW D5C-GPPW-type GPP function soft-
ware package
GX Developer : Version of the software
3
Check the GX Developer versions that can be used for each CPU module in "System
Configuration," User's Manual (Hardware Design, Maintenance and Inspection).
4
Product name of Q/L series Corresponding SW D5C-GXW2-type GPP function software
package
GX Works2 : Version of the software
Check the GX Works2 versions that can be used for each CPU module in "System
4
Configuration," User's Manual (Hardware Design, Maintenance and Inspection).

Intelligent function module Generic name for intelligent function modules and special function modules
6
Intelligent function module
Generic name for intelligent function module devices and special function module devices
device
7

1.2 Abbreviations and Generic Names

1-7
MEMO

1-8
2 INSTRUCTION
TABLES 2

2-1
 2.1 Types of Instructions
The major types of CPU module instructions consist of sequence instructions, basic instructions,
application instructions, data link instructions, QCPU instructions and redundant system
instructions. These types of instructions are listed in Table 2.1 below.

Table 2.1 Types of Instructions

Reference
Types of Instruction Meaning
Chapter
Contact instruction Operation start, series connection, parallel connection
Ladder block connection, store/read operation results, creation of pulses from
Association instruction
operation results
Output instruction Bit device output, pulse output, output reversal
Sequence
Shift instruction Bit device shift 5
instruction
Master control instruction Master control
Termination instruction Program termination
Program stop, instructions such as no operation which do not fit in the above
Other instruction
categories
Comparison operation
Comparisons such as , ,
instruction
Arithmetic operation instruction Addition, subtraction, multiplication or division of BIN or BCD

BCD BIN conversion Conversion from BCD to BIN and from BIN to BCD
instruction
Basic
Data transfer instruction Transmits designated data 6
instruction
Program branch instruction Program jumps
Program run control instruction Enables or inhibits interrupt programs
I/O refresh Executes partial refresh
Instructions for: Counter increment/decrement, teaching timer, special function timer,
Other convenient instruction
rotary table shortest direction control, etc.
Logical operation instruction Logical operations such as logical sum, logical product, etc.
Rotation instruction Rotation of designated data
Shift instruction Shift of designated data
Bit processing instruction Bit set and reset, bit test, batch reset of bit devices
Data processing instruction 16-bit data searches, data processing such as decoding and encoding
Structure creation instruction Repeated operation, subroutine program calls, indexing in ladder units
Table operation instruction Data table read/write
Buffer memory access
Data read/write from/to an intelligent function module
instruction
Display instruction Print ASCII code, LED character display, etc.
Debugging and failure
Check, status latch, sampling trace, program trace
diagnosis instruction
Conversion between BIN/BCD and ASCII;conversion between BIN and character
Character string processing
string; conversion between floating decimal point data and character strings,
instruction
Application character string processing, etc.
7
instruction Trigonometric functions, conversion between angles and radians, exponential
Special function instruction
operations, automatic logarithms, square roots
Data control instruction Upper and lower limit controls, dead band controls, zone controls
Switching instruction File register block No. switches, designation of file registers and comment files
Reading/writing of the values of year, month, day, hour, minute, second, and day of
the week; addition/subtraction of the values of hour, minute, and second; conversion
Clock instruction of the values of hour, minute, and second into second; comparison between the
values of year, month, and day; and comparison between the values of hour, minute,
and second
Reading of the values of year, month, day, hour, minute, second, millisecond, and
Expansion clock instruction day of the week; addition/subtraction of the values of hour, minute, second, and
millisecond
Peripheral device instruction I/O to peripheral devices
Program control instruction Instructions to switch program execution conditions
Instructions that do not fit in the above categories, such as watchdog timer reset
Other instruction
instructions and timing clock instructions

2-2
 Table 2.1 Types of Instructions (Continued)
Reference
Types of Instruction Meaning
Chapter
Link refresh instruction Designated network refresh
Instruction
Routing information read/write 8
for Data Link
instruction
Reads, writes, and registers routing information
2
Multiple
CPU Multiple CPU dedicated
Writing to host CPU shared memory, Reading from other CPU shared memory 9
dedicated
instruction
instruction
3
Multiple CPU
high-speed
transmission
Multiple CPU device write/read
instruction
Writes/reads devices to/from another CPU. 10 4
dedicated
instruction
Redundant
system Instruction for Redundant CPU System switching 11
4
instruction

2.1 Types of Instructions

2-3
 2.2 How to Read Instruction Tables
The instruction tables found from Section 2.3 to 2.5 have been made according to the following
format:

Table 2.2 How to Read Instruction Tables

Number of Basic Steps

Instruction Symbols

See for Description

Subset
Execution
Category Symbol Processing Details
Condition

+ + S D
BIN (D)+(S) (D) 3 6-16
16-bit
addition +P +P S D
and
subtraction + + S1 S2 D
operations
(S1)+(S2) (D) 4 6-20
+P +P S1 S2 D

1) 2) 3) 4) 5) 6) 7) 8)

Description
1) ..........Classifies instructions according to their application.
2) ..........Indicates the instruction symbol added to the instruction in a program.
Instruction code is built around the 16-bit instruction. The following notations are used to
mark 32-bit instructions, instructions executed only at the leading edge of OFF to ON,
real number instructions, and character string instructions:
• 32-bit instruction ..... The letter "D" is added to the first line of the instruction.
Example + D+

16-bit instruction 32-bit instruction

• Instructions executed only at the leading edge of OFF to ON

............................... The letter "P" is added to the end of the instruction.
Example + +P

Instruction executed Instruction executed

when ON only at the leading
edge of OFF to ON

• Real number instructions

............................... The letter "E" is added to the first line of the instruction.
Example + E+

Real number instructions

• Character string instructions

............................... A dollar sign $ is added to the first line of the instruction.
Example + $+

Character string instructions

2-4
3) ..........Shows symbol diagram on the ladder.

+ S D + S1 S2 D

Indicates destination. Indicates destination.

Indicates source.
Indicates instruction symbol.
Indicates source.
Indicates instruction symbol.
2
Fig. 2.1 Symbol Diagram on the Ladder
3
Destination............ Indicates where data will be sent after operation.
Source .................. Stores data prior to operation.
4
4) ..........Indicates the type of processing that is performed by individual instructions.

(D)+(S) (D) (D+1, D) +(S+1, S) (D +1,D)

4
16 bits 16 bits
Indicates 16 bits.

D+1
Indicates 32 bits.
D 6
Upper 16 bits Lower 16 bits

Fig. 2.2 Type of Processing Performed by Individual Instructions

7
5) ..........The details of conditions for the execution of individual instructions are as follows:
Symbol Execution Condition
8
Instruction executed under normal circumstances, with no regard to the ON/OFF status of conditions prior to
No symbol
the instruction.
recorded
If the precondition is OFF, the instruction will conduct OFF processing.
Executed during ON; instruction is executed only while the precondition is ON. If the preconditions is OFF,
the instruction is not executed, and no processing is conducted.

2.2 How to Read Instruction Tables

Executed once at ON; instruction executed only at leading edge when precondition goes from OFF to ON.
Following execution, instruction will not be executed and no processing conducted even if condition remains
ON.
Executed during OFF; instruction is executed only while the precondition is OFF. If the precondition is ON,
the instruction is not executed, and no processing is conducted.
Executed once at OFF; instruction executed only at trailing edge when precondition goes from ON to OFF.
Following execution, instruction will not be executed and no processing conducted even if condition remains
OFF.

6) ..........Indicates the basic number of steps for individual instructions.

See Section 3.8 for a description of the number of steps.

7) ..........The mark indicates instructions for which subset processing is possible.

See Section 3.5 for details on subset processing.

8) ..........Indicates the page numbers where the individual instructions are explained.

2-5
 2.3 Sequence Instructions

2.3.1 Contact instructions

Table 2.3 Contact Instructions

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

• Starts logic operation

LD
(Starts a contact logic operation)
• Starts logical NOT operation
LDI
(Starts b contact logic operation)

AND • Logical product (a contact series connection)

*1 5-2
• Logical product NOT (b contact series
ANI
connection)

OR • Logical sum (a contact parallel connection)

• Logical sum NOT (b contact parallel

ORI
connection)

LDP • Starts leading edge pulse operation

LDF • Starts trailing edge pulse operation

ANDP • Leading edge pulse series connection

Contact
*1 5-5
ANDF • Trailing edge pulse series connection

ORP • Leading edge pulse parallel connection

ORF • Trailing edge pulse parallel connection

LDPI • Starts leading edge pulse NOT operation 3*2

LDFI • Starts trailing edge pulse NOT operation 3*2

ANDPI • Leading edge pulse NOT series connection 4*2

5-7
ANDFI • Trailing edge pulse NOT series connection 4*2

ORPI • Leading edge pulse NOT parallel connection 4*2

ORFI • Trailing edge pulse NOT parallel connection 4*2

*1: The number of steps may vary depending on the device being used.

Device Number of Steps

Internal device, file register (R0 to R32767) 1
Direct access input (DX) 2
Devices other than above 3

2-6
 *2: The number of steps may vary depending on the device and type of CPU module being used.

Device Number of Steps

Internal device, file register (R0 to R32767) 1

Direct access input (DX) 1

Devices other than above 3 2

The number of steps may vary depending on the device being used.

Device Number of Steps

3
Internal device, file register (R0 to R32767) Number of Basic Steps

Serial number access format file register (ZR), Extended data register (D),
Number of Basic Steps +1
Extended link register (W), Multiple CPU shared device (U3En\G10000) 4
Direct access input (DX) Number of Basic Steps +1

Devices other than above Number of Basic Steps +2

4
2.3.2 Association instructions
6
Table 2.4 Association Instructions

Number of Basic Steps

7

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition
8

• AND between logical blocks

ANB
ANB (Series connection between logical blocks)
1 - 5-10

2.3.2 Association instructions

2.3 Sequence Instructions
• OR between logical blocks
ORB
ORB (Series connection between logical blocks)

MPS • Memory storage of operation results

MPS • Read of operation results stored with MPS

MRD
instruction 1 - 5-12
MRD
MPP • Read and reset of operation results stored with
MPP
MPS instruction
Connec-
tion INV • Inversion of operation result 1 - 5-15
• Conversion of operation result to leading edge
MEP
pulse
1 - 5-17
• Conversion of operation result to trailing edge
MEF
pulse
• Conversion of operation result to leading edge
EGP Vn pulse 1
(Stored at Vn)
- 5-18
• Conversion of operation result to trailing edge
EGF Vn pulse *1
(Stored at Vn)

*1: The number of steps may vary depending on the device and type of CPU module being used.

Component Number of Basic Steps

High Performance model QCPU
Process CPU
Redundant CPU 1
Universal model QCPU
LCPU
Basic model QCPU 2

2-7
 2.3.3 Output instructions

Table 2.5 Output Instructions

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

5-20
5-22
OUT • Device output *1 -
5-26
5-28

*2 5-30
SET SET D • Sets device *1 -
5-35

*2 5-32
RST RST D • Resets device *1 -
5-35
Output
• Generates 1 cycle program pulse at leading
PLS PLS D
edge of input signal.
2 - 5-37
• Generates 1 cycle program pulse at trailing
PLF PLF D
edge of input signal.

FF FF D • Reversal of device output 2 - 5-40

DELTA DELTA D
• Pulse conversion of direct output 2 - 5-42
DELTAP DELTAP D

*1: The number of steps may vary depending on the device being used. See description pages of individual
instructions for number of steps.

*2: The execution condition applies only when an annunciator (F) is in use.

2.3.4 Shift instructions

Table 2.6 Shift Instructions

Number of Basic Steps

See for Description

Instruction Symbol

Subset

Execution
Category Symbol Processing Details
Condition

SFT SFT D
Shift • 1-bit shift of device 2 - 5-44
SFTP SFTP D

2-8
 2.3.5 Master control instructions

Table 2.7 Master Control Instructions

Number of Basic Steps

2

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition
3

MC • Starts master control 2

Master MC n D
- 5-47 4
control
MCR MCR n • Resets master control 1

4
2.3.6 Termination instructions

Table 2.8 Termination Instructions 6

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

8
FEND FEND • Termination of main program 5-51
Termination 1 -
END END • Termination of sequence program 5-53

2.3.5 Master control instructions

2.3 Sequence Instructions
2.3.7 Other instructions

Table 2.9 Other Instructions

Number of Basic Steps

See for Description

Instruction Symbol

Subset

Execution
Category Symbol Processing Details
Condition

• Terminates sequence operation after

input condition has been met.
Stop STOP STOP • Sequence program is executed by 1 - 5-55
placing the RUN/STOP key switch
back in the RUN position.
• Ignored (For program deletion or
NOP ––––––
space)
• Ignored (To change pages during
Ignored NOPLF NOPLF 1 - 5-57
printouts)
• Ignored (Subsequent programs will be
PAGE PAGE n
controlled from step 0 of page n)

2-9
 2.4 Basic instructions

2.4.1 Comparison operation instructions

Table 2.10 Comparison Operation Instructions

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

LD= S1 S2
• Conductive status when (S1) (S2)
AND= S1 S2
• Non-conductive status when 3
(S1) (S2)
OR=
S1 S2

LD<> S1 S2
• Conductive status when (S1) (S2)
AND<> S1 S2
• Non-conductive status when 3
(S1) (S2)
OR<>
S1 S2

LD> S1 S2
• Conductive status when (S1) (S2)
AND> S1 S2
• Non-conductive status when 3
(S1) (S2)
OR>
BIN 16-bit S1 S2
data 6-2
comparisons LD<= S1 S2
• Conductive status when (S1) (S2)
AND<= S1 S2
• Non-conductive status when 3
(S1) (S2)
OR<=
S1 S2

LD< S1 S2
• Conductive status when (S1) (S2)
AND< S1 S2
• Non-conductive status when 3
(S1) (S2)
OR<
S1 S2

LD>= S1 S2
• Conductive status when (S1) (S2)
AND>= S1 S2
• Non-conductive status when 3
(S1) (S2)
OR>=
S1 S2

2-10
 Table 2.10 Comparison Operation Instructions (Continued)

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition
2

LDD= D S1 S2
• Conductive status when
3
ANDD= D S1 S2 (S1+1, S1) (S2+1, S2)
*1
• Non-Conductive status when
ORD= (S1+1, S1) (S2+1, S2) 4
D S1 S2

LDD<> D S1 S2

ANDD<> D S1 S2
• Conductive status when
(S1+1, S1) (S2+1, S2)
4
*1
• Non-Conductive status when
ORD<> (S1+1, S1) (S2+1, S2)
D S1 S2 6
LDD> D S1 S2
• Conductive status when
ANDD> D S1 S2 (S1+1, S1) (S2+1, S2)
• Non-Conductive status when
*1 7
ORD> (S1+1, S1) (S2+1, S2)
BIN 32-bit D S1 S2
data
comparisons LDD<= D S1 S2
6-4
8
• Conductive status when
ANDD<= D S1 S2 (S1+1, S1) (S2+1, S2)
*1
• Non-Conductive status when
ORD<= (S1+1, S1) (S2+1, S2)
D S1 S2

2.4.1 Comparison operation instructions

2.4 Basic instructions
LDD< D S1 S2
• Conductive status when
ANDD< D S1 S2 (S1+1, S1) (S2+1, S2)
*1
• Non-Conductive status when
ORD< (S1+1, S1) (S2+1, S2)
D S1 S2

LDD>= D S1 S2
• Conductive status when
ANDD>= D S1 S2 (S1+1, S1) (S2+1, S2)
*1
• Non-Conductive status when
ORD>= (S1+1, S1) (S2+1, S2)
D S1 S2

*1: The number of steps may vary depending on the device and type of CPU module being used.

Number of
Component Device
Steps
• Word device: Internal device (except for file register ZR)
High Performance model QCPU • Bit device: Devices whose device Nos. are multiples of 16, whose digit
5 Note 1)
Process CPU designation is K8, and which use no Indexing.
• Constant: No limitations
Redundant CPU
Devices other than above 3 Note 2)
Basic model QCPU
Universal model QCPU All devices that can be used 3 Note 2)
LCPU

Note 1) When using a High Performance model QCPU, Process CPU or Redundant CPU,
the number of steps increases but the processing speed becomes faster.
Note 2) The number of steps may increase due to the conditions described in Section 3.8.

2-11
 Table 2.10 Comparison Operation Instructions (Continued)

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

LDE= E S1 S2
• Conductive status when
ANDE= E S1 S2 (S1+1, S1) (S2+1, S2)
3 -
• Non-Conductive status when

ORE= (S1+1, S1) (S2+1, S2)

E S1 S2

LDE<> E S1 S2
• Conductive status when
ANDE<> E S1 S2 (S1+1, S1) (S2+1, S2)
3 -
• Non-Conductive status when

ORE<> (S1+1, S1) (S2+1, S2)

E S1 S2

LDE> E S1 S2
• Conductive status when
ANDE> E S1 S2 (S1+1, S1) (S2+1, S2)
3 -
Floating • Non-Conductive status when
decimal ORE> (S1+1, S1) (S2+1, S2)
point data
E S1 S2
6-6
comparisons
LDE<= E S1 S2
(Single • Conductive status when
precision) ANDE<= E S1 S2 (S1+1, S1) (S2+1, S2)
3 -
• Non-Conductive status when

ORE<= (S1+1, S1) (S2+1, S2)

E S1 S2

LDE< E S1 S2
• Conductive status when
ANDE< E S1 S2 (S1+1, S1) (S2+1, S2)
3 -
• Non-Conductive status when

ORE< (S1+1, S1) (S2+1, S2)

E S1 S2

LDE>= E S1 S2
• Conductive status when
ANDE>= E S1 S2 (S1+1, S1) (S2+1, S2)
3 -
• Non-Conductive status when

ORE>= (S1+1, S1) (S2+1, S2)

E S1 S2

2-12
 Table 2.10 Comparison Operation Instructions (Continued)

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition
2

LDED= ED S1 S2 • Conductive status when 3

(S1+3, S1+2, S1+1, S1)
ANDED= ED S1 S2 (S2+3, S2+2, S2+1, S2)
3 -
• Non-Conductive status when

ORED= (S1+3, S1+2, S1+1, S1) 4

ED S1 S2 (S2+3, S2+2, S2+1, S2)

LDED<> • Conductive status when

4
ED S1 S2
(S1+3, S1+2, S1+1, S1)
ANDED<> ED S1 S2 (S2+3, S2+2, S2+1, S2)
3 -
• Non-Conductive status when
ORED<>
ED S1 S2
(S1+3, S1+2, S1+1, S1)
(S2+3, S2+2, S2+1, S2)
6
LDED> ED S1 S2 • Conductive status when
(S1+3, S1+2, S1+1, S1)
ANDED> ED S1 S2 (S2+3, S2+2, S2+1, S2)
3 -
7
Floating • Non-Conductive status when
decimal ORED> (S1+3, S1+2, S1+1, S1)
point data ED S1 S2 (S2+3, S2+2, S2+1, S2)
6-8 8
comparisons • Conductive status when
LDED<= ED S1 S2
(Double (S1+3, S1+2, S1+1, S1)
precision) ANDED<= ED S1 S2 (S2+3, S2+2, S2+1, S2)
3 -
• Non-Conductive status when
(S1+3, S1+2, S1+1, S1)

2.4.1 Comparison operation instructions

2.4 Basic instructions
ORED<=
ED S1 S2 (S2+3, S2+2, S2+1, S2)

LDED< ED S1 S2 • Conductive status when

(S1+3, S1+2, S1+1, S1)
ANDED< ED S1 S2 (S2+3, S2+2, S2+1, S2)
3 -
• Non-Conductive status when
ORED< (S1+3, S1+2, S1+1, S1)
ED S1 S2 (S2+3, S2+2, S2+1, S2)

LDED>= ED S1 S2 • Conductive status when

(S1+3, S1+2, S1+1, S1)
ANDED>= ED S1 S2 (S2+3, S2+2, S2+1, S2)
3 -
• Non-Conductive status when
ORED>= (S1+3, S1+2, S1+1, S1)
ED S1 S2 (S2+3, S2+2, S2+1, S2)

2-13
 Table 2.10 Comparison Operation Instructions (Continued)

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

LD$= • Compares character string S1 and

$ S1 S2
character string S2 one character at a
AND$= $ S1 S2 time. *2
• Conductive status when (character
3 -
string S1) (character string S2)
• Non-Conductive status when
OR$=
$ S1 S2 (character string S1) (character
string S2)

LD$<> • Compares character string S1 and

$ S1 S2
character string S2 one character at a
AND$<> $ S1 S2 time. *2
• Conductive status when (character
3 -
string S1) (character string S2)
OR$<> • Non-Conductive status when
$ S1 S2 (character string S1) (character
string S2)

LD$> • Compares character string S1 and

$ S1 S2
character string S2 one character at a
AND$> $ S1 S2 time. *2
• Conductive status when (character
3 -
string S1) (character string S2)
• Non-Conductive status when
OR$>
$ S1 S2 (character string S1) (character
Character
string S2)
string data 6-8
• Compares character string S1 and
comparisons LD$<= $ S1 S2
character string S2 one character at a
AND$<= $ S1 S2 time. *2
• Conductive status when (character
3 -
string S1) (character string S2)
• Non-Conductive status when
OR$<=
$ S1 S2 (character string S1) (character
string S2)

LD$< • Compares character string S1 and

$ S1 S2
character string S2 one character at a
AND$< $ S1 S2 time. *2
• Conductive status when (character
3 -
string S1) (character string S2)

OR$< • Non-Conductive status when

$ S1 S2 (character string S1) (character
string S2)

LD$>= • Compares character string S1 and

$ S1 S2
character string S2 one character at a
AND$>= $ S1 S2 time. *2
• Conductive status when (character
3 -
string S1) (character string S2)
• Non-Conductive status when
OR$>=
$ S1 S2 (character string S1) (character
string S2)

*2: The conditions under which character string comparisons can be made are as shown below:
• Match: All characters in the strings must match
• Larger string: If character strings are different, determines the string with the largest number of
character codes. If the lengths of the character strings are different, determines the
longest character string.
• Smaller string: If the character strings are different, determines the string with the smallest number of
character codes.
If the lengths of the character strings are different, determines the shortest character
string.

2-14
 Table 2.10 Comparison Operation Instructions (Continued)

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition
2

BKCMP= BKCMP S1 S2 D n 3
BKCMP<> BKCMP S1 S2 D n

BKCMP> BKCMP S1 S2 D n 4
BKCMP<= BKCMP S1 S2 D n

BKCMP< BKCMP S1 S2 D n
• This instruction compares BIN 16-bit
data stored in n-point devices starting
4
BIN 16-bit from the device specified by S1 with
BKCMP>= BKCMP S1 S2 D n
Block BIN 16-bit data stored in n-point
5 - 6-15
data
comparisons
BKCMP=P BKCMP P S1 S2 D n
devices starting from the device
specified by S2, and then stores the
6
result into the nth device specified by
BKCMP<>P BKCMP P S1 S2 D n (D) and up.

BKCMP>P BKCMP P S1 S2 D n 7
BKCMP<=P BKCMP P S1 S2 D n

BKCMP<P BKCMP P S1 S2 D n 8
BKCMP>=P BKCMP P S1 S2 D n

DBKCMP= DBKCMP S1 S2 D n

2.4.1 Comparison operation instructions

2.4 Basic instructions
DBKCMP<> DBKCMP S1 S2 D n

DBKCMP> DBKCMP S1 S2 D n

DBKCMP<= DBKCMP S1 S2 D n
• This instruction compares BIN 32-bit
DBKCMP< DBKCMP S1 S2 D n data stored in n-point devices starting
BIN from the device specified by S1 with
DBKCMP>= DBKCMP S1 S2 D n
32-bit block BIN 32-bit data stored in n-point
5 - 6-18
data devices starting from the device
DBKCMP=P DBKCMP P S1 S2 D n
comparisons specified by a constant and S2, and
DBKCMP<>P then stores the result into the nth
DBKCMP P S1 S2 D n
device specified by (D) and up.
DBKCMP>P DBKCMP P S1 S2 D n

DBKCMP<=P DBKCMP P S1 S2 D n

DBKCMP<P DBKCMP P S1 S2 D n

DBKCMP>=P DBKCMP P S1 S2 D n

2-15
 2.4.2 Arithmetic operation instructions

Table 2.11 Arithmetic Operation Instructions

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

+ + S D
• (D)+(S) (D) 3 6-22
+P +P S D

+ + S1 S2 D
BIN 16-bit • (S1)+(S2) (D) 4 6-24
+P +P S1 S2 D
addition and
subtraction
- S D
operations
• (D) (S) (D) 3 6-22
-P P S D

- S1 S2 D
• (S1) (S2) (D) 4 6-24
-P P S1 S2 D

D+ D+ S D
• (D+1, D)+(S+1, S) (D+1, D) *1 6-26
D+P D+P S D

D+ D+ S1 S2 D
BIN 32-bit • (S1+1, S1)+(S2+1, S2) (D+1, D) *2 6-28
D+P D+P S1 S2 D
addition and
subtraction
D- D S D
operations *1 6-26
• (D+1, D) (S+1, S) (D+1, D)
D-P D P S D

D- D S1 S2 D
• (S1+1, S1) (S2+1, S2) (D+1, D) *2 6-28
D-P D P S1 S2 D

* * S1 S2 D
• (S1) (S2) (D+1,D) *3
BIN 16-bit
*P S1 S2 D
multiplication
6-30
and division
/ / S1 S2 D
operations • (S1) / (S2)
4*4
Quotient(D), Remainder (D+1)
/P /P S1 S2 D

D* S1 S2 D
BIN 32-bit • (S1+1,S1) (S2+1,S2) (D+3,D+2,D+1,D) 4*4
D*P S1 S2 D
multiplication
6-32
and division • (S1+1, S1) / (S2+1, S2)
D/ D/ S1 S2 D
operations
Quotient (D+1, D), Remainder (D+3, 4*4
D/P D/P S1 S2 D D+2)

2-16
 *1: The number of steps may vary depending on the device and type of CPU module being used.

Number of
Component Device
Steps
• Word device: Internal device (except for file register ZR)
High Performance model QCPU • Bit device: Devices whose device Nos. are multiples of 16, whose digit
5 Note 1)
designation is K8, and which use no indexing.
Process CPU
Redundant CPU
• Constant: No limitations 2
Devices other than above Note 2)
3
Basic model QCPU
Universal model QCPU All devices that can be used 3 Note 2) 3
LCPU

Note 1) When using a High Performance model QCPU, Process CPU or Redundant CPU,
the number of steps increases but the processing speed becomes faster. 4
Note 2) The number of steps may increase due to the conditions described in Section 3.8.

*2: The number of steps may vary depending on the device and type of CPU module being used. 4
Number of
Component Device
Steps
• Word device: Internal device (except for file register ZR) 6
High Performance model QCPU • Bit device: Devices whose device Nos. are multiples of 16, whose digit
6 Note 1)
Process CPU designation is K8, and which use no indexing.
• Constant: No limitations
Redundant CPU
Devices other than above 4 Note 2)
7
Basic model QCPU 4 Note 2)
All devices that can be used
Universal model QCPU
LCPU
3 Note 2) 8
Note 1) When using a High Performance model QCPU, Process CPU or Redundant CPU,
the number of steps increases but the processing speed becomes faster.
Note 2) The number of steps may increase due to the conditions described in Section 3.8.

2.4.2 Arithmetic operation instructions

2.4 Basic instructions
*3: The number of steps may vary depending on the device and type of CPU module being used.

Component Device Number of Steps

• Word device: Internal device (except for file register ZR)
• Bit device: Devices whose device Nos. are multiples of 16, whose digit
QCPU 3
designation is K8, and which use no indexing.
LCPU • Constant: No limitations
Devices other than above 4 Note 1)

Note 1) The number of steps may increase due to the conditions described in Section 3.8.
*4: The number of basic steps is three for the Universal model QCPU and LCPU only.

2-17
 Table 2.11 Arithmetic Operation Instructions (Continued)

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

B+ B+ S D
• (D)+(S) (D) 3 6-34
B+P B+P S D

B+ B+ S1 S2 D
BCD 4-digit 4 - 6-36
• (S1)+(S2) (D)
addition B+P B+P S1 S2 D
and
subtraction B- B S D
operations • (D) (S) (D) 3 6-34
B-P B P S D

B- B S1 S2 D
• (S1) (S2) (D) 4 - 6-36
B-P B P S1 S2 D

DB+ DB+ S D
• (D+1, D)+(S+1, S) (D+1, D) 3 - 6-38
DB+P DB+P S D

DB+ DB+ S1 S2 D
BCD 8-digit 4 - 6-40
• (S1+1, S1)+(S2+1, S2) (D+1, D)
addition DB+P DB+P S1 S2 D
and
subtraction DB- DB S D
operations • (D+1, D) (S+1, S) (D+1, D) 3 - 6-38
DB-P DB P S D

DB- DB S1 S2 D
• (S1+1, S1) (S2+1, S2) (D+1, D) 4 - 6-40
DB-P DB P S1 S2 D

B* B S1 S2 D
BCD 4-digit 4
• (S1) (S2) (D+1,D)
multiplication B*P B P S1 S2 D
and 6-42
division B/ B/ S1 S2 D • (S1) / (S2)
operations 4
Quotient(D), Remainder (D+1)
B/P B/P S1 S2 D

DB* DB S1 S2 D
BCD 8-digit • (S1+1,S1) (S2+1,S2)
4 -
multiplication DB*P (D+3,D+2,D+1,D)
DB P S1 S2 D
and 6-44
division DB/ DB/ S1 S2 D • (S1+1, S1) / (S2+1, S2)
operations Quotient (D+1, D), 4
DB/P DB/P S1 S2 D Remainder (D+3, D+2)

2-18
 Table 2.11 Arithmetic Operation Instructions (Continued)

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition
2

E+ E+ S D 3
• (D+1, D)+(S+1, S) (D+1, D) 3 6-46
E+P *6
E+P S D
Floating
decimal
point data
E+ E+ S1 S2 D
4
4
• (S1+1, S1)+(S2+1, S2) (D+1, D) 6-48
*5 *6
addition E+P E+P S1 S2 D
and
subtraction E- E S D 4
operations • (D+1, D) (S+1, S) (D+1, D) 3 6-46
E-P *6
(Single E P S D
precision)
E- E S1 S2 D
4
6
• (S1+1, S1) (S2+1, S2) (D+1, D) 6-48
*5 *6
E-P E P S1 S2 D

ED+ ED+ S D • (D+3, D+2, D+1, D)+(S+3, S+2, S+1, S) 7

3 6-50
(D+3, D+2, D+1, D)
ED+P ED+P S D
Floating
decimal
point data
ED+ ED+ S1 S2 D • (S1+3, S1+2, S1+1, S1)+ 8
(S2+3, S2+2, S2+1, S2) 4 6-52
addition ED+P ED+P S1 S2 D (D+3, D+2, D+1, D)
and
subtraction ED- ED S D
• (D+3, D+2, D+1, D) (S+3, S+2, S+1, S)
operations 3 6-50
(D+3, D+2, D+1, D)

2.4.2 Arithmetic operation instructions

2.4 Basic instructions
ED-P ED P S D
(Double
precision)
ED- ED S1 S2 D • (S1+3, S1+2, S1+1, S1)
(S2+3, S2+2, S2+1, S2) 4 6-52
ED-P ED P S1 S2 D
(D+3, D+2, D+1, D)
Floating
E* S1 S2 D
decimal 3
• (S1+1,S1) (S2+1,S2) (D+1,D)
point data *6
E*P S1 S2 D
multiplication
6-54
and division E/ E/ S1 S2 D
• (S1+1, S1) / (S2+1, S2)
operations 4
(Single Quotient (D+1, D) *6
E/P E/P S1 S2 D
precision)
Floating • (S1+3,S1+2,S1+1,S1)
ED* ED S1 S2 D
decimal 4
(S2+3,S2+2,S2+1,S2)
point data *6
ED*P ED P S1 S2 D (D+3,D+2,D+1,D)
multiplication
6-56
and division ED/ ED/ S1 S2 D • (S1+3, S1+2, S1+1, S1) /
operations 4
(S2+3, S2+2, S2+1, S2)
(Double ED/P ED/P S1 S2 D *6
Quotient (D+3, D+2, D+1, D)
precision)

*5: The number of basic steps is three for the Universal model QCPU and LCPU only.
*6: The subset is effective only with Universal model QCPU and LCPU.

2-19
 Table 2.11 Arithmetic Operation Instructions (Continued)

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

• This instruction adds BIN 16-bit data

BK+ BK+ S1 S2 D n
stored in n-point devices starting from the
BIN 16-bit device specified by (S1) to the n-point data 5 -
data block BK+P BK+P S1 S2 D n stored in the devices starting from the
addition device specified by (S2) in batch.
6-59
and • This instruction substracts BIN 16-bit data
BK- BK S1 S2 D n
subtraction stored in the n-point devices starting from
operations the devices specified by (S2) from BIN 16- 5 -
BK-P BK P S1 S2 D n bit data stored in n-point devices starting
from the device specified by (S1) in batch.
• Adds BIN 32-bit data stored in the n-
DBK+ DBK+ S1 S2 D n point devices starting from the device
specified by (S1) and a constant to BIN
32-bit data stored in the n-point devices 5 -
BIN 32-bit starting from the device specified by
DBK+P DBK+P S1 S2 D n
data block (S2) and stores the result into the nth
addition device specified by (D) and up.
6-62
and • Subtracts BIN 32-bit data stored in the
subtraction DBK- DBK S1 S2 D n n-point devices starting from the device
operations specified by (S2) or a constant from BIN
32-bit data stored in n-point devices 5 -
starting from the device specified by
DBK-P DBK P S1 S2 D n
(S1) and stores the operation result into
the nth device specified by (D) and up.

$+ $+ S D • Links character string designated with (S)

to character string designated with (D), 3 - 6-66
Character $+P $+P S D and stores the result from (D) onward.
string data
Connection $+ $+ S1 S2 D • Links character string designated with (S2)
to character string designated with (S1), 4 - 6-68
$+P $+P S1 S2 D and stores the result from (D) onward.

INC INC D
• (D)+1 (D) 2 6-70
INCP INCP D

DINC DINC D
• (D+1, D)+1 (D+1, D) *7 6-72
DINCP DINCP D
BIN data
increment
DEC DEC D
• (D) 1 (D) 2 6-70
DECP DECP D

DDEC DDEC D
• (D+1, D) 1 (D+1, D) *7 6-72
DDECP DDECP D

2-20
 *7: The number of steps may vary depending on the device and type of CPU module being used.

Number of
Component Device
Steps
• Word device: Internal device (except for file register ZR)
High Performance model QCPU • Bit device: Devices whose device Nos. are multiples of 16, whose digit
3 Note 1)
designation is K8, and which use no indexing.
Process CPU
Redundant CPU
• Constant: No limitations 2
Devices other than above Note 2)
2
Basic model QCPU
Universal model QCPU All devices that can be used 2 Note 2) 3
LCPU

Note 1) When using a High Performance model QCPU, Process CPU or Redundant CPU,
the number of steps increases but the processing speed becomes faster. 4
Note 2) The number of steps may increase due to the conditions described in Section 3.8.

2.4.2 Arithmetic operation instructions

2.4 Basic instructions

2-21
 2.4.3 Data conversion instructions

Table 2.12 Data Conversion Instructions

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

BCD BCD S D BCD conversions 3

(S) (D)
*1
BCDP BCDP S D BIN (0 to 9999)
BCD
6-74
conversions
DBCD DBCD S D BCD conversions
3
(S+1, S) (D+1, D)
*1
DBCDP DBCDP S D BIN (0 to 99999999)

BIN BIN S D BIN conversions 3

(S) (D)
*1
BINP BINP S D BCD (0 to 9999)
BIN
6-76
conversions
DBIN DBIN S D BIN conversions
(S+1, S) (D+1, D) 3
*1
DBINP DBINP S D BCD (0 to 99999999)

BIN FLT FLT S D Conversion to real number 3

(S) (D+1, D)
*1 *2
FLTP FLTP S D BIN( 32768 to 32767)
Floating
point 6-79
DFLT DFLT S D Conversion to real number
conversions (S+1, S) (D+1, D) 3
(Single BIN( 2147483648 to *1 *2
DFLTP DFLTP S D
precision) 2147483647)
BIN FLTD FLTD S D Conversion to real number
(S) ( D+3, D+2, D+1, D) 4
FLTDP *2
FLTDP S D BIN( 32768 to 32767)
Floating
point 6-82
DFLTD DFLTD S D Conversion to real number
conversions (S+1, S) (D+3, D+2, D+1, D)
4
(Double BIN( 2147483648 to *2
DFLTDP DFLTDP S D
precision) 2147483647)

Floating INT INT S D Conversion to BIN

point
3
(S+1, S) (D)
*1 *2
INTP INTP S D  
Real number (-32768 to 32767)

BIN 6-84
DINT DINT S D Conversion to BIN
conversions (S+1, S) (D+1, D) 3
(Single Real number (-2147483648 to *1 *2
DINTP DINTP S D
precision) 2147483647)

Floating INTD INTD S D Conversion to BIN

point
(S+3, S+2, S+1, S) (D)
3
INTDP
Real number ( 32768 to *2
INTDP S D
32767)
BIN 6-87
DINTD DINTD S D Conversion to BIN
conversions
(S+3, S+2, S+1, S) (D+1, D)
(Double 3
DINTDP
Real number ( 2147483648 to *2
precision) DINTDP S D
2147483647)

*1: The number of basic steps is two for the Universal model QCPU and LCPU only.
*2: The subset is effective only with Universal model QCPU and LCPU.

2-22
 Table 2.12 Data Conversion Instructions (Continued)

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition
2

BIN
DBL DBL S D Conversion 3
(S) (D+1, D) 3 - 6-89
16-bit DBLP DBLP S D BIN (-32768 to 32767)

32-bit WORD WORD S D Conversion 4

(S+1, S) (D) 3 - 6-90
conversion
WORDP WORDP S D BIN (-32768 to 32767)

GRY GRY S D Conversion to gray code

(S) (D)
4
3 -
BIN
GRYP GRYP S D BIN (-32768 to 32767)
6-91
Gray code DGRY DGRY S D Conversion to gray code
(S+1, S) (D+1, D)
6
conversions 3 -
DGRYP BIN (-2147483648 to
DGRYP S D
2147483647)

GBIN GBIN S D Conversion to BIN data

7
Gray code
(S) (D) 3 -
GBINP GBINP S D Gray code (-32768 to 32767)

BIN DGBIN DGBIN S D Conversion to BIN data

6-93 8
conversions (S+1, S) (D+1, D)
3 -
DGBINP DGBINP S D Gray code (-2147483648 to
2147483647)

NEG NEG D (D) (D)

2.4.3 Data conversion instructions

2.4 Basic instructions
2 -
BIN data
NEGP NEGP D
6-95
DNEG DNEG D (D+1, D) (D+1, D)
2 -
BIN data
DNEGP DNEGP D
Complement
to 2
ENEG ENEG D
(D+1, D) (D+1, D)
2 - 6-97
Real number data
ENEGP ENEGP D

EDNEG EDNEG D
(D+3, D+2, D+1, D) (D+3, D+2, D+1, D)
3 - 6-98
EDNEGP Real number data
EDNEGP D

BKBCD BKBCD S D n • Batch converts BIN data n points from (S)

to BCD data and stores the result from (D) 4 - 6-99
BKBCDP BKBCDP S D n onward.
Block
conversion
BKBIN BKBIN S D n • Batch converts BCD data n points from (S)
to BIN data and stores the result from (D) 4 - 6-101
BKBINP BKBINP S D n onward.

Floating-point ECON
ECON S D
Single precision Conversion to double precision
(S+1, S) (D+3, D+2, D+1, D) 3 - 6-103
ECONP ECONP S D 32-bit floating-point real number
Double precision
Floating-point EDCON
EDCON S D
Double precision Conversion to single precision
(S+3, S+2, S+1, S) (D+1, D) 3 - 6-105
EDCONP EDCONP S D 64-bit floating-point real number
Single precision

2-23
 2.4.4 Data transfer instructions

Table 2.13 Data Transfer Instructions

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

MOV MOV S D
16-bit data
(S) ( D) *1
transfer
MOVP MOVP S D
6-107
DMOV DMOV S D
32-bit data
(S+1,S) (D+1,D) *2
transfer
DMOVP DMOVP S D

Floating
EMOV EMOV S D
decimal
point data (S+1, S) (D+1, D) *2 6-109
transfer Real number data *3
EMOVP EMOVP S D
(Single
precision)
Floating
decimal EDMOV EDMOV S D
point data (S+3, S+2, S+1, S) (D+3, D+2, D+1, D)
2 6-111
transfer Real number data *3
(Double EDMOVP EDMOVP S D
precision)

Character $MOV $MOV S D

• Transfers character string designated by
string data 3 - 6-113
(S) to device designated by (D) onward.
transfer $MOVP $MOVP S D

16-bit data CML CML S D

negation (S) (D) *1
transfer CMLP CMLP S D
6-115
32-bit data DCML DCML S D
negation (S+1,S) (D+1,D) *2

transfer DCMLP DCMLP S D

BMOV BMOV S D n (S) (D)

Block
4 6-118
transfer n
BMOVP BMOVP S D n

Identical 16- FMOV FMOV S D n (D)

bit data block (S) 4
n
transfers FMOVP FMOVP S D n
6-122
Identical 32- DFMOV DFMOV S D n (D+1,D)
bit data block (S+1,S) 4
n
transfers DFMOVP DFMOVP S D n

XCH XCH D1 D2
16-bit data
(D1) (D2) 3
exchange
XCHP XCHP D1 D2
6-125
DXCH DXCH D1 D2
32-bit data
(D1+1,D1) (D2+1,D2) 3
exchange
DXCHP DXCHP D1 D2

2-24
 Table 2.13 Data Transfer Instructions (Continued)

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition
2

Block data
BXCH BXCH S D n (S) (D) 3
4 - 6-129
exchange n
BXCHP BXCHP S D n

Exchange SWAP SWAP D

b15 to b8 b7 to b0 4
(S) 8 bits 8 bits
of upper
3 - 6-131
and lower
SWAPP b15 to b8 b7 to b0
bytes SWAPP D
(D) 8 bits 8 bits 4
*1: The number of steps may vary depending on the device and type of CPU module being used.

Component Device
Number of 6
Steps
• Word device: Internal device (except for file register ZR)

QCPU
• Bit device: Devices whose device Nos. are multiples of 16, whose digit
designation is K4, and which use no indexing.
2 7
LCPU • Constant: No limitations
Devices other than above 3 Note 1)
8
Note 1) The number of steps may increase due to the conditions described in Section 3.8.

*2: The number of steps may vary depending on the device and type of CPU module being used.

Number of

2.4.4 Data transfer instructions

2.4 Basic instructions
Component Device
Steps
• Word device: Internal device (except for file register ZR)
High Performance model QCPU • Bit device: Devices whose device Nos. are multiples of 16, whose
3
Process CPU digit designation is K8, and which use no indexing.
Redundant CPU • Constant: No limitations
Devices other than above 3 Note 1)
• Word device: Internal device (except for file register ZR)
• Bit device: Devices whose device Nos. are multiples of 16, whose digit
designation is K8, and which use no indexing. 2
Basic model QCPU • Constant: No limitations
(The number of steps is 3 when the above device + constant are used.)
Devices other than above 3 Note 1)
Universal model QCPU
All devices that can be used 2 Note 1)
LCPU

Note 1) The number of steps may increase due to the conditions described in Section 3.8.

2-25
 *3: The number of steps may vary depending on the device and type of CPU module being used.

Number of
Component Device
Steps
• Word device: Internal device (except for file register ZR)
• Bit device: Devices whose device Nos. are multiples of 16, whose digit
QCPU 2
designation is K4, and which use no indexing.
LCPU • Constant: No limitations
Devices other than above 3 Note 1)

Note 1) The number of steps may increase due to the conditions described in Section 3.8.

2-26
 2.4.5 Program branch instructions
Table 2.14 Program Branch Instructions

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

3
• Jumps to Pn when input conditions are
CJ CJ Pn 2
met.
• Jumps to Pn from the scan after the
4
SCJ SCJ Pn 2 6-132
meeting of input condition.
Jump
JMP • Jumps unconditionally to Pn. 2
JMP Pn
4
• Jumps to END instruction when input
GOEND GOEND 1 - 6-135
condition is met.

6
2.4.6 Program execution control instructions
Table 2.15 Program Execution Control Instructions
7

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

Disable • Prohibits the running of an interrupt

2.4.5 Program branch instructions

2.4 Basic instructions
DI DI 1 -
interrupts program.
Enable • Resets interrupt program execution
EI EI 1 -
interrupts prohibition.
6-136
Interrupt
disable/ • Inhibits or permits interrupts for each
IMASK IMASK S 2 -
enable interrupt program.
setting
• Returns to sequence program from an
Return IRET IRET 1 - 6-143
interrupt program.

2.4.7 I/O refresh instructions

Table 2.16 I/O Refresh Instructions
Number of Basic Steps

See for Description

Instruction Symbol

Subset

Execution
Category Symbol Processing Details
Condition

RFS RFS S n
I/O • Refreshes the relevant I/O area during
3 - 6-145
Refresh scan.
RFSP RFSP S n

2-27
 2.4.8 Other convenient instructions

Table 2.17 Other convenient instructions

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

(S)+0
(S)+1 Up Down Up
UDCNT1 UDCNT1 S D n Present Cn value 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 -1 -2 -3 -2 -1 0
4 - 6-147
Cn contact

Up/Down
counter (S)+0
(S)+1
UDCNT2 UDCNT2 S D n Present Cn value 0 1 2 3 4 5 4 3 2 1 0 -1
4 - 6-150
Cn contact

(Time that TTMR is ON) n (D)

Teaching
TTMR TTMR D n 3 - 6-153
timer
n=0:1, n=1:10, n=2:100
• The 4 points from the bit device
designated by (D) operate as shown
below, depending on the ON/OFF
status of the input conditions for the
STMR instruction:
Special
STMR STMR S n D (D)+0: Off delay timer output 3 - 6-155
timer
(D)+1: One shot after off timer output
(D)+2: One shot after on timer output
(D)+3: On delay and off delay timer
output
• Rotates a rotary table with n1 divisions
Shortest
from the stop position to the position
direction ROTC ROTC S n1 n2 D 5 - 6-158
designated by (S+1) in the shortest
control
direction.
Ramp • Changes device data designated by D1
RAMP RAMP n1 n2 D1 n3 D2 6 - 6-161
signal from n1 to n2 in n3 scans.
• Counts the pulse input from the device
Pulse designated by (S) for the duration of
SPD SPD S n D 4 - 6-164
density time designated by n, and stores the
count in the device designated by (D).
Pulse (n1)Hz (D)
PLSY PLSY n1 n2 D 4 - 6-166
output Output n2 times

Pulse n1
width PWM PWM n1 n2 D n2 4 - 6-168
modulation
(D)

• Reads data of 16 points n rows from

the devices starting from the one
Matrix
MTR MTR S D1 D2 n specified by (S), and stores them to the 5 - 6-170
input
devices starting from the one specified
by (D2).

2-28
 2.5 Application Instructions
1
2.5.1 Logical operation instructions
Table 2.18 Logical Operation Instructions 2

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

4
WAND WAND S D

WANDP WANDP S D
(D) (S) (D) 3 7-3
2
WAND WAND S1 S2 D
4
WANDP WANDP S1 S2 D
(S1) (S2) (D)
*1
7-6
6
DAND DAND S D
Logical
product
DANDP DANDP S D
(D+1,D) (S+1,S) (D+1,D) *2 7-3
7
DAND DAND S1 S2 D

DANDP DANDP S1 S2 D
(S1+1,S1) (S2+1,S2) (D+1,D) *3 7-6
8
BKAND BKAND S1 S2 D n (S1) (S2) (D)
5 - 7-9
BKANDP n
BKANDP S1 S2 D n

2.5.1 Logical operation instructions

2.5 Application Instructions
WOR WOR S D
(D) (S) (D) 3 7-11
WORP WORP S D

WOR WOR S1 S2 D
4
(S1) (S2) (D) 7-14
*1
WORP WORP S1 S2 D

DOR DOR S D
Logical
(D+1,D) (S+1,S) (D+1,D) *2 7-11
sum
DORP DORP S D

DOR DOR S1 S2 D
(S1+1,S1) (S2+1,S2) (D+1,D) *3 7-14
DORP DORP S1 S2 D

BKOR BKOR S1 S2 D n (S1) (S2) (D)

5 - 7-17
BKORP n
BKORP S1 S2 D n

WXOR WXOR S D
(D) (S) (D) 3 7-19
WXORP WXORP S D

WXOR WXOR S1 S2 D
Exclusive 4
(S1) (S2) (D) 7-22
OR *1
WXORP WXORP S1 S2 D

DXOR DXOR S D
(D+1,D) (S+1,S) (D+1,D) *2 7-19
DXORP DXORP S D

2-29
 Table 2.18 Logical Operation Instructions (Continued)

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

DXOR DXOR S1 S2 D
(S1+1,S1) (S2+1,S2) (D+1,D) *3 7-22
DXORP DXORP S1 S2 D
Exclusive
OR
BKXOR BKXOR S1 S2 D n (S1) (S2) (D)
5 - 7-25
BKXORP n
BKXORP S1 S2 D n

WXNR WXNR S D
(D) (S) (D) 3 7-27
WXNRP WXNRP S D

WXNR WXNR S1 S2 D
4
(S1) (S2) (D) 7-30
*1
WXNRP WXNRP S1 S2 D
NON
DXNR DXNR S D
exclusive
(D+1,D) (S+1,S) (D+1,D) *2 7-27
logical
DXNRP DXNRP S D
sum
DXNR DXNR S1 S2 D
(S1+1,S1) (S2+1,S2) (D+1,D) *3 7-30
DXNRP DXNRP S1 S2 D

BKXNR BKXNR S1 S2 D n (S1) (S2) (D)

5 - 7-33
BKXNRP n
BKXNRP S1 S2 D n

2-30
 *1: The number of basic steps is three for the Universal model QCPU and LCPU only.
*2: The number of steps may vary depending on the device and type of CPU module being used.

Component Device
Number of 1
Steps
• Word device: Internal device (except for file register ZR)
High Performance model QCPU • Bit device: Devices whose device Nos. are multiples of 16, whose digit
designation is K8, and which use no indexing.
5 Note 1) 2
Process CPU
Redundant CPU • Constant: No limitations
Devices other than above 3 Note 2)
Basic model QCPU
4
Universal model QCPU All devices that can be used 3 Note 2)
LCPU

Note 1) When using a High Performance model QCPU, Process CPU or Redundant CPU,
4
the number of steps increases but the processing speed becomes faster.
Note 2) The number of steps may increase due to the conditions described in Section 3.8.
2
*3: The number of steps may vary depending on the device and type of CPU module being used.

Number of
Component Device
Steps
6
• Word device: Internal device (except for file register ZR)
High Performance model QCPU • Bit device: Devices whose device Nos. are multiples of 16, whose digit
Process CPU designation is K8, and which use no indexing.
6 Note 1)
7
Redundant CPU • Constant: No limitations
Devices other than above 4 Note 2)
Basic model QCPU 4 Note 2) 8
Universal model QCPU All devices that can be used
3 Note 2)
LCPU

Note 1) When using a High Performance model QCPU, Process CPU or Redundant CPU,
the number of steps increases but the processing speed becomes faster.

2.5.1 Logical operation instructions

2.5 Application Instructions
Note 2) The number of steps may increase due to the conditions described in Section 3.8.

2-31
 2.5.2 Rotation instructions

Table 2.19 Rotation Instructions

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

ROR ROR D n b15 (D) b0 SM700

3
RORP RORP D n Right rotation by n bits Carry flag
Right
7-35
rotation
RCR RCR D n b15 (D) b0 SM700
3
RCRP RCRP D n Right rotation by n bits Carry flag

ROL ROL D n SM700 b15 (D) b0

3
ROLP ROLP D n Carry flag Left rotation by n bits
Left
7-38
rotation
RCL RCL D n SM700 b15 (D) b0
3
RCLP RCLP D n Carry flag Left rotation by n bits

DROR DROR D n (D+1) (D)

b31 to b16 b15 to b0 SM700
3
DRORP DRORP D n
Right Right rotation by n bits Carry flag
7-41
rotation
DRCR DRCR D n (D+1) (D)
b31 to b16 b15 to b0 SM700
3
DRCRP DRCRP D n
Right rotation by n bits Carry flag

DROL DROL D n (D+1) (D)

SM700 b31 to b16 b15 to b0
3
DROLP DROLP D n
Left Carry flag Left rotation by n bits
7-44
rotation
DRCL DRCL D n (D+1) (D)
SM700 b31 to b16 b15 to b0
3
DRCLP DRCLP D n
Carry flag Left rotation by n bits

2-32
 2.5.3 Shift instructions
Table 2.20 Shift Instructions 1

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

4
SFR SFR D n b15 bn b0
Carry flag 3 4
SFRP SFRP D n b15 b0 SM700
n-bit shift
0 to 0
of 16-bit 7-46
data SFL SFL D n b15 bn b0 2
3
Carry flag
SFLP SFLP D n SM700 b15 b0
0 to 0

n
6
BSFR BSFR D n
(D)
Carry flag 3 -

1-bit shift BSFRP BSFRP D n

0
SM700 7
of n-bit 7-49
data n
BSFL BSFL D n

Carry flag
(D)
3 - 8
BSFLP BSFLP D n SM700
0

SFTBR SFTBR D n1 n2 n1
n2

2.5.3 Shift instructions

2.5 Application Instructions
(D) 4 -
Carry flag
SFTBRP SFTRP D n1 n2
n-bit shift SM700
of n-bit 0 0
7-51
data n1
SFTBL SFTBL D n1 n2
n2
(D)
Carry flag
4 -
SFTBLP SFTBLP D n1 n2 SM700
0 0

n
DSFR DSFR D n
(D)
3
1-word DSFRP DSFRP D n
shift of 0
7-54
n-words n
DSFL DSFL D n
data
(D)
3
DSFLP DSFLP D n
0
n1
SFTWR SFTWR D n1 n2 n2

(D) 4 -
n-words SFTWRP SFTWRP D n1 n2
shift of 0 0
7-56
n-words n1
SFTWL SFTWL D n1 n2
data n2
(D)
4 -
SFTWLP SFTWLP D n1 n2
0 0

2-33
 2.5.4 Bit processing instructions
Table 2.21 Bit Processing Instructions

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

BSET BSET D n (D)

b15 bn b0
3
BSETP BSETP D n
Bit 1
7-59
set/reset
BRST BRST D n (D)
b15 bn b0
3
BRSTP BRSTP D n 0

TEST (S1)
TEST S1 S2 D b15 to b0 (D)
4 -
TESTP TESTP S1 S2 D Bit designated by (S2)
Bit tests 7-61
DTEST DTEST S1 S2 D (S1)
b31 to b0 (D)
4 -
DTESTP DTESTP S1 S2 D
Bit designated by (S2)

BKRST (D) ON (D) OFF

Batch BKRST D n OFF OFF
Reset n
reset of bit 3 - 7-64
devices BKRSTP ON OFF
BKRSTP D n
ON OFF

2-34
 2.5.5 Data processing instructions
1
Table 2.22 Data Processing Instructions

Number of Basic Steps

2

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition
4
(S2)
SER SER S1 S2 D n (S1)
n 4
5 -
(D): Match No.
SERP SERP S1 S2 D n (D + 1): Number of matches
Data
searches 32 bits
7-66 2
DSER DSER S1 S2 D n (S2)
(S1)
n
5 -
DSERP DSERP S1 S2 D n
(D): Match No.
(D + 1): Number of matches
6
SUM SUM S D (S)
7
b15 b0
3
SUMP SUMP S D (D): Number of 1s
Bit checks 7-69
DSUM DSUM S D (S + 1) (S)
3 8
DSUMP DSUMP S D (D): Number of 1s

DECO DECO S D n Decode from 8 to 256

(D)
Decode (S) Decode 4 - 7-71
DECOP DECOP S D n n 2n bits

2.5.5 Data processing instructions

2.5 Application Instructions
ENCO ENCO S D n Decode from 256 to 8
(S)
Encode Encode (D) 4 - 7-73
n
ENCOP ENCOP S D n 2 bits n

7-seg- SEG SEG S D to 0

ment (S) (D) 3 7-75
decode SEGP 7SEG
SEGP S D

2-35
 Table 2.22 Data Processing Instructions (Continued)

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

DIS DIS S D n • Separates 16-bit data designated by (S)

into 4-bit units, and stores at the lower 4 4 - 7-77
DISP DISP S D n bits of n points from (D). (n 4)

UNI UNI S D n • Links the lower 4 bits of n points from the

device designated by (S) and stores at the 4 - 7-79
UNIP UNIP S D n device designated by (D). (n 4)

• Separates the data in the devices starting

NDIS NDIS S1 D S2 from the one specified by (S1) into bits
specified by the devices from (S2), and
NDISP stores them to the devices starting from the
NDISP S1 D S2
one specified by (D).
Separating 4 - 7-81
• Links the data in the devices starting from
and linking NUNI NUNI S1 D S2 the one specified by (S1) with bits specified
by the devices from (S2), and stores them
NUNIP to the devices starting from the one
NUNIP S1 D S2
specified by (D).

WTOB • Breaks n points of 16-bit data from the

WTOB S D n
device designated by (S) into 8-bit units,
and stores in sequence at the device
WTOBP WTOBP S D n designated by (D).
4 - 7-85
BTOW • Links the lower 8 bits of 16-bit data of n
BTOW S D n
points from the device designated by (S)
into 16-bit units, and stores in sequence at
BTOWP BTOWP S D n the device designated by (D).

MAX • Searches the data of n points from the

MAX S D n
device designated by (S) in 16-bit units,
7-89
and stores the maximum value at the
MAXP MAXP S D n device designated by (D).
4 -
MIN • Searches the data of n points from the
MIN S D n
device designated by (S) in 16-bit units,
7-92
and stores the minimum value at the
MINP MINP S D n device designated by (D).
Search
DMAX • Searches the data of 2n points from the
DMAX S D n
device designated by (S) in 32-bit units,
7-89
and stores the maximum value at the
DMAXP DMAXP S D n device designated by (D).
4 -
DMIN • Searches the data of 2n points from the
DMIN S D n
device designated by (S) in 32-bit units,
7-92
and stores the minimum value at the
DMINP DMINP S D n device designated by (D).

2-36
 Table 2.22 Data Processing Instructions (Continued)

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition
2

SORT S1 n S2 D1 D2
• Sorts data of n points from device
4
· S2: Number of comparisons to be
SORT made during a single run designated by (S1) in 16-bit units.
· D1: Device to be turned ON at the
completion of sort (n x (n-1)/2 scans required)
· D2: For system use 4
Sort 6 - 7-95
DSORT S1 n S2 D1 D2
· S2: Number of comparisons to be • Sorts data of 2n points from device
DSORT made during a single run
· D1: Device to be turned ON at the
designated by (S1) in 32-bit units.
(n x (n-1)/2 scans required)
2
completion of sort
· D2: For system use

WSUM WSUM S D n • Adds 16 bit BIN data of n points from the 6

device specified by (S), and stores it in 7-99
WSUMP WSUMP S D n the device specified by (D).
Total value
calculations
4 -
7
DWSUM DWSUM S D n • Adds 32 bit BIN data of n points from the
device specified by (S), and stores it in 7-101
the device specified by (D).
DWSUMP DWSUMP S D n
8
• Calculates the mean of n-point devices
MEAN MEAN S D n
(in 16-bit units) starting from the device
specified by (S), and then stores the
MEANP MEANP S D n
Calculation result into the device specified by (D).
4 -

2.5.5 Data processing instructions

2.5 Application Instructions
7-103
of averages • Calculates the mean of n-point devices
DMEAN DMEAN S D n
(in 32-bit units) starting from the device
specified by (S), and then stores the
DMEANP DMEANP S D n result into the device specified by (D).

2-37
 2.5.6 Structure creation instructions

Table 2.23 Structure Creation Instructions

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

FOR FOR n 2 -
• Executes n times between the FOR
7-105
NEXT and NEXT . 1 -
NEXT
Number of
repeats
BREAK BREAK D Pn
• Forcibly ends the execution of the FOR
3 - 7-108
BREAKP to NEXT cycle and jumps pointer Pn.
BREAKP D Pn

CALL Pn
CALL
• Executes subroutine program Pn when *1
CALL Pn S1 Sn
input condition is met. (S1 to Sn are 2
7-110
arguments sent to subroutine program. + *3
CALLP Pn
n 5) n
CALLP
CALLP Pn S1 Sn

RET RET • Returns from subroutine program 1 - 7-115

FCALL Pn
FCALL • Performs non-execution processing of *1

Subroutine FCALL Pn S1 Sn subroutine program Pn if input 2

program conditions have not been met. (S1 to + - 7-116
calls FCALLP Pn Sn are arguments sent to subroutine n
FCALLP program. n 5)
FCALLP Pn Sn S1

ECALL Pn

ECALL ECALL Pn S1 Sn • Executes subroutine program Pn from *2

: File name within designated program name when 3

input condition is met. (S1 to Sn are + - 7-120
ECALLP arguments sent to subroutine program. n

ECALLP
n 5)
ECALLP Pn S1 Sn

: File name

*1: n indicates number of arguments for subroutine program.

*2: n indicates the total of the number of arguments used in the subroutine program and the number of program
name steps. The number of program name steps is calculated as "number of characters in the program/2"
(decimal fraction is rounded up).
*3: The subset is effective only with the Universal model QCPU and LCPU.

2-38
 Table 2.23 Structure Creation Instructions (Continued)

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition
2

EFCALL Pn 4
EFCALL • Performs non-execution processing of *2
EFCALL Pn S1toSn
subroutine program Pn if input 3
:File name
conditions have not been met. (S1 to + - 7-125 4
EFCALLP Pn Sn are arguments sent to subroutine n

EFCALLP program. N 5)
Subroutine
program
EFCALLP Pn S1toSn
2
:File name
calls
• Executes subroutine program Pn when
input condition is met.
• Performs non-execution processing of
*1 6
2
XCALL XCALL Pn S1 Sn subroutine program Pn if input - 7-129
+
conditions have not been met. (S1 to
Sn are arguments sent to subroutine
n
7
program. N 5)
• Performs auto refresh of intelligent

COM COM
function modules, link refresh, auto
1 - 7-134 8
refresh of CPU shared memory, and
communications with peripherals.
Select
• Performs auto refresh of intelligent
refresh CCOM CCOM 1 - 7-142
function modules, auto refresh of CPU
shared memory, and communications

2.5.6 Structure creation instructions

2.5 Application Instructions
COM CCOMP with peripherals after the input 1 - 7-137
conditions are met.

IX IX S 2 -
• Perform indexing for individual devices
Device indexing ladder 7-143
used in device indexing ladder.
IXEND
IXEND 1 -

Fixed
indexing
IXDEV IXDEV 1 -
• Stores indexing value used for indexing
IXSET S D performed between the IX and IXEND 7-147
IXSET to the device designated by D or later. 3 -
Designates indexing value.

*1: n indicates number of arguments for subroutine program.

*2: n indicates the total of the number of arguments used in the subroutine program and the number of program
name steps. The number of program name steps is calculated as "number of characters in the program/2"
(decimal fraction is rounded up).

2-39
 2.5.7 Data table operation instructions

Table 2.24 Data table Operation Instructions

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

FIFW (S) (D) Pointer Pointer + 1

FIFW S D
3 - 7-150
FIFWP FIFWP S D Device at
pointer + 1

(S) Pointer Pointer - 1 (D)

FIFR FIFR S D
3 - 7-152
FIFRP FIFRP S D

(S) Pointer Pointer - 1 (D)

FPOP FPOP S D
Data table 3 - 7-154
processing
FPOPP FPOPP S D
Device at pointer + 1

FDEL FDEL S D n (S) Pointer Pointer - 1 (D)

4 -
FDELP FDELP S D n
Designated by n
7-156
FINS FINS S D n (S) (D) Pointer Pointer + 1

4 -
FINSP FINSP S D n
Designated by n

2-40
 2.5.8 Buffer memory access instructions
1
Table 2.25 Buffer Memory Access Instructions

Number of Basic Steps

2

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition
4

FROM FROM n1 n2 D n3 • Reads data in 16-bit units from an

5 - 4
intelligent function module.
FROMP FROMP n1 n2 D n3
Data read 7-159
DFRO DFRO n1 n2 D n3 • Reads data in 32-bit units from an
5 - 2
intelligent function module.
DFROP DFROP n1 n2 D n3

TO TO n1 n2 S n3 • Writes data in 16-bit units to an

5 -
6
intelligent function module.
TOP TOP n1 n2 S n3
Data write 7-162
DTO DTO n1 n2 S n3 • Writes data in 32-bit units to an
5 -
7
intelligent function module.
DTOP DTOP n1 n2 S n3

8
2.5.9 Display instructions

Table 2.26 Display Instructions

2.5.8 Buffer memory access instructions

2.5 Application Instructions
Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

• Outputs ASCII code of 8 points (16

When SM701 is OFF
PR characters) from device designated by
PR S D
(S) to output module.
7-165
• Outputs ASCII code from device
ASCII When SM701 is ON
PR designated by (S) to 00H to output 3 -
print PR S D
module.
• Converts comments from device
PRC PRC S D designated by (S) to ASCII code and 7-168
outputs to output module.
• Resets annunciator and LED indicator
Reset LEDR LEDR 1 - 7-171
display.

2-41
 2.5.10 Debugging and failure diagnosis instructions

Table 2.27 Debugging and Failure Diagnosis Instructions

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

• The CHK instruction is executed when

CHKST is executable.
CHKST CHKST • Jumps to the step following the CHK
instruction when CHKST is in a
non-executable status.
1 - 7-174
• During normal conditions SM80 : OFF,
Checks CHK SD80 : 0
CHK
Check condition • During abnormal conditions SM80 : ON,
SD80 : Failure No.
• Starts update in ladder pattern being
CHKCIR CHKCIR
checked by the CHK instruction.
1 - 7-178
• Ends update in ladder pattern being
CHKEND CHKEND
checked by the CHK instruction.

2-42
 2.5.11 Character string processing instructions
1
Table 2.28 Character String Processing Instructions

Number of Basic Steps

2

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition
4
• Converts 1-word BIN value designated
BINDA BINDA S D
by (S) to a 5-digit, decimal ASCII value,
3 -
4
and stores it at the word device
BIN BINDAP BINDAP S D
designated by (D).

Decimal DBINDA DBINDA S D

• Converts 2-word BIN value designated 7-182
2
by (S) to a 10-digit, decimal ASCII value,
ASCII
and stores it at word devices following 3 -
DBINDAP DBINDAP S D the word device number designated by
(D). 6
• Converts 1-word BIN value designated
BINHA BINHA S D
by (S) to a 4-digit, hexadecimal ASCII
value, and stores it at a word device 3 - 7
BIN BINHAP BINHAP S D following the word device number
designated by (D).
7-185
• Converts 2-word BIN value designated
Hexadecimal
ASCII
DBINHA DBINHA S D
by (S) to an 8-digit, hexadecimal ASCII
8
value, and stores it at word devices 3 -
DBINHAP DBINHAP S D following the word device number
designated by (D).
• Converts 1-word BCD value designated

2.5.11 Character string processing instructions

2.5 Application Instructions
BCDDA BCDDA S D
by (S) to a 4-digit, decimal ASCII value,
and stores it at a word device following 3 -
BCD BCDDAP BCDDAP S D the word device number designated by
(D).
7-188
Decimal • Converts 2-word BCD value designated
DBCDDA DBCDDA S D
ASCII by (S) to an 8-digit, decimal ASCII value,
and stores it at word devices following 3 -
DBCDDAP DBCDDAP S D the word device number designated by
(D).
• Converts a 5-digit, decimal ASCII value
DABIN DABIN S D
designated by (S) to a 1-word BIN value,
3 -
Decimal and stores it at a word device number
DABINP DABINP S D
ASCII designated by (D).
7-191
• Converts a 10-digit, decimal ASCII value
DDABIN DDABIN S D
BIN designated by (S) to a 2-word BIN value,
3 -
and stores it at a word device number
DDABINP DDABINP S D
designated by (D).

• Converts a 4-digit, hexadecimal ASCII

HABIN HABIN S D
value designated by (S) to a 1-word BIN
3 -
Hexadecimal value, and stores it at a word device
HABINP HABINP S D
ASCII number designated by (D).
7-194
• Converts an 8-digit, hexadecimal ASCII
DHABIN DHABIN S D
BIN designated by (S) value to a 2-word BIN
3 -
value, and stores it at a word device
DHABINP DHABINP S D
number designated by (D).

2-43
 Table 2.28 Character String Processing Instructions (Continued)

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

• Converts a 4-digit, decimal ASCII value

DABCD DABCD S D
designated by (S) to a 1-word BCD
Decimal 3 -
value, and stores it at a word device
DABCDP DABCDP S D
ASCII number designated by (D).
7-197
• Converts a 8-digit decimal ASCII value
DDABCD DDABCD S D
BCD designated by (S) to a 2-word BCD
3 -
value, and stores it at the word device
DDABCDP DDABCDP S D
number designated by (D).
Device
COMRD COMRD S D
comment • Stores comment from device designated
3 - 7-200
read by (S) at a device designated by (D).
COMRDP COMRDP S D
operation
• Stores data length (number of
Character LEN LEN S D
characters) in character string
string length 3 - 7-203
designated by (S) at a device designated
detection LENP LENP S D by (D).
• Converts a 1-word BIN value designated
STR STR S1 S2 D by (S2) to a decimal character string with
the total number of digits and the
4 -
BIN number of decimal fraction digits
STRP STRP S1 S2 D designated by (S1) and stores them at a
device designated by (D).
Decimal 7-205
• Converts a 2-word BIN value designated
character DSTR DSTR S1 S2 D by (S2) to a decimal character string with
string the total number of digits and the
4 -
number of decimal fraction digits
DSTRP DSTRP S1 S2 D designated by (S1) and stores them at a
device designated by (D).
• Converts a character string including
VAL VAL S D1 D2 decimal point designated by (S) to a
Decimal 1-word BIN value and the number of 4 -
VALP decimal fraction digits, and stores them
character VALP S D1 D2
into devices designated by (D1) and (D2).
string 7-211
• Converts a character string including
DVAL DVAL S D1 D2 decimal point designated by (S) to a
BIN 2-word BIN value and the number of 4 -
DVALP DVALP S D1 D2 decimal fraction digits, and stores them
into devices designated by (D1) and (D2).

Floating
ESTR ESTR S1 S2 D • Converts the 32-bit floating decimal point
decimal point
data designated by (S) to a character
4 - 7-216
string, and stores it in devices
Character designated by (D).
ESTRP ESTRP S1 S2 D
string

Character
EVAL EVAL S D • Converts the character string designated
string
by (S) to a 32-bit floating decimal point
3 - 7-223
data, and stores it in devices designated
Floating by (D).
EVALP EVALP S D
decimal point

2-44
 Table 2.28 Character String Processing Instructions (Continued)

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition
2

Hexadecimal
ASC ASC S D n
• Converts the 1-word BIN value at the
device numbers designated by (S) to
4
BIN
hexadecimal ASCII, and stores n 4 - 7-227
ASCP ASCP S D n characters of them at the device numbers
ASCII designated by (D) and after. 4
ASCII • Converts n hexadecimal ASCII
HEX HEX S D n characters of the device numbers
designated by (S) and after to BIN 4 - 7-229
Hexadecimal
HEXP HEXP S D n
values, and stores them at the device 2
BIN numbers designated by (D).

RIGHT RIGHT S D n • Stores n characters from the end of a

character string designated by (S) at the 6
RIGHTP RIGHTP S D n device designated by (D).
4 - 7-231
LEFT LEFT S D n • Stores n characters from the beginning
of a character string designated by (S) at
7
LEFTP LEFTP S D n the device designated by (D).

MIDR MIDR S1 D S2
• Stores the designated number of
characters in the character string
8
designated by (S1) from the position
MIDRP MIDRP S1 D S2 designated by (S2) at the device
designated by (D). 4 - 7-234
Character

2.5.11 Character string processing instructions

2.5 Application Instructions
MIDW MIDW S1 D S2 • Stores the character string of (S1) in the
string specified number to the character string
MIDWP MIDWP S1 D S2 of (D) at the position specified by (S2).

INSTR INSTR S1 S2 D n • Searches character string (S1) from the

nth character of character string (S2), 5 - 7-238
INSTRP INSTRP S1 S2 D n and stores matched positions at (D).

STRINS • Inserts the character string data

STRINS S D n
specified by (S) to the (n)th character
4 - 7-240
(insert position) from the initial character
STRINSP STRINSP S D n
string data specified by (D).

STRDEL STRDEL D n1 n2 • Deletes the (n2) characters data

specified by (D) starting from the 4 - 7-242
STRDELP STRDELP D n1 n2 device(insert position) specified by n1.

• Converts 32-bit floating decimal point

Floating EMOD EMOD S1 S2 D
data (S1) to BCD data with number of
decimal point
decimal fraction digits designated by 4 - 7-244
(S2) , and stores at device designated
BCD EMODP EMODP S1 S2 D
by (D).

• Converts BCD data (S1) to 32-bit

BCD EREXP EREXP S1 S2 D
floating decimal point data with the
number of decimal fraction digits 4 - 7-247
Floating
designated by (S2), and stores at device
decimal point EREXPP EREXPP S1 S2 D
designated by (D).

2-45
 2.5.12 Special function instructions

Table 2.29 Special Function Instructions

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

SIN SIN S D
Sin (S+1,S) (D+1,D) 3 - 7-249
SINP SINP S D

COS COS S D
Cos(S+1,S) (D+1,D) 3 - 7-253
COSP COSP S D

TAN TAN S D
Trigonometric 3 - 7-257
Tan(S+1,S) (D+1,D)
functions TANP TANP S D
(Floating-
point single- ASIN ASIN S D
precision) Sin -1 (S+1,S) (D+1,D) 3 - 7-261
ASINP ASINP S D

ACOS ACOS S D
Cos-1(S+1,S) (D+1,D) 3 - 7-266
ACOSP ACOSP S D

ATAN ATAN S D
Tan-1(S+1,S) (D+1,D) 3 - 7-270
ATANP ATANP S D

SIND SIND S D
Sin(S+3, S+2, S+1, S) 3 - 7-251
(D+3, D+2, D+1, D)
SINDP SINDP S D

COSD COSD S D
Cos(S+3, S+2, S+1, S) 3 - 7-255
(D+3, D+2, D+1, D)
COSDP COSDP S D

TAND TAND S D
Trigonometric Tan(S+3, S+2, S+1, S) 3 - 7-259
functions (D+3, D+2, D+1, D)
TANDP TANDP S D
(Floating-
point double- ASIND ASIND S D -1
Sin (S+3, S+2, S+1, S) 3 - 7-264
precision) (D+3, D+2, D+1, D)
ASINDP ASINDP S D

ACOSD ACOSD S D -1
Cos (S+3, S+2, S+1, S) 3 - 7-268
(D+3, D+2, D+1, D)
ACOSDP ACOSDP S D

ATAND ATAND S D -1
Tan (S+3, S+2, S+1, S) 3 - 7-272
(D+3, D+2, D+1, D)
ATANDP ATANDP S D

2-46
 Table 2.29 Special Function Instructions (Continued)

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition
2

RAD RAD S D (S+1, S) (D+1, D)

4
3 - 7-274
Conversion from angles to radians
RADP RADP S D

RADD RADD S D
(S+3, S+2, S+1, S) (D+3, D+2, D+1, D)
4
Angles 3 - 7-276
RADDP RADDP S D Conversion from angle to radian

Radians DEG DEG S D

(S+1, S) (D+1, D)
2
conversion 3 - 7-278
Conversion from radians to angles
DEGP DEGP S D

DEGD DEGD S D
(S+3, S+2, S+1, S) (D+3, D+2, D+1, D)
6
3 - 7-280
DEGDP DEGDP S D Conversion from radian to angle

SQR SQR S D 7
(S+1,S) (D+1,D) 3 - 7-286
SQRP SQRP S D
Square root
SQRD SQRD S D 8
(S+3, S+2, S+1, S) (D+3, D+2, D+1, D) 3 - 7-288
SQRDP SQRDP S D

EXP EXP S D
e(S+1,S) (D+1,D) 3 - 7-290

2.5.12 Special function instructions

2.5 Application Instructions
EXPP EXPP S D
Exponent
operations
EXPD EXPD S D
e(S+3, S+2, S+1, S) (D+3, D+2, D+1, D) 3 - 7-293
EXPDP EXPDP S D

LOG LOG S D
Loge (S+1,S) (D+1,D) 3 - 7-295
LOGP LOGP S D
Natural
logarithms
LOGD LOGD S D
Loge(S+3, S+2, S+1, S) (D+3, D+2, D+1, D) 3 - 7-297
LOGDP LOGDP S D

POW POW S1 S2 D
(S2+1,S2)
• (S1+1,S1) (D+1,D) 4 - 7-299
POWP POWP S1 S2 D
Expone
ntiation
POWD POWD S1 S2 D
(S2+3,S2+2,S2+1,S2)
• (S1+3,S1+2,S1+1,S1) (D+3,D+2,D+1,D) 4 - 7-301
POWDP POWDP S1 S2 D

LOG10 LOG10P
LOG10 S D
• log10(S+1,S) (D+1,D) 3 - 7-299
LOG10P LOG10P S D
Common
logarithm
LOG10D LOG10D S D
• log10(S+3,S+2S+1,S) (D+3,D+2,D+1,D) 3 - 7-301
LOG10DP LOG10DP S D

2-47
 Table 2.29 Special Function Instructions (Continued)

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

Random RND RND D • Generates a random number (from 0 to

number less than 32767) and stores it at the
generation RNDP RNDP D device designated by (D).
2 - 7-303
Random SRND SRND D • Updates random number series
number according to the 16-bit BIN data stored
series update SRNDP SRNDP D in the device designated by (S).

BSQR BSQR S D
(S) (D)+0 Integer part
3 -
+1 Decimal fraction part
BSQRP BSQRP S D
Square root 7-305
BDSQR BDSQR S D (S+1, S) (D)+0 Integer part
+1 Decimal fraction part
3 -
BDSQRP BDSQRP S D

BSIN BSIN S D Sin(S) (D)+0 Sign

+1 Integer part 3 - 7-308
BSINP BSINP S D +2 Decimal fraction part

BCOS BCOS S D Cos(S) (D)+0 Sign

+1 Integer part 3 - 7-310
BCOSP +2 Decimal fraction part
BCOSP S D

BTAN BTAN S D Tan(S) (D)+0 Sign

+1 Integer part 3 - 7-312
BTANP BTANP S D +2 Decimal fraction part
Trigonometric
functions
BASIN BASIN S D Sin -1 (S) (D)+0 Sign
+1 Integer part 3 - 7-314
BASINP BASINP S D +2 Decimal fraction part

BACOS BACOS S D Cos -1 (S) (D) +0 Sign

+1 Integer part 3 - 7-316
BACOSP BACOSP S D +2 Decimal fraction part

BATAN BATAN S D Tan -1 (S) (D) +0 Sign

+1 Integer part 3 - 7-318
BATANP BATANP S D +2 Decimal fraction part

2-48
 2.5.13 Data control instructions
1
Table 2.30 Data Control Instructions

Number of Basic Steps

2

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition
4

LIMIT LIMIT S1 S2 S3 D
• When (S3) (S1)
......... Stores value of (S1) at (D)
4
• When (S1) (S3) (S2)
5 -
......... Stores value of (S3) at (D)
LIMITP LIMITP S1 S2 S3 D • When (S2) (S3) 2
Upper and ......... Stores value of (S2) at (D)
lower
7-320
limit
controls DLIMIT DLIMIT S1 S2 S3 D
• When ((S3)+1, (S3)) ((S1)+1, S1) 6
.. Stores value of ((S1)+1, (S1)) at ((D)+1, (D))
• When ((S1)+1, (S1)) ((S3)+1, (S3))
(S2+1, S2) 5 -
.. Stores value of ((S3)+1, (S3)) at ((D)+1, (D)) 7
DLIMITP DLIMITP S1 S2 S3 D • When ((S2), (S2)+1) ((S3), (S3)+1)
.. Stores value of ((S2)+1, (S2)) at ((D)+1, (D))

BAND • When (S1) (S3) (S2)..............0 (D)

8
BAND S1 S2 S3 D
• When (S3) (S1)......... (S3) (S1) (D) 5 -
BANDP BANDP S1 S2 S3 D • When (S2) (S3)......... (S3) (S2) (D)

Dead
• When ((S1)+1, (S1)) ((S3)+1, (S3))

2.5.13 Data control instructions

2.5 Application Instructions
band DBAND DBAND S1 S2 S3 D 7-323
((S2)+1, (S2)) ................... 0 ((D)+1, (D))
controls
• When ((S3)+1, (S3)) ((S1)+1, (S1)) ........
5 -
((S3)+1, (S3)) ((S1)+1, (S1)) ((D)+1, (D))
• When ((S2)+1, (S2)) ((S3)+1, (S3)) .......
DBANDP DBANDP S1 S2 S3 D
((S3)+1, (S3)) ((S2)+1, (S2)) ((D)+1, (D))

ZONE ZONE S1 S2 S3 D • When (S3) 0 ................................ 0 (D)

• When (S3) 0 .................. (S3)+(S2) (D) 5 -
ZONEP ZONEP S1 S2 S3 D • When (S3) 0 .............. (S3) (S1) (D)

• When ((S3)+1, (S3)) 0

Zone DZONE .................................... 0 ((D)+1, (D))
DZONE S1 S2 S3 D 7-326
controls • When ((S3)+1, (S3)) 0
......... ((S3)+1, (S3))+((S2)+1, (S2))
5 -
((D)+1, (D))
• When ((S3)+1, (S3)) 0
DZONEP DZONEP S1 S2 S3 D ........ ((S3)+1, (S3)) + ((S1)+1, (S1))
((D)+1, (D))

2-49
 Table 2.30 Special Function Instructions (Continued)

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

• Executes scaling for the scaling

conversion data (16-bit data units)
SCL SCL S1 S2 D
specified by (S2) with the input value
specified by (S1), and then stores the
result into the device specified by (D). 4 -
The scaling conversion is executed
SCLP SCLP S1 S2 D based on the scaling conversion data
Point-by- stored in the device specified by (S2) an
point up.
7-329
coordinate • Executes scaling for the scaling
data conversion data (32-bit data units)
DSCL DSCL S1 S2 D
specified by (S2) with the input value
specified by (S1), and then stores the
result into the device specified by (D). 4 -
The scaling conversion is executed
DSCLP DSCLP S1 S2 D based on the scaling conversion data
stored in the device specified by (S2) an
up.
• Executes scaling for the scaling
conversion data (16-bit data units)
SCL2 SCL2 S1 S2 D
specified by (S2) with the input value
specified by (S1), and then stores the
result into the device specified by (D). 4 -
The scaling conversion is executed
SCL2P SCL2P S1 S2 D based on the scaling conversion data
stored in the device specified by (S2)
X or Y
and up.
coordinate 7-333
• Executes scaling for the scaling
data
conversion data (32-bit data units)
DSCL2 DSCL2 S1 S2 D
specified by (S2) with the input value
specified by (S1), and then stores the
result into the device specified by (D). 4 -
The scaling conversion is executed
DSCL2P DSCL2P S1 S2 D based on the scaling conversion data
stored in the device specified by (S2)
and up.

2-50
 2.5.14 Switching instructions
1
Table 2.31 Switching Instructions

Number of Basic Steps

2

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition
4

Block
number
RSET RSET S
• Converts extension file register block
2 - 7-336
4
number to number designated by (S).
switching RSETP RSETP S

QDRSET QDRSET File name

*1
2
2
• Sets file names used as file registers. - 7-338
+
QDRSETP QDRSETP File name n
File set
QCDSET QCDSET File name
*1 6
2
• Sets file names used as comment files. - 7-341
+
QCDSETP QCDSETP File name
n
7
*1: n ([number of file name characters] / 2) indicates a step. (Decimal fractions are rounded up.)

2.5.14 Switching instructions

2.5 Application Instructions

2-51
 2.5.15 Clock instructions

Table 2.32 Clock Instructions

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

DATERD (Clock elements) (D) +0 Year

DATERD D +1 Month
+2 Day
+3 Hour 2 - 7-343
+4 Minute
DATERDP DATERDP D +5 Sec.
Read/ +6 Day of the week
write clock
data (D) +0 Year (Clock elements)
DATEWR DATEWR S +1 Month
+2 Day
+3 Hour 2 - 7-345
+4 Minute
DATEWRP DATEWRP S +5 Sec.
+6 Day of the week

DATE+ DATE+ S1 S2 D (S1) (S2) (D)

Hour Hour Hour 4 - 7-347
Mitnute + Mitnute Mitnute
Clock data DATE+P DATE+P S1 S2 D Sec. Sec. Sec.
addition/
subtraction DATE- DATE- S1 S2 D (S1) (S2) (D)
Hour Hour Hour 4 - 7-349
Mitnute Mitnute Mitnute
DATE-P DATE-P S1 S2 D Sec. Sec. Sec.

SECOND SECOND S D (S) (D)

Hour Sec. (Lower 16 bits) 3 - 7-351
Minute Sec. (Upper 16 bits)
SECONDP SECONDP S D Sec.
Clock data
translation
HOUR HOUR S D (S) (D)
Sec. (Lower 16 bits) Hour 3 - 7-353
Sec. (Upper 16 bits) Mitnute
HOURP HOURP S D Sec.

2-52
 Table 2.32 Character String Processing Instructions (Continued)

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition
2

LDDT= DT S1 S2 n 4
S1 Year S2 Year
ANDDT= DT S1 S2 n Companson
S1 +1 Month S2 +1 Month 4 -
4
operation resuit
S1 +2 Day S2 +2 Day

ORDT=
DT S1 S2 n

LDDT<> DT S1 S2 n 2
S1 Year S2 Year
ANDDT<> DT S1 S2 n Companson
S1 +1 Month S2 +1 Month operation resuit
4 -
S1 +2 Day S2 +2 Day
6
ORDT<>
DT S1 S2 n

LDDT< DT S1 S2 n
7
S1 Year S2 Year
ANDDT< DT S1 S2 n Companson
S1 +1 Month S2 +1 Month operation resuit
4 -

ORDT<
S1 +2 Day S2 +2 Day
8
Date DT S1 S2 n
7-355
comparison
LDDT<= DT S1 S2 n

S1 Year S2 Year
ANDDT<= DT S1 S2 n

2.5.15 Clock instructions

2.5 Application Instructions
Companson
S1 +1 Month S2 +1 Month operation resuit
4 -
S1 +2 Day S2 +2 Day
ORDT<=
DT S1 S2 n

LDDT> DT S1 S2 n

S1 Year S2 Year
ANDDT> DT S1 S2 n Companson
S1 +1 Month S2 +1 Month operation resuit
4 -
S1 +2 Day S2 +2 Day
ORDT>
DT S1 S2 n

LDDT>= DT S1 S2 n

S1 Year S2 Year
ANDDT>= DT S1 S2 n Companson
S1 +1 Month S2 +1 Month operation resuit 4 -
S1 +2 Day S2 +2 Day

ORDT>=
DT S1 S2 n

2-53
 Table 2.32 Character String Processing Instructions (Continued)

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

LDTM= TM S1 S2 n

S1 Hour S2 Hour
ANDTM= TM S1 S2 n Companson
S1 +1 Minute S2 +1 Minute operation resuit 4 -
S1 +2 Second S2 +2 Second

ORTM=
TM S1 S2 n

LDTM<> TM S1 S2 n

S1 Hour S2 Hour
ANDTM<> TM S1 S2 n Companson
S1 +1 Minute S2 +1 Minute operation resuit 4 -
S1 +2 Second S2 +2 Second

ORTM<>
TM S1 S2 n

LDTM< TM S1 S2 n

S1 Hour S2 Hour
ANDTM< TM S1 S2 n Companson
S1 +1 Minute S2 +1 Minute operation resuit 4 -
S1 +2 Second S2 +2 Second

ORTM<
Clock TM S1 S2 n
7-360
comparison
LDTM<= TM S1 S2 n

S1 Hour S2 Hour
ANDTM<= TM S1 S2 n Companson
S1 +1 Minute S2 +1 Minute operation resuit 4 -
S1 +2 Second S2 +2 Second

ORTM<=
TM S1 S2 n

LDTM> TM S1 S2 n

S1 Hour S2 Hour
ANDTM> TM S1 S2 n Companson
S1 +1 Minute S2 +1 Minute operation resuit 4 -
S1 +2 Second S2 +2 Second

ORTM>
TM S1 S2 n

LDTM>= TM S1 S2 n

S1 Hour S2 Hour
ANDTM>= TM S1 S2 n Companson
S1 +1 Minute S2 +1 Minute operation resuit 4 -
S1 +2 Second S2 +2 Second

ORTM>=
TM S1 S2 n

2-54
 2.5.16 Expansion clock instruction
1
Table 2.33 Expansion clock instruction

Number of Basic Steps

2

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition
4

Reading
S.DAT-
S.DATERD D
(Clock elements) (D) +0
+1
Year
Month 4
ERD +2 Day
data of the +3 Hour
+4 6 - 7-365
expan- Minute
sion clock SP.DAT-
SP.DATERD D
+5 Sec.
+6 Day of the week 2
ERD +7 1/1000 sec.

(S1) (S2) (D)

S.DATE+ S.DATE+ S1 S2 D Hour Hour Hour 6
Minute Minute Minute
Adding or Sec. + Sec. Sec. 8 - 7-368
subtracting SP.DATE+ SP.DATE+ S1 S2 D 1/1000 sec. 1/1000 sec. 1/1000 sec.
data val-
ues of the
7
(S1) (S2) (D)
expansion S.DATE- S.DATE S1 S2 D Hour Hour Hour
clock Minute Minute Minute
8 - 7-371
SP.DATE- SP.DATE S1 S2 D
Sec. Sec. Sec.
8
1/1000 sec. 1/1000 sec. 1/1000 sec.

2.5.16 Expansion clock instruction

2.5 Application Instructions

2-55
 2.5.17 Program control instructions

Table 2.34 Program Control Instructions

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

*1
PSTOP PSTOP File name
• Places designated program in standby 2
- 7-376
status. +
PSTOPP PSTOPP File name n
*1
POFF POFF File name • Turns OUT instruction coil of designated
2
program OFF, and places program in - 7-377
+
POFFP POFFP File name standby status.
n
*1
PSCAN PSCAN File name
• Registers designated program as scan 2
- 7-379
Program execution type. +
PSCANP PSCANP File name
control n
instructions *1
PLOW PLOW File name
• Registers designated program as 2
- 7-381
low-speed execution type. +
PLOWP PLOWP File name
n

LDPCHK PCHK File name

• In conduction when program of specified *1

ANDPCHK PCHK File name file name is being executed. 2

- 7-383
• In non-conduction when program of +
specified file name is not executed. n
ORPCHK
PCHK File name

*1: n ([number of file name characters] / 2) indicates a step. (Decimal fractions are rounded up.)

2-56
 2.5.18 Other instructions
1
Table 2.35 Other Instructions

Number of Basic Steps

2

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition
4

WDT
WDT WDT
• Resets watchdog timer during sequence
1 - 7-385
4
reset program.
WDTP WDTP

Timing (D) 2
DUTY DUTY n1 n2 D n1 scans n2 scans 4 - 7-387
clock
SM420 to SM424, SM430 to SM434
• Turns ON device specified by (D) if 6
Time check TIMCHK TIMCHK S1 S2 D measured ON time of input condition is 4 - 7-389
longer than preset time continuously.

ZRRDB ZRRDB n D 0 Lower 8 bits ZR0 7

1 Upper 8 bits
2 Lower 8 bits ZR1 3 - 7-390
3 Upper 8 bits
ZRRDBP ZRRDBP n D
n 8 bits (D) 8
Direct read/
ZRWRB ZRWRB n S (S) 0 Lower 8 bits
write ZR0
1 Upper 8 bits
operations in 2 Lower 8 bits 3 - 7-392
ZR1
3 Upper 8 bits
1-byte units ZRWRBP ZRWRBP n S
n 8 bits

2.5.18 Other instructions

2.5 Application Instructions
ADRSET ADRSET S D (S) (D)
Indirect address of
3 - 7-394
designated device
ADRSETP ADRSETP S D Device name
• Takes in ASCII data for 8 points of input
Numerical
unit designated by (S), converts to
key input KEY KEY S n D1 D2 5 - 7-395
hexadecimal value following device
from keyboard
number designated by (D1), and stores.

Batch save ZPUSH ZPUSH D • Saves the contents of index registers to a

of index location starting from the device
register ZPUSHP ZPUSHP D designated by (D).
2 - 7-399
Batch ZPOP ZPOP D • Reads the data stored in the location
recovery of starting from the device designated by
index register ZPOPP ZPOPP D (D) to index registers.

• Reads the module information stored in

Reading UNIRD UNIRD n1 D n2 the area starting from the I/O No.
module infor- designated by n by the points designated 4 - 7-401
mation by n2, and stores it in the area starting
UNIRDP UNIRDP n1 D n2 from the device designated by (D).

2-57
 Table 2.35 Other Instructions (Continued)

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

• This instruction reads the module

TYPERD TYPERD n D information stored in the area starting from
Module model
the I/O number specified by "n", and stores 3 - 7-408
name read
TYPERDP TYPERDP n D it in the area starting from the device
specified by (D).
• Stores the trace data set with peripheral
device by the number of times set when
Trace set TRACE TRACE 1 - 7-413
SM800, SM801 and SM802 turn on, to
the sampling trace file.
• Resets the data set the TRACE
Trace rset TRACER TRACER 1 - 7-413
instruction.
Writing data to the
SP.FWRITE SP.FWRITE U0 S0 D0 S1 S2 D1 • Writes data to the designated file. 11 - 7-415
designated file
Reading data
from designated SP.FREAD SP.FREAD U0 S0 D0 S1 S2 D1 • Reads data from the designated file. 11 - 7-427
file
Writing data to • Writes data to the device data storage file in
S.DEVST SP.DEVST n1 S n2 D 9 - 7-439
standard ROM the standard ROM.

S.DEVLD S.DEVLD n1 D n2
Reading data from • Reads data from the device data storage file
8 - 7-441
standard ROM in the standard ROM.
SP.DEVLD SP.DEVLD n1 D n2
• Transfers the program stored in a
Loading program memory card or standard memory (other
PLOADP PLOADP S D 3 - 7-443
from memory than drive 0) to drive 0 and places the
program in standby status.
Unloading
• Deletes the standby program stored in
program from PUNLOADP PUNLOADP S D 3 - 7-446
standard memory (drive 0).
program memory
• Deletes standby program stored in
standard memory (drive 0) designated by
Load
(S1). Then, transfers the program stored
+ PSWAPP PSWAPP S1 S2 D 4 - 7-448
in a memory card or standard memory
Unload
(other than drive 0) designated by (S2) to
drive 0 and places it in standby status.

RBMOV • Transfers n points of 16-bit data from the

High-speed RBMOV S D n
device designated by (S) to the devices
block transfer of 4 - 7-451
of n points starting from the one
file register
RBMOVP designated by (D).
RBMOVP S D n

• Displays the specified character strings

User message UMSG UMSG S 2 - 7-456
on the display unit as a user message.

2-58
 2.6 Instructions for Data Link
1
2.6.1 Instructions for Network refresh
Table 2.36 Instructions for Network refresh
2

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

4
S.ZCOM S.ZCOM Jn

Link instruc- SP.ZCOM

2
SP.ZCOM Jn
tion: Net- Refreshes the designated network. 5 - 8-2
work refresh S.ZCOM S.ZCOM Un

SP.ZCOM
6
SP.ZCOM Un

7
2.6.2 Instructions for Reading/Writing Routing Information
Table 2.37 Instructions for Reading/Writing Routing Information 8

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

2.6.1 Instructions for Network refresh

2.6 Instructions for Data Link
Reading S.RTREAD S.RTREAD n D
routing Reads data set at routing parameters. 7 - 8-6
information SP.RTREAD SP.RTREAD n D
Registering S.RTWRITE S.RTWRITE n S Writes routing data to the area designated by
routing 8 - 8-8
routing parameters.
information SP.RTWRITE SP.RTWRITE n S

2-59
 2.7 Multiple CPU dedicated instruction

2.7.1 Instructions for Writing to the CPU Shared Memory of Host

CPU
Table 2.38 Instructions for Writing to the CPU Shared Memory of Host CPU

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

S. TO S.TO n1 n2 n3 n4 D • Writes device data of the host station to

5 - 9-4
the host CPU shared memory.
SP. TO SP.TO n1 n2 n3 n4 D

Write to host TO TO n1 n2 S n3 • Writes device data of the host station to

CPU shared 5 -
the host CPU shared memory.
memory TOP TOP n1 n2 S n3
9-7
DTO • Writes device data of the host station to
DTO n1 n2 S n3
the host CPU shared memory in 32-bit 5 -
DTOP DTOP n1 n2 S n3 units.

2.7.2 Instructions for Reading from the CPU Shared Memory of

Another CPU
Table 2.39 Instructions for Reading from the CPU Shared Memory of another CPU

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

FROM • Reads device data from the other CPU

FROM n1 n2 D n3
shared memories, and stores the data in 5 -
Read from other FROMP the host station.
FROMP n1 n2 D n3
CPU shared 9-12
memory DFRO DFRO n1 n2 D n3 • Reads device data from the other CPU
shared memories in 32-bit units, and 5 -
DFROP DFROP n1 n2 D n3 stores the data in the host station.

2-60
 2.8 Multiple CPU high-speed transmission dedicated
instruction 1

2.8.1 Instructions for Multiple CPU high-speed transmission 2

dedicated
Table 2.40 Multiple CPU high-speed transmission dedicated instruction
4

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

2
In multiple CPU system, data stored in a
D.DDWR D.DDWR n S1 S2 D1 D2 10 -
device specified by host CPU ( S2 ) or later is
Writing Devices stored by the number of write points specified 10-13
6
to Another CPU
DP.DDWR DP.DDWR n S1 S2 D1 D2 by ( D2 +1) into a device specified by another 10 -

CPU (n) ( D1 ) or later

In multiple CPU system, data stored in a
7
D.DDRD D.DDRD n S1 S2 D1 D2 10 -
Reading Devices device specified by another CPU (n) ( D1 ) or
from Another
CPU
lrater is stored by the number of read points 10-17
8
DP.DDRD DP.DDRD n S1 S2 D1 D2 specified by ( S1 +1) into a device specified by 10 -

host CPU ( S2 ) or late

2.8.1 Instructions for Multiple CPU high-speed transmission dedicated

2.8 Multiple CPU high-speed transmission dedicated instruction

2-61
 2.9 Redundant system instructions (For Redundant CPU)

2.9.1 Instructions for Redundant system (For Redundant CPU)

Table 2.41 Redundant System Instructions (For Redundant CPU)

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

Switches between the control system and

System standby system at the END processing of the
SP.CONTSW SP.CONTSW S D 8 - 11-2
switching scan executed with the SP.CONTSW
instruction.

2-62
3 CONFIGURATION
OF INSTRUCTIONS
3

3-1
 3.1 Configuration of Instructions
Most CPU module instructions consist of an instruction part and a device part.
Each part is used for the following purpose:
• Instruction part ...... indicates the function of the instruction.
• Device part ............ indicates the data that is to be used with the instruction.
The device part is classified into source data, destination data, and number of devices.
(1) Source (S)
(a) Source is the data used for operations.

(b) The following source types are available, depending on the designated device:
• Constant ............................................... Designates a numeric value to be used in the
operation.
This is set when the program is created, and
cannot be changed during the execution of
the program.
Constants should be indexed when used as
variable data.
• Bit devices and word devices ............... Designates the device that stores the data to
be used in the operation.
Data must be stored in the designated
device until the operation is executed.
By changing the data stored in a designated
device during program execution, the data to
be used in the instruction can be changed.
(2) Destination (D)
(a) The destination stores the data after the operation has been conducted. However,
some instructions require storing the data to be used in an operation at the destination
prior to the operation execution.
Example An addition instruction involving BIN 16-bit data

+ S D + S1 S2 D

Stores the data needed for operation Stores only the

before the actual operation. operation results.

(b) A device for the data storage must always be set to the destination.

(3) Number of devices and number of transfers (n)

(a) The number of devices and number of transfers designate the numbers of devices and
transfers used by instructions involving multiple devices.
Example Block transfer instruction

BMOV S D n

Designates the number of transfers

used by a BMOV instruction

(b) The number of devices or number of transfers can be set between 0 and 32767.
However, if the number is 0, the instruction will be a no-operation instruction.

3-2
 3.2 Designating Data
The following six types of data can be used with CPU module instructions.

Data that can be handled by Bit data ...................... Section 3.2.1

CPU module
Numeric data Integer data Word data .......................Section 3.2.2

Double-word data ...........Section 3.2.3 3

Real number
(floating point) data Single-precision .... Section 3.2.4 (1)
floating point data

4
Double-precision .... Section 3.2.4 (2)
floating point data
Character string data .... Section 3.2.5

4
3.2.1 Using bit data
6
Bit data is data used in one-bit units, such as for contacts or coils.
"Bit devices" and "Bit designated word devices" can be used as bit data.

(1) When using bit devices

7
Bit devices are designated in one-point units.

Designation of 1 point 8
of bit device M0

M0
SET Y10

Designation of 1 point

3.2.1 Using bit data

3.2 Designating Data
of bit device Y10

(2) Using word devices

(a) Word devices enable the use of a designated bit number 1/0 as bit data by the
designation of that bit number.
b15 to b0
Word device 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0

Each bit of a word device can be

used (1=ON, 0=OFF)

(b) Word device bit designation is done by designating " Word device . Bit No. ".
(Designation of bit numbers is done in hexadecimal.)
For example, bit 5 (b5) of D0 is designated as D0.5, and bit 10 (b10) of D0 is designated
as D0.A. However, there can be no bit designation for timers (T), retentive timers (ST),
counters (C) or index register (Z). (Example Z0.0 is not available).
Bit designated for word device
X0 (Bit 5 (b5) of D0 is turned ON if X0 is ON.)
SET D0.5

Bit designated for word device

(Turns ON Y10 if bit 5 (b5) of D0 is ON (1).)
D0.5
SET Y10

3-3
 3.2.2 Using word (16 bits) data
Word data is 16-bit numeric data used by basic instructions and application instructions.
The following two types of word data can be used with CPU module:
• Decimal constants................. K-32768 to K32767
• Hexadecimal constants ......... H0000 to HFFFF
Word devices and bit devices designated by digit can be used as word data.
For direct access input (DX) and direct access output (DY), word data cannot be designated by
digit. (For details of direct access input and direct access output, refer to the QnUCPU User's
Manual (Function Explanation, Program Fundamentals) or Qn(H)/QnPH/QnPRHCPU User's
Manual (Function Explanation, Program Fundamentals).

(1) When Using Bit Devices

(a) Bit devices can deal with word data when digits are designated.
Digit designation of bit devices is done by designating
" Number of digits Head number of bit device ". Digit designation of bit devices can
be done in
4-point (4-bit) units, and designation can be made for K1 to K4. (For link direct devices,
designation is done by "J Network No. \ Number of digits
Head number of bit device ".
When X100 to X10F are designated for Network No.2, it is done by J2\K4X100).For
example, if X0 is designated for digit designation, the following points would be
designated:
• K1X0 ......... The 4 points X0 to X3 are designated.
• K2X0 ......... The 8 points X0 to X7 are designated.
• K3X0 ......... The 12 points X0 to XB are designated.
• K4X0 ......... The 16 points X0 to XF are designated.

XF to XC XB to X8 X7 to X4 X3 to X0

K1 designation
range
(4 points)
K2 designation range
(8 points)
K3 designation range
(12 points)
K4 designation range
(16 points)

Fig 3.1 Digit Designation Setting Range for 16-Bit Instruction

(b) In cases where digit designation has been made at the source (S), the numeric values
shown in Table 3.1 are those which can be dealt with as source data.
Table 3.1 List of Numeric Values that Can Be Dealt with as Digit Designation
Number of Digits Designated With 16-Bit Instruction
K1 (4 points) 0 to 15
K2 (8 points) 0 to 255
K3 (12 points) 0 to 4095
K4 (16 points) -32768 to 32767

3-4
 (c) When destination (D) data is a word device
The word device for the destination becomes 0 following the bit designated by digit
designation at the source.
Ladder Example Processing
With 16-Bit Instruction K1X0 X3 X2 X1 X0
X010
MOV K1X0 D0 Filled with 0s

Source (S) data

b15 b4 b3 b2 b1 b0
D0 0 0 0 0 0 0 0 0 0 0 0 0 X3 X2 X1 X0
3
Fig 3.2 Ladder Example and Processing Conducted

(d) In cases where digit designation is made at the destination (D), the number of points
4
designated are used as the destination.
Bit devices below the number of points designated as digits do not change.
4
Ladder Example Processing
When source (S) data is a numerical value 1 2 3 4

H1234 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 6
X010
MOV H1234 K2M0

K2M0
M15 M8 M7 M0
0 0 1 1 0 1 0 0
7
Destination (D)
Not changed 3 4

When source (S) data is a word device

b15 b8 b7 b0 8
D0 1 1 1 0 1 0 1 0 1 0 0 1 1 1 0 1
X10
MOV D0 K2M100
M115 M108 M107 M100
K2M100 1 0 0 1 1 1 0 1

3.2.2 Using word (16 bits) data

3.2 Designating Data
Destination (D)
Not changed

Fig 3.3 Ladder Example and Processing Conducted

(2) Using word devices

Word devices are designated in 1-point (16 bits) units.

M0
MOV K100 D0

Designation of 1 point of word

device D0 (16 bits)

1. When digit designation processing is conducted, a random value can be used

for the bit device initial device number.
2. Digit designation cannot be made for the direct access I/O (DX, DY).

3-5
 3.2.3 Using double word data (32 bits)
Double word data is 32-bit numerical data used by basic instructions and application instructions.
The two types of double word data that can be dealt with by CPU module are as follows:
• Decimal constants................. K-2147483648 to K2147483647
• Hexadecimal constants ......... H00000000 to HFFFFFFFF
Word devices and bit devices designated by digit designation can be used as double word data.
For direct access input (DX) and direct access output (DY), designation of double word data is
not possible by digit designation.
(1) When Using Bit Devices
(a) Digit designation can be used to enable a bit device to deal with double word data.
Digit designation of bit devices is done by designating
" Number of digits Head number of bit device ". For link direct devices, designation
is done by
"J Network No. \ Number of digits Head number of bit device ". When X100
to X11F are designated for Network No.2, it is done by J2\K8X100. Digit designation of
bit devices can be done in 4-point (4-bit) units, and designation can be made for K1 to
K8. For example, if X0 is designated for digit designation, the following points would be
designated:
• K1X0 ...... The 4 points X0 to X3 are • K5X0...... The 20 points X0 to X13 are
designated. designated.
• K2X0 ...... The 8 points X0 to X7 are • K6X0...... The 24 points X0 to X17 are
designated. designated.
• K3X0 ...... The 12 points X0 to XB are • K7X0...... The 28 points X0 to X1B are
designated. designated.
• K4X0 ...... The 16 points X0 to XF are • K8X0...... The 32 points X0 to X1F are
designated. designated.

X1F X1C X1B X18 X17 X14 X13 X10 XF XC XB X8 X7 X4 X3 X0

K1
designation
range
(4 points)
K2 designation
range
(8 points)
K3 designation range
(12 points)
K4 designation range
(16 points)
K5 designation range
(20 points)
K6 designation range
(24 points)
K7 designation range
(28 points)
K8 designation range
(32 points)

Fig 3.4 Digit Designation Setting Range for 32-Bit Instructions

(b) In cases where digit designation has been made at the source (S) , the numeric values
shown in Table 3.2 are those which can be dealt with as source data.
Table 3.2 List of Numeric Values that Can Be Dealt with as Digit Designation
Number of Digits Number of Digits
With 32 Bit Instructions With 32 Bit Instructions
Designated Designated
K1 (4 points) 0 to 15 K5 (20 points) 0 to 1048575
K2 (8 points) 0 to 255 K6 (24 points) 0 to 16777215
K3 (12 points) 0 to 4095 K7 (28 points) 0 to 268435455
K4 (16 points) 0 to 65535 K8 (32 points) 2147483648 to 2147483647

3-6
 (c) When destination (D) data is a word device
The word device for the destination becomes 0 following the bit designated by digit
designation at the source.
Ladder Example Processing
With 32 bit Instructions
K1X0 X3 X2 X1 X0

Filled with 0s
X10
DMOV K1X0 D0
b15 b4 b3 b2 b1 b0
D0 0 0 0 0 0 0 0 0 0 0 0 0 X3 X2 X1 X0
3
D1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Source (S) data b31 b16

Filled with 0s 4
Fig 3.5 Ladder Example and Processing Conducted

(d) In cases where digit designation is made at the destination (D), the number of points 4
designated are used as the destination. Bit devices below the number of points
designated as digits do not change.
Ladder Example Processing
6
When source (S) data is a numerical value H78123456
0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0

3 4 5 6
7
0 1 1 1 1 0 0 0 0 0 0 1 0 0 1 0
X10
DMOV H78123456 K5M0 K5M0
7 8 1 2
8
M15 M8 M7 M0
Destination (D) 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0
M31 M20 M19 M16
0 0 1 0

3.2.3 Using double word data (32 bits)

3.2 Designating Data
Not changed

When source (S) data is a word device

b15 b8 b7 b0
D0 1 1 1 0 0 1 0 0 0 1 0 1 1 1 0 1
b15 b8 b7 b0
D1 0 0 1 1 0 1 0 0 1 0 0 1 0 1 1 1
X10
DMOV D0 K5M10
M25 M18 M17 M10
1 1 1 0 0 1 0 0 0 1 0 1 1 1 0 1
Destination (D)
M41 M30M29 M26
0 1 1 1

Not changed

Fig 3.6 Ladder Example and Processing Conducted

1. When digit designation processing is conducted, a random value can be used

for the bit device initial device number.
2. Digit designation cannot be made for the direct access I/O (DX, DY).

3-7
 (2) Using word devices

A word device designates devices used by the lower 16 bits of data. A 32-bit instruction
uses (designation device number) and (designation device number + 1).
M0
DMOV K100 D0

Designation of 2 points of
word devices D0 and D1 (32 bits)
32-bit data transfer instruction

3.2.4 Using real number data

Real number data is floating decimal point data used with basic instructions and application
instructions.
Only word devices are capable of storing real number data.

(1) Single-precision floating-point data

Instructions which deal with single-precision floating-point data designate devices which are
used for the lower 16 bits of data.
Single-precision floating-point data are stored in the 32 bits which make up (designated
device number) and (designated device number + 1).

M0
EMOV R100 D0

Designation of 2 points of word devices D0 and D1

(32 bits)
Designation of 2 points of R100 and R101 (32 bits)
Single-precision floating-point data transfer instruction

Remark
In sequence programs, floating decimal point data are designated by E .

Single-precision floating-point data uses two word devices and is expressed in

the following manner:
[Sign] 1. [Mantissa part] 2 [Exponent part]
The bit configuration and meaning of the internal representation of single-
precision floating-point data is as follows:

b31 b30 to b23 b22 to b16 b15 to b0

b31 b23 to b30 b0 to b22

Sign Exponent part Mantissa part

• Sign The sign is represented at b31.

0: Positive
1: Negative

• Exponent part The n of 2n is represented from b23 to b30.

Depending on the BIN value of b23 to b30, the value of n is as follows:

b23 to b30 FFH FEH FDH 81 80 7FH 7EH 02 01 00

n Not used 127 126 2 1 0 -1 -125 -126 Not used

3-8
 • Variable part The 23 bits from b0 to b22, represents the XXXXXX... at
binary 1.XXXXXX....
(2) Double-precision floating-point data
Instructions which deal with double-precision floating-point datadesignate devices which are
used for the lower 16 bits of data.
Double-precision floating-point data are stored in the 64 bits which make up (designated
device number) to (designated device number + 3).

M0
EDMOV R100 D0
3

Designation of 4 points of word devices D0, D1, D2

and D3 (64 bits) 4
Designation of 4 points of R100, R101, R102 and
R103 (64 bits)
Double-precision floating-point data transfer
instruction 4
Remark
In sequence programs, floating decimal point data are designated by E .
6

Double-precision floating-point data uses four word devices and is expressed 7

in the following manner:
[Sign] 1. [Mantissa part] 2 [Exponent part]
The bit configuration and meaning of the internal representation of double- 8
precision floating-point data is as follows:

b63 b62 to b52 b51 to b16 b15 to b0

3.2.4 Using real number data

3.2 Designating Data
b63 b52 to b62 b0 to 51
Sign Exponent part Mantissa part

• Sign The sign is represented at b63.

0: Positive
1: Negative

• Exponent part The n of 2n is represented from b52 to b62.

Depending on the BIN value of b52 to b62, the value of n is as follows:

b52 to b62 7FFH 7FEH 7FDH 400H 3FFH 3FEH 3FDH 3FCH 02H 01H 00H

n Not used 1023 1022 2 1 0 1 2 1021 1022 Not used

• Variable part The 52 bits from b0 to b51, represents the XXXXXX... at

binary 1.XXXXXX....

3-9
 1. The CPU module floating decimal point data can be monitored using the
monitoring function of a peripheral device.
2. When floating-point data is used to express 0, all data in the following range are
turned to 0.
(a) Single-precision floating-point data: b0 to b31
(b) Double-precision floating-point data: b0 to b63
3. The setting range of floating decimal point data is as follows. *1
(a) Single-precision floating-point data
2128 < Device data 2-126, 0, 2-126 Device data < 2128
(b) Double-precision floating-point data
21024 < Device data 2-1022,0,2-1022 Device data < 21024
4. Do not specify 0 in floating-point data (only when the most significant bit of
the floating-point real number is 1). (An operation error will occur if
floating-point operation is performed with 0.)
When 0 is specified, the following CPU module internally converts the value
to 0 to perform a floating-point operation. Therefore an operation error does not
occur.
• The High Performance model QCPU with the internal processing set to
"double precision". *2(Double precision is set by default for the floating-
point operation processing.)
When 0 is specified, the following CPU module performs a floating-point
operation with 0, keeping its processing speed. Therefore an operation error
occurs.
• Basic model QCPU *3
• High Performance model QCPU where internal operation is set to single
precision *2
• Process CPU
• Redundant CPU
• Universal model QCPU
• LCPU

*1: For operations when a real number is out of range and operations when an invalid value is input, refer to the
QnUCPU User's Manual (Function Explanation, Program Fundamentals) or Qn(H)/QnPH/QnPRHCPU
User's Manual (Function Explanation, Program Fundamentals).
*2: Switch between single precision and double precision of the internal operation of floating-point operation in
the PLC system of the PLC parameter dialog box. For the single precision and double precision of floating-
point operation, refer to the QnUCPU User's Manual (Function Explanation, Program Fundamentals) or
Qn(H)/QnPH/QnPRHCPU User's Manual (Function Explanation, Program Fundamentals).
*3: The Basic model QCPU can perform floating-point operation if its first five digits of serial No. are "04122 or
later".

3-10
3.2.5 Using character string data

Character string data is character data used by basic instructions and application instructions.
The target ranges from the designated character to the NULL code (00H) that indicates the end
of the character string.

(1) When designated character is the NULL code

3
One word is used to store the NULL code.
M0
$MOV " "
4
D0

D0 NULL

Designation of NULL code (00H) 4

Character string data transfer instruction

(2) When character string is even 6

Uses (number of characters/2 + 1) words, and stores character string and NULL code.
For example, if "ABCD" is transferred to D0, the character string ABCD is stored at D0 and
D1, and the NULL code is stored at D2. (The NULL code is stored as the last one word.) 7
M0
$MOV "ABCD" D0
8
D0 42H 41H
D1 44H 43H
D2 NULL

3.2.5 Using character string data

3.2 Designating Data
Designation of a character string
composed of even numbers
Character string data transfer instruction

(3) When number of characters is odd

Uses (number of characters/2) words (rounds up decimal fractions) and stores the character
string and NULL code.
For example, if "ABCDE" is transferred to devices starting from D0, the character string
(ABCDE) and the NULL code are stored from D0 to D2. (The NULL code is stored into the
upper 8 bits of the last one word.)
M0
$MOV "ABCDE" D0

D0 42H 41H
D1 44H 43H
D2 NULL 45H

Designation of a character string

composed of odd numbers
Character string data transfer instruction

3-11
 3.3 Indexing
(1) Overview of indexing
(a) Indexing is an indirect setting made by using an index register.
When an Indexing is used in a sequence program, the device to be used will become
the device number specified directly plus the contents of the index register.
For example, if D2Z2 has been specified, the specified device is calculated as
follows: D(2+3) = D5 and the content of Z2 is 3 become the specified device.

(b) Indexing with 32-bit index registers in addition to 16-bit index registers is available with
the Universal model QCPU and LCPU.

(2) Indexing with 16-bit index registers

(a) Example of indexing
Each index register can be set between 32768 and 32767.
Indexing is performed in the way shown below:
X0
MOV K 1 Z0 Stores -1 at Z0.

X0
Stores the data of D10Z0=
MOV D10Z0 D0 D{10+(-1)} = D9 at D0.

Indexing

(b) Devices to which indexing can be used

With the exception of the restrictions noted below, Indexing can be used with devices
used with contacts, coils, basic instructions, and application instructions.
1) Devices to which indexing can not be used
Device Meaning
E Floating decimal point data
$ Character string data

. Bit designated for word device

FX, FY, FD Function devices

P Pointers used as labels
I Interrupt pointers used as labels
Z Index register
S Step relay
TR SFC transfer devices*1
BL SFC block devices*1

*1: SFC transfer devices and SFC block devices are devices for SFC use.
Refer to the manual below for how to use these devices.
• MELSEC-Q / L / QnA Programming Manual (SFC)

3-12
 2) Devices with limits for use with index registers
Device Meaning Application Example

• Only Z0 and Z1 can be used for

T0Z0 K100
1
T T1Z1
timer contacts and coils.

• Only Z0 and Z1 can be used for

C0Z1 K100 2
C C1Z0
counter contacts and coils.

3
Remark
For timer and counter present values, there are no limits on index register
numbers used. 4
Value set for timer
X0 K100
T0 2
Present value of timer
SM400
BCD T0Z4 K4Y30
Value set for counter
6
X1 K10
C100

Present value of counter

7
SM400
BCD C100Z6 K2Y40

8
(c) A case where Indexing has been performed, and the actual process device, would be
as follows:
(When Z0 20 and Z1 5)

3.3 Indexing
Ladder Example Actual Process Device

X0
X1
MOV K20 Z0
MOV K2X64 K1M33

Description
MOV K 5 Z1 K2X50Z0 K2X(50 + 14) = K2X64

X1 Converts K20 into a hexadecimal number.

MOV K2X50Z0 K1M38Z1 K1M38Z1 K1M(38 - 5) = K1M33

X0
MOV K20 Z0 X1
MOV D20 K3Y12A

Description
MOV K 5 Z1
D0Z0 D (0 + 20) = D20
K3Y12FZ1 K3Y(12F - 5) = K3Y12A
X1
MOV D0Z0 K3Y12FZ1 Hexadecimal number

Fig. 3.7 Ladder Example and Actual Process Device

(3) Indexing with 32-bit (Universal model QCPU (excluding Q00UJCPU) and LCPU)
A method of specifing index registers in indexing with 32-bit can be selected from the
following two methods.
• Specifing the index registers’ range used for indexing with 32-bit.

3-13
 • Specifing the 32-bit indexing using “ZZ” specification.

32-bit indexing with the "ZZ" specification is only available for the following CPU
modules. See the programming tool operating manual for the available
programming tools.
• The first five digits of the serial No. for QnU(D)(H)CPU is “10042” or higher.
(excluding Q00UJCPU)
• QnUDE(H)CPU
• LCPU

(a) Example of specifing the range of index registers for use of 32-bit indexing.
1) Each index register can be set between -2147483648 and 2147483647.
An example of indexing is shown below.
X0
DMOV K40000 Z0 Stores 40000 at Z0.

X0
MOV ZR10Z0 D0 Stores the data of ZR10Z0=
ZR{10+40000}=ZR40010 at D0.

Indexing

2) Specification method
For indexing with a 32-bit index register, specify the head number of an index
register to be used on the Device tab of the Q parameter setting screen.

GX Developer 8.68R or earlier GX Deveioper 8.68W or later

Fig. 3.8 Setting windows for ZR device indexing setting parameter

When the head number of the index register used is changed on the Device tab of
the Q parameter setting screen, do not change the parameters only or do not write
only the parameters into the programmable controller. Be sure to write the
parameter into the programmable controller with the program.
When the parameter is forced to be written into the programmable controller, an
error of CAN'T EXE. PRG. occurs. (Error code: 2500)

3-14
 3) Device that indexing can be used
Indexing can be used only for the device shown below.
1
Device Meaning
ZR Serial number access format file register
D Extended data register (D)
2
W Extended link register (W)

4) Usable range of index registers

The following table shows the usable range of index registers for indexing with 3
32-bit index registers.
For indexing with 32-bit index registers, the specified index register (Zn) and
the next index register of the specified register (Zn+1) are used. Be sure not to 4
overlap index registers to be used.
Setting Value Index Registers to be Used Setting Value Index Registers to be Used
2
Z0 Z0, Z1 Z10 Z10, Z11
Z1 Z1, Z2 Z11 Z11, Z12
Z2 Z2, Z3 Z12 Z12, Z13
6
Z3 Z3, Z4 Z13 Z13, Z14
Z4 Z4, Z5 Z14 Z14, Z15
Z5 Z5, Z6 Z15 Z15, Z16
7
Z6 Z6, Z7 Z16 Z16, Z17
Z7 Z7, Z8 Z17 Z17, Z18
Z8 Z8, Z9 Z18 Z18, Z19
8
Z9 Z9, Z10 Z19 Cannot be specified

5) An example of indexing and the actual process device are as follows.

(When Z0 (32-bit) 100000 and Z2 (16-bit) 20)

3.3 Indexing
Ladder Example Actual Process Device

X0
X1
DMOV K100000 Z0
MOV ZR101000 D10

MOV K-20 Z2
Description
X1 ZR1000Z0 ZR(1000+100000)=ZR101000
MOV ZR1000Z0 D30Z2 D30Z2 D(30-20)=D10

Fig. 3.9 Ladder Example and Actual Process Device

3-15
 (b) Example of specifing 32-bit indexing with “ZZ” specification.
1) One index register can specify 32-bit indexing by using “ZZ” specification such
as “ZR0ZZ4”.
The 32-bit indexing with “ZZ” specification is as follows.
M0
DMOVP K100000 Z4 Stores 100000 at Z4 and Z5.

M0 Indexing ZR device with 32-bit

MOVP K100 ZR0ZZ4 index registers (Z4 and Z5)
ZR (0+100000) =ZR100000

2) Specification method
To perform 32-bit indexing by using “ZZ” specification, select “Use of ZZ” in
“Indexing Setting for ZR Device” in PC parameter.

Fig. 3.10 Setting window for indexing setting parameter for ZR device

3) Device that indexing can be used

The following device is available for indexing.
Device Meaning
ZR Serial number access format file register
D Extended data register (D)
W Extended link register (W)

4) Usable range of index registers

The following table shows the usable range of index registers in 32-bit indexing
used “ZZ” specification.
The 32-bit indexing with “ZZ” specification is specified as the format ZRmZZn.
Specifying ZRmZZn enables Zn and Zn+1 of 32-bit values to index the device
number, ZRm,
“ZZ” “ZZ”
*1
Index Registers Used Index Registers Used
specification specification*1

ZZ0 Z0, Z1 ZZ10 Z10, Z11

ZZ1 Z1, Z2 ZZ11 Z11, Z12

ZZ2 Z2, Z3 ZZ12 Z12, Z13

ZZ3 Z3, Z4 ZZ13 Z13, Z14

ZZ4 Z4, Z5 ZZ14 Z14, Z15

ZZ5 Z5, Z6 ZZ15 Z15, Z16

ZZ6 Z6, Z7 ZZ16 Z16, Z17

ZZ7 Z7, Z8 ZZ17 Z17, Z18

ZZ8 Z8, Z9 ZZ18 Z18, Z19

ZZ9 Z9, Z10 ZZ19 Not available

*1: refers to device name (ZR) for indexing target.

3-16
 5) The 32-bit indexing used “ZZ” specification and the acutual processing device
are as follows.
1
(Z0 (32-bit) 100000.Z2 (16-bit) 20)
Ladder Example Actual Process Device
2
X1
X0 MOV ZR101000 D10
DMOV K100000 Z0

END 3
MOV K-20 Z2

X1 Description
MOV ZR1000ZZ0 D30Z2 ZR1000ZZ0 ZR(1000+100000)=ZR101000 4
D30Z2 D(30-20)=D10

Fig.3.10 Ladder Example and Actual Process Device 2

6) Available functions for “ZZ” specification
The 32-bit indexing specification with “ZZ” specification applies in the following 6
functions.
No. Function Name and Description
1 Specifing devices in program instruction 7
2 Monitoing device registrations
3 Testing devices execution type
4 Testing devices with conditions 8
5 Setting monitor conditions
6 Tracing sampling (Trace point (specifing devices), trace taget device)
7 Data logging function (Sampling interval (specifying devices), logging target data)

3.3 Indexing
ZZn cannot be used alone as a device like “DMOV K100000 ZZ0”. When setting
values of index registers to specify 32-bit indexing with “ZZ” specification, set the
value of Zn (Z0~Z19).
ZZn alone cannot be input to each function.

3-17
 (4) Index modification using extended data register (D) and extended link register (W)
(Universal model QCPU (excluding Q00UJCPU) and LCPU)
Like index modification using data register (D) and link register (W) of internal user device, a
device can be specified by index modification within the range of the extended data register
(D) and extended link register (W).
Index modification in internal
user device Image of D device
User Program
Z0=0
D100 Internal user
device
MOV K1234

D1100
Z0=1000

Z1=0 Extended data

D20000
register
MOV K1234

D22000
Z1=2000

Index modification in
extended data register

1) Index modification where the device number crosses over the boundary
between the internal user device and the extended data register (D) or
extended link register (W)
The specification of index modification where the device number crosses over
the boundary between the internal user device and the extended data register
(D) or extended link register (W) cannot be made.
If doing so, an error occurs when the device range check is enabled at index
modification (error code: 4101).
Index modification in internal
user device Image of D device
User Program
Z0=0
D100 Internal user
device
MOV K1234

D20100 Extended data

Z0=20000 register
Index modification where the device number
crosses over the boundary between
theinternal user device and the extended data
register is not possible.

3-18
 2) Index modification where the device number crosses over the boundary
among the file register (ZR), extended data register (D), and extended link
register (W)
1
Index modification where the device number crosses over the boundary
among the file register (ZR), extended data register (D), and extended link
register (W) will not cause an error.
2
However, an error occurs if the index modification result of file register (ZR),
extended data register (D), and extended link register exceeds the file register
range (error code: 4101).
3
Index modification where the device
number crosses over the boundary
among the file register (ZR), extended
4
data register (D) will not cause an error.
File register files
User Program
File 2
ZR100 register
Z0=0 (8k)
MOV K1234
Z0=10000
D14196
Extended data
register (D)
6
(8k)
D20000 D12288~
Z1=0
MOV K1234 Z20000Z1 7
Extended link
Z1=4000 register (W)
W2DC0
(8k)

Index modification where the device number

W2000~
8
crosses over the boundary among the
extended data register (D), and extended
link register (W) will not cause an error.

Extended link register exceeds

3.3 Indexing
the file register range.
Z1=10000

3-19
 (5) Other index modifications
(a) Bit data
Device numbers can be index modified when performing digit designation. However,
Indexing is not possible by digit designation.

BIN K4X0Z2 D0
Setting is possible since this indicates
Indexing for device number.
If Z2=3, then (X0+3)=X3

BIN K4Z3X0 D0

Setting is not possible since this indicates

Indexing by digit designation.

(b) Both I/O numbers and buffer memory number can be performed indexing with
intelligent function module devices*1.

MOV U10Z1\G0Z2 D0

If Z1=2 and Z2=8,

then U(10+2)\G(0+8)=U12\G8

(c) Both network numbers and device numbers can be performed indexing with link direct
devices*1.

MOV J1Z1\K4X0Z2 D0

If Z1=2 and Z2=8,

then J(1+2)\K4X(0+8)=J3\K4X8
*1: For the intellingent function module device, link direct devices, refer to the QnUCPU User’s Manual
(Function Explanation, Program Fundamentals) or Qn(H)/QnPH/QnPRHCPU User’s Manuall
(Function Explanation, Program Fundamentals)

(d) When indexing is used for multiple CPU shared devices*2, indexing for the head I/O
numbers of CPU modules and indexing for the CPU shared memory address are
automatically executed.

MOV U3E0Z1\G0Z2 D0

If Z1=2 and Z2=8,

then U3E(0+2)\G(0+8)=U3E2\G8
*2: For the multiple CPU shared device, refer to the QnUCPU User’s Manual
(Function Explanation, Program Fundamentals) or Qn(H)/QnPH/QnPRHCPU User’s Manuall
(Function Explanation, Program Fundamentals)

3-20
 (e) Index modification using extended data register (D) and extended link register (W) by
32 bits (Universal model QCPU(except Q00UJCPU) and LCPU.)
Like index modification using file register (ZR), index modification using extended data
register (D) and extended link register (W) by 32 bits can be performed by the following
1
two methods.
• Specifing the index registers’ range used for indexing with 32-bit. 2
• Specifing the 32-bit indexing using “ZZ” specification.

3
32-bit indexing with the "ZZ" specification is only available for the following CPU
modules. See the programming tool operating manual for the available
programming tools. 4
• The first five digits of the serial No. for QnU(D)(H)CPU is “10042” or higher.
(except Q00UJCPU)
• QnUDE(H)CPU 2
• LCPU

6
(6) Cautions
(a) Performing indexing between the FOR and NEXT instructions
Pulses can be output between the FOR and NEXT instructions by use of the edge relay 7
(V). However, pulse output using the PLS/PLF/pulse ( P) instruction is not allowed.

[When edge relay is used] [When edge relay is not used] 8

(M0Z1 provides normal pulse output.) (M0Z1 does not provide normal pulse output.)
SM400 SM400
MOV K0 Z1 MOV K0 Z1

FOR K10 FOR K10

3.3 Indexing
X0Z1 V0Z1 X0Z1
M0Z1 PLS M0Z1
SM400 SM400
INC Z1 INC Z1

NEXT NEXT

Remark
The ON/OFF data of X0Z1 is stored by the edge relay V0Z1.
For example, the ON/OFF data of X0 is stored by V0, and that of X1 by V1.

3-21
 (b) Performing indexing with the CALL instruction
Pulses can be output with the CALL instruction by use of the edge relay (V). However,
pulse output using the PLS/PLF/pulse ( P) instruction is not allowed.

[When edge relay is used] [When edge relay is not used]

(M0Z1 provides normal pulse output.) (M0Z1 does not provide normal pulse output.)
SM400 SM400
MOV K0 Z1 MOV K0 Z1

CALL P0 CALL P0

SM400 SM400
MOV K1 Z1 MOV K1 Z1

CALL P0 CALL P0

FEND FEND
X0Z1 V0Z1 X0Z1
P0 M0Z1 P0 PLS M0Z1

RET RET

(c) Device range check during indexing

1) Basic model QCPU, High Performance model QCPU, Process CPU, and
Redundant CPU
Device range checks are not conducted during indexing.
Therefore, when the data after index modification exceed the user specified
device range, the data is written to another device without causing an
error.(Note, however, that when the data after index modification is written to
the device for system use exceeding the user specified device range, an error
occurs. (Error code: 1103))
Take extra precaution when using indexing in programming.
2) Universal model QCPU and LCPU
The device range is checked for indexing.
With changing the settings of the PLC parameter, the device range is not
checked.

(d) Changing indexing with 16-bit index register for indexing with 32-bit index register
For changing indexing with 16-bit index register for indexing with 32-bit index register,
check if the program has enough spaces for indexing.
For indexing with 32-bit index registers, the specified index register (Zn) and the next
index register of the specified register (Zn+1) are used. Be sure not to overlap index
registers to be used.

3-22
3.4 Indirect Specification
1
(1) Indirect Specification
(a) Indirect specification is a method that specifies address of the device to be used in a
sequence program using two word devices (two points of word device). Use indirect 2
specification as index modification when the index register is insufficient.
ADRSET D100 D0 Stores the address of

MOV K50 Z0 DMOV K50 W0

D100 to D0.
3
DMOV K10000 D150 DMOV K10000 D150

DMOV D100Z0 D110 D+ D0 W0 D10 (Address of D100) + 50 =

(Address of D150)
4
Specification of
MOV @D10 D110
D (100 + 50) = D150
Specification of

[When index resister is used]

address of D150

[When indirect specification is used]

2
(b) Specify the device to be used for specifying the address as "@ + (word device
number)". For example, when @D100 is specified, the device address will be the
contents of D101 and D100.
6
(c) The address of the device specified indirectly can be confirmed with the ADRSET
instruction.
For the ADRSET instruction, refer to Section 7.18.6. 7
(2) Indirect specification available devices

Table 3.3 shows that the CPU module devices can be specified indirectly. 8
Table 3.3 List of Indirect Specification Available Devices
Availability of
Device Type Indirect Example of Indirect Specification

3.4 Indirect Specification

Specification
Bit device *1 N/A ––––––––––
Internal user device • @D100
Word device *1 Available
• @D100Z2 *2
Bit device *1 N/A ––––––––––
Link direct device • @J1\W10
Word device *1 Available*3
• @J1Z1\W10Z2 *2
• @U10\G0
Intelligent function module device Available*3
• @U10Z1\G0Z2 *2
Index register N/A ––––––––––
• @R0, @ZR20000
File register Available
• @R0Z1,@ZR20000Z1 *2
Extended data register (D) • @D1000
Available
Extended link register (W) • @W1000
Nesting ––––––––––
Pointer ––––––––––
Constants ––––––––––
SFC block device
N/A
SFC transition device
Other Network No. specification ––––––––––
device
I/O No. specification device

*1: For the device names, refer to the QnUCPU User’s Manual
(Function Explanation, Program Fundamentals) or Qn(H)/QnPH/QnPRHCPU User’s Manuall
(Function Explanation, Program Fundamentals)
*2: Indicates when index modification by an index register is performed.
*3: Indirect specification is possible, but the address can not be written with the ADRSET instruction.

3-23
 (3) Precautions
(a) The address for indirect specification uses two words.Therefore, to substitute indirect
specification for index modification, the addition/subtraction of 32-bit data is required.
The following is the ladder used for the address addition/subtraction of the device
stored in D1 and D0 for indirect specification.
[To add "1" to the address of the device for indirect specification]

DINCP D0

Device used for indirect specification

32-bit instruction

[To subtract "1" from the address of the device for indirect specification]

DDECP D0

Device used for indirect specification

32-bit instruction

(b) Indirect specification of extended data register (D) and extended link register (W)
Indirect specification with indirect address can be performed in the extended data
register (D) and extended link register (W).
Note that when indirect specification is performed to the extended data register (D) and
data register (D) in internal device or to the extended link register (W) and link register
(W) in internal device, the areas of the internal user device and extended data register
(D) or extended link register (W) are not treated as a sequence.
Internal user device

Setting an address D0
ADRSET D12000 D100 Data register
"D12000 h to D100 and D101
D12000
Setting the address that D12287
is an addition of 1000 to
D+ K1000 D100 D102
the address of D12000 to
D102 and D103

MOV K1234 @D102

File register files

File register

D12288
Extended data
register(D)
D13000
Since the areas of the data register and
extended data register are not sequence,
D63487
D13000 is inaccessible.
Extended link
register (W)

3-24
3.5 Reducing Instruction Processing Time
1
3.5.1 Subset Processing
2
Subset processing is used to place limits on bit devices used by basic instructions and
application instructions in order to increase processing speed.
However, the instruction symbol does not change. 3
To shorten scans, run instructions under the conditions indicated below.

(1) Conditions which each device must meet for subset processing 4
(a) When using word data
Device Condition
• Designates a bit device number in a factor of 16.
2
Bit device • Only K4 can be designated for digit designation.
• Does not perform indexing.
• Internal user device. 6
• File register (R, ZR *4)
Word device
• Multiple CPU shared device *1, *2
• Index register (Z) / Standard device register (Z) *3
Constants • No limitations
7

(b) When using double word data 8

Device Condition
• Designates a bit device number in a factor of 16.
Bit device • Only K8 can be designated for digit designation.
• Does not perform indexing.

3.5.1 Subset Processing

3.5 Reducing Instruction Processing Time
• Internal user device.
• File register (R, ZR *4)
Word device
• Multiple CPU shared device *1, *2
• Index register (Z) / Standard device register (Z) *3
Constants • No limitations

(c) When using bit data

Device Condition
Bit device • Internal user device (indexing possible)
• Bit specification of internal user device
Word device • Bit specification of file register (R, ZR *4)
• Bit specification of multiple CPU shared device *1, *2

*1: Only for Universal model QCPU

*2: Valid only for the multiple CPU high speed transmission area (from U3En\G10000)
(Excluding the case that indexing is executed for the head I/O number of the CPU module (U3En\G10000))
*3: Applies only to Universal model QCPU and LCPU.
*4: Applies only to Universal model QCPU (excluding Q00UJCPU) and LCPU.

3-25
 (2) Instructions for which subset processing can be used
Types of Instructions Instruction Symbols
LD,LDI,AND,ANI,OR,ORI,LDP,LDF,ANDP,ANDF,ORP,ORF,LDPI,ANDPI,ANDFI,
Contact instructions
ORPI,ORFI
Output instructions OUT,SET,RST

Comparison operation instruction • , , , , , ,D ,D ,D ,D ,D ,D

• +, ,*,/,INC,DEC,D+,D ,D*,D/,DINC,DDEC
Arithmetic operation
• B+,B ,B*,B/, E+,E ,E*,E/
Data conversion instructions • BCD, BIN, DBCD, DBIN, FLT, DFLT, INT, DINT
• MOV, DMOV, CML, DCML, XCH, DXCH
Data transfer instruction
• FMOV, BMOV, EMOV
Program branch instruction • CJ, SCJ, JMP
Logic operations • WAND, DAND, WOR, DOR, WXOR, DXOR, WXNR, DXNR
Rotation instruction • RCL, DRCL, RCR, DRCR, ROL, DROL, ROR, DROR
Shift instruction • SFL, DSFL, SFR, DSFR
Data processing instructions • SUM, SEG
Structure creation instructions • FOR, CALL

3.5.2 Operation processing with standard device registers (Z)

(Universal model QCPU and LCPU only)
Operation processing time can be reduced with standard device registers (Z).
The following shows an example program with standard device registers.

+ D0 D10 D20 Using data registers takes three steps and

the operation processing time of 28.5 ns.
(With Q4/Q06/Q10/Q13/Q20/Q26UD(E)HCPU)

+ Z0 Z1 Z2 Using standard device registers instead of

data registers takes one step and the
operation processing time of 9.5 ns.
(With Q4/Q06/Q10/Q13/Q20/Q26UD(E)HCPU)

Operation processing time is reduced with the instructions that the subset processing is possible.
For the number of steps, refer to Section 3.8.
For the operation time for each instruction, refer to Appendix 1.

Because standard device registers are the same devices as index registers, do
not use device numbers of the standard device registers for the index registers.

3-26
3.6 Cautions on Programming (Operation Errors)
1
Operation errors are returned in the following cases when executing basic instructions and
application instructions with CPU module:
• An error listed on the explanatory page for the individual instruction occurred. 2
• When an intelligent function module device is used, no intelligent function module is installed
at the specified I/O number position.
• When an intelligent function module device is used, the specified buffer memory address does not exist. 3
• The relevant network does not exist when using a link device.
• When a link device is used, no network module is installed at the specified I/O number position.
• When a multiple CPU shared device is used, a CPU module is not installed at the head I/O 4
number position of the specified CPU module.
• When a multiple CPU shared device is used, the specified shared memory address does not exist.
• The setting of the device number crosses over the boundary between the internal user device 2
and the extended data register (D) or extended link register (W).
(Universal model QCPU (excluding Q00UJCPU) and LCPU)
6
When file register is set but a memory card is not installed or when file register is
not set, writing/reading to/from file register is as follows:
(1) For the High Performance model QCPU, Process CPU, and Redundant CPU 7
An error does not occur even when writing/reading to/from file register is
performed. However, “0H” is stored when reading from file register is
performed. 8
(2) For the Universal model QCPU and LCPU
The OPERATION ERROR (error code:4101) occurs when writing/reading to/
from file register is performed.

3.6 Cautions on Programming (Operation Errors)

(1) Device range check
Device range checks for the devices used by basic instructions and application instructions
in CPU module are as indicated below:
(a) Instructions for specified each device, including MOV and DMOV
1) For the Basic Model QCPU, High Performance model QCPU, Process CPU,
and Redundant CPU
The device range is not checked. In cases where the corresponding device
range is exceeded, data is written to other devices. *1

For example, in a case where the data register has been allocated 12k points,
there will be no error even if it exceeds D12287.

DMOV K100 D12287

This designates D12287 and D12288 as the

target devices for executing the DMOV instruction.
However, since D12288 does not exist,
data in another device is corrupted.
Device range checks are not conducted also in cases where indexing is being
performed.
In cases where the corresponding device range is exceeded as the result of
performing indexing, data is written to other devices.*1
*1: For the assignment order of internal user devices, refer to this Section (c) Character string data.

3-27
 2) Universal model QCPU and LCPU
The device range is checked. When the device number is outside the device
range, an operation error occurs.
For example, when12 k points are assigned to a data register, an error occurs
if the device number of the data register exceeds D12287.

DMOV K100 D12287

When D12287 is specified with the DMOV instruction,

the target devices are D12287 and D12288.
However, an operation error occurs because D12288
does not exist.

The device range is checked even though indexing is executed.

With changing the settings of the PLC parameter, the device range is not
checked.*2
*2: For changing the settings of the PLC parameter on GX Developer, refer to the following manual.
• QCPU User's Manual (Function Explanation, Program Fundamentals)

(b) Instructions for a block of devices, including BMOV and FMOV

1) For the Basic Model QCPU, High Performance model QCPU, Process CPU,
and Redundant CPU
The device range is checked.
When the device number is outside the device range, an operation error
occurs.
For example, when 12 k points are assigned to a data register, an error occurs
if the device number of the data register exceeds D12287.

BMOV D0 D12287 K2

This designates D12287 and D12288 as the

target devices for executing the BMOV instruction.
However, since D12288 does not exist,
an operation error occurs.

Device range checks are also conducted when indexing is performed.

However, if indexing has been conducted, there will be no error returned if the initial device
number exceeds the relevant device range.

MOV K2 Z1

BMOV D0 D12285Z1 K2

When D12287 is specified with the BMOV instruction,

the target devices are D12287 and D12288.
However, an operation error occurs because D12288
BMOV D0 D12287Z1 K2 does not exist.

An operation error occurs since head device number

is D12289 that exceeds the device range.

3-28
 2) Universal model QCPU and LCPU
The device range is checked.
When the device number is outside the device range, an operation error 1
occurs.
For example, when12 k points are assigned to a data register, an error occurs
if the device number of the data register exceeds D12287.
2
BMOV D0 D12287 K2

When D12287 is specified with the BMOV instruction, 3

the target devices are D12287 and D12288.
However, an operation error occurs because D12288
does not exist.
The device range is checked even though indexing is executed. 4
An error occurs when the head device number of the devices with indexing
exceeds the device range.
2
MOV K2 Z1

BMOV D0 D12285Z1 K2 6
When D12287 is specified with the BMOV instruction,
the target devices are D12287 and D12288.

BMOV D0 D12287Z1 K2
However, an operation error occurs because D12288
does not exist.
7
An operation error occurs since head device number
is D12289 that exceeds the device range.
8
With changing the settings of the PLC parameter, the device range is not
checked.*2
*2: For changing the settings of the PLC parameter on GX Developer, refer to the following manual.

3.6 Cautions on Programming (Operation Errors)

• QCPU User's Manual (Function Explanation, Program Fundamentals)

(c) Character string data

Because all character string data is of variable length, device range checks are
performed.
In cases where the corresponding device range has been exceeded, an operation error
will be returned.
For example, in a case where the data register has been allocated 12k points, there will
be an error if it exceeds D12287.

$MOV "ABC" D12287

This designates D12287 and D12288 as the

target devices for executing the $MOV instruction.
However, since D12288 does not exist,
an operation error occurs.
However, with the Basic Model QCPU, High Performance model QCPU, Process CPU,
and Redundant CPU, when indexing is executed and the head device number is
outside the device range, no error occurs and the other devices are accessed.

3-29
 When performing the following access in Universal model QCPU or LCPU, an error
(error code: 4101) occurs.
1) Access crossing the boundary of devices caused by indexing
(range of A area)
The allocation order of individual devices is shown below:
SM
SD
X
Y
M
L
B
F
SB
V
Area A
S
Contact and coil of T
Contact and coil of ST
Contact and coil of C
Present value of T
Present value of ST
Present value of C
D
W
SW
Empty area
File register Boundary B
(32K points)

2) Access crossing the boundary of file registers caused by indexing

3) Access to file registers (R, ZR) without setting file register files
4) Access to file registers (R, ZR) exceeded the range of file register files
Presetting PC parameter not to check indexing device range enables the Universal
model QCPU not to detect an error in the above accesses from 1) to 4).
Detecting an error in the above accesses from 1) to 4) , however, depends on the serial
No. of Universal model QCPU.*2
First 5 digits of serial No. for Universal model QCPU
Setting device range in indexing
Serial No.”10021” or lower Serial No.”10022” or higer
Set Detected errors in accesses 1) to 4)
Not set Detected errors in accesses 2) to 4) Not detected

*2: For changing the settings of the PLC parameter, refer to the QnUCPU User's Manual (Function
Explanation, Program Fundamentals) or Qn(H)/QnPH/QnPRHCPU User's Manual (Function
Explanation, Program Fundamentals).

When indexing is executed only with Universal model QCPU or LCPU, devices
between internal user devices (SW) and file registers (R) cannot be skipped.
(Error code: 4101).

3-30
 Remark
For how to change the internal user device allocation, refer to the User’s Manual
1
(Functions Explanation, Program Fundamentals) for the CPU module used.

2
(d) Device range checks are conducted when indexing is performed by direct access
output (DY).
3
(e) Precautions for using the extended data register (D) or extended link register (W) (for
the Universal model QCPU except the Q00UJCPU, and LCPU )
With the following specification methods, data cannot be specified crossing over the
boundary of the internal user device and extended data register (D) or extended link
4
register (W). Doing so causes "OPERATION ERROR" (error code: 4101).
• Index modification 2
• Indirect specification

• Specification with the instructions that handle data blocks*1

6
Data block where the device number
crosses over the boundary between the
internal user device and the extended data
User Program
register (D) cannot be handled. Image of D device 7
D100 Internal user
device
FMOV K0 D100 K200
8
D199

FMOV K0 D12200 K200

D12200

3.6 Cautions on Programming (Operation Errors)

FMOV K0 D20000 K200 D12299 Extended data
register (D)
D20100

D20299

*1 Data block indicates the following data.

• Data used in the instructions, such as FMOV, BMOV, BK+, which multiple words are targeted for
operation
• Control data, composed of two or more words, specified in the instructions, such as SP.FWRITE,
SP.FREAD
• Data whose data type is 32-bit or more (BIN 32-bit, real number, indirect address of the device)

3-31
 (2) Device data check

Device data checks for the devices used by basic instructions and application instructions in
CPU module are as indicated below:

(a) When using BIN data

No error is returned even if the operation results in overflow or underflow. The carry flag
does not go on at such times, either.

(b) When using BCD data

1) Each digit is check for BCD value (0 to 9). An operation error is returned if individual
digits are outside the 0 to 9 (A to F) range.
2) No error is returned even if the operation results in overflow or underflow. The carry
flag does not go on at such times, either.

(c) When using floating-point data

1) An operation error occurs when the following operation results are returned with the
single-precision floating-point operation instruction.
When the absolute value of the floating decimal point data is 1.0 2-127 or lower
When absolute value of floating decimal point data is 1.0 2128 or higher
2) An operation error occurs when the following operation results are returned with the
double-precision floating-point operation instruction.
When the absolute value of the floating decimal point data is 1.0 2-1023 or lower
When absolute value of floating decimal point data is 1.0 21024 or higher

(d) Using character string data

No data check is conducted.

(3) Buffer memory access

For accessing buffer memories, using instructions with intelligent function module devices
(from Un\G0) is recommended.
(4) Multiple CPU shared memory access
For accessing multiple CPU shared memories, using instructions with multiple CPU shared
devices (from U3En\G10000) is recommended.

3-32
3.7 Conditions for Execution of Instructions
1
The following four types of execution conditions exist for the execution of CPU module sequence
instructions, basic instructions, and application instructions:
• Non-conditional execution...... Instructions executed without regard to the ON/OFF status of 2
the device
Example LD X0, OUT Y10
3
• Executed at ON...................... Instructions executed while input condition is ON
Example MOV instruction, FROM instruction
• Executed at leading edge ...... Instructions executed only at the leading edge of the input 4
condition (when it goes from OFF to ON) Example
PLS instruction, MOVP instruction.
• Executed at trailing edge ....... Instructions executed only at the trailing edge of the input 2
condition (when it goes from ON to OFF) Example
PLF instruction.
6
For coil or equivalent basic instructions or application instructions, where the same instruction
can be designated for either execution at ON or leading edge execution, a "P" is added after the
instruction name to specify the condition for execution.
7
• Instruction to be executed at ON Instruction name
• Instruction to be executed at leading edge Instruction name + P 8

Execution at ON and execution at leading edge for the MOV instruction are designated as
follows:

3.7 Conditions for Execution of Instructions

MOV K4X0 D0

Execution during ON

MOVP K4X0 D0

Execution at leading edge

3-33
 3.8 Counting Step Number
The number of steps in CPU module sequence instructions, basic instructions, and application
instructions differs depending on whether indirect setting of the device used is possible or not.

(1) Counting the number of basic steps

The basic number of steps for basic instructions and application instructions is calculated by
adding the device number and 1.
For example, the "+ instruction" would be calculated as follows:

+ D0 D10
(1) (2) Number of devices 2 Number of basic steps: 3

+ D0 D10 D20
(1) (2) (3) Number of devices 3 Number of basic steps: 4

(2) Conditions for increasing the number of steps

The number of steps is increased over the number of basic steps in cases where a device is
used that is designated indirectly or for which the number of steps is increased.

(a) When device is designated indirectly

In cases where indirect designation is done by @ , the number of steps is increased 1
step over the number of basic steps.
For example, when a 3-step MOV instruction is designated indirectly (example: MOV
K4X0 @D0), one step is added and the instruction becomes 4 steps.

(b) Devices with additional steps (the Basic Model QCPU, High Performance model QCPU,
Process CPU, and Redundant CPU)
Devices with Additional Steps Added Steps Example
Intelligent function module device MOV U4\G10 D0
Multiple CPU shared device MOV U3E1\G0 D0
Link direct device MOV J3\B20 D0
Index register 1 MOV Z0 D0
Serial number access format file register MOV ZR123 D0
32-bit constant DMOV K123 D0
Real constant EMOV E0.1 D0
For even numbers: (number of characters) / 2
Character string constant For odd numbers: $MOV "123" D0
(number of characters + 1) / 2

3-34
 (c) Devices with additional steps (Universal model QCPU(except Q00UJCPU) and LCPU)
1) Instructions applicable to subset processing
The following table shows steps depending on the devices. 1
Added Steps
Basic Number of
Instruction Symbols Devices with Additional Steps (Number of
Instruction Steps)
Steps
2
Serial number access format file register,
LD,LDI,AND,ANI,OR,ORI, Extended data register (D),
LDP,LDF,ANDP,ANDF,ORP,ORF Extended link register (W) 1(2) 1
3
Multiple CPU shared device*3
Serial number access format file register,

LDPI,LDFI
Extended data register (D),
1(4) 3
4
Extended link register (W)

Multiple CPU shared device*3

Serial number access format file register, 2
Extended data register (D),
ANDPI,ANDFI,ORPI,ORFI
Extended link register (W) 1(5) 4

Multiple CPU shared device*3

6
Serial number access format file register
Extended data register (D),
SET
Extended link register (W) 1(2) 1

Multiple CPU shared device*3

7
Timer/Counter 3(4)
Serial number access format file register
OUT Extended data register (D), 1
8
Extended link register (W) 1(2)

Multiple CPU shared device*3

Serial number access format file register
Extended data register (D),

3.8 Counting Step Number

RST (bit device)
Extended link register (W) 1(2) 1

Multiple CPU shared device*3

Timer/Counter
2(4)
(Bit/word device)
Serial number access format file register
RST (word device) 2
Extended data register (D), 1(3)
Extended link register (W)

Multiple CPU shared device*3 1(3)

Standard device register *2 -1

LD=,LD<>,LD<,LD<=,LD>,LD>=, Serial number access format file register
AND=,AND<>,AND<,AND<=,AND>,AND>=, Extended data register (D), 3
OR=,OR<>,OR<.OR<=,OR>,OR>= Extended link register (W) 1

Multiple CPU shared device*3

Standard device register *2 -1

Serial number access format file register
LDD=,LDD<>,LDD<,LDD<=,LDD>,LDD>=,
Extended data register (D),
ANDD=,ANDD<>,ANDD<,ANDD<=,ANDD>,
Extended link register (W) 3
AND>=,ORD=,ORD<>,ORD<.ORD<=, 1
3
ORD>,ORD>= Multiple CPU shared device*
Decimal constant, hexadecimal
constant, real constant

3-35
 Added Steps
Basic Number of
Instruction Symbols Devices with Additional Steps (Number of
Steps
Instruction Steps)

Standard device register *2 D :-1

+,-,+P,-P,WAND,WOR,WXOR,WXNR, Serial number access format file register
WANDP,WORP,WXORP,WXNRP Extended data register (D), 3
(2 devices) Extended link register (W) S1 :1, D :3
Multiple CPU shared device*3

Standard device register *2 D :-1

Serial number access format file register
D+,D-,D+P,D-P,DAND,DOR,DXOR,DXNR, Extended data register (D),
DANDP,DORP,DXORP,DXNRP Extended link register (W) S1 :1, D :3 3
(2 devices)
Multiple CPU shared device*3
Decimal constant, hexadecimal
S1 :1
constant, real constant
Serial number access format file register
+,-,+P,-P,WAND,WOR,WXOR,WXNR,
Extended data register (D),
WANDP,WORP,WXORP,WXNRP S1 , S2 :1, D :2 3
Extended link register (W)
(3 devices)*1
Multiple CPU shared device*3
Serial number access format file register
Extended data register (D),
D+,D-,D+P,D-P,DAND,DOR,DXOR,DXNR,
Extended link register (W) S1 , S2 :1, D :2
DANDP,DORP,DXORP,DXNRP 3
Multiple CPU shared device*3
(3 devices)*1
Decimal constant, hexadecimal
S1 , S2 :1
constant, real constant
Serial number access format file register
Extended data register (D),
*, *P, /, /P
Extended link register (W) S1 , S2 :1, D :2 3

Multiple CPU shared device*3

Serial number access format file register
Extended data register (D),
Extended link register (W) S1 , S2 :1, D :2
D*, D*P, D/, D/P, E*, E*P 3
Multiple CPU shared device*3
Decimal constant, hexadecimal
S1 , S2 :1
constant, real constant

3-36
 Added Steps
Basic Number of
Instruction Symbols Devices with Additional Steps (Number of
Steps
Instruction Steps) 1
Index register/Standard device register *2 -1
Serial number access format file register
INC,INCP,DEC,DECP,DINC,DINCP,
Extended data register (D), 2
DDEC,DDECP
Extended link register (W)
3 2
3
Multiple CPU shared device*
Serial number access format file register

MOV,MOVP
Extended data register (D),
1 2 3
Extended link register (W)
Multiple CPU shared device*3
Serial number access format file register
Extended data register (D), 4
Extended link register (W)
DMOV,DMOVP,EMOV,EMOVP 1 2
Multiple CPU shared device*3
Decimal constant, hexadecimal
constant, real constant
2
Serial number access format file register
Extended data register (D),
BCD,BCDP,BIN,BINP,FLT,FLTP,CML,CMLP
Extended link register (W)
S1 :1, S2 :2 2
6
Multiple CPU shared device*3
Serial number access format file register

DBCD,DBCDP,DBIN,DBINP,INT,INTP,DINT,
Extended data register (D),
Extended link register (W)
S1 :1, S2 :2 7
2
DINTP,DFLT,DFLTP,DCML,DCMLP Multiple CPU shared device*3
Decimal constant, hexadecimal
:1
constant, real constant
S1
8
*1: If the same device is used for S1 and S2 , the number of basic steps increases by one.
*2: The number of steps decreases with a standard device register.
When multiple standard device registers are used in an instruction applicable
to subset processing, the number of steps decreases. The following table

3.8 Counting Step Number

shows the number of steps for each instruction.
*3: Not available with LCPU.
Added Steps
Locations Where Standard Device Regis- Basic Number of
Instruction Symbols (Number of
ter Is Used Steps
Instruction Steps)
LD=,LD<>,LD<,LD<=,LD>,LD>=,
AND=,AND<>,AND<,AND<=,AND>,AND>=,
OR=,OR<>,OR<.OR<=,OR>,OR>=
LDD=,LDD<>,LDD<,LDD<=,LDD>,LDD>=, S1 and S2 -2(1) 3
ANDD=,ANDD<>,ANDD<,ANDD<=,ANDD>,
AND>=,ORD=,ORD<>,ORD<.ORD<=,
ORD>,ORD>=
+,-,+P,-P,D+,D-,D+P,D-P,
WAND,WOR,WXOR,WXNR,
DAND,DOR,DXOR,DXNR,
S1 and D -2(1) 3
WANDP,WORP,WXORP,WXNRP,
DANDP,DORP,DXORP,DXNRP
(2 devices)

3-37
 Added Steps
Locations Where Standard Device Regis- Basic Number of
Instruction Symbols (Number of
ter Is Used Steps
Instruction Steps)
S1 , S2 , and D -2(1)

S1 , or S2 and D -1(2)
+,-,+P,-P,D+,D-,D+P,D-P, S1 and S2
WAND,WOR,WXOR,WXNR,
(only when that device that the
DAND,DOR,DXOR,DXNR, ±0(3)
number of steps does not increase is 3
WANDP,WORP,WXORP,WXNRP,
DANDP,DORP,DXORP,DXNRP specified for D )
(3 devices)*1 S1 and S2

(only when a serial number access format +2(5)

file register is specified for D )

*1: If the same device is used for S1 and D , the number of basic steps increases by one.

Added Steps
Locations Where Standard Device Regis- Basic Number of
Instruction Symbols (Number of
ter Is Used Steps
Instruction Steps)

S1 , S2 , and D -2(1)
*, *P, /, /P 3
S1 , or S2 and D -1(2)

S1 , S2 , and D -2(1)

S1 , or S2 and D -1(2)

S1 and S2

(only when that device that the

D*, D*P, D/, D/P, E*, E*P
±0(3) 3
number of steps does not increase is

specified for D )

S1 and S2

(only when a serial number access format +2(5)

file register is specified for D )

MOV,MOVP,DMOV,DMOVP,EMOV,EMOVP S1 and D -1(1) 2

BCD,BCDP,BIN,BINP,DBCD,DBCDP,
DBIN,DBINP,FLT,FLTP,DFLT,DFLTP,
S1 and D -1(1) 2
INT,INTP,DINT,DINTP,CML,CMLP,
DCML,DCMLP

2) Except Instructions applicable to subset processing

The following table shows steps depending on the devices.
Devices with Additional Steps Added Steps Example
Intelligent function module device MOV U4\G10 D0
Multiple CPU shared device MOV U3E1\G10000 D0
Link direct device MOV J3\B20 D0
Index register / standard device register MOV Z0 D0
Serial number access format file register 1 MOV ZR123 D0
Extended data register(D) MOV D123
Extended link register(W) MOV W123
32-bit constant DMOV K123 D0
Real constant EMOV E0.1 D0
For even number: (number of characters) / 2
Character string constant $MOV "123" D0
For odd numbers: (number of characters + 1) / 2

(d) In cases where the conditions described in (a) to (c) above overlap, the number of steps
becomes a culmination of the two.

3-38
Example MOV If U1\G10 ZR123 has been designated, a total of 2 steps are added.

MOV
U1\
G10 ZR123
1

2
Serial number access format file registers : 1 step
+
: 1 step
Intelligent function module devices
3

=
Increased by 2 steps

3.8 Counting Step Number

3-39
 3.9 Operation when the OUT, SET/RST, or PLS/PLF
Instructions Use the Same Device

The following describes the operation for executing multiple instructions of the OUT, SET/RST, or
PLS/PLF that use the same device in one scan.

(1) OUT instructions using the same device

Do not program more than one OUT instruction using the same device in one scan. If the
OUT instructions using the same device are programmed in one scan, the specified device
will turn ON or OFF every time the OUT instruction is executed, depending on the operation
result of the program up to the relevant OUT instruction. Since turning ON or OFF of the
device is determined when each OUT instruction is executed, the device may turn ON and
OFF repeatedly during one scan. The following diagram shows an example of a ladder that
turns the same internal relay (M0) with inputs X0 and X1 ON and OFF.
[Ladder]
X0
M0

X1
M0

[Timing Chart]
X0 X0
M0 M0
X1 X1
M0 M0
END END END

ON
X0 OFF
ON
X1 OFF

ON
M0 OFF

M0 turns ON because X1 is ON.

M0 turns OFF because X1 is OFF.
M0 turns ON because X0 is ON. M0 remains OFF because X0 is OFF.

With the refresh type CPU module, when the output (Y) is specified by the OUT instruction,
the ON/OFF status of the last OUT instruction of the scan will be output.

3-40
(2) SET/RST instructions using the same device
(a) The SET instruction turns ON the specified device when the execution command is ON 1
and performs nothing when the execution command is OFF.
For this reason, when the SET instructions using the same device are executed two or
more times in one scan, the specified device will be ON if any one of the execution 2
commands is ON.

(b) The RST instruction turns OFF the specified device when the execution command is
ON and performs nothing when the execution command is OFF. 3
For this reason, when the RST instructions using the same device are executed two or
more times in one scan, the specified device will be OFF if any one of the execution
commands is ON. 4
(c) When the SET instruction and RST instruction using the same device are programmed
in one scan, the SET instruction turns ON the specified device when the SET execution 2
command is ON and the RST instruction turns OFF the specified device when the RST
execution command is ON.
When both the SET and RST execution commands are OFF, the ON/OFF status of the
6
specified device will not be changed.
[Ladder]
X0 7
SET M0

X1
8
RST M0

[Timing Chart]

3.9 Operation when the OUT, SET/RST, or PLS/PLF Instructions Use the Same Device
X0 X0
SET M0 SET M0
X1 X1
RST M0 RST M0
END END END

ON
X0 OFF
ON
X1 OFF

ON
M0 OFF

RST M0 is not executed M0 turns OFF because X1 is ON.

because X0 is OFF.
(M0 remains ON.) SET M0 is not executed
because X0 is OFF.
M0 turns ON because X0 is ON.
(M0 remains ON.)

When using a refresh type CPU module and specifying output (Y) in the SET/RST
instruction, the ON/OFF status of the device at the execution of the last instruction in the
scan is returned as the output (Y).

3-41
 (3) PLS instructions using the same device
The PLS instruction turns ON the specified device when the execution command is turned
ON from OFF.
It turns OFF the device at any other time (OFF to OFF, ON to ON, or ON to OFF).
If two or more PLS instructions using the same device are executed in one scan, each
instruction turns ON the device when the corresponding execution command is turned ON
from OFF and turns OFF the device in other cases.
For this reason, if multiple PLS instructions using the same device are executed in a single
scan, a device that has been turned ON by the PLS instruction may not be turned ON during
one scan.

[Ladder]
X0
PLS M0

X1
PLS M0

[Timing Chart]
• The ON/OFF timing of the X0 and X1 is different. (The specified device does not turn ON
throughout the scan.)
X0 X0
PLS M0 PLS M0
X1 X1
PLS M0 PLS M0
END END END

ON
X0 OFF
ON
X1 OFF

ON ON
M0 OFF

M0 turns OFF because X1 M0 turns ON because X1

status is other than OFF ON. goes ON (OFF ON).
M0 turns ON because M0 turns OFF because X0 status
X0 goes ON (OFF ON). is other than OFF ON.
(M0 remains OFF.)

3-42
 • The X0 and X1 turn ON from OFF at the same time.
X0
PLS M0
X0
PLS M0
1
X1 X1
PLS M0 PLS M0
END END END 2
ON
X0 OFF
ON
3
X1 OFF

ON 4
M0 OFF

M0 turns ON because X1 M0 turns OFF because X1 status is

goes ON (OFF ON). other than OFF ON. 2
(M0 remains ON.) (M0 remains OFF.)

M0 turns ON because M0 turns OFF because X0 status is other

X0 goes ON (OFF ON). than OFF ON.
6
When using a refresh type CPU module and specifying output (Y) in the PLS instructions,
the ON/OFF status of the device at the execution of the last PLS instruction in the scan is
returned as the output (Y). 7
(4) PLF instructions using the same device
The PLF instruction turns ON the specified device when the execution command is turned
OFF from ON.
8
It turns OFF the device at any other time (OFF to OFF, OFF to ON, or ON to ON).
If two or more PLF instructions using the same device are executed in one scan, each
instruction turns ON the device when the corresponding execution command is turned OFF
from ON and turns OFF the device in other cases.

3.9 Operation when the OUT, SET/RST, or PLS/PLF Instructions Use the Same Device
For this reason, if multiple PLF instructions using the same device are executed in a single
scan, a device that has been turned ON by the PLF instruction may not be turn ON during
one scan.

[Ladder]
X0
PLF M0

X1
PLF M0

3-43
 [Timing Chart]
• The ON/OFF timing of the X0 and X1 is different. (The specified device does not turn ON
throughout the scan.)
X0 X0
PLF M0 PLF M0
X1 X1
PLF M0 PLF M0
END END END

ON
X0 OFF
ON
X1 OFF

ON
M0 OFF

M0 turns OFF because X1 M0 turns OFF because X1 status is

status is other than ON OFF. other than ON OFF.
M0 turns ON because (M0 remains OFF.)
X0 goes OFF (ON OFF). M0 turns OFF because X0 status is
other than ON OFF
(M0 remains OFF.)

• The X0 and X1 turn OFF from ON at the same time.

X0 X0
PLF M0 PLF M0
X1 X1
PLF M0 PLF M0
END END END

ON

X0 OFF
ON
X1 OFF

ON
M0 OFF

M0 turns ON because M0 turns OFF because X1 status is

X1 goes OFF (ON OFF). other than ON OFF.
(M0 remains ON.) (M0 remains OFF.)
M0 turns ON because M0 turns OFF because X1 status is
X0 goes OFF (ON OFF). other than ON OFF.
When using a refresh type CPU module and specifying output (Y) in the PLF instructions,
the ON/OFF status of the device at the execution of the last PLF instruction in the scan is
returned as the output (Y).

3-44
3.10 Precautions for Use of File Registers
1
This section explains the precautions for use of the file registers in the QCPU and LCPU.

(1) CPU modules that cannot use file registers

2
The Q00JCPU and Q00UJCPU cannot use the file registers. When using the file registers,
use the CPU module of other than the Q00JCPU and Q00UJCPU.
(2) Setting of file registers to be used 3
When using the file registers, the file registers to be used must be set with the PLC
parameter or QDRSET instruction. (The PLC parameters of the Q00CPU, Q01CPU and
LCPU need not be set since they are preset to "Use file register". QDRSET instructions are 4
not available with LCPU.) If the file registers to be used have not been set, normal operation
cannot be performed with the instructions that use the file registers.
2
Even when file registers to be used are not set in the PLC parameter, a program
that uses file registers can be created. For the CPU module other than the 6
Universal model QCPU and LCPU, an error does not occur when that program is
written to the CPU module.
However, note that the correct data cannot be written/read to/from the file register.
7
For the Universal model QCPU and LCPU, an error occurs if the program where
file registers are used is executed.
8
(3) Securing of file register area
(a) High Performance model QCPU, Process CPU, Redundant CPU, Universal model
QCPU
When using file registers, register the file registers to the standard RAM/memory card to

3.10 Precautions for Use of File Registers

secure the file register area.

(b) Basic Model QCPU (except Q00JCPU)

The file register area has been secured in the standard RAM beforehand. The user
need not secure the file register area.

(c) LCPU
To use the file register, secure a file register area by registering the file register in
standard RAM.

The following table indicates the memories that can use the file registers in each CPU
module.
High Performance model QCPU
Basic Model QCPU
Process CPU
Memory (except Q00JCPU),
Redundant CPU
LCPU
Universal model QCPU(except Q00UJCPU)
Standard RAM

Memory card *1 *2 *3

: Can be registered, : Cannot be registered.

*1: When the flash memory is used, only read from the file registers can be performed. (Write to the flash ROM
cannot be performed.)
*2: When the E2PROM is used, write to the E2PROM can be performed with the PROMWR instruction.
*3: Unusable for the Q00UCPU and Q01UCPU.

3-45
 Remark
For the file register setting method and file register area securing method, refer to
User’s Manual (Functions Explanation, Program Fundamentals) for the CPU
module used.

(4) Designation of file register number in excess of the registered number of points
(a) Basic Model QCPU, High Performance model QCPU, Process CPU, and Redundant
CPU
An error will not occur if data are written or read to or from the file registers that have
numbers greater than the registered number of points. However, note that the read/write
of correct data to/from the file registers cannot be performed.

(b) Universal model QCPU and LCPU

When data are written to or read from the file registers that are not registered, an error
occurs. (Error code: 4101)

(5) File register specifying method

There are the block switching method and serial number access method to specify the file
registers.

(a) Block switching method

In the block switching method, specify the number of used file register points in units of
32k points (one block). For file registers of 32k points or more, specify the file registers
by switching the block No. to be used with the RSET instruction. Specify each block as
R0 to R32767.

RSET K1 Specifying R0 Standard RAM/Memory card

for block 1 R0

to
MOV D0 R0 Block 0

R32767

RSET K2 R0
Specifying R0
for block 2 to Block 1

MOV D0 R0 R32767
R0
to Block 2

3-46
 (b) Serial number access method
In the serial number access method, specify the file registers beyond 32k points with
consecutive device numbers. The file registers of multiple blocks can be used as
consecutive file registers. Use "ZR" as the device name.
1
Standard RAM/Memory card
MOV D0 ZR32768
ZR0 2
to (Block 0)

MOV D0 ZR65536
ZR32767
ZR32768 3
to (Block 1)

ZR65535
4
ZR65536

to (Block 2)
2
(6) Settings and restrictions when refreshing file registers
(a) Settings 6
The settings of refresh devices are as follows.
• Refresh settings for CC-Link IE controller network (Cannot be set on LCPU.)
• Refresh settings for MELSECNET/H (Cannot be set on LCPU.) 7
• Refresh settings for CC-Link
• Auto refresh settings for the intelligent function module 8
• Auto refresh settings for the multiple CPU system (Cannot be set on LCPU.)

(b) Restrictions
The restrictions when specifying file registers to refresh devices are as follows.

3.10 Precautions for Use of File Registers

1) On QCPU, Refresh cannot be performed correctly if the use of file register
which has the same name as the program is specified by the PLC parameter.
When the file register which has the same name as the program is used,
refresh is performed to the data of the file register having the same name as
the program that is set at the last number in the [Program] tab page of PLC
parameter. To read/write the refresh data, specify the file register to the refresh
device after switching the file register to the corresponding one with the
QDRSET instruction.
2) Refresh cannot be performed correctly if the file name of file register or the
drive number is changed by the QDRSET instruction. (QDRSET instructions
are not available with LCPU.)
If the file name of file register or the drive number is changed by the QDRSET
instruction, link refresh is performed to the data of the setting file at the time of
the END instruction execution. To read/write the refresh data, specify the file
register of the setting file at the time of the END instruction execution.
If the drive number is changed by the QDRSET instruction when "ZR" is
specified for the device in the CPU modules other than the Universal model
QCPU, an error (LINK PARA ERROR (3101)) occurs. (Note that an error does
not occur when "R" is specified for the device.)

3-47
 3) When a block number is switched by the RSET instruction, refresh is
performed to the data of the file register (R) in the switched block number.
When a block number is switched by the RSET instruction, refresh is
performed to the data of the file register (R) in the block number at the time of
the END instruction execution. To read/write the refresh data, specify the file
register of the block number at the time of the END instruction execution.

(7) Precautions when file registers in the flash memory are used
This section explains the precautions for use of the flash memory.

(a) The following flash memory can be used.

•Flash card

(b) File registers in the flash memory can be only read in a sequence program.
(Write to the flash memory cannot be performed in a sequence program.)

Sequence program Flash memory

BMOV D100 R0 K10

Write

File register
BMOV R100 D0 K10
Read

When using the flash memory for the file registers, write data in advance.
Using GX Developer or GX Works2, write data to the flash card.

3-48
4 HOW TO READ
INSTRUCTIONS
4

4-1
 The description of instructions that are contained in the following chapters are presented in the
following format.

1)

2)

3)

4)

5)

6)

7)

8)

1) Code used to write instruction (instruction symbol).

2) Section number and general category of instructions described.
3) Shows if instructions are enabled or disabled for each CPU module type.
Icon
Basic model High Performance Universal model Meaning
Process CPU Redundant CPU LCPU
QCPU model QCPU QCPU
A normal icon means the
Basic High LCPU corresponding instruction can be
performance Process Redundant Universal
used.
The icon with Ver. means the
Ver. Ver. Ver. Ver. Ver. Ver. instruction can be used with
High LCPU
Basic performance Process Redundant Universal some restrictions (e.g., function
version, software version).

The icon with (cross) means

Basic High
Process Redundant Universal LCPU the corresponding instruction
performance
cannot be used.

4-2
 9)

4) Indicates ladder mode expressions and execution conditions for instructions.

Non-conditional Executed One Time Executed One
Execution Condition Executed while ON Executed while OFF
Execution at ON Time at OFF
Code recorded on No symbol
description page recorded

5) Indicates the data set for each instruction and the data type.
Data Type Meaning
Bit Bit data or head number in bit data
BIN 16 bits BIN 16-bit data or head number in word device
BIN 32 bits BIN 32-bit data or head number in double word device
BCD 4-digit 4-digit BCD data
BCD 8-digit 8-digit BCD data
Real number Floating decimal point data
character string Character string data
Device name Device name data

4-3
 6) Devices which can be used by the instruction in question are indicated with circle. The types
of devices that can be used are as indicated below:

Internal Devices Link direct device *4 *6 Intelligent

File
(System, User) J \ function Index register
Setting Data Register Constant *5 Others *5
module Zn
Bit Word R, ZR Bit Word
U \G

T, ST, C, *3 J \X
X, Y, M, L, P, I, J, U,
Applicable SM, F, D, W, SD, J \Y J \W DX, DY, N,
R, ZR U \G Z K, H , E, $
devices *1 B, SB, SW, FD, BL, TR,
J \B J \SW
FX, FY *2 @ BL \ S,V
J \SB

*1: For the description for the individual devices, refer to the QnUCPU User’s Manual
(Function Explanation, Program Fundamentals) or Qn(H)/QnPH/QnPRHCPU User’s Manuall
(Function Explanation, Program Fundamentals)
*2: FX and FY can be used only for bit data, and FD only for word data.
*3: When T, ST and C are used for other than the instructions below, only word data can be used.
(Bit data cannot be used.)
[Instructions that can be used with bit data]
LD, LDI, AND, ANI, OR, ORI, LDP, LDF, ANDP, ANDF, ORP, ORF,LDPI, LDFI, ANDPI, ANDFI, ORPI, ORFI,
OUT, RST
*4: Usable with the CC-Link IE controller network, MELSECNET/H, and MELSECNET/10.
*5: Devices which can be set are recorded in the "Constant" and the "Other" columns.

*6: Link direct devices (J \ ) cannot be used with LCPU.

7) Indicates the function of the instruction.

8) Indicates conditions under which error is returned, and error number. See Section 3.6 for
errors not included here.
9) Indicates both ladder and list for simple program example. Also indicates the types of
individual devices used when the program is executed.

4-4
5
7
SEQUENCE
INSTRUCTIONS 7

7
Reference
Category Processing Details
Section
Section 5.1
Contact instruction Operation start, series connection, parallel connection
Ladder block connection, creation of pulses from operation
7
Association instruction Section 5.2
results, store/read operation results
Output instruction Bit device output, pulse output, output reversal Section 5.3
Shift instruction Bit device shift Section 5.4
Master control instruction Master control Section 5.5
Termination instruction Program termination Section 5.6
Program stop, instructions such as no operation which do not
Other instruction Section 5.7
fit in the above categories

5-1
 LD,LDI,AND,ANI,OR,ORI

5.1 Contact Instructions

5.1.1 Operation start, series connection, parallel connection

(LD,LDI,AND,ANI,OR,ORI)
LD,LDI,AND,ANI,OR,ORI

Basic High
performance Process Redundant Universal LCPU

Bit device number / Word device bit designation ( S )

X1/D0.1
LD

X1/D0.1
LDI

X2/D0.2
AND

X2/D0.2
ANI

OR

X3/D0.3

ORI

X3/D0.3

S : Devices used as contacts (bits)

Setting Internal Devices J \ Other

R, ZR U \G Zn Constants
Data Bit Word Bit Word DX, BL

S ––

Function
LD, LDI
(1) LD is the A contact operation start instruction, and LDI is the B contact operation start
instruction. They read ON/OFF information from the designated device*1, and use that as an
operation result.
*1: When a bit designation is made for a word device, the device turns ON or OFF depending on the 1/0 status of
the designated bit.

5-2
 LD,LDI,AND,ANI,OR,ORI

AND, ANI
(1) AND is the A contact series connection instruction, and ANI is the B contact series 1
connection instruction. They read the ON/OFF data of the designated bit device*2, perform
an AND operation on that data and the operation result to that point, and take this value as
the operation result. 2
*2: When a bit designation is made for a word device, the device turns ON or OFF depending on the 1/0 status of
the designated bit.

(2) There are no restrictions on the use of AND or ANI, but the following applies with a 3
peripheral device used in the ladder mode:
(a) Write ......... When AND and ANI are connected in series, a ladder with up to 24 stages
can be displayed. 4
(b) Read......... When AND and ANI are connected in series, a ladder with up to 24 stages
can be displayed. If the number exceeds 24 stages, up to 24 will be
displayed.
5
OR, ORI
(1) OR is the A contact single parallel connection instruction, and ORI is the B contact single 6
parallel connection instruction. They read ON/OFF information from the designated
device*3, and perform an OR operation with the operation results to that point, and use the
resulting value as the operation result. 7
*3: When a bit designation is made for a word device, the device turns ON or OFF depending on the 1/0 status of
the designated bit.

(2) There are no limits on the use of OR or ORI, but the following applies with a peripheral 8
device used in the ladder mode.
(a) Write ......... OR and ORI can be used to create connections of up to 23 ladders.
(b) Read......... OR and ORI can be used to create connections of up to 23 ladders.
The 24th or subsequent ladders cannot be displayed properly.

5.1.1 Operation start, series connection, parallel connection (LD,LDI,AND,ANI,OR,ORI)

5.1 Contact Instructions
Remark
Word device bit designations are made in hexadecimal.
Bit b11 of D0 would be D0.0B.
See 3.2.1 for more information on word device bit designation.

5-3
 LD,LDI,AND,ANI,OR,ORI

Operation Error
(1) There are no operation errors with LD, LDI, AND, ANI, OR, or ORI instruction.

Program Example
(1) A program using the LD, AND, OR, and ORI instructions.

[Ladder Mode] [List Mode]

Step Instruction Device

b15 b5 b0 Bit designated

1 for word
D0 0
device

(2) A program linking contacts using the ANB and ORB instructions.

[Ladder Mode] [List Mode]

Step Instruction Device

b15 b4 b1b0
1 1
D6 0 0
Bit designated
ORB for word
device

ANB

(3) A parallel program with the OUT instruction.

[Ladder Mode] [List Mode]

Step Instruction Device

5-4
 LDP,LDF,ANDP,ANDF,ORP,ORF

5.1.2 Pulse operation start, pulse series connection, pulse parallel

connection (LDP,LDF,ANDP,ANDF,ORP,ORF) 1
LDP,LDF,ANDP,ANDF,ORP,ORF

Basic High
performance Process Redundant Universal LCPU
2

3
Bit device number / Word device bit designation ( S )
4
X1/D0.1
LDP

X1/D0.1 5
LDF

ANDP
X2/D0.2
6
X2/D0.2
ANDF 7
ORP
8
X3/D0.3

ORF

5.1.2 Pulse operation start, pulse series connection, pulse parallel connection (LDP,LDF,ANDP,ANDF,ORP,ORF)
5.1 Contact Instructions
X3/D0.3

S : Devices used as contacts (bits)

Setting Internal Devices J \ Other

R, ZR U \G Zn Constants
Data Bit Word Bit Word DX

S ––

Function
LDP, LDF
(1) LDP is the leading edge pulse operation start instruction, and is ON only at the leading edge
of the designated bit device (when it goes from OFF to ON). If a word device has been
designated, it is ON only when the designated bit changes from 0 to 1.
In cases where there is only an LDP instruction, it acts identically to instructions for the
creation of a pulse that are executed during ON( P).
Ladder using an LDP instruction Ladder not using an LDP instruction
X0 X0
MOV K0 D0 MOVP K0 D0

X0 X0
M0 PLS M0

5-5
 LDP,LDF,ANDP,ANDF,ORP,ORF

(2) LDF is the trailing edge pulse operation start instruction, and is ON only at the trailing edge
of the designated bit device (when it goes from ON to OFF).
If a word device has been designated, it is ON only when the designated bit changes from 1
to 0.

ANDP, ANDF
(1) ANDP is a leading edge pulse series connection instruction, and ANDF is a trailing edge
pulse series connection instruction. They perform an AND operation with the operation
result to that point, and take the resulting value as the operation result.
The ON/OFF data used by ANDP and ANDF are indicated in the table below:
Device Specified in ANDP or ANDF
Bit Designated for ANDP State ANDF State
Bit Device
Word Device
OFF to ON 0 to 1 ON
OFF 0 OFF
ON 1 OFF
ON to OFF 1 to 0 ON

ORP, ORF
(2) ORP is a leading edge pulse parallel connection instruction, and ORF is a trailing edge pulse
serial connection instruction. They perform an OR operation with the operation result to that
point, and take the resulting value as the operation result.
The ON/OFF data used by ORP and ORF are indicated in the table below:
Device Specified in ORP or ORF
Bit Designated for ORP State ORF State
Bit Device
Word Device
OFF to ON 0 to 1 ON
OFF 0 OFF
ON 1 OFF
ON to OFF 1 to 0 ON

Operation Error
(1) There are no operation errors with LDP, LDF, ANDP, ANDF, ORP, or ORF instruction.

Program Example
(1) The following program executes the MOV instruction at input X0, or at the leading edge of
b10 (bit 11) of data register D0.

[Ladder Mode] [List Mode]

Step Instruction Device

*1

*1: Word device bit designation is performed in hexadecimal. Bit b10 of D0 will be D0.A.

5-6
 LDPI,LDFI,ANDPI,ANDFI,ORPI,ORFI

5.1.3 Pulse NOT operation start, pulse NOT series connection,

pulse NOT parallel connection 1
(LDPI,LDFI,ANDPI,ANDFI,ORPI,ORFI)
LDPI,LDFI,ANDPI,ANDFI,ORPI,ORFI
2
Ver.
High
Basic performance Process Redundant Universal LCPU

• QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later. 3

• QnUDE(H)CPU: The serial number (first five digits) is "10102" or later.

4
Bit device number / Word device bit designation ( S )

X1/D0.1
LDPI 5
X1/D0.1
LDFI
6
X2/D0.2
ANDPI
7
X2/D0.2
ANDFI
8
ORPI

X3/D0.3

5.1.3 Pulse NOT operation start, pulse NOT series connection, pulse NOT parallel connection (LDPI,LDFI,ANDPI,ANDFI,ORPI,ORFI)
5.1 Contact Instructions
ORFI

X3/D0.3

S : Devices used as contacts (bits)

Setting Internal Devices J \ Other

R, ZR U \G Zn Constants
Data Bit Word Bit Word DX

S ––

Function
LDPI, LDFI
(1) LDPI is the leading edge pulse NOT operation start instruction that is on only at the leading
edge of the specified bit device (when the bit device goes from on to off) or when the bit
device is on or off. If a word device has been specified, LDPI is on only when the specified
bit is 0, 1, or changes from 1 to 0.

5-7
 LDPI,LDFI,ANDPI,ANDFI,ORPI,ORFI

(2) LDFI is the trailing edge pulse NOT operation start instruction that is on only at the trailing
edge of the specified bit device (when the bit device goes from off to on) or when the bit
device is on or off. If a word device has been specified, LDFI is on only when the specified
bit is 0, 1, or changes from 0 to 1.
Device Specified in LDPI or LDFI
Bit Designated for LDPI State LDFI State
Bit Device
Word Device
OFF to ON 0 to 1 OFF ON
OFF 0 ON ON
ON 1 ON ON
ON to OFF 1 to 0 ON OFF

ANDPI, ANDFI
(1) ANDPI is a leading edge pulse NOT series connection, and ANDFI is a trailing pulse NOT
series connection. ANDPI and ANDFI execute an AND operation with the previous operation
result, and take the resulting value as the operation result.
The on or off data used by ANDPI and ANDFI are indicated in the table below.
Device Specified in ANDPI or ANDFI
Bit Designated for LDPI State LDFI State
Bit Device
Word Device
OFF to ON 0 to 1 OFF ON
OFF 0 ON ON
ON 1 ON ON
ON to OFF 1 to 0 ON OFF

ORPI, ORFI
(1) ORPI is a leading edge pulse NOT parallel connection, and ORFI is a trailing pulse NOT
parallel connection. ORPI and ORFI execute an OR operation with the previous operation
result, and take the resulting value as the operation result.
The on or off data used by ORPI and ORFI are indicated in the table below.
Device Specified in ORPI or ORFI
Bit Designated for ORPI State ORFI State
Bit Device
Word Device
OFF to ON 0 to 1 OFF ON
OFF 0 ON ON
ON 1 ON ON
ON to OFF 1 to 0 ON OFF

Operation Error
(1) There are no operation errors with LDPI, LDFI, ANDPI, ANDFI, ORPI, or ORFI instruction.

5-8
 LDPI,LDFI,ANDPI,ANDFI,ORPI,ORFI

Program Example
1
(1) The following program stores 0 into D0 when X0 is on, off, or turns from on to off, or M0 is
on, off, or turns from off to on.
[Ladder Mode] [List Mode] 2
Step Instruction Device

(2) The following program stores 0 into D0 when X0 is on and b10 (bit 11) of D0 is on, off, or 5
turns from on to off.
Ladder Mode] [List Mode]
Step Instruction Device 6

5.1.3 Pulse NOT operation start, pulse NOT series connection, pulse NOT parallel connection (LDPI,LDFI,ANDPI,ANDFI,ORPI,ORFI)
5.1 Contact Instructions

5-9
 ANB,ORB

5.2 Association Instructions

5.2.1 Ladder block series connection and parallel connection

(ANB,ORB)
ANB,ORB

Basic High
performance Process Redundant Universal LCPU

ANB

ANB

Block A Block B

Block A

ORB

ORB
Block B
For parallel connection of 1 contact,
OR or ORI is used.

Setting Internal Devices J \

R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
–– ––

Function
ANB
(1) Performs an AND operation on block A and block B, and takes the resulting value as the
operation result.
(2) The symbol for ANB is not the contact symbol, but rather is the connection symbol.
(3) When programming in the list mode, up to 15 ANB instructions (16 blocks) can be written
consecutively.
ORB
(1) Conducts an OR operation on Block A and Block B, and takes the resulting value as the
operation result.
(2) ORB is used to perform parallel connections for ladder blocks with two or more contacts.
For ladder blocks with only one contact, use OR or ORI; there is no need for ORB in such
cases.
[Ladder Mode] [List Mode]
X0 X1
Y10 0 LD X0
0
1 AND X1
X2 X3 2 LD X2
3 AND X3
4 ORB
X4 5 OR X4
6 OUT Y10

(3) The ORB symbol is not the contact symbol, but rather is the connection symbol.
(4) When programming in the list mode, it is possible to use up to 15 ORB instructions
successively (16 blocks).

5-10
 ANB,ORB

Operation Error
1
(1) There are no operation errors associated with ANB or ORB instruction.

2
Program Example
(1) A program using the ANB and ORB instructions.
3

[Ladder Mode] [List Mode]

4
Step Instruction Device

5.2.1 Ladder block series connection and parallel connection (ANB,ORB)

5.2 Association Instructions

5-11
 MPS,MRD,MPP

5.2.2 Operation results push,read,pop (MPS,MRD,MPP)

MPS,MRD,MPP

Basic High
performance Process Redundant Universal LCPU

In the ladder display, MPS, MRD and MPP are not displayed.
Command Command
MPS
Command
MRD

Command
MPP

Setting Internal Devices J \

R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
–– ––

Function
MPS
(1) Stores the memory of the operation result (ON or OFF) immediately prior to the MPS
instruction.
(2) Up to 16 MPS instructions can be used successively.
If the MPP instruction is used during this process, the number of uses calculated for the
MPS instruction will be decremented by one.

MRD
(1) Reads the operation result stored for the MPS instruction, and uses that result to perform the
operation in the next step.
MPP
(1) Reads the operation result stored for the MPS instruction, and uses that result to perform the
operation in the next step.
(2) Clears the operation results stored by the MPS instruction.
(3) Subtracts 1 from the number of MPS instruction times of use.

5-12
 MPS,MRD,MPP

1. The following shows ladders both using and not using the MPS, MRD, and 1
MPP instructions.
Ladder Using the MPS, MRD and MPP Instruction Ladder not Using MPS, MRD, and MPP Instructions
2
X0 X1 X2 X0 X1 X2
Y10 Y10
X3 X4
Y11
X0 X1 X3 X4
Y11
3
X5 X0 X1 X5
Y12 Y12
4
2. The MPS and MPP instructions must be used the same number of times.
Failure to observe this will not correctly display the ladder in the ladder mode of
the peripheral device.
5

6
Operation Error
(1) There are no errors associated with the MPS, MRD, or MPP instruction. 7

8
Program Example
(1) A program using the MPS, MRD, and MPP instructions.
[Ladder Mode] [List Mode]

5.2.2 Operation results push,read,pop (MPS,MRD,MPP)

5.2 Association Instructions
1) Step Instruction Device

1)
2)
3) 4) 2)

3)
5) 4)

6) 5)
7)
6)

8)
7)

9) 8)

10) 9)

10)

5-13
 MPS,MRD,MPP

(2) A program using the MPS and MPP instructions successively.

[Ladder Mode]

[List Mode]

Step Instruction Device

5-14
 INV

5.2.3 Operation results inversion (INV)

INV
1
Basic High
performance Process Redundant Universal LCPU
2

3
Command
INV
4
Setting Internal Devices J \
R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
–– –– 5

Function 6
Inverts the operation result immediately prior to the INV instruction.
Operation Result Immediately Prior to the Operation Result Following the Execution of
7
INV Instruction the INV Instruction
OFF ON
ON OFF 8

Operation Error

5.2.3 Operation results inversion (INV)

5.2 Association Instructions
(1) There are no operation errors associated with the INV instruction.

Program Example
(1) A program which inverts the X0 ON/OFF data, and outputs from Y10.
[Ladder Mode] [List Mode]

Step Instruction Device

[Timing Chart]
ON
OFF
X0

ON
Y10
OFF

5-15
 INV

1. The INV instruction operates based on the results of calculation made until the
INV instruction is given. Accordingly, use it in the same position as that of the
AND instruction.
The INV instruction cannot be used at the LD and OR positions.
2. When a ladder block is used, the operation result is inverted within the range of
the ladder block. To operate a ladder using the INV instruction in combination
with the ANB instruction, pay attention to the range that will be inverted.
Range inverted
M0 M1 M2
0 Y10

M10 M20
ANB

10 END

For details of the ANB instruction, refer to Section 5.2.1

5-16
 MEP,MEF

5.2.4 Operation result conversions (MEP,MEF)

MEP,MEF
1
Basic High
performance Process Redundant Universal LCPU

Command
MEP 3

Command
MEF 4

Setting
Data
Internal Devices
Bit Word
R, ZR
Bit
J \
Word
U \G Zn Constants Other 5
–– ––

6
Function
MEP 7
(1) If operation results up to the MEP instruction are leading edge (from OFF to ON), goes ON
(continuity status).
If operation results up to the MEP instruction are anything other than leading edge, goes
OFF (non-continuity status). 8
(2) Use of the MEP instruction simplifies pulse conversion processing when multiple contacts are
connected in series.
MEF
(1) If operation results up to the MEF instruction are trailing edge (from ON to OFF), goes ON

5.2.4 Operation result conversions (MEP,MEF)

5.2 Association Instructions
(continuity status).
If operation results up to the MEF instruction are anything other than trailing edge, goes OFF
(non-continuity status).
(2) Use of the MEF instruction simplifies pulse conversion processing when multiple contacts are
connected in series.

Operation Error
(1) There are no operation errors associated with the MEP or MEF instruction.

Program Example
(1) A program which performs pulse conversion to the operation results of X0 and X1
[Ladder Mode] [List Mode]
Step Instruction Device

1. The MEP and MEF instructions will occasionally not function properly when
pulse conversion is conducted for a contact that has been indexed by a
subroutine program or by the FOR to NEXT instructions. If pulse conversion is
to be conducted for a contact that has been indexed by a subroutine program
or by the FOR to NEXT instructions, use the EGP/EGF instructions.
2. Because the MEP and MEF instructions operate with the operation results
immediately prior to the MEP and MEF instructions, the AND instruction should
be used at the same position. The MEP and MEF instructions cannot be used
at the LD or OR position.

5-17
 EGP,EGF

5.2.5 Pulse conversions of edge relay operation results (EGP,EGF)

EGP,EGF

Basic High
performance Process Redundant Universal LCPU

Command D
EGP
Command D
EGF

D : Edge relay number where operation results are stored (bits)

Setting Internal Devices J \ Other

R, ZR U \G Zn Constants
Data Bit Word Bit Word V

D ––

Function
EGP
(1) Operation results up to the EGP instruction are stored in memory by the edge relay (V).
(2) Goes ON (continuity status) at the leading edge (OFF to ON) of the operation result up to the
EGP instruction.
If the operation result up to the EGP instruction is other than a leading edge (i.e., from ON to
ON, ON to OFF, or OFF to OFF), it goes OFF (non-continuity status).
(3) The EGP instruction is used for subroutine programs, and for conducting pulse operations
for programs designated by indexing between the FOR and NEXT instructions.
(4) The EGP instruction can be used like an AND instruction.
EGF
(1) Operation results up to the EGF instruction are stored in memory by the edge relay (V).
(2) Goes ON at the trailing edge (from ON to OFF) of the operation result up to the EGF
instruction.
If the operation result up to the EGF instruction is other than a trailing edge (i.e., from OFF to
ON, ON to ON, or OFF to OFF), it goes OFF (non-continuity status).
(3) The EGF instruction is used for subroutine programs, and for conducting pulse operations
for programs designated by indexing between the FOR and NEXT instructions.
(4) The EGF instruction can be used like an AND instruction.

Operation Error
(1) There are no operation errors associated with the EGP or EGF instruction.

5-18
 EGP,EGF

Program Example
1
(1) A program using the EGP instruction in the subroutine program using the EGD instruction
[Ladder Mode] [List Mode]
2
Step Instruction Device

7
[Operation]
END processing (1) (2) (1) (2) (1) (2) (1) (2) (1) (2) 8
ON ON
X0 OFF OFF

ON
X1 OFF

5.2.5 Pulse conversions of edge relay operation results (EGP,EGF)

5.2 Association Instructions
ON Turns OFF as X0 remains ON. ON
V0 OFF
Turns ON at the leading ON
edge of X0. Turns OFF as X1 remains ON.
V1 OFF
Turns ON at the leading edge of X1.
D0 1 2

D1 1

1. Since the EGP and EGF instructions are executed according to the operation
results performed immediately before the EGP/EGF instructions, these
instructions must be used at the same position as the AND instruction.
(Refer to Section 5.1.1.)
The EGP and EGF instruction cannot be used at the position of the LD or OR
instruction.
2. EGP and EGF instructions cannot be used at the ladder block positions shown
below.

X0 X1 V0
SET M0

X2

5-19
 OUT

5.3 Output Instructions

5.3.1 Out instruction (excluding timers, counters, and annunciators) (OUT)

OUT

Basic High
performance Process Redundant Universal LCPU

Bit device number ( D )

Command
OUT Y35

Word device
Command bit designation ( D )
D0.5

D : Number of the device to be turned ON and OFF (bits)

Setting Internal Devices J \ Other

R, ZR U \G Zn Constants
Data Bit Word Bit Word DY

(Other
D than T, C, ––
or F)

Function
(1) Operation results up to the OUT instruction are output to the designated device.
(a) When Using Bit Devices
Operation Results Coil
OFF OFF
ON ON

(b) When Bit Designation has been Made for Word Device
Operation Results Bit Designated
OFF 0
ON 1

Operation Error
(1) There are no operation errors associated with the OUT instruction.

5-20
 OUT

Program Example
1
(1) When using bit devices
[Ladder Mode] [List Mode]
2
Step Instruction Device

(2) When bit designation has been made for word device
5
[Ladder Mode] [List Mode]
Step Instruction Device
6

8
b15 b7 b6 b5 b0

D0

5.3.1 Out instruction (excluding timers, counters, and annunciators) (OUT)

5.3 Output Instructions
Remark
The number of basic steps for the OUT instructions is as follows:
• When using internal device or file register (R) :1
• When using direct access output (DY) :2
• When using serial number access format file register
(Only for Universal model QCPU and LCPU) :2
(Basic Model QCPU, High Performance model QCPU, Process CPU,
and Redundant CPU) :3
• Devices other than above :3

5-21
 OUT T,OUTH T

5.3.2 Timers (OUT T,OUTH T)

OUT T,OUTH T

Basic High
performance Process Redundant Universal LCPU

Command K50 Set value

T0 Setting in the range
from 1 to 32767 is valid.
OUT T
(Low-speed timer) Command D10 Set value
T0 Data register value in
the range from 1 to
32767 is valid.

Command H K50 Set value

T0 Setting in the range
from 1 to 32767 is valid.
OUTH T
(High-speed timer) Command H D10 Set value
T0 Data register value in
the range from 1 to
32767 is valid.

Command K50 Set value

ST0 Setting in the range
from 1 to 32767 is valid.
OUT ST
(Low-speed retentive timer) Command D10 Set value
ST0 Data register value in
the range from 1 to
32767 is valid.

Command H K50 Set value

ST0 Setting in the range
from 1 to 32767 is valid.
OUTH ST
(High-speed retentive timer) Command H D10 Set value
ST0 Data register value in
the range from 1 to
32767 is valid.

D : Timer number (bit)

Set value : Value set for timer (BIN 16 bits *1)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K

D (Only T) –– –– –– –– –– –– ––

(Other
Set value –– –– –– *2 ––
than T, C)
*1: The value setting for the timer cannot be designated indirectly.

@D0 Indirect designation is

T0 not permitted.

See Section 3.4 for further information on indirect designation.

*2: Timer values can be set only as a decimal constant (K). Hexadecimal constants (H) and real numbers
cannot be used for timer settings.

Function
(1) When the operation results up to the OUT instruction are ON, the timer coil goes ON and the
timer counts up to the value that has been set; when the time up status (total numeric value
is equal to or greater than the setting value), the contact responds as follows:
A Contact Continuity
B Contact Non-continuity

5-22
 OUT T,OUTH T

(2) The contact responds as follows when the operation result up to the OUT instruction is a
change from ON to OFF:
Present Value of Prior to Time Up After Time Up
1
Type of Timer Timer Coil
Timer A Contact B Contact A Contact B Contact
Low speed timer
High speed timer
OFF 0 Non-continuity Continuity Non-continuity Continuity 2
Low speed
retentive timer Maintains the
High speed
OFF
present value
Non-continuity Continuity Continuity Non-continuity
3
retentive timer

(3) To clear the present value of a retentive timer and turn the contact OFF after time up, use the
RST instruction. 4
(4) A negative number ( 32768 to 1) cannot be set as the setting value for the timer.*3
If the setting value is 0, the timer will time out when the time the OUT instruction is executed.
*3: When specifying a setting value for the timer using a word device (D, W, R, ZR, J \ or U \ ), whether
5
the value is in the setting range is not checked. Check the value in the user program so that a negative
number is not set.
(5) The following processing is conducted when the OUT instruction is executed: 6
• OUT T coil turned ON or OFF
• OUT T contact turned ON or OFF
• OUT T present value updated 7
In cases where a JMP instruction or the like is used to jump to an OUT T instruction while
the OUT T instruction is ON, no present value update or contact ON/OFF operation is
conducted. 8
Also, if the same OUT T instruction is conducted two or more times during the same scan,
the present value of the number of repetitions executed will be updated.
(6) Indexing for timer coils or contacts can be conducted only by Z0 or Z1.
Timer setting value has no limitation for indexing.

5.3.2 Timers (OUT T,OUTH T)

5.3 Output Instructions
Remark
1. Timer's time limit
Time limit of the timer is set in the PLC system of the PLC parameter dialog
box.
Basic Model QCPU,
Universal model QCPU,
High Performance model QCPU,
LCPU
Type of Timer Process CPU, Redundant CPU
Setting Setting
Setting Range Setting Range
Unit Unit
Low speed timer
1 ms to 1000 ms 1 ms to 1000 ms
Low speed 1 ms 1 ms
(Default: 100 ms) (Default: 100 ms)
retentive timer
High speed timer
0.1 ms to 100.0 ms 0.01 ms to 100.0 ms
High speed 0.1 ms 0.01 ms
(Default: 10.0 ms) (Default: 10.0 ms)
retentive timer

2. For information on timer counting methods, User's Manual

(Functions Explanation, Program Fundamentals) for the CPU module used.
3. The number of basic steps of the OUT C instruction is 4.

Operation Error
(1) There are no operation errors associated with the OUT T instruction.

5-23
 OUT T,OUTH T

Caution
(1) When creating a program in which the operation the timer contact triggers the operation of
other timer, create the program for the timer that operates later first.
In the following cases, all timers go ON at the same scan if the program is created in the
order the timers operate.
• If the set value is smaller than a scan time.
• If "1" is set
Example

• For timers T0 to T2, the program is created in the order the timer operates later.
T1 K1
T2 T2 timer starts measurement from the next scan after
turning ON of the contact of T1 timer.
T0 K1
T1 T1 timer starts measurement from the next scan after
turning ON of the contact of T0 timer.
X0 K1
T0 T0 timer starts measurement when X0 is turned ON.

• For timers T0 to T2, the program is created in the order of timer operation.
X0 K1
T0 T0 timer starts measurement when X0 is turned ON.

T0 K1
T1

Contacts of T1 and T2 timers are turned ON

T1 K1 when the contact of T0 timer is turned ON.
T2

5-24
 OUT T,OUTH T

Program Example
1
(1) The following program turns Y10 and Y14 ON 10 seconds after X0 has gone ON.
[Ladder Mode] [List Mode]
*3
2
Step Instruction Device

*3: The setting value of the low-speed timer indicates its default time limit (100 ms). 5
(2) The following program uses the BCD data at X10 to X1F as the timer's set value.
[Ladder Mode] 6
Converts the BCD data at X10 to X1F to BIN
and stores the converted value at D10.
When X2 is turned ON, T2 starts measurement
7
using the data stored in D10 as the set value.
Y15 goes ON at the count-up of T2.
8

[List Mode]

Step Instruction Device

5.3.2 Timers (OUT T,OUTH T)

5.3 Output Instructions
(3) The following program turns Y10 ON 250 ms after X0 goes ON.
[Ladder Mode] [List Mode]
*4 Instruction Device
Step

*4: The setting value of the high-speed timer indicates its default time limit (10 ms).

5-25
 OUT C

5.3.3 Counter (OUT C)

OUT C

Basic High
performance Process Redundant Universal LCPU

Command K50 Set value

C0 Setting in the range
from 1 to 32767 is valid.
OUT C
Command D10 Set value
C1 Data register value in
the range from 1 to
32767 is valid.

D : Counter number (bits)

Set value : Counter setting value (BIN 16 bits *1)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K

D (Only C) –– –– –– –– –– –– ––

(Other
Set value –– –– –– *2 ––
than T, C)
*1: Counter value cannot be set by indirect designation.

@D0 Indirect designation is

C0 not permitted.

See Section 3.4 for further information on indirect designation.

*2: Counter value can be set only with a decimal constant (K). A hexadecimal constant (H) or a real number
cannot be used for the counter value setting.

Function
(1) When the operation results up to the OUT instruction change from OFF to ON, 1 is added to
the present value (count value) and the count up status (present value set value), and the
contacts respond as follows:
A Contact Continuity
B Contact Non-continuity

(2) No count is conducted with the operation results at ON. (There is no need to perform pulse
conversion on count input.)
(3) After the count up status is reached, there is no change in the count value or the contacts
until the RST instruction is executed.
(4) A negative number ( 32768 to 1) cannot be set as the setting value for the timer.
If the set value is 0, the processing is identical to that which takes place for 1.
(5) Indexing for the counter coil and contact can use only Z0 and Z1.
Counter setting value has no limitation for indexing.

Remark
1. For counter counting methods, refer to the User's Manual
(Functions Explanation, Program Fundamentals) for the CPU module used.
2. The number of basic steps of the OUT C instruction is 4.

5-26
 OUT C

Operation Error
1
(1) There are no operation errors associated with the OUT C instruction.

2
Program Example
(1) The following program turns Y30 ON after X0 has gone ON 10 times, and resets the counter 3
when X1 goes ON.
[Ladder Mode] [List Mode]

Step Instruction Device 4

(2) The following program sets the value for C10 at 10 when X0 goes ON, and at 20 when X1 7
goes ON.
[Ladder Mode]

Stores 10 at D0 when X0 goes ON.

8
Stores 20 at D0 when X1 goes ON.

C10 executes counting using the data

stored in D0 as the set value.

5.3.3 Counter (OUT C)

5.3 Output Instructions
Y30 goes ON at the count-up of C10.

[List Mode]

Step Instruction Device

5-27
 OUT F

5.3.4 Annunciator output (OUT F)

OUT F

Basic High
performance Process Redundant Universal LCPU

Annunciator number
Command
OUT F F35

D : Number of the annunciator to be turned ON (bits)

Setting Internal Devices J \

R, ZR U \G Zn Constants Other
Data Bit Word Bit Word

D (Only F) ––

Function
(1) Operation results up to the OUT instruction are output to the designated annunciator.
(2) The following responses occur when an annunciator (F) is turned ON.

• The "USER"/"ERR." LED goes ON.

• The annunciator numbers which are ON (F numbers) are stored in special registers
(SD64 to SD79).
• The value of SD63 is incremented by 1.
(3) If the value of SD63 is 16 (which happens when 16 annunciators are already ON), even if a
new annunciator is turned ON, its number will not be stored at SD64 to SD79.
(4) The following responses occur when the annunciator is turned OFF by the OUT instruction.
The coil goes OFF, but there are no changes in the status of the "USER" / "ERR." LED and
the contents of the values stored in SD63 to SD79.
Use the RST F instruction to make the "USER"/"ERR." LED go OFF as well as to delete
the annunciator which was turned OFF by the OUT F instruction from SD63 to SD79.

5-28
 OUT F

Operation Error
1
(1) There are no operation errors associated with the OUT F instruction.

Remark
2
1. For details of annunciators, refer to the User's Manual (Functions Explanation,
Program Fundamentals) for the CPU module used. 3
2. The number of basic steps for the OUT module F instruction is 2.
3. The table below shows which CPU module features either the LED display
device on front of the CPU module or "USER" LED. 4
Type of LED CPU Module Type Name
High Performance model QCPU, Process CPU, Redundant
"USER" LED
CPU, Universal model QCPU, LCPU
5
"ERR." LED Basic model QCPU

Program Example 7
(1) The following program turns F7 ON when X0 goes ON, and stores the value 7 from SD64 to
SD79.
[Ladder Mode] [List Mode]
8
Step Instruction Device

5.3.4 Annunciator output (OUT F)

5.3 Output Instructions
[Operation]
X0 ON
Adds 1
SD63 0 SD63 1
SD64 0 SD64 7
SD65 0 SD65 0
SD66 0 SD66 0
SD67 0 SD67 0

SD79 0 SD79 0

5-29
 SET

5.3.5 Setting devices (except for annunciators) (SET)

SET

Basic High
performance Process Redundant Universal LCPU

Command
SET SET D

D : Bit device number to be set (ON)/Word device bit designation (bits)

Setting Internal Devices J \ Other

R, ZR U \G Zn Constants
Data Bit Word Bit Word BL, DY

D (Other than T, C) ––

Function
(1) When the execution command is turned ON, the status of the designated devices becomes
as shown below:
Device Device Status
Bit device Coils and contacts turned ON
When Bit Designation has been Made for Word Device Designation bit set at 1

(2) Devices turned ON by the instruction remain ON when the same command is turned OFF.
Devices turned ON by the SET instruction can be turned OFF by the RST instruction.
Command ON
X5
SET Y10 X5 OFF
ON
X7
RST Y10 X7 OFF
Command
ON

Y10 OFF

(3) When the execution command is OFF, the status of devices does not change.

5-30
 SET

Operation Error
1
(1) There are no operation errors associated with the SET instruction.

2
Program Example
(1) The following program sets Y8B (ON) when X8 goes ON, and resets Y8B (OFF) when X9
3
goes ON.
[Ladder Mode] [List Mode]
4
Step Instruction Device

6
(2) The following program sets the value of D0 bit 5 (b5) to 1 when X8 goes ON, and set the bit
value to 0 when X9 goes ON. 7
[Ladder Mode] [List Mode]

Step Instruction Device

Sets b5 of D0 at 1. 8
Sets b5 of D0 at 0.

5.3.5 Setting devices (except for annunciators) (SET)

5.3 Output Instructions
B5 B0
D0

Remark
1. The number of basic steps for the SET instruction is as follows:
• When internal device or file register (R0 to R32767) are in use : 1
• When direct access output (DY) or SFC program device (BL) are in use
:2
• When using serial number access format file register
(Only for Universal model QCPU and LCPU) :2
(Basic Model QCPU, High Performance model QCPU, Process CPU,
and Redundant CPU) :3
• When some other device is in use :3
2. When using X as a device, use the device numbers that are not used for the
actual input. If the same number is used for the actual input device and input X,
the data of the actual input will be written over the input X specified in the SET
instruction.

5-31
 RST

5.3.6 Resetting devices (except for annunciators) (RST)

RST

Basic High
performance Process Redundant Universal LCPU

Command
RST RST D

D : Bit device number to be reset/ Word device bit designation (bits)

Word device number to be reset (BIN 16 bits)

Setting Internal Devices J Other

R, ZR U G Zn Constants
Data Bit Word Bit Word DY

D ––

Function
(1) When the execution command is turned ON, the status of the designated devices becomes
as shown below:
Device Device Status
Bit device Turns coils and contacts OFF
Timers and counters Sets the present value to 0, and turns coils and contacts OFF
When Bit Designation has been Made for Word Device Sets value of designated bit to 0
Word devices other than timers and counters Sets contact to 0

(2) When the execution command is OFF, the status of devices does not change.
(3) The functions of the word devices designated by the RST instruction are identical to the
following ladder:

Command Command
X10 X10
RST D50 MOV K0 D50

Device number Device number

5-32
 RST

Operation Error
1
(1) There are no operation errors associated with the RST instruction.

Remark
2
The basic number of steps of the RST instruction is as follows.
a) For bit processing
3
• Internal device (bit to be specified by bit device or word device) : 1
• Direct access output :2
• Timer, counter :4
4
• When using serial number access format file register
(Only for Universal model QCPU and LCPU) :2
(Basic Model QCPU, High Performance model QCPU, Process CPU,
and Redundant CPU) :3
5
• Other than above :3
b) For word processing
• Internal device :2 6
• Index resister :2
• When using serial number access format file register
(Only for Universal model QCPU and LCPU) :2 7
(Basic Model QCPU, High Performance model QCPU, Process CPU,
and Redundant CPU) :3
• Other than above :3 8

Program Example

5.3.6 Resetting devices (except for annunciators) (RST)

5.3 Output Instructions
(1) The following program sets the value of the data register to 0.
[Ladder Mode]

Stores the contents at X10 to X1F in D8

when X0 is turned ON.
Resets D8 to 0 when X5 is turned ON.

[List Mode]

Steps Instruction Device

5-33
 RST

(2) The following program resets the 100 ms retentive timer and counter.
[Ladder Mode]

When ST225 is set as retentive timer, it is

turned ON when X4 ON time reaches 30 min.
Counts the number of times ST225 was
turned ON.
Resets the coil, contact and present value of
ST225 when the contact of ST225 is turned ON.
Y55 goes ON at the count-up of C23.

Resets C23 to 0 when X5 is turned ON.

[List Mode]
Step Instruction Device

5-34
 SET F,RST F

5.3.7 Setting and resetting the annunciators (SET F,RST F)

SET F,RST F
1
Basic High
performance Process Redundant Universal LCPU

SET
Command
SET D
3
Command
RST RST D
4
SET D : Number of the annunciator to be set (F number) (bits)

RST D : Number of the annunciator to be reset (F number) (bits) 5

Setting Internal Devices J \
R, ZR U \G Zn Constants Other
Data

D
Bit

(Only F)
Word Bit Word

––
6

7
Function
SET
8
(1) The annunciator designated by D is turned ON when the execution command is turned ON.
(2) The following responses occur when an annunciator (F) is turned ON.
• The "USER" LED goes ON.*1
• The annunciator numbers which are ON (F numbers) are stored in special registers

5.3.7 Setting and resetting the annunciators (SET F,RST F)

5.3 Output Instructions
(SD64 to SD79).
• The value of SD63 is incremented by 1.
*1: When using the Basic model QCPU, the "ERR."LED goes ON.
(3) If the value of SD63 is 16 (which happens when 16 annunciators are already ON), even if a
new annunciator is turned ON, its number will not be stored at SD64 to SD79.
RST
(1) The annunciator designated by D is turned OFF when the execution command is turned ON.
(2) The annunciator numbers (F numbers) of annunciators that have gone OFF are deleted
from the special registers (SD64 to SD79), and the value of SD63 is decremented by 1.

Remark
1. For details of annunciators,refer to the User's Manual (Functions Explanatio
Program Fundamentals) for the CPU module used.
2. The number of basic steps for the SET F and RST F instructions is 2.

5-35
 SET F,RST F

(3) When the value of SD63 is "16", the annunciator numbers are deleted from SD64 to SD79
by the use of the RST instruction. If the annunciators whose numbers are not registered in
SD64 to SD79 are ON, these numbers will be registered.
If all annunciator numbers from SD64 to SD79 are turned OFF, the LED display device on
the front of the CPU module, or the "USER" LED, will be turned OFF.*2
*2: When using the Basic model QCPU, the "ERR." LED goes OFF.

[Operations which take place when SD63 is 16]

Turns F30 ON. Resets F90.

SD63 16 16 16
SD64 233 SD64 233 SD64 233
SD65 90 SD65 90 SD65 700
SD66 700 SD66 700 SD66 28 F number in
SD67 is stored.

SD77 145
SD78 145 SD78 145 SD78 1027
SD79 1027 SD79 1027 SD79 30
Contents of SD63 and F30, which was ON,
those of SD64 to SD79 is stored in SD79.
are not changed.

Operation Error
(1) There are no operation errors associated with the SET F or RST F instruction.

Program Example
(1) The following program turns annunciator F11 ON when X1 goes ON, and stores the value 11
at the special register (SD64 to SD79). Further, the program resets annunciator F11 if X2
goes ON, and deletes the value 11 from the special registers (SD64 to SD79).
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
When X1 is ON When X2 is ON
Adds 1 Subtracts 1
SD63 0 SD63 1 SD63 0
SD64 0 SD64 11 SD64 0
SD65 0 SD65 0 SD65 0
SD66 0 SD66 0 SD66 0
SD67 0 SD67 0

SD78 0 SD78 0 SD78 0

SD79 0 SD79 0 SD79 0

5-36
 PLS,PLF

5.3.8 Leading edge and trailing edge outputs (PLS,PLF)

PLS,PLF
1
Basic High
performance Process Redundant Universal LCPU
2

3
Command
PLS PLS D

Command 4
PLF PLF D

D : Pulse conversion device (bits)

5
Setting Internal Devices J \ Other
R, ZR U \G Zn Constants
Data Bit Word Bit Word DY

D ––
6

Function 7

PLS
8
(1) Turns ON the designated device when the execution command is turned OFF ON, and
turns OFF the device in any other case the execution command is turned OFF ON (i.e., at
ON ON, ON OFF or OFF OFF of the execution command).
When there is one PLS instruction for the device designated by D during one scan, the

5.3.8 Leading edge and trailing edge outputs (PLS,PLF)

5.3 Output Instructions
specified device turns ON one scan.
See Section 3.9 for the operation to be performed when the PLS instruction for the same
device is executed more than once during one scan.
ON

X5 OFF
X5
PLS M0 ON

M0 OFF
1 scan 1 scan

(2) If the RUN/STOP key switch is changed from RUN to STOP after the execution of the PLS
instruction, the PLS instruction will not be executed again even if the switch is set back to
RUN.
X0 Operating the Operating the
PLS M0 RUN/STOP RUN/STOP
key switch of key switch of
Operating the
Operating the CPU module CPU module
RUN/STOP
RUN/STOP key "STOP RUN". "STOP RUN".
key switch of
switch of CPU module CPU module
LD X0 "RUN STOP". "RUN STOP".
LD X0 LD X0
PLS
PLS M0 PLS M0
END 0 M0 END END 0
CPU operation CPU operation
ON stop time stop time

X0 OFF ON

M0 OFF
1 scan of PLS M0

5-37
 PLS,PLF

(3) When designating a latch relay (L) for the execution command and turning the power supply
OFF to ON with the latch relay ON, the execution command turns OFF to ON at the first
scan, executing the PLS instruction and turning ON the designated device.
The device turned ON at the first scan after power-ON turns OFF at the next PLS instruction.

PLF
(1) Turns ON the designated device when the execution command is turned ON OFF, and
turns OFF the device in any other case the execution command is turned ON OFF (i.e., at
OFF OFF, OFF ON or ON ON of the execution command).
When there is one PLF instruction for the device designated by D during one scan, the
specified device turns ON one scan.
See Section 3.9 for the operation to be performed when the PLF instruction for the same device
is executed more than once during one scan.
ON

X5 OFF
X5
PLF M0 ON

M0 OFF

1 scan 1 scan

(2) If the RUN/STOP key switch is changed from RUN to STOP after the execution of the PLF
instruction, the PLF instruction will not be executed again even if the switch is set back to
RUN.

Note that the device designated by D may remain ON for more than one scan if
the PLS or PLF instruction is jumped by the CJ instruction or if the executed
subroutine program was not called by the CALL instruction.

Operation Error
(1) There are no operation errors associated with the PLS or PLF instruction.

Program Example
(1) The following program executes the PLS instruction when X9 goes ON.
[Ladder Mode] [List Mode]

Step Instruction Device

[Timing Chart]
ON

X9 OFF
ON

M9 OFF
1 scan

5-38
 PLS,PLF

(2) The following program executes the PLF instruction when X9 goes OFF.
[Ladder Mode] [List Mode] 1
Step Instruction Device

[Timing Chart] 3
ON

X9 OFF
ON 4
M9 OFF
1 scan
5

5.3.8 Leading edge and trailing edge outputs (PLS,PLF)

5.3 Output Instructions

5-39
 FF

5.3.9 Bit device output reverse (FF)

FF

Basic High
performance Process Redundant Universal LCPU

Command
FF FF D

D : Device number of the device to be reversed (bits)

Setting Internal Devices J \ Other

R, ZR U \G Zn Constants
Data Bit Word Bit Word DY

D ––

Function
(1) Reverses the output status of the device designated by D when the execution command is
turned OFF ON.
Device Status
Device
Prior to FF Execution After FF Execution
OFF ON
Bit device
ON OFF
0 1
Bit designated for word device
1 0

Operation Error
(1) There are no operation errors associated with the FF instruction.

Program Example
(1) The following program reverses the output of Y10 when X9 goes ON.
[Ladder Mode] [List Mode]

Step Instruction Device

[Timing Chart]
ON
X9 OFF

ON
Y10 OFF

5-40
 FF

(2) The following program reverses b10 (bit 10) of D10 when X0 goes ON.
[Ladder Mode] [List Mode]
1
Step Instruction Device

[Timing Chart] 3
ON
X0 OFF
4
D10 of b10 0 1 0

5.3.9 Bit device output reverse (FF)

5.3 Output Instructions

5-41
 DELTA(P)

5.3.10 Pulse conversions of direct outputs (DELTA(P))

DELTA(P)

Basic High
performance Process Redundant Universal LCPU

Command
DELTA DELTA D

Command
DELTAP DELTAP D

D : Bit for which pulse conversion is to be conducted (bits)

Setting Internal Devices J \ Other

R, ZR U \G Zn Constants
Data Bit Word Bit Word DY

D ––

Function
(1) Conducts pulse output of direct access output (DY) designated by D .
If DELTA DY0 has been designated, the resulting operation will be identical to the ladder
shown below, which uses the SET/RST instructions.
[Ladder using the DELTA instruction] [Ladder using the SET/RST instructions]
X100 X100
DELTA DY0 SET DY0

RST DY0

[Operation]
END processing DELTA DY0 DELTA DY0

ON
X100 OFF
ON ON
DY0 OFF

(2) The DELTA (P) instruction is used by commands for leading edge execution for an intelligent
function module.

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• A direct access output number designated by D has exceeded the CPU module output
range. (Error code: 4101)

5-42
 DELTA(P)

Program Example
1
(1) The following program presets CH1 of the AD61 mounted at slot 0 of the main base unit,
when X20 goes ON.
[Ladder Mode] 2
Stores preset value (0) at addresses 1 and 2
of the AD61 buffer memory. 3
Outputs the preset command.

[List Mode]
5
Step Instruction Device

5.3.10 Pulse conversions of direct outputs (DELTA(P))

5.3 Output Instructions

5-43
 SFT(P)

5.4 Shift Instructions

5.4.1 Bit device shifts (SFT(P))

SFT(P)

Basic High
performance Process Redundant Universal LCPU

Command
SFT SFT D

Command
SFTP SFTP D

D : Device number to shift (bits)

Setting Internal Devices J \ Other

R, ZR U \G Zn Constants
Data Bit Word Bit Word DY

D (Other than T, C) ––

Function
(1) When bit device is used

(a) Shifts to a device designated by D the ON/OFF status of the device immediately prior
to the one designated by D , and turns the prior device OFF.
For example, if M11 has been designated by the SFT instruction, when the SFT
instruction is executed, it will shift the ON/OFF status of M10 to M11, and turn M10 OFF.

(b) Turn the first device to be shifted ON with the SET instruction.

(c) When the SFT and SFTP are to be used consecutively, the program starts from the
device with the larger number.
Shift range
Shift input
M0 M15 M14 M13 M12 M11 M10 M9 M8
SFTP M14 (1) 0 0 0 0 0 1 1 0 X02 ON
0
(2) 0 0 0 0 1 0 1 0 After the 1st shift input
SFTP M13 0
(3) 0 0 0 1 0 0 1 0 After the 2nd shift input

SFTP M12 (4) 0 0 0 1 0 1 1 0 X02 ON

0
(5) 0 0 1 0 1 0 1 0 After the 3rd shift input
SFTP M11 0
(6) 0 1 0 1 0 0 1 0 After the 4th shift input
X2 0
SET M10 (7) 0 0 1 0 0 0 1 0 After the 5th shift input

Head device to shift * At M8 to M15, "1" indicates ON and "0" indicates OFF.

5-44
 SFT(P)

(2) When word device bit designation is used

(a) Shifts to a bit in the device designated by D the 1/0 status of the bit immediately prior to 1
the one designated by D , and turns the prior bit to 0.
For example, if D0.5 (bit 5 [b5] of D0) has been designated by the SFT instruction, when
the SFT instruction is executed, it will shift the 1/0 status of b4 of D0 to b5, and turn b4 2
to 0.
b15 to b5 b4 to b0
Before the
execution of shift
0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 3
D0 0
After the
0 1 0 0 1 0 0 0 1 1 1 0 0 0 0 1
execution of shift
4

Operation Error 5
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0. 6
• The device specified by D exceeds the range of the corresponding device.
(For the Universal model QCPU and LCPU only.) (Error code: 4101)
7

5.4.1 Bit device shifts (SFT(P))

5.4 Shift Instructions

5-45
 SFT(P)

Program Example
(1) The following program shifts Y57 to Y5B when X8 goes ON.
[Ladder Mode]

Executes shift for Y57 to Y5B when X8 goes

ON.
Start programming from the device having
a large number.

Turns Y57 ON when X7 goes ON.

[Timing Chart] [List Mode]

ON
Step Instruction Device
OFF
X8
ON
OFF
X7
ON
OFF
Y57
ON
OFF
Y58
ON
OFF
Y59
ON
OFF
Y5A
ON
OFF
Y5B

5-46
 MC,MCR

5.5 Master Control Instructions

1
5.5.1 Setting and resetting the master control (MC,MCR)
MC,MCR
2
Basic High
Process Redundant Universal LCPU
3
performance

Command
4
MC n MC n D
D

Master control ladder 5

MCR MCR n
6
n : Nesting (N0 to N14) (Nesting)

: Device number to be turned ON (bits)

7
D

Setting Internal Devices J \ Other

R, ZR U \G Zn Constants
Data Bit Word Bit Word N DY
n –– –– ––

D –– ––
8

Function

5.5.1 Setting and resetting the master control (MC,MCR)

5.5 Master Control Instructions
The master control instruction is used to enable the creation of highly efficient ladder switching
sequence programs, through the opening and closing of a common bus for ladders.
A ladder using the master control is as follows:
Ladder as displayed in GPP ladder mode Ladder as it actually operates
X0 X0
MC n1 M0 MC n1 M0
n1 M0 n1 M0
X1 X3 M7 X1 X3 M7
Y47 Y47
Executed
M5 M5 only when
X0 is ON.
Y4F Y4F

X6 X4 X6 X4

MCR n1 MCR n1

XF XF
Y40 Y40

Remark
Inputting of contacts on the vertical bus is not necessary when programming in the
write mode of a peripheral device.
These will be automatically displayed when the "conversion" operation is
conducted after the creation of the ladder and then "read" mode is set.

5-47
 MC,MCR

MC
(1) If the execution command of the MC instruction is ON when master control is started, the
result of the operation from the MC instruction to the MCR instruction will be exactly as the
instruction (ladder) shows.
If the execution command of the MC instruction is OFF, the result of the operation from the
MC instruction to the MCR instruction will be as shown below:
Device Device Status
High speed timer
Count value goes to 0, coils and contacts all go OFF.
Low speed timer
High speed retentive timer
Coils go OFF, but counter values and contacts all maintain
Low speed retentive timer
current status.
Counter
Devices in OUT instruction All turned OFF
SET, RST
SFT
Devices in the following instructions: Maintain current status
Basic,
Application

(2) Even when the MC instruction is OFF, instructions from the MC instruction to the MCR
instruction will be executed, so scan time will not be shortened.

When a ladder with master control contains instructions that do not require any
contact instruction (such as FOR to NEXT, EI, DI instructions), the CPU module
executes these instructions regardless of the ON/OFF status of the MC instruction
execution command.

(3) By changing the device designated by D , the MC instruction can use the same nesting (N)
number as often as desired.

(4) Coils from devices designated by D are turned ON when the MC instruction is ON.
Further, using these same devices with the OUT instruction or other instructions will cause
them to become double coils, so devices designated by D should not be used within other
instructions.

MCR
(1) This is the instruction for recovery from the master control, and indicates the end of the
master control range of operation.
(2) Do not place contact instructions before the MCR instruction.
(3) Use the MC instruction and MCR instruction of the same nesting number as a set.
However, when the MCR instructions are nested in one place, all master controls can be
terminated with the lowest nesting (N) number.
(Refer to the "Precautions for nesting" in the program example.)

Operation Error
(1) There are no operation errors associated with the MC or MCR instruction.

5-48
 MC,MCR

Program Example
1
The master control instruction can be used in nesting. The different master control regions are
distinguished by nesting (N). Nesting can be performed from N0 to N14.
2
The use of nesting enables the creation of ladders which successively limit the execution
condition of the program.
A ladder using nesting would appear as shown below: 3

[Ladder as displayed in the GPP ladder mode] [Ladder as it actually operates]

A A
4
MC N0 M15 MC N0 M15
NO M15 NO M15
Executed
when A is ON. 5
B B
MC N1 M16 MC N1 M16

6
N1 M16 N1 M16 Executed
when A and
B are ON.
C C
MC N2 M17 MC N2 M17
N2 M17 N2 M17 Executed 7
when A, B
and C are ON.
MCR N2 MCR N2
8
Executed
when A and
B are ON.
MCR N1 MCR N1

5.5.1 Setting and resetting the master control (MC,MCR)

5.5 Master Control Instructions
Executed
when A is ON.

MCR N0 MCR N0

Not related
to the status
of A, B or C.

5-49
 MC,MCR

Cautions when Using Nesting Architecture

(1) Nesting can be used up to 15 times (N0 to N14)
When using nesting, nests should be inserted from the lower to higher nesting number (N)
with the MC instruction, and from the higher to the lower order with the MCR instruction.
If this order is reversed, there will be no nesting architecture, and the CPU module will not be
capable of performing correct operations. For example, if nesting is designated in the order
N1 to N0 by the MC instruction, and also designated in the N1 to N0 order by the MCR
instruction, the vertical bus will intersect and a correct master control ladder will not be
produced.

[Ladder as displayed in the GPP ladder mode] [Ladder as it actually operates]

A A
MC N1 M15 MC N1 M15
N1 M15 N1 M15

B
MC N0 M16 MC N0 M16
N0 M16 N0 M16

MCR N1 MCR N1

MCR N0 MCR N0

(2) If the nesting architecture results in MCR instructions concentrated in one location, all
master controls can be terminated by use of just the lowest nesting number (N).
X1 X1
MC NO M15 MC NO M15
NO M15 NO M15

X2 X2
MC N1 M16 MC N1 M16
N1 M16 N1 M16

X3 X3
MC N2 M17 MC N2 M17
N2 M17 N2 M17

MCR N2 MCR N0

MCR N1

MCR N0

5-50
 FEND

5.6 Termination Instructions

1
5.6.1 End main routine program (FEND)
FEND
2
Basic High
Process Redundant Universal LCPU
3
performance

4
FEND FEND

5
Setting Internal Devices J \
R, ZR U \G Zn Constants Other
Data
––
Bit Word Bit Word
––
6

7
Function
(1) The FEND instruction is used in cases where the CJ instruction or other instructions are
used to cause a branch in the sequence program operations, and in cases where the main 8
routine program is to be split from a subroutine program or an interrupt program.
(2) Execution of the FEND instruction will cause the CPU module to terminate the program it
was executing.

5.6.1 End main routine program (FEND)

5.6 Termination Instructions
(3) Even sequence programs following the FEND instruction can be displayed in ladder display
at a peripheral device.
(Peripheral devices continue to display ladders until encountering the END instruction.)

Operation 0 CALL P
Main routine
performed program Jump caused Main routine
when the CJ by the CJ instruction program
instruction is CJ P
not executed Operation FEND
Main routine
program performed P Subroutine
when the CJ program
FEND instruction is
executed I
P Main routine Interrupt program
program
END
FEND
END

(a) When the CJ instruction is used (b) When there are subroutine and
interrupt programs

5-51
 FEND

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The FEND instruction is executed after the execution of the CALL, FCALL, ECALL, or
EFCALL instruction, and before the execution of the RET instruction.
(Error code: 4211)
• The FEND instruction is executed after the execution of the FOR instruction, and before
the execution of the NEXT instruction. (Error code: 4200)
• The FEND instruction is executed during an interrupt program, and before the execution
of the IRET instruction. (Error code: 4221)
• The FEND instruction is executed between the CHKCIR and CHKEND instructions.
(Error code: 4230)
• The FEND instruction is executed between the IX and IXEND instructions.
(Error code: 4231)

Program Example
(1) The following program uses the CJ instruction.
[Ladder Mode]

When XB is ON, the program jumps to

label P23 and the steps that follow P23
are executed.

Executed when XB is OFF.

Indicates the termination of the sequence

program to be executed when XB is OFF.

[List Mode]

Step Instruction Device

5-52
 END

5.6.2 End sequence program (END)

END
1
Basic High
performance Process Redundant Universal LCPU
2

END
5
END

6
Setting Internal Devices J \
R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
–– ––
7

Function 8
(1) Indicates termination of programs, including main routine program, subroutine program, and
interrupt programs.
Execution of the END instruction will cause the CPU module to terminate the program that
was being executed.

5.6.2 End sequence program (END)

5.6 Termination Instructions
0

Sequence program

END

(2) The END instruction cannot be used during the execution of the main sequence program.
If it is necessary to perform END processing during the execution of a program, use the
FEND instruction.
(3) When programming in the ladder mode of a peripheral device, it is not necessary to input the
END instruction.

5-53
 END

(4) The use of the END and FEND instructions is broken down as follows for main routine
programs, subroutine programs, and interrupt programs:

Main routine program

FEND (FEND instruction is necessary.)

Subroutine program Main sequence

program area

Interrupt program

END (END instruction is necessary.)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The END instruction was executed before the execution of the RET instruction and after
the execution of the CALL, FCALL, ECALL, or EFCALL instruction.
(Error code: 4211)
• The END instruction was executed before the execution of the NEXT instruction and after
the execution of the FOR instruction.
(Error code: 4200)
• The END instruction was executed during an interrupt program prior to the execution of
the IRET instruction.
(Error code: 4221)
• The END instruction was executed within the CHKCIR to CHKEND instruction loop.
(Error code: 4230)
• The END instruction was executed within the IX to IXEND instruction loop.
(Error code: 4231)

5-54
 STOP

5.7 Other instructions

1
5.7.1 Sequence program stop (STOP)
STOP
2
Basic High
performance Process Redundant Universal LCPU

4
Command
STOP STOP

5
Setting Internal Devices J \
R, ZR U \G Zn Constants Other
Data
––
Bit Word Bit Word
––
6

7
Function
(1) Resets the output (Y) and stops the CPU module operation when the execution command is
turned ON.
8
(The same result will take place if switch is turned to the STOP setting.)
(2) Execution of the STOP instruction will cause the value of b4 to b7 of the special register
SD203 to become "3".

5.7.1 Sequence program stop (STOP)

5.7 Other instructions
b15 to b12 b11 to b8 b7 to b4 b3 to b0
SD203 0 0 1 1

Sets value "3".

(3) In order to restart CPU module operations after the execution of the STOP instruction, return
switch, which has been changed from RUN to STOP, back to the RUN position.

5-55
 STOP

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The STOP instruction was executed before the execution of the RET instruction and after
the execution of the CALL/FCALL/ECALL/EFCALL/XCALL instruction.
(Error code: 4211)
• The STOP instruction was executed before the execution of the NEXT instruction and
after the execution of the FOR instruction. (Error code: 4200)
• The STOP instruction was executed during an interrupt program prior to the execution of
the IRET instruction. (Error code: 4221)
• The STOP instruction was executed within the CHKCIR to CHKEND instruction loop.
(Error code: 4230)
• The STOP instruction was executed within the IX to IXEND instruction loop.
(Error code: 4231)
• The STOP instruction was executed during the fixed scan execution type program.
(For the Universal model QCPU and LCPU only) (Error code: 4223)

Program Example
(1) The following program stops the CPU module when X8 goes ON.
[Ladder Mode]

Stops the programmable controller when X8 goes ON.

Sequence program

[List Mode]

Step Instruction Device

5-56
 NOP,NOPLF,PAGE n

5.7.2 No operations (NOP,NOPLF,PAGE n)

NOP,NOPLF,PAGE n 1
Basic High
performance Process Redundant Universal LCPU

In the ladder display, NOP is not displayed.

3
Command
NOP NOP
4
NOPLF NOPLF

PAGE n PAGE n
5

Setting Internal Devices J \

6
R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
–– ––

7
Function
8
NOP
(1) This is a no operation instruction that has no impact on any operations up to that point.
(2) The NOP instruction is used in the following cases:

5.7.2 No operations (NOP,NOPLF,PAGE n)

5.7 Other instructions
(a) To insert space for sequence program debugging.

(b) To delete an instruction without having to change the number of steps. (Replace the
instruction with NOP.)

(c) To temporarily delete an instruction.

NOPLF
(1) This is a no operation instruction that has no impact on any operations up to that point.
(2) The NOPLF instruction is used when printing from a peripheral device to force a page
change at any desired location.
(a) When printing ladders
• A page break will be inserted between ladder blocks with the presence of the NOPLF
instruction.
• The ladder cannot be displayed correctly if an NOPLF instruction is inserted in the
midst of a ladder block.
Do not insert an NOPLF instruction in the midst of a ladder block.

(b) When printing instruction lists

• The page will be changed after the printing of the NOPLF instruction.

(3) Refer to the Operating Manual for the peripheral device in use for details of printouts from
peripheral devices.

5-57
 NOP,NOPLF,PAGE n

PAGE n
(1) This is a no operation instruction that has no impact on any operations up to that point.
(2) No processing is performed at peripheral devices with this instruction.

Operation Error
(1) There are no errors associated with the NOP, NOPLF, or PAGE instruction.

Program Example
NOP
(1) Contact closed.... Deletes the AND or ANI instruction.
[Ladder Mode] [List Mode]

Before change

Step Instruction Device

Changing to NOP

After change

Step Instruction Device

(2) Contact closed.... LD, LDI changed to NOP. (Note carefully that changing the LD and LDI
instructions to NOP completely changes the nature of the ladder.)
[Ladder Mode] [List Mode]
Before change

Step
Step Instruction
Instruction Device
Device

Changing to NOP

After change

Step Instruction Device

5-58
 NOP,NOPLF,PAGE n

[Ladder Mode] [List Mode]

Before change 1
Step Instruction Device

2
Changing to LD T3
Changing to NOP

After change 4
Step Instruction Device
5

NOPLF 7
[Ladder Mode] [List Mode]

Step Instruction Device 8

5.7.2 No operations (NOP,NOPLF,PAGE n)

5.7 Other instructions

5-59
 NOP,NOPLF,PAGE n

• Printing the ladder will result in the following:

X0
0 MOV K1 D30

MOV K2 D40

5 NOPLF NOPLF instruction, inserted as a delimiter

of ladder blocks, causes print out page to
be changed forcibly.

X1
6 Y40

8 END

• Printing an instruction list with the NOPLF instruction will result in the following:

0 LD X0

1 MOV K1 D30

3 MOV K2 D40

5 NOPLF Changes print output page

after printing NOPLF.

6 LD X1

7 OUT Y40

8 END

PAGE n
[Ladder Mode] [List Mode]
Step Instruction Device

NOP

5-60
6
7
BASIC
INSTRUCTIONS 7

Reference
7
Category Processing Details
Section
Comparison operation
instruction
Compares data to data. Section 6.1
7
Adds, subtracts, multiplies, divides, increments, or
Arithmetic operation instruction Section 6.2
decrements data with other data.
Data conversion instructions Converts data types. Section 6.3
Data transfer instruction Transmits designated data. Section 6.4
Program branch instruction Program jumps. Section 6.5
Program run control instruction Enables and disables program interrupts. Section 6.6
I/O refresh instruction Refreshes bit devices. Section 6.7
Up/down counters, teaching timers, special function timers,
Other convenient instructions Section 6.8
rotary table shortest direction controls, etc.

6-1
 =,<>,>,<=,<,>=

6.1 Comparison Operation Instructions

6.1.1 BIN 16-bit data comparisons (=,<>,>,<=,<,>=)

=,<>,>,<=,<,>=

Basic High
performance Process Redundant Universal LCPU

indicates an instruction symbol of / / / / / .

LD S1 S2

Command
AND S1 S2

Command Command

OR
S1 S2

S1 , S2 : Data for comparison or head number of the devices where the data for comparison is stored (BIN 16 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S1 ––

S2 ––

Function
(1) Treats BIN 16-bit data from device designated by S1 and BIN 16-bit data from device
designated by S2 as an a normally-open contact, and performs comparison operation.
(2) The results of the comparison operations for the individual instructions are as follows:
Instruction Comparison Instruction Comparison
Condition Condition
Symbol in Operation Result Symbol in Operation Result

= S2 = S1 = S1 S2

<> S1 S2 <> S2 = S1

> S1 > S2 > S1 S2

Continuity Non-continuity
<= S1 S2 <= S1 > S2

< S1 < S2 < S1 S2

>= S1 S2 >= S1 < S2

(3) When S1 and S2 are assigned by a hexadecimal constant and the numerical value (8 to F)
whose most significant bit (b15) is "1" is designated as a constant, the value is considered
as a negative BIN value in comparison operation.

6-2
 =,<>,>,<=,<,>=

Operation Error
1
(1) There are no operation errors associated with the , , , , , or instruction.

2
Program Example
(1) The following program compares the data at X0 to XF with the data at D3, and turns Y33 ON 3
if the data is identical.
[Ladder Mode] [List Mode]
Step Instruction Device 4

4
(2) The following program compares BIN value K100 to the data at D3, and establishes
continuity if the data in D3 is something other than 100. 6
[Ladder Mode] [List Mode]
Step Instruction Device
7

8
(3) The following program compares the BIN value 100 with the data at D3, and establishes
continuity if the D3 data is less than 100.
[Ladder Mode] [List Mode]

6.1.1 BIN 16-bit data comparisons (=,<>,>,<=,<,>=)

6.1 Comparison Operation Instructions
Step Instruction Device

(4) The following program compares the data in D0 and D3, and if the data in D0 is equal to or
less than the data in D3, establishes continuity.
[Ladder Mode] [List Mode]
Step Instruction Device

6-3
 D=,D<>,D>,D<=,D<,D>=

6.1.2 BIN 32-bit data comparisons (D=,D<>,D>,D<=,D<,D>=)

D=,D<>,D>,D<=,D<,D>=

Basic High
performance Process Redundant Universal LCPU

indicates an instruction symbol of D / D /D /D /D / D .

LD S1 S2

Command
AND S1 S2

Command Command

OR
S1 S2

S1 , S2 : Data for comparison or head number of the devices where the data for comparison is stored (BIN 32 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S1 ––

S2 ––

Function
(1) Treats BIN 32-bit data from device designated by S1 and BIN 32-bit data from device
designated by S2 as an a normally-open contact, and performs comparison operation.
(2) The results of the comparison operations for the individual instructions are as follows:
Instruction Comparison Instruction Comparison
Condition Condition
Symbol in Operation Result Symbol in Operation Result

D= S2 = S1 D= S1 S2

D<> S1 S2 D<> S2 = S1

D> S1 > S2 D> S1 S2

Continuity Non-continuity
D<= S1 S2 D<= S1 > S2

D< S1 < S2 D< S1 S2

D>= S1 S2 D>= S1 < S2

(3) When S1 and S2 are assigned by a hexadecimal constant and the numerical value (8 to F)
whose most significant bit (b31) is "1" is designated as a constant, the value is considered
as a negative BIN value in comparison operation.
(4) Data used for comparison should be designated by a 32-bit instruction (DMOV instruction,
etc.).
If designation is made with a 16-bit instruction (MOV instruction, etc.), comparisons of large
and small values cannot be performed correctly.

6-4
 D=,D<>,D>,D<=,D<,D>=

Operation Error
1
(1) There are no operation errors associated with the D , D ,D ,D ,D or D
instruction.
2
Program Example
3
(1) The following program compares the data at X0 to X1F with the data at D3 and D4, and
turns Y33 ON, if the data at X0 to X1F and the data at D3 and D4 match.
[Ladder Mode] [List Mode] 4
Step Instruction Device

(2) The following program compares BIN value K38000 to the data at D3, and D4, and
6
establishes continuity if the data in D3 and D4 is something other than 38000.
[Ladder Mode] [List Mode]
7
Step Instruction Device

(3) The following program compares BIN value K 80000 to the data at D3 and D4, and
establishes continuity if the data in D3 and D4 is less than 80000.

6.1.2 BIN 32-bit data comparisons (D=,D<>,D>,D<=,D<,D>=)

6.1 Comparison Operation Instructions
[Ladder Mode] [List Mode]
Step Instruction Device

(4) The following program compares the data in D0 and D1 with the data in D3 and D4, and
establishes continuity if the data in D0 and D1 is equal to or less than the data in D3 and D4.
[Ladder Mode] [List Mode]
Step Instruction Device

6-5
 E=,E<>,E>,E<=,E<,E>=

6.1.3 Floating decimal point data comparisons (Single precision)

(E=,E<>,E>,E<=,E<,E>=)
E=,E<>,E>,E<=,E<,E>=

Ver.
High
Basic performance Process Redundant Universal LCPU

Basic model QCPU: The upper five digits of the serial No. are "04122" or larger.

indicates an instruction symbol of E / E /E /E /E / E .

LD S1 S2

Command
AND S1 S2

Command Command

OR
S1 S2

S1 , S2 : Data for comparison or head number of the devices where the data for comparison is stored
(real number)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word E

S1 –– –– *1 ––

S2 –– –– *1 ––

*1:Available only in multiple Universal model QCPU and LCPU

(1) The 32-bit floating decimal point data from device designated by S1 and 32-bit floating decimal
point data from device designated by S2 as A normally-open contact, and performs comparison
operation.
(2) The results of the comparison operations for the individual instructions are as follows:
Instruction Comparison Instruction Comparison
Condition Condition
Symbol in Operation Result Symbol in Operation Result

E= S2 = S1 E= S1 S2

E<> S1 S2 E<> S2 = S1

E> S1 > S2 E> S1 S2

Continuity Non-continuity
E<= S1 S2 E<= S1 > S2

E< S1 < S2 E< S1 S2

E>= S1 S2 E>= S1 < S2

Note that use of the E= instruction can on occasion result in situations where
errors cause the two values to not be equal.
Example X0
EMOV E1.23 D0

E* D0 E4.56 D2

E/ D2 E4.56 D2

E D0 D2 M0

Two values may not be equal.

6-6
 E=,E<>,E>,E<=,E<,E>=

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The value of the specified device is 0. *1 2
(For the Basic model QCPU, High Performance model QCPU, Process CPU, Redundant
CPU) (Error code: 4100)
*1: There are CPU modules that will not result in an operation error if 0 is specified. For details, refer to 3
Section 3.2.4.

• The value of the specified device is outside the following range. (For the Universal model
QCPU, LCPU) 4
0, 2 -126 | value of specified device | < 2128 (Error code: 4140)
• The value of the specified device is 0, unnormalized number, nonnumeric, and ± .
(For the Universal model QCPU, LCPU) (Error code: 4140) 4

Program Example 6
(1) The following program compares 32-bit floating decimal point real number data at D0 and
D1 to 32-bit floating decimal point real number data at D3 and D4.
[Ladder Mode] [List Mode] 7
Step Instruction Device

(2) The following program compares the floating decimal point real number 1.23 to the 32-bit
floating decimal point real number data at D3 and D4.

6.1.3 Floating decimal point data comparisons (Single precision) (E=,E<>,E>,E<=,E<,E>=)

6.1 Comparison Operation Instructions
[Ladder Mode] [List Mode]
Step Instruction Device

(3) The following program compares 32-bit floating decimal point real number data at D0 and
D1 to 32-bit floating decimal point real number data at D3 and D4.
[Ladder Mode] [List Mode]
Step Instruction Device

(4) The following program compares the 32-bit floating decimal point data at D0 and D1 to the
floating decimal point real number 1.23.
[Ladder Mode] [List Mode]
Step Instruction Device

6-7
 ED=,ED<>,ED>,ED<=,ED<,ED>=

6.1.4 Floating decimal point data comparisons (Double precision)

(ED=,ED<>,ED>,ED<=,ED<,ED>=)
ED=,ED<>,ED>,ED<=,ED<,ED>=

High
Basic performance Process Redundant Universal LCPU

indicates an instruction symbol of ED /ED /ED /E /E /E

LD S1 S2

Command
AND S1 S2

Command Command

OR
S1 S2

S1 , S2 : Data for comparison or head number of the devices where the data for comparison is stored
(real number)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word E

S1 –– –– –– ––

S2 –– –– –– ––

Function
(1) The 64-bit floating decimal point real number from device designated by S1 and 64-bit floating
decimal point real number from device designated by S2 as A normally-open contact, and
performs comparison operation.
(2) The results of the comparison operations for the individual instructions are as follows:
Instruction Comparison Instruction Comparison
Condition Condition
Symbol in Operation Result Symbol in Operation Result

ED= S2 = S1 ED= S1 S2

ED<> S1 S2 ED<> S2 = S1

ED> S1 > S2 ED> S1 S2

Continuity Non-continuity
ED<= S1 S2 ED<= S1 > S2

ED< S1 < S2 ED< S1 S2

ED>= S1 S2 ED>= S1 < S2

6-8
 ED=,ED<>,ED>,ED<=,ED<,ED>=

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The value of the specified device is not in the following range: (Error code: 4140) 2
0,2 -1022 | value of specified device | < 21024
• The value of the designated device is 0. (Error code: 4140)
3

Program Example 4
(1) The following program compares 64-bit floating decimal point real number data at D0 to D3
with 64-bit floating decimal point real number data at D4 to D7.
4
[Ladder Mode] [List Mode]

Step Instruction Device

6

7
(2) The following program compares the floating decimal point real number 1.23 with the 64-bit
floating decimal point real number data at D4 to D7.
[Ladder Mode] [List Mode] 8
Step Instruction Device

6.1.4 Floating decimal point data comparisons (Double precision) (ED=,ED<>,ED>,ED<=,ED<,ED>=)

6.1 Comparison Operation Instructions
(3) The following program compares 64-bit floating decimal point real number data at D0 to D3
with 64-bit floating decimal point real number data at D4 to D7.
[Ladder Mode] [List Mode]

Step Instruction Device

(4) The following program compares the 64-bit floating decimal point data at D0 to D3 with the
floating decimal point real number 1.23.
[Ladder Mode] [List Mode]

Step Instruction Device

6-9
 ED=,ED<>,ED>,ED<=,ED<,ED>=

Caution
(1) Since the number of digits of the real number that can be input by Programing Tool is up to
15 digits, the comparison with the real number whose number of significant digits is 16 or
more cannot be made by the instruction shown in this section.
When judging match/mismatch with the real number whose significant digits is 16 or more by
the instruction in this section, compare it with the approximate values of the real number to
be compared and judge by the sizes.
Example When judging the match of E1.234567890123456+10 (Number of significant
digits is 16) and the double-precision floating-point data.

E1.23456789012345+10 E1.234567890123456+10 E1.23456789012346+10

Whether D0 to D3 is within this range is checked.(Values on boundaries are excluded.)

Example When judging the mismatch of E1.234567890123456+10 (Number of significant

digits is 16) and the double-precision floating-point data.

E1.23456789012345+10 E1.234567890123456+10 E1.23456789012346+10

Whether D0 to D3 is within this range is checked.(Values on boundaries are included.)

6-10
 $=,$<>,$>,$<=,$<,$>=

6.1.5 Character string data comparisons ($=,$<>,$>,$<=,$<,$>=)

$=,$<>,$>,$<=,$<,$>=
1
High
2
Basic performance Process Redundant Universal LCPU

indicates an instruction symbol of $ /$ /$ / $ /$ / $ .

3
LD S1 S2

Command
4
AND S1 S2

Command Command
4
OR
S1 S2

6
S1 , S2 : Data for comparison or head number of the devices where the data for comparison is stored
(character string)
7
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word $

S1 –– –– ––
8
S2 –– –– ––

Function

6.1.5 Character string data comparisons ($=,$<>,$>,$<=,$<,$>=)

6.1 Comparison Operation Instructions
(1) Compares the character string data designated by S1 with the character string data
designated by S2 as a normally-open contact.
(2) A comparison operation involves the character-by-character comparison of the ASCII code
of the first character in the character string.

(3) The character string data of S1 and S2 for comparison refers to the data stored at the range
from the designated device number to the device number where "00H" code is stored.
(a) If all character strings match, the comparison result will be matched.
b15 b8 b7 b0 b15 b8 b7 b0
S1 42H (B) 41H (A) S2 42H (B) 41H (A)
S1 +1 44H (D) 43H (C) S2 +1 44H (D) 43H (C)
S1 +2 00H 45H (E) S2 +2 00H 45H (E)
"ABCDE" "ABCDE"

Comparison Operation Comparison Operation

Instruction Symbol in Instruction Symbol in
Result Result
$= Continuity $<= Continuity
$<> Non-continuity $< Non-continuity
$> Non-continuity $>= Continuity

6-11
 $=,$<>,$>,$<=,$<,$>=

(b) If the character strings are different, the character string with the larger character code
will be the larger.
b15 b8 b7 b0 b15 b8 b7 b0
S1 42H (B) 41H (A) S2 42H (B) 41H (A)
S1 +1 44H (D) 43H (C) S2 +1 44H (D) 43H (C)
S1 +2 00H 46H (F) S2 +2 00H 45H (E)
"ABCDF" "ABCDE"

Comparison Operation Comparison Operation

Instruction Symbol in Instruction Symbol in
Result Result
$= Non-continuity $<= Non-continuity
$<> Continuity $< Non-continuity
$> Continuity $>= Continuity

(c) If the character strings are different, the first different sized character code will
determine whether the character string is larger or smaller.
b15 b8 b7 b0 b15 b8 b7 b0
S1 32H (2) 31H (1) S2 32H (2) 31H (1)
S1 +1 34H (4) 33H (3) S2 +1 33H (3) 34H (4)
S1 +2 00H 35H (5) S2 +2 00H 35H (5)
"12345" "12435"

Comparison Operation Comparison Operation

Instruction Symbol in Instruction Symbol in
Result Result
$= Non-continuity $<= Continuity
$<> Continuity $< Continuity
$> Non-continuity $>= Non-continuity

(4) If the character strings designated by S1 and S2 are of different lengths, the data with the
longer character string will be larger.
b15 b8 b7 b0 b15 b8 b7 b0
S1 32H (2) 31H (1) S2 32H (2) 31H (1)
S1 +1 34H (4) 33H (3) S2 +1 34H (4) 33H (3)
S1 +2 36H (6) 35H (5) S2 +2 36H (6) 35H (5)
S1 +3 00H 37H (7) S2 +3 00H 00H
"1234567" "123456"

Comparison Operation Comparison Operation

Instruction Symbol in Instruction Symbol in
Result Result
$= Non-continuity $<= Non-continuity
$<> Continuity $< Non-continuity
$> Continuity $>= Continuity

6-12
 $=,$<>,$>,$<=,$<,$>=

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The code "00H" does not exist within the range of the relevant device, starting from the 2
device number designated by S1 and S2 . (Error code: 4101)

• The character string of S1 and S2 exceeds 16383 characters. (Error code: 4101) 3

The character string data comparison instruction checks the device range while 4
comparing the designated character string data. For this reason, if the "00H" code
does not exist in the relevant device range, the instruction outputs the comparison
result instead of returning an operation error when no match of characters is 4
detected.
Example $ D12287 D10 M0
S1 S2 6
Data of S1 Data of S2

D12287
W0
B
00 H
A
C
D10
D11
Z
00 H
A
C
7
If S1 and S2 data are as shown above, the second character of S1 does not
match with that of S2 , and the comparison result is expressed as S1 S2 (the 8
operation result is "non-conductive"). Though the "00H" code is not included
within the S1 device range, no operation error is returned, because the
no-match is detected at D12287, which is within the device range.

6.1.5 Character string data comparisons ($=,$<>,$>,$<=,$<,$>=)

6.1 Comparison Operation Instructions
Program Example
(1) The following program compares character strings stored following D0 and characters
following D10.
[Ladder Mode] [List Mode]
Step Instruction Device

(2) The following program compares the character string "ABCDEF" with the character string
stored following D10.
[Ladder Mode] [List Mode]
Step Instruction Device

6-13
 $=,$<>,$>,$<=,$<,$>=

(3) The following program compares the character string stored following D10 with the character
string stored following D100.
[Ladder Mode] [List Mode]
Step Instruction Device

(4) The following program compares the character string stored following D200 with the
character string "12345".
[Ladder Mode] [List Mode]
Step Instruction Device

6-14
 BKCMP …,BKCMP … P

6.1.6 BIN block data comparisons (BKCMP … ,BKCMP … P)

BKCMP …,BKCMP … P
1
Basic High
performance Process Redundant Universal LCPU

3
indicates an instruction symbol of / / / / / .
Command
BKCMP BKCMP S1 S2 D n
4
Command
BKCMP P BKCMP P S1 S2 D n

4
S1 : Data to be compared or head number of the devices where the data to be compared is stored (BIN 16 bits)

S2 : Head number of the devices where the comparison data is stored (BIN 16 bits)
6
D : Head number of the devices where the comparison operation result will be stored (bits)
n : Number of comparison data blocks (BIN 16 bits)

Setting Internal Devices

R, ZR
J \
U \G Zn
Constants
Other
7
Data Bit Word Bit Word K, H

S1 –– –– ––

S2 –– –– –– –– 8
D –– –– ––

n ––

6.1.6 BIN block data comparisons (BKCMP … ,BKCMP … P)

6.1 Comparison Operation Instructions
Function
(1) Compares BIN 16-bit data the nth point from the device number designated by S1 with BIN
16-bit data the nth point from the device number designated by S2 , and stores the result
from the device designated by D onward.

(a) If the comparison condition has been met, the device designated by D will be turned ON.

(b) If the comparison condition has not been met, the device designated by D will be
turned OFF.
Operation Results
S1 1234 (BIN) S2 5321 (BIN) D OFF (0)
S1 1 5678 (BIN) S2 1 3399 (BIN) D 1 ON (1)
S1 2 5000 (BIN) S2 2 5678 (BIN) D 2 OFF (0)
n n n

S1 (n 2) 7777 (BIN) S2 (n 2) 6543 (BIN) D (n 2) ON (1)

S1 (n 1) 4321 (BIN) S2 (n 1) 1200 (BIN) D (n 1) ON (1)

(2) The comparison operation is conducted in 16-bit units.

(3) The constant designated by S1 can be between 32768 and 32767 (BIN 16-bit data).
Operation Results
S2 32000 (BIN) D ON (1)
S2 1 4321 (BIN) D 1 OFF (0)
S2 2 32000 (BIN) D 2 ON (1)
S1 32000 (BIN) n n
S2 (n 2) 1234 (BIN) D (n 2) OFF (0)
S2 (n 1) 5678 (BIN) D (n 1) OFF (0)

6-15
 BKCMP …,BKCMP … P

(4) The results of the comparison operations for the individual instructions are as follows:
Instruction Comparison Instruction Comparison
Condition Condition
Symbols Operation Result Symbols Operation Result
BKCMP= S2 = S1 BKCMP= S1 S2

BKCMP<> S1 S2 BKCMP<> S2 = S1

BKCMP> S1 > S2 BKCMP> S1 S2

ON (1) OFF (0)
BKCMP<= S1 S2 BKCMP<= S1 > S2

BKCMP< S1 < S2 BKCMP< S1 S2

BKCMP>= S1 S2 BKCMP>= S1 < S2

(5) If all comparison results stored n points from D are ON (1), SM704 (block comparison
signal) goes ON.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The range of the device n points from a device designated by S1 , S2 or D exceeds the
relevant device. (Error code: 4101)

• The device range for n points starting from the device designated by S1 overlaps with the
device range for n points starting from the device designated by D .
(Error code: 4101)

• The device range for n points starting from the device designated by S2 overlaps with the
device range for n points starting from the device designated by D .
(Error code: 4101)

Program Example
(1) The following program compares, when X20 is turned ON, the data stored at D100 to D103
with the data stored at R0 to R3 and stores the operation result into the area starting from
M10.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
b15 b0 b15 b0
D100 1000 (BIN) R0 1000 (BIN) M10 ON
D101 2000 (BIN) R1 2000 (BIN) M11 ON
D102 3000 (BIN) R2 5000 (BIN) M12 OFF
D103 4000 (BIN) R3 4000 (BIN) M13 ON

D0 4

6-16
 BKCMP …,BKCMP … P

(2) The following program compares, when X1C is turned ON, the constant K1000 with the data
stored at D10 to D13, and stores the operation result at b4 to b7 in D0.
[Ladder Mode] [List Mode]
1
Step Instruction Device

[Operation] 3
b15 b0
D10 2000 (BIN)

4
b15 b0 D11 1000 (BIN)
1000 (BIN)
D12 1000 (BIN)
D13 2222 (BIN)

4
b15 b7 b4 b0
D0 before 0 10000 1000 100000
operation
6
b15 b7 b4 b0
D0 after 0 10000 10100 10000
operation
7
(3) The following program compares, when X20 is turned ON, the data at D10 to D12 with the
data at D30 to D32, and stores the operation result into the area starting from M100.
The following program transfers the character string "ALL ON" to D100 onward when all
8
devices from M100 onward have reached the 1 "ON" state.
[Ladder Mode] [List Mode]

Step Instruction Device

6.1.6 BIN block data comparisons (BKCMP … ,BKCMP … P)

6.1 Comparison Operation Instructions
[Operation]
b15 b0 b15 b0
D10 1234 (BIN) D30 4321 (BIN) M100 ON SM704
D11 5678 (BIN) D31 5678 (BIN) M101 ON ON
D12 9876 (BIN) D32 9999 (BIN) M102 ON

b15 b8 b7 b0
D100 4CH (L) 41H (A) $MOV
D101 20H ( ) 4CH (L)
D102 4EH (N) 4FH (O)

6-17
 DBKCMP …,DBKCMP … P

6.1.7 BIN 32-bit block data comparisons

(DBKCMP … ,DBKCMP … P)
DBKCMP …,DBKCMP … P

Ver.
High
Basic performance Process Redundant Universal LCPU

QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later.

QnUDE(H)CPU: The serial number (first five digits) is "10102" or later.

indicates an instruction symbol of / / / / / .

Command
DBKCMP DBKCMP S1 S2 D n

Command
DBKCMP P DBKCMP P S1 S2 D n

S1 : Data to be compared or head number of the devices where the data to be compared are stored (BIN 32 bits)
S2 : Head number of the devices where the comparison data are stored (BIN 32 bits)
D : Head number of the devices where the comparison operation result will be stored (bits)
n : Number of comparison data blocks (BIN 16 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S1 –– –– ––

S2 –– –– –– ––

D –– –– –– ––

n –– ––

Function
(1) This instruction compares BIN 32-bit data stored in n-point devices starting from the device
specified by S1 with BIN 32-bit data stored in n-point devices starting from the device
specified by a constant and S2 and then stores the result into the nth device specified by D
and up.

(a) If the comparison condition has been met, the corresponding devices specified by D will
be turned on.

(b) If the comparison condition has not been met, the corresponding devices specified by D
will be turned off.
b31 b0 b31 b0 Operation result
S1 ＋1, S1 1090 (BIN) S2 ＋1, S2 1000 (BIN) D OFF (0)
S1 ＋3, S1 ＋2 2080 (BIN) S2 ＋3, S2 ＋2 2000 (BIN) D ＋1 OFF (0)
S1 ＋5, S1 ＋4 5060 (BIN) n S2 ＋5, S2 ＋4 5060 (BIN) n D ＋2 ON (1) n

S1 ＋n 1, S1 ＋n 2 1106 (BIN) S2 ＋n 1, S2 ＋n 2 1106 (BIN) D ＋n 1 ON (1)

6-18
 DBKCMP …,DBKCMP … P

(2) The comparison operation is executed in 32-bit units.

(3) The constant in the device specified by S1 can be between 2147483648 and 2147483647 1
(BIN 32-bit data).
b31 b0 Operation result
S2 ＋1, S2 32700 (BIN) D ON (1) 2
b31 b0 S2 ＋3, S2 ＋2 40000 (BIN) D ＋1 OFF (0)
S1 ＋1, S1 32800 (BIN) S2 ＋5, S2 ＋4 32800 (BIN) n D ＋2 ON (1) n

S2 ＋n 1, S2 ＋n 2 2147400 (BIN) D ＋n 1 OFF (0) 3

(4) specifies out of the device range of n-point devices starting from the device specified by
4
D

S1 and S2 .
(5) The following table shows the results of the comparison operations for each individual
instruction.
4
Instruction Comparison Instruction Comparison
Condition Condition
Symbols Operation Result Symbols Operation Result
DBKCMP= S2 = S1 DBKCMP= S1 S2
6
DBKCMP<> S1 S2 DBKCMP<> S2 = S1

DBKCMP> S1 > S2 DBKCMP> S1 S2

DBKCMP<= S1 S2
ON (1)
DBKCMP<= S1 > S2
OFF (0) 7
DBKCMP< S1 < S2 DBKCMP< S1 S2

DBKCMP>= S1 S2 DBKCMP>= S1 < S2

8
(6) If all comparison results stored into the devices starting from the device specified by D to
nth device are on(1), or one of the results is off(2), the special relays will be on or off in
accordance with the conditions as follows.

6.1.7 BIN 32-bit block data comparisons (DBKCMP … ,DBKCMP … P)

6.1 Comparison Operation Instructions
When results of comparison operations have a result of
When all results of comparison operations are on(1)
off(0)
No. Number Interrupt (other Interrupt (other
Initial execu- Initial execution/
than l45)/Fixed Interrupt(l45) than l45)/Fixed Interrupt(l45)
tion/Scan Scan
scan execution scan execution
1 SM704 ON ON ON OFF OFF OFF
2 SM716 ON –– –– OFF –– ––
3 SM717 –– ON –– –– OFF ––
4 SM718 –– –– ON –– –– OFF

In a standby program, a special relay depending on the caller program turns on or off.
(7) If the value specified by n is 0, the instruction will be not processed.

6-19
 DBKCMP …,DBKCMP … P

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an
error code is stored into SD0.
• A negative value is specified for n. (Error code: 4100)

• The range of the n-point devices starting from the device specified by S1 , S2 . or D
exceeds the specified device range. (Error code: 4101)

• The range of the n-point devices starting from the device specified by S1 overlaps with the
range of the n-point devices starting from the device specified by D .
(Error code: 4101)

• The range of the n-point devices starting from the device specified by S2 overlaps with the
range of the n-point devices starting from the device specified by D .
(Error code: 4101)

Program Example
(1) The following program compares the value data stored at R0 to R5 with the value data
stored at D20 to D25, and then stores the operation result into Y0 to Y2, when M0 is turned
on,
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
b31 b0 b31 b0
R1,R0 -2147483000 D21,D20 -2147483000 Y0 OFF (0)
R3,R2 0 D23,D22 1 Y1 ON (1)
R5,R4 2147483000 D25,D24 2147482999 Y2 ON (1)

(2) The following program compares the constant with the value data stored at D0 to D9, and
then stores the operation result into D10.5 to D10.9, when M0 is turned on,
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]

b31 b0
D1,D0 -70000 D10.5 ON (1)
b31 b0 D3,D2 50000 D10.6 OFF (0)
-60000 D5,D4 -32768 D10.7 OFF (0)
D7,D6 32767 D10.8 OFF (0)
D9,D8 0 D10.9 OFF (0)

6-20
 DBKCMP …,DBKCMP … P

When certain bits are specified in a word device, bits other than the certain bits 1
that store the operation result do not change.
D10.F D10.0
Before execution 0 0 1 0 1 1 1 1 1 0 0 1 1 0 0 0 2
D10.F D10.0
After execution 0 0 1 0 1 1 0 0 0 0 1 1 1 0 0 0
3
No change No change

4
(3) The following program compares the value data stored at D0 to D5 with the value data
stored at D10 to D15, and then stores the operation result into M20 to M22, when M0 is
turned on. Also, the program transfers the character string "ALL ON" to D100 and up when
all devices from M20 to M22 have reached the on status. 4
[Ladder Mode] [List Mode]

Step Instruction Device 6

[Operation]
8
b31 b0 b31 b0
D1,D0 -2147483000 D11,D10 -2147483000 M20 ON (1)
D3,D2 60000 D13,D12 60001 M21 ON (1)
D5,D4 -900000 D15,D14 -899999 M22 ON (1)

6.1.7 BIN 32-bit block data comparisons (DBKCMP … ,DBKCMP … P)

6.1 Comparison Operation Instructions
When all operation results are on(1),
the special relays corresponding to SM704 ON (1)
each program turn on(1).
(Since this program examples refer SM716 ON (1)
to scan programs, SM704 and SM716 SM717 OFF (0)
turn on(1), SM7171 and SM718 do not SM718 OFF (0)
change in the scan program)

6-21
 +(P),-(P)

6.2 Arithmetic Operation Instructions

6.2.1 BIN 16-bit addition and subtraction operations (+(P),-(P))

+(P),-(P)

Basic High
performance Process Redundant Universal LCPU

When two data are set ( D + S D , D - S D )

indicates an instruction symbol of +/ .

Command
+, S D

Command
+P, P P S D

S : Data for additing/subtracting or head number of the devices where the data for additing/subtracting is stored
(BIN 16 bits)
S1
D : Head number of the devices where the data to be added to/subtracted from is stored (BIN 16 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S ––

D –– ––

Function
+

(1) Adds 16-bit BIN data designated by D to 16-bit BIN data designated by S and stores the
result of the addition at the device designated by D .
D S D

b15 b0 b15 b0 b15 b0

5678 (BIN) 1234 (BIN) 6912 (BIN)

(2) Values for S and D can be designated between 32768 and 32767 (BIN, 16 bits).
(3) The judgment of whether data is positive or negative is made by the most significant bit
(b15).
• 0: Positive
• 1: Negative
(4) The following will happen when an underflow or overflow is generated in an operation result:
The carry flag in this case does not go ON.
K32767 +K2 K 32767 Since bit 15 value is "1",
(7FFFH) (0002H) (8001H) result of operation takes a negative value.
K 32768 +K 2 K32766 Since bit 15 value is "0",
(8000H) (FFFEH) (7FFEH) result of operation takes a positive value.

6-22
 +(P),-(P)

(1) Subtracts 16-bit BIN data designated by D from 16-bit BIN data designated by S and 1
stores the result of the subtraction at the device designated by D .
D S D
2
b15 b0 b15 b0 b15 b0
5678 (BIN) 1234 (BIN) 4444 (BIN)

(2) Values for S and D can be designated between 32768 and 32767 (BIN, 16 bits). 3
(3) The judgment of whether data is positive or negative is made by the most significant bit
(b15).
• 0: Positive
4
• 1: Negative
(4) The following will happen when an underflow or overflow is generated in an operation result: 4
The carry flag in this case does not go ON.
K 32768 K2 K32766 Since bit 15 value is "0",
(8000H) (0002H) (7FFEH) result of operation takes a positive value. 6
K32767 K 2 K 32767 Since bit 15 value is "1",
(7FFFH) (FFFEH) (8001H) result of operation takes a negative value.

7
Operation Error
8
(1) There are no operation errors associated with the +(P) or -(P) instruction.

6.2.1 BIN 16-bit addition and subtraction operations (+(P),-(P))

6.2 Arithmetic Operation Instructions

6-23
 +(P),-(P)

When three data are set ( S1 + S2 D , S1 - S2 D )

indicates an instruction symbol of +/ .

Command
+, S1 S2 D

Command
+P, P P S1 S2 D

S1 : Data to be added to/subtracted from or head number of the devices where the data to be added
to/subtracted from is stored (BIN 16 bits)
S2 : Data for additing/subtracting or head number of the devices where the data for additing/subtracting is stored
(BIN 16 bits)
D : Head number of the devices where the addition/subtraction operation result will be stored (BIN 16 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S1 ––

S2 ––

D
S –– ––

Function
+

(1) Adds 16-bit BIN data designated by S1 to 16-bit BIN data designated by S2 and stores the
result of the addition at the device designated by D .
S1 S2 D

b15 b0 b15 b0 b15 b0

5678 (BIN) 1234 (BIN) 6912 (BIN)

(2) Values for S1 , S2 D andcan be designated between D 32768 and 32767 (BIN, 16 bits).
(3) The judgment of whether data is positive or negative is made by the most significant bit
(b15).
• 0: Positive
• 1: Negative
(4) The following will happen when an underflow or overflow is generated in an operation result:
The carry flag in this case does not go ON.
K32767 +K2 K 32767 Since bit 15 value is "1",
(7FFFH) (0002H) (8001H) result of operation takes a negative value.

K 32768 +K 2 K32766 Since bit 15 value is "0",

(8000H) (FFFEH) (7FFEH) result of operation takes a positive value.

6-24
 +(P),-(P)

(1) Subtracts 16-bit BIN data designated by S1 from 16-bit BIN data designated by S2 and 1
stores the result of the subtraction at the device designated by D .

S1 S2 D 2
b15 b0 b15 b0 b15 b0
5678 (BIN) 1234 (BIN) 4444 (BIN)

3
(2) Values for S1 , S2 D and can be designated between D 32768 and 32767 (BIN, 16 bits).
(3) The judgment of whether data is positive or negative is made by the most significant bit
(b15). 4
• 0: Positive
• 1: Negative
(4) The following will happen when an underflow or overflow is generated in an operation result:
4
The carry flag in this case does not go ON.
K 32768 K2
(8000H) (0002H)
K32766
(7FFEH)
Since bit 15 value is "0",
result of operation takes a positive value. 6
K32767 K 2 K 32767 Since bit 15 value is "1",
(7FFFH) (FFFEH) (8001H) result of operation takes a negative value.
7
Operation Error
(1) There are no operation errors associated with the +(P) or -(P) instruction. 8

Program Example

6.2.1 BIN 16-bit addition and subtraction operations (+(P),-(P))

6.2 Arithmetic Operation Instructions
(1) The following program adds, when X5 is turned ON, the data at D3 and D0 and outputs the
operation result at Y38 to Y3F.
[Ladder Mode] [List Mode]
Step Instruction Device

(2) The following program outputs the difference between the set value for timer T3 and its
present value in BCD to Y40 to Y53.
[Ladder Mode] [List Mode]
Step Instruction Device

6-25
 D+(P),D-(P)

6.2.2 BIN 32-bit addition and subtraction operations (D+(P),D-(P))

D+(P),D-(P)

Basic High
performance Process Redundant Universal LCPU

When two data are set (( D +1, D )+( S +1, S ) ( D +1, D ), ( D +1, D )-( S +1, S ) ( D +1, D ))

indicates an instruction symbol of D+/D .

Command
D+, D S D

Command
D+P, D P P S D

S : Data for additing/subtracting or head number of the devices where the data for additing/subtracting is stored
(BIN 32 bits)
D : Head number of the devices where the data to be added to/subtracted from is stored (BIN 32 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S ––

D –– ––

Function
D+
(1) Adds 32-bit BIN data designated by D to 32-bit BIN data designated by S , and stores the
result of the addition at the device designated by D .

D +1 D S +1 S D +1 D

b31 b16 b15 b0 b31 b16 b15 b0 b31 b16 b15 b0

567890 (BIN) 123456 (BIN) 691346 (BIN)

(2) The values for S and D can be designated at between 2147483648 and 2147483647
(BIN 32 bits).
(3) Judgment of whether the data is positive or negative is made on the basis of the most
significant bit (b31).
• 0: Positive
• 1: Negative
(4) The following will happen when an underflow or overflow is generated in an operation result:
The carry flag in this case does not go ON.
K2147483647 +K2 K 2147483647 Since bit 31 value is "1",
(7FFFFFFFH) (00000002H) (80000001H) result of operation takes a negative value.

K 2147483648 +K 2 K2147483646 Since bit 31 value is "0",

(80000000H) (FFFFFFFEH) (7FFFFFFEH) result of operation takes a positive value.

6-26
 D+(P),D-(P)

D-

(1) Subtracts 32-bit BIN data designated by D from 32-bit BIN data designated by S and 1
stores the result of the subtraction at the device designated by D .
D +1 D S +1 S D +1 D
2
b31 b16 b15 b0 b31 b16 b15 b0 b31 b16 b15 b0
567890 (BIN) 123456 (BIN) 444434 (BIN)

(2) The values for S and D can be designated at between 2147483648 and 2147483647 3
(BIN 32 bits).
(3) Judgment of whether the data is positive or negative is made on the basis of the most
significant bit (b31). 4
• 0: Positive
• 1: Negative
4
(4) The following will happen when an underflow or overflow is generated in an operation result:
The carry flag in this case does not go ON.
K 2147483648 K2 K2147483646 Since bit 31 value is "0", 6
(80000000H) (00000002H) (7FFFFFFEH) result of operation takes a positive value.

K2147483647 K 2 K 2147483647 Since bit 31 value is "1",

(80000000H) (FFFFFFFEH) (80000001H) result of operation takes a negative value. 7
Operation Error
8
(1) There are no operation errors associated with the D+(P) or D-(P) instruction.

6.2.2 BIN 32-bit addition and subtraction operations (D+(P),D-(P))

6.2 Arithmetic Operation Instructions

6-27
 D+(P),D-(P)

When three data are set (( S1 +1, S1 )+( S2 +1, S2 ) ( D +1, D ), ( S1 +1, S1 )-( S2 +1, S2 ) ( D +1, D ))

indicates an instruction symbol of D+/ D .

Command
D+, D S1 S2 D

Command
D+P, D P P S1 S2 D

S1 : Data to be added to/subtracted from or head number of the devices where the data to be added
to/subtracted from is stored (BIN 32 bits)
S2 : Data for additing/subtracting or head number of the devices where the data for additing/subtracting is stored
(BIN 32 bits)
D : Head number of the devices where the addition/subtraction operation result will be stored (BIN 32 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S1 ––

S2
S1 ––

D –– ––

Function
D+

(1) Adds 32-bit BIN data designated by S1 to 32-bit BIN data designated by S2 , and stores the
result of the addition at the device designated by D .
S1 +1 S1 S2 +1 S2 D +1 D

b31 b16 b15 b0 b31 b16 b15 b0 b31 b16 b15 b0

567890 (BIN) 123456 (BIN) 691346 (BIN)

(2) The values for S1 , S2 and D can be designated at between 2147483648 and 2147483647
(BIN 32 bits).
(3) Judgment of whether the data is positive or negative is made on the basis of the most
significant bit (b31).
• 0: Positive
• 1: Negative
(4) The following will happen when an underflow or overflow is generated in an operation result:
The carry flag in this case does not go ON.
K2147483647 +K2 K 2147483647 Since bit 31 value is "1",
(7FFFFFFFH) (00000002H) (80000001H) result of operation takes a negative value.

K 2147483648 +K 2 K2147483646 Since bit 31 value is "0",

(80000000H) (FFFFFFFEH) (7FFFFFFEH) result of operation takes a positive value.

6-28
 D+(P),D-(P)

D-

(1) Subtracts 32-bit BIN data designated by S1 from 32-bit BIN data designated by S2 and 1
stores the result of the subtraction at the device designated by D .
S1 +1 S1 S2 +1 S2 D +1 D
2
b31 b16 b15 b0 b31 b16 b15 b0 b31 b16 b15 b0
567890 (BIN) 123456 (BIN) 444434 (BIN)

(2) The values for S1 , S2 and D can be designated at between 2147483648 and 2147483647 3
(BIN 32 bits).
(3) Judgment of whether the data is positive or negative is made on the basis of the most
significant bit (b31). 4
• 0: Positive
• 1: Negative
4
(4) The following will happen when an underflow or overflow is generated in an operation result:
The carry flag in this case does not go ON.
K 2147483648 K2 K2147483646 Since bit 31 value is "0", 6
(80000000H) (00000002H) (7FFFFFFEH) result of operation takes a positive value.

K2147483647 K 2 K 2147483647 Since bit 31 value is "1",

(7FFFFFFFH) (FFFFFFFEH) (80000001H) result of operation takes a negative value.
7

Operation Error 8
(1) There are no operation errors associated with the D+(P) or D-(P) instruction.

6.2.2 BIN 32-bit addition and subtraction operations (D+(P),D-(P))

6.2 Arithmetic Operation Instructions
Program Example
(1) The following program adds 28-bit data from X10 to X2B to the data at D9 and D10 when X0
goes ON, and outputs the result of the operation to Y30 to Y4B.
[Ladder Mode] [List Mode]
Step Instruction Device

(2) The following program subtracts the data from M0 to M23 from the data at D0 and D1 when
XB goes ON, and stores the result at D10 and D11.
[Ladder Mode] [List Mode]
Step Instruction Device

6-29
 *(P),/(P)

6.2.3 BIN 16-bit multiplication and division operations (*(P),/(P))

*(P),/(P)

Basic High
performance Process Redundant Universal LCPU

indicates an instruction symbol of * , / .

Command
*, / S1 S2 D

Command
*P, / P P S1 S2 D

S1 : Data to be multiplied/divided or head number of the devices where the data to be multiplied/divided is stored
(BIN 16 bits)
S2 : Data for multiplying/dividing or head number of the devices where the data for multiplying/dividing is stored
(BIN 16 bits)
D : Head number of the devices where the multiplication/division operation result will be stored (BIN 32 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S1 ––

S2 ––

D –– ––

Function
*

(1) Multiplies BIN 16-bit data designated by S1 and BIN 16-bit data designated by S2 , and
stores the result in the device designated by D .

S1 S2 D D

b15 b0 b15 b0 b31 b16 b15 b0

5678 (BIN) 1234 (BIN) 7006652 (BIN)

(2) If D is a bit device, designation is made from the lower bits.

Example K1.......... Lower 4 bits (b0 to b3)
K4.......... Lower 16 bits (b0 to b15)
K8.......... 32 bits (b0 to b31)

(3) Values for S1 and S2 can be designated between 32768 and 32767 (BIN, 16 bits).

(4) Judgments whether S1 , S2 , and D are positive or negative are made on the basis of the
most significant bit (b15 for S1 , and S2 , for D and b31).
• 0: Positive
• 1: Negative

6-30
 *(P),/(P)

(1) Divides BIN 16-bit data designated by S1 and BIN 16-bit data designated by S2 , and stores 1
the result in the device designated by D .

2
Quotient Remainder
S1 S2 D D 1

b15 b0 b15 b0 b15 b0 b15 b0

5678 (BIN) 1234 (BIN) 4 (BIN) 742 (BIN)
3
(2) If a word device has been used, the result of the division operation is stored as 32 bits, and
both the quotient and remainder are stored; if a bit device has been used, 16 bits are used
and only the quotient is stored.
4
Quotient: Stored at the lower 16 bits.
Remainder: Stored at the upper 16 bits (Stored only when using a word device).

(3) Values for S1 and S2 can be designated between 32768 and 32767 (BIN 16 bits). 4
(4) Judgment whether values for S1 , S2 , D and D +1 are positive or negative is made on the
basis of the most significant bit (b15). (Sign is attached to both the quotient and remainder.)
• 0: Positive
6
• 1: Negative

7
Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
8
• Attempt to divide S2 by 0. (Error code: 4100)

Program Example

6.2.3 BIN 16-bit multiplication and division operations (*(P),/(P))

6.2 Arithmetic Operation Instructions
(1) The following program multiplies "5678" by "1234" in BIN and stores the result at D3 and D4
when X5 turns ON.
[Ladder Mode] [List Mode]
Step Instruction Device

(2) The following program multiplies BIN data at X8 to XF by BIN data at X10 to X1B, and
outputs the result of the multiplication to Y30 to Y3F.
[Ladder Mode] [List Mode]
Step Instruction Device

(3) The following program divides, when X3 is turned ON, the data at X8 to XF by 3.14 and
outputs the operation result at Y30 to Y3F.
[Ladder Mode] [List Mode]
Step Instruction Device

6-31
 D*(P),D/(P)

6.2.4 BIN 32-bit multiplication and division operations (D*(P),D/(P))

D*(P),D/(P)

Basic High
performance Process Redundant Universal LCPU

indicates an instruction symbol of D * D/ .

Command
D* , D/ S1 S2 D

Command
D* P,D/P P S1 S2 D

S1 : Data to be multiplied/divided or head number of the devices where the data to be multiplied/divided is stored
(BIN 32 bits)
S2 : Data for multiplying/dividing or head number of the devices where the data for multiplying/dividing is stored
(BIN 32 bits)
D : Head number of the devices where the multiplication/division operation result will be stored (BIN 64 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S1 ––

S2 ––

D –– ––

Function
D*
(1) Multiplies BIN 32-bit data designated by S1 and BIN 32-bit data designated by S2 , and
stores the result in the device designated by D .

S1 S1 S2 S2 D D D D
b31 b16 b15 b0 b31 b16 b15 b0 b63 b48 b47 b32 b31 b16 b15 b0
567890 (BIN) 123456 (BIN) 70109427840 (BIN)

(2) If D is a bit device, only the lower 32 bits of the multiplication result will be considered, and
the upper 32 bits cannot be designated.

Example K1.......... Lower 4 bits (b0 to b3)

K4.......... Lower 16 bits (b0 to b15)
K8.......... Lower 32 bits (b0 to b31)
If the upper 32 bits of the bit device are required for the result of the multiplication operation,
first temporarily store the data in a word device, then transfer the word device data to the bit
device by designating ( D +2) and ( D +3) data.
(3) The values for S1 and S2 can be designated at between 2147483648 and 2147483647
(BIN 32 bits).
(4) Judgments whether S1 , S2 , and D are positive or negative are made on the basis of the
most significant bit (b31 for S1 and S2 , b63 for D ).
• 0: Positive
• 1: Negative

6-32
 D*(P),D/(P)

D/

(1) Divides BIN 32-bit data designated by S1 and BIN 32-bit data designated by S2 , and stores 1
the result in the device designated by D .
S1 S1 S2 S2 D D D D
2
b31 b16 b15 b0 b31 b16 b15 b0 b31 b16 b15 b0 b31 b16 b15 b0
567890 (BIN) 123456 (BIN) 4 (BIN) 74066 (BIN)

(2) With a word device, the division operation result is stored in 64 bits and both the quotient 3
and remainder are stored. With a bit device, only the quotient is stored as the operation
result in 32 bits.

Quotient : Stored at the lower 32 bits.

4
Remainder : Stored at the upper 32 bits (Stored only when using a word device).

(3) The values for S1 and S2 can be designated at between 2147483648 and 2147483647 4
(BIN 32 bits).

(4) Judgment whether values for S1 , S2 , and +2 are positive or negative is made on the
6
D D
basis of the most significant bit (b31).
(Sign is attached to both the quotient and remainder.)
• 0: Positive
7
• 1: Negative

Operation Error 8
(1) In any of the following cases, an operation error occurs, the error flag (SM0) is turned ON,
and the corresponding error code is stored into SD0.
• Attempt to divide S2 by 0. (Error code: 4100)

6.2.4 BIN 32-bit multiplication and division operations (D*(P),D/(P))

6.2 Arithmetic Operation Instructions
Program Example
(1) The following program multiplies the BIN data at D7 and D8 by the BIN data at D18 and D19
when X5 is ON, and stores the result at D1 to D4.
[Ladder Mode] [List Mode]
Step Instruction Device

(2) The following program outputs the value resulting when the data at X8 to XF is multiplied by
3.14 to Y30 to Y3F when X3 is ON.
[Ladder Mode] [List Mode]
Step Instruction Device

6-33
 B+(P),B-(P)

6.2.5 BCD 4-digit addition and subtraction operations (B+(P),B-(P))

B+(P),B-(P)
B+(P), B-(P)

Basic High
performance Process Redundant Universal LCPU

When two data are set ( D + S D , D - S D )

indicates an instruction symbol of B+/B .

Command
B+, B S D

Command
B+P, B P P S D

S : Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored
(BCD 4 digits)
D : Head number of the devices where the data to be added to/subtracted from is stored (BCD 4 digits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S ––

D –– ––

Function
B+

(1) Adds the BCD 4-digit data designated by D and the BCD 4-digit data designated by S , and
stores the result of the addition at the device designated by D .
D S D

5 6 7 8 1 2 3 4 6 9 1 2

(2) 0 to 9999 (BCD 4 digits) can be assigned to S and D .

(3) If the result of the addition operation exceeds 9999, the higher bits are ignored.
The carry flag in this case does not go ON.

6 4 3 2 3 5 8 3 0 0 1 5

B-

(1) Subtracts the BCD 4-digit data designated by S and the BCD 4-digit data designated by D ,
and stores the result of the subtraction at the device designated by D .
D S D

0 6 7 8 0 2 3 4 0 4 4 4
Digits exceeding the designated
number of digits are assumed to be 0.

(2) 0 to 9999 (BCD 4 digits) can be assigned to S and D .

6-34
 B+(P), B-(P)

(3) The following will result if an underflow is generated by the subtraction operation:
The carry flag in this case does not go ON.
1
0 0 0 1 0 0 0 3 9 9 9 8

Operation Error 2
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0. 3
• The S or D BCD data is outside the 0 to 9999 range. (Error code: 4100)

4
Program Example
(1) The following program adds BCD data 5678 and 1234, stores it at D993, and at the same 4
time outputs it to from Y30 to Y3F.
[Ladder Mode]
6
Stores 5678 in BCD to D993.

7
Adds 1234 in BCD to the value at D993,
and stores the result to D993.

Outputs the data in D993 to Y30 to Y3F.

[List Mode]
Step Instruction Device

6.2.5 BCD 4-digit addition and subtraction operations (B+(P),B-(P))

6.2 Arithmetic Operation Instructions
(2) The following program subtracts the BCD data 4321 from 7654, stores the result at D10, and
at the same time outputs it to Y30 to Y3F.
[Ladder Mode]

Stores 7654 in BCD to D10.

Subtracts the value in D10 from 4321 in BCD,

and stores the result to D10.
Outputs the data in D10 to Y30 to Y3F.

[List Mode]
Step Instruction Device

6-35
 B+(P), B-(P)

When three data are set ( S1 + S2 D , S1 - S2 D )

indicates an instruction symbol of B+/B- .

Command
B+, B- S1 S2 D

Command
B+P,B-P P S1 S2 D

S1 : Data to be added to/subtracted from or head number of the devices where the data to be added
to/subtracted from is stored (BCD 4 digits)
S2 : Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored
(BCD 4 digits)
D : Head number of the devices where the addition/subtraction operation result will be stored (BCD 4 digits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S1 ––

S2 ––

D –– ––

Function
B+

(1) Adds the BCD 4-digit data designated by S1 and the BCD 4-digit data designated by S2 , and
stores the result of the addition at the device designated by D .
S1 S2 D

5 6 7 8 1 2 3 4 6 9 1 2

(2) 0 to 9999 (BCD 4 digits) can be assigned to S1 , S2 and D .

(3) If the result of the addition operation exceeds 9999, the higher bits are ignored.
The carry flag in this case does not go ON.
6 4 3 2 3 5 8 3 0 0 1 5

B-

(1) Subtracts the BCD 4-digit data designated by S1 and the BCD 4-digit data designated by S2 ,
and stores the result of the subtraction at the device designated by D .
S1 S2 D

0 6 7 8 0 2 3 4 0 4 4 4
Digits exceeding the designated
number of digits are assumed to be 0.

(2) 0 to 9999 (BCD 4 digits) can be assigned to S1 , S2 and D .

6-36
 B+(P), B-(P)

(3) The following will result if an underflow is generated by the subtraction operation:
The carry flag in this case does not go ON.
1
0 0 0 1 0 0 0 3 9 9 9 8

Operation Error 2
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0. 3
• The S1 , S2 D or BCD data is outside the 0 to 9999 range. (Error code: 4100)

4
Program Example
(1) The following program adds the D3 BCD data and the Z1 BCD data when X20 goes ON, and
4
outputs the result to Y8 to Y17.
[Ladder Mode] [List Mode]
6
Step Instruction Device

7
(2) The following program subtracts the BCD data at D20 from the BCD data at D10 when X20
goes ON, and stores the result at R10. 8
[Ladder Mode] [List Mode]
Step Instruction Device

6.2.5 BCD 4-digit addition and subtraction operations (B+(P),B-(P))

6.2 Arithmetic Operation Instructions

6-37
 DB+(P),DB-(P)

6.2.6 BCD 8-digit addition and subtraction operations

(DB+(P),DB-(P))
DB+(P),DB-(P)

Basic High
performance Process Redundant Universal LCPU

When two data are set (( D +1, D )+( S +1, S ) ( D +1, D ), ( D +1, D )-( S +1, S ) ( D +1, D ))

indicates an instruction symbol of DB+/DB- .

Command
DB+, DB- S D

Command
DB+P. DB-P P S D

S : Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored
(BCD 8 digits)
D : Head number of the devices where the data to be added to/subtracted from is stored (BCD 8 digits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S ––

D –– ––

Function
DB+

(1) Adds the BCD 8-digit data designated by D and the BCD 8-digit data designated by S , and
stores the result of the addition at the device designated by D .
D D S S D D

(Upper 4 digits)(Lower 4 digits) (Upper 4 digits)(Lower 4 digits) (Upper 4 digits)(Lower 4 digits)

0 9 8 7 1 0 6 8 0 0 3 2 3 4 5 6 1 0 1 9 4 5 2 4

Digits exceeding the designated number

of digits are assumed to be 0.

(2) 0 to 99999999 (BCD 8 digits) can be assigned to S and D .

(3) If the result of the addition operation exceeds 99999999, the upper bits will be ignored.
The carry flag in this case does not go ON.
9 9 0 0 0 0 0 0 0 1 6 5 4 3 2 1 0 0 6 5 4 3 2 1

DB-

(1) Subtracts the BCD 8-digit data designated by D and the BCD 8-digit data designated by S ,
and stores the result of the subtraction at the device designated by D .
D +1 D S +1 S D +1 D

(Upper 4 digits) (Lower 4 digits) (Upper 4 digits) (Lower 4 digits) (Upper 4 digits) (Lower 4 digits)
0 9 8 7 1 0 6 8 0 0 3 2 3 4 5 6 0 9 5 4 7 6 1 2

Digits exceeding the designated number

of digits are assumed to be 0.

6-38
 DB+(P),DB-(P)

(2) 0 to 99999999 (BCD 8 digits) can be assigned to S and D .

(3) The following will result if an underflow is generated by the subtraction operation: The carry 1
flag in this case does not go ON.
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 9 9 9 9 9 9 9 9 9
2
Operation Error
3
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• The S or D BCD data is outside the 0 to 99999999 range. (Error code: 4100) 4
Program Example
4
(1) The following program adds the BCD data 12345600 and 34567000, stores the result at
D887 and D888, and at the same time outputs them to from Y30 to Y4F.
[Ladder Mode] 6
Stores 12345600 in BCD to D887 and D888.

Adds 34567000 in BCD to the value in D887 and D888,

7
and stores the result to D887 and D888.

Outputs the data in D887 and D888 to Y30 to Y4F.

8

[List Mode]

6.2.6 BCD 8-digit addition and subtraction operations (DB+(P),DB-(P))

6.2 Arithmetic Operation Instructions
Step Instruction Device

(2) The following program subtracts the BCD data 98765432 from 12345678, stores the result
at D100 and D101, and at the same time outputs it from Y30 to Y4F.
[Ladder Mode]

Stores 98765432 in BCD to D100 and D101.

Subtracts the value in D100 and D101 from 12345678

in BCD, and stores the result to D100 and D101.

Outputs the data in D100 and D101 to T30

to Y4F.

[List Mode]
Step Instruction Device

6-39
 DB+(P),DB-(P)

When three data are set (( S1 +1, S1 )+( S2 +1, S2 ) ( D +1, D ), ( S1 +1, S1 )-( S2 +1, S2 ) ( D +1, D ))

indicates an instruction symbol of DB+/ DB .

Command
DB+, DB- S1 S2 D

Command
DB+P, DB-P P S1 S2 D

S1 : Data to be added to/subtracted from or head number of the devices where the data to be added
to/subtracted from is stored (BCD 8 digits)
S2 : Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored
(BCD 8 digits)
D : Head number of the devices where the addition/subtraction operation result is stored (BCD 8 digits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S1 ––

S2 ––

D –– ––

Function
DB+

(1) Adds the BCD 8-digit data designated by S1 and the BCD 8-digit data designated by S2 , and
stores the result of the addition at the device designated by D .
S1 +1 S1 S2 +1 S2 D +1 D

(Upper 4 digits) (Lower 4 digits) (Upper 4 digits) (Lower 4 digits) (Upper 4 digits) (Lower 4 digits)
5 6 7 8 9 1 2 3 + 0 1 2 3 4 5 6 7 5 8 0 2 3 6 9 0
Digits exceeding the designated number
of digits are assumed to be 0.

(2) 0 to 99999999 (BCD 8 digits) can be assigned to S1 , S2 and D .

(3) If the result of the addition operation exceeds 99999999, the upper bits will be ignored.
The carry flag in this case does not go ON.
9 9 0 0 0 0 0 0 0 1 6 5 4 3 2 1 0 0 6 5 4 3 2 1

6-40
 DB+(P),DB-(P)

DB-

(1) Subtracts the BCD 8-digit data designated by S1 and the BCD 8-digit data designated by S2 , 1
and stores the result of the subtraction at the device designated by D .
S1 +1 S1 S2 +1 S2 D +1 D
2
(Upper 4 digits) (Lower 4 digits) (Upper 4 digits) (Lower 4 digits) (Upper 4 digits) (Lower 4 digits)
5 6 7 8 9 1 2 3 0 1 2 3 4 5 6 7 5 5 5 5 4 5 5 6
Digits exceeding the designated
number of digits are assumed to be 0.
3
(2) 0 to 99999999 (BCD 8 digits) can be assigned to S1 , S2 and D .
(3) The following will result if an underflow is generated by the subtraction operation:
4
The carry flag in this case does not go ON.
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 9 9 9 9 9 9 9 9 9
4

Operation Error
6
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• The S1 , S2 D or BCD data is outside the 0 to 99999999 range. (Error code: 4100)
7

Program Example 8
(1) The following program adds the BCD data at D3 and D4 to the BCD data at Z1 and Z2 when
X20 goes ON, and stores the result at R10 and R11.
[Ladder Mode] [List Mode]

6.2.6 BCD 8-digit addition and subtraction operations (DB+(P),DB-(P))

6.2 Arithmetic Operation Instructions
Step Instruction Device

6-41
 B*(P),B/(P)

6.2.7 BCD 4-digit multiplication and division operations

(B*(P),B/(P))
B*(P),B/(P)

Basic High
performance Process Redundant Universal LCPU

indicates an instruction symbol of B * ,B/ .

Command
B * , B/ S1 S2 D

Command
B * P, B/P P S1 S2 D

S1 : Data to be multiplied/divided or head number of the devices where the data to be multiplied/divided is stored
(BCD 4 digits)
S2 : Data for multiplying/dividing or head number of the devices where the data for multiplying/dividing is stored
(BCD 4 digits)
D : Head number of the devices where the multiplication/division operation result will be stored (BCD 8 digits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S1 ––

S2 ––

D –– ––

Function
B*
(1) Multiplies BCD data designated by S1 and BCD data designated by S2 , and stores the result
in the device designated by D .
D +1 D
S1 S2 (Upper 4 digits) (Lower 4 digits)

5 6 7 8 0 8 7 6 0 4 9 7 3 9 2 8

(2) 0 to 9999 (BCD 4 digits) can be assigned to S1 and S2 .

B/
(1) Divides BCD data designated by S1 and BCD data designated by S2 , and stores the result in
the device designated by D .
S1 S2 D (Quotient) D +1 (Remainder)

5 6 7 8 / 0 8 7 6 0 0 0 6 0 4 2 2
Digits exceeding the designated number of digits are
assumed to be 0.
(2) Uses 32 bits to store the result of the division as quotient and remainder
Quotient (BCD 4 digits) :Stored at the lower 16 bits.
Remainder (BCD 4 digits) :Stored at the upper 16 bits.
(3) If D has been designated as a bit device, the remainder of the operation will not be stored.

6-42
 B*(P),B/(P)

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The S1 or S2 BCD data is outside the 0 to 9999 range. (Error code: 4100)
2
• Attempt to divide S2 by 0. (Error code: 4100)
3
Program Example
(1) The following program multiplies, when X20 is turned ON, the BCD data at X0 to XF by the 4
BCD data at D8 and stores the operation result at D0 to D1.
[Ladder Mode] [List Mode]
Step Instruction Device 4

6
[Operation]

XF X0
D8 D1 (Upper 4 digits) D0 (Lower 4 digits)
7
9 7 5 3 8 6 4 2 8 4 2 8 5 4 2 6
Multiplicand Multiplier Multiplication result

(2) The following program divides 5678 by the BCD data 1234, stores the result at D502 and
8
D503, and at the same time outputs the quotient to Y30 to Y3F.
[Ladder Mode] [List Mode]
Step Instruction Device

6.2.7 BCD 4-digit multiplication and division operations (B*(P),B/(P))

6.2 Arithmetic Operation Instructions
[Operation]
D502 D503

5 6 7 8 / 1 2 3 4 0 0 0 4 0 7 4 2
Quotient Remainder
Y3F Y30
0 0 0 4
Quotient

6-43
 DB*(P),DB/(P)

6.2.8 BCD 8-digit multiplication and division operations

(DB*(P),DB/(P))
DB*(P),DB/(P)

Basic High
performance Process Redundant Universal LCPU

indicates an instruction symbol of DB * ,DB/ .

Command
DB * , DB/ S1 S2 D

Command
DB * P, DB/P P S1 S2 D

S1 : Data to be multiplied/divided or head number of the devices where the data to be multiplied/divided is stored
(BCD 8 digits)
S2 : Data for multiplying/dividing or head number of the devices where the data for multiplying/dividing is stored
(BCD 8 digits)
D : Head number of the devices where the multiplication/division operation result will be stored (BCD 16 digits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S1 ––

S2 ––

D –– ––

Function
DB*
(1) Multiplies the BCD 8-digit data designated by S1 and the BCD 8-digit data designated by S2 ,
and stores the product at the device designated by D .
S1 +1 S1 S2 +1 S2

9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9

D +3 D +2 D +1 D

9 9 9 9 9 9 9 8 0 0 0 0 0 0 0 1

(2) If D has designated a bit device, the lower 8 digits (lower 32 bits) will be used for the
product, and the higher 8 digits (upper 32 bits) cannot be designated.
K1 ....Lower 1 digit (b0 to 3), K4 ....Lower 4 digits (b0 to 15), K8.....Lower 8 digits (b0 to 31)
(3) 0 to 99999999 (BCD 8 digits) can be assigned to S1 and S2 .
DB/
(1) Divides 8-digit BCD data designated by S1 and 8-digit BCD data designated by S2 , and
stores the result in the device designated by D .
S1 +1 S1 S2 +1 S2

5 6 7 8 9 1 2 3 / 0 1 2 3 4 5 6 7
Digits exceeding the designated number of digits
are assumed to be 0
D +1 D D +3 D +2
Quotient (Upper 4 digits) (Lower 4 digits) Remainder (Upper 4 digits) (Lower 4 digits)

0 0 0 0 0 0 4 5 0 1 2 3 3 6 0 8

6-44
 DB*(P),DB/(P)

(2) 64 bits are used for the result of the division operation, and stored as quotient and
remainder.
1
Quotient (BCD 8 digits) :Stored at the lower 32 bits.
Remainder (BCD 8 digits) :Stored at the upper 32 bits.

(3) If D has been designated as a bit device, the remainder of the operation will not be stored. 2

Operation Error 3
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
4
• The S1 or S2 BCD data is outside the 0 to 99999999 range. (Error code: 4100)

• Attempt to divide S2 by 0. (Error code: 4100)

4
Program Example
(1) The following program multiplies the BCD data 67347125 and 573682, stores the result from 6
D502 to D505, and at the same time outputs the upper 8 digits to Y30 to Y4F.
[Ladder Mode] [List Mode]
Step Instruction Device
7

[Operation]

6.2.8 BCD 8-digit multiplication and division operations (DB*(P),DB/(P))

6.2 Arithmetic Operation Instructions
D505 D504 D503 D502

6 8 3 4 7 1 2 5 0 0 5 7 3 6 8 2 0 0 3 9 2 0 9 5 1 5 3 6 4 2 5 0
Multiplicand Multiplier
Y4F Y30
0 0 3 9 2 0 9 5

(2) The following program divides the BCD data from X20 to X3F by the BCD data at D8 and D9
when X0B goes ON, and stores the result from D765 to D768.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
D9 (Upper 4 digits) D8 (Lower 4 digits)
X3F X20
9 9 8 6 4 3 2 1 / 1 5 2 6 3 7 4 8
Dividend Divisor
D766 D765 D768 D767
(Upper 4 digits) (Lower 4 digits) (Upper 4 digits) (Lower 4 digits)

0 0 0 0 0 0 0 6 0 8 2 8 1 8 3 3

Quotient Remainder

6-45
 E+(P),E-(P)

6.2.9 Addition and subtraction of floating decimal point data

(Single precision) (E+(P),E-(P))
E+(P),E-(P)

Ver.
High
Basic performance Process Redundant Universal LCPU

Basic model QCPU: The upper five digits of the serial No. are "04122" or larger.

When two data are set (( D +1, D )+( S +1, S ) ( D +1, D ), ( D +1, D )-( S +1, S ) ( D +1, D ))

indicates an instruction symbol of E+/E- .

Command
E+, E- S D

Command
E+P, E-P P S D

S : Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored
(real number)
D : Head number of the devices where the data to be added to/subtracted from is stored (real number)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word E

S –– –– *1 ––

D –– –– *1 –– ––

*1:Available only in multiple Universal model QCPU and LCPU

Function
E+

(1) Adds the 32-bit floating decimal point type real number designated at D and the 32-bit
floating decimal point type real number designated at S , and stores the sum in the device
designated at D .
D +1 D S +1 S D +1 D
+

32-bit floating-point 32-bit floating-point 32-bit floating-point

real number real number real number
(2) Values which can be designated at S and D and which can be stored, are as follows:

0, 2-126 | Designated value (stored value) | < 2128

E-
(1) Subtracts a 32-bit floating decimal point type real number designated by D and a 32-bit
floating decimal point type real number designated by S , and stores the result at a device
designated by D .
D +1 D S +1 S D +1 D

32-bit floating-point 32-bit floating-point 32-bit floating-point

real number real number real number

6-46
 E+(P),E-(P)

(2) Values which can be designated at S and D and which can be stored, are as follows:

0, 2-126 | Designated value (stored value) | < 2128

1
Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
2
an error code is stored into SD0.
• The contents of the designated device or the result of the addition are not "0", or not within
the following range: (Error code: 4100)
3
0, 2-126 | Contents of designated device | < 2128
(For the Basic model QCPU, High Performance model QCPU, Process CPU, Redundant
CPU) (Error code: 4100)
4
• The value of the specified device is 0.*2
(For the Basic model QCPU, High Performance model QCPU, Process CPU, Redundant 4
CPU) (Error code: 4100)

*2: There are CPU modules that will not result in an operation error if 0 is specified.
Refer to Section 3.2.4 for details. 6
• The result of addition and subtraction exceeds the following range. (The overflow occurs.)
(For the Universal model QCPU, LCPU)
2128 | Result of addition and subtraction | (Error code: 4141) 7
• The value of the specified device is 0, unnormalized number, nonnumeric, and ± .
(For the Universal model QCPU, LCPU) (Error code: 4140)
8
Program Example
(1) The following program adds the 32-bit floating decimal point type real numbers at D3 and D4

6.2.9 Addition and subtraction of floating decimal point data (Single precision) (E+(P),E-(P))
6.2 Arithmetic Operation Instructions
and the 32-bit floating decimal point type real numbers at D10 and D11 when X20 goes ON,
and stores the result at D3 and D4.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
D4 D3 D11 D10 D4 D3
5961.437 12003.200 17964.637

(2) The following program subtracts the 32-bit floating decimal point type real number at D10
and D11 from the 32-bit floating decimal point type real numbers at D20 and D21, and stores
the result of the subtraction at D20 and D21.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
D21 D20 D11 D10 D21 D20
97365.203 76059.797 21305.406

6-47
 E+(P),E-(P)

When three data are set (( S1 +1, S1 )+( S2 +1, S2 ) ( D +1, D ), ( S1 +1, S1 )-( S2 +1, S2 ) ( D +1, D ))

indicates an instruction symbol of E+/E-.

Command
E+, E- S1 S2 D

Command
E+P, E-P P S1 S2 D

S1 : Data to be added to/subtracted from or head number of the devices where the data to be added
to/subtracted from is stored (real number)
S2 : Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored
(real number)
D : Head number of the devices where the addition/subtraction operation result is stored (real number)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word E

S1 –– –– *1 ––

S2 –– –– *1 ––

D –– –– *1 –– ––

*1:Available only in multiple Universal model QCPU and LCPU

Function
E+

(1) Adds the 32-bit floating decimal point type real number designated at S1 and the 32-bit
floating decimal point type real number designated at S2 , and stores the sum in the device
designated at D .
S1 +1 S1 S2 +1 S2 D +1 D
+

32-bit floating-point 32-bit floating-point 32-bit floating-point

real number real number real number

(2) Values which can be designated at S1 , S2 and D and which can be stored, are as follows:

0, 2-126 | Designated value (stored value) | < 2128

E-

(1) Subtracts a 32-bit floating decimal point type real number designated by S1 and a 32-bit
floating decimal point type real number designated by S2 , and stores the result at a device
designated by D .
S1 +1 S1 S2 +1 S2 D +1 D

32-bit floating-point 32-bit floating-point 32-bit floating-point

real number real number real number

(2) Values which can be designated at S1 and S2 and D which can be stored, are as follows:

0, 2-126 | Designated value (stored value) | < 2128

6-48
 E+(P),E-(P)

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The contents of the designated device or the result of the addition are not "0", or not within 2
the following range:
0, 2-126 | Contents of designated device | < 2128
(For the Basic model QCPU, High Performance model QCPU, Process CPU, Redundant 3
CPU) (Error code: 4100)
• The value of the specified device is 0.*2
(For the Basic model QCPU, High Performance model QCPU, Process CPU, Redundant
4
CPU) (Error code: 4100)

*2: There are CPU modules that will not result in an operation error if 0 is specified.
4
Refer to Section 3.2.4 for details.

• The result of addition and subtraction exceeds the following range. (The overflow occurs.)
(For the Universal model QCPU, LCPU) 6
2128 | Result of addition and subtraction | (Error code: 4141)
• The value of the specified device is 0, unnormalized number, nonnumeric, and ± . 7
(For the Universal model QCPU, LCPU) (Error code: 4140)

Program Example 8
(1) The following program adds the 32-bit floating decimal point type real numbers at D3 and D4
and the 32-bit floating decimal point type real numbers at D10 and D11 when X20 goes ON,
and outputs the result to R0 and R1.

6.2.9 Addition and subtraction of floating decimal point data (Single precision) (E+(P),E-(P))
6.2 Arithmetic Operation Instructions
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
D4 D3 D11 D10 R1 R0
5961.437 12003.200 17964.637

(2) The following programs subtracts the 32-bit floating decimal point type real numbers at D20
and D21 from the 32-bit floating decimal point type real numbers at D11 and D10, and stores
the result at D30 and D31.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
D11 D10 D21 D20 D31 D30
97365.203 76059.797 21305.406

6-49
 ED+(P),ED-(P)

6.2.10 Addition and subtraction of floating decimal point data

(Double precision) (ED+(P),ED-(P))
ED+(P),ED-(P)

High
Basic performance Process Redundant Universal LCPU

When two data are set (( D +3, D +2, D +1, D )+( S +3, S +2, S +1, S ) ( D +3, D +2, D +1, D ),
( D +3, D +2, D +1, D )-( S +3, S +2, S +1, S ) ( D +3, D +2, D +1, D ))

indicates an instruction symbol of ED+/ED-.

Command
ED+, ED- S D

Command
ED+P, ED-P P S D

S : Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored
(real number)
D : Head number of the devices where the data to be added to/subtracted from is stored (real number)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word E

S –– –– ––

D –– –– –– ––

Function
ED+

(1) Adds the 64-bit floating decimal point type real number designated at D and the 64-bit
floating decimal point type real number designated at S , and stores the sum in the device
designated at D .

D +3 D +2 D +1 D S +3 S +2 S +1 S D +3 D +2 D +1 D

64-bit floating-point 64-bit floating-point 64-bit floating-point

real number real number real number

(2) Values which can be designated at S and D and which can be stored, are as follows:

0, 2-1022 | Designated value (stored value) | < 21024

6-50
 ED+(P),ED-(P)

ED-

(1) Subtracts a 64-bit floating decimal point type real number designated by D and a 64-bit 1
floating decimal point type real number designated by S , and stores the result at a device
designated by .
D
2
D +3 D +2 D +1 D S +3 S +2 S +1 S D +3 D +2 D +1 D

64-bit floating-point 64-bit floating-point 64-bit floating-point 3

real number real number real number

(2) Values which can be designated at and and which can be stored, are as follows:
4
S D

0, 2-1022 | Designated value (stored value) | < 21024

Operation Error 4
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0. 6
• The contents of the designated device or the result of the addition are not "0", or not within
the following range: (Error code: 4140)
0, 2-1022 | Contents of designated device | < 21024 7
• The value of the designated device is 0. (Error code: 4140)
• The result of addition/subtraction exceeds the following range (Operation results in an 8
overflow):
21024 | Result of operation | (Error code: 4141)

Program Example

6.2.10 Addition and subtraction of floating decimal point data (Double precision) (ED+(P),ED-(P))
6.2 Arithmetic Operation Instructions
(1) The following program adds the 64-bit floating decimal point type real numbers at D3 to D6
and the 64-bit floating decimal point type real numbers at D10 to D13 when X20 goes ON,
and stores the result at D3 to D6.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
D6 D5 D4 D3 D13 D12 D11 D10 D6 D5 D4 D3
5961.437 12003.200 17964.637

(2) The following program subtracts the 64-bit floating decimal point type real number at D10 to
D13 from the 64-bit floating decimal point type real numbers at D20 to D23, and stores the
result of the subtraction at D20 to D23.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
D23 D22 D21 D20 D13 D12 D11 D10 D23 D22 D21 D20
97365.203 76059.797 21305.406

6-51
 ED+(P),ED-(P)

When three data are set(( S1 +3, S1 +2, S1 +1, S1 )+( S2 +3, S2 +2, S2 +1, S2 ) ( D +3, D +2, D +1, D ),
( S1 +3, S1 +2, S1 +1, S1 )-( S2 +3, S2 +2, S2 +1, S2 ) ( D +3, D +2, D +1, D ))

indicates an instruction symbol of ED+/ED-.

Command
ED+, ED- S1 S2 D

Command
ED+P, ED-P P S1 S2 D

S1 : Data to be added to/subtracted from or head number of the devices where the data to be added
to/subtracted from is stored (real number)
S2 : Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored
(real number)
D : Head number of the devices where the addition/subtraction operation result is stored (real number)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word E

S1 –– –– ––

S2 –– –– ––

D –– –– –– ––

Function
ED+

(1) Adds the 64-bit floating decimal point type real number designated at S1 and the 64-bit
floating decimal point type real number designated at S2 , and stores the sum in the device
designated at D .

S1 +3 S1 +2 S1 +1 S1 S2 +3 S2 +2 S2 +1 S2 D +3 D +2 D +1 D
+

64-bit floating-point 64-bit floating-point 64-bit floating-point

real number real number real number

(2) Values which can be designated at S1 , S2 and D and which can be stored, are as follows:

0, 2-1022 | Designated value (stored value) | < 21024

ED-

(1) Subtracts a 64-bit floating decimal point type real number designated by S1 and a 64-bit
floating decimal point type real number designated by S2 , and stores the result at a device
designated by D .
S1 +3 S1 +2 S1 +1 S1 S2 +3 S2 +2 S2 +1 S2 D +3 D +2 D +1 D

64-bit floating-point 64-bit floating-point 64-bit floating-point

real number real number real number

(2) Values which can be designated at S1 and S2 and D which can be stored, are as follows:

0, 2-1022 | Designated value (stored value) | < 21024

6-52
 ED+(P),ED-(P)

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The contents of the designated device or the result of the addition are not "0", or not within 2
the following range: (Error code: 4140)
0, 2-1022 | Contents of designated device | < 21024
3
• The value of the specified device is 0. (Error code: 4140)
• The result of addition/subtraction exceeds the following range (Operation results in an
overflow): 4
21024 | Result of operation | (Error code: 4141)

Program Example 4
(1) The following program adds the 64-bit floating decimal point type real numbers at D3 to D6
and the 64-bit floating decimal point type real numbers at D10 to D13 when X20 goes ON, 6
and outputs the result at R0 to R3.
[Ladder Mode] [List Mode]
Step Instruction Device 7

8
[Operation]
D6 D5 D4 D3 D13 D12 D11 D10 R3 R2 R1 R0
5961.437 12003.200 17964.637

6.2.10 Addition and subtraction of floating decimal point data (Double precision) (ED+(P),ED-(P))
6.2 Arithmetic Operation Instructions
(2) The following programs subtracts the 64-bit floating decimal point type real numbers at D20
to D23 from the 64-bit floating decimal point type real numbers at D10 to D13, and stores the
result at D30 to D33.
[Ladder Mode] [List Mode]
SM 400 Step Instruction Device
10 20 30
SM 400
20 30

[Operation]
D13 D12 D11 D10 D23 D22 D21 D20 D33 D32 D31 D30
97365.203 76059.797 21305.406

6-53
 E*(P),E/(P)

6.2.11 Multiplication and division of floating decimal point data

(Single precision) (E*(P),E/(P))
E*(P),E/(P)

Ver.
High
Basic performance Process Redundant Universal LCPU

Basic model QCPU: The upper five digits of the serial No. are "04122" or larger.

indicates an instruction symbol of E* , E/ .

Command
E* , E/ S1 S2 D

Command
E* P, E/P P S1 S2 D

S1 : Data to be multiplied/divided or head number of the devices where the data to be multiplied/divided is stored
(real number)
S2 : Data for multiplying/dividing or head number of the devices where the data for multiplying/dividing is stored
(real number)
D : Head number of the devices where the multiplication/division operation result will be stored (real number)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word E

S1 –– –– *1 ––

S2 –– –– *1 ––

D –– –– *1 –– ––

*1:Available only in multiple Universal model QCPU and LCPU

Function
E*
(1) Multiplies the 32-bit floating decimal point real number designated by S1 by the 32-bit
floating decimal point real number designated by S2 and stores the operation result at the
device designated by D .
S1 +1 S1 S2 +1 S2 D +1 D

32-bit floating-point 32-bit floating-point 32-bit floating-point

real number real number real number

(2) Values which can be designated at S1 , S2 and D and which can be stored, are as follows:

0, 2-126 | Designated value (stored value) | < 2128

E/
(1) Divides the 32-bit floating decimal point real number designated by S1 by the 32-bit floating
decimal point real number designated by S2 and stores the operation result at the device
designated by D .
S1 +1 S1 S2 +1 S2 D +1 D
/

32-bit floating-point 32-bit floating-point 32-bit floating-point

real number real number real number

6-54
 E*(P),E/(P)

(2) Values which can be designated at S1 , S2 and D and which can be stored, are as follows:

0, 2-126 | Designated value (stored value) | < 2128 1

Operation Error
2
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The value of the specified device or the result of multiplication is not within the following 3
range:
0, 2-126 | Contents of designated device | < 2128
(For the Basic model QCPU, High Performance model QCPU, Process CPU, Redundant 4
CPU) (Error code: 4100)
• The value of the designated device is 0.*2
(For the Basic model QCPU, High Performance model QCPU, Process CPU, Redundant
4
CPU) (Error code: 4100)
*2: There are CPU modules that will not result in an operation error if -0 is specified.
Refer to Section 3.2.4 for details.
6
• The result of multiplication and division exceeds the following range.
(The overflow occurs.)(For the Universal model QCPU, LCPU)
7
2128 | Result of addition and subtraction | (Error code: 4141)
• The value of the specified device is 0, unnormalized number, nonnumeric, and ± .
(For the Universal model QCPU, LCPU) (Error code: 4140) 8
Program Example
(1) The following program multiplies the 32-bit floating decimal point real numbers at D3 and D4

6.2.11 Multiplication and division of floating decimal point data (Single precision) (E*(P),E/(P))
6.2 Arithmetic Operation Instructions
and the 32-bit floating decimal point real numbers at D10 and D11, and stores the result at
R0 and R1.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
D4 D3 D11 D10 R1 R0
36.7896 11.9278 438.8190

(2) The following program divides the 32-bit floating decimal point real numbers at D10 and D11
by the 32-bit floating decimal point real numbers at D20 and D21, and stores the result at
D30 and D31.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
D11 D10 D21 D20 D31 D30
52171.39 9.73521 5359.041

6-55
 ED*(P),ED/(P)

6.2.12 Multiplication and division of floating decimal point data

(Double precision) (ED*(P),ED/(P))
ED*(P),ED/(P)

High
Basic performance Process Redundant Universal LCPU

indicates an instruction symbol of ED*, ED/.

Command
ED*, ED/ S1 S2 D

Command
ED* P, ED/P P S1 S2 D

S1 : Data to be multiplied/divided or head number of the devices where the data to be multiplied/divided is stored
(real number)
S2 : Data for multiplying/dividing or head number of the devices where the data for multiplying/dividing is stored
(real number)
D : Head number of the devices where the multiplication/division operation result will be stored (real number)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word E

S1 –– –– ––

S2 –– –– ––

D –– –– –– ––

Function
ED*
(1) Multiplies the 64-bit floating decimal point real number designated by S1 by the 64-bit
floating decimal point real number designated by S2 and stores the operation result at the
device designated by D .
S1 +3 S1 +2 S1 +1 S1 S2 +3 S2 +2 S2 +1 S2 D +3 D +2 D +1 D

64-bit floating-point 64-bit floating-point 64-bit floating-point

real number real number real number

(2) Values which can be designated at S1 , S2 and D and which can be stored, are as follows:
0, 2-1022 | Designated value (stored value) | < 21024
(3) When the operation results in -0 or an underflow, the result is processed as 0.

6-56
 ED*(P),ED/(P)

ED/
(1) Divides the 64-bit floating decimal point real number designated by S1 by the 64-bit floating 1
decimal point real number designated by S2 and stores the operation result at the device
designated by D .
S1 +3 S1 +2 S1 +1 S1 S2 +3 S2 +2 S2 +1 S2 D +3 D +2 D +1 D 2
64-bit floating-point 64-bit floating-point 64-bit floating-point
real number real number real number 3
(2) Values which can be designated at S1 , S2 and D and which can be stored, are as follows:

0, 2-1022 | Designated value (stored value) | < 21024 4

(3) When the operation results in -0 or an underflow, the result is processed as 0.

4
Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
6
• The value of the specified device or the result of multiplication is not within the following
range: (Error code: 4140)
0, 2-1022 | Contents of designated device | < 21024
7
• The value of the designated device is 0. (Error code: 4140)

• The value of S2 at division operation is 0. (Error code: 4100) 8

• The result of multiplication/division exceeds the following range (Operation results in an
overflow):
21024 | Result of operation | (Error code: 4141)

6.2.12 Multiplication and division of floating decimal point data (Double precision) (ED*(P),ED/(P))
6.2 Arithmetic Operation Instructions
Program Example
(1) The following program multiplies the 64-bit floating decimal point real numbers at D3 to D6
and the 64-bit floating decimal point real numbers at D10 to D13, and stores the result at R0
to R3.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
D6 D5 D4 D3 D13 D12 D11 D10 R3 R2 R1 R0
36.7896 11.9278 438.8190

6-57
 ED*(P),ED/(P)

(2) The following program divides the 64-bit floating decimal point real numbers at D10 to D13
by the 64-bit floating decimal point real numbers at D20 to D23, and stores the result at D30
to D33.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]

D13 D12 D11 D10 D23 D22 D21 D20 D33 D32 D31 D30
52171.39 9.73521 5359.041

6-58
 BK+(P),BK-(P)

6.2.13 Block addition and subtraction (BK+(P),BK-(P))

BK+(P),BK-(P)
1
Basic High
performance Process Redundant Universal LCPU
2

3
indicates an instruction symbol of BK+, BK- .

Command
BK+, BK- S1 S2 D n
4
Command
BK+P, BK-P P S2 S2 D n
4
S1 : Head number of the devices where the data to be added to/subtracted from is stored (BIN 16 bits)

S2 : Data for additing/subtracting or head number of the devices where the data for additing/subtracting is stored 6
(BIN 16 bits)
D : Head number of the devices where the operation result will be stored (BIN 16 bits)
n : Number of addition/subtraction data blocks (BIN 16 bits)
7
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word $

S1 –– –– –– ––
8
S2 –– –– ––

D –– –– –– ––

n ––

6.2.13 Block addition and subtraction (BK+(P),BK-(P))

6.2 Arithmetic Operation Instructions
Function
BK+

(1) Adds n points of BIN data from the device designated by S1 and n-points of BIN data from
the device designated by S2 and stores the result from the device designated by D onward.
b15 b0 b15 b0 b15 b0
S1 1234 (BIN) S2 4000 (BIN) D 5234 (BIN)
S1 +1 4567 (BIN) S2 +1 1234 (BIN) D +1 5801 (BIN)
S1 +2 2000 (BIN) S2 +2 1234 (BIN) D +2 3234 (BIN)
n n n
S1 +(n 2) 1234 (BIN) S2 +(n 2) 5000 (BIN) D +(n 2) 3766 (BIN)
S1 +(n 1) 4000 (BIN) S2 +(n 1) 4321 (BIN) D +(n 1) 8321 (BIN)

(2) Block addition is performed in 16-bit units.

(3) The constant designated by S2 can be between 32768 and 32767 (BIN 16-bit data).
b15 b0 b15 b0
S1 1234 (BIN) D 5555 (BIN)
S1 +1 4567 (BIN) D +1 8888 (BIN)
b15 b0
S1 +2 2000 (BIN) D +2 2321 (BIN)
S2 4321 (BIN)
n n
S1 +(n 2) 1234 (BIN) D +(n 2) 3087 (BIN)
S1 +(n 1) 4000 (BIN) D +(n 1) 8321 (BIN)

6-59
 BK+(P),BK-(P)

(4) The following will happen when an underflow or overflow is generated in an operation result:
The carry flag in this case does not go ON.
K32767 +K2 K 32767
(7FFFH) (0002H) (8001H)

K 32767 +K 2 K32767
(8001H) (FFFEH) (7FFFH)

BK-

(1) Subtracts n points of BIN data from the device designated by S1 and n-points of BIN data
from the device designated by S2 and stores the result from the device designated by D
onward.
b15 b0 b15 b0 b15 b0
S1 8765 (BIN) S2 1234 (BIN) D 7531 (BIN)
S1 +1 8888 (BIN) S2 +1 5678 (BIN) D +1 3210 (BIN)
S1 +2 9325 (BIN) S2 +2 9876 (BIN) D +2 551 (BIN)
n n n
S1 +(n 2) 5000 (BIN) S2 +(n 2) 4321 (BIN) D +(n 2) 679 (BIN)
S1 +(n 1) 4352 (BIN) S2 +(n 1) 4000 (BIN) D +(n 1) 352 (BIN)

(2) Block subtraction is performed in 16-bit units.

(3) The constant designated by S2 can be between 32768 and 32767 (BIN 16-bit data).
b15 b0 b15 b0
S1 8765 (BIN) D 115 (BIN)
S1 +1 8888 (BIN) D +1 8 (BIN)
b15 b0
S1 +2 9325 (BIN) 8880 (BIN) D +2 445 (BIN)
S2
n n
S1 +(n 2) 5000 (BIN) D +(n 2) 3880 (BIN)
S1 +(n 1) 4352 (BIN) D +(n 1) 4528 (BIN)

(4) The following will happen when an underflow or overflow is generated in an operation result:
The carry flag in this case does not go ON.
K 32768 K2 K32766
(8000H) (0002H) (7FFEH)

K32767 K 2 32767
(7FFFH) (FFFEH) (8001H)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The n-bit range from the S1 , S2 or D device exceeds the range of that device.
(Error code: 4101)

• The device ranges of S1 and D overlap. (Except when the same device is assigned to S1

and D ) (Error code: 4101)

• The device ranges of S2 and D overlap. (Except when the same device is assigned to S2

and D ) (Error code: 4101)

6-60
 BK+(P),BK-(P)

Program Example
1
(1) The following program adds, when X20 is turned ON, the data stored at D100 to D103 to the
data stored at R0 to R3 and stores the operation result into the area starting from D200.
[Ladder Mode] [List Mode] 2
Step Instruction Device

[Operation] 4
b15 b0 b15 b0 b15 b0
D100 6789 (BIN) R0 1234 (BIN) D200 8023 (BIN)
D101 7821
D102 5432
(BIN)
(BIN)
R1
R2
2032
3252
(BIN)
(BIN)
D201 9853
D202 2180
(BIN)
(BIN)
4
D103 3520 (BIN) R3 1000 (BIN) D203 2520 (BIN)

D0 4
6
(2) The following program subtracts, when X1C is turned ON, the constant 8765 from the data
at D100 to D102 and stores the operation result into the area starting from R0.
[Ladder Mode] [List Mode] 7
Step Instruction Device

[Operation]
b15 b0 b15 b0

6.2.13 Block addition and subtraction (BK+(P),BK-(P))

6.2 Arithmetic Operation Instructions
D100 12345 (BIN) b15 b0 R0 3580 (BIN)
D101 8701 (BIN) 8765 (BIN) R1 64 (BIN)
D102 3502 (BIN) R2 5263 (BIN)

6-61
 DBK+(P),DBK-(P)

6.2.14 BIN 32-bit data block addition and subtraction operations

(DBK+(P),DBK-(P))
DBK+(P),DBK-(P)

Ver.
High
Basic performance Process Redundant Universal LCPU

QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later.

QnUDE(H)CPU: The serial number (first five digits) is "10102" or later.

indicates an instruction symbol of DBK+, DBK- .

Command
DBK+,DBK- S1 S2 D n

Command
DBKP+,DBK-P P S1 S2 D n

S1 : Head number of the devices where the data to be added and subtracted are stored (BIN 32 bits)
S2 : Addition and subtraction data or head number of the devices where the addition and subtraction data are
stored (BIN 32 bits)
D : Head number of the devices where the addition and subtraction operation result will be stored (BIN 32 bits)

n: Number of addition and subtraction data blocks (BIN 16 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K,H

S1 –– –– –– ––

S2 –– –– ––

D –– –– –– ––

n –– ––

Function
DBK+
(1) This instruction adds BIN 32-bit data stored in n-point devices starting from the device
specified by S1 to BIN 32-bit data stored in n-point devices starting from the device specified
by S2 or a constant. and then stores the operation result into the nth device specified by D
and up,
When a device is specified for S2

b31 b0 b31 b0 b31 b0

S1 ＋1, S1 -30000 (BIN) S2 ＋1, S2 50000 (BIN) D ＋1, D 20000 (BIN)
S1 ＋3, S1 ＋2 40000 (BIN) S2 ＋3, S2 ＋2 20000 (BIN) D ＋3, D ＋2 60000 (BIN)
S1 ＋5, S1 ＋4 -50000 (BIN) n ＋ S2 ＋5, S2 ＋4 -10000 (BIN) n D ＋5, D ＋4 -60000 (BIN) n

S1 ＋n 1, S1 ＋n 2 60000 (BIN) S2 ＋n 1, S2 ＋n 2 -20000 (BIN) D ＋n 1, D ＋n 2 40000 (BIN)

6-62
 DBK+(P),DBK-(P)

When a constant is specified for S2

S1 ＋1, S1
b31
-30000 (BIN)
b0
D ＋1, D
b31
20000 (BIN)
b0 1
S1 ＋3, S1 ＋2 40000 (BIN) b31 b0 D ＋3, D ＋2 90000 (BIN)
S1 ＋5, S1 ＋4 -50000 (BIN) n ＋ S2 ＋1, S2 50000 (BIN) D ＋5, D ＋4 0 (BIN) n
2
S1 ＋n 1, S1 ＋n 2 60000 (BIN) D ＋n 1, D ＋n 2 110000 (BIN)

(2) Block addition is executed in 32-bit units. 3

(3) The constant in the device specified by S2 can be between 2147483648 to 2147483647
(BIN 32-bit data).
(4) If the value specified by n is 0, the instruction will be not processed.
4
(5) The following will happen if an overflow occurs in an operation result:
The carry flag in this case is not turned on.
4
・K2147483647+K2 K 2147483647
(7FFFFFFFH) (00000002H ) ( 80000001H)

K2147483647
6
・ K 2147483647 +K 2
(80000001H) ( FFFFFFFEH) (7FFFFFFFH)

DBK- 7
(1) This instruction subtracts BIN 32-bit data stored in the n-point devices starting from the
device specified by S2 or a constant from BIN 32-bit data stored in n-point devices starting
8
from the device specified by S1 , and then stores the operation result into the nth device
specified by D and up,
When a device is specified for S2

6.2.14 BIN 32-bit data block addition and subtraction operations (DBK+(P),DBK-(P))
6.2 Arithmetic Operation Instructions
b31 b0 b31 b0 b31 b0
S1 ＋1, S1 -55555 (BIN) S2 ＋1, S2 44445 (BIN) D ＋1, D -1000000 (BIN)
S1 ＋3, S1 ＋2 33333 (BIN) S2 ＋3, S2 ＋2 3333 (BIN) D ＋3, D ＋2 30000 (BIN)
S1 ＋5, S1 ＋4 44444 (BIN) n S2 ＋5, S2 ＋4 -10000 (BIN) n D ＋5, D ＋4 54444 (BIN) n

S1 ＋n 1, S1 ＋n 2 13579 (BIN) S2 ＋n 1, S2 ＋n 2 12345 (BIN) D ＋n 1, D ＋n 2 1234 (BIN)

When a constant is specified for S2

b31 b0 b31 b0
S1 ＋1, S1 -99999 (BIN) D ＋1, D -109998 (BIN)
S1 ＋3, S1 ＋2 99999 (BIN) b31 b0 D ＋3, D ＋2 90000 (BIN)
S1 ＋5, S1 ＋4 -59999 (BIN) n S2 ＋1, S2 9999 (BIN) D ＋5, D ＋4 69998 (BIN) n

S1 ＋n 1, S1 ＋n 2 79999 (BIN) D ＋n 1, D ＋n 2 70000 (BIN)

(2) Block subtraction is executed in 32-bit units.

(3) The constant in the device specified by S2 can be between 2147483648 to 2147483647
(BIN 32-bit data).
(4) If the value specified by n is 0, the instruction will be not processed.

(5) D specifies out of the range of n-point devices starting from the device specified by S1 and
S2 .
However, S1 and S2 can specify the same device.

6-63
 DBK+(P),DBK-(P)

(6) The following will happen if an overflow occurs in an operation result:

The carry flag in this case is not turned on.

・K2147483647 −K−2 K 2147483647

(7FFFFFFFH) (00000002H ) ( 80000001H )

・ K 2147483647 −K2 K2147483647

(80000001H) ( FFFFFFFEH ) ( 7FFFFFFFH )

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an
error code is stored into SD0.
• A negative value is specified for n. (Error code: 4100)

• The range of the n-point devices starting from the device specified by S1 , S2 , or D
exceeds the specified device range. (Error code: 4101)

• The range of the n-point devices starting from the device specified by S1 overlaps with the
range of the n-point devices starting from the device specified by D . (Exclude the case
that S1 and D specify the same device. (Error code: 4101)

• The range of the n-point devices starting from the device specified by S2 overlaps with the
range of the n-point devices starting from the device specified by D . (Error code: 4101)

6-64
 DBK+(P),DBK-(P)

Program Example
1
(1) The following program adds the value data stored at R0 to R5 to the constant, and then
stores the operation result into D30 to D35, when M0 is turned on.
[Ladder Mode] [List Mode] 2
Step Instruction Device

[Operation] 4
b31 b0 b31 b0
R1,R0 600000 D31,D30 723456
R3,R2
R5,R4
-800000
-123456
＋ 123456 D33,D32
D35,D34
-676544
0
4

(2) The following program subtracts the value data stored at D50 to D59 from the value data
stored at D100 to D109, and then stores the operation result into R100 to R109, when M0 is 6
turned on.
[Ladder Mode] [List Mode]
Step Instruction Device
7

8
[Operation]
b31 b0 b31 b0 b31 b0
D101,D100 12345 D51,D50 11111 R101,R100 1234

6.2.14 BIN 32-bit data block addition and subtraction operations (DBK+(P),DBK-(P))
6.2 Arithmetic Operation Instructions
D103,D102 54321 D53,D52 -11111 R103,R102 65432
D105,D104 -12345 D55,D54 22222 R105,R104 -34567
D107,D106 -54321 D57,D56 -22222 R107,R106 -32099
D109,D108 99999 D58,D58 33333 R109,R108 66666

6-65
 $+(P)

6.2.15 Linking character strings ($+(P))

$+(P)

High
Basic performance Process Redundant Universal LCPU

When two data are set ( D + S D )

Command
$+ $+ S D

Command
$+P $+P S D

S : Data for linking or head number of the devices where the data for linking is stored (character string)

D : Head number of the devices where the data to be linked is stored (character string)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word $

S –– –– ––

D –– –– –– ––

Function
(1) Links the character string data designated by S after the character string data designated
by D and stores the result into the area starting with the device number designated by D .
The object of character string data is that character string data stored from device numbers
designated at D and S to that stored at "00H".
b15 b8 b7 b0 b15 b8 b7 b0 b15 b8 b7 b0
D 42H (B) 41H (A) S 32H (2) 31H (1) 42H (B) 41H (A)
D +1 44H (D) 43H (C) S +1 34H (4) 33H (3) D +1 44H (D) 43H (C)
D +2 00H 45H (E) S +2 36H (6) 35H (5) D +2 31H (1) 45H (E)
S +3 00H D +3 33H (3) 32H (2)
"ABCDE"
D +4 35H (5) 34H (4)
"123456"
D +5 00H 36H (6)
"ABCDE123456"

(2) When character strings are linked, the "00H", which indicates the end of character string
data designated at D , is ignored, and the character string designated at S is appended to
the last character of the D string.

6-66
 $+(P)

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The entire character string linked from the device number designated by D to the final
2
device number of the relevant device cannot be stored. (Error code: 4101)

• The storage device numbers for the character strings designated by S and D overlap. 3
(Error code: 4101)

• The character string of S and D exceeds 16383 characters. (Error code: 4101)
4
Program Example
(1) The following program links the character string stored from D10 to D12 to the character
4
string "ABCD" when X0 is ON.
[Ladder Mode] [List Mode]
Instruction Device
6
Step

7
[Operation]
b15 b8 b7 b0 b15 b8 b7 b0 8
D10 62 H (b) 61H (a) D10 62 H (b) 61H (a)
D11 64 H (d) 63 H (c) + "ABCD" D11 64 H (d) 63 H (c)
D12 00H 65 H (e) D12 41H (A) 65 H (e)
D13 43H (C) 42H (B)
D14 00H 44H (D)

6.2.15 Linking character strings ($+(P))

6.2 Arithmetic Operation Instructions
Automatically stores "00H".

6-67
 $+(P)

When three data are set ( S1 + S2 D )

Command
$+ $+ S1 S2 D

Command
$+P $+P S1 S2 D

S1 : Data for linking or head number of the devices where the data for linking is stored (character string)

S2 : Data to be linked or head number of the devices where the data to be linked is stored (character string)

D : Head number of the devices where the linking result will be stored (character string)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word $

S1 –– –– ––

S2 –– –– ––

D –– –– –– ––

Function
(1) Links the character string data designated by S2 after the character string data designated
by S1 and stores the result into the area starting with the device number designated by D .
b15 b8 b7 b0 b15 b8 b7 b0 b15 b8 b7 b0
S1 46H (F) 48H (H) S2 35H (5) 31H (1) D 46H (F) 48H (H)
S1 +1 2DH ( ) 41H (A) S2 +1 39H (9) 33H (3) D +1 2DH ( ) 41H (A)
S1 +2 00H S2 +2 00H 41H (A) D +2 35H (5) 31H (1)
D +3 39H (9) 33H (3)
D +4 00H 41H (A)

(2) When character strings are linked, the "00H" which indicates the end of character string data
indicated by S1 , is ignored, and the character string indicated by S2 is appended to the last
character of the S1 string.

6-68
 $+(P)

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The entire character string linked from the device number designated by D to the final
2
device number of the relevant device cannot be stored. (Error code: 4101)

• The storage device numbers for the character strings designated by S1 and S2 overlap. 3
(Error code: 4101)

• The storage device numbers for the character strings designated by S2 and D overlap.
(Error code: 4101) 4
• The character string of S1 , S2 and D exceeds 16383 characters. (Error code: 4101)

4
Program Example
(1) The following program links the character string stored from D10 to D12 with the character 6
string "ABCD" when X0 is ON, and stores them in D100 onwards.
[Ladder Mode] [List Mode]
Step Instruction Device 7

8
[Operation]
b15 b8 b7 b0 b15 b8 b7 b0
D10 62 H (b) 61H (a) D100 62 H (b) 61H (a)
D11 64 H (d) 63 H (c) + "ABCD" D101 64 H (d) 63 H (c)

6.2.15 Linking character strings ($+(P))

6.2 Arithmetic Operation Instructions
D12 00H 65 H (e) D102 41H (A) 65 H (e)
D103 43H (C) 42H (B)
D104 00H 44H (D)

Automatically stores "00H".

6-69
 INC(P),DEC(P)

6.2.16 Incrementing and decrementing 16-bit BIN data

(INC(P),DEC(P))
INC(P),DEC(P)

Basic High
performance Process Redundant Universal LCPU

indicates an instruction symbol of INC/DEC.

Command
INC, DEC D

Command
INCP, DECP P D

D : Head number of devices for INC (+1)/DEC ( 1) operation (BIN 16 bits)

Setting Internal Devices J \

R, ZR U \G Zn Constants Other
Data Bit Word Bit Word

D ––

Function
INC

(1) Adds 1 to the device designated by D (16-bit data).

D D

b15 b0 b15 b0
5678 (BIN) 5679 (BIN)

(2) When INC/INCP operation is executed for the device designated by D , whose content is
32767, the value 32768 is stored at the device designated by D .
DEC

(1) Subtracts 1 from the device designated by D (16-bit data).

D D

b15 b0 b15 b0
5678 (BIN) 1 5677 (BIN)

(2) When DEC/DECP operation is executed for the device designated by D , whose content is
32768, the value 32767 is stored at the device designated by D .

Operation Error
(1) There are no operation errors associated with the INC(P)/DEC(P) instruction.

6-70
 INC(P),DEC(P)

Program Example
1
(1) The following program outputs the present value at the counter C0 to C20 to the area Y30 to
Y3F in BCD, every time X8 is turned ON. (When present value is less than 9999)
[Ladder Mode] 2
Outputs the present value of (0+Z1) to
Y30 to Y3F in BCD.
Executes Z1 + 1. 3
Sets Z1 at "0" when Z1=21 or X7
(reset input) is ON.
4

[List Mode] 6
Step Instruction Device

8
(2) The following is a down counter program.
[Ladder Mode]

Transfers 100 to D8 when X7 goes ON.

6.2.16 Incrementing and decrementing 16-bit BIN data (INC(P),DEC(P))

6.2 Arithmetic Operation Instructions
In the state M38=OFF, decrement at D8 (D8 - 1) is
executed when X8 goes from OFF to ON.
At D8=0, M38 goes ON.

[List Mode]
Step Instruction Device

6-71
 DINC(P),DDEC(P)

6.2.17 Incrementing and decrementing 32-bit BIN data

(DINC(P),DDEC(P))
DINC(P),DDEC(P)

Basic High
performance Process Redundant Universal LCPU

indicates an instruction symbol of DINC/DDEC.

Command
DINC, DDEC D

Command
DINCP, DDECP P D

D : Head number of devices for DINC(+1) or DDEC(-1) operation (BIN 32 bits)

Setting Internal Devices J \

R, ZR U \G Zn Constants Other
Data Bit Word Bit Word

D ––

Function
DINC

(1) Adds 1 to the device designated by D (32-bit data).

D +1 D D +1 D

b31 b16 b15 b0 b31 b16 b15 b0

73500 (BIN) 73501 (BIN)

(2) When DINC/DINCP operation is executed for the device designated by D , whose content is
2147483647, the value 2147483648 is stored at the device designated by D .
DDEC

(1) Subtracts 1 from the device designated by D (32-bit data).

D +1 D D +1 D

b31 b16 b15 b0 b31 b16 b15 b0

73500 (BIN) 1 73499 (BIN)

(2) When DDEC/DDECP operation is executed for the device designated by D , whose content
is 0, the value 1 is stored at the device designated by D .

Operation Error
(1) There are no operation errors associated with the DINC(P) or DDEC(P).

6-72
 DINC(P),DDEC(P)

Program Example
1
(1) The following program adds 1 to the data at D0 and D1 when X0 is ON.
[Ladder Mode] [List Mode]
2
Step Instruction Device

3
(2) The following program adds 1 to the data set at X10 to X27 when X0 goes ON, and stores
the result at D3 and D4. 4
[Ladder Mode] [List Mode]
Step Instruction Device
4

(3) The following program subtracts 1 from the data at D0 and D1 when X0 goes ON.
7
[Ladder Mode] [List Mode]
Step Instruction Device

(4) The following program subtracts 1 from the data set at X10 to X27 when X0 goes ON, and
stores the result at D3 and D4.

6.2.17 Incrementing and decrementing 32-bit BIN data (DINC(P),DDEC(P))

6.2 Arithmetic Operation Instructions
[Ladder Mode] [List Mode]
Step Instruction Device

6-73
 BCD(P),DBCD(P)

6.3 Data conversion instructions

6.3.1 Conversion from BIN data to 4-digit and 8-digit BCD
(BCD(P),DBCD(P))
BCD(P),DBCD(P)
BCD(P), DBCD(P)

Basic High
performance Process Redundant Universal LCPU

indicates an instruction symbol of BCD/DBCD.

Command
BCD, DBCD S D

Command
BCDP, DBCDP P S D

S : BIN data or head number of the devices where the BIN data is stored (BIN 16/32 bits)

D : Head number of the devices where BCD data will be stored (BCD 4/8 digits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S ––

D –– ––

Function
BCD
Converts BIN data (0 to 9999) at the device designated by S to BCD data, and stores it at the
device designated by D .
-32768 16384 8192 4096 2048 1024 512 256 128 64 32 16 8 4 2 1
S BIN 9999 0 0 1 0 0 1 1 1 0 0 0 0 1 1 1 1
Must always be "0". BCD conversion
8000 4000 2000 1000 800 400 200 100 80 40 20 10 8 4 2 1
D BCD 9999 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1

Thousands digits Hundreds digits Tens digits Ones digits

DBCD
Converts BIN data (0 to 99999999) at the device designated by S to BCD data, and stores it at
the device designated by D .
S +1 (Upper 16 bits) S (Lower 16 bits)
231
230
229
228
227
226
225
224
223
222
221
220
219
218
217
216
215
214
213
212
211
210
29
28
27
26
25
24
23
22
21
20

S BIN 99999999 0 0 0 0 0 1 0 1 1 1 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1

Must always be "0" (upper 5 digits). BCD conversion

107

106

105

104

103

102

101

100
1

1
8
4
2

8
4
2

8
4
2

8
4
2

8
4
2

8
4
2

8
4
2

8
4
2

D BCD 99999999 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1

Ten Millions Hundred Ten Thousands Hundreds Tens Ones

millions digits thousands thousands digits digits digits digits
digits digits digits

D +1 (Upper 4 digits) D (Lower 4 digits)

6-74
 BCD(P), DBCD(P)

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The data of S is other than 0 to 9999 at BCD instruction. (Error code: 4100)
2
• The data of S or S +1 is other than 0 to 99999999 at DBCD instruction.
(Error code: 4100) 3
Program Example
4
(1) The following program outputs the present value of C4 from Y20 to Y2F to the BCD display
device.
Programmable Controller Output Module
4
COM

Y2D
Y2C
Y2E

Y2B
Y2A
Y2F

Y29
Y28

Y27
Y26
Y25
Y24

Y23
Y22
Y21
Y20
6
8000
4000
2000
1000

1
800
400
200
100

80
40
20
10

2
8
4
Output
power supply 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0
7

7-segment display unit 8

[Ladder Mode] [List Mode]
Step Instruction Device

6.3.1 Conversion from BIN data to 4-digit and 8-digit BCD (BCD(P),DBCD(P))
6.3 Data conversion instructions
(2) The following program outputs 32-bit data from D0 to D1 to Y40 to Y67.
Programmable Controller Output Module

Y67 to Y64 Y63 to Y60 Y5F to Y5C Y5B to Y58 Y57 to Y54 Y53 to Y50 Y4F to Y4C Y4B to Y48 Y47 to Y44 Y43 to Y40
Output
power supply

7-segment display unit

[Ladder Mode] [List Mode]

Step Instruction Device

6-75
 BIN(P),DBIN(P)

6.3.2 Conversion from BCD 4-digit and 8-digit data to BIN data
(BIN(P),DBIN(P))
BIN(P),DBIN(P)

Basic High
performance Process Redundant Universal LCPU

indicates an instruction symbol of BIN/DBIN.

Command
BIN, DBIN S D

Command
BINP, DBINP P S D

S : BCD data or head number of the devices where the BCD data is stored (BCD 4/8 digits)

D : Head number of the devices where BIN data will be stored (BIN 16/32 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S ––

D –– ––

Function
BIN
Converts BCD data (0 to 9999) at device designated by S to BIN data, and stores at the device
designated by D .
8000 4000 2000 1000 800 400 200 100 80 40 20 10 8 4 2 1
S BCD 9999 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1

Thousands digits Hundreds digits Tens digits Ones digits

BIN conversion
32768 16384 8192 4096 2048 1024 512 256 128 64 32 16 8 4 2 1
D BIN 9999 0 0 1 0 0 1 1 1 0 0 0 0 1 1 1 1
Always filled with 0s.

DBIN
Converts BCD data (0 to 99999999) at device designated by S to BIN data, and stores at the
device designated by D .
S +1 S
107

106

105

104

103

102

101

100
1

1
8
4
2

8
4
2

8
4
2

8
4
2

8
4
2

8
4
2

8
4
2

8
4
2

S BCD 99999999 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1

Ten Millions Hundred Ten Thousands Hundreds Tens Ones

millions digits thousands thousands digits digits digits digits
digits digits digits
BIN conversion
D +1 D
231
230
229
228
227
226
225
224
223
222
221
220
219
218
217
216
215
214
213
212
211
210
29
28
27
26
25
24
23
22
21
20

D BIN 99999999 0 0 0 0 0 1 0 1 1 1 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1

Always filled with 0s.

6-76
 BIN(P),DBIN(P)

Operation Error
1
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• When values other than 0 to 9 are designated to any digits of S
2
(Error code: 4100)

The error above can be suppressed by turning ON SM722. 3

However, the instruction is not executed regardless of whether SM722 is turned ON or OFF
if the designated value is out of the available range.
For the BINP/DBINP instruction, the next operation will not be performed until the command
(execution condition) is turned from OFF to ON regardless of the presence/absence of an
4
error.

4
Program Example
(1) The following program converts the BCD data at X10 to X1B to BIN when X8 is ON, and stores it
at D8.
6
BCD digital switch

Can be used
7
COM

COM

COM
in other purposes.
1
80
40

2
400

20

4
800

200

10
100

Input
power supply
8
0
0

0
0

0
1
1

1
0

0
COM

X1D
X1C
X1E

X1B
X1A
X1F

X19
X18

X17
X16
X15
X14

X13
X12
X11
X10

Programmable Controller input module

[Ladder Mode] [List Mode]

6.3.2 Conversion from BCD 4-digit and 8-digit data to BIN data (BIN(P),DBIN(P))
6.3 Data conversion instructions
Step Instruction Device

6-77
 BIN(P),DBIN(P)

(2) The following program converts the BCD data at X10 to X37 to BIN when X8 is ON, and stores it
at D0 and D1.
(Addition of the BIN data converted from BCD at X20 to X37 and the BIN data converted
from BCD at X10 to X1F)
BCD digital switch

Input power supply

X37 to X34 X33 to X30 X2F to X2C X2B to X28 X27 to X24 X23 to X20 X1F to X1C X1B to X18 X17 to X14 X13 to X10

Programmable Controller Output Module

[Ladder Mode] [List Mode]

Step Instruction Device

If the data set at X10 to X37 is a BCD value which exceeds 2147483647, the value at D0
and D1 will be a negative value, because it exceeds the range of numerical values that can
be handled by a 32-bit device.

6-78
 FLT(P),DFLT(P)

6.3.3 Conversion from BIN 16 and 32-bit data to floating decimal

point (Single precision) (FLT(P),DFLT(P)) 1
FLT(P),DFLT(P)

Ver.
High
2
Basic performance Process Redundant Universal LCPU

Basic model QCPU: The upper five digits of the serial No. are "04122" or larger.
3
indicates an instruction symbol of FLT/DFLT.

Command
4
FLT, DFLT S D

FLTP, DFLTP
Command
P S D
4

S : Integer data to be converted to 32-bit floating decimal point data or head number of the devices where the
6
integer data is stored (BIN 16/32 bits)
D : Head number of the devices where the converted 32-bit floating decimal point data will be stored
(real number) 7
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S –– 8
D –– –– *1 –– ––

*1:Available only in multiple Universal model QCPU and LCPU

6.3.3 Conversion from BIN 16 and 32-bit data to floating decimal point (Single precision)
6.3 Data conversion instructions
Function

(FLT(P),DFLT(P))
FLT

(1) Converts 16-bit BIN data designated by S to 32-bit floating decimal point type real number,
and stores at device number designated by D .
S D +1 D
BIN 16 bits

32-bit floating-point
real number

(2) BIN values between 32768 to 32767 can be designated by S .

DFLT

(1) Converts 32-bit BIN data designated by S to 32-bit floating decimal point type real number,
and stores at device number designated by D .
S +1 S D +1 D
Upper 16 bits Lower 16 bits

BIN 32 bits 32-bit floating-point

real number

(2) BIN values between 2147483648 to 2147483647 can be designated by S +1 and S .

6-79
 FLT(P),DFLT(P)

(3) Due to the fact that 32-bit floating decimal point type real numbers are processed by simple
32-bit processing, the number of significant digits is 24 bits if the display is binary and
approximately 7 digits if the display is decimal.
For this reason, if the integer exceeds the range of 16777216 to 16777215 (24-bit BIN
value), errors can be generated in the conversion value.
As for the conversion result, the 25th bit from the upper bit of the integer is always filled with
1 and 26th bit and later bits are truncated.
Integer After conversion
b31 b24 b23 b16 b15 b8 b7 b0
222030030 0 0 0 0 1 1 0 1 0 0 1 1 1 0 1 1 1 1 1 0 1 0 0 0 1 1 0 0 1 1 1 0 Result of operation
is 222030032.
Truncation
Always filled with 1
b31 b24 b23 b16 b15 b8 b7 b0
372588919 0 0 0 1 0 1 1 0 0 0 1 1 0 1 0 1 0 1 0 0 0 0 0 1 0 1 1 1 0 1 1 1 Result of operation
is 372588928.
Truncation
Always filled with 1

Operation Error
(1) There are no errors associated with the FLT,DFLT instruction.

6-80
 FLT(P),DFLT(P)

Program Example
1
(1) The following program converts the BIN 16-bit data at D20 to a 32-bit floating decimal point
type real number and stores the result at D0 and D1.
[Ladder Mode] [List Mode] 2
Step Instruction Device

[Operation]
Integer
4
D20 conversion D1 D0
15923 15923
BIN value 32-bit floating-point
real number
4
(2) The following program converts the BIN 32-bit data at D20 and D21 to a 32-bit floating
decimal point type real number, and stores the result at D0 and D1. 6
[Ladder Mode] [List Mode]
Step Instruction Device
7

[Operation] 8
Integer
D21 D20 D1 D0
conversion
16543521 16543521
BIN value 32-bit floating-point
Integer real number
D21 D20
conversion An error is generated in operation results since

6.3.3 Conversion from BIN 16 and 32-bit data to floating decimal point (Single precision)
6.3 Data conversion instructions
173963112
the number of significant digits is "7".
BIN value D1 D0

(FLT(P),DFLT(P))
173963120
32-bit floating-point
real number

6-81
 FLTD(P),DFLTD(P)

6.3.4 Conversion from BIN 16 and 32-bit data to floating decimal

point (Double precision) (FLTD(P),DFLTD(P))
FLTD(P),DFLTD(P)

High
Basic performance Process Redundant Universal LCPU

indicates an instruction symbol of FLTD/DFLTD.

Command
FLTD, DFLTD S D

Command
FLTDP, DFLTDP P S D

S : Integer data to be converted to 64-bit floating decimal point data or head number of the devices where the
integer data is stored (BIN 16/32 bits)
D : Head number of the devices where the converted 64-bit floating decimal point data will be stored
(real number)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S –– –– ––

D –– –– –– ––

Function
FLTD

(1) Converts 16-bit BIN data designated by S to 64-bit floating decimal point type real number,
and stores at device number designated by D .
S D +3 D +2 D +1 D
BIN 16 bits

64-bit floating-point
real number

(2) BIN values between 32768 to 32767 can be designated by S .

DFLTD

(1) Converts 32-bit BIN data designated by S to 64-bit floating decimal point type real number,
and stores at device number designated by D .
S +1 S D +3 D +2 D +1 D
Upper 16 bits Lower 16 bits

BIN 32 bits 64-bit floating-point

real number

(2) BIN values between 2147483648 to 2147483647 can be designated by S +1 and S .

6-82
 FLTD(P),DFLTD(P)

Operation Error
1
(1) There are no errors associated with the FLTD,DFLTD instruction.

2
Program Example
(1) The following program converts the BIN 16-bit data at D20 to a 64-bit floating decimal point
type real number and stores the result at D0 to D3.
3
[Ladder Mode] [List Mode]
Step Instruction Device 4

4
[Operation]
D20 Conversion to real number D3 D2 D1 D0
15923 15923 6
BIN value 64-bit floating-point
real number

(2) The following program converts the BIN 32-bit data at D20 and D21 to a 64-bit floating
7
decimal point type real number, and stores the result at D0 to D3.
[Ladder Mode] [List Mode]
8
Step Instruction Device

6.3.4 Conversion from BIN 16 and 32-bit data to floating decimal point (Double precision)
6.3 Data conversion instructions
[Operation]

(FLTD(P),DFLTD(P))
D21 D20 Conversion to real number D3 D2 D1 D0
16543521 16543521
BIN value 64-bit floating-point
real number

6-83
 INT(P),DINT(P)

6.3.5 Conversion from floating decimal point data to BIN16- and

32-bit data (Single precision) (INT(P),DINT(P))
INT(P),DINT(P)

Ver.
High
Basic performance Process Redundant Universal LCPU

Basic model QCPU: The upper five digits of the serial No. are "04122" or larger.

indicates an instruction symbol of INT/DINT.

Command
INT, DINT S D

Command
INTP, DINTP P S D

S : 32-bit floating decimal point data to be converted to BIN value or head number of the devices where the
floating decimal point data is stored (real number)
D : Head number of the devices where the converted BIN value will be stored (BIN 16/32 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word E

S –– –– *1 ––

D –– ––

*1:Available only in multiple Universal model QCPU and LCPU

Function
INT
(1) Converts the 32-bit floating decimal point real number designated at S into BIN 16-bit data
and stores it at the device number designated at D .
S +1 S D
BIN16-bit

32-bit floating-point
real number

(2) The range of 32-bit floating decimal point type real numbers that can be designated at S +1
or S is from 32768 to 32767.

(3) Stores integer values stored at D as BIN 16-bit values.

(4) After conversion, the first digit after the decimal point of the real number is rounded off.
DINT
(1) Converts 32-bit floating decimal point type real number designated by S to BIN 32-bit data,
and stores the result at the device number designated by D .
S +1 S D +1 D
Upper 16 bits Lower 16 bits

32-bit floating-point BIN 32 bits

real number

(2) The range of 32-bit floating decimal point type real numbers that can be designated at S +1
or S is from 2147483648 to 2147483647.

6-84
 INT(P),DINT(P)

(3) The integer value stored at D +1 and D is stored as BIN 32 bits.

(4) After conversion, the first digit after the decimal point of the real number is rounded off. 1

Operation Error
2
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The contents of the designated device or the result of the addition are not "0", or not within 3
the following range(For the Universal model QCPU, LCPU):
0, 2-126 | Contents of designated device | < 2128 (Error code: 4140)
4
• The value of the specified device is 0, unnormalized number, nonnumeric, and ± .
(For the Universal model QCPU and LCPU) (Error code: 4140)

• The 32-bit floating decimal point type data designated by S when the INT instruction was 4
used was outside the 31768 to 32767 range. (Error code: 4100)

• The 32-bit floating decimal point type data designated by when the DINT instruction
S
6
was used was outside the 2147483648 to 2147483647 range. (Error code: 4100)

Program Example 7
(1) The following program converts the 32-bit floating decimal point type real number at D20
and D21 to BIN 16-bit data, and stores the result at D0.
8
[Ladder Mode] [List Mode]
Step Instruction Device

6.3.5 Conversion from floating decimal point data to BIN16- and 32-bit data (Single precision)
6.3 Data conversion instructions
[Operation]

(INT(P),DINT(P))
D21 D20 Integer D0
conversion
25915.6796 25916
32-bit floating-point BIN value
real number
D21 D20 Integer
conversion
-33562.3211 An operation error occurs
since "setting data < -32768."
32-bit floating-point
real number

6-85
 INT(P),DINT(P)

(2) The following program converts the 32-bit floating decimal point type real number at D20
and D21 to BIN 32-bit data and stores the result at D0 and D1.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
Integer
D21 D20 conversion D1 D0
-574968.321 -574968
32-bit floating-point BIN value
real number
Integer
D21 D20 conversion
2147483649.22 An operation error occurs
since "setting data > 2147483647."
32-bit floating-point
real number

6-86
 INTD(P),DINTD(P)

6.3.6 Conversion from floating decimal point data to BIN16- and

32-bit data (Double precision) (INTD(P),DINTD(P)) 1
INTD(P),DINTD(P)

High
2
Basic performance Process Redundant Universal LCPU

3
indicates an instruction symbol of INTD/DINTD.

Command 4
INTD, DINTD S D

INTDP, DINTDP
Command
P S D 4

S : 64-bit floating decimal point data to be converted to BIN value or head number of the devices where the 6
floating decimal point data is stored (real number)
D : Head number of the devices where the converted BIN value will be stored (BIN 16/32 bits)

Setting Internal Devices

R, ZR
J \
Zn
Constants
Other
7
U \G
Data Bit Word Bit Word E

S –– –– –– ––

D –– –– –– –– 8

Function

6.3.6 Conversion from floating decimal point data to BIN16- and 32-bit data (Double precision)
6.3 Data conversion instructions
INTD

(INTD(P),DINTD(P))
(1) Converts the 64-bit floating decimal point real number designated at S into BIN 16-bit data
and stores it at the device number designated at D .
S +3 S +2 S +1 S D
BIN 16 bit

64-bit floating-point
real number

(2) The range of 64-bit floating decimal point type real numbers that can be designated at
S +3, S +2, S +1 or S is from 32768 to 32767.

(3) Stores integer values stored at D as BIN 16-bit values.

(4) The converted data is the value rounded 64-bit floating-point real number to the first digit
after the decimal point.
DINTD
(1) Converts 64-bit floating decimal point type real number designated by S to BIN 32-bit data,
and stores the result at the device number designated by D .
S +3 S +2 S +1 S D +1 D
Upper 16 bits Lower 16 bits

64-bit floating-point BIN 32 bit

real number

6-87
 INTD(P),DINTD(P)

(2) The range of 64-bit floating decimal point type real numbers that can be designated at
S +3, S +2, S +1 or S is from 2147483648 to 2147483647.

(3) The integer value stored at D +1 and D is stored as BIN 32 bits.

(4) The converted data is the value rounded 64-bit floating-point real number to the first digit
after the decimal point.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The value of the specified device is not in the following range: (Error code: 4140)
0, 2-1022 | value of specified device | 21024
• The value of the designated device is 0. (Error code: 4140)

• The 64-bit floating decimal point type data designated by S when the INTD instruction
was used was outside the 31768 to 32767 range. (Error code: 4100)

• The 64-bit floating decimal point type data designated by S when the DINTD instruction
was used was outside the 2147483648 to 2147483647 range. (Error code: 4100)

Program Example
(1) The following program converts the 64-bit floating decimal point type real number at D20 to
D23 with BIN 16-bit data, and stores the result at D0.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
D23 D22 D21 D20 Conversion to integer D0
25915.6796 25916
64-bit floating-point real number BIN value
D23 D22 D21 D20 Conversion to integer
33562.3211 An operation erroe occurs because the specified data is larger than -32768.
64-bit floating-point real number

(2) The following program converts the 64-bit floating decimal point type real number at D20 to
D23 with BIN 32-bit data and stores the result at D0 and D1.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
D23 D22 D21 D20 Conversion to integer D1 D0
574968.321 574968
64-bit floating-point real number BIN value
D23 D22 D21 D20 Conversion to integer
2147483649.22 An operation erroe occurs because the
64-bit floating-point real number specified data is larger than 2147483647.

6-88
 DBL(P)

6.3.7 Conversion from BIN 16-bit to BIN 32-bit data (DBL(P))

DBL(P)
1
Basic High
performance Process Redundant Universal LCPU
2

3
Command
DBL DBL S D

Command 4
DBLP DBLP S D

4
S : BIN 16-bit data or head number of the devices where the BIN 16-bit data is stored (BIN 16 bits)

D : Head number of the devices where the converted BIN 32-bit data will be stored (BIN 32 bits)

Setting Internal Devices

R, ZR
J \
Zn
Constants
Other
6
U \G
Data Bit Word Bit Word K, H

S ––

D –– ––
7

8
Function
Converts BIN 16-bit data at device designated by S to BIN 32-bit data with sign, and stores the
result at a device designated by D .

6.3.7 Conversion from BIN 16-bit to BIN 32-bit data (DBL(P))

6.3 Data conversion instructions
S D +1 D
BIN 16-bit data Upper 16 bits Lower 16 bits

BIN 32-bit data

Operation Error
(1) There are no errors associated with the DBL(P) instruction.

Program Example
(1) The following program converts the BIN 16-bit data stored at D100 to BIN 32-bit data when
X20 is ON, and stores at R100 and R101.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
D100 R101 R100
FB2EH FFFFFB2EH
( 1234) ( 1234)

6-89
 WORD(P)

6.3.8 Conversion from BIN 32-bit to BIN 16-bit data (WORD(P))

WORD(P)

Basic High
performance Process Redundant Universal LCPU

Command
WORD WORD S D

Command
WORDP WORDP S D

S : BIN 32-bit data or head number of the devices where the BIN 32-bit data is stored (BIN 32 bits)

D : Head number of the devices where the converted BIN 16-bit data will be stored (BIN 16 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S ––

D –– ––

Function
Converts BIN 32-bit data at device designated by S to BIN 16-bit data with sign, and stores the
result at a device designated by D .
Devices can be designated in the range from -32768 to 32767.
S +1 S D
Upper 16 bits Lower 16 bits BIN 16-bit data

BIN 32-bit data

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• The contents of the data designated by S +1 and S are outside the range of 32768 to
32767. (Error code: 4100)

Program Example
(1) The following program converts the BIN 32-bit data at R100 and R101 to BIN 16-bit data
when X20 is ON, and stores it at D100.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
R101 R100 D100
FFFF8253 H 8253H
(-32173) (-32173)

6-90
 GRY(P),DGRY(P)

6.3.9 Conversion from BIN 16 and 32-bit data to Gray code

(GRY(P),DGRY(P)) 1
GRY(P),DGRY(P)

Basic High
performance Process Redundant Universal LCPU
2

3
indicates an instruction symbol of GRY, DGRY.

Command 4
GRY, DGRY S D

Command
GRYP, DGRYP P S D 4

S : BIN data or head number of the devices where the BIN data is stored (BIN 16/32 bits) 6
D : Head number of the devices where the converted Gray code will be stored (BIN 16/32 bits)

Setting Internal Devices J \ Constants

Data Bit Word
R, ZR
Bit Word
U \G Zn
K, H
Other
7
S ––

8
D –– ––

Function

6.3.9 Conversion from BIN 16 and 32-bit data to Gray code (GRY(P),DGRY(P))
6.3 Data conversion instructions
GRY
Converts BIN 16-bit data at the device designated by S to Gray code, and stores result at
device designated by D .
16 bits
b15 b0
S BIN 1234 0 0 0 0 0 1 0 0 1 1 0 1 0 0 1 0

b15 b0
D Gray code 1234 0 0 0 0 0 1 1 0 1 0 1 1 1 0 1 1

DGRY
Converts BIN 32-bit data at the device designated by S to Gray code, and stores result at
device designated by D .
S +1 (Upper 16 bits) S (Lower 16 bits)

b31 b16 b15 b0

S BIN 305419896 000 100 1000 110 1000 10 10 1100 1111000

D +1 D

b31 b16 b15 b0

D Gray code 305419896 0 0 0 1 1 0 1 1 0 0 1 0 1 1 1 0 0 1 1 1 1 1 0 1 0 1 0 0 0 1 0 0

6-91
 GRY(P),DGRY(P)

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• The data at S is a negative number. (Error code: 4100)

Program Example
(1) The following program converts the BIN data at D100 to Gray code when X10 is ON, and
stores result at D200.
[Ladder Mode] [List Mode]
Step Instruction Device

(2) The following program converts the BIN data at D10 and D11 to Gray code when X1C is ON,
and stores it at D100 and D101.
[Ladder Mode] [List Mode]
Step Instruction Device

6-92
 GBIN(P),DGBIN(P)

6.3.10 Conversion of Gray code to BIN 16 and 32-bit data

(GBIN(P),DGBIN(P)) 1
GBIN(P),DGBIN(P)

Basic High
performance Process Redundant Universal LCPU
2

3
indicates an instruction symbol of GBIN/DGBIN.

Command 4
GBIN, DGBIN S D

Command
GBINP, DGBINP P S D 4

S : Gray code data or head number of the devices where the Gray code data is stored (BIN 16/32 bits) 6
D : Head number of the devices where the converted BIN data will be stored (BIN 16/32 bits)

Setting Internal Devices Constants

Data Bit Word
R, ZR
Bit
J \
Word
U \G Zn
K, H
Other 7
S ––

D –– ––
8

Function

6.3.10 Conversion of Gray code to BIN 16 and 32-bit data (GBIN(P),DGBIN(P))

6.3 Data conversion instructions
GBIN
Converts Gray code data at device designated by S to BIN 16-bit data and stores at device
designated by D .

16 bit
b15 b0
S Gray code 1234 0 0 0 0 0 1 1 0 1 0 1 1 1 0 1 1

b15 b0
D BIN 1234 0 0 0 0 0 1 0 0 1 1 0 1 0 0 1 0

DGBIN
Converts Gray code data at device designated by S to BIN 32-bit data and stores at device
designated by D .
S +1 (Upper 16 bits) S (Lower 16 bits)

b31 b16 b15 b0

S Gray code 305419896 0 0 0 1 1 0 1 1 0 0 1 0 1 1 1 0 0 1 1 1 1 1 0 1 0 1 0 0 0 1 0 0

D +1 D

b31 b16 b15 b0

D BIN 305419896 00010010001101000101011001111000

6-93
 GBIN(P),DGBIN(P)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• Data at S when the GBIN instruction was issued is outside the 0 to 32767 range.
(Error code: 4100)

• Data at S when the DGBIN instruction was issued is outside the 0 to 2147483647 range.
(Error code: 4100)

Program Example
(1) The following program converts the Gray code data at D100 when X10 is ON to BIN data,
and stores the result at D200.
[Ladder Mode] [List Mode]
Step Instruction Device

(2) The following program converts the Gray code data at D10 and D11 to BIN data when X1C
is ON, and stores the result at D0 and D1.
[Ladder Mode] [List Mode]
Step Instruction Device

6-94
 NEG(P),DNEG(P)

6.3.11 Complement of 2 of BIN 16- and 32-bit data (sign reversal)

(NEG(P),DNEG(P)) 1
NEG(P),DNEG(P)

Basic High
performance Process Redundant Universal LCPU
2

3
indicates an instruction symbol of NEG/DNEG.

Command 4
NEG, DNEG D

Command
NEGP, DNEGP P D 4

D : Head number of the devices where the data for which complement of 2 is performed is stored 6
(BIN 16/32 bits)

Setting Internal Devices J \

R, ZR Zn Constants Other
Data Bit Word Bit Word
U \G
7
D ––

8
Function
NEG

6.3.11 Complement of 2 of BIN 16- and 32-bit data (sign reversal) (NEG(P),DNEG(P))
6.3 Data conversion instructions
(1) Reverses the sign of the 16-bit device designated by D and stores at the device designated
by D .
16 bit
b15 b0
Before execution D 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 -21846

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Sign conversion
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

b15 b0
After execution D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 21846

(2) Used when reversing positive and negative signs.

6-95
 NEG(P),DNEG(P)

DNEG

(1) Reverses the sign of the 32-bit device designated by D and stores at the device designated
by D .
32 bit
Before b31 b0
execution D 1 1 1 1 1 1 1 0 1 0 0 1 0 0 -218460

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Sign
conversion - 1 1 1 1 1 1 1 0 1 0 0 1 0 0

After b31 b0
execution D 0 0 0 0 0 0 0 1 0 1 1 1 0 0 218460

(2) Used when reversing positive and negative signs.

Operation Error
(1) There are no operation errors associated with the NEG(P) or DNEG(P) instruction.

Program Example
(1) The following program calculates a total for the data at D10 through D20 when XA goes ON,
and seeks an absolute value if the result is negative.
[Ladder Mode]

M3 is turned ON if D10 < D20.

Executes "D10 - D20".

Calculates the absolute value

(complement of 2) when M3 is ON.

[List Mode]
Step Instruction Device

6-96
 ENEG(P)

6.3.12 Floating-point sign invertion (Single precision) (ENEG(P))

ENEG(P)
1
Ver.
High
Basic
2
performance Process Redundant Universal LCPU

Basic model QCPU: The upper five digits of the serial No. are "04122" or larger.

3
Command
ENEG ENEG D

Command 4
ENEGP ENEGP D

4
D : Head number of the devices where the 32-bit floating decimal point data whose sign is to be reversed is
stored (real number)

Setting
Data
Internal Devices
R, ZR
J \
U \G Zn Constants Other 6
Bit Word Bit Word

D –– –– *1 ––

*1:Available only in multiple Universal model QCPU and LCPU

7

Function 8
(1) Reverses the sign of the 32-bit floating decimal point type real number data designated by
D , and stores at the device designated by D .

(2) Used when reversing positive and negative signs.

6.3.12 Floating-point sign invertion (Single precision) (ENEG(P))

6.3 Data conversion instructions
Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The contents of the designated device or the result of the addition are not "0", or not within
the following range(For the Universal model QCPU, LCPU):
0, 2-126 | Contents of designated device | < 2128 (Error code: 4140)
• The value of the specified device is 0, unnormalized number, nonnumeric, and ± .
(For the Universal model QCPU, LCPU) (Error code: 4140)

Program Example
(1) The following program inverts the sign of the 32-bit floating decimal point type real number
data at D100 and D101 when X20 goes ON, and stores result at D100 and D101.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
D101 D100 D101 D100
1.2345 1.2345

6-97
 EDNEG(P)

6.3.13 Floating-point sign invertion (Double precision)

(EDNEG(P))
EDNEG(P)

High
Basic performance Process Redundant Universal LCPU

Command
EDNEG EDNEG D

Command
EDNEGP EDNEGP D

D : Head number of the devices where the 64-bit floating decimal point data whose sign is to be reversed is
stored (real number)

Setting Internal Devices J \

R, ZR U \G Zn Constants Other
Data Bit Word Bit Word

D –– ––

Function
(1) Reverses the sign of the 64-bit floating decimal point type real number data designated by
D , and stores at the device designated by D .
(2) Used when reversing positive and negative signs.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The value of the specified device is not in the following range: (Error code: 4140)
-1022 1024
0, 2 | value of specified device | < 2
• The value of the designated device is 0. (Error code: 4140)

Program Example
(1) The following program inverts the sign of the 64-bit floating decimal point type real number
data at D0 to D3 when X20 goes ON, and stores result at D0 to D3.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
D3 D2 D1 D0 D3 D2 D1 D0
1.2345

6-98
 BKBCD(P)

6.3.14 Conversion from block BIN 16-bit data to BCD 4-digit data
(BKBCD(P)) 1
BKBCD(P)

Basic High
performance Process Redundant Universal LCPU
2

3
Command
BKBCD BKBCD S D n
4
Command
BKBCDP BKBCDP S D n

4
S : Head number of the devices where BIN data is stored (BIN 16 bits)

D : Head number of the devices where the converted BCD data will be stored (BCD 4 digits) 6
n : Number of variable data blocks (BIN 16 bits)

Setting Internal Devices J \ Constants

Data Bit Word
R, ZR
Bit Word
U \G Zn
K, H
Other
7
S –– –– ––

D –– –– ––

n ––
8

Function

6.3.14 Conversion from block BIN 16-bit data to BCD 4-digit data (BKBCD(P))
6.3 Data conversion instructions
(1) Converts BIN data (0 to 9999) n points from device designated by S to BCD, and stores
result following the device designated by D .
Must always be "0".
8192
4096
2048
1024
512
256
128
64
32
16
8
4
2
1

S BIN 1234 00000 100110 10010

S +1 BIN 5678 000 10 11000 10 1110
S +2 BIN 1545 0000011000001001
n

S +(n 2) BIN 4321 000 10000 1110000 1

S +(n 1) BIN 5555 000 10 101101100 11

BCD conversion
8000
4000
2000
1000
800
400
200
100
80
40
20
10
8
4
2
1

D BCD 1234 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0
D +1 BCD 5678 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0
D +2 BCD 1545 0 0 0 1 0 1 0 1 0 1 0 0 0 1 0 1
n

D +(n 2) BCD 4321 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1

D +(n 1) BCD 5555 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

6-99
 BKBCD(P)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The range of the device n points from a device designated by S , D or exceeds the
relevant device. (Error code: 4101)

• The data n points from the device designated by S is outside the 0 to 9999 range.
(Error code: 4100)

• The S and D devices overlap. (Error code: 4101)

Program Example
(1) The following program converts, when X20 is turned ON, the BIN data stored at D100 to
D102 to BCD and stores the operation result into the area starting from D200.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
8192
4096
2048
1024
512
256
128
64
32
16
8
4
2
1

D100 BIN 5432 000 10 10 100 111000

D101 BIN 4444 000 1000 10 10 11100
D102 BIN 3210 0000110010001010

BCD D0 3
conversion
8000
4000
2000
1000
800
400
200
100
80
40
20
10
8
4
2
1

D200 BCD 5432 0 1 0 1 0 1 0 0 0 0 1 1 0 0 1 0

D201 BCD 4444 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
D202 BCD 3210 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0

6-100
 BKBIN(P)

6.3.15 Conversion from block BCD 4-digit data to block BIN 16-bit
data (BKBIN(P)) 1
BKBIN(P)

Basic High
performance Process Redundant Universal LCPU
2

3
Command
BKBIN BKBIN S D n
4
Command
BKBINP BKBINP S D n

4
S : Head number of the devices where BCD data is stored (BCD 4 digits)

D : Head number of the devices where the converted BIN data will be stored (BIN 16 bits)
n : Number of variable data blocks (BIN 16 bits)
6
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data K, H
Bit Word Bit Word
7
S –– –– ––

D –– –– ––

n –– 8

Function

6.3.15 Conversion from block BCD 4-digit data to block BIN 16-bit data (BKBIN(P))
6.3 Data conversion instructions
(1) Converts BCD data (0 to 9999) n points from device designated by S to BIN, and stores
result following the device designated by D .
8000
4000
2000
1000
800
400
200
100
80
40
20
10
8
4
2
1

D BCD 1234 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0
D +1 BCD 5678 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0
D +2 BCD 1545 0 0 0 1 0 1 0 1 0 1 0 0 0 1 0 1
n

D +(n 2) BCD 4321 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1

D +(n 1) BCD 5555 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

BIN conversion
8192
4096
2048
1024
512
256
128
64
32
16
8
4
2
1

S BIN 1234 00000100110 100 10

S +1 BIN 5678 000 10 11000 10 1110
S +2 BIN 1545 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 1
n

S +(n 2) BIN 4321 0 0 0 1 0 0 0 0 1 1 1 0 0 0 0 1

S +(n 1) BIN 5555 0 0 0 1 0 1 0 1 1 0 1 1 0 0 1 1

6-101
 BKBIN(P)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The n-bit range from the S , D , or device exceeds the range of that device.
(Error code: 4101)

• The data n points at the S device is outside the 0 to 9999 range.

(Error code: 4100)

• The S and D devices overlap. (Error code: 4101)

Program Example
(1) The following program converts, when X20 is turned ON, the BCD data stored at D100 to
D102 to BIN and stores the operation result into the area starting from D200.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
8000
4000
2000
1000
800
400
200
100
80
40
20
10
8
4
2
1

D100 BCD 8080 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0

D101 BCD 7654 0 0 1 1 1 0 1 1 0 0 1 0 1 0 1 0
D102 BCD 9999 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1

BIN conversion
(when D0=3)
8192
4096
2048
1024
512
256
128
64
32
16
8
4
2
1

D200 BIN 8080 00 01111110010000

D201 BIN 7654 00 0111 011110 0110
D202 BIN 9999 0 010 0111000 01111

6-102
 ECON(P)

6.3.16 Single precision to Double precision conversion

(ECON(P)) 1
ECON(P)

High
2
Basic performance Process Redundant Universal LCPU

3
Command
ECON ECON S D 4
Command
ECONP ECONP S D
4
S : Conversion source data, or head number of the device where conversion source data is stored
(Real number (single precision))
D : Head number of the device where the converted data is stored (Real number (double precision)) 6
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word E

S –– –– –– 7
D –– –– –– ––

8
Function
Converts 32-bit floating-point real number specified for S into 64-bit floating-point real

6.3.16 Single precision to Double precision conversion (ECON(P))

6.3 Data conversion instructions
number, and stores the conversion result to the device specified for D .
S +1 S D +3 D +2 D +1 D

32-bit floating-point real number 64-bit floating-point real number

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The value of the specified device is not in the following range: (Error code: 4140)
-126 128
0,2 | value of specified device | 2
• The value of the specified device is 0, unnormalized number, nonnumeric, and ± .
(Error code: 4140)

6-103
 ECON(P)

Program Example
(1) The program which converts 32-bit floating-point real number of the devices, D10 to D11,
into 64-bit floating-point real number when X0 turns ON, and outputs the conversion result to
the devices, D0 to D3.
[Ladder Mode] [List Mode]
Step Instruction Device

6-104
 EDCON(P)

6.3.17 Double precision to Single precision conversion

(EDCON(P)) 1
EDCON(P)

High
2
Basic performance Process Redundant Universal LCPU

3
Command
EDCON EDCON S D 4
Command
EDCONP EDCONP S D
4
S : Conversion source data, or head number of the device where conversion source data is stored
(Real number (double precision))
D : Head number of the device where the converted data is stored (Real number (single precision)) 6
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word E

S –– –– –– ––
7
D –– –– –– ––

8
Function
Converts 64-bit floating-point real number specified for S into 32-bit floating-point real

6.3.17 Double precision to Single precision conversion (EDCON(P))

6.3 Data conversion instructions
number, and stores the conversion result to the device specified for D .
S +3 S +2 S +1 S D +1 D

64-bit floating-point real number 32-bit floating-point real number

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The value of the specified device is not in the following range: (Error code: 4140)
0,2-1022 | value of specified device | 21024
• The value of the designated device is 0. (Error code: 4140)
• The result exceeds the following range (Conversion results in an overflow):
2128 | Conversion result | (Error code: 4141)

6-105
 EDCON(P)

Program Example
(1) The program which converts 64-bit floating-point real number of the devices, D10 to D13,
into 32-bit floating-point real number when X0 turns ON, and outputs the conversion result to
the devices, D0 to D1.
[Ladder Mode] [List Mode]
Step Instruction Device

6-106
 MOV(P),DMOV(P)

6.4 Data Transfer Instructions

1
6.4.1 16-bit and 32-bit data transfers (MOV(P),DMOV(P))
MOV(P),DMOV(P)
2
Basic High
Process Redundant Universal LCPU
3
performance

4
indicates an instruction symbol of MOV/DMOV.

Command
MOV, DMOV S D 4
Command
MOVP, DMOVP P S D
6
S : Data to be transferred or the number of the device where the data to be transferred is stored (BIN 16/32 bits)

D : Number of the device where the data will be transferred (BIN 16/32 bits) 7
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S –– 8
D –– ––

Function

6.4.1 16-bit and 32-bit data transfers (MOV(P),DMOV(P))

6.4 Data Transfer Instructions
MOV

(1) Transfers the 16-bit data from the device designated by S to the device designated by D .
b15 b0
Before transfer S 1 0 1 1 0 1 0 0 0 1 1 1 0 0 1 0

Transfer
b15 b0
After transfer D 1 0 1 1 0 1 0 0 0 1 1 1 0 0 1 0

DMOV

(1) Transfers 32-bit data at the device designated by S to the device designated by D .
S +1 S
b15 b0 b15 b0
Before transfer S 1 0 1 1 0 1 0 0 0 1 1 1 0 0 1 0

Transfer
D +1 D
b15 b0 b15 b0
After transfer D 1 0 1 1 0 1 0 0 0 1 1 1 0 0 1 0

Operation Error
(1) There are no operation errors associated with the MOV(P) or DMOV(P) instruction.

6-107
 MOV(P),DMOV(P)

Program Example
(1) The following program stores input data from X0 to XB at D8.
[Ladder Mode] [List Mode]
Step Instruction Device

(2) The following program stores the constant K155 at D8 when X8 goes ON.
[Ladder Mode] [List Mode]
Step Instruction Device

009BH
b15 b8b7 b0
D8 0 0 0 0 0 0 0 0 1 0 0 1 1 0 1 1

(3) The following program stores the data from D0 and D1 at D7 and D8.
[Ladder Mode] [List Mode]
Step Instruction Device

(4) The following program stores the data from X0 to X1F at D0 and D1.
[Ladder Mode] [List Mode]
Step Instruction Device

6-108
 EMOV(P)

6.4.2 Floating-point data transfer (Single precision) (EMOV(P))

EMOV(P)
1
Ver.
High
Basic
2
performance Process Redundant Universal LCPU

Basic model QCPU: The upper five digits of the serial No. are "04122" or larger.

3
Command
EMOV EMOV S D

Command 4
EMOVP EMOVP S D

S : Data to be transferred or number of the device to which the data to be transferred is stored (real number)
4
D : The number of the device to which the transferred data will be stored (real number)

Setting
Data
Internal Devices
R, ZR
J \
U \G Zn
Constants
E
Other 6
Bit Word Bit Word

S –– –– *1 ––

D –– –– *1 –– –– 7
*1:Available only in multiple Universal model QCPU, LCPU

8
Function
Transfers 32-bit floating decimal point type real number data being stored at the device
designated by to a device designated by .

6.4.2 Floating-point data transfer (Single precision) (EMOV(P))

6.4 Data Transfer Instructions
S D
S

S +1 S D +1 D
Transfer
4.23542 4.23542

32-bit floating-point 32-bit floating-point

real number real number

Operation Error
(1) There are no operation errors associated with the EMOV(P) instruction.

6-109
 EMOV(P)

Program Example
(1) The following program stores the real numbers at D10 and D11 at D0 and D1.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
D11 D10 D1 D0
36.475 36.475

(2) The following program stores the real number 1.23 at D10 and D11 when X8 is ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
D11 D10
1.23 1.23

6-110
 EDMOV(P)

6.4.3 Floating-point data transfer (Double precision) (EDMOV(P))

EDMOV(P)
1
High
2
Basic performance Process Redundant Universal LCPU

Command
3
EDMOV EDMOV S D

Command 4
EDMOVP EDMOVP S D

S : Data to be transferred or number of the device to which the data to be transferred is stored (real number) 4
D : The number of the device to which the transferred data will be stored (real number)

Setting
Data
Internal Devices
Bit Word
R, ZR
Bit
J \
Word
U \G Zn
Constants
E
Other 6
S –– –– ––

D –– –– –– ––
7

Function 8
Transfers 64-bit floating decimal point type real number data being stored at the device
designated by S to a device designated by D
S .

6.4.3 Floating-point data transfer (Double precision) (EDMOV(P))

6.4 Data Transfer Instructions
S +3 S +2 S +1 S Transfer D +3 D +2 D +1 D
4.23542 4.23542

64-bit floating-point real number 64-bit floating-point real number

Operation Error
(1) There are no operation errors associated with the EDMOV(P) instruction.

6-111
 EDMOV(P)

Program Example
(1) The following program stores the 64-bit floating decimal point type real number at D10 to
D13 at D0 to D3.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
D13 D12 D11 D10 D3 D2 D1 D0
36.475 36.475

(2) The following program stores the real number 1.23 at D10 to D13 when X8 is ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
D13 D12 D11 D10

6-112
 $MOV(P)

6.4.4 Character string transfers ($MOV(P))

$MOV(P)
1
Basic High
performance Process Redundant Universal LCPU
2

3
Command
$MOV $MOV S D

Command 4
$MOVP $MOVP S D

S : Character string to be transferred (maximum string length: 32 characters) or head number of the devices
4
where the character string to be transferred is stored
(character string)
D : Head number of the devices where the transferred character string will be stored (character string) 6
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word $

S –– –– –– 7
D –– –– –– ––

8
Function
(1) Transfers the character string data designated by S to the devices from the device

6.4.4 Character string transfers ($MOV(P))

6.4 Data Transfer Instructions
designated by D and onward.
The character string data enclosed in " (double quotes) or devices from the number
specified by S to the device number storing "00H" are transferred all at once.
b15 b8 b7 b0 b15 b8 b7 b0
S 2nd character 1st character D 2nd character 1st character
S + 1 4th character 3rd character D + 1 4th character 3rd character
S + 2 6th character 5th character D + 2 6th character 5th character

00H nth character 00H nth character

Indicates the end of character string.

(2) Processing will be performed without error even in cases where the range for the devices
storing the character data to be transferred ( S to S +n) overlaps with the range of the
devices which will store the character string data after it has been transferred ( D to D +n).
The following occurs when the character string data that had been stored from D10 to D13 is
transferred to D11 to D14:
b15 b8 b7 b0 b15 b8 b7 b0
D10 32 H (2) 31 H (1) D10 32 H (2) 31 H (1) Character string before
D11 34 H (4) 33 H (3) D11 32 H (2) 31 H (1) transfer is remained.
D12 36 H (6) 35 H (5) D12 34 H (4) 33 H (3)
D13 00 H D13 36 H (6) 35 H (5)
D14 D14 00 H

6-113
 $MOV(P)

(3) If the "00H" code is being stored at lower bytes of S +n, "00H" will be stored at both the
higher bytes and the lower bytes of D +n.
b15 b8 b7 b0 b15 b8 b7 b0
S 42 H (B) 41 H (A) D 42 H (B) 41 H (A)
S +1 44 H (D) 43 H (C) D +1 44 H (D) 43 H (C)
S +2 45 H (E) 00 H D +2 00 H 00 H

Upper byte is not transferred. At the upper byte position,

"00H" is automatically stored.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• There is no "00H" code stored between the device number designated by S and the
relevant device. (Error code: 4101)

• The entire character string linked from the device number designated by D to the final
device number of the relevant device cannot be stored. (Error code: 4101)

• The character string of S exceeds 16383 characters. (Error code: 4101)

Program Example
(1) The character string data stored in D10 to D12 is transferred to D20 to D22 when X0 goes
ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
b15 b8 b7 b0 b15 b8 b7 b0
D10 4DH (M) 2AH ( * ) D20 4DH (M) 2AH ( * )
D11 45H (E) 45H (E) D21 45H (E) 45H (E)
D12 00H D22 00H

(2) When X0 is turned ON, the character string "ABCD" is transferred to D20 and D21.
[Ladder Mode] [List Mode]
Step Instruction Device

6-114
 CML(P),DCML(P)

6.4.5 16-bit and 32-bit negation transfers (CML(P),DCML(P))

CML(P),DCML(P)
1
Basic High
performance Process Redundant Universal LCPU
2

3
indicates an instruction symbol of CML, DCML.

Command
CML, DCML S D 4
Command
CMLP, DCMLP P S D
4
S : Data to be reversed or the number of the device where data to be reversed is stored (BIN 16/32 bits)

D : Number of the device where the reversing result will be stored (BIN 16/32 bits) 6
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S –– 7
D –– ––

8
Function
CML

6.4.5 16-bit and 32-bit negation transfers (CML(P),DCML(P))

6.4 Data Transfer Instructions
(1) Inverts 16-bit data designated by S bit by bit, and transfers the result to the device
designated by D .
b15 b0
Before execution S 1 0 1 1 0 1 0 0 0 1 1 1 0 0 1 0

Inversion
b15 b0
After execution D 0 1 0 0 1 0 1 1 1 0 0 0 1 1 0 1

DCML

(1) Inverts 32-bit data designated by S bit by bit, and transfers the result to the device
designated by D .
S +1 S
b15 b0 b15 b0
Before execution S 1 0 1 1 0 1 0 0 0 1 1 1 0 0 1 0

D +1 Inversion D
b15 b0 b15 b0
After execution D 0 1 0 0 1 0 1 1 1 0 0 0 1 1 0 1

Operation Error
(1) There are no operation errors associated with the CML(P) or DCML(P) instruction.

6-115
 CML(P),DCML(P)

Program Example
(1) The following program inverts the data from X0 to X7, and transfers result to D0.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
If "Number of bits of S < Number of bits of D "

X7 X0
These bits are all regarded as 0. 11010000

b15 b8 b7 b0
D0 1 1 1 1 1 1 1 1 0 0 1 0 1 1 1 1

(2) The following program inverts the data at M16 to M23, and transfers the result to Y40 to
Y47.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
If "Number of bits of S < Number of bits of D "

M23 M16
These bits are all regarded as 0. 01011100

Y4B Y48Y47 Y40

111110100011

(3) The following program inverts the data at D0 when X3 is ON, and stores the result at D16.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
b15 b8 b7 b0
D0 1101100110101111

b15 b8 b7 b0
D16 0 0 1 0 0 1 1 0 0 1 0 1 0 0 0 0

6-116
 CML(P),DCML(P)

(4) The following program inverts the data at X0 to X1F, and transfers results to D0 and D1.
[Ladder Mode] [List Mode]
1
Step Instruction Device

2
[Operation]
If "Number of bits of S < Number of bits of D " 3
X1B X8 X7 X0
These bits are all regarded as 0. 0100 011100101100
4
b31 b28 b27 b24 b8 b7 b0

D0, 1 1 1 1 1 1 0 1 1 100011010011
4
(5) The following program inverts the data at M16 to M35, and transfers it to Y40 to Y63.
[Ladder Mode] [List Mode] 6
Step Instruction Device

7
[Operation]
If "Number of bits of S < Number of bits of D "
8
M35 M24 M23 M16
These bits are all regarded as 0. 0 10 0 0 1 1 10 0 10 1 10 0

6.4.5 16-bit and 32-bit negation transfers (CML(P),DCML(P))

6.4 Data Transfer Instructions
Y63 Y56 Y48 Y47 Y40
1 1 1 1 10 1 1 10 0 0 1 10 10 0 1 1

(6) Inverts the data at D0 and D1 when X3 is ON, and stores the result at D16 and D17.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
b31 b24 b8 b7 b0
D0,D1 0 0 0 0 0 1 0 0 0 11100101100

b31 b24 b8 b7 b0
D16,D17 1 1 1 1 1 0 1 1 1000 110 100 11

6-117
 BMOV(P)

6.4.6 Block 16-bit data transfers (BMOV(P))

BMOV(P)

Basic High
performance Process Redundant Universal LCPU

Command
BMOV BMOV S D n

Command
BMOVP BMOVP S D n

S : Head number of the devices where the data to be transferred is stored (BIN 16 bits)

D : Head number of the devices of transfer destination (BIN 16 bits)

n : Number of transfers (BIN 16 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S –– ––

D –– ––

n ––

Function
(1) Transfers in batch 16-bit data of n points from the device designated by S to location n
points from the device designated by D .
b15 B0 b15 B0
S 1234 H D 1234 H
S +1 5678 H Block D +1 5678 H
transfer
S +2 7FF0 H D +2 7FF0 H
n n
S +(n-2) 6FFFH D +(n-2) 6FFF H
S +(n-1) 553F H D +(n-1) 553F H

(2) Transfers can be accomplished even in cases where there is an overlap between the source
and destination device.
In the case of transmission to the smaller device number, transmission is from S ; for
transmission to the larger device number, transmission is from S + (n 1).
However, as shown in the example below, when transferring data from R to ZR, or from ZR
to R, the range to be transferred (source) and the range of destination must not overlap.
Transfer from R to R, or from ZR to ZR can be performed without any problem.

• ZR transfer range ((specified head No. of ZR) to (specified head No. of ZR + the number
of transfers -1))
• R transfer range ((specified head No. of R + file register block No. 32768) to (specified
head No. of R + file register block No. 32768 + the number of transfers -1))

6-118
 BMOV(P)

Example
Transfer ranges of ZR and R overlap when transferring 10000 blocks of data from ZR30000
(source) to R10 (block No.1 of the destination). 1
• ZR transfer range (30000) to (30000+10000-1) (30000) to (39999)
• R transfer range (10+(1 32768)) to (10+(1 32768)+10000-1) 2
(32778) to (42777)
Therefore, the range 32778 to 39999 overlaps and the data is not correctly transferred.
Source of transfer Destination of transfer 3
ZR0 R0

Overlapped Block No. 0 4

Z R30000 R32767
R10
Z R39999
R10009
4
Block No. 1

(3) When S is a word device and D is a bit device, the object for the word device will be the
number of bits designated by the bit device digit designation.
7
If K1Y30 has been designated by D , the lower four bits of the word device designated by S

will become the object.

b15 b4 b3 b2 b1b0
8
D +2 D +1 D
S D100 1011
Y3B Y38 Y37 Y34 Y33 Y30
S +1 D101 0011 n 011100111011
n
S +2 D102 0111

6.4.6 Block 16-bit data transfers (BMOV(P))

6.4 Data Transfer Instructions
(4) If bit device has been designated for S and D , then S and D should always have the
same number of digits.

(5) When using a link direct device and an intelligent function module device for S and D , only
either of S or D can be used.
(6) Selection whether to check a device range
Whether to check a device range during execution of the BMOV instruction can be selected
with the device range check inhibit flag (SM237) (only when the conditions for subset
processing are established).
While SM237 is ON, whether S to S + (n) -1 and D to D + (n) - 1 are within the device
range or not are not checked.
For details of SM237, refer to Appendix 3 SPECIAL RELAY LIST.

SM237 can be used only for the Universal model QCPU whose first 5 digits of
serial number is 10012 or later and LCPU.

6-119
 BMOV(P)

Caution
While SM237 is on, do not make the following access.
• The indexing target exceeds the device range.

• The value obtained from " D to D + (n) - 1" is over the boundaries of the device ranges.
• Accessing the file register with file register not set.
• Accessing the area where the multiple CPU high speed transmission area device is not
available (only for the QCPU).
*1: Refer to the DFMOV instruction.

SM237 can be used only for the Universal model QCPU whose first 5 digits of
serial number is 10012 or later and LCPU.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The device range of n points from S or D exceeds the corresponding device range.
(Error code: 4101)

6-120
 BMOV(P)

Program Example
1
(1) The following program outputs the lower 4 bits of data at D66 to D69 to Y30 to Y3F in 4-point
units.
[Ladder Mode] [List Mode] 2
Step Instruction Device

[Operation] 4
Before execution (source of transfer)
b15 b4b3 b0 After execution (destination of transfer)
D66 1110 1 1 1 0 1 Y33 to Y30
D67 00000 0 0 0 0 Y37 to Y34 4
D68 10011 0 0 1 1 Y3B to Y38
D69 0 110 1 1 1 0 1 Y3F to Y3C

Ignored 6

(2) The following program outputs the data at X20 to X2F to D100 to D103 in 4-point units. 7
[Ladder Mode] [List Mode]
Step Instruction Device
8

[Operation]

6.4.6 Block 16-bit data transfers (BMOV(P))

6.4 Data Transfer Instructions
X2F X2CX2B X28X27 X24X23 X20
Before execution 1 0 0 0 0 1 1 1 0 1 1 0 0 1 0 0

After execution (destination of transfer)

b15 b4 b3 b0
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 D100

0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 D101
4 points
0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 D102

0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 D103

Filled with 0s.

6-121
 FMOV(P)

6.4.7 Identical 16-bit data block transfers (FMOV(P))

FMOV(P)

Basic High
performance Process Redundant Universal LCPU

Command
FMOV FMOV S D n

Command
FMOVP FMOVP S D n

S : Data to be transferred or the head number of the devices where the data to be transferred is stored
(BIN 16 bits)
D : Head number of the devices of transfer destination (BIN 16 bits)
n : Number of transfers (BIN 16 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S ––

D –– ––

n ––

Function
(1) Transfers 16-bit data at the device designated by S to n points of devices starting from the
one designated by D .
b15 b0
b15 b0 Transfer D 3456 H
S 3456 H D +1 3456 H
D +2 3456 H
n

D +(n-2) 3456 H
D +(n-1) 3456 H

(2) In cases where S designates a word device and D a bit device, the number of bits
designated by digit designation for the bit device will be the object bits for the word device. S

If K1Y30 has been designated by D , the lower 4 bits of the word device designated by S

will become the object.

D +3 D +2 D +1 D
b15 b4 b3 b2 b1b0 Transfer Y3F Y3C Y3B Y38 Y37 Y34 Y33 Y30
S D100 1 011 1 01 1 1 01 11 01 1 1 01 1
n

(3) If bit device has been designated for S and D , then S and D should always have the
same number of digits.

6-122
 FMOV(P)

(4) Selection whether to check a device range

Whether to check a device range during execution of the FMOV instruction can be selected
with the device range check inhibit flag (SM237) (only when the conditions for subset 1
processing are established).
While SM237 is ON, whether D to D + (n) - 1 is within the device range or not is not
checked.
For details of SM237, refer to Appendix 3 SPECIAL RELAY LIST.
2

Caution 3
While SM237 is on, do not make the following access.
• The indexing target exceeds the device range. 4
• The value obtained from " D to D + (n) - 1" is over the boundaries of the device ranges.
• Accessing the file register with file register not set.
4
• Accessing the area where the multiple CPU high speed transmission area device is not
available (only for the QCPU).
*1: Refer to the DFMOV instruction. 6

SM237 can be used only for the Universal model QCPU whose first 5 digits of 7
serial number is 10012 or later and LCPU.

8
Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.

6.4.7 Identical 16-bit data block transfers (FMOV(P))

6.4 Data Transfer Instructions
• The device range of n points from D or exceeds the corresponding device range.
(Error code: 4101)

6-123
 FMOV(P)

Program Example
(1) The following program outputs the lower 4 bits of D0 when XA goes ON to Y10 to Y23 in
4-bit units.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
b15 b4 b3 b2 b1 b0
D0 1 1 0 1 1 0 1 1 1 0 0 1 1 0 1 1
1 0 1 1 Y13 to Y10
Ignored
1 0 1 1 Y17 to Y14
1 0 1 1 Y1B to Y18 5 points
Transfer 1 0 1 1 Y1F to Y1C
1 0 1 1 Y23 to Y20
(2) The following program outputs the data at X20 through X23 to D100 through D103 when XA
goes ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
X2F X2CX2B X28X27 X24X23 X20
Before execution 1 0 1 1 0 1 1 1 0 0 1 0 1 1 1 0

Ignored After execution (destination of transfer)

b15 b4 b3 b0
0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 D100

0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 D101
4 points
0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 D102

0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 D103

Filled with 0s.

6-124
 DFMOV(P)

6.4.8 Identical 32-bit data block transfers (DFMOV(P))

DFMOV(P)
1
Ver.
High
2
Basic performance Process Redundant Universal LCPU

QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later.

QnUDE(H)CPU: The serial number (first five digits) is "10102" or later.

3
Command
DFMOV DFMOV S D n

Command
4
DFMOVP DFMOVP S D n

4
S : Data to be transferred or head number of the devices where the data to be transferred are stored (BIN 32 bits)

D : Head number of the devices of transfer destination (BIN 32 bits)

n : Number of transfers (BIN 16 bits)
6
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S –– 7
D –– ––

n ––
8

Function

6.4.8 Identical 32-bit data block transfers (DFMOV(P))

6.4 Data Transfer Instructions
(1) This instruction transfers 32-bit data of the device specified by S to the n-point devices
starting from the device specified by D .
b31 b0
b31 b0 Transfer D ＋1, D 1234567H
S ＋1, S 1234567H D ＋3, D ＋2 1234567H
D ＋5, D ＋4 1234567H n

D ＋n 1, D ＋n 2 1234567H

(2) If S specifies data of a device with digit specification, the amount of data to be transferred
will be the amount of the data specified digit.
If K5Y0 is specified by S , the lower 20 bits (five digits) of the word device specified by S
will be the object.
Y1F Y14 Y13 Y0
S ＋1, S

Ignored 20 bits (five digits) data

b31 b20 b19 b0

0 D ＋1, D

0 D ＋3, D ＋2
・ ・
・ ・
Transfer b31 b20 b19 ・ b0 ・
0 D ＋(2n 1), D ＋(2n 2)

Filled with 0s 20 bits (five digits) data

6-125
 DFMOV(P)

(3) If D specifies data of a device with digit specification, the amount of data stored in the
device specified by D will be transferred.
If K5Y0 is specified by D , the lower 20 bits of the word device specified by S will be the
object.
If both S and D specify data of a device with digit specification, the amount of data
specified by D will be transferred regardless of the number of digits.
b31 b20 b19 b0
S ＋1, S

Amount of data specified digits by D

Transfer

D ＋n … D ＋1 D

Y14n+19 Y14n Y27 Y14 Y13 Y0

(4) If the value specified by n is 0, the instruction will be not processed.

(5) Whether to check a device range during the execution of the FMOV instruction can be
selected with the device range check inhibit flag (SM237). (Only when the conditions of the
subset processing are established)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an
error code is stored into SD0.
• The value specified by n is negative. (Error code: 4100)
• The range of n-point devices, to be transferred, exceeds the range of devices specified by
D . (Error code: 4101)

Program Example
(1) The following program stores the value data stored at Y0 to Y13(20 bits) into D10 to
D17,when M0 is turned on,
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
Y1F Y14 Y13 Y0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Ignored 20 bits (five digits) data

b31 b20 b19 b0

0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D11,D10

0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D13,D12
Transfer

0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D15,D14

0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D17,D16

20 bits (five digits)

Filled with 0s

6-126
 XCH(P),DXCH(P)

6.4.9 16-bit and 32-bit data exchanges (XCH(P),DXCH(P))

XCH(P),DXCH(P)
1
Basic High
performance Process Redundant Universal LCPU
2

3
indicates an instruction symbol of XCH, DXCH.

Command
XCH, DXCH D1 D2 4
Command
XCHP, DXCHP P D1 D2
4
D1 , D2 : Head number of the devices where the data to be exchanged is stored (BIN 16/32 bits)

Setting Internal Devices

R, ZR
J \
Zn Constants Other
6
U \G
Data Bit Word Bit Word
D1 ––

D2 –– 7

8
Function
XCH

(1) Conducts 16-bit data exchange between and .

6.4.9 16-bit and 32-bit data exchanges (XCH(P),DXCH(P))

6.4 Data Transfer Instructions
D1 D2

D1 D2

b15 b8 b7 b0 b15 b8 b7 b0
Before execution 0 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1111 00001111 0000

D1 D2

b15 b8 b7 b0 b15 b8 b7 b0
After execution 1111000011110000 0111000000000111

DXCH

(1) Conducts 32-bit data exchange between D1 +1, D1 and D2 +1, D2 .

D1 +1 D1 D2+1 D2

b31 b16 b15 b0 b31 b16 b15 b0

Before execution 1 1 1 1 000111 0000 0000 111111 1111

D1 +1 D1 D2 +1 D2

b31 b16 b15 b0 b31 b16 b15 b0

After execution 0000 111111 1111 1111 000111 0000

6-127
 XCH(P),DXCH(P)

Operation Error
(1) There are no errors associated with the XCH (P) and DXCH (P) instruction.

Program Example
(1) The following program exchanges the present value of T0 with the contents of D0 when X8
goes ON.
[Ladder Mode] [List Mode]

Step Instruction Device

(2) The following program exchanges the contents of D0 with the data from M16 to M31 when
X10 goes ON.
[Ladder Mode] [List Mode]
Step Instruction Device

(3) The following program exchanges the contents of D0 and D1 with the data at M16 to M47
when X10 goes ON.
[Ladder Mode] [List Mode]
Step Instruction Device

(4) The following program exchanges the contents of D0 and D1 with those of D9 and D10
when M0 goes ON.
[Ladder Mode] [List Mode]
Step Instruction Device

6-128
 BXCH(P)

6.4.10 Block 16-bit data exchanges (BXCH(P))

BXCH(P)
1
Basic High
performance Process Redundant Universal LCPU
2

Command
3
BXCH BXCH D1 D2 n

BXCHP
Command
BXCHP D1 D2 n
4

D1 , D2 : Head number of the devices where the data to be exchanged is stored (BIN 16 bits) 4
n : Number of exchanges (BIN 16 bits)

Setting Internal Devices J \ Constants

Data Bit Word
R, ZR
Bit Word
U \G Zn
K, H
Other
6
D1 –– –– ––

D2 –– –– ––

n ––
7

8
Function
(1) Exchanges 16-bit data of n points from device designated by D1 and 16-bit data of n points
from device designated by D2 .

6.4.10 Block 16-bit data exchanges (BXCH(P))

6.4 Data Transfer Instructions
b15 b8 b7 b0 b15 b8 b7 b0
D1 0000 111100001111 D2 00 11001100 110011
D1 +1 1111111100000000 D2 +1 110000 11110000 11
D1 +2 0000000011111111 D2 +2 1111111100000000
n n

D1 +(n 2) 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 D2 +(n 2) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
D1 +(n 1) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D2 +(n 1) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

b15 b8 b7 b0 b15 b8 b7 b0
D1 00 11001100110011 D2 0000 111100001111
D1 +1 110000 11110000 11 D2 +1 1111111100000000
D1 +2 1111111100000000 D2 +2 0000000011111111
n n

D1 +(n 2) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D2 +(n 2) 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
D1 +(n 1) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 +(n 1) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

6-129
 BXCH(P)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The range of the device of n points from a device designated by D1 , D2 or exceeds the
relevant device. (Error code: 4101)

• The D1 and D2 devices overlap. (Error code: 4101)

Program Example
(1) The following program exchanges 16-bit data for 3 points from D200 for 16-bit data for 3
points from R0 when X1C goes ON.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]

b15 b8 b7 b0 b15 b8 b7 b0
D200 0 0 1 1 1 1 0 0 1 1 1 1 1 1 1 1 R0 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1
D201 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 R1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
D202 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 R2 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0

b15 b8 b7 b0 b15 b8 b7 b0
D200 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 R0 0 0 1 1 1 1 0 0 1 1 1 1 1 1 1 1
D201 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 R1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
D202 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 R2 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

6-130
 SWAP(P)

6.4.11 Upper and lower byte exchanges (SWAP(P))

SWAP(P)
1
Basic High
performance Process Redundant Universal LCPU
2

3
Command
SWAP SWAP D

Command 4
SWAPP SWAPP D

D : Head number of the devices where the data is stored (BIN 16 bits)
4
Setting Internal Devices J \
R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
6
D ––

7
Function
(1) Exchanges the higher and lower 8 bits of the device designated by D . 8
b15 b12 b11 b8 b7 b4 b3 b0
D 0 10 1010 11010 10 10

6.4.11 Upper and lower byte exchanges (SWAP(P))

6.4 Data Transfer Instructions
b15 b12 b11 b8 b7 b4 b3 b0
D 10 10 10 100 10 10 10 1

Operation Error
(1) There are no operation errors associated with the SWAP(P) instruction.

Program Example
(1) The following program exchanges the higher 8 bits and lower 8 bits of R10 when X10 goes
ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
b15 b12 b11 b8 b7 b4 b3 b0
R10 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

b15 b12 b11 b8 b7 b4 b3 b0

R10 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0

6-131
 CJ,SCJ,JMP

6.5 Program Branch Instructions

6.5.1 Pointer branch instructions (CJ,SCJ,JMP)

CJ,SCJ,JMP

Basic High
performance Process Redundant Universal LCPU

Command
CJ CJ P**

Command
SCJ SCJ P**

JMP JMP P**

Label
Command
P**

P** : Pointer number of jump destination (Device name)

Setting Internal Devices J \ Other

R, ZR U \G Zn Constants
Data Bit Word Bit Word P

P ––

Function
CJ
(1) Executes the program specified by the pointer number within the same program file, when
the execution command is ON.
(2) When the execution command is OFF, the program at the next step is executed.
ON

Execution command OFF

CJ
Executed at each scan

SCJ
(1) Executes the program specified by the pointer number within the same program file starting
with the scan immediately after OFF ON of the execution command.
(2) When the execution command is OFF or turned ON OFF, the program at the next step is
executed.
ON

Execution command OFF

SCJ
1 scan Executed at each scan

6-132
 CJ,SCJ,JMP

JMP
(1) Unconditionally executes program of designated pointer number within the same program 1
file.

2
Note the following points when using the jump instruction.
1. After the timer coil has gone ON, accurate measurements cannot be made if
there is an attempt to jump the timer of a coil that has been turned ON using the 3
CJ, SCJ or JMP instructions.
2. Scan time is shortened if the CJ, SCJ or JMP instruction is used to force a jump
to the OUT instruction.
3. Scan time is shortened if the CJ, SCJ or JMP instruction is used to force a jump
4
to the rear.
4. The CJ, SCJ, and JMP instructions can be used to jump to a step prior to the
step currently being executed. However, it is necessary to consider methods to 4
get out of the loop so that the watchdog timer does not time out in the process.
X0
P8
Y40 6
When X3 is X7
ON, the loop CJ P9
is closed. X3
CJ P8
Exits the loop when
X7 is turned ON.
7
P9 X6
Y42

5. The device to which a jump has been made with the CJ, SCJ or JMP does not
8
change.
XB Jumps to label P19
10 CJ P19 when XB turns ON.
XC Y43 and Y49 remain

6.5.1 Pointer branch instructions (CJ,SCJ,JMP)

6.5 Program Branch Instructions
14 Y43 unchanged regardless
XB of whether XB and XC are
16 Y49 turned ON/OFF during the
P19 execution of CJ instruction.
X9
18 Y4C

6. The label (P*) occupies step 1.

X8
10 CJ P9
M33
14 Y30
Occupies 1 step
M3
16 Y36
P9 M36
18 Y39
X9
21 Y3B

7. The jump instructions can be used only for pointer numbers within the same
program file.
8. If a jump is made to a pointer number inside the skip range during a skip
operation, program execution will be taken up following the pointer number of
the jump destination.

6-133
 CJ,SCJ,JMP

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The pointer number designated does not come prior to the END instruction.
(Error code: 4210)
• A pointer number which is not in use as a label in the same program has been
designated. (Error code: 4210)
• A common pointer has been designated. (Error code: 4210)

Program Example
(1) The following program jumps to P3 when X9 goes ON.
[Ladder Mode] [List Mode]
Step Instruction Device

(2) The following program jumps to P3 from the next scan after XC goes ON.
[Ladder Mode] [List Mode]
Step Instruction Device

Caution
(1) When using the Universal model QCPU and LCPU with the SCJ instruction, inserting "AND
SM400" (or the NOP instruction) in immediately before the SCJ instruction is required.
[Program example1]
[Ladder Mode] [List Mode]
Step Instruction Device
0 LD M0
1 AND SM400
2 SCJ P0

[Program example2]
[Ladder Mode] [List Mode]
Step Instruction Device
0 LD M0
1 OUT Y0
2 AND SM400
3 SCJ P0

6-134
 GOEND

6.5.2 Jump to END (GOEND)

GOEND
1
Basic High
performance Process Redundant Universal LCPU
2

3
Command
GOEND GOEND

4
Setting Internal Devices J \
Data Bit Word
R, ZR
Bit Word
U \G Zn Constants Other
4
–– ––

6
Function
(1) Jumps to the FEND or END instruction in the same program file.
7
Operation Error
8
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The GOEND instruction has been executed after the execution of the CALL, ECALL
instruction, and prior to the execution of the RET instruction. (Error code: 4211)

6.5.2 Jump to END (GOEND)

6.5 Program Branch Instructions
• The GOEND instruction has been executed after the execution of the FOR instruction,
and prior to the execution of the NEXT instruction. (Error code: 4200)
• The GOEND instruction has been executed during an interrupt program but prior to the
execution of the IRET instruction. (Error code: 4221)
• The GOEND instruction was executed between the CHKCIR and CHKEND instruction
block. (Error code: 4230)
• The GOEND instruction was executed between the IX and IXEND instruction block.
(Error code: 4231)

Program Example
(1) The following program jumps to the END instruction if D0 holds a negative number.
[Ladder Mode] [List Mode]
Step Instruction Device

6-135
 DI,EI,IMASK

6.6 Program Execution Control Instructions

6.6.1 Interrupt disable/enable instructions, interrupt program mask

(DI,EI,IMASK)
DI,EI,IMASK

Basic High
performance Process Redundant Universal LCPU

When the Basic model QCPU is used

DI DI

Sequence program

IMASK IMASK S

EI EI

S : Interrupt mask data or head number of the devices where the interrupt mask data is stored (BIN 16 bits)

Setting Internal Devices J \

R, ZR U \G Zn Constants Other
Data Bit Word Bit Word

S –– ––

Function
DI
(1) Disables the execution of an interrupt program until the EI instruction has been executed,
even if a start cause for the interrupt program occurs.
(2) A DI state is entered when power is turned ON or when the CPU module is reset.
EI
The EI instruction is used to clear the interrupt disable state resulting from the execution of
the DI instruction, and to create a state in which the interrupt program designated by the
interrupt pointer number certified by the IMASK instruction can be executed.
When the IMASK instruction is not executed, I32 to I47 are disabled.

Sequence program

DI
Even if a cause of interrupt occurs during
Sequence program the execution of the sequence program
between the DI and EI instructions, execution
EI of the interrupt program is suspended until
FEND the processing of the sequence program
is completed.
In Interrupt programs

6-136
 DI,EI,IMASK

IMASK
(1) Enables/disables the execution of the interrupt program marked by the designated interrupt 1
pointer by using the bit pattern of 8 points from the device designated by S .
• 1(ON)...... Interrupt program execution enabled
• 0(OFF).... Interrupt program execution disabled
2
(2) The interrupt pointer numbers corresponding to the individual bits are as shown below:

S
b15 b14 b13 b12 b11 b10 b9
I15 I14 I13 I12 I11 I10 I9
b8
I8
b7
I7
b6
I6
b5
I5
b4
I4
b3
I3
b2
I2
b1
I1
b0
I0
3
S+1 I31 I30 I29 I28 I27 I26 I25 I24 I23 I22 I21 I20 I19 I18 I17 I16

S+2 I47 I46 I45 I44 I43 I42 I41 I40 I39 I38 I37 I36 I35 I34 I33 I32
4
S+3 I63 I62 I61 I60 I59 I58 I57 I56 I55 I54 I53 I52 I51 I50 I49 I48

S+4 I79 I78 I77 I76 I75 I74 I73 I72 I71 I70 I69 I68 I67 I66 I65 I64

S+5 I95 I94 I93 I92 I91 I90 I89 I88 I87 I86 I85 I84 I83 I82 I81 I80
4
S+6 I111 I110 I109 I108 I107 I106 I105 I104 I103 I102 I101 I100 I99 I98 I97 I96

S+7 I127 I126 I125 I124 I123 I122 I121 I120 I119 I118 I117 I116 I115 I114 I113 I112

(3) When the power is turned ON or when the CPU module has been reset, the execution of
6
interrupt programs I0 to I31,I48 to I127 is enabled, and the execution of interrupt programs
I32 to I47 is disabled.
(4) The statuses of devices S , S +1, S +2, and S +3 to S +7 are stored in SD715 to SD717 7
and SD781 to SD785 (storage area for the IMASK instruction mask pattern).
(5) Although the special registers are separated as SD715 to SD717 and SD781 to SD785,
device numbers should be designated as S to S +7 successively. 8

1. An interrupt pointer occupies 1 step.

I 10

6.6.1 Interrupt disable/enable instructions, interrupt program mask (DI,EI,IMASK)

6.6 Program Execution Control Instructions
X1C
50 Y10
Stored at step 50
X5
53 Y30

55 IRET

2. For the information on interrupt conditions, link direct devices, refer to the
QnUCPU User’s Manual(Function Explanation, Program Fundamentals) or
Qn(H)/QnPH/QnPRHCPU User’s Manuall(Function Explanation, Program
Fundamentals)
3. The DI state (interrupt disabled) is active during the execution of an interrupt
program. Do not insert the EI instructions in interrupt programs to attempt the
execution of multiple interrupts, with interrupt programs running inside interrupt
programs.
4. If there are the EI and DI instructions within a master control, these instructions
will be executed regardless of the execution/non-execution status of the MC
instruction.

6-137
 DI,EI,IMASK

Operation Error
(1) There are no operation errors associated with the DI, EI or IMASK instruction.

Program Example
(1) The following program is designed to enable the execution of only the interrupt programs
having the interrupt pointer numbers I1 and I3 while X0 is ON.
[Ladder Mode] [List Mode]
Step Instruction Device

6-138
 DI,EI,IMASK

When the High Performance model QCPU/Process CPU/Redundant CPU/Universal model

QCPU or LCPU is used 1

DI DI 2
Sequence program

IMASK IMASK S 3
EI EI
4
S : Head number of the devices where the interrupt mask data is stored (BIN 16 bits)

Setting Internal Devices J \

4
R, ZR U \G Zn Constants Other
Data Bit Word Bit Word

S –– ––
6

Function 7
DI
(1) Disables the execution of an interrupt program until the EI instruction has been executed, 8
even if a start cause for the interrupt program occurs.
(2) A DI state is entered when power is turned ON or when the CPU module is reset.
EI

6.6.1 Interrupt disable/enable instructions, interrupt program mask (DI,EI,IMASK)

6.6 Program Execution Control Instructions
The EI instruction is used to clear the interrupt disable state resulting from the execution of
the DI instruction, and to create a state in which the interrupt program designated by the
interrupt pointer number enabled by the IMASK instruction and the fixed cycle execution
type program can be executed.
When the IMASK instruction is not executed, I32 to I47 are disabled.

Sequence program

DI Even if a cause of interrupt occurs during

Sequence program the execution of the sequence program
between the DI and EI instructions,
EI execution of the interrupt program is
FEDN suspended until the processing of the
sequence program is completed.
In Interrupt programs

6-139
 DI,EI,IMASK

IMASK
(1) Enables/disables the execution of the interrupt program marked by the designated interrupt
pointer by using the bit pattern of 16 points from the device designated by S .
• 1(ON)......Interrupt program execution enabled
• 0(OFF) .... Interrupt program execution disabled
(2) The interrupt pointer numbers corresponding to the individual bits are as shown below:
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
S I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0

S +1 I31 I30 I29 I28 I27 I26 I25 I24 I23 I22 I21 I20 I19 I18 I17 I16

S +2 I47 I46 I45 I44 I43 I42 I41 I40 I39 I38 I37 I36 I35 I34 I33 I32

S +3 I63 I62 I61 I60 I59 I58 I57 I56 I55 I54 I53 I52 I51 I50 I49 I48

S +4 I79 I78 I77 I76 I75 I74 I73 I72 I71 I70 I69 I68 I67 I66 I65 I64

S +5 I95 I94 I93 I92 I91 I90 I89 I88 I87 I86 I85 I84 I83 I82 I81 I80

S +6 I111 I110 I109 I108 I107 I106 I105 I104 I103 I102 I101 I100 I99 I98 I97 I96

S +7 I127 I126 I125 I124 I123 I122 I121 I120 I119 I118 I117 I116 I115 I114 I113 I112

S +8 I143 I142 I141 I140 I139 I138 I137 I136 I135 I134 I133 I132 I131 I130 I129 I128

S +9 I159 I158 I157 I156 I155 I154 I153 I152 I151 I150 I149 I148 I147 I146 I145 I144

S +10 I175 I174 I173 I172 I171 I170 I169 I168 I167 I166 I165 I164 I163 I162 I161 I160

S +11 I191 I190 I189 I188 I187 I186 I185 I184 I183 I182 I181 I180 I179 I178 I177 I176

S +12 I207 I206 I205 I204 I203 I202 I201 I200 I199 I198 I197 I196 I195 I194 I193 I192

S +13 I223 I222 I221 I220 I219 I218 I217 I216 I215 I214 I213 I212 I211 I210 I209 I208

S +14 I239 I238 I237 I236 I235 I234 I233 I232 I231 I230 I229 I228 I227 I226 I225 I224

S +15 I255 I254 I253 I252 I251 I250 I249 I248 I247 I246 I245 I244 I243 I242 I241 I240

(3) When the power is turned on or the CPU module is reset, the interrupt programs are as
follows.
(a) High Performance model QCPU, Process CPU, and Redundant CPU
Execution of interrupt programs I0 to I31 and I48 to I255 is enabled, and execution of
interrupt programs I32 to I47 is disabled.
(b) Universal model QCPU and LCPU
Execution of interrupt programs I0 to I31 and I45 to I255 is enabled, and execution of
interrupt programs I32 to I44 is disabled.

(4) The status of devices S , S +1, S +2, and S +3 to S +15 are stored in SD715 to SD717
and SD781 to SD793 (storage area for the IMASK instruction mask pattern).
(5) Although the special registers are separated as SD715 to SD717 and SD781 to SD793,
device numbers should be designated as S to S +15 successively.

6-140
 DI,EI,IMASK

1. An interrupt pointer occupies 1 step.

T10
1
X1C
50 Y10
Stored at step 50
X5
53 Y30 2
55 IRET

• For the information on interrupt conditions, link direct devices, refer to the 3
QnUCPU User’s Manual(Function Explanation, Program Fundamentals) or
Qn(H)/QnPH/QnPRHCPU User’s Manuall(Function Explanation, Program
Fundamentals) 4
2. The DI state (interrupt disabled) is active during the execution of an interrupt
program. Do not insert the EI instructions in interrupt programs to attempt the
execution of multiple interrupts, with interrupt programs running inside interrupt
programs.
4
3. If there are the EI and DI instructions within a master control, these instructions
will be executed regardless of the execution/non-execution status of the MC
instruction. 6

6.6.1 Interrupt disable/enable instructions, interrupt program mask (DI,EI,IMASK)

6.6 Program Execution Control Instructions

6-141
 DI,EI,IMASK

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• The device specified by S exceeds the range of the corresponding device.
(For the Universal model QCPU, LCPU.) (Error code: 4101)

Program Example
(1) The following program creates an execution enabled state for the interrupt program marked
by the interrupt pointer number when X0 is ON.
[Ladder Mode] [List Mode]
Step Instruction Device

6-142
 IRET

6.6.2 Recovery from interrupt programs (IRET)

IRET
1
Basic High
performance Process Redundant Universal LCPU
2

3
I
**
IRET
4
IRET

Setting
Data
Internal Devices
Bit Word
R, ZR
Bit
J \
Word
U \G Zn Constants Other 4
–– ––

6
Function
(1) Indicates the completion of interrupt program processing. 7
(2) Returns to sequence program processing following the execution of the IRET instruction.

Operation Error 8
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• There is no pointer corresponding to the interrupt number. (Error code: 4220)

6.6.2 Recovery from interrupt programs (IRET)

6.6 Program Execution Control Instructions
• The IRET instruction was executed before the interrupt program is executed.
(Error code: 4223)
• The END, FEND, GOEND, or STOP instruction has been executed after the generation of
an interrupt and prior to the execution of the IRET instruction. (Error code: 4221)
• The IRET instruction was executed during the fixed scan execution type program.
(For the Universal model QCPU, LCPU) (Error code: 4223)

6-143
 IRET

Program Example
(1) The following program adds 1 to D0 if M0 is ON when the number 3 interrupt is generated.
[Ladder Mode] [List Mode]
Step Instruction Device

6-144
 RFS(P)

6.7 I/O Refresh Instructions

1
6.7.1 I/O refresh (RFS(P))
RFS(P)
2
Basic High
Process Redundant Universal LCPU
3
performance

4
Command
RFS RFS S n

Command 4
RFSP RFSP S n

6
S : Head number of the devices to be refreshed (bits)
n : Number of refreshes (BIN 16 bits)

Setting Internal Devices

R, ZR
J \
U \G Zn
Constants
Other 7
Data Bit Word Bit Word K, H

S –– ––
(Only X, Y)

n –– 8

Function

6.7.1 I/O refresh (RFS(P))

6.7 I/O Refresh Instructions
(1) Refreshes only the device being scanned during a scan, and functions to fetch input from
external sources or to output data to an output module.
(2) Fetching of input from or sending output to an external source is conducted in batch only
after the execution of the END instruction, so it is not possible to output a pulse signal to an
outside source during the execution of a scan.
When the I/O refresh instruction is executed, the inputs (X) or outputs (Y) of the
corresponding device numbers are refreshed forcibly midway through program execution.
Therefore, a pulse signal can be output to an external source during a scan.
(3) Use direct access inputs (DX) or direct access outputs (DY) to refresh inputs (X) or outputs
(Y) in 1-point units.
[Program based on the RFS instruction]
Command
RFS X0 K1 Refreshes X0
X0
Y20
Command
RFS Y20 K1 Refreshes Y20

[Program based on direct access input and direct access output]

DX0
DY20

Direct access input Direct access output

6-145
 RFS(P)

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• The range n points from the device designated by S exceeds the proximate I/O range.
(Error code: 4101)

Program Example
(1) The following program refreshes X100 to X11F and Y200 to Y23F when M0 goes ON.
[Ladder Mode] [List Mode]
Step Instruction Device

6-146
 UDCNT1

6.8 Other Convenient Instructions

1
6.8.1 Counter 1-phase input up or down (UDCNT1)
UDCNT1
2
High
Basic performance Process Redundant Universal LCPU

Command 4
UDCNT1 UDCNT1 S D n

S : S + 0: Input number for count input (bits) 4

S + 1: For setting count up/down (bits)
•OFF: Count up (add numbers when counting)
•ON: Count down (subtract numbers when counting)
D : Number of the counter to be enabled to start counting with the UDCNT1 instruction (Device name)
6
n : Value to set (BIN 16 bits)

Setting
Data
Internal Devices
Bit Word
R, ZR
Bit
J \
Word
U \G Zn
Constants
K, H
Other 7
S (Only X)*1 –– –– –– ––

D –– (Only C)*2 –– –– ––
8
n *2 *2 *2 ––

*1: Only the X device can be used for S . However, the X device can be used only in the range of number of I/O points
(the number of accessible points to actual I/O modules).
*2: Local devices and the file registers set for individual programs cannot be used.

6.8.1 Counter 1-phase input up or down (UDCNT1)

6.8 Other Convenient Instructions
Function
(1) When the input designated at S goes from OFF to ON, the present value of the counter
designated at D will be updated.
(2) The direction of the count is determined by the ON/OFF status of the input designated by
S +1.

• OFF : Count up (counts by adding to the present value)

• ON : Count down (counts by subtracting from the present value)
(3) Count processing is conducted as described below:
• When the count is going up, the counter contact designated at D goes ON when the
present value becomes identical with the setting value designated by n. However, the
present value count will continue even when the contact of the counter designated at D

goes ON. (See Program Example (1))

• When the count is going down, the counter for the contact designated at D goes OFF
when the present value reaches the set value 1. (See Program Example (1))

6-147
 UDCNT1

• The counter designated at D is a ring counter. If it is counting up when the present value
is 32767, the present value will become 32768. Further, if it is counting down when the
present value is 32768, the present value will become 32767. The count processing
performed on the present value is as shown below:
32768 32767 2 1 0 1 2 32766 32767

When counting up

When counting down

(4) The UDCNT1 instruction triggers counting when the execution command is turned
OFF ON and suspends counting when the execution command is turned ON OFF.
When the execution command is turned OFF ON again, the counting resumes from the
suspended value.

(5) The RST instruction clears the present value of the counter designated at D and turns the
contact OFF.

1. With the UDCNT1 instruction, the argument device data is registered in the
work area of the CPU module and counting operation is processed as a system
interrupt. (The device data registered in the work area is cleared by turning the
execution command OFF, or turning the STOP/RUN switch STOP RUN.) For
this reason, the pulses that can be counted must have longer ON and OFF
times than the interrupt interval of the CPU module. The interrupt interval of
individual modules is shown below:
CPU Module Type Name Interrupt Interval
High Performance model QCPU, Process CPU,
1 ms
Universal model QCPU, LCPU

2. The set value cannot be changed during counting directed by the UDCNT1
instruction (while the execution command is ON). To change the set value, turn
OFF the execution command.
3. Counters which have been designated by the UDCNT1 instruction cannot be
used by other instructions. If they are used by other instructions, they will not be
capable of returning an accurate count.
4. The UDCNT1 instruction can be used as many as 6 times within all the
programs being executed. The seventh and the subsequent UDCNT1
instructions are not processed.

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• The device specified by S exceeds the range of the corresponding device.
(Error code: 4101)

6-148
 UDCNT1

Program Example
1
(1) This program uses C0 (Up/Down counter) to count the number of times X0 goes from OFF
to ON after X20 has gone ON.
[Ladder Mode] [List Mode] 2
Step Instruction Device

[Operation] 4
X20

X0
4
X1 Up Down Up

C0 present value 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0- 1- 2- 3- 2- 1 0 1 1 6
C0 contact

6.8.1 Counter 1-phase input up or down (UDCNT1)

6.8 Other Convenient Instructions

6-149
 UDCNT2

6.8.2 Counter 2-phase input up or down (UDCNT2)

UDCNT2

High
Basic performance Process Redundant Universal LCPU

Command
UDCNT2 UDCNT2 S D n

S : S + 0: Input number for count input (A phase pulse) (bits)

S + 1: Input number for count input (B phase pulse) (bits)

D : Number of the counter to be enabled to start counting with the UDCNT2 instruction (Device name)
n : Value to set (BIN 16 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S (Only X)*1 –– –– –– ––

D –– (Only C)*2 –– –– ––

n *2 *2 *2 ––

*1: Only the X device can be used for S . However, the X device can be used only in the range of number of I/O points
(the number of accessible points to actual I/O modules).
*2: Local devices and the file registers set for individual programs cannot be used.

Function
(1) The present value of the counter designated by D is updated depending on the status of the
input designated by S (A phase pulse) and the status of the input designated by S +1 (B
phase pulse).
(2) Direction of the count is determined in the following manner:
• When S is ON, if S +1 goes from OFF to ON, count up operation is performed (values
are added to the present value of the counter).
• When S is ON, if S +1 goes from ON to OFF, count down operation is performed (values
are subtracted from the present value of the counter).
• No count operation is performed if S is OFF.
(3) Count processing is conducted as described below:
• When the count is going up, the counter contact designated at D goes ON when the
present value becomes identical with the setting value designated by n. However, the
present value count will continue even when the contact of the counter designated at D
goes ON. (See Program Example (1))
• When the count is going down, the counter for the contact designated at D goes OFF
when the present value reaches the set value 1. (See Program Example (1))

6-150
 UDCNT2

• The counter designated at D is a ring counter. If it is counting up when the present value
is 32767, the present value will become 32768. Further, if it is counting down when the
present value is 32768, the present value will become 32767. The count processing 1
performed on the present value is as shown below:
32768 32767 2 1 0 1 2 32766 32767

2
When counting up

When counting down

(4) Count processing conducted according to the UDCNT2 instruction begins when the count 3
command goes from OFF to ON, and is suspended when it goes from ON to OFF.
When the execution command is turned OFF to ON again, the counting resumes from the
suspended value. 4
(5) The RST instruction clears the present value of the counter designated at D and turns the
contact OFF.
4
1. With the UDCNT2 instruction, the argument device data is registered in the
work area of the CPU module and counting operation is processed as a system 6
interrupt. (The device data registered in the work area is cleared by turning the
execution command OFF, or turning the STOP/RUN switch STOP RUN.) For
this reason, the pulses that can be counted must have longer ON and OFF 7
times than the interrupt interval of the CPU module. The interrupt interval of
individual modules is shown below:
CPU Module Type Name Interrupt Interval 8
High Performance model QCPU, Process CPU,
1 ms
Universal model QCPU, LCPU

2. The set value cannot be changed during counting directed by the UDCNT2
instruction (while the execution command is ON). To change the set value, turn

6.8.2 Counter 2-phase input up or down (UDCNT2)

6.8 Other Convenient Instructions
OFF the execution command.
3. Counters designated by the UDCNT2 instruction cannot be used by any other
instruction. If they are used by other instructions, they will not be capable of
returning an accurate count.
4. The UDCNT2 instruction can be used as many as 5 times within all the
programs being executed. The sixth and the subsequent UDCNT2 instructions
are not processed.

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• The device specified by S exceeds the range of the corresponding device.
(Error code: 4101)

6-151
 UDCNT2

Program Example
(1) The following program performs a count operation as instructed by C0 (count up or down) on
the status of X0 and X1 after X20 has gone ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]

X20

X0

X1

COM present value 0 1 2 3 4 5 4 3 2 1 0 1 2 1 1

C0 contact

6-152
 TTMR

6.8.3 Teaching timer (TTMR)

TTMR
1
High
2
Basic performance Process Redundant Universal LCPU

3
Command
TTMR TTMR D n

4
D : D + 0: The device where measurement value is stored (BIN 16 bit)

D + 1: For CPU module system use (BIN 16 bit) 4

n : Measurement value multiplier (BIN 16 bits)

Setting Internal Devices J \ Constants

Data Bit Word
R, ZR
Bit Word
U \G Zn
K, H
Other
6
D –– –– ––

n –– ––
7

Function
8
(1) Measures the time while the execution command is ON in units of seconds, and stores the
multiplied value of the measured time by the multiplier specified by n at the device
designated by D .

(2) Clears the device designated by +0 or +1 when the execution command is turned

6.8.3 Teaching timer (TTMR)

6.8 Other Convenient Instructions
D D

OFF ON.
(3) The multipliers that can be designated by n are as shown below:
n Multiplier
0 1
1 10
2 100

1. Time measurements are conducted when the TTMR instruction is executed.

Using the JMP or similar instruction to jump the TTMR instruction will make it
impossible to get an accurate measurement.
2. Do not change the multiplier designated by n while the TTMR instruction is
being executed. Changing this multiplier will result in an inaccurate value being
returned.
3. The TTMR instruction can also be used in low speed execution type programs.
4. The device designated by D +1 is used by the system of the CPU module, so
users should not change its value. If users do change this value, the value
stored in the device designated by D will no longer be accurate.

(4) No processing is performed when the value specified by "n" is other than 0 to 2.

6-153
 TTMR

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• The device specified by D exceeds the range of the corresponding device.
(For the Universal model QCPU, LCPU.) (Error code: 4101)

Program Example
(1) The following program stores the amount of time that X0 is ON at D0.
[Ladder Mode] [List Mode]
Step Instruction Device

6-154
 STMR

6.8.4 Special function timer (STMR)

STMR
1
High
2
Basic performance Process Redundant Universal LCPU

3
Command
STMR STMR S n D

4
S : Timer number (word)
n : Value to set (BIN 16 bits).
4
D : D + 0: Off delay timer output (bits)

D + 1: One shot timer output after OFF (bits)

D + 2: One shot timer output after ON (bits) 6

D + 3: ON delay and Off delay timer output (bits)

Setting Internal Devices J \ Constants

7
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S –– *1 –– –– ––

n ––

D –– –– –– –– 8
*1:Can be used only by timer (T) data

Function

6.8.4 Special function timer (STMR)

6.8 Other Convenient Instructions
(1) The STMR instruction uses the 4 points from the device designated by D to perform four
types of timer output.
• OFF delay timer output ( D +0)
Goes ON at the leading edge of the command for the STMR instruction, and after the
trailing edge of the command, goes OFF when the amount of time designated by n has
passed.
• One shot timer output after OFF ( D +1)
Goes ON at the trailing edge of the command for the STMR instruction, and goes OFF
when the amount of time designated by n has passed.
• One shot timer output after ON ( D +2)
Goes ON at the leading edge of the command for the STMR instruction, and goes OFF
either when the amount of time designated by n has passed, or when the command for
the STMR instruction goes OFF.
• ON delay timer output ( D +3)
Goes ON at the trailing edge of the timer coil, and after the trailing edge of the command
for the STMR instruction, goes OFF when the amount of time designated by n has
passed.

(2) The timer coil designated by S turns ON at the leading edge and trailing edge of the
command for the STMR instruction, and starts measurement of the present value.
• The timer coil measures to the point where the value reaches the set value designated by
n, then enters a time up state and goes OFF.
• If the command for the STMR instruction goes OFF before the timer coil reaches the time
up state, it will remain ON. Timer measurement is continued at this time. When the STRM
instruction command goes ON once again, the present value will be cleared to 0 and
measurement will begin once again.

6-155
 STMR

(3) The timer contact goes ON at the leading edge of the command for the STMR instruction,
and after the trailing edge is reached, the timer coil goes OFF at the trailing edge of the
STMR instruction command.
The timer contact is used by the CPU module system, and cannot be used by the user.

Command for
STMR instruction

S (Coil)

S (Contact)

D +0 OFF delay timer

D +1 One-shot timer after OFF

D +2 One-shot timer after ON

D +3 ON delay timer + OFF delay timer

Setting value Set value Set value Set value

designated by n designated by n designated by n designated by n

(4) Measurement of the present value of the timer specified by the STMR instruction is
executed regardless of the command ON/OFF status of the STMR instruction.
If the STMR instruction is jumped with the JMP or similar instruction, it will not be possible to
get accurate measurement.

(5) Measurement unit for the timer designated by D is identical to the low speed timer.
(6) A value between 0 to 32767 can be set for n.
No operation if n is other than 0 to 32767.

(7) The timer designated by S cannot be used by the OUT instruction.

If the STMR instruction and the OUT instruction use the same timer number, accurate
operation will not be conducted.

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• The device specified by D exceeds the range of the corresponding device.
(For the Universal model QCPU, LCPU.) (Error code: 4101)

6-156
 STMR

Program Example
1
(1) The following program turns Y0 and Y1 ON and OFF once each second (flicker) when X20
is ON.
(Uses 100 ms timer) 2
[Ladder Mode] [List Mode]
Step Instruction Device
3

4
[Timing Chart]

X20 6
M1, Y0

M2, Y1 7
M3

1 sec 1 sec 8

6.8.4 Special function timer (STMR)

6.8 Other Convenient Instructions

6-157
 ROTC

6.8.5 Rotary table shortest direction control (ROTC)

ROTC

High
Basic performance Process Redundant Universal LCPU

Command
ROTC ROTC S n1 n2 D

S : S +0 : Measures the number of table rotations (for system use) (BIN 16 bits)
S +1 : Call station number (BIN 16 bits)
S +2 : Call item number (BIN 16 bits)
n1 : Number of divisions of table (2 to 32767) (BIN 16 bits)
n2 : Number of low-speed sections (value from 0 to less than n1) (BIN 16 bits)
D : D +0 : A phase input signal (bits)
D +1 : B phase input signal (bits)
D +2 : 0 point detection input signal (bits)
D +3 : High speed forward rotation output signal (for system use) (bits)
D +4 : Low speed forward rotation output signal (for system use) (bits)
D +5 : Stop output signal (for system use) (bits)
D +6 : Low speed reverse rotation output signal (for system use) (bits)
D +7 : High speed reverse rotation output signal (for system use) (bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S –– –– ––

n1 ––

n2 ––

D –– –– ––

Function
(1) This control functions to enable shortest direction control of the rotary table to the position of
the station number designated by S +1 in order to remove or deposit an item whose number
has been designated by S +2 on a rotary table with equal divisions of the value designated
by n1.
(2) The item number and station number are controlled as items allocated by counterclockwise
rotation.
(3) The system uses S +0 as a counter to instruct it as to what item is at which number counting
from station number 0. Do not rewrite the sequence program data.
Accurate controls will not be possible in cases where users have rewritten the data.
(4) The value of n2 should be less than the number of table divisions specified by n1.
(5) D +0 and D +1 are A and B phase input signals that are used to detect whether the direction
of the rotary table rotation is forward or reverse.
The direction of rotation is judged by whether the B phase pulse is at its leading or trailing
edge when the A phase pulse is ON:
• When the B phase is at the leading edge: Forward rotation (clockwise rotation)
• When the B phase is at the trailing edge: Reverse rotation (counterclockwise rotation)

6-158
 ROTC

(6) D +2 is the 0 point detection output signal that goes ON when item number 0 has arrived at

the No. 0 station.

When the device designated by D +2 goes ON while the ROTC instruction is being
1
executed, S +0 is cleared.
It is best to perform this clear operation first, then to begin shortest direction control with the
ROTC instruction.
2
(7) The data from D +3 to D +7 consists of output signals needed to control the table's
operation. 3
The output signal of one of the devices from D +3 to D +7 will go ON in response to the
execution results of the ROTC instruction.

(8) If the command for the ROTC instruction is OFF, clears all D +3 to D +7 without performing
4
shortest direction control.
(9) The ROTC instruction can be used only one time in all programs where it is executed.
Attempts to use it more than one time will result in inaccurate operations.
4
(10) No processing is performed when the value of S +0 to S +2, or the value of n2 is greater
than n1. 6

Operation Error
7
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• The device specified by S or D exceeds the range of the corresponding device. 8
(For the Universal model QCPU, LCPU.) (Error code: 4101)

6.8.5 Rotary table shortest direction control (ROTC)

6.8 Other Convenient Instructions

6-159
 ROTC

Program Example
(1) The following program deposits the item at section D2 on a 10-division rotary table at the
station at section D1, and the two sections ahead and behind this determine the rotation
direction and control speed of the motor when the table is being rotated at low speed.
[Ladder Mode] [List Mode]
Step Instruction Device

Station No. 0

0 point detection
X002

9 8
0 7
Part
X000
6
1 Detection
switch Forward
rotation 5
2 X001
4 Rotary table
3
Station No. 1

6-160
 RAMP

6.8.6 Ramp signal (RAMP)

RAMP
1
High
2
Basic performance Process Redundant Universal LCPU

3
Command
RAMP RAMP n1 n2 D1 n3 D2

4
n1 : Initial value (BIN 16 bits)
n2 : Final value (BIN 16 bits)

D1 : D1 +0 : Present value (BIN 16 bits) 4

D1 +1 : Number of executions (BIN 16 bits)
n3 : Number of shifts (BIN 16 bits)

D2 : D2 +0 : Completion device (bits) 6

D2 +1 : Bit for selecting data retaining at completion (bit)

Setting Internal Devices J \ Constants

Data Bit Word
R, ZR
Bit Word
U \G Zn
K, H
Other
7
n1 ––

n2 ––

D1 –– –– 8
n3 ––

D2 –– –– ––

6.8.6 Ramp signal (RAMP)

6.8 Other Convenient Instructions
Function
(1) When the execution command is ON, the following processing is executed.
• Shifts from the value specified by n1 to the value specified by n2 in the number of times
specified by n3.
• For n3, designate the number of scans (number of shifts) required for shift from n1 to n2.
No operation if other than 0<n3<32768.
• The system uses D1 +1 to store the number of times the instruction has been executed.
• The value of one variation (one scan) is obtained by the expression below:
(Value specified by n2) (Value specified by n1)
Value of one variation (one scan)
(Value specified by n3)

Example 0 is varied to 350 in seven scans as shown below.

Value stored in 300 (7)
D1 + 0 (Present value) 250 (6)
200
150 (5) Value specified by n2 (350)
(4)
Value specified by n1 (0) 100
(3)
50 (2) Value stored in D1 + 1
(1)
(0) (Number of execution times)

Number of shifts (7) specified by n3

When the calculated one variation is indivisible, compensation is made to achieve the value
specified in n2 by the number of shifts specified in n3.
Hence, a linear ramp may not be made.

6-161
 RAMP

(2) If the scan is performed for the number of moves specified by n3, the complete device
specified by D2 +0 is turned ON.
The ON/OFF status of the completion device and the contents of D1 +0 are determined by
the ON/OFF status of the device designated by D2 +1.
• When D2 +1 is OFF, +0 will go OFF at the next scan, and the RAMP instruction will begin a
new move operation from the value currently at D2 +0.
• When D2 +1 is ON, D2 +0 will remain ON, and the contents of D1 +0 will not change.
(3) When the command is turned OFF during the execution of this instruction, the contents of
D1 +0 will not change following this.

When the command goes ON again, the RAMP instruction will begin a new move from the
present value at +0.
(4) Do not change the specified values in n1 and n2 before the completion device specified in
D2 +0 turns ON.

Since the same expression is used every scan to calculate the value stored in D1 +1,
changing n1/n2 may cause a sudden variation.

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• The device specified by D1 or D2 exceeds the range of the corresponding device.
(For the Universal model QCPU, LCPU.) (Error code: 4101)

Caution
(1) When the digit specification of bit device is made to D1 , the digit specification of bit device
can only be used when the following condition is met.
• Specification of digits: K8

6-162
 RAMP

Program Example
1
(1) The following program changes the contents of D0 from 10 to 100 in a total of 6 scans, and
saves the contents of D0 when the move has been completed.
[Ladder Mode] [List Mode] 2
Step Instruction Device

4
[Timing Chart]

4
ON

X0 OFF

D0 10 25 40 55 70 85 100
D1 0 1 2 3 4 5 6
6
1scan 1scan 1scan 1scan 1scan 1scan
ON

7
M0 OFF

ON

M1 OFF

6.8.6 Ramp signal (RAMP)

6.8 Other Convenient Instructions

6-163
 SPD

6.8.7 Pulse density measurement (SPD)

SPD

High
Basic performance Process Redundant Universal LCPU

Command
SPD SPD S n D

S : Pulse input (bits)

n : Measurement time (unit: ms) (BIN 16 bits)

D : Head number of the devices where the measurement result will be stored (BIN 16 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S (Only X) –– –– ––

n *1 *1 ––

D –– *1 –– ––
*1: Local devices and the file registers set for individual programs cannot be used.

Function
(1) The number of turning OFF ON input of the device specified by S is counted for just the
amount of time specified by n, and the count results are stored in the device specified by D .

Start of measurement
n [ms] n [ms]

ON
Execution command OFF

ON
S OFF

Measurement result is stored at (D) Measurement result is stored at (D)

(2) When measurement directed by the SPD instruction has been completed, measurement is
done again from 0.
Turn OFF the execution command to stop the measurement directed by the SPD instruction.

6-164
 SPD

1. With the SPD instruction, the argument device data is registered in the work 1
area of the CPU module and counting operation is processed as a system
interrupt. (The device data registered in the work area is cleared by turning the
execution command OFF, or turning the STOP/RUN switch STOP RUN.) For 2
this reason, the pulses that can be counted must have longer ON and OFF
times than the interrupt interval of the CPU module. The interrupt interval of
individual modules is shown below: 3
CPU Module Type Name Interrupt Interval
High Performance model QCPU, Process CPU,
Universal model QCPU, LCPU
1 ms
4
2. • When the High Performance model QCPU or Process CPU is used:
The instruction is not processed when n = 0.
3. The SPD instruction can be used as many as 6 times within all the programs
4
being executed. The seventh and the subsequent SPD instructions are not
processed.
4. While the measurement is in execution (while the command input is ON) by the 6
SPD instruction, the setting value cannot be changed. Turn OFF the command
input before changing the setting value.
7

Operation Error 8
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• The device specified by S exceeds the range of the corresponding device.

6.8.7 Pulse density measurement (SPD)

6.8 Other Convenient Instructions
(For the Universal model QCPU, LCPU.) (Error code: 4101)

Program Example
(1) The following program measures the pulses input to X0 for a period of 500 ms when X10
goes ON, and stores the result at D0.
[Ladder Mode] [List Mode]

Step Instruction Device

6-165
 PLSY

6.8.8 Fixed cycle pulse output (PLSY)

PLSY

High
Basic performance Process Redundant Universal LCPU

Command
PLSY PLSY n1 n2 D

n1 : Frequency or the number of the device where frequency is stored (BIN 16 bits)
n2 : Outputs count or the number of the device where the outputs count is stored (BIN 16 bits)

D : Number of the device to which pulses are output (bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

n1 ––

n2 ––

D *1 –– ––
*1: Only output (Y) can be used.

Function
(1) Outputs a pulse at a frequency designated by n1 the number of times designated by n2, to
the output module with the output signal (Y) designated by D .
(2) Frequencies between 1 to 100 Hz can be designated by n1.
If n1 is other than 1 to 100 Hz, the PLSY instruction will not be executed.
(3) The number of outputs that can be designated by n2 is between 0 to 65535 (0000H to
FFFFH).
If n2 is set to "0", pulses are continuously output.
(4) Only an output number corresponding to the output module can be designated for pulse
output at D .
(5) Pulse output commences with the command leading edge of the PLSY instruction.
Pulse output is suspended when the PLSY instruction command goes OFF.

6-166
 PLSY

1. With the PLSY instruction, the argument device data is registered in the work 1
area of the CPU module and counting operation is processed as a system
interrupt. (The device data registered in the work area is cleared by turning the
execution command OFF, or turning the STOP/RUN switch STOP RUN.) For 2
this reason, the pulses that can be output must have longer ON and OFF times
than the interrupt interval of the CPU module. The interrupt interval of individual
modules is shown below: 3
CPU Module Type Name Interrupt Interval
High Performance model QCPU, Process CPU,
Universal model QCPU, LCPU
1 ms
4
2. Do not change the argument for the PLSY instruction during pulse output
directed by the PLSY instruction (while the execution command is ON). To
change the argument, turn OFF the execution command.
4
3. The PLSY instruction can be used only once in all programs executed by the
CPU module. The second and the subsequent PLSY instructions are not
processed. 6

7
Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0. 8
• The device specified by D exceeds the range of the corresponding device.
(For the Universal model QCPU, LCPU.) (Error code: 4101)

6.8.8 Fixed cycle pulse output (PLSY)

6.8 Other Convenient Instructions
Program Example
(1) The following program outputs a 10 Hz pulse 5 times to Y20 when X0 is ON.
[Ladder Mode] [List Mode]

Step Instruction Device

6-167
 PWM

6.8.9 Pulse width modulation (PWM)

PWM

High
Basic performance Process Redundant Universal LCPU

Command
PWM PWM n1 n2 D

n1 : ON time or the number of the device where the ON time is stored (BIN 16 bits)
n2 : Frequency or the number of the device where the frequency is stored (BIN 16 bits)

D : Number of the device to which pulses are output (bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

n1 ––

n2 ––

D *1 –– ––
*1: Only output (Y) can be used.

Function
(1) Outputs the pulse of the cycle set by n2, for the amount of time ON designated by n1, to the
output module designated by D .

n1

n2

(2) The setting ranges for n1 and n2 are shown below:

CPU Module Type Name Setting Range for n1 and n2 [ms] *2
High Performance model QCPU, Process CPU,
1 to 65535 (0001H to FFFFH)
Universal model QCPU, LCPU

*2: The value specified by n1 should be less than the value specified by n2.

6-168
 PWM

1. With the PWM instruction, the argument device data is registered in the work 1
area of the CPU module and counting operation is processed as a system
interrupt. (The device data registered in the work area is cleared by turning the
execution command OFF, or turning the STOP/RUN switch STOP RUN.) The 2
interrupt interval of individual modules is shown below:
CPU Module Type Name Interrupt Interval of n1, n2
High Performance model QCPU, Process CPU,
3
1 ms
Universal model QCPU, LCPU

For this reason, the PWM instruction can be used only once within all the 4
programs being executed by the CPU module.
2. The instruction is not processed in the following cases:
• When both n1 and n2 are 0
• When n1 n2
4
• When the PWM instruction is executed twice or more.
3. Do not change the argument for the PWM instruction during pulse output
directed by the PWM instruction (while the execution command is ON). To
6
change the argument, turn OFF the execution command.

7
Operation Error
8
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• The device specified by D exceeds the range of the corresponding device.
(For the Universal model QCPU, LCPU.) (Error code: 4101)

6.8.9 Pulse width modulation (PWM)

6.8 Other Convenient Instructions
Program Example
(1) The following program outputs a 100 ms pulse once each second to Y20 when X0 is ON.
[Ladder Mode] [List Mode]
Step Instruction Device

6-169
 MTR

6.8.10 Matrix input (MTR)

MTR

High
Basic performance Process Redundant Universal LCPU

Command
MTR MTR S D1 D2 n

S : Head input device (bits)

D1 : Head output device (bits)

D2 : Head number of the devices where matrix input data will be stored (bits)
n : Number of input rows (BIN 16 bit)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S (Only X) –– ––

D1 (Only Y) –– ––

D2 –– ––

n ––

Function
(1) It reads the input from 16 points n-rows starting from the input number designated by S ,
then stores fetched input data from the device designated by D2 onward.
(2) One row (16 points) can be fetched in 1 scan.
(3) Fetching from the first to the n th row is repeated.
(4) The first through the 16th points store the first row of data and the next 16 points store the
second row of data at the devices following the device designated by D2 .
For this reason, the space of 16 n points from the device designated by D2 are occupied
by the MTR instruction.

(5) D1 is the output needed to select the row which will be fetched, and the system automatically

turns it ON and OFF.

It uses the n points from the device designated by D1 .

(6) Only device numbers divisible by 16 can be designated for S , D1 and D2 .

(7) For n, a value in the range from 2 to 8 can be assigned.
(8) No processing is performed in the following cases.
• The device number designated by S , D1 , or D2 is not divisible by 16.
• The device designated by S is outside the actual input range.
• The device designated by D1 is outside the actual output range.
• The space 16 n points following the device designated by D2 exceeds the relevant
device range.
• The value for n is not between 2 and 8.

6-170
 MTR

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The device other than the input (X) was specified at S . (Error code: 4101)
2
• The device other than the output (Y) was specified at D1 . (Error code: 4101)
3
Program Example
(1) The following program fetches, when X0 is turned ON, the 16 points 3 matrix starting from 4
X10, and stores the matrix into the area starting from M0.
[Ladder Mode] [List Mode]
Step Instruction Device
4

6
[Operation]
3rd row 7

Y20 Y21 Y22

M32

M33

M34

M35

M36

M37

M38

M39

M40

M41

M42

M43

M44

M45

M46

M47
8
X010 X011 X012 X013 X014 X015 X016 X017 X018 X019 X01A X01B X01C X01D X01E X01F
2nd row
M16

M17

M18

M19

M20

M21

M22

M23

M24

M25

M26

M27

M28

M29

M30

M31

6.8.10 Matrix input (MTR)

6.8 Other Convenient Instructions
X010 X011 X012 X013 X014 X015 X016 X017 X018 X019 X01A X01B X01C X01D X01E X01F
1st row
M10

M11

M12

M13

M14

M15
M0

M1

M2

M3

M4

M5

M6

M7

M8

M9

X010 X011 X012 X013 X014 X015 X016 X017 X018 X019 X01A X01B X01C X01D X01E X01F

Caution
(1) Note that the MTR instruction directly operates on actual input and output.
The output D1 that had been turned ON by the MTR instruction does not turn OFF when the
MTR command turns OFF.
Turn OFF the specified output D1 in the sequence program.
(2) The MTR instruction execution interval must be longer than the total of response time of
input and output modules.
If the set interval is shorter than the value indicated above, an input cannot be read correctly.
If the scan time in a sequence program is short, select the constant scan and set the scan
time longer than the total of response time.

6-171
MEMO

6-172
7
7
APPLICATION
INSTRUCTIONS 7

Reference
Category Processing Details
section 7
Logical operations such as logical sum, logical product,
Logical operation instructions Section 7.1
etc.
Rotation instruction Rotation of designated data Section 7.2 7
Shift instruction Shift of designated data Section 7.3
Bit processing instructions Sets and resets bit data; bit extraction Section 7.4
Data processing including data searching, sorting,
Data processing instructions Section 7.5
decoding and encoding
Repeated operation, subroutine program calls, index
Structure creation instructions Section 7.6
modification in ladder units
Data Table Operation
Data table read/write Section 7.7
Instructions
Buffer memory access Read/write from/to the buffer memory of intelligent function
Section 7.8
instruction modules
Character code outputs to external devices and displays
Display instructions Section 7.9
on indicators
Debugging and failure
Check, status latch, sampling trace, program trace Section 7.10
diagnosis instructions
Character string processing
Character string (ASCII code data) processing Section 7.11
instructions
BCD real number and floating point real number
Special function instructions Section 7.12
processing
Data control instructions Output value controls based on input data range checks Section 7.13
File register switching
Sets file registers; switches block numbers Section 7.14
instructions
Reading, writing, addition, subtraction, and conversion of
Clock instructions clock values; comparison between the clock values; and Section 7.15
comparison between the date values
Reading, addition, and subtraction of clock values up to
Expansion clock instruction Section 7.16
millisecond
Program control instructions Instructions to switch program execution conditions Section 7.17
Instructions that do not fit in the above categories, such as
Other instructions watchdog timer reset instructions and timing clock Section 7.18
instructions

7-1
 7.1 Logical operation instructions
(1) The logical operation instructions perform logical sum, logical product or other logical
operations in 1-bit units.
Formula for Example
Category Processing Details
Operation A B Y
0 0 0
Logical product Becomes 1 only when both input A and 0 1 0
Y A·B
(AND) input B are 1; otherwise, is 0 1 0 0
1 1 1
0 0 0
Logical sum Becomes 0 only when both input A and 0 1 1
Y A+B
(OR) input B are 0; otherwise, is 1 1 0 1
1 1 1
0 0 0
Exclusive OR Becomes 0 if input A and input B are 0 1 1
(XOR) equal; otherwise, is 1 Y A·B+A·B 1 0 1
1 1 0
0 0 1
NON exclusive
Becomes 1 if input A and input B are 0 1 0
logical sum
equal; otherwise, is 0 Y (A + B)(A + B) 1 0 0
(XNR)
1 1 1

7-2
 WAND(P),DAND(P)

7.1.1 Logical products with 16-bit and 32-bit data

(WAND(P),DAND(P)) 1
WAND(P),DAND(P)

Basic High
performance Process Redundant Universal LCPU
2

When two data are set ( D S D ,( D +1, D ) ( S +1, S ) ( D +1, D )) 3

4
indicates an instruction symbol of WAND/DAND.

Command
WAND,DAND S D
6
Command
P S D
WANDP,DANDP
6
S : Data for a logical product operation or the head number of the devices where the data is stored (BIN 16/32 bits)
D : Head number of the devices where the logical product operation result will be stored (BIN 16/32 bits)
7
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S –– 8
D –– ––

Function

7.1.1 Logical products with 16-bit and 32-bit data (WAND(P),DAND(P))

7.1 Logical operation instructions
WAND
(1) A logical product operation is conducted for each bit of the 16-bit data of the device
designated at D and the 16-bit data of the device designated at S , and the results are
stored in the device designated at D .
b15 b8 b7 b0
D 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1
AND
b15 b8 b7 b0
S 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0

b15 b8 b7 b0
D 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0

(2) When bit devices are designated, the bit devices after the points designated as digits are
regarded as "0" in the operation. (See Program Example (2))

7-3
 WAND(P),DAND(P)

DAND
(1) Conducts a logical product operation on each bit of the 32-bit data for the device designated
by S1 and the 32-bit data for the device designated by S2 , and stores the results at the
device designated by D .
D +1 D
b31 b16 b15 b0
D 1 1 1 1 1 1 0 0 1 1 0 0 1 1

AND
S +1 S
b31 b16 b15 b0
S 0 1 0 1 1 0 0 1 0 1 0 0 0 1

D +1 D
b31 b16 b15 b0
D 0 1 0 1 1 0 0 0 0 1 0 0 0 1

(2) When bit devices are designated, the bit devices below the points designated as digits are
regarded as "0" in the operation. (See Program Example (2))

Operation Error
(1) There are no operation errors associated with the WAND(P) or DAND(P) instruction.

Program Example
(1) The following program masks the digit in the 10s place of the 4-digit BCD value at D10
(second digit from the end) to 0 when XA is turned ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
b15 b8 b7 b0
D10 BCD1234 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0
AND
b15 b8 b7 b0
HFF0F 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1

b15 b8 b7 b0
D10 BCD1204 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0

7-4
 WAND(P),DAND(P)

(2) The following program performs a logical product operation on the data at D99 and D100,
and the 24-bit data between X30 and X47 when X8 is ON, and stores the results at D99 and
D100.
[Ladder Mode] [List Mode]
1
Step Instruction Device

[Operation] 3
b31 b30b29 b28 b27 b26 b25b24 b23 b22 b3 b2 b1 b0
D100, D99 1 1 1 1 1 1 1 1 1 1 1 1 1 1
AND
X47X46 X33X32X31X30 4
X47 X30 0 0 0 0 0 0 0 0 1 1 0 1 0 1

Regarded as 0s.
6
b31 b30 b29 b28 b27b26 b25b24 b23 b22 b3 b2 b1 b0
D100, D99 0 0 0 0 0 0 0 0 1 1 0 1 0 1

7.1.1 Logical products with 16-bit and 32-bit data (WAND(P),DAND(P))

7.1 Logical operation instructions

7-5
 WAND(P),DAND(P)

When three data are set ( S1 S2 D , ( S1 +1, S1 ) ( S2 +1, S2 ) ( D +1, D ))

indicates an instruction symbol of WAND/DAND.

Command
WAND,DAND S1 S2 D

Command
WANDP,DANDP P S1 S2 D

S1 , S2 : Data for a logical product operation or the head number of the devices where the data is stored (BIN 16/32 bits)
D : Head number of the devices where the logical product operation result will be stored (BIN 16/32 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S1 ––

S2 ––

D –– ––

Function
WAND
(1) A logical product operation is conducted for each bit of the 16-bit data of the device
designated at S1 and the 16-bit data of the device designated at S2 , and the results are
stored in the device designated at D .
b15 b8 b7 b0
S1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1
AND
b15 b8 b7 b0
S2 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0

b15 b8 b7 b0
D 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0

(2) For bit devices, the bit devices after the points designated by digit specification are regarded as "0" in
the operation. (See Program Examples (1) and (2))
DAND
(1) Conducts a logical product operation on each bit of the 32-bit data for the device designated
by S1 and the 32-bit data for the device designated by S2 , and stores the results at the
device designated by D .
S1 + 1 S1
b31 b16 b15 b0
S1 1 1 1 1 1 1 0 0 1 1 0 0 1 1

AND
S2 + 1 S2
b31 b16 b15 b0
S2 0 1 0 1 1 0 0 1 0 1 0 0 0 1

D+1 D
b31 b16 b15 b0
D 0 1 0 1 1 0 0 0 0 1 0 0 0 1

(2) For bit devices, the bit devices after the points designated by digit specification are regarded

7-6
 WAND(P),DAND(P)

as "0" in the operation. (See Program Example (3))

Operation Error 1
(1) There are no operation errors associated with the WAND(P) or DAND(P) instruction.
2
Program Example
(1) The following program performs a logical product operation on the data from X10 to X1B and 3
the data at D33 when XA is ON, and stores the results at D40.
[Ladder Mode] [List Mode]
Step Instruction Device
4

6
[Operation]

6
X1B X18X17 X13 X10
X1B to X10 0 0 0 0 1 0 0 1 0 0 1 1 1 1 0 0
Regarded as 0s.
AND

7
b15 b8 b7 b0
D33 0 1 0 1 1 1 0 1 1 1 1 1 0 0 0 0

b15 b8 b7 b0
D40 0 0 0 0 1 0 0 1 0 0 1 1 0 0 0 0 8
(2) The following program performs a logical product operation on the data at D10 and at D20
when X1C is ON, and stores the results from M0 to M11.
[Ladder Mode] [List Mode]

7.1.1 Logical products with 16-bit and 32-bit data (WAND(P),DAND(P))

7.1 Logical operation instructions
Step Instruction Device

[Operation]
b15 b8 b7 b0
D10 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0
AND
b15 b8 b7 b0
D20 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1

M15 M12 M11 M8 M7 M4 M3 M0

1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0

Not changed

7-7
 WAND(P),DAND(P)

(3) The following program masks the digit in the hundred-thousands place of the 8-digit BCD
value at D10 and D11 (sixth digit from the end) to 0 when XA is ON, and outputs the results
to from Y10 to Y2B.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
b31 b16b15 b0
D10, D11 (BCD12345678) 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0
AND
b31 b16b15 b0
H FF0FFFFF 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Y2F Y2C Y2B Y28 Y27 Y24 Y23 Y20 Y1F Y1CY1B Y18 Y17 Y14 Y13 Y10
Y2B to Y10 1 1 1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0
Not changed

7-8
 BKAND(P)

7.1.2 Block logical products (BKAND(P))

BKAND(P)
1
Basic High
performance Process Redundant Universal LCPU
2

3
Command
BKAND BKAND S1 S2 D n

Command 4
BKANDP S1 S2 D n
BKANDP

6
S1 *1 : Head number of the devices where data on which a logical operation will be conducted is stored
(BIN 16 bits)

*1 : Data for a logical operation or head number of the devices where the data for the logical operation is
6
S2

stored (BIN 16 bits)

D *1 : Head number of the devices where the operation result will be stored (BIN 16 bits)
n : Number of operation data blocks (BIN 16 bits)

Setting Internal Devices

R, ZR
J \
U \G Zn
Constants
Other
7
Data Bit Word Bit Word K, H

S1 *1 –– –– –– ––

S2 *1 –– –– –– 8
D *1 –– –– –– ––

n ––

*1: The same device number can be specified for S1 and D or S2 and D .

7.1.2 Block logical products (BKAND(P))

7.1 Logical operation instructions
Function
(1) Performs a logical product operation on the data located in the n points from the device
designated by S1 , and the data located in the n points from the device designated by S2 , and
stores the results into the area starting from the device designated by D .
b15 b8 b7 b0 b15 b8 b7 b0
S1 0011001100110011 S2 0011110000111100
S1 + 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 S2 + 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
S1 + 2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 S2 + 2 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
n n
AND

S1 +(n 2) 0101010101010101 S2 +(n 2) 1111111111111111

S1 +(n 1) 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 S2 +(n 1) 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0

b15 b8b7 b0
D 0011000000110000
D +1 1111000000000000
D +2 0000000011111111
n

D +(n 2) 0101010101010101
D +(n 1) 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0

7-9
 BKAND(P)

(2) The constant designated by S2 can be between -32768 and 32767 (BIN 16-bit data).
b15 b8 b7 b0
S1 0011001100110011
S1 + 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1
S1 + 2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 b15 b8b7 b0
n BKAND S2 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1

S1 + (n 2) 0101010101010101
S1 + (n 1) 1111000011110000

b15 b8 b7 b0
D 0011001100000011
D +1 1111000000001111
D +2 0000000000001111
n

D + (n 2) 0101010100000101
D + (n 1) 1111000000000000

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The n-bit range from the S1 , S2 , or D device exceeds the range of that device.
(Error code: 4101)

• The device range for n points starting from the device designated by S1 overlaps with the
device range for n points starting from the device designated by D .
(except when the same device is specified for S1 and D ) (Error code: 4101)

• The device range for n points starting from the device designated by S2 overlaps with the
device range for n points starting from the device designated by D .
(except when the same device is specified for S2 and D ) (Error code: 4101)

Program Example
(1) The following program performs a logical product operation on the data stored at D100 to
D102 and the data stored at R0 to R2 when X20 is turned ON, and stores the operation
result into the area starting from D200.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
b15 b8 b7 b0 b15 b8b7 b0
D100 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 R0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
BKAND
D101 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 R1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0
D102 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R2 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1

b15 b8 b7 b0
D200 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 D0 3
D201 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0
D202 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

7-10
 WOR(P),DOR(P)

7.1.3 Logical sums of 16-bit and 32-bit data (WOR(P),DOR(P))

WOR(P),DOR(P)
1
Basic High
performance Process Redundant Universal LCPU
2
When two data are set ( D S D ,( D +1, D ) ( S +1, S ) ( D +1, D ))
3

indicates an instruction symbol of WOR/DOR.

4
Command
WOR, DOR S D

Command 6
P S D
WORP, DORP

6
S : Data for a logical sum operation or head number of the devices where the data is stored (BIN 16/32 bits)
D : Head number of the devices where the logical sum operation result will be stored (BIN 16/32 bits)

Setting
Data
Internal Devices
R, ZR
J \
U \G Zn
Constants
K, H
Other 7
Bit Word Bit Word

S ––

D –– –– 8

Function

7.1.3 Logical sums of 16-bit and 32-bit data (WOR(P),DOR(P))

7.1 Logical operation instructions
WOR
(1) Conducts a logical sum operation on each bit of the 16-bit data of the device designated by
D and the 16-bit data of the device designated by S , and stores the results at the device
designated by D .
b15 b8 b7 b0
D 0 1 0 1 1 1 1 1 0 0 0 0 0 0 1 1
OR
b15 b8 b7 b0
S 1 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0

b15 b8 b7 b0
D 1 1 0 1 1 1 1 1 1 1 0 0 1 1 1 1

(2) For bit devices, the bit devices after the points designated by digit specification are regarded
as "0" in the operation.

7-11
 WOR(P),DOR(P)

DOR
(1) Conducts a logical sum operation on each bit of the 32-bit data of the device designated by
D and the 32-bit data of the device designated by S , and stores the results at the device
designated by D .
D +1 D
b31 b16 b15 b0
D 1 1 1 1 0 0 0 0 0 0 0 0 1 1

OR
S +1 S
b31 b16 b15 b0
S 1 0 0 1 0 0 0 1 1 1 0 0 1 1

D +1 D
b31 b16 b15 b0
D 1 1 1 1 0 0 0 1 1 1 0 0 1 1

(2) For bit devices, the bit devices after the points designated by digit specification are regarded
as "0" in the operation.

Operation Error
(1) There are no operation errors associated with the WOR(P) or DOR(P) instructions.

Program Example
(1) The following program performs a logical sum operation on the data at D10 and D20 when
XA is turned ON, and stores the results at D10.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
b15 b8 b7 b0
D10 1 1 0 0 1 1 0 0 1 1 1 1 0 0 0 0
OR
b15 b8 b7 b0
D20 0 0 0 0 1 0 1 1 1 0 0 1 0 0 0 1

b15 b8 b7 b0
D10 1 1 0 0 1 1 1 1 1 1 1 1 0 0 0 1

7-12
 WOR(P),DOR(P)

(2) The following program performs a logical sum operation on the 32-bit data from X0 to X1F,
and on the hexadecimal value FF00FF00H when XB is turned ON, and stores the results at
D66 and D67. 1
[Ladder Mode] [List Mode]
Step Instruction Device
2

[Operation]
4
S +1 S
X1F X1C X10 XF X3 X0
X1F X0 1 0 1 0 0 0 0 0 0 0 1 0 1 0
6
OR
D +1 D
b31 b16 b15 b0
FF00FF00H 1 1 1 1 0 0 0 1 1 1 0 0 0 0 6

D +1 D
b31 b16 b15 b0 7
D67,D66 1 1 1 1 0 0 0 1 1 1 1 0 1 0

7.1.3 Logical sums of 16-bit and 32-bit data (WOR(P),DOR(P))

7.1 Logical operation instructions

7-13
 WOR(P),DOR(P)

When three data are set ( S1 S2 D , ( S1 +1, S1 ) ( S2 +1, S2 ) ( D +1, D ))

indicates an instruction symbol of WOR/DOR.

Command
WOR, DOR S1 S2 D

Command
WORP, DORP P S1 S2 D

S1 , S2 : Data for a logical sum operation or head number of the devices where the data is stored (BIN 16/32 bits)

D : Head number of the devices where the logical sum operation result will be stored (BIN 16/32 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S1 ––

S2 ––

D –– ––

Function
WOR
(1) Conducts a logical sum operation on each bit of the 16-bit data of the device designated by
S1 and the 16-bit data of the device designated by S2 , and stores the results at the device
designated by D .
b15 b8 b7 b0
S1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0
OR
b15 b8 b7 b0
S2 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 1

b15 b8 b7 b0
D 1 1 0 0 1 1 0 0 1 1 1 1 0 0 1 1

(2) For bit devices, the bit devices after the points designated by digit specification are regarded
as "0" in the operation. (See Program Example (1))

7-14
 WOR(P),DOR(P)

DOR
(1) Conducts a logical sum operation on each bit of the 32-bit data of the device designated by
S1 and the 32-bit data of the device designated by S2 , and stores the results at the device 1
designated by D .
S1 + 1 S1
2
b31 b16 b15 b0
S1 0 0 1 1 0 0 1 1 0 0 1 1 0 0

S2 + 1
OR
S2
3
b31 b16 b15 b0
S2 0 0 1 0 1 1 0 0 0 0 1 1 1 1
4
D +1 D
b31 b0
6
b16 b15
D 0 0 1 1 1 1 1 1 0 0 1 1 1 1

(2) When bit devices are designated, the bit devices below the points designated as digits are
regarded as "0" in the operation. (See Program Example (2)) 6

Operation Error 7
(1) There are no operation errors associated with the WOR(P) or DOR(P) instructions.
8
Program Example
(1) The following program performs a logical sum operation on the data from X10 to X1B, and
the data at D33, and stores the result at Y30 to Y3B when XA is ON.

7.1.3 Logical sums of 16-bit and 32-bit data (WOR(P),DOR(P))

7.1 Logical operation instructions
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
X1B X18X17 X14X13 X10
X1B to X10 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0

Regarded as 0s.
OR
b15 b8 B7 b0
D33 1 1 1 1 1 0 0 1 1 0 0 1 0 0 1 1

Y3B Y38Y37 Y34Y33 Y30

Y3B to Y30 1 0 0 1 1 1 0 1 1 0 1 1 0 0 1 1

Not changed

7-15
 WOR(P),DOR(P)

(2) The following program performs a logical sum operation on the 32-bit data at D0 and D1,
and the 24-bit data from X20 to X37, and stores the results at D23 and D24 when M8 is ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
S +1 S
b31 b28 b27 b24 b23 b22b21 b3 b2 b1 b0
D1, D0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 1
OR
X37X36X35 X23X22X21X20
X37 to X20 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1

Regarded as 0s.

D +1 D
b31 b16 b15 b0
D24, D23 1 1 1 1 0 0 0 0 1 1 0 1 1 1 1

7-16
 BKOR(P)

7.1.4 Block logical sum operations (BKOR(P))

BKOR(P)
1
Basic High
performance Process Redundant Universal LCPU
2

3
Command
BKOR BKOR S1 S2 D n

Command 4
BKORP S1 S2 D n
BKORP

6
S1 *1 : Head number of the devices where data on which a logical operation will be conducted is stored
(BIN 16 bits)

*1 : Data for a logical operation or head number of the devices where the data for the logical operation is stored
6
S2

(BIN 16 bits)
D *1 : Head number of the devices where the operation result will be stored (BIN 16 bits)
n : Number of operation data blocks (BIN 16 bits)

Setting Internal Devices

R, ZR
J \
U \G Zn
Constants
Other
7
Data Bit Word Bit Word K, H

S1 *1 –– –– –– ––

S2 *1 –– –– –– 8
D *1 –– –– –– ––

n ––

*1: The same device number can be specified for S1 and D or S2 and D .

7.1.4 Block logical sum operations (BKOR(P))

7.1 Logical operation instructions
Function
(1) Performs a logical sum operation on the data located in the n points from the device
designated by S1 , and the data located in the n points from the device designated by S2 , and
stores the results into the area starting from the device designated by D .

b15 b8 b7 b0 b15 b8 b7 b0
S1 0000111100001111 S2 0000111111000011
S1 + 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 S2 + 1 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1
S1 + 2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 S2 + 2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0
n n
OR

S1 +(n 2) 0000111111110000 S2 +(n 2) 0011001100110011

S1 +(n 1) 1111111100000000 S2 +(n 1) 0011110000001111

b15 b8 b7 b0
D 0000111111001111
D +1 1100110011111111
D +2 0000111111111111
n

D +(n 2) 0011111111110011
D +(n 1) 1111111100001111

7-17
 BKOR(P)

(2) The constant designated by S2 can be between 32768 and 32767 (BIN 16-bit data).
b15 b8 b7 b0
S1 0011110011000011
S1 + 1 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0
S1 + 2 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 b15 b8 b7 b0
n OR S2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0

S1 +(n 2) 0000111100001111
S1 +(n 1) 1100001111000011

b15 b8 b7 b0
D 0011111111110011
D +1 0000111111111010
D +2 1010111111111010
n

D +(n 2) 0000111111111111
D +(n 1) 1100111111110011

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The n-bit range from the S1 , S2 , or D device exceeds the range of that device.
(Error code: 4101)
• The device range for n points starting from the device designated by S1 overlaps with the
device range for n points starting from the device designated by D . (except when the same
device is specified for S1 and D ) (Error code: 4101)
• The device range for n points starting from the device designated by S2 overlaps with the
device range for n points starting from the device designated by D . (except when the same
device is specified for S2 and D ) (Error code: 4101)

Program Example
(1) The following program performs a logical sum operation on the data stored at D100 to D102
and the data stored at R0 to R2 when X20 is turned ON, and stores the operation result into
the area starting from D200.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]

b15 b8 b7 b0 b15 b8 b7 b0
D100 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 R0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0
OR
D101 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 R1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0
D102 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 R2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

b15 b8 b7 b0
D200 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0
D201 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1
D202 1 1 0 0 1 1 1 1 0 0 1 1 1 1 1 1 D0 3

7-18
 WXOR(P),DXOR(P)

7.1.5 16-bit and 32-bit exclusive OR operations

(WXOR(P),DXOR(P)) 1
WXOR(P),DXOR(P)

Basic High
performance Process Redundant Universal LCPU
2

When two data are set ( D S D ,( D +1, D ) ( S +1, S ) ( D +1, D )) 3

4
indicates an instruction symbol of WXOR/DXOR.

Command
WXOR, DXOR S D
6
Command
P S D
WXORP, DXOR
6
S : Data for an exclusive OR operation or head number of the devices where the data is stored (BIN 16/32 bits)
D : Head number of the devices where the exclusive OR operation result will be stored (BIN 16/32 bits)
7
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S –– 8
D –– ––

Function

7.1.5 16-bit and 32-bit exclusive OR operations (WXOR(P),DXOR(P))

7.1 Logical operation instructions
WXOR
(1) Conducts an exclusive OR operation on each bit of the 16-bit data of the device designated
by D and the 16-bit data of the device designated by S , and stores the results at the device
designated by D .
b15 b8 b7 b0
D 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
XOR
b15 b8 b7 b0
S 0 0 0 1 1 0 1 1 1 1 1 1 0 0 0 0

b15 b8 b7 b0
D 1 0 1 1 0 0 0 1 0 1 0 1 1 0 1 0

(2) For bit devices, the bit devices after the points designated by digit specification are regarded as
"0" in the operation.

7-19
 WXOR(P),DXOR(P)

DXOR
(1) Conducts an exclusive OR operation on each bit of the 32-bit data of the device designated
by D and the 32-bit data of the device designated by S , and stores the results at the device
designated by D .
D +1 D
b31 b16 b15 b0
D 0 1 0 1 0 1 0 1 0 1 0 1 0 1

XOR
S +1 S

b31 b16 b15 b0

S 0 1 1 0 0 1 1 0 1 0 0 1 1 0

D +1 D

b31 b16 b15 b0

D 0 0 1 1 0 0 1 1 1 1 0 0 1 1

(2) For bit devices, the bit devices after the points designated by digit specification are regarded as
"0" in the operation.

Operation Error
(1) There are no operation errors associated with the WXOR(P) or DXOR(P) instructions.

Program Example
(1) The following program performs an exclusive OR operation on the data at D10 and D20
when XA is ON, and stores the result at D10.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
b15 b8 b7 b0
D10 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
XOR
b15 b8 b7 b0
D20 0 0 1 1 1 0 0 1 0 0 1 1 1 0 0 1

b15 b8 b7 b0
D10 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0

7-20
 WXOR(P),DXOR(P)

(2) The following program compares the bit pattern of the 32-bit data from X20 to X3F with the
bit pattern of the data at D9 and D10 when X6 is ON, and stores the number of differing bits
at D16. 1
[Ladder Mode] [List Mode]
Step Instruction Device
2

3
[Operation]
S +1 S 4
X3F X3C X3B X38 X37 X34 X33 X30 X2F X2CX2B X28 X27 X24 X23 X20
X3F to X20 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

D +1
XOR
D
6
b31 b16 b15 b0
D10,D9 1 0 1 1 1 0 0 1 1 1 0 0 0 0 0 1 1 0 1 1 1 1 0 1 1 0 1 0 1 1 0 1
6
D +1 D

b31 b16 b15 b0

D10,D9 1 1 1 0 1 1 0 0 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 0 1 1 1 1 1 0 0 0 7

D16 17 8
Remark
See Section 7.5.2 for more information on the DSUMP instruction.

7.1.5 16-bit and 32-bit exclusive OR operations (WXOR(P),DXOR(P))

7.1 Logical operation instructions

7-21
 WXOR(P),DXOR(P)

When three data are set ( S1 S2 D ( S1 +1, S1 ) ( S2 +1, S2 ) ( D +1, D ))

indicates an instruction symbol of WXOR/DXOR.

Command
WXOR, DXOR S1 S2 D

Command
WXORP, DXORP P S1 S2 D

S1 , S2 : Data for an exclusive OR operation or head number of the devices where the data is stored
(BIN 16/32 bits)
D : Head number of the devices where the exclusive OR operation result will be stored (BIN 16/32 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S1 ––

S2 ––

D –– ––

Function
WXOR
(1) Conducts an exclusive OR operation on each bit of the 16-bit data of the device designated
by S1 and the 16-bit data of the device designated by S2 , and stores the results at the device
designated by D .
b15 b8 b7 b0
S1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0
XOR
b15 b8 b7 b0
S2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

b15 b8 b7 b0
D 0 1 0 1 1 0 1 0 1 0 1 0 0 1 0 1

(2) For bit devices, the bit devices after the points designated by digit specification are regarded
as "0" in the operation. (See Program Example (1))

7-22
 WXOR(P),DXOR(P)

DXOR
(1) Conducts an exclusive OR operation on each bit of the 32-bit data of the device designated 1
by S1 and the 32-bit data of the device designated by S2 , and stores the results at the device
designated by D .
S1 + 1 S1
2
b31 b16 b15 b0
S1 1 1 1 1 0 0 0 0 0 0 1 1 1 1

XOR
3
S2 + 1 S2
b31 b16 b15 b0
S2 1 1 1 1 1 0 1 0 1 0 1 1 0 0
4
D +1 D

D
b31 b16 b15 b0 6
0 0 0 0 1 0 1 0 1 0 0 0 1 1

(2) For bit devices, the bit devices after the points designated by digit specification are regarded
as "0" in the operation. 6

Operation Error
7
(1) There are no operation errors associated with the WXOR(P) or DXOR(P) instructions.

8
Program Example
(1) The following program conducts an exclusive OR operation on the data from X10 to X1B
and the data at D33 when X10 is ON, and outputs the result to Y30 to Y3B.

7.1.5 16-bit and 32-bit exclusive OR operations (WXOR(P),DXOR(P))

7.1 Logical operation instructions
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
X1B X18X17 X14X13 X10
X1B to X10 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1

Regarded as 0s.
XOR
b15 b8 b7 b0
D33 1 1 1 1 0 0 1 1 0 0 1 1 1 0 0 1

Y3B Y38Y37 Y34Y33 Y30

Y3B to Y30 0 1 1 0 0 1 1 0 0 1 1 0 1 1 0 0
Not changed

7-23
 WXOR(P),DXOR(P)

(2) The following program conducts an exclusive OR operation on the data at D20 and D21, and
the data at D30 and D31 when X10 is turned ON, and stores the results at D40 and D41.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
S1 + 1 S1
b31 b16 b15 b0
D21,D20 1 1 0 0 1 0 1 0 1 1 0 0 1 1

XOR
S2 + 1 S2
b31 b16 b15 b0
D31,D30 0 0 0 0 1 1 0 0 0 1 0 1 0 1

D +1 D
b31 b16 b15 b0
D41,D40 1 1 0 0 0 1 1 0 1 0 0 1 1 0

7-24
 BKXOR(P)

7.1.6 Block exclusive OR operations (BKXOR(P))

BKXOR(P)
1
Basic High
performance Process Redundant Universal LCPU
2

3
Command
BKXOR BKXOR S1 S2 D n

Command 4
BKXORP S1 S2 D n
BKXORP

6
S1 *1 : Head number of the devices where data on which a logical operation will be conducted is stored (BIN 16 bits)
S2 *1 : Data for a logical operation or head number of the devices where the data for the logical operation is stored
(BIN 16 bits)
D *1 : Head number of the devices where the operation result will be stored (BIN 16 bits)
6
n : Number of operation data blocks (BIN 16 bits)

Setting Internal Devices J \ Constants

Data Bit Word
R, ZR
Bit Word
U \G Zn
K, H
Other
7
S1 *1 –– –– –– ––

–– –– ––
8
S2 *1

D *1 –– –– –– ––

n ––

*1: The same device number can be specified for S1 and D or S2 and D .

7.1.6 Block exclusive OR operations (BKXOR(P))

7.1 Logical operation instructions
Function
(1) Performs an exclusive OR operation on the data located in the n points from the device
designated by S1 , and the data located in the n points from the device designated by S2 , and
stores the results into the area starting from the device designated by D .
b15 b8 b7 b0 b15 b8b7 b0
S1 0011001100000011 S2 0011110000111100
S1 + 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 S2 + 1 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0
S1 + 2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 S2 + 2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
n n
XOR

S1 +(n 2) 0000000011111111 S2 +(n 2) 1111111100001111

S1 +(n 1) 0000111111110000 S2 +(n 1) 0000111111111111

b15 b8 b7 b0
D 0000111100111111
D +1 1111000011000000
D +2 1111000000001111
n

D +(n 2) 1111111111110000
D +(n 1) 0000000000001111

7-25
 BKXOR(P)

(2) The constant designated by S2 can be between 32768 and 32767 (BIN 16-bit data).
b15 b8b7 b0
S1 1111111100000000
S1 + 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0
S1 + 2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 b15 b8b7 b0
n XOR S2 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

S1 +(n 2) 1111111100001111
S1 +(n 1) 0101010101010101

b15 b8b7 b0
D 0101010110101010
D +1 1010010101011010
D +2 1010101001010101
n

D +(n 2) 0101010110100101
D +(n 1) 1111111111111111

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The n-bit range from the S1 , S2 , or D device exceeds the range of that device.
(Error code: 4101)
• The device range for n points starting from the device designated by S1 overlaps with the
device range for n points starting from the device designated by D . (except when the
same device is specified for S1 and D ) (Error code: 4101)
• The device range for n points starting from the device designated by S2 overlaps with the
device range for n points starting from the device designated by D . (except when the
same device is specified for S2 and D ) (Error code: 4101)

Program Example
(1) The following program performs an exclusive OR operation on the data stored at D100 to
D102 and the data stored at R0 to R2 when X20 is turned ON, and stores the operation
result into the area starting from D200.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
b15 b8 b7 b0 b15 b8 b7 b0
D100 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 R0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
XOR
D101 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 R1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
D102 0 1 0 1 1 1 1 1 1 1 1 1 0 1 0 1 R2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0

b15 b8b7 b0
D200 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1
D201 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D0 3
D202 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 1

7-26
 WXNR(P),DXNR(P)

7.1.7 16-bit and 32-bit data exclusive NOR operations

(WXNR(P),DXNR(P)) 1
WXNR(P),DXNR(P)

Basic High
performance Process Redundant Universal LCPU
2

When two data are set ( D S D ,( D +1, D ) ( S +1, S ) ( D +1, D )) 3

4
indicates an instruction symbol of WXNR/DXNR.

Command
WXNR, DXNR S D 6
Command
P S D
WXNRP, DXNRP
6
S : Data for an exclusive NOR operation or head number of the devices where the data is stored (BIN 16/32 bits)
D : Head number of the devices where the exclusive NOR operation result will be stored (BIN 16/32 bits) 7
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S –– 8
D –– ––

Function

7.1.7 16-bit and 32-bit data exclusive NOR operations (WXNR(P),DXNR(P))

7.1 Logical operation instructions
WXNR
(1) Conducts an exclusive NOR operation on the 16-bit data of the device designated by D and
the 16-bit data of the device designated by S , and stores the results at the device
designated by D .
b15 b8 b7 b0
D 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1
XNR
b15 b8 b7 b0
S 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 0

b15 b8 b7 b0
D 1 0 1 0 0 1 0 1 0 1 0 1 0 0 0 0

(2) For bit devices, the bit devices after the points designated by digit specification are regarded as
"0" in the operation.

7-27
 WXNR(P),DXNR(P)

DXNR

(1) Conducts an exclusive NOR operation on the 32-bit data of the device designated by D and
the 32-bit data of the device designated by S , and stores the results at the device
designated by D .
D +1 D
b31 b16 b15 b0
D 1 1 0 0 0 0 0 0 0 0 0 0 1 1

XNR
S +1 S
b31 b16 b15 b0
S 1 1 1 1 0 0 0 0 1 1 1 1 0 0

D +1 D
b31 b16 b15 b0
D 1 1 0 0 1 1 1 1 0 0 0 0 0 0

(2) For bit devices, the bit devices after the points designated by digit specification are regarded as
"0" in the operation.

Operation Error
(1) There are no operation errors associated with the WXNR(P) or DXNR(P) instruction.

Program Example
(1) The following program compares the bit patterns of the 16-bit data located from X30 to X3F
with the bit patterns of the 16-bit data at D99 when XC is ON, and stores the number of
identical bit patterns at D7.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
X3F X3CX3B X38X37 X34X33 X30
X3F to X30 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
XNR
b15 b8 b7 b0
D99 1 1 0 0 1 0 0 1 1 0 1 0 1 0 1 1

b15 b8 b7 b0
D99 0 1 1 0 0 0 1 1 0 0 0 0 0 0 0 1

D7 5

7-28
 WXNR(P),DXNR(P)

(2) The following program compares the bit patterns of the 32-bit data located from X20 to X3F
with the bit patterns of the data at D16 and D17 when X6 is ON, and stores the number of
identical bit patterns at D18. 1
[Ladder Mode] [List Mode]
Step Instruction Device
2

[Operation]
S +1 S
4
X3F X3C X3B X38 X37 X34 X33 X30 X2F X2C X2B X28 X27 X24 X23 X20
X3F to X20 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

D +1
XOR
D
6
b31 b16 b15 b0
D17,D16 1 1 0 0 1 0 0 1 0 1 1 0 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 0 1 1

6
D +1 D

b31 b16b15 b0
D17,D16 0 1 1 0 0 0 1 1 1 1 0 0 0 1 1 0 1 0 0 1 0 1 1 0 0 0 1 1 0 0 0 1
7
D18 15

8
Remark
See 7.5.2 for more information on the SUMP/DSUMP instructions.

7.1.7 16-bit and 32-bit data exclusive NOR operations (WXNR(P),DXNR(P))

7.1 Logical operation instructions

7-29
 WXNR(P),DXNR(P)

When three data are set ( S1 S2 D , ( S1 +1, S1 ) ( S2 +1, S2 ) ( D +1, D ))

indicates an instruction symbol of WXNR/DXNR.

Command
WXNR, DXNR S1 S2 D

Command
WXNRP, DXNRP P S1 S2 D

S1 , S2 : Data for an exclusive NOR operation or head number of the devices where the data is stored (BIN 16/32 bits)

D : Head number of the devices where the exclusive NOR operation result will be stored (BIN 16/32 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S1 ––

S2 ––

D –– ––

Function
WXNR

(1) Conducts an exclusive NOR operation on the 16-bit data of the device designated by S1 and
the 16-bit data of the device designated by S2 , and stores the results at the device
designated by D .
b15 b8 b7 b0
S1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
XNR
b15 b8 b7 b0
S2 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1

b15 b8 b7 b0
D 0 0 1 1 0 0 1 1 0 0 1 1 1 1 0 0

(2) For bit devices, the bit devices after the points designated by digit specification are regarded as
"0" in the operation.

7-30
 WXNR(P),DXNR(P)

DXNR

(1) Conducts an exclusive NOR operation on the 32-bit data of the device designated by and
1
S1

the 32-bit data of the device designated by S2 , and stores the results at the device
designated by D .
S1 + 1 S1 2
b31 b16 b15 b0
S1 0 0 1 1 0 0 1 1 1 1 0 0 1 1

S2 + 1
XNR
S2
3
b31 b16 b15 b0
S2 0 1 0 1 0 1 0 1 0 1 0 1 0 1
4
D +1 D
b31 b16 b15 b0
D 1 0 0 1 1 0 0 1 0 1 1 0 0 1 6
(2) For bit devices, the bit devices after the points designated by digit specification are regarded
as "0" in the operation. 6

Operation Error
7
(1) There are no operation errors associated with the WXNR(P) or DXNR(P) instructions.

8
Program Example
(1) The following program performs an exclusive NOR operation on the 16-bit data from X30 to
X3F and the data at D99 when X0 is turned ON, and stores the results to D7.

7.1.7 16-bit and 32-bit data exclusive NOR operations (WXNR(P),DXNR(P))

7.1 Logical operation instructions
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
X3F X3CX3B X38X37 X34X33 X30
X3F to X30 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
XNR
b15 b8 b7 b0
D99 1 1 0 0 1 0 0 1 1 1 1 1 1 1 0 0

b15 b8 b7 b0
D7 0 1 1 0 0 0 1 1 0 1 0 1 0 1 1 0

7-31
 WXNR(P),DXNR(P)

(2) The following program performs an exclusive NOR operation on the 32-bit data at D20 and
D21 and the data at D10 and D11 when X10 is turned ON, and stores the result to D40 and
D41.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
S +1 S
b31 b16 b15 b0
D21,D20 0 1 0 1 1 0 1 0 1 0 0 1 0 1
XNR
S +1 S
b31 b16 b15 b0
D11,D10 0 1 1 0 0 1 0 1 1 0 1 1 0 0

D +1 D
b31 b16 b15 b0
D41,D40 1 1 0 0 0 0 0 0 1 1 0 1 1 0

7-32
 BKXNR(P)

7.1.8 Block exclusive NOR operations (BKXNR(P))

BKXNR(P)
1
Basic High
performance Process Redundant Universal LCPU
2

3
Command
BKXNR BKXNR S1 S2 D n

Command 4
BKXNRP S1 S2 D n
BKXNRP

6
S1 *1 : Head number of the devices where data on which a logical operation will be conducted is stored (BIN 16 bits)
S2 *1 : Data for a logical operation or head number of the devices where the data for the logical operation is stored (BIN 16 bits)
D

n
*1 : Head number of the devices where the operation result will be stored (BIN 16 bits)
: Number of operation data blocks (BIN 16 bits)
6
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data K, H

S1 *1
Bit

––
Word Bit Word

–– ––
7
––
S2 *1 –– ––
––
D *1 ––
––
–– –– 8
n ––

*1: The same device number can be specified for S1 and D or S2 and D .

7.1.8 Block exclusive NOR operations (BKXNR(P))

7.1 Logical operation instructions
Function
(1) Performs an exclusive NOR operation on the data located in the n points from the device
designated by S1 , and the data located in the n points from the device designated by S2 , and
stores the results into the area starting from the device designated by D .
b15 b8 b7 b0 b15 b8 b7 b0
S1 0000111111110000 S2 0000000011110000
S1 + 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 S2 + 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0
S1 + 2 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 S2 + 2 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
n n
XNR

S1 + (n 2) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 S2 +(n 2) 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0
S1 + (n 1) 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 S2 +(n 1) 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

b15 b8b7 b0
D 1111000011111111
D +1 0000000011111111
D +2 1010101001010101
n

D +(n 2) 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0
D +(n 1) 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1

7-33
 BKXNR(P)

(2) The constant designated by S2 can be between 32768 and 32767 (BIN 16-bit data).
b15 b8b7 b0
S1 0000111111111111
S1 + 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0
S1 + 2 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 b15 b8b7 b0
n XNR S2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0

S1 +(n 2) 1100110011001100
S1 +(n 1) 0000111111110000

b15 b8 b7 b0
D 0000000011110000
D +1 0000000011111111
D +2 1100001100111100
n

D +(n 2) 1100001111000011
D +(n 1) 0000000011111111

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The n-bit range from the S1 , S2 , or D device exceeds the range of that device.
(Error code: 4101)
• The device range for n points starting from the device designated by S1 overlaps with the
device range for n points starting from the device designated by D . (except when the same
device is specified for S1 and D ) (Error code: 4101)
• The device range for n points starting from the device designated by S2 overlaps with the
device range for n points starting from the device designated by D . (except when the same
device is specified for S2 and D ) (Error code: 4101)

Program Example
(1) The following program performs an exclusive NOR operation on the data stored at D100 to
D102 and the data stored at R0 to R2 when X20 is turned ON, and stores the operation
result into the area starting from D200.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
b15 b8 b7 b0 b15 b8 b7 b0
D100 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 R0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
XNR
D101 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 R1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
D102 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R2 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

b15 b8 b7 b0
D200 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1
D201 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 D0 3
D202 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0

7-34
 ROR(P),RCR(P)

7.2 Rotation instruction

1
7.2.1 Right rotation of 16-bit data (ROR(P),RCR(P))
ROR(P),RCR(P)
2
Basic High
Process Redundant Universal LCPU
3
performance

4
indicates an instruction symbol of ROR/RCR.

Command
ROR, RCR D n 6
Command
P D n
RORP, RCRP
6
D : Head number of the devices to rotate (BIN 16 bits)
n : Number of rotations (0 to 15) (BIN 16 bits)
7
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

D –– ––
8
n ––

Function

7.2.1 Right rotation of 16-bit data (ROR(P),RCR(P))

7.2 Rotation instruction
ROR
(1) Rotates 16-bit data of the device designated by D , not including the carry flag, n-bits to the right.
The carry flag is ON or OFF depending on the status prior to the execution of the ROR
instruction.
Carry flag
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 (SM700)
D 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0

Right rotation (1 bit)

Carry flag
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 (SM700)
D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

Right rotation (1 bit)

Value of b0 Value of b0
Carry flag
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 (SM700)
D 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0

Value of b0 Right rotation (n bits) Value of b0

Carry flag
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 (SM700)
D

Value of b(n-1)
Value of b(n-1)

7-35
 ROR(P),RCR(P)

(2) When a bit device is designated for D , a rotation is performed within the device range
specified by digit specification.
The number of bits by which a rotation is carried out is the remainder of n/(specified number
of bits).
For example, when n 15 and (specified number of bits) 12 bits, the remainder of 15/12
1 is "3", and the data is rotated 3 bits.
(3) Specify any of 0 to 15 as n.
If the value specified as n is 16 or greater, the remainder of n / 16 is used for rotation.
For example, when n 18, the contents are rotated two bits to the right since the remainder
of 18 / 16 1 is "2".
RCR

(1) Rotates 16-bit data of the device designated by D , including the carry flag, n-bits to the
right.
The carry flag is ON or OFF depending on the status prior to the execution of the ROR
instruction.
Carry flag
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 (SM700)
D 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0

Right rotation (1 bit)

Carry flag
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 (SM700)
D 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

Right rotation (1 bit)

Value of carry flag Value of b0

Carry flag
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 (SM700)
D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0

Value of carry flag Right rotation (n bits) Value of b0

Carry flag
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 (SM700)
D

Value of b(n-1)

(2) When a bit device is designated for D , a rotation is performed within the device range
specified by digit specification.
The number of bits by which a rotation is executed is the remainder of n/(specified number of
bits).
For example, when n 15 and (specified number of bits) 12 bits, the remainder of 15/12
1 is "3", and the data is rotated 3 bits.
(3) Specify any of 0 to 15 as n.
If the value specified as n is 16 or greater, the remainder of n / 16 is used for rotation.
For example, when n 18, the contents are rotated two bits to the right since the remainder
of 18 / 16 1 is "2".

7-36
 ROR(P),RCR(P)

Operation Error
1
(1) There are no operation errors associated with the ROR(P) or RCR(P) instructions.

2
Program Example
(1) The following program rotates the contents of D0, not including the carry flag, 3 bits to the
right when XC is turned ON.
3
[Ladder Mode] [List Mode]
Step Instruction Device 4

6
[Operation]
Carry flag
b15 b14 b13 b12 b11b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 (SM700) 6
D0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0
Carry flag
b15 b14 b13b12 b11b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
D0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1
(SM700)
1
7
Contents of b2 to b0 Contents of b15 to b4
before execution before execution Content of b3 Content of b2
before execution before execution 8
(2) The following program rotates the contents of D0, including the carry flag, 3 bits to the right
when XC is turned ON.
[Ladder Mode] [List Mode]

7.2.1 Right rotation of 16-bit data (ROR(P),RCR(P))

7.2 Rotation instruction
Step Instruction Device

[Operation]
Carry flag
b15 b14 b13 b12 b11b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 (SM700)
D0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 *
Carry flag
b15 b14 b13 b12 b11b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 (SM700)
D0 1 1 * 0 0 0 0 0 0 0 0 0 0 0 0 1 1

Contents of b1 and b0 Contents of b15 to b4

Content of b3 Content of b2
before execution before execution
Content of carry before execution before execution
flag SM700
* ON/OFF status of the carry flag depends on its status before the execution of ROR.

7-37
 ROL(P),RCL(P)

7.2.2 Left rotation of 16-bit data (ROL(P),RCL(P))

ROL(P),RCL(P)

Basic High
performance Process Redundant Universal LCPU

indicates an instruction symbol of ROL/RCL.

Command
ROL, RCL D n

Command
P D n
ROLP, RCLP

D : Head number of the devices to rotate (BIN 16 bits)

n : Number of rotations (0 to 15) (BIN 32 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

D –– ––

n ––

Function
ROL

(1) Rotates the 16-bit data of the device designated at D , not including the carry flag, n-bits to
the left.
The carry flag turns ON or OFF depending on its status prior to the execution of ROL instruction.
Carry flag
(SM700) b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 D

Left rotation (1 bit)

Carry flag
(SM700) b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 D

Value of b15 Left rotation (1 bit) Value of b15

Carry flag
(SM700) b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 D

Value of b15 Left rotation (n bits) Value of b15

Carry flag
(SM700) b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
D

Value of b(16-n)
Value of b(16-n)

7-38
 ROL(P),RCL(P)

(2) When a bit device is designated for D , a rotation is performed within the device range
specified by digit specification.
1
The number of bits by which a rotation is executed is the remainder of n/(specified number of
bits).
For example, when n 15 and (specified number of bits) 12 bits, the remainder of 15/12
2
1 is "3", and the data is rotated 3 bits.
(3) Specify any of 0 to 15 as n.
If the value specified as n is 16 or greater, the remainder of n / 16 is used for rotation. 3
For example, when n 18, the data is rotated 2 bits to the left since the remainder of 18/16
1 is "2".
4
RCL

(1) Rotates the 16-bit data of the device designated by , including the carry flag, n-bits to the
6
D
left.
The carry flag turns ON or OFF depending on its status prior to the execution of RCL
instruction.
Carry flag 6
(SM700) b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 D

Left rotation (1 bit) 7

Carry flag
(SM700) b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D
8
Value of b15 Left rotation (1 bit)
Value of carry flag

Carry flag
(SM700) b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

7.2.2 Left rotation of 16-bit data (ROL(P),RCL(P))

7.2 Rotation instruction
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 D

Value of b15 Value of carry flag

Left rotation (n bits)

Carry flag
(SM700) b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
D

Value of b(16-n)

(2) When a bit device is designated for D , a rotation is performed within the device range
specified by digit specification.
The number of bits by which a rotation is executed is the remainder of n/(specified number of
bits).
For example, when n 15 and (specified number of bits) 12 bits, the remainder of 15/12
1 is "3", and the data is rotated 3 bits.
(3) Specify any of 0 to 15 as n.
If the value specified as n is 16 or greater, the remainder of n / 16 is used for rotation.
For example, when n 18, the data is rotated 2 bits to the left since the remainder of 18/16
1 is "2".

7-39
 ROL(P),RCL(P)

Operation Error
(1) There are no operation errors associated with the ROL(P) or RCL(P) instructions.

Program Example
(1) The following program rotates the contents of D0, not including the carry flag, 3 bits to the
left when XC is turned ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
Carry flag
(SM700) b15 b14 b13 b12 b11b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 D0

Carry flag
(SM700) b15 b14 b13 b12 b11b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 D0

Content of b13 Contents of b11 to b0 Contents of b15 to b13

before execution Content of b12 before execution before execution
before execution

(2) The following program rotates the contents of D0, including the carry flag, 3 bits to the left
when XC is turned ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
Carry flag
(SM700) b15 b14 b13 b12 b11b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
* 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 D0

Carry flag
(SM700) b15 b14 b13 b12 b11b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
1 1 0 0 0 0 0 0 0 0 0 0 0 0 * 1 1 D0

Content of b12 Contents of b11 to b0 Contents of b15 and b14

Content of b13
before execution before execution before execution
before execution
Content of carry flag SM700

* ON/OFF status of the carry flag depends on its status before the execution of RCL.

7-40
 DROR(P),DRCR(P)

7.2.3 Right rotation of 32-bit data (DROR(P),DRCR(P))

DROR(P),DRCR(P)
1
Basic High
performance Process Redundant Universal LCPU
2

indicates an instruction symbol of DROR/DRCR.

3
Command
DROR, DRCR D n
4
Command
P D n
DRORP, DRCRP
6
D : Head number of the devices to rotate (BIN 32 bits)
n : Number of rotations (0 to 31) (BIN 16 bits)
6
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

D –– ––
7
n ––

8
Function
DROR

7.2.3 Right rotation of 32-bit data (DROR(P),DRCR(P))

7.2 Rotation instruction
(1) The 32-bit data of the device designated at D , not including the carry flag, is rotated n-bits
to the right.
The carry flag turns ON or OFF depending on its status prior to the execution of the DROR
instruction.
D +1 D Carry flag
b31 b30 b29 b28 b27 b18 b17 b16 b15b14 b5 b4 b3 b2 b1 b0 (SM700)

n-bit rotation

(2) When a bit device is designated for D , a rotation is performed within the device range
specified by digit specification.
The number of bits by which a rotation is executed is the remainder of n/(specified number of
bits).
For example, when n 31 and (specified number of bits) 24 bits, the remainder of 31/24
1 is "7", and the data is rotated 7 bits.
(3) Specify any of 0 to 31 as n.
If the value specified as n is 32 or greater, the remainder of n / 32 is used for rotation.
For example, when n 34, the contents are rotated two bits to the right since the remainder
of 34 / 32 1 is "2".

7-41
 DROR(P),DRCR(P)

DRCR

(1) Rotates 32-bit data, including carry flag, at device designated by D n bits to the right.
The carry flag goes ON or OFF depending on its status prior to the execution of the DRCR
instruction.
D +1 D Carry flag
b31 b30 b29 b28 b27 b18 b17 b16 b15b14 b5 b4 b3 b2 b1 b0 (SM700)

n-bit rotation

(2) When a bit device is designated for D , a rotation is performed within the device range
specified by digit specification. The number of bits by which a rotation is executed is the
remainder of n /(specified number of bits).
For example, when n 31 and (specified number of bits) 24 bits, the remainder of 31/24
1 is "7", and the data is rotated 7 bits.
(3) Specify any of 0 to 31 as n. If the value specified as n is 32 or greater, the remainder of n /
32 is used for rotation. For example, when n 34, the contents are rotated two bits to the
right since the remainder of 34 / 32 1 is "2".

Operation Error
(1) There are no operation errors associated with the DROR(P) or DRCR(P) instruction.

Program Example
(1) The following program rotates the contents of D0 and D1, not including the carry flag, 4 bits
to the right when XC is ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
Carry flag
b31 b28 b27 b24 b23 b20 b19 b16 b15 b12 b11 b8 b7 b4 b3 b0 (SM700)
D0, D1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0

Carry flag
b31 b28 b27 b24b23 b20b19 b16 b15 b12 b11 b8 b7 b4 b3 b0 (SM700)
D0, D1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1

Contents of b3 to b0 Contents of b31 to b4

before execution Content of b3
before execution
before execution

7-42
 DROR(P),DRCR(P)

(2) The following program rotates the contents of D0 and D1, including the carry flag, 4 bits to
the right when XC is ON.
[Ladder Mode] [List Mode]
1
Step Instruction Device

[Operation] 3
Carry flag
b31 b28b27 b24b23 b20b19 b16b15 b12b11 b8b7 b4b3 b0 (SM700)
D0, D1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 * 4
Carry flag
b31 b28b27 b24b23 b20b19 b16b15 b12b11 b8b7 b4b3 b0 (SM700)
D0, D1 1 1 1 * 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1
6
Before execution
Contents of b2 to b0 Content of b3
before execution Content of carry flag before execution
SM700 before execution
6
* : ON/OFF status of the carry flag depends on its status before the execution of DRCR.

7.2.3 Right rotation of 32-bit data (DROR(P),DRCR(P))

7.2 Rotation instruction

7-43
 DROL(P),DRCL(P)

7.2.4 Left rotation of 32-bit data (DROL(P),DRCL(P))

DROL(P),DRCL(P)

Basic High
performance Process Redundant Universal LCPU

indicates an instruction symbol of DROL/DRCL.

Command
DROL, DRCL D n

Command
P D n
DROLP, DRCLP

D : Head number of the devices to rotate (BIN 32 bits)

n : Number of rotations (0 to 31) (BIN 16 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

D –– ––

n ––

Function
DROL

(1) The 32-bit data of the device designated at D , not including the carry flag, is rotated n-bits
to the left. The carry flag turns ON or OFF depending on its status prior to the execution of
the DROL instruction.
D +1 D
Carry flag
(SM700) b31 b30 b29 b28 b27 b18 b17 b16 b15b14 b5 b4 b3 b2 b1 b0

n-bit rotation

(2) When a bit device is designated for D , a rotation is performed within the device range
specified by digit specification. The number of bits by which a rotation is executed is the
remainder of n /(specified number of bits).
For example, when n 31 and (specified number of bits) 24 bits, the remainder of 31/24
1 is "7", and the data is rotated 7 bits.
(3) Specify any of 0 to 31 as n. If the value specified as n is 32 or greater, the remainder of n/32
is used for rotation. For example, when n 34, the data is rotated 2 bits to the left since the
remainder of 34/32 1 is "2".
DRCL
(1) Rotates 32-bit data of the device designated by D , including the carry flag, n-bits to the left.
The carry flag turns ON or OFF depending on its status prior to the execution of the DRCL
instruction.
D +1 D
Carry flag
(SM700) b31 b30 b29 b28b27 b18 b17 b16 b15b14 b5 b4 b3 b2 b1 b0

n-bit rotation

7-44
 DROL(P),DRCL(P)

(2) When a bit device is designated for D , a rotation is performed within the device range
specified by digit specification. The number of bits by which a rotation is executed is the
remainder of n /(specified number of bits).
1
For example, when n 31 and (specified number of bits) 24 bits, the remainder of 31/24
1 is "7", and the data is rotated 7 bits.
2
(3) Specify any of 0 to 31 as n. If the value specified as n is 32 or greater, the remainder of n/32
is used for rotation. For example, when n 34, the data is rotated 2 bits to the left since the
remainder of 34/32 1 is "2".
3
Operation Error
4
(1) There are no operation errors associated with the DROL(P) or DRCL(P) instructions.

Program Example 6

(1) The following program rotates the contents of D0 and D1, not including the carry flag, 4 bits
to the left when XC is ON. 6
[Ladder Mode] [List Mode]
Step Instruction Device
7

8
[Operation]
Carry flag
(SM700) b31 b28b27 b24b23 b20 b19 b16 b15 b12 b11 b8 b7 b4 b3 b0
0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 D0, D1

7.2.4 Left rotation of 32-bit data (DROL(P),DRCL(P))

7.2 Rotation instruction
Carry flag
(SM700) b31 b28b27 b24b23 b20 b19 b16 b15 b12 b11 b8 b7 b4 b3 b0
1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D0, D1

Contents of b27 to b0 Contents of b31 to b28

Content of b28 before execution before execution
before execution

(2) The following program rotates the contents of D0 and D1, including the carry flag, 4 bits to
the left when XC is ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]

Carry flag
(SM700) b31 b28b27 b24b23 b20 b19 b16 b15 b12 b11 b8 b7 b4 b3 b0
* 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 D0, D1

Carry flag
(SM700) b31 b28b27 b24b23 b20 b19 b16 b15 b12 b11 b8 b7 b4 b3 b0
1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 * 1 1 1 D0, D1

Contents of b27 to b0 Contents of b31 to b29

Content of b28 before execution
before execution
before execution Content of carry flag
SM700 before execution
* : ON/OFF status of the carry flag depends on its status before the execution of DRCL.

7-45
 SFR(P),SFL(P)

7.3 Shift instruction

7.3.1 n-bit shift to right or left of 16-bit data (SFR(P),SFL(P))

SFR(P),SFL(P)

Basic High
performance Process Redundant Universal LCPU

indicates an instruction symbol of SFR/SFL.

Command
SFR, SFL D n

Command
P D n
SFRP, SFLP

D : Head number of the devices where shift data is stored (BIN 16 bits)
n : Number of shifts (0 to 15) (BIN 16 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

D –– ––

n ––

Function
SFR

(1) Causes a shift to the right by n bits of the 16-bit data from the device designated at D .
The n bits from the upper bit are filled with 0s.
b15 b14 b13 b12 b11b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
D 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0

When n=6:
Carry flag
b15 b14 b13 b12 b11b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 (SM700)
D 0 0 0 0 0 0 1 1 1 0 1 1 1 0 1 1 1

Filled with 0s.

(2) When a bit device is designated for D , a right shift is executed within the device range
specified by digit specification.
Y1B Y18 Y17 Y14 Y13 Y10
1 0 1 0 1 0 1 0 1 0 1 0

When n = 4:
Carry flag
Y1B Y18 Y17 Y14 Y13 Y10 (SM700)
0 0 0 0 1 0 1 0 1 0 1 0 1

Filled with 0s.

7-46
 SFR(P),SFL(P)

The number of bits by which a shift is executed is the remainder of n/(specified number of
bits).
For example, when n 15 and (specified number of bits) 8 bits, the remainder of 15/8 1
1 is "7", and the data is shifted 7 bits.
(3) Specify any of 0 to 15 as n. If the value specified as n is 16 or greater, the remainder of n/16
is used for a shift to the right. 2
For example, when n 18, the data is shifted 2 bits to the right since the remainder of 18/16
1 is 2.
SFL
3
(1) Shifts 16-bit data at device designated by D n bits to the left.
Bits starting from the lowest bit to n bit are filled with 0s. 4
b15 b14 b13 b12 b11b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
1 1 1 1 0 0 1 1 0 0 0 0 1 1 1 1 D
6
When n=8:
Carry flag
(SM700) b15 b14 b13 b12 b11b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 D 6
Filled with 0s.

(2) When a bit device is designated for D , a left shift is executed within the device range specified 7
by digit specification.
X17 X14 X13 X10
0 0 1 1 0 0 1 1 8
Carry flag
(SM700) X17 X14 X13 X12 X10
1 1 0 0 1 1 0 0 0

7.3.1 n-bit shift to right or left of 16-bit data (SFR(P),SFL(P))

7.3 Shift instruction
Filled with 0s.

The number of bits by which a shift is executed is the remainder of n/(specified number of
bits). For example, when n 15 and (specified number of bits) 8 bits, the remainder of
15/8 1 is "7", and the data is shifted 7 bits.
(3) Specify any of 0 to 15 as n. If the value specified as n is 16 or greater, the remainder of n/16
is used for a shift to the left.
For example, when n 18, the data is shifted 2 bits to the left since the remainder of 18/16
1 is "2".

Operation Error
(1) There are no operation errors associated with the SFR(P) or SFL(P) instructions.

7-47
 SFR(P),SFL(P)

Program Example
(1) The following program shifts the data of D0 to the right by the number of bits designated by
D100 when X20 is turned ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
b15 b14 b13b12 b11b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
D0 1 0 1 0 0 1 1 1 0 0 1 0 1 0 0 0

D100 3
Carry flag
b15 b14 b13b12 b11b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 (SM700)
D0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 0

Filled with 0s.

(2) The following program shifts the contents of X10 to X17 3 bits to the left when X1C is ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
X17 X14 X13 X10
0 0 1 1 0 0 1 1

Carry flag
(SM700) X17 X14 X13 X12 X10
1 1 0 0 1 1 0 0 0

Filled with 0s.

7-48
 BSFR(P),BSFL(P)

7.3.2 1-bit shift to right or left of n-bit data (BSFR(P),BSFL(P))

BSFR(P),BSFL(P)
1
Basic High
performance Process Redundant Universal LCPU
2

indicates an instruction symbol of BSFR/BSFL.

3
Command
BSFR, BSFL D n
4
Command
P D n
BSFRP, BSFLP
6
D : Head number of the devices to be shifted (bits)
n : Number of devices to which shift is executed (BIN 16 bits)
6
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

D –– ––
7
n ––

8
Function
BSFR

7.3.2 1-bit shift to right or left of n-bit data (BSFR(P),BSFL(P))

7.3 Shift instruction
(1) Shifts the data in n points from the device designated by D to the right by one bit.
n
D +(n-1) D +(n-2) D +(n-3) D +2 D +1 D
1 1 0 1 1 0

Carry flag
D +(n-1) D +(n-2) D +(n-3) D +2 D +1 D (SM700)
0 1 1 0 1 1 0

Filled with 0

(2) The device designated by D + (n 1) is filled with 0.

BSFL

(1) Shifts the data in n points from the device designated by D to the left by one bit.
D +(n-1) D +(n-2) D +(n-3) D +2 D +1 D
1 1 0 0 1 1

Carry flag
(SM700) D +(n-1) D +(n-2) D +(n-3) D +2 D +1 D
1 1 0 0 1 1 0

Filled with 0

(2) The device designated by D is filled with 0.

7-49
 BSFR(P),BSFL(P)

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• The range of the device n points from a device designated by D , or exceeds the
relevant device. (Error code: 4101)

Program Example
(1) The following program shifts the data at M668 to M676 to the right when X8F is turned ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
Designation range for the
BSFRP instruction
M678M677M676M675M674M673M672M671M670M669M668M667
1 1 1 0 1 0 1 1 0 0 1 1

Carry flag
M678M677M676M675M674M673M672M671M670M669M668M667 (SM700)
1 1 0 1 0 1 0 1 1 0 0 1 1

Filled with 0s.

(2) The following program shifts the data at Y60 to Y6F to the left when X4 is turned ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
Y6FY6EY6DY6CY6BY6AY69Y68Y67Y66Y65Y64Y63Y62Y61Y60
1 0 0 1 1 0 0 0 0 1 0 1 0 1 1 1

Carry flag
(SM700) Y6FY6EY6DY6CY6BY6AY69Y68Y67Y66Y65Y64Y63Y62Y61Y60
1 0 0 1 1 0 0 0 0 1 0 1 0 1 1 1 0

Filled with 0

7-50
 SFTBR(P),SFTBL(P)

7.3.3 n-bit shift to right or left of n-bit data (SFTBR(P),SFTBL(P))

SFTBR(P),SFTBL(P)
1
Ver.
High
2
Basic performance Process Redundant Universal LCPU

QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later.

QnUDE(H)CPU: The serial number (first five digits) is "10102" or later.

3
indicates an instruction symbol of SFTBR/SFTBL.

Command 4
SFTBR,SFTBL D n1 n2

Command
SFTBRP,SFTBLP P D n1 n2 6

D : Head number of the devices to be shifted (bits)

n1 : Number of bits to be shifted (BIN 16 bits)
6
n2 : Number of shifts (BIN 16 bits)

Setting Internal Devices J \ Constants

Data Bit Word
R, ZR
Bit Word
U \G Zn
K, H
Other
7
D *1 –– –– ––

n1 –– ––

n2 –– –– 8
*1 : T, C, ST, and S devices are not available.

Function

7.3.3 n-bit shift to right or left of n-bit data (SFTBR(P),SFTBL(P))

7.3 Shift instruction
SFTBR(P)

(1) This instruction shifts the n1 bits data in the devices starting from the device specified by D
to the right by n2 bits.
n1=10, n2=4
n2
n1
D ＋9 D ＋8 D ＋7 D ＋6 D ＋5 D ＋4 D ＋3 D ＋2 D ＋1 D
0 1 1 1 1 0 0

Carry flag
D ＋9 D ＋8 D ＋7 D ＋6 D ＋5 D ＋4 D ＋3 D ＋2 D ＋1 D (SM700)
0 0 0 0 1 1 1 0 1 1

Filled with 0s

(2) n1 and n2 are specified under the condition that n1 is larger than n2. If the value of n2 is
equal to or larger than the value of n1, the remainder of n2 / n1 (n2 devided by n1) is used
for a shift.
(3) This instruction specifies n1 ranged from 1 to 64.
(4) Bits starting from the highest bit to n2th bit are filled with 0s. If the value of n2 is larger than
the value of n1, the remainder of n2 / n1 will be 0.
(5) If the value specified by n1 or n2 is 0, the instruction will be not processed.

7-51
 SFTBR(P),SFTBL(P)

SFTBL(P)

(1) This instruction shifts the n1 bits data in the devices starting from the device specified by D
to the left by n2 bits.
n1=10, n2=4
n2
n1
D ＋8 D ＋7 D ＋6 D ＋5 D ＋4 D ＋3 D ＋2 D ＋1 D
1 1 0 1 1 1 1 0 1

Carry flag
(SM700) D ＋8 D ＋7 D ＋6 D ＋5 D ＋4 D ＋3 D ＋2 D ＋1 D
1 1 1 1 0 1 0 0 0 0

Filled with 0s

(2) n1 and n2 are specified under the condition that n1 is larger than n2. If the value of n2 is
equal to or larger than the value of n1, the remainder of n2 / n1 (n2 devided by n1) is used
for a shift.
However, if the remainder of n2 / n1 is 0, the instruction will be not processed.
(3) This instruction specifies n1 ranged from 1 to 64.
(4) Bits starting from the lowest bit to n2th bit are filled with 0s. If the value of n2 is larger than
the value of n1, the remainder of n2 / n1 will be 0.
(5) If the value specified by n1 or n2 is 0, the instruction will be not processed.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an
error code is stored into SD0.
• The value specified by n1 is other than 0 to 64. (Error code: 4100)
• The value data specified by n2 is negative. (Error code: 4100)

• The range of devices specified by n1 exceeds the range of devices specified by D .

(Error code: 4101)

7-52
 SFTBR(P),SFTBL(P)

Program Example
1
(1) The following program shifts the data of Y10 to Y17 (8 bits) specified by D to the right by 2
bits (n2), when M0 is turned on.
[Ladder Mode] [List Mode]
2
Step Instruction Device

[Operation]
4
Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10
1 0 1 1 1 0 0 1
6
Carry flag
Y17
0
Y16
0
Y15
1
Y14
0
Y13
1
Y12
1
Y11
1
Y10
0
(SM700)
0
6

(2) The following program shifts the data of Y21 to Y2C (12 bits) specified by to the left by 5
bits (n2), when M0 is turned on.
D
7
[Ladder Mode] [List Mode]
Step Instruction Device
8

[Operation]

7.3.3 n-bit shift to right or left of n-bit data (SFTBR(P),SFTBL(P))

7.3 Shift instruction
Y2C Y2B Y2A Y29 Y28 Y27 Y26 Y25 Y24 Y23 Y22 Y21
1 0 1 1 0 1 0 1 1 0 0 1

Carry flag
(SM700)
0 Y2C Y2B Y2A Y29 Y28 Y27 Y26 Y25 Y24 Y23 Y22 Y21
1 0 1 1 0 0 1 0 0 0 0 0

7-53
 DSFR(P),DSFL(P)

7.3.4 1-word shift to right or left of n-word data (DSFR(P),DSFL(P))

DSFR(P),DSFL(P)

Basic High
performance Process Redundant Universal LCPU

indicates an instruction symbol of DSFR/DSFL.

Command
DSFR, DSFL D n

Command
P D n
DSFRP, DSFLP

D : Head number of the devices to be shifted (BIN 16 bits)

n : Number of devices to which shift is executed (BIN 16 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

D –– –– ––

n ––

Function
DSFR

(1) Shifts data n points from device designated by D 1-word to the right.
n
D +(n-1) D +(n-2) D +(n-3) D +2 D +1 D
555 212 325 100 50 40

D +(n-1) D +(n-2) D +(n-3) D +(n-4) D +1 D

0 555 212 325 100 50

Filled with 0.

(2) The device designated by D + (n 1) is filled with 0.

DSFL

(1) Shifts data n points from device designated by D 1-word to the left.
n
D +(n-1) D +(n-2) D +(n-3) D +2 D +1 D
555 120 325 100 50 40

D +(n-1) D +(n-2) D +3 D +2 D +1 D
120 325 100 50 40 0

Filled with 0.

(2) The device designated by D is filled with 0.

7-54
 DSFR(P),DSFL(P)

Operation Error
1
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• The range of the device n points from a device designated by D , or exceeds the
2
relevant device. (Error code: 4101)

3
Program Example
(1) The following program shifts the contents of D683 to D689 to the right when XB is turned
ON.
4
[Ladder Mode] [List Mode]
Step Instruction Device 6

6
[Operation]
Designation range for the DSFRP instruction
D689 D688 D687 D686 D685 D684 D683 7
-100 503 600 -336 3802 -32765 5003

D689 D688 D687 D686 D685 D684 D683

8
0 -100 503 600 -336 3802 -32765

Filled with 0.

(2) The following program shifts the contents of D683 to D689 to the left when XB is turned ON.

7.3.4 1-word shift to right or left of n-word data (DSFR(P),DSFL(P))

7.3 Shift instruction
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
Designation range for the DSFLP instruction
D689 D688 D687 D686 D685 D684 D683
-100 503 600 -336 3802 -32765 5003

D689 D688 D687 D686 D685 D684 D683

503 600 -336 3802 -32765 5003 0

Filled with 0.

7-55
 SFTWR(P),SFTWL(P)

7.3.5 n-bit shift to right or left of n-word data (SFTWR(P),SFTWL(P))

SFTWR(P),SFTWL(P)

Ver.
High
Basic performance Process Redundant Universal LCPU

QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later.

QnUDE(H)CPU: The serial number (first five digits) is "10102" or later.

indicates an instruction symbol of SFTWR/SFTWL.

Command
SFTWR,SFTWL D n1 n2

Command
P D n1 n2
SFTWRP,SFTWLP

D : Head number of the devices to be shifted (BIN 16 bits)

n1 : Number of words to be shifted (BIN 16 bits)
n2 : Number of shifts (BIN 16 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

D –– –– ––

n1 –– ––

n2 –– ––

Function
SFTWR(P)

(1) This instruction shifts n1 words data in the devices starting from the device specified by D to
the right by n2 words.
n1=9, n2=4
n2
n1
D ＋8 D ＋7 D ＋6 D ＋5 D ＋4 D ＋3 D ＋2 D ＋1 D
30FH 1EH 100H 0H 1FFH 10 H 1FH 7FFH 2A H

D ＋8 D ＋7 D ＋6 D ＋5 D ＋4 D ＋3 D ＋2 D ＋1 D
0H 0H 0H 0H 30FH 1EH 100H 0H 1FFH

Filled with 0H

(2) The n2 words data in the devices starting from the highest device are filled with 0s.
(3) If the value specified by n1 or n2 is 0, the instruction will be not processed.
(4) If the value of n2 is equal to or larger than the value of n1, the n1 words data in the devices
starting from the device specified by D will be filled with 0s.

7-56
 SFTWR(P),SFTWL(P)

SFTWL(P)
(1) This instruction shifts the n1 words data in the devices starting from the device specified by 1
D to the left by n2 words.
n1=9, n2=4
n2
2
n1
D ＋8 D ＋7 D ＋6 D ＋5 D ＋4 D ＋3 D ＋2 D ＋1 D
1FFH 10H 0H 7FFH 3AH 1F H 30 H 0H FFH
3

D ＋8 D ＋7 D ＋6 D ＋5 D ＋4 D ＋3 D ＋2 D ＋1 D 4
3AH 1F H 30 H 0H FFH 0H 0H 0H 0H

Filled with 0H
6
(2) The n2 words in the devices starting from the lowest device are filled with 0s.
(3) If the value specified by n1 or n2 is 0, the instruction will be not processed.
(4) If the value of n2 is equal to or greater than the value of n1, the n1 words devices starting 6
from the device specified by D will be filled with 0s.

7
Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an
error code is stored into SD0.
8
• n1 or n2 is negative value. (Error code: 4100)

• The range of devices specified by n1 exceeds the range of devices specified by D .

(Error code: 4101)

7.3.5 n-bit shift to right or left of n-word data (SFTWR(P),SFTWL(P))

7.3 Shift instruction
Program Example
(1) The following program shifts the 8 words (n1) data stored in the devices starting from D10
specified by D to the right by 2 words (n2), when M0 is turned on.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]

D17 D16 D15 D14 D13 D12 D11 D10

1FFH 0H 2AH 7FFH 10H 4EH 5FH FFH

D17 D16 D15 D14 D13 D12 D11 D10 × ×

Filled with 0H 0H 0H 1FFH 0H 2AH 7FFH 10H 4EH

7-57
 SFTWR(P),SFTWL(P)

(2) The following program shifts the 12 words (n1) data in the devices starting from D21
specified by D to the left by 5 words (n2), when M0 is turned on.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
D2C D2B D2A D29 D28 D27 D26 D25 D24 D23 D22 D21
FFH EH 5H 0H 2AH FFH 3AH 1H 0H 0H 10 H 7FFH

× × × × × D2C D2B D2A D29 D28 D27 D26 D25 D24 D23 D22 D21
FFH 3AH 1H 0H 0H 10 H 7FFH 0H 0H 0H 0H 0H Filled with 0H

7-58
 BSET(P),BRST(P)

7.4 Bit processing instructions

1
7.4.1 Bit set and reset for word devices (BSET(P),BRST(P))
BSET(P),BRST(P)
2
Basic High
Process Redundant Universal LCPU
3
performance

4
indicates an instruction symbol of BSET/BRST.

Command
BSET, BRST D n
6
Command
P D n
BSETP, BRSTP
6
D : Number of the device whose bits are set/reset (BIN 16 bits)
n : Number of the bit to be set/reset (0 to 15) (BIN 16 bits)
7
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

D –– ––
8
n ––

Function

7.4.1 Bit set and reset for word devices (BSET(P),BRST(P))

7.4 Bit processing instructions
BSET
(1) Sets (sets "1" at) the nth bit in the word device designated at D .
(2) If n exceeds "15", bit set/reset is performed with the lower 4 bits of the data.

BSETP D10 K6

b15 b6 b1b0
Before execution D10 1 1 0 0 1 0 1 1 0 0 1 1 1 0 1 1

b15 b6 b1b0
After execution D10 1 1 0 0 1 0 1 1 0 1 1 1 1 0 1 1

1 is set

BRST

(1) Resets the nth bit of a word device designated by D to 0.

(2) If n exceeds "15", bit set/reset is performed with the lower 4 bits of the data.

BRSTP D10 K11

b15 b11 b1b0

Before execution D10 1 1 0 0 1 0 1 1 0 0 1 1 1 0 1 1

b15 b11 b1b0

After execution D10 1 1 0 0 0 0 1 1 0 0 1 1 1 0 1 1

0 is set.

7-59
 BSET(P),BRST(P)

Operation Error
(1) There are no operation errors associated with the BSET(P) or BRST(P) instructions.

Program Example
(1) The following program resets the 8th bit of D8 (b8) to 0 when XB is OFF, and sets the 3rd bit
of D8 (b3) to 1 when XB is ON.
[Ladder Mode]

Resets b8 of D8.

Sets b3 of D8.

[List Mode]
Step Instruction Device

[Operation]
b15 b8 b3 b0
Before execution D8 0 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1
When XB turns OFF. When XB turns ON.

b15 b8 b3 b0
After execution D8 0 0 1 1 0 1 0 0 1 1 1 1 1 0 0 1

Remark
Bit set or reset of word devices can also be conducted by bit designation of word
devices.
• For the bit specification for word devices, link direct devices, refer to the
QnUCPU User’fs Manual(Function Explanation, Program Fundamentals) or
Qn(H)/QnPH/QnPRHCPU User’s Manuall(Function Explanation, Program
Fundamentals)
The processing of program example (1) would be conducted as shown below if bit
designation of a word device had been used:
XB
RST D8.8 Resets b8 of D8.
Designation of b8 of D8
XB
SET D8.3 Sets b3 of D8.
Designation of b3 of D8

7-60
 TEST(P),DTEST(P)

7.4.2 Bit tests (TEST(P),DTEST(P))

1
Basic High
performance Process Redundant Universal LCPU

2
TEST(P),DTEST(P)

3
indicates an instruction symbol of TEST/DTEST.

Command
TEST, DTEST S1 S2 D
4
Command
TESTP, DTESTP P S1 S2 D

6
S1 : Number of the device where bit data to be extracted is stored (BIN 16 bits)
S2 : Location of the bit data to be extracted (0 to 15 (TEST)/0 to 31 (DTEST)) (BIN 16/32 bits) 6
D : Number of the bit device where the extracted data will be stored (bits)

Setting Internal Devices J \ Constants

R, ZR Zn Other
Data Bit Word Bit Word
U \G
K, H
7
S1 –– ––

S2 ––

D –– –– ––
8

Function

7.4.2 Bit tests (TEST(P),DTEST(P))

7.4 Bit processing instructions
TEST

(1) Fetches bit data at the location designated by S2 within the word device designated by S1 ,
and writes it to the bit device designated by D .

(2) The bit device designated by D is OFF when the relevant bit is "0" and ON when it is "1".

(3) The position designated by S2 indicates the position of an individual bit in a 1-word data
block (0 to 15). When 16 or more is designated at S2 , the target is the bit data at the position
indicated by the remainder of n / 16. For example, when n 18, the target is the data at b2
since the remainder of 18 / 16 1 is "2".
S2 bit (When S2 =5)

b15 b5 b0
S1 D

DTEST

(1) Fetches bit data at the location designated by S2 within the 2-word device designated by S1 ,
or S1 +1, and writes it to the bit device designated by D .

(2) The bit device designated by D is OFF when the relevant bit is "0" and ON when it is "1".

7-61
 TEST(P),DTEST(P)

(3) The position designated by S2 indicates the position of an individual bit in a 2-word data
block (0 to 31). When 32 or more is designated at S2 , the target is the bit data at the position
indicated by the remainder of n / 32. For example, when n 34, the target is the data at b2
since the remainder of 34 / 32 1 is "2".
S2 bit (When S2 =21)

b31 b21 b16 b15 b0

D
S1 +1 S1

Operation Error
(1) There are no operation errors associated with the TEST(P) or DTEST(P) instructions.

Program Example
(1) The following program turns M0 ON or OFF based on the status of the 10th bit in the 1-word
data block (D0).
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
b15 b10 b0
D0 1 0 1 1 0 0 1 1 0 1 1 0 1 0 1 0

Turns M0 OFF since b10 is "0."

b15 b10 b0
D0 0 0 1 0 0 1 1 1 1 0 1 0 0 0 0 1

Turns M0 ON since b10 is "1."

7-62
 TEST(P),DTEST(P)

(2) The following program turns Y40 ON or OFF, depending on the status of the 19th bit of the
2-word data (W0 and W1).
[Ladder Mode] [List Mode]
1
Step Instruction Device

[Operation]
3
b31 b19 b16 b15 b0
10 1 10 0 10 10 1 100 00 10 1 10 1 1 10 1 1 10 110

b31 b19 b16 b15

Turns Y40 OFF since b19 is "0."
b0
4
0 110 110 1110 1 10 0 110 10 110 000 10 1 10 1
Turns Y40 ON since b19 is "1."
6
Remark
Programs using the bit test instruction can be rewritten as programs using bit
designation of word devices.
6
If the program in example (1) were changed to use bit designation of a word
device, it would appear as follows:
7
D0.A
M0 turns ON/OFF depending on the ON/OFF
M0
status of b10 of D0 (D0.A).
Designation of b10 of D0
8

7.4.2 Bit tests (TEST(P),DTEST(P))

7.4 Bit processing instructions

7-63
 BKRST(P)

7.4.3 Batch reset of bit devices (BKRST(P))

BKRST(P)

Basic High
performance Process Redundant Universal LCPU

Command
BKRST BKRST D n

Command
BKRSTP D n
BKRSTP

D : Head number of the devices to be reset (bits)

n : Number of the devices to be reset (BIN 16 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

D –– ––

n ––

Function
(1) Resets bit device n-points from the bit device designated by D .
Device Status

• Turns device n-points from annunciator (F) number designated by D OFF.

• Deletes annunciator number turned OFF from SD64 to SD79 and compresses remaining data
Annunciator (F)
forward.
• Stores number of annunciators stored from SD64 to SD79 at SD63.
Timer (T) • Sets the current value n-points from timer (T) or counter c designated by (C) to 0, and turns coil
Counter (C) contact OFF.
Bit devices other
• Turns OFF coil or contact n-points from the device designated by D .
than the above

(2) If the designated device is OFF, the device status will not change.

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• The n-bit range from the D , or device exceeds the range of that device.
(Error code: 4101)

7-64
 BKRST(P)

Program Example
1
(1) The following program turns OFF devices from M0 to M7 when X0 is turned ON.
[Ladder Mode] [List Mode]
2
Step Instruction Device

3
[Operation]
M9M8M7 M4 M3 M0 M9 M8M7 M4M3 M0 4
1 1100 11100 1100000000

Not changed

(2) The following program sets data from 2nd bit (b2) of D10 to 1st bit (b1) of D11 to 0 when X20
6
is turned ON.
[Ladder Mode] [List Mode]
Step Instruction Device
6

7
[Operation]
b15 b8 b7 b2 b1 b0 b15 b8b7 b2 b1b0 8
D10 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 D10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0

b15 b8 b7 b1 b0 b15 b8b7 b1 b0

D11 0 0 0 1 0 1 0 0 1 1 1 1 1 1 1 1 D11 0 0 0 1 0 1 0 0 1 1 1 1 1 1 0 0

7.4.3 Batch reset of bit devices (BKRST(P))

7.4 Bit processing instructions

7-65
 SER(P),DSER(P)

7.5 Data processing instructions

7.5.1 16-bit and 32-bit data searches (SER(P),DSER(P))

SER(P),DSER(P)

Basic High
performance Process Redundant Universal LCPU

Command
SER, DSER S1 S2 D n

Command
SERP, DSERP P S1 S2 D n

S1 : Search data or head number of the devices where the search data is stored (BIN 16/32 bits)
S2 : Data to be searched or head number of the devices where the data to be searched is stored (BIN 16 bits)
D : Head number of the devices where the search result will be stored (BIN 16 bits)
n : Number of searches (BIN 16 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S1 ––

S2 –– –– –– –– ––

D –– –– –– ––

n ––

Function
SER

(1) Searches n points from the 16-bit data of the device designated by S2 , regarding 16-bit data
of the device designated by S1 as a keyword. Then, the number of matches with the
keyword is stored at the device designated by D +1, and the first matched device number (in
the relative number from S2 ) is stored at the device designated by D .
Head number to be
Search data searched
S1 123 123
S2 10
S2 +1 500 Match data Search results
S2 +2 123 Search range D 3 Position of match
Relative value (n points) D +1 2 Number of matches
-123
S2 +(n-2) 20
S2 +(n-1) 123
123

(2) No processing is conducted if n is 0 or a negative value.

(3) If no matches are found in the search, the devices designated at D and D +1 become "0".

7-66
 SER(P),DSER(P)

DSER

(1) Searches n points from the device designated by S2 in 32-bit units (2 n points in 16-bit 1
units.) regarding 32-bit data of the device designated by S1 +1 and S1 as a keyword. Then,
the number of matches with the keyword is stored at the device designated by +1, and the
first matched device number (in the relative number from S2
D

) is stored at the device

2
designated by D .

Search data
Head number to be
searched
3
S1 +1. S1 5678901 5678901
S2 +1, S2 5678901 Match data
S2 +3, S2 +2 123456
Search range D
Search results
4
S2 +5, S2 -1 1 Position of match
(2 n points) D +1 2 Number of matches
Relative value
S2 +(n-3), S2 +(n-4) 5678901
S2 +(n-1), S2 +(n-2) 0 6
5678901

(2) No processing is conducted if n is 0 or a negative value. 6

(3) If no matches are found in the search, the devices designated at D and D +1 become "0".

7
If the data to be searched using the SER/DSER instruction is sorted in the
ascending order, searches can be accelerated by the use of the binary search
8
method, which is activated by turning SM702 *1 ON. However, correct searche
results are not obtained if SM702 is turned ON when the data to be searched is
not sorted in the ascending order.

7.5.1 16-bit and 32-bit data searches (SER(P),DSER(P))

7.5 Data processing instructions
*1: SM702 is the special relay for setting the search method.
• SM702 OFF: Sequential search method (linear search method) (Comparison with the search data starts
from the beginning of the data to be searched.)
• SM702 ON: Binary search method (Obtains the center value of the sorted array and decides if the
obtained value is larger or smaller than the search value, then, chooses the area for search between the
larger and smaller value divisions. By repeating this process, the area for search is narrowed down.)

Search order

Search data Data to be searched Data to be searched Data to be searched

500 100 100 100
200 200 200
300 300 300
Search range Compared with the
400 400 400
search data
500 500 Search range 500 Compared with the
600 Search range 600 Compared with the 600 search data
700 700 search data 700

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The location n-points from the device S2 exceeds the designated device range.
(Error code: 4101)
• The device specified by D exceeds the range of the corresponding device.
(For the Universal model QCPU, LCPU.) (Error code: 4101)

7-67
 SER(P),DSER(P)

Program Example
(1) The following program searches D100 to D105 for the contents of D0 when X20 is ON, and
stores the search results at W0 and W1.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
Search data Data to be searched
D0 123 D100 500
D101 123 Search results
D102 300 W0 2 Position of match
D103 123 W1 2 Number of matches
D104 32000
D105 122

(2) The following program searches D100 to D111 for the contents of D11 and D10 when X20 is
ON, and stores the search results at W0 and W1.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
Search data Data to be searched
D11, D10 56789051 D101, D100 200000
D103, D102 56789051 Search results
D105, D104 56789051 W0 2 Position of match
D107, D106 -30000 W1 3 Number of matches
D109, D108 56789051
D111, D110 30000

7-68
 SUM(P),DSUM(P)

7.5.2 16-bit and 32-bit data checks (SUM(P),DSUM(P))

SUM(P),DSUM(P)
1
Basic High
performance Process Redundant Universal LCPU
2

indicates an instruction symbol of SUM/DSUM.

3
Command
SUM, DSUM S D
4
Command
P S D
SUMP, DSUMP
6
S : Head number of the devices where the total number of bits of "1" is counted (BIN 16/32 bits)
D : Head number of the devices where the total number of the bits will be stored (BIN 16/32 bits) 6
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S –– 7
D –– ––

8
Function
SUM

7.5.2 16-bit and 32-bit data checks (SUM(P),DSUM(P))

7.5 Data processing instructions
From the 16-bit data in the device designated by S , stores the total number of bits where 1
is set, in the device designated by D .
b15 b8 b7 b0
S 1 10 0 10 1 100 1 100 0 1

Total number of bits where 1 is set

b15 b8 b7 b0
D 0 00 00 00 000 00 10 00

Stores the total number of bits where 1 is set in BIN.

(There are 8 bits where 1 is set in the example.)

DSUM
From the 32-bit data in the device designated by S , stores the total number of bits where 1
is set, in the device designated by D .
S +1 S

b31 b16b15 b0
100 1110 0 10 10 0 1 110 00 100 0 0 111 10 1 10

Total number of bits where 1 is set

b15 b8 b7 b0
D 00000000000 10000

Stores the total number of bits where 1 is set in BIN.

(There are 16 bits where 1 is set in the example.)

7-69
 SUM(P),DSUM(P)

Operation Error
(1) There are no operation errors associated with the SUM(P) or DSUM(P) instructions.

Program Example
(1) The following program stores the number of bits which are ON from X8 to X17 into D0 when
X10 is turned ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
X17 X8
0 0 10 10 1 100 00 0 1 11

Stores the total number of bits

where 1 is set at D0.

D0 7

(2) The following program stores the number of bits which are ON in D100 and D101 into D0
when X10 is turned ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
b31 b16 b15 b0
D100, D101 0 1 0 1 0 0 0 0 1 1 1 1 0 0 0 1 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1

Stores the total number of bits where 1 is set into D0.

D0 15

7-70
 DECO(P)

7.5.3 Decoding from 8 to 256 bits (DECO(P))

DECO(P)
1
Basic High
performance Process Redundant Universal LCPU
2

3
Command
DECO S D n
DECO
Command 4
DECOP S D n
DECOP

6
S : Data to be decoded or the number of the device where the data to be decoded is stored (BIN 16 bits)
D : Head number of the devices where the decoding result will be stored (Device name)
n : Valid bit length (1 to 8), 0: No processing (BIN 16 bits)
6
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S ––
7
D –– –– ––

n ––

8
Function
(1) Turns ON the bit position of , which corresponds to the binary value designated by the

7.5.3 Decoding from 8 to 256 bits (DECO(P))

7.5 Data processing instructions
D

lower n bits at S .
n=3

S 1 1 0 (Binary value = 6)

7 6 5 4 3 2 1 0
D 0 1 0 0 0 0 0 0

ON

(2) The value of n can be designated between 1 and 8.

(3) No processing is conducted if n 0, and there are no changes in the details of the device
designated at D .
(4) Bit devices are treated as 1 bit, and word devices as 16 bits.

7-71
 DECO(P)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The value of n is not in the 0 to 8 range. (Error code: 4100)

• The range 2n bits from D exceeds the range of the relevant device.
(Error code: 4101)

Program Example
(1) The following program decodes the 3 bits from X0 and stores the results at M10 when X20 is
ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
X2 X1 X0
0 1 1 0 When 6 is designated at X0 to X2

M17 M10
0 0 0 0 0 1 0 0 0 0 0 0 Decoding result

If 3 bits are designated as significant bits, 8 points are occupied.

7-72
 ENCO(P)

7.5.4 Encoding from 256 to 8 bits (ENCO(P))

ENCO(P)
1
Basic High
performance Process Redundant Universal LCPU
2

3
Command
ENCO S D n
ENCO
Command 4
ENCOP S D n
ENCOP

6
S : Head number of the device where the data to be encoded is stored (Device name)
D : Number of the device where the encoding result will be stored (BIN 16 bits)
n : Valid bit length (1 to 8), 0: No processing (BIN 16 bits)

Setting Internal Devices Constants

6
J \
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

–– –– ––
7
S

D –– ––

n ––

8
Function
(1) Stores the binary value corresponding to the bits which are "1" included in the 2n-bit data of

7.5.4 Encoding from 256 to 8 bits (ENCO(P))

7.5 Data processing instructions
S to D .
8 7 6 5 4 3 2 1 0
S 0 0 1 0 0 0 0 0 0

D 1 1 0 (Binary value = 6)

(2) The value of n can be designated at between 1 and 8.

(3) If n 0, there will be no operation, and the contents of D will not change.
(4) Bit devices are treated as 1 bit, and word devices as 16 bits.
(5) If more than 1 bit is at 1, processing will be conducted at the upper bit location.

7-73
 ENCO(P)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The value of n is not in the 0 to 8 range. (Error code: 4100)

• The range 2n bits from S exceeds the range of the relevant device.
(Error code: 4101)

• All data 2n bits from S is "0". (Error code: 4100)

Program Example
(1) The following program encodes the 3 bits from M10 when X20 is ON, and stores the results
at D8.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
M17 M10
0 0 0 0 0 0 0 0 1 0 0 0

If 3 bits are designated as significant bits, 8 points are occupied.

Storage device D8
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Encoding result

The location of the ON bit, counted from M10, is stored in BIN.

7-74
 SEG(P)

7.5.5 7-segment decode (SEG(P))

SEG(P)
1
Basic High
performance Process Redundant Universal LCPU
2

3
Command
SEG S D
SEG
Command
S D
4
SEGP SEGP

S : Data to be decoded or head number of the devices where the data to be decoded is stored (BIN 16 bits)
6
D : Head number of the devices where the decoding result will be stored (BIN 16 bits)

Setting
Data
Internal Devices
R, ZR
J \
U \G Zn
Constants
K, H
Other 6
Bit Word Bit Word

S ––

D –– –– 7

Function 8
(1) Decodes the data from 0 to F designated by the lower 4 bits of S to 7-segment display data,
and stores at D .

7.5.5 7-segment decode (SEG(P))

7.5 Data processing instructions
(2) If D is a bit device, indicates the head number of the devices storing the 7-segment display
data; if it is a word device, indicates the number of the device storing the data.
Before execution After execution
Y4F Y48
Bit device SEG K7 K2Y48 0 0 100 111

8 points

D8
b15 b8b7 b0
Word device SEG K7 D8 0 00000000 0 100 111

Upper 8 bits are 7-segment display data is

always filled with 0s. stored in lower 8 bits.

Operation Error
(1) There are no operation errors associated with the SEG(P) instruction.

7-75
 SEG(P)

7-segment decode display

S D
Configuration of 7
Hexa- Display Data
Bit Pattern Segments B7 B6 B5 B4 B3 B2 B1 B0
decimal

0 0000 0 0 1 1 1 1 1 1

1 0001 0 0 0 0 0 1 1 0

2 0010 0 1 0 1 1 0 1 1

3 0011 0 1 0 0 1 1 1 1

4 0100 0 1 1 0 0 1 1 0

5 0101 0 1 1 0 1 1 0 1
B0
6 0110 0 1 1 1 1 1 0 1
B5 B1
7 0111 B6 0 0 1 0 0 1 1 1

8 1000 0 1 1 1 1 1 1 1
B4 B2
9 1001 0 1 1 0 1 1 1 1
B3
A 1010 0 1 1 1 0 1 1 1

B 1011 0 1 1 1 1 1 0 0

C 1100 0 0 1 1 1 0 0 1

D 1101 0 1 0 1 1 1 1 0

E 1110 0 1 1 1 1 0 0 1

F 1111 0 1 1 1 0 0 0 1

Head number of bit device

Lowest bit of word device

Program Example
(1) The following program converts the data from XC to XF to 7-segment display data and
outputs it to Y38 to Y3F when X0 is turned ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Timing Chart]

X0

*1
Y38 to Y3F

*1: The data Y38 to Y3F will not change until the next data is output.

7-76
 DIS(P)

7.5.6 4-bit dissociation of 16-bit data (DIS(P))

DIS(P)
1
Basic High
performance Process Redundant Universal LCPU
2

3
Command
DIS S D n
DIS
Command 4
S D n
DISP DISP

6
S : Head number of the devices where data to be dissociated is stored (BIN 16 bits)
D : Head number of the devices where the dissociated data will be stored (BIN 16 bits)
n : Number of dissociations (1 to 4), 0: No processing (BIN 16 bits)
6
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S ––
7
D –– –– ––

n ––

8
Function
(1) Stores the lower n-digits (1 digit is 4 bits) of the 16-bit data designated by S at the lower 4

7.5.6 4-bit dissociation of 16-bit data (DIS(P))

7.5 Data processing instructions
bits n-points from the device designated by D .
b15 b12b11 b8 b7 b4 b3 b0 b15 b4 b3 b0
S D
D +1
n
D +2
D +3
Filled with 0s. Storage area

(2) The upper 12 bits n-points from the device designated by S become 0.
(3) The value of n can be designated at between 1 and 4.

(4) If n 0, there will be no processing, and the contents n-points from D will not change.

7-77
 DIS(P)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The range n-points from D exceeds the relevant device. (Error code: 4101)
• The value of n is outside the 0 to 4 range. (Error code: 4100)

Program Example

(1) The following program dissociates the 16-bit data from D0 into 4-bit groups, and stores from
D10 to D13 when X0 is ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
b15 b12 b11 b8 b7 b4 b3 b0 b15 b4 b3 b2 b1 b0
D0 1 1 0 0 1 0 0 1 0 1 0 1 0 0 0 1 D10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
D11 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
D12 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1
D13 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0

Filled with 0s. Storage area

7-78
 UNI(P)

7.5.7 4-bit linking of 16-bit data (UNI(P))

UNI(P)
1
Basic High
performance Process Redundant Universal LCPU
2

3
Command
UNI S D n
UNI
Command 4
UNIP S D n
UNIP

6
S : Head number of the devices where data to be linked is stored (BIN 16 bits)
D : Head number of the devices where the linked data will be stored (BIN 16 bits)
n : Number of links (1 to 4), 0: No processing (BIN 16 bits)

Internal Devices
6
Setting J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S –– –– –– ––
7
D –– ––

n ––

8
Function
(1) Links lower 4 bits of 16-bit data n-points from device designated by S to 16-bit device

7.5.7 4-bit linking of 16-bit data (UNI(P))

7.5 Data processing instructions
designated by D .
b15 b4b3 b0
S
S +1
S +2 b15 b12 b11 b8 b7 b4 b3 b0
S +3 D

Ignored Linked data

(2) The bits of the upper (4 n) digits of the device designated by D become 0.
(3) The value of n can be designated at between 1 and 4.

(4) If n 0, there will be no processing, and the contents of device D will not change.

7-79
 UNI(P)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The range n-points from S exceeds the relevant device. (Error code: 4101)
• The value of n is outside the 0 to 4 range. (Error code: 4100)

Program Example
(1) The following program links the lower 4 bits of D0 to D2 when X0 is ON, and stores them at
D10.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
b15 b4 b3 b2 b1 b0 b15 b8 b7 b0
D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 D10 0 0 0 0 1 0 0 1 0 1 0 1 0 0 0 1
D1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
D2 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1

Linked data

7-80
 NDIS(P),NUNI(P)

7.5.8 Dissociation or linking of random data (NDIS(P),NUNI(P))

NDIS(P),NUNI(P)
1
Basic High
performance Process Redundant Universal LCPU
2

3
indicates an instruction symbol of NDIS/NUNI.
Command
NDIS, NUNI S1 D S2
4
Command
NDISP, NUNIP P S1 D S2

6
S1 : Head number of the devices where data to be dissociated/linked is stored (BIN 16 bits)
D : Head number of the devices where the dissociated/linked data will be stored (BIN 16 bits) 6
S2 : Head number of the devices where the units of dissociation/linking will be stored (BIN 16 bits)

Setting Internal Devices J \

R, ZR Zn Constants Other
Data Bit Word Bit Word
U \G
7
S1 –– ––

D –– ––

S2 –– ––
8

Function

7.5.8 Dissociation or linking of random data (NDIS(P),NUNI(P))

7.5 Data processing instructions
NDIS

(1) Dissociates data stored in device numbers starting from that designated at S1 into the
number of individual bits designated at S2 , and stores this data in device numbers starting
from that designated at D .
Designation of the number of dissociated bits
S2 6
S2 +1 8
S2 6
S2 +3 4
S2 +4 8
S2 +5 10
S2 +6 3
S2 +7 0 Designation of the end of setting
b15b14b13 b6b5 b0 b5 b0
S1 Number of bits D
designated at S2
b7 b0
Number of bits D +1
designated at S2 +1
b15 b8b7 b4b3 b0 b5 b0
S1 +1 Number of bits D +2
designated at S2 +2
b3 b0
Number of bits D +3
designated at S2 +3
b7 b0
Number of bits D +4
designated at S2 +4
b12 b10b9 b0 b9 b0
S1 +2 Number of bits D +5
designated at S2 +5
b2 b0
Number of bits D +6
designated at S2 +6

7-81
 NDIS(P),NUNI(P)

(2) The number of dissociated bits designated at S2 can be designated within a range of 1 to 16
bits.
(3) Bits from the device number designated at S2 to the device number where "0" is stored are
processed as dissociated bits.
(4) Do not overlap the device range for data to be dissociated( S1 to end range of S1 ) with the
device range which stores the dissociated data ( D to end range of D ). If overlapped, the
correct operation result may not be obtained.
(5) Do not specify the same device number for S1 , S2 , and D . If the same device is specified
for S1 , S2 , and D , the operation does not work correctly.
NUNI
(1) Links individual bits of data stored into the area starting from the device number designated
by S1 in the number of bits specified by S2 , and stores them following the device number
designated by D .
Designation of the number of linked bits
S2 6
S2 +1 8
S2 +2 6
S2 +3 4
S2 +4 8
S2 +5 10
S2 +6 3
S2 +7 0 Designation of the end of setting
b5 b0 b15b14b13 b6 b5 b0
S1 Number of bits D
designated at S2
b7 b0
Number of bits
S1 +1 designated at S2 +1

b5 b0 b15 b8 b7 b4 b3 b0
S1 +2 Number of bits D
designated at S2 +2
b4 b0
S1 +3 Number of bits
designated at S2 +3
b7 b0
S1 +4 Number of bits
designated at S2 +4
b9 b0 b12 b10 b0
S1 +5 Number of bits D
designated at S2 +5
b2 b0
S1 +6 Number of bits
designated at S2 +6

(2) The number of bits to be linked as designated by S2 can be within a range of from 1 to 16.
(3) Processing will be performed on the number of bits to be linked from the device number
designated by S2 to the device number storing "0".

(4) Do not overlap the device range for data to be linked( S1 to end range of S1 ) with the device
range which stores the linked data ( D to end range of D ). If overlapped, the correct
operation result may not be obtained.
(5) Do not overlap the device numbers to be designated at S1 , S2 and D . If overlapped, correct
operation is not possible.

7-82
 NDIS(P),NUNI(P)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and 1
an error code is stored into SD0.
• The number of bits to be dissociated or linked as specified by S2 , or the device use range
specified by S1 or D exceeds the final device number of their respective devices. 2
(Error code: 4101)
• The number of bits for dissociation or linking specified by has not been set within the
3
S2
range of from 1 to 16 bits. (Error code: 4100)

Program Example 4
(1) The following program dissociates data of 4, 3, and 6 bits respectively from the lower bits of
D0, and stores them from D10 to D12.
6
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]

7.5.8 Dissociation or linking of random data (NDIS(P),NUNI(P))

7.5 Data processing instructions
b12 b7 b6 b4b3 b0
1 1 0 1 0 1 1 0 0 0 1 1 1 1 0 0 D0
4 bits b3 b0
0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 D10
Filled with 0s.
3 bits b2 b0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 D11
Filled with 0s.
The data in these
6 bits b5 b0
bits is ignored.
0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 D12
Filled with 0s.

7-83
 NDIS(P),NUNI(P)

(2) The following program links the lower 4 bits of data from D10, the lower 3 bits of data from
D11, and the lower 6 bits of data from D12, and stores at D0.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
b3 b0
D10 0 0 0 1 0 1 1 0 0 1 1 0 1 1 0 0
4 bits
b2 b0
D11 0 1 0 1 1 1 1 0 1 0 0 0 1 1 0 1
3 bits
b5 b0
D12 0 0 1 1 1 0 1 1 0 0 1 0 1 1 0 0
6 bits

The data in these bits is ignored. D0 0 0 0 1 0 1 1 0 0 1 0 1 1 1 0 0

b12 b7b6 b4b3 b0
Filled with 0s.

7-84
 WTOB(P),BTOW(P)

7.5.9 Data dissociation and linking in byte units

(WTOB(P),BTOW(P)) 1
WTOB(P),BTOW(P)

Basic High
performance Process Redundant Universal LCPU
2

3
indicates an instruction symbol of WTOB/BTOW.

Command 4
S D n
WTOB, BTOW
Command
WTOBP, BTOWP P S D n 6

S : Head number of the devices where data to be dissociated/linked in byte units is stored (BIN 16 bits) 6
D : Head number of the devices where the result of dissociated/linking in byte units will be stored (BIN 16 bits)
n : Number of byte data to be dissociated/linked (BIN 16 bits)

Setting Internal Devices

R, ZR
J \
U \G Zn
Constants
Other
7
Data Bit Word Bit Word K, H

S –– –– ––

D –– –– –– 8
n ––

Function

7.5.9 Data dissociation and linking in byte units (WTOB(P),BTOW(P))

7.5 Data processing instructions
WTOB
(1) Dissociates n-bytes of the 16-bit data stored into the area starting from the device number
designated by S , and stores them following the device designated by D .
b15 b8b7 b0 b15 b8 b7 b0
S Upper byte Lower byte D 00H Data of lower byte
S +1 Upper byte Lower byte D +1 00H Data of upper byte
D +2 00H Data of lower byte
n n bytes
S +( -1) *1 Upper byte Lower byte D +3 00H Data of upper byte
2
*1: Fractions that follow the decimal
point are rounded up. D +(n-2) 00H Data of lower byte
D +(n-1) 00H Data of upper byte

For example, if n 5, data through the lower 8 bits of S to ( S +2) would be stored from ( D

to D +4).
b15 b8b7 b0 b15 b8 b7 b0
S 12H 39H D 00H 39H
S +1 56H 78H D +1 00H 12H
When n=5
S +2 FEH DCH D +2 00H 78H
bytes
D +3 00H 56H
Ignored when n=5 D +4 00H DCH

7-85
 WTOB(P),BTOW(P)

(2) Setting the number of bytes with n automatically determines the range of the 16-bit data
designated by S and the range of the devices to store the byte data designated by D .
(3) No processing will be conducted when the number of bytes designated by n is "0".
(4) The "00H" code will automatically be stored at the upper 8 bits of the byte storage device
designated by D .
b15 b8 b7 b0 b15 b8 b7 b0
D12 32H 31H 00H 31H
D11
D13 34H 33H 00H 32H
D12
D14 36H 35H 00H 33H
D13
D14 00H 34H
00H 35H
D15
D16 00H 36H

Stores 00H.

n
(5) Even though the range of the device with the data to be devided ( S to S +( 2 -1)) is the
same as the range of the device with the devided data ( D to D +(n-1)), the instruction
operates correctly.

BTOW
(1) Links the lower 8 bits of the 16-bit data in n words stored in the area starting from the device
designated by S in 1-word units and stores it into the area starting from the device
designated by D . The upper 8 bits of n-word data stored in the area starting from the device
designated by S will be ignored. Further, if n is an odd number, 0 is stored at the upper 8
bits of the device where the nth byte data is stored.
b15 b8b7 b0 b15 b8 b7 b0
S Data of the 1st byte D Data of the 2nd byte Data of the 1st byte
S +1 Data of the 2nd byte D Data of the 4th byte Data of the 3rd byte
n bytes S +2 Data of the 3rd byte
n *1
S +3 Data of the 4th byte D +( -1) Data of the nth byte Data of the (n-1) byte
2
*1: Figures after the decimal point are rounded up.
S +(n-1) Data of the nth byte

Upper bytes are ignored.

For example, if n 5, the lower 8 bits of data from S to ( S +4) are linked and stored at D

to ( D +2).
b15 b8b7 b0 b15 b8 b7 b0
S 00H 12H D 34H 12H
S +1 00H 34H D +1 78H 56H
If n = 5 S +2 00H 56H D +2 00H FEH
S +3 00H 78H
+4 00H is set.
S 00H FEH

(2) Setting the number of bytes with n automatically determines the range of the byte data
designated by S and the range of the devices to store the linked data designated by D .
(3) No processing will be conducted when the number of bytes designated by n is "0".

7-86
 WTOB(P),BTOW(P)

(4) The upper 8 bits of the byte storage device designated by S are ignored, and the lower 8
bits are used.
1
(5) Linking is correctly processed even when the device range ( S to S +(n-1)) where the data
n
to be linked is stored overlaps with the device range ( D to D +( 2 -1)) where the linked data
will be stored. 2
For example, the following will take place in a case where the lower 8 bits of D11 to D16 are
to be stored at D12 to D14:
b15 b8 b7 b0 b15 b8 b7 b0 3
D11 00H 31H D11 00H 31H
D12 00H 32H D12 32H 31H
D13
D14
00H
00H
33H
34H
D13
D14
34H
36H
33H
35H
4
D15 00H 35H D15 00H 35H
D16 00H 36H D16 00H 36H
6
Operation Error
6
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The range of the number of bytes designated by n following the device number
7
designated by S exceeds the relevant device range. (Error code: 4101)
• The range of the number of bytes designated by n following the device number
designated by D exceeds the relevant device range. (Error code: 4101) 8

Program Example
(1) The following program dissociates the data at D10 to D12 in byte units and stores it at D20

7.5.9 Data dissociation and linking in byte units (WTOB(P),BTOW(P))

7.5 Data processing instructions
to D25 when X0 is turned ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
b15 b8 b7 b0 b15 b8 b7 b0
D10 FDH 58H D20 00H 58H
D11 57H E2H D21 00H FDH
D12 34H 44 H D22 00H E2H
00H 57H 6 bytes
D23
D24 00H 44H
D25 00H 34H

7-87
 WTOB(P),BTOW(P)

(2) The following program links the lower 8 bits of data from D20 through D25 and stores the
result at D10 to D12 when X0 is turned ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
b15 b8 b7 b0 b15 b8 b7 b0
D20 00H 78H D10 12H 78H
D21 31H 12H D11 55H 49H
D22 36H 49H D12 31H 67H
6 bytes 44H 55H
D23
D24 48H 67H
D25 49H 31H

Upper byte is ignored.

7-88
 MAX(P),DMAX(P)

7.5.10 Maximum value search for 16- and 32-bit data

(MAX(P),DMAX(P)) 1
MAX(P),DMAX(P)

Basic High
performance Process Redundant Universal LCPU
2

3
indicates an instruction symbol of MAX/DMAX.

Command 4
MAX, DMAX S D n

Command
MAXP ,DMAXP P S D n 6

S : Head number of the devices where a maximum value is searched (BIN 16/32 bits) 6
D : Head number of the devices where the maximum value search result will be stored (BIN 16/32 bits)
n : Number of data blocks to be searched (BIN 16 bits)

Setting Internal Devices

R, ZR
J \
U \G Zn
Constants
Other
7
Data Bit Word Bit Word K, H

S –– –– ––

D –– –– –– 8
n ––

Function

7.5.10 Maximum value search for 16- and 32-bit data (MAX(P),DMAX(P))
7.5 Data processing instructions
MAX
(1) Searches in the n points of 16-bit BIN data, from the device designated by S , for the
maximum value and stores the searched maximum value at the device designated by D .
Starts the search from the device designated by S and stores the location, specified in the
number of points counted from S , of the device where the maximum value is found first at
D +1 and stores the number of the found minimum values at D +2.
S 1234 (BIN)
S +1 5678 (BIN)
D 5678 (BIN) Maximum value
S +2 5678 (BIN)
n D +1 2 Location
D +2 2 Quantity
S +(n-2) -5214 (BIN)
S +(n-1) 5555 (BIN)

7-89
 MAX(P),DMAX(P)

DMAX

(1) Searches in the n points of 32-bit BIN data, from the device designated by S , for the
maximum value and stores the searched maximum value at the device designated by D

and D +1.
Starts the search from the device designated by S and stores the location, specified in the
number of points counted from S , of the device where the maximum value is found first at
D +2 and stores the number of the found minimum values at D +3.

S +1, S 54321000 (BIN)

S +3, S +2 4321000 (BIN) D +1, D 54321000 (BIN) Maximum value
S +5, S +4 3254000 (BIN) n D +2 1 Location
S +7, S +6 54321000 (BIN) D +3 2 Quantity
S +9, S +8 12345678 (BIN)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The n-bit range from the S , or device exceeds the range of that device.
(Error code: 4101)
• The device specified by D exceeds the range of the corresponding device.
(For the Universal model QCPU, LCPU.) (Error code: 4101)

Program Example
(1) The following program subtracts, when X1C is turned ON, the data stored at D100 to D103
from the data stored at R0 to R3, and searches in the results of subtraction for the maximum
value, then, stores it at D200 to D202.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
b15 b0 b15 b0 b15 b0
D100 4321 (BIN) R0 5000 (BIN) D150 -679 (BIN)
D101 5432 (BIN) R1 4000 (BIN) D151 1432 (BIN)
D102 4444 (BIN) R2 4000 (BIN) D152 444 (BIN)
D103 5000 (BIN) R3 6000 (BIN) D153 -1000 (BIN)
D200 1432 Maximum value
D201 2 Location
D0 4 D202 1 Quantity

7-90
 MAX(P),DMAX(P)

(2) The following program searches for the maximum value from the32-bit data at D0 to D7, and
stores it at D100 to D103 when X20 is turned ON.
[Ladder Mode] [List Mode]
1
Step Instruction Device
2

[Operation] 3
D1, D0 3786213 (BIN) D101, D100 8744740
D3, D2
D5, D4
-3235 (BIN)
8744740 (BIN)
D102
D103
3
1
4
D7, D6 7141821 (BIN)

7.5.10 Maximum value search for 16- and 32-bit data (MAX(P),DMAX(P))
7.5 Data processing instructions

7-91
 MIN(P),DMIN(P)

7.5.11 Minimum value search for 16- and 32-bit data

(MIN(P),DMIN(P))
MIN(P),DMIN(P)

Basic High
performance Process Redundant Universal LCPU

indicates an instruction symbol of MIN/DMIN.

Command
MIN, DMIN S D n

Command
P S D n
MINP, DMINP

S : Head number of the devices where a minimum value is searched (BIN 16/32 bits)
D : Head number of the devices where the minimum value search result will be stored (BIN 16/32 bits)
n : Number of data blocks to be searched (BIN 16 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S –– –– ––

D –– –– ––

n ––

Function
MIN
(1) Searches in the n points of 16-bit BIN data, from the device designated by S , for the
minimum value and stores searched minimum value at the device designated by D .
Starts the search from the device designated by S and stores the location, specified in the
number of points counted from S , of the device where the minimum value is found first at
D +1 and stores the number of the found minimum values at D +2.
S 5015 (BIN)
S +1 6192 (BIN)
D 5015 (BIN) Minimum value
S +2 5571 (BIN) n D +1 1 Location
D +2 2 Quantity
S +(n-2) 5015 (BIN)
S +(n-1) 5571 (BIN)

7-92
 MIN(P),DMIN(P)

DMIN

(1) Searches in the n points of 32-bit BIN data, from the device designated by S , for the 1
minimum value and stores searched minimum value at the devices designated by D and
+1.
D

Starts the search from the device designated by S and stores the location, specified in the
2
number of points counted from S , of the device where the minimum value is found first at
D +2 and stores the number of the found minimum values at D +3. 3
S 22342001 (BIN)
D +1, D 22342001 (BIN) Minimum value
S +2 37282010 (BIN)
D +2 1 Location
S +4
S +6
22342001 (BIN)
59872019 (BIN) D +3 2 Quantity 4

6
Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and 6
an error code is stored into SD0.
• The n-bit range from the device specified by exceeds the range of the corresponding
7
S

device. (Error code: 4101)

• The device specified by D exceeds the range of the corresponding device.
(For the Universal model QCPU, LCPU.) (Error code: 4101)
8
Program Example
(1) The following program adds, when X1C is turned ON, the data stored at D100 to D103 and

7.5.11 Minimum value search for 16- and 32-bit data (MIN(P),DMIN(P))
7.5 Data processing instructions
the data stored at R0 to R3, and searches in the results of addition for the minimum value,
then, stores it at D200 to D202.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
b15 b0 b15 b0 b15 b0
D100 5542 (BIN) R0 5500 (BIN) D150 11042 (BIN)
D101 5857 (BIN) R1 4000 (BIN) D151 9857 (BIN)
+
D102 4590 (BIN) R2 4500 (BIN) D152 9090 (BIN)
D103 4450 (BIN) R3 6000 (BIN) D153 10450 (BIN)
D200 9090 Minimum value
D201 3 Location
D0 4 D202 1 Quantity

7-93
 MIN(P),DMIN(P)

(2) The following program, when X20 is turned ON, searches for the minimum value from the
32-bit data contained from D0 to D7, and stores it from D100 to D103.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
D1,D0 57020175 (BIN) D101,D100 69386
D3,D2 2070166 (BIN) D102 4
D5,D4 3596045 (BIN) D103 1
D7,D6 69386 (BIN)

7-94
 SORT,DSORT

7.5.12 BIN 16 and 32 bits data sort operations (SORT,DSORT)

SORT,DSORT
1
Basic High
performance Process Redundant Universal LCPU
2

3
indicates an instruction symbol of SORT/DSORT.

Command
SORT, DSORT S1 n S2 D1 D2 4

S1 : Head device number in the table to be sorted (BIN 16/32 bits) 6

n : Number of data blocks to be sorted (BIN 16 bits)
S2 : Number of data blocks to be compared in one sort operation (BIN 16 bits)
D1 : Number of the bit device to be turned ON at the completion of the sort operation (bits)
6
D2 : Device reserved for the system (BIN 16 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
7
S1 –– –– ––

n ––

S2 –– 8
D1 –– –– ––

D2 –– –– ––

7.5.12 BIN 16 and 32 bits data sort operations (SORT,DSORT)

7.5 Data processing instructions
Function
SORT

(1) Sorts (rearranges data) BIN 16-bit data n points from S1 in ascending or descending order.
Sort order is designated by the ON/OFF status of SM703:
• When SM703 is OFF: Ascending order sort
• When SM703 is ON : Descending order sort
S -124
Data before sort When SM703 = OFF S +1 -10
Sort in the ascending order
S 35 S +2 35
S +1 -10 S +3 500
S +2 500
S +3 -124
S 500
S +1 35
Sort in the descending order
When SM703 = ON S +2 -10
S +3 -124

7-95
 SORT,DSORT

(2) Several scans are required for sorts performed by the SORT instruction. The number of
scans executed until completion is the value obtained by dividing the maximum number of
times executed until the completion of the sort by the number of data blocks compared at
one execution designated by S2 . (Decimal fractions are rounded up.)When the value of S2
is increased, the number of scans until completion of the sort is reduced, but the amount of
time per scan is lengthened.
(3) The maximum number of executions until completion of the sort should be calculated
according to the following equation:
The maximum number of executions until completion (n) (n - 1) / 2 [times executed]

Example
When n 10, the number of executions is obtained as 10 (10 - 1) / 2 45 [times executed].
If S2 2, then the number of scans until the completion of sort is calculated as
45/2 22.5 23 [scans].

(4) The device designated by D1 (the completion device) is turned OFF by the execution of the
SORT instruction, and turned ON when the sort is completed. Because the device
designated by D1 is maintained in the ON state after the completion of the sort, the user
must turn it OFF if required.

(5) The 2 points from the device designated by D2 are used by the system during the execution
of the SORT instruction. These 2 points from the device designated by D2 should therefore
not be used by the user.
Changing these points may cause an error code to be returned (Error code: 4100).
(6) If the value of n is changed during the execution of the SORT instruction, the sort will be
conducted in accordance with the number of sort data blocks after the change.
(7) If the execution command is turned OFF during the execution of the SORT instruction, the
sort is suspended. The sort resumes from the beginning when the execution command is
turned ON again.
(8) To execute another sort operation immediately after the completion of the previous sort, turn
OFF the execution command once, then turn it ON.
DSORT

(1) Sorts (rearranges data) BIN 32-bit data n points from S1 in ascending or descending order.
Sort order is designated by the ON/OFF status of SM703:
• When SM703 is OFF : Ascending order sort
• When SM703 is ON : Descending order sort
S1 +1 , S1 -1000
Data before sort When SM703 = OFF S1 +3 , S1 +2 -124
Sort in the ascending order
S1 +1 , S1 35000 S1 +5 , S1 +4 500
S1 +3 , S1 +2 -1000 S1 +7 , S1 +6 35000
S1 +5 , S1 +4 500
S1 +7 , S1 +6 -124
S1 +1 , S1 35000
S1 +3 , S1 +2 500
When SM703 = ON Sort in the descending order
S1 +5 , S1 +4 -124
S1 +7 , S1 +6 -1000

7-96
 SORT,DSORT

(2) Several scans are required for sorts performed by the DSORT instruction. The number of
scans executed until completion is the value obtained by dividing the maximum number of
times executed until the completion of the sort by the number of data blocks compared at 1
one execution designated by S2 . (Decimal fractions are rounded up.)When the value of S2
is increased, the number of scans until completion of the sort is reduced, but the amount of
time per scan is lengthened. 2
(3) The maximum number of executions until completion of the sort should be calculated
according to the following equation:
The maximum number of executions until completion (n) (n 1)/2 [times executed]
3

Example
4
When n 10, the number of executions is obtained as 10 (10 1)/2 45 [times executed].
If S2 2, then the number of scans until the completion of sort is calculated as
45/2 22.5 23 [scans]. 6
(4) The device designated by D1 (the completion device) is turned OFF by the execution of the
SORT instruction, and turned ON when the sort is completed. Because the device desig-
nated by D1 is maintained in the ON state after the completion of the sort, the user must turn 6
it OFF if required.

(5) The 2 points from the device designated by D2 are used by the system during the execution
7
of a DSORT instruction. These 2 points from the device designated by D2 should therefore
not be used by the user.
Changing these points may cause an error code to be returned (Error code: 4100).
8
(6) If the value of n is changed during the execution of the SORT instruction, the sort will be
conducted in accordance with the number of sort data blocks after the change.
(7) If the execution command is turned OFF during the execution of the SORT instruction, the
sort is suspended. The sort resumes from the beginning when the execution command is

7.5.12 BIN 16 and 32 bits data sort operations (SORT,DSORT)

7.5 Data processing instructions
turned ON again.
(8) To execute another sort operation immediately after the completion of the previous sort, turn
OFF the execution command once, then turn it ON.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• For the SORT(P) instruction, the range for n points starting from the device at S1 exceeds
the corresponding device range. (Error code: 4101)

• For the DSORT(P) instruction, the range for 2 n points starting from the device at S1
exceeds the corresponding device range. (Error code: 4101)

• The device range of the (n/2 n) points starting from the device designated by S1

overlaps with the device range of the 2 points starting from the device designated by D2 .
(Error code: 4101)

• S2 is 0 or is a negative value. (Error code: 4100)

7-97
 SORT,DSORT

Program Example
(1) The following program sorts the BIN 16-bit data in 10 points from D0 in the ascending/
descending order when X10 is turned ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
Data after sort
D0 -999
Data before sort D1 -1
X0 OFF
D0 100 D2 100
D1 -1 D3 12345
D2 12345
D3 -999
D0 12345
X0 ON D1 100
D2 -1
D3 -999

(2) The following program sorts the BIN 32-bit data in 20 points from D0 in ascending/
descending order when X10 is turned ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
Data before sort
D1, D0 -99999
D3, D2 -1111
Data before sort
X0 OFF D5, D4 1
D1, D0 456789
D7, D6 5000
D3, D2 -1111
D9, D8 456789
D5, D4 5000
D7, D6 -1 D1, D0 456789
D9, D8 -99999 D3, D2 5000
X0 ON
D5, D4 1
D7, D6 -1111
D9, D8 -99999

7-98
 WSUM(P)

7.5.13 Calculation of totals for 16-bit data (WSUM(P))

WSUM(P)
1
Basic High
performance Process Redundant Universal LCPU
2

3
Command
WSUM S D n
WSUM
Command
n
4
WSUMP WSUMP S D

S : Head number of the devices where data to be summed are stored (BIN 16 bits)
6
D : Head number of the devices where the sum will be stored (BIN 32 bits)
n : Number of data blocks (BIN 16 bits)

Setting Internal Devices J \ Constants

6
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S –– –– –– ––

D –– ––
7
n ––

8
Function
(1) Adds all 16-bit BIN data for n blocks from the device designated at S , and stores it in the

7.5.13 Calculation of totals for 16-bit data (WSUM(P))

7.5 Data processing instructions
device designated at D .
S 4444 (BIN)
S +1 3333 (BIN)
S +2 1234 (BIN) n D + 1, D 13914 (BIN)
S +3 5426 (BIN)
S +4 329 (BIN)
S +5 10000 (BIN)

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• The n-bit range from the S , or device exceeds the range of that device.
(Error code: 4101)

7-99
 WSUM(P)

Program Example
(1) The following program adds the 16-bit BIN data from D10 to D14, and stores it in D100 and
D101 when X1C is turned ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]

D10 4500 (BIN)

D11 2500 (BIN)
D12 3276 (BIN) D101,D100 14948 (BIN)
D13 6780 (BIN)
D14 4444 (BIN)

7-100
 DWSUM(P)

7.5.14 Calculation of totals for 32-bit data (DWSUM(P))

DWSUM(P)
1
Basic High
performance Process Redundant Universal LCPU
2

3
Command
DWSUM S D n
DWSUM
Command 4
DWSUMP S D n
DWSUMP

6
S : Head number of the devices where data to be summed are stored (BIN 32 bits)
D : Head number of the devices where the sum will be stored (BIN 64 bits)
n : Number of data blocks (BIN 16 bits)

Internal Devices
6
Setting J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

7
S –– –– –– ––

D –– –– ––

n ––

8
Function
(1) Adds all 32-bit BIN data stored in n points of devices starting from the one designated by S ,

7.5.14 Calculation of totals for 32-bit data (DWSUM(P))

7.5 Data processing instructions
and stores the result to 4 points of devices (4 words) starting from the one designated by D .
S + 1, S 32767000 (BIN)
S + 3, S +2 6000 (BIN)
S + 5, S +4 35392000 (BIN) n D + 3 to D 68640000 (BIN)
S + 7, S +6 11870000 (BIN)
S + 9, S +8 12345000 (BIN)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The n-bit range from the S , or device exceeds the range of that device.
(Error code: 4101)
• The device specified by D exceeds the range of the corresponding device.
(For the Universal model QCPU, LCPU.) (Error code: 4101)

7-101
 DWSUM(P)

Program Example
(1) The following program adds the 32-bit BIN data at D100 to D107, and stores the result at
D10 and D13 when X20 is turned ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
D101,D100 11245600 (BIN)
D103,D102 27543200 (BIN)
D13 to D10 23672600 (BIN)
D105,D104 558800 (BIN)
D107,D106 15675000 (BIN)

7-102
 MEAN(P),DMEAN(P)

7.5.15 Calculation of averages for 16-bit or 32-bit data

(MEAN(P),DMEAN(P)) 1
MEAN(P),DMEAN(P)

High
Ver. 2
Basic performance Process Redundant Universal LCPU

• QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later.

• QnUDE(H)CPU: The serial number (first five digits) is "10102" or later. 3
indicates an instruction symbol of MEAN/DMEAN.

Command
4
MEAN,DMEAN S D n

Command
P S D n
6
MEANP,DMEANP

S : Head number of the devices where the data to be averaged are stored (BIN16/32 bits)
6
D : Head number of the devices where the average will be stored (BIN 16/32 bits)
n : Number of data or number of the devices where the number of data are stored(Setting range: 1 to 32767)
(BIN 16 bits)

Setting Internal Devices J \ Constants

7
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S –– –– –– ––

D –– –– –– ––
8
n –– ––

7.5.15 Calculation of averages for 16-bit or 32-bit data (MEAN(P),DMEAN(P))

7.5 Data processing instructions
Function
MEAN(P)
(1) This instruction calculates the mean of 16-bit BIN data stored in n-point devices starting from
the device specified by S , and then stores the result into the device specified by D .

S
S ＋1 Average value D
S ＋2 n

S ＋n−1

(2) If the value calculated is not integer, this instruction will drop the number of decimal places.
(3) If the value specified by n is 0, the instruction will be not processed.
DMEAN(P)
(1) This instruction calculates the mean of 32-bit BIN data stored in n-point devices starting from
the device specified by S , and then stores the result into the device specified by D .
S ＋1, S D ＋1, D
Average value
S ＋3, S ＋2
n

S ＋2n−1, S ＋2n−2

(2) If the value calculated is not integer, this instruction will drop the number of decimal places.
(3) If the value specified by n is 0, the instruction will be not processed.

7-103
 MEAN(P),DMEAN(P)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an
error code is stored into SD0.
• The value specified by n is other than 0 to 32767. (Error code: 4100)

• The range of the n-point devices starting from the device specified by S exceeds the
range of the devices specified by D . (Error code: 4101)

Program Example
(1) The following program stores the average value of 16-bit data stored from D0 to D2 into
D10,when M0 is turned on.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
D0 105 (BIN)
D1 555 (BIN) D10 550 (BIN)
D2 990 (BIN)

(2) The following program stores the average value of 32-bit data stored from D0 to D5 into D10
and D11, when M0 is turned on.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
D1,D0 623541 (BIN)
D3,D2 4753647 (BIN) D11,D10 2101176 (BIN)
D5,D4 926342 (BIN)

7-104
 FOR,NEXT

7.6 Structure creation instructions

1
7.6.1 FOR to NEXT instruction loop (FOR,NEXT)
FOR,NEXT
2
Basic High
Process Redundant Universal LCPU
3
performance

4
FOR n
FOR
Repeat program
6
NEXT NEXT

n : Number of repetitions of FOR to NEXT loop (1 to 32767) (BIN 16 bits)

6
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data K, H

n
Bit Word Bit Word
––
7

8
Function
(1) When the processing in the FOR to NEXT loop is executed n-times without conditions, the
step following the NEXT instruction will be executed.

7.6.1 FOR to NEXT instruction loop (FOR,NEXT)

7.6 Structure creation instructions
(2) The value of n can be designated at between 1 and 32767. If it is designated from 32768
to 0, the processing which is executed when n=1 will be performed.
(3) If you do not desire to execute the processing called for within the FOR to NEXT loop, use
the CJ or SCJ instruction to jump.
(4) FOR instructions can be nested up to 16 deep.

FOR K5
X

FOR K3
X1

FOR instructions can be

FOR K100 nested up to 16 deep.
X2

NEXT

NEXT

NEXT

7-105
 FOR,NEXT

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• An END, FEND or GOEND instruction was executed before the execution of a NEXT
instruction and after the execution of a FOR instruction. (Error code: 4200)
• A NEXT instruction is executed prior to the execution of a FOR instruction.
(Error code: 4201)
• A STOP instruction has been inserted within the FOR to NEXT loop.
(Error code: 4200)
• The 17th FOR instruction is executed when FOR instructions have been nested.
(Error code: 4202)

Program Example
(1) The following program executes the FOR to NEXT loop when X8 is OFF, and does not
execute it when X8 is ON.
[Ladder Mode] [List Mode]
Step Instruction Device

7-106
 FOR,NEXT

Remark
1. To force an end to the repetitious execution of the FOR to NEXT loop during the
1
execution of the loop, insert a BREAK instruction. See 7.6.2 for details
concerning the use of the BREAK instruction.
2. Use the EGP/EGF instruction to perform the pulse operation of an
2
index-modified program between the FOR and NEXT instructions. Note,
however, that rise and fall instructions are not available on the operation output
side. Refer to 5.2.5 for details of the EGP/EGF instruction. The program
3
samples are shown below:

7
3. Branching into a FOR to NEXT loop using a JMP or other branch instruction
from the outside of the FOR to NEXT loop is not possible.
8

7.6.1 FOR to NEXT instruction loop (FOR,NEXT)

7.6 Structure creation instructions

7-107
 BREAK(P)

7.6.2 Forced end of FOR to NEXT instruction loop (BREAK(P))

BREAK(P)

Basic High
performance Process Redundant Universal LCPU

Command
BREAK D Pn
BREAK
Command
BREAKP BREAKP D Pn

D : Number of the device where the remaining number of loops will be stored (BIN 16 bits)
Pn : Number of the pointer (device name (pointer)) where the program is branched at the forced end of a loop.

Setting Internal Devices J \ Other

R, ZR U \G Zn Constants
Data Bit Word Bit Word P

D –– ––

Pn –– ––

Function
(1) Forces an end to a FOR to NEXT instruction loop and shifts the operation to the pointer
specified by Pn. Only a pointer within the same program file can be assigned to Pn. If a
pointer of the other program file is used, an operation error will be returned.

FOR K **
If the BREAK instruction is not executed,
Forced end condition program returns to the FOR instruction
BREAK D Pn as many times as the number specified
When forced end condition is satisfied with the FOR instruction.
NEXT

Pn

(2) The remaining number of the FOR to NEXT instruction loop times is stored at D .
Note that the remaining number includes the operation when the BREAK instruction is
executed.
(3) The BREAK instruction can be used only during the execution of a FOR to NEXT instruction
loop.
(4) The BREAK instruction can be used only when there is only one level of nesting. When an
end is forced to the multiple nesting levels, execute the same number of BREAK instructions
for the nesting levels.

7-108
 BREAK(P)

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The BREAK instruction is used in a case other than with the FOR to NEXT instruction 2
loop. (Error code: 4203)
• The jump destination for the pointer designated by Pn does not exist.
(Error code: 4210) 3
• The pointer of another program file is designated for Pn. (Error code: 4210)

4
Program Example
(1) The following program forces the FOR to NEXT loop to end when the value of D0 reaches
30 (when the FOR to NEXT loop has been executed 30 times).
6
[Ladder Mode] [List Mode]
Step Instruction Device 6

7.6.2 Forced end of FOR to NEXT instruction loop (BREAK(P))

7.6 Structure creation instructions
Remark
The value 71 is stored at D1 when the BREAK instruction is executed.

7-109
 CALL(P)

7.6.3 Subroutine program calls (CALL(P))

CALL(P)

Basic High
performance Process Redundant Universal LCPU

Command
CALL CALL Pn

Command
CALLP CALLP Pn

Command
CALL CALL Pn S1 to S5

Command
CALLP CALLP Pn S1 to S5

Pn : Head pointer number of a subroutine program (Device name)

S1 to S5 : Number of the device to be passed as an argument to a subroutine program (bits, BIN 16 bits, BIN 32 bits)

Setting Internal Devices J \ Constants Other

R, ZR U \G Zn
Data Bit Word Bit Word K, H P

Pn –– –– ––

(Other
S1 to S5 ––
than F)

Function
(1) When the CALL (P) instruction is executed, executes the subroutine program of the program
specified by Pn.

The CALL (P) instruction can execute subroutine programs specified by a

pointer within the same program file and subroutine programs specified by a
common pointer.
Main routine Subroutine
program program
Pn

CALL Pn RET

END

7-110
 CALL(P)

(2) When function devices (FX, FY, FD) are used by a subroutine program, specify a device with
to corresponding to the function device. The contents to the devices specified by
S1 S5 S1
1
to S5 are as indicated below.

(a) Prior to execution of the subroutine program, bit data is transmitted to FX, and word
data is transmitted to FD.
6
(b) After the execution of the subroutine program, the contents of FY and FD are
transmitted to the corresponding devices. 6
(c) The processing units for the function devices are as follows:
• FX, FY: Bits
7
• FD : 4-word units
The size of the data to be dealt with will differ depending on the device specified in the
argument. The device specified as a function device should be secured for the data 8
size. An error will occur if it cannot be secured for the data size.
Function devices Device Data Size Remark
• FX Bit device 1 point
––
• FY When bit designation is made for word device 1 bit

7.6.3 Subroutine program calls (CALL(P))

7.6 Structure creation instructions
When digit designation of a bit device is used *1 4 words The data size varies
• FD depending on the
Word device 4 words instruction to be used.

*1: An error will not occur even when the device number specified by S1 to S5 is not a multiple of 16 at the digit
designation of the bit device.

[Main routine program]

X0
CALL P0 M0 D0 D30

Occupies from D30 to D33 (Transfer to FD2).

Occupies from D0 to D3 (Transfer to FD1).
Occupies M0 (Transfer to FX0).

(3) S1 to S5 can be used with the CALL (P) instruction.

(4) The number of function devices to be used by a subroutine program must be identical to the
number of arguments in the CALL (P) instruction.
Also, the types of the function device and CALL (P) argument used should be identical.
(5) Device numbers specified by the CALL (P) instruction should not overlap.
If they do overlap, it will not be possible to obtain accurate calculations.

7-111
 CALL(P)

(6) The device used in the argument of the CALL (P) instruction should not be used in a
subroutine program. If used, it will not be possible to obtain accurate calculations.
(Refer to the following program example.)
(7) When the device, either timer or counter, is used in the argument of the CALL(P) instruction,
only the current value is transmitted/received.

Incorrect operation example

The following example shows the operation performed when D0 is specified for FD0 in the
subroutine program and D1 is used in the subroutine program.

[Program example]

[Operation performed after subroutine program execution]

Before the execution Immediately after the At the time of

of subroutine program execution of CALL subroutine program After the execution
instruction execution of RET instruction
D0 0 D0 0 D0 0 D0 33 *2
D1 10 D1 10 D1 110 *1 D1 110 *3
D2 100 D2 100 D2 100 D2 100 *2
Transfer Transfer
D3 1000 D3 1000 D3 1000 D3 1000 *2

Indefinite 0 33 *1 Indefinite
Indefinite 10 1 *1 Indefinite
FD0 FD0 FD0 FD0
Indefinite 100 100 Indefinite
Indefinite 1000 1000 Indefinite

*1: Stores the execution result of the subroutine program.

*2: Replaced by the value of the function device.
*3: D1 does not reflect the value of the function device.

7-112
 CALL(P)

Correct operation example

The following example shows the operation performed when D0 is specified for FD0 in the
subroutine program and D4 is used in the subroutine program.
1

[Program example]
2

[Operation performed after subroutine program execution] 6

Immediately after the At the time of
Before the execution
execution of CALL subroutine program After the execution
of subroutine program
instruction execution
7
of RET instruction
D0 0 D0 0 D0 0 D0 33 *2
D1 10 D1 10 D1 10 D1 1 *2
D2 100 Transfer D2 100 D2 100 D2 100 *2
D3 1000 D3 1000 D3 1000 Transfer D3 1000 *2 8
D4 0 D4 0 D4 100 *1 D4 100

Indefinite 0 33 *1 Indefinite
Indefinite 10 1 *1 Indefinite
FD0 FD0 FD0 FD0

7.6.3 Subroutine program calls (CALL(P))

7.6 Structure creation instructions
Indefinite 100 100 Indefinite
Indefinite 1000 1000 Indefinite

*1: Stores the execution result of the subroutine program.

*2: Replaced by the value of the function device.

(8) Up to 16 nesting levels are possible with the CALL(P) instruction. However, this 16 levels is
the total number of levels in the CALL(P), FCALL(P), ECALL(P), EFCALL(P), and XCALL
instructions.

CALL P0 P0 P10 P20

CALL P10 CALL P20

FEND RET RET RET

END

(9) Devices which are turned ON within subroutine programs will be latched even if the
subroutine program is not executed. Devices which are turned ON during the execution of a
subroutine program can be turned OFF by the execution of the FCALL(P) instruction.

7-113
 CALL(P)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The device specified for the argument cannot be secured for the data size.
(Error code: 4101)
• Following the execution of the CALL (P) instruction, an END, FEND, GOEND, or STOP
instruction is executed before the execution of the RET instruction.
(Error code: 4211)
• An RET instruction is executed prior to the execution of the CALL (P) instruction.
(Error code: 4212)
• A 17th nesting level is executed. (Error code: 4213)
• There is no subroutine program for the pointer specified in the CALL (P) instruction.
(Error code: 4210)

Program Example
(1) The following program executes a subroutine program with argument when X20 is turned
ON.
[Ladder Mode] [List Mode]
Step Instruction Device

7-114
 RET

7.6.4 Return from subroutine programs (RET)

RET
1
Basic High
performance Process Redundant Universal LCPU
2

3
RET RET

4
Setting Internal Devices J \
R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
–– –– 6

Function 6
(1) Indicates end of subroutine program
(2) When the RET instruction is executed, returns to the step following the CALL (P), FCALL 7
(P), ECALL (P), EFCALL (P) or XCALL instruction which called the subroutine program.

Main routine Subroutine

program program 8
Pn

CALL Pn RET

7.6.4 Return from subroutine programs (RET)

7.6 Structure creation instructions
END

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• Following the execution of the CALL(P), FCALL (P), ECALL (P), EFCALL (P) or XCALL
instruction, an END, FEND, GOEND, or STOP instruction is executed before the
execution of the RET instruction. (Error code: 4211)
• An RET instruction is executed prior to the execution of the CALL (P), FCALL (P), ECALL
(P), EFCALL (P) or XCALL instruction. (Error code: 4212)

7-115
 FCALL(P)

7.6.5 Subroutine program output OFF calls (FCALL(P))

FCALL(P)

Basic High
performance Process Redundant Universal LCPU

Command
FCALL FCALL Pn

Command
FCALLP FCALLP Pn

Command
FCALL FCALL Pn S1 to S5

Command
FCALLP FCALLP Pn S1 to S5

Pn : Head pointer number of a subroutine program (Device name)

S1 to S5 : Number of the device to be passed as an argument to a subroutine program (bits, BIN 16 bits, BIN 32 bits)

Setting Internal Devices J \ Other

R, ZR U \G Zn Constants
Data Bit Word Bit Word P

Pn –– –– ––

(Other
S1 to S5 ––
than F)

Function
(1) When FCALL(P) is executed, the non-execution processing of the subroutine program of the
pointer designated by Pn is performed.

The FCALL (P) instruction can execute subroutine programs designated by a

pointer within the same program file, and subroutine programs designated by
common pointers.

(a) Non-execution processing is identical to the processing that is conducted when the
condition contacts for the individual coil instructions are in the OFF state.
Main routine Subroutine
program program
Pn Non-execution processing is
executed when the command
for the FCALL(P) instruction is
FCALL Pn RET turned from ON to OFF.

END

7-116
 FCALL(P)

(b) The operation results for the individual coil instructions following non-execution
processing will be as follows, regardless of the ON/OFF status of the individual
contacts:
1
OUT instruction ...... Forced OFF
SET instruction 2
RST instruction
SFT instruction ...... Maintains status
Basic instructions
Application instructions
3
PLS instruction Processing identical to
Pulse generation ...... when condition contacts
instruction ( P) are OFF 4
Present value of low speed/high speed timers ...... 0
Present value of retentive timer
...... Preserves
Present value of counter 6
(2) The FCALL (P) instruction is used in conjunction with the CALL(P) instruction.
(3) If the FCALL (P) instruction is used in conjunction with the CALL(P) instruction, 6
non-execution processing of a subroutine program is performed when the execution
command is turned OFF, enabling forcible turning OFF of the OUT instruction and the PLS
instruction (including P instructions).
In case the FCALL (P) instruction is not used in conjunction with the CALL(P) instruction,
7
non-execution processing of a subroutine program is not performed even if the execution
command is turned OFF. Therefore, output status of the individual coil instructions remains
unchanged. 8

X0
CALL P0 When FCALL instruction is used

7.6.5 Subroutine program output OFF calls (FCALL(P))

7.6 Structure creation instructions
FCALL P0 X0

X1

FEND Y10
X1
P0 Y10 Y11

SET Y11 M0

Forced OFF by FCALL instruction

PLS M0

RET

X0 When FCALL instruction is not used

CALL P0
X0

X1
FEND
X1 Y10
P0 Y10
Y11
SET Y11
M0
PLS M0

RET

7-117
 FCALL(P)

(4) When function devices (FX, FY, FD) are used by a subroutine program, specify a device with
S1 to S5 corresponding to the function device. The contents to the devices specified by S1

to S5 are as indicated below.

(a) Prior to execution of the subroutine program, bit data is transmitted to FX, and word
data is transmitted to FD.

(b) After the execution of the subroutine program, the contents of FY and FD are
transmitted to the corresponding devices.

(c) The processing units for the function devices are as follows:
• FX, FY: Bits
• FD : 4-word units
The size of the data to be dealt with will differ depending on the device specified in the
argument. The device specified as a function device should be secured for the data
size. An error will occur if it cannot be secured for the data size.
Function devices Device Data Size Remark
Bit device 1 point
• FX
When Bit Designation has been Made for Word ––––
• FY 1 bit
Device
The upper 2 words of
When digit designation of a bit device is used*1 4 words
• FD FD become 0
Word device 4 words ––––

*1: An error will not occur if the device number specified by S1 to S5 is not a multiple of 16 at the digit
designation of the bit device.

[Main routine program]

X0
FCALL P0 M0 D0 D30

Occupies from D30 to D33 (Transfer to FD2).

Occupies from D0 to D3 (Transfer to FD1).
Occupies M0 (Transfer to FX0).

(5) The FCALL (P) instruction can use from S1 to S5 .

7-118
 FCALL(P)

(6) Up to 16 nesting levels are possible with the FCALL(P) instruction. However, this 16 levels
is the total number of levels in the CALL(P), FCALL(P), ECALL(P), EFCALL(P), and XCALL
instructions. 1
CALL P0
P0 P10
2
FCALL P0 P20

CALL P10 CALL P20

FCALL P10 FCALL P20
3
FEND RET RET RET

END
4

Operation Error
6
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The device specified for the argument cannot be secured for the data size. 6
(Error code: 4101)
• Following the execution of the CALL (P) instruction, an END, FEND, GOEND, or STOP
instruction is executed before the execution of the RET instruction.
(Error code: 4211)
7
• An RET instruction is executed prior to the execution of the FCALL (P) instruction.
(Error code: 4212)
• A 17th nesting level is executed. (Error code: 4213)
8
• The subroutine program of the pointer designated by the FCALL (P) instruction does not
exist. (Error code: 4210)

7.6.5 Subroutine program output OFF calls (FCALL(P))

7.6 Structure creation instructions
Program Example
(1) The following program executes a subroutine program with argument when X20 is turned
ON, and forces non-execution processing when X20 is turned from ON to OFF.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
X20

M0

Y1

Forced OFF by FCALL instruction

7-119
 ECALL(P)

7.6.6 Subroutine calls between program files (ECALL(P))

ECALL(P)

High
Basic performance Process Redundant Universal LCPU

Command
ECALL ECALL File name Pn

Command
ECALLP ECALLP File name Pn

Command
ECALL ECALL File name Pn S1 to S5

Command
ECALLP ECALLP File name Pn S1 to S5

File name : Name of the program file to be called (character string)

Pn : Head pointer number of a subroutine program (Device name)
S1 to S5 : Number of the device to be passed as an argument to a subroutine program (bits, BIN 16 bits, BIN 32 bits)

Setting Internal Devices J \ Constants Other

R, ZR U \G Zn
Data Bit Word Bit Word K, H $ P

File name –– –– ––

Pn –– –– –– ––

(Other
S1 to S5 –– ––
than F)

Function
(1) Executes the subroutine program of the pointer designated by Pn in the designated program
file name when the ECALL (P) instruction is executed. The ECALL(P) instruction can be
used to call a subroutine program that uses a local pointer from a different program file.

[File name: MAIN] [File name: ABC]

Main routine Subroutine
program program
Pn

ECALLABCPn RET

END

7-120
 ECALL(P)

(2) Only the file name of a program file stored in the drive 0 (program memory/internal RAM)
can be designated for a file name.
1
(3) It is not necessary to designate the extension (.QPG) with the file name.
(Only .QPG files will be acted on.)
(4) When function devices (FX, FY, FD) are used by a subroutine program, specify a device 2
corresponding to the function device with S1 to S5 . The contents of the devices specified by

S1 to S5 are as indicated below.

3
[MAIN]

4
[ABC]
6

7
(a) Prior to execution of the subroutine program, bit data is transmitted to FX, and word
data is transmitted to FD.
8
(b) After the execution of the subroutine program, the contents of FY and FD are
transmitted to the corresponding devices.

(c) The processing units for the function devices are as follows:

7.6.6 Subroutine calls between program files (ECALL(P))

7.6 Structure creation instructions
• FX, FY: Bits
• FD : 4-word units
The size of the data to be dealt with will differ depending on the device specified in the
argument. The device specified as a function device should be secured for the data
size. An error will occur if it cannot be secured for the data size.
Function devices Device Data Size Remark
Bit device 1 point
• FX
When Bit Designation has been Made for Word ––––
• FY 1 bit
Device

When digit designation of a bit device is used*1 4 words The data size varies
• FD depending on the
Word device 4 words instruction to be used.

*1: An error will not occur even when the device number specified by S1 to S5 is not a multiple of 16 at the digit
designation of the bit device.

[Main routine program]

X0
ECALL "A-LINE" P0 M0 D0 D30

Occupies from D30 to D33 (Transfer to FD2).

Occupies from D0 to D3 (Transfer to FD1).
Occupies M0 (Transfer to FX0).

7-121
 ECALL(P)

(5) From S1 to S5 can be used by the ECALL instruction.

(6) The device used in the argument of the ECALL instruction should not be used in a
subroutine program.
If used, it will not be possible to obtain accurate calculations. (Refer to the following
program example.)
Incorrect operation example
The following example shows the operation performed when D0 is specified for FD0 in the
subroutine program and D1 is used in the subroutine program.

[Program example]

[Operation performed after subroutine program execution]

Before the execution Immediately after the At the time of
of subroutine program execution of ECALL subroutine program After the execution
instruction execution of RET instruction
D0 0 D0 0 D0 0 D0 33 *2
D1 10 D1 10 D1 110 *1 D1 110 *3
D2 100 D2 100 D2 100 Transfer D2 100 *2
Transfer
D3 1000 D3 1000 D3 1000 D3 1000 *2

Indefinite 0 33 *1 Indefinite
Indefinite 10 1 *1 Indefinite
FD0 FD0 FD0 FD0
Indefinite 100 100 Indefinite
Indefinite 1000 1000 Indefinite

*1: Stores the execution result of the subroutine program.

*2: Replaced by the value of the function device.
*3: D1 does not reflect the value of the function device.

7-122
 ECALL(P)

Correct operation example

The following example shows the operation performed when D0 is specified for FD0 in the
subroutine program and D4 is used in the subroutine program.
1

[Program example]
2
[MAIN]

3
[ABC]
4

[Operation performed after subroutine program execution]

7
Immediately after the At the time of
Before the execution
execution of ECALL subroutine program After the execution of
of subroutine program
instruction execution RET instruction 8
D0 0 D0 0 D0 0 D0 33 *2
D1 10 D1 10 D1 10 D1 1 *2
D2 100 D2 100 D2 100 Transfer D2 100 *2
Transfer
D3 1000 D3 1000 D3 1000 D3 1000 *2

7.6.6 Subroutine calls between program files (ECALL(P))

7.6 Structure creation instructions
D4 0 D4 0 D4 100 *1 D4 100

Indefinite 0 33 *1 Indefinite
Indefinite 10 1 *1 Indefinite
FD0 FD0 FD0 FD0
Indefinite 100 100 Indefinite
Indefinite 1000 1000 Indefinite

*1: Stores the execution result of the subroutine program.

*2: Replaced by the value of the function device.

(7) The numbers of the devices designated by the arguments in the ECALL(P) instruction
should not overlap. If they do overlap, it will not be possible to obtain accurate calculations.
(8) Up to 16 levels of nesting can be used with the ECALL(P) instruction. However, this 16
levels is the total number of levels in the CALL(P), FCALL(P), ECALL(P), EFCALL(P), and
XCALL instructions.

ECALL "ABC" P0 P0 P10 P20

ECALL "DEF" P10 ECALL "GHI" P20

FEND RET RET RET

END

(9) Devices which are turned ON within subroutine programs will be latched even if the
subroutine program is not executed. Devices turned ON during the execution of a
subroutine program can be turned OFF by the EFCALL(P) instruction.

7-123
 ECALL(P)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The device specified for the argument cannot be secured for the data size.
(Error code: 4101)
• Following the execution of the ECALL (P) instruction, an END, FEND, GOEND, or STOP
instruction is executed before the execution of the RET instruction.
(Error code: 4211)
• An RET instruction is executed prior to the execution of the ECALL(P) instruction.
(Error code: 4212)
• A 17th nesting level is executed. (Error code: 4213)
• The subroutine program of the pointer designated by the ECALL(P) instruction does not
exist. (Error code: 4210)
• The designated file does not exist. (Error code: 2410)
• The designated file cannot be executed. (Error code: 2411)

Program Example
(1) The following program executes program block P0 of the program A-LINE when X20 is
turned ON.
[Ladder Mode] [List Mode]
[MAIN] Step Instruction Device

[A-LINE] Step Instruction Device

7-124
 EFCALL(P)

7.6.7 Subroutine output OFF calls between program files

(EFCALL(P)) 1
EFCALL(P)

High
2
Basic performance Process Redundant Universal LCPU

3
Command
EFCALL EFCALL File name Pn
4
Command
EFCALLP EFCALLP File name Pn

Command
6
EFCALL EFCALL File name Pn S1 to S5

EFCALLP
Command
EFCALLP File name Pn S1 to S5 6

File name : Name of the program file to be called (character string) 7

Pn : Head pointer number of a subroutine program (Device name)
S1 to S5 : Number of the device to be passed as an argument to a subroutine program
(bits, BIN 16 bits, BIN 32 bits)
8
Setting Internal Devices J \ Constants Other
R, ZR U \G Zn
Data Bit Word Bit Word K, H $ P

File name –– –– ––

Pn –– –– –– ––

7.6.7 Subroutine output OFF calls between program files (EFCALL(P))

7.6 Structure creation instructions
(Other
S1 to S5 –– ––
than F)

Function
(1) When the EFCALL(P) instruction is executed, the non-execution processing of the
subroutine program of the pointer designated by Pn is performed.

The EFCALL (P) can also be used to call a subroutine program that uses a
local pointer from a different program file.

(a) Non-execution processing is identical to the processing that is conducted when the
condition contacts for the individual coil instructions are in the OFF state.
[File name: MAIN] [File name: ABC]
Main routine Subroutine
program program
Pn Non-execution processing
is executed when the
command for the
EFCALL(P) instruction is
EFCALL "ABC" Pn RET turned from ON to OFF.

END

7-125
 EFCALL(P)

(b) The operation results for the individual coil instructions following non-execution
processing will be as follows, regardless of the ON/OFF status of the individual contacts:
OUT instruction ...... Forced OFF
SET instruction
RST instruction
SFT instruction ...... Maintains status
Basic instructions
Application instructions
PLS instruction Processing identical to
Pulse generation ...... when condition contacts
instruction ( P) are OFF
Present value of low speed/high speed timers ...... 0
Present value of retentive timer
...... Preserves
Present value of counter

(2) The EFCALL (P) instruction is used in combination with the ECALL (P) instruction.
(3) If the EFCALL(P) instruction is used in conjunction with the ECALL(P) instruction,
non-execution processing of a subroutine program is performed when the execution
command is turned OFF, enabling forcible turning OFF of the OUT instruction and the PLS
instruction (including P instructions).
In case the EFCALL(P) instruction is not used in conjunction with the ECALL(P) instruction,
non-execution processing of a subroutine program is not performed even if the execution
command is turned OFF. Therefore, output status of the individual coil instructions remains
unchanged.

When EFCALL instruction is used

[File Name: ABC.QPG]

Forced OFF by FCALL instruction

When EFCALL instruction is not used

[File Name: ABC.QPG]

7-126
 EFCALL(P)

(4) Only the file name of a program file stored in the drive 0 (program memory/internal RAM)
can be designated for a file name.
1
(5) It is not necessary to designate the extension (.QPG) with the file name.
(Only .QPG files will be acted on.)
(6) When function devices (FX, FY, FD) are used by a subroutine program, specify a device 2
corresponding to the function device with S1 to S5 .
[MAIN]
3

[ABC] 6

(a) Prior to execution of the subroutine program, bit data is transmitted to FX, and word 8
data is transmitted to FD.
(b) After the execution of the subroutine program, the contents of FY and FD are
transmitted to the corresponding devices.
(c) The processing units for the function devices are as follows:

7.6.7 Subroutine output OFF calls between program files (EFCALL(P))

7.6 Structure creation instructions
• FX, FY: Bits
• FD : 4-word units
The size of the data to be dealt with will differ depending on the device specified in the
argument. The device specified as a function device should be secured for the data
size. An error will occur if it cannot be secured for the data size.
Function devices Device Data Size Remark
Bit device 1 point
• FX
When Bit Designation has been Made for Word ––
• FY 1 bit
Device
The upper 2 words of
When digit designation of a bit device is used*1 4 words
• FD FD become 0
Word device 4 words ––

*1: An error will not occur even when the device number specified by S1 to S5 is not a multiple of 16 at the digit
designation of the bit device.

[Main routine program]

X0
EFCALL "ABC" P0 M0 D0 D30

Occupies from D30 to D33 (Transfer to FD2).

Occupies from D0 to D3 (Transfer to FD1).
Occupies M0 (Transfer to FX0).

7-127
 EFCALL(P)

(7) S1 to S5 can be used with the EFCALL (P) instruction.

(8) The number of function devices used by subroutine programs must be identical to the
number of arguments used by the EFCALL (P) instruction. Further, the function devices
should be identical to the types of arguments used by the EFCALL (P) instruction.
(9) Up to 16 levels of nesting can be used with the EFCALL (P) instruction. However, this 16
levels is the total number of levels in the CALL(P), FCALL(P), ECALL(P), EFCALL(P), and
XCALL instructions.
ECALL "ABC" P0

EFCALL "ABC" P0 P0 P10 P20

ECALL "DEF" P10 ECALL "GHI" P20

EFCALL"DEF" P10 EFCALL "GHI" P20
FEND
RET RET RET
END

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The device specified for the argument cannot be secured for the data size.
(Error code: 4101)
• Following the execution of the EFCALL (P) instruction, an END, FEND, GOEND, or STOP
instruction is executed before the execution of the RET instruction.
(Error code: 4211)
• An RET instruction is executed prior to the execution of the EFCALL (P) instruction.
(Error code: 4212)
• A 17th nesting level is executed. (Error code: 4213)
• The subroutine program of the pointer designated by the EFCALL (P) instruction does not
exist. (Error code: 4210)
• The designated file does not exist. (Error code: 4210)
• The designated file cannot be executed. (Error code: 2411)

Program Example
(1) The following program executes a subroutine program with argument when X0 is ON, and
forces non-execution processing when X20 is turned from ON to OFF.
[Ladder Mode] [List Mode]
Step Instruction Device

7-128
 XCALL

7.6.8 Subroutine program call (XCALL)

XCALL
1
Ver.
High
Basic
2
performance Process Redundant Universal LCPU

Basic model QCPU: The upper five digits of the serial No. are "04122" or larger.

3
Command
XCALL XCALL Pn S1 to S5
4
Pn : Head pointer number of a subroutine program (Device name)
S1 to S5 : Number of the device to be passed as an argument to a subroutine program (bits, BIN 16 bits, BIN 32 bits) 6
Setting Internal Devices J \ Constants Other
R, ZR U \G Zn
Data Bit Word Bit Word K, H P

P –– –– –– 6
(Other
S1 to S5 ––
than F)

7
Function
8
(1) XCALL instruction executes the subroutine program and performs non-execution processing
of the subroutine program.
(a) Execution of subroutine program
Executes each coil instruction according to ON/OFF status of the condition contacts.

7.6.8 Subroutine program call (XCALL)

7.6 Structure creation instructions
(b) Non-execution of subroutine program
Performs the same processing for each coil instruction as when the condition contacts
are OFF status. The operation results for the individual coil instructions following
non-execution processing will be as follows,
regardless of the ON/OFF status of the individual contacts:
OUT instruction ...... Forced OFF
SET instruction
RST instruction
SFT instruction ...... Maintains status
Basic instructions
Application instructions
PLS instruction Processing identical to
Pulse generation ...... when condition contacts
instruction ( P) are OFF
Present value of low speed/high speed timers ...... 0
Present value of retentive timer
...... Preserves
Present value of counter

7-129
 XCALL

(2) Operation of XCALL instruction varies according to the CPU module type. The following
program example shows the operation of XCALL instruction for each CPU module.

[Program example]

Subroutine program (P1)

call by XCALL instruction

P1 subroutine program

[ON/OFF timing of X0]

(1) Turning X0 ON (3) Turning X0 OFF
(OFF ON) (2) During X0 is ON *2 (ON OFF)
ON
OFF
X0

*2: Time during X0 is ON(2)) does not include the time when turning X0 ON (1)).

Component Operation of XCALL instruction

• Process CPU 1) When X0 is turned ON: Without process (Do not execute subroutine program of "P1".)
(serial No. of first 5 digits : 07031 or earlier) 2) During X0 is ON: Execute subroutine program of "P1".
• High performance model QCPU 3) When X0 is turned OFF: Perform "Non-execution processing" of subroutine program of "P1".
(serial No. of first 5 digits: 06081 or earlier.)
1) Using SM734 (XCALL instruction executing condition designation) to select operation when
• High performance model QCPU X0 is turned ON.
(serial No. of first 5 digits: 06082 or later.) • When SM734 is OFF: Without process (Do not execute subroutine program of "P1".)
• Process CPU • When SM734 is ON: Execute subroutine program of "P1".
(serial No. of first 5 digits : 07032 or later) 2) During X0 is ON: Execute subroutine program of "P1".
3) When X0 is turned OFF: Perform "Non-execution processing" of subroutine program of "P1".
• Redundant CPU 1) When X0 is turned ON: Execute subroutine program of "P1".
• Basic model QCPU 2) During X0 is ON: Execute subroutine program of "P1".
• Universal model QCPU 3) When X0 is turned OFF: Perform "Non-execution processing" of subroutine program of "P1".
• LCPU

7-130
 XCALL

(3) When function devices (FX, FY, FD) are used by a subroutine program, specify a device with
to corresponding to the function device. The contents to the devices specified by
S1 S5 S1
1
to S5 are as indicated below.

4
(a) Prior to execution of the subroutine program, bit data is transmitted to FX, and word
data is transmitted to FD.
6
(b) After the execution of the subroutine program, the contents of FY and FD are
transmitted to the corresponding devices.

(c) The processing units for the function devices are as follows: 6
• FX, FY: Bits
• FD : 4-word units
7
The size of the data to be dealt with will differ depending on the device specified in the
argument. The device specified as a function device should be secured for the data
size. An error will occur if it cannot be secured for the data size.
8
Function devices Device Data Size Remark
Bit device 1 point
• FX
When Bit Designation has been Made for Word ––––
• FY 1 bit
Device

7.6.8 Subroutine program call (XCALL)

7.6 Structure creation instructions
When digit designation of a bit device is used*3 4 words The data size varies
• FD depending on the
Word device 4 words instruction to be used.

*3: An error will not occur even when the device number specified by S1 to S5 is not a multiple of 16 at the digit
specification of the bit device.

[Main routine program]

X0
XCALL P0 M0 D0 D30

Occupies from D30 to D33 (Transfer to FD2).

Occupies from D0 to D3 (Transfer to FD1).
Occupies M0 (Transfer to FX0).

(4) S1 to S5 can be used by the XCALL instruction.

(5) The number of function devices used by a subroutine program must be identical to the
number of arguments in the XCALL instruction. Also, the function device and the type of
XCALL argument should be identical.
(6) Device numbers specified in the argument of the XCALL instruction should not overlap.
If they do overlap, it will not be possible to obtain accurate calculations.

7-131
 XCALL

(7) Up to 16 nesting levels can be used with the XCALL instruction. However, this 16 levels is
the total number of levels in the CALL(P), FCALL(P), ECALL(P), EFCALL(P), and XCALL
instructions.

XCALL P0 X0 P0 P20

XCALL P10 X10 XCALL P20 X20

FEND RET RET RET

END

(8) The device used for the argument of the XCALL instruction must not be used in a subroutine
program.
If used, it will not be possible to perform correct calculations.
(Refer to the following program example.)
The processing to be executed when D1 is used in a subroutine program with D0 designated
for FD0 in a subroutine program is shown below.

[Program example]

[Operation performed after subroutine program execution]

Immediately after the At the time of
Before the execution After the execution
execution of subroutine program
of subroutine program of RET instruction
XCALL instruction execution
D0 0 D0 0 D0 0 D0 1 *2
D1 10 D1 10 D1 110 *1 D1 10 *2
D2 100 D2 100 D2 100 Transfer D2 100 *2
Transfer
D3 1000 D3 1000 D3 1000 D3 1000 *2

Indefinite 0 1 *1 Indefinite
Indefinite 10 10 Indefinite
FD0 FD0 FD0 FD0
Indefinite 100 100 Indefinite
Indefinite 1000 1000 Indefinite

*1: Stores the execution result of the subroutine program.

*2: Replaced by the value of the function device. D1 does not reflect the operation result in the subroutine
program.

7-132
 XCALL

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The device specified for the argument cannot be secured for the data size. 2
(Error code: 4101)
• Following the execution of the XCALL(P) instruction, the END, FEND, GOEND or STOP
instruction is executed before the execution of the RET instruction. 3
(Error code: 4211)
• The RET instruction is executed prior to the execution of the XCALL(P) instruction.
(Error code: 4212) 4
• A 17th nesting level is executed. (Error code: 4213)
• There is no subroutine program for the pointer specified in the XCALL(P) instruction. 6
(Error code: 4210)

Program Example 6
(1) The following program executes a subroutine program with argument when X20 is turned
ON. 7
[Ladder Mode] [List Mode]

Step Instruction Device

8

7.6.8 Subroutine program call (XCALL)

7.6 Structure creation instructions

7-133
 COM

7.6.9 Refresh instruction (COM)

Basic High
performance Process Redundant Universal LCPU

COM

Refer to Section 7.6.10 for the COM instruction of the following CPU modules.
• Basic model QCPU of serial No. 04122 or later
• High Performance model QCPU of serial No. 04012 or later
• Process CPU of serial No. 07032 or later
• Redundant CPU
• Universal model QCPU
• LCPU

COM
COM

Setting Internal Devices J \

R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
–– ––

Function
(1) Use the COM instruction when:
(a) It is desired to increase the speed of transmission/reception processing to/from the
remote I/O stations.

(b) It is desired to ensure reliable data transmission/reception with other stations that use
different scan times during the execution of the data link.

(2) The processing of the COM instruction differs depending on whether the special relay
SM775 is ON or OFF.
• When SM775 is OFF: Performs auto refresh and communication with a peripheral
device *1 *2
• When SM775 is ON: Performs communication with peripheral device only *1
*1: The following processing is performed in communication with peripheral device:
• Monitor processing of other stations
• Read processing by the serial communications module of the buffer memory of another intelligent
function module
*2: The auto refresh includes the following processing:
• Refresh of MELSECNET/10H
• CC-Link refresh
• Auto refresh of intelligent function modules.

7-134
 COM

(3) At the point of the execution of the COM instruction, the CPU module temporarily stops the
processing of the sequence program, and performs the same operation as ordinary data
processing as well as auto refresh of intelligent function modules (including link refreshes) at 1
the END processing. However, the low speed cyclic refresh of
MELSECNET/10 or MELSECNET/H is not performed.
Execution of COM instruction Execution of COM instruction 2
0 END 0 END 0

General data processing and auto refresh 3

(including link refresh) of intelligent function module

4
(4) The COM instruction can be used in a sequence program any number of times. However,
note that the scan time of the sequence program will be lengthened by the time taken for
communication with peripheral device and the auto refresh (including the link refresh) of the
intelligent function modules.
6
(5) Data communications using the COM instruction
(a) Example of data communications when COM instruction is not used 6
Host station program 0 END 0 END 0 END 0 END 0 END 0 END 0

7
Data communications

Program at other station 0 END 0 END 0 END 0 END 0 8

I/O refresh at remote I/O station

(b) Example of data communications when COM instruction has been used

7.6.9 Refresh instruction (COM)

7.6 Structure creation instructions
COM COM COM COM COM COM
Host station program 0 END 0 END 0 END 0 END 0 END 0

Data communications

COMCOM COM COM COM

Program at other station 0 0 0 END 0 0

END END COM COM COM END

I/O refresh at remote I/O station

1) When the COM instruction is used at the host station, it is possible to increase the number
of data communication repetitions with the remote I/O station unconditionally, as shown in
(b) above, and thus to speed up data communications.
2) In cases where the remote station scan time is longer than the scan time of the host
station, the COM instruction used at the remote station side can avoid the occurrence of
timing failure in which the data cannot be fetched, as shown in (a).
3) When the COM instruction has been used at the other station, a link refresh will be
performed each time that station receives a command from the host station.
Step 0 COM instruction Link refresh can be performed
COM instruction COM instruction once in each of these intervals.
COM instruction END instruction

7-135
 COM

(6) If the scan time from the linked station is longer than the sequence program scan time at the
host station, designating the COM instruction at the host station will not increase the speed
of data communications.
END

Sequence program 0 COM END 0 COM END 0 COM 0 COM END

Link scan

The programs in which the COM instruction cannot be used are shown below:
• Low-speed execution type programs
• Interrupt programs
• Fixed scan execution type programs

Operation Error
(1) There are no operation errors associated with the COM instruction.

7-136
 COM

7.6.10 Select Refresh Instruction (COM)

COM
1
Refer to Section 7.6.9. for the COM instruction of the following CPU modules.
• Basic model QCPU of serial No. 04121 or later
• High Performance model QCPU of serial No. 04011 or later 2
• Process CPU of serial No. 07031 or later

Basic
Ver.
High
Ver.
performance
Ver.
Process Redundant Universal LCPU 3
Basic model QCPU:The first 5 digits of the serial No. are "04122" or higher.
High Performance model QCPU:The first 5 digits of the serial No. are "04012" or higher.
Process CPU:The first 5 digits of the serial No. are "07032" or higher. 4

6
COM
COM

Setting Internal Devices J \

6
Z, ZR U \G Zn Constants Other
Data Bit Word Bit Word
–– ––
7
Function
8
(1) When the COM instruction is executed, the following refresh operations can be performed.
Refresh Items QCPU LCPU
I/O refresh

7.6.10 Select Refresh Instruction (COM)

7.6 Structure creation instructions
CC-Link refresh

CC-Link IE controller network refresh

MELSECNET/H refresh

Auto refresh of intelligent function modules

Auto refresh using QCPU standard area of multiple

CPU system
Reading input/output data of all modules other than
the multiple CPU system group
Auto refresh using the multiple CPU high speed
transmission area of multiple CPU system

Communication with display unit

Service process (communication with programming

tool, GOT, or other external device)

Remark
The following processing is performed in communication with peripheral device.
• Monitor processing of other station
• Read of another intelligent function module buffer memory by the serial
communication module

(2) Turning OFF SM775 refreshes all refresh items except I/O refresh.

7-137
 COM

(3) When selecting refresh items

(a) Select refresh items by SD778, and set SM775 to ON.
The following table shows the refresh items that can be designated by turning SM775
ON/OFF and with SD778.
QCPU LCPU
Refresh Item When SM775 When SM775 When SM775 When SM775
is OFF is ON is OFF is ON
I/O refresh Not executed Not executed Whether to be
executed or
CC-Link refresh Executed not can be
selected.
CC-Link IE controller network refresh - -
MELSECNET/H refresh - -
Whether to be Whether to be
executed or executed or
Auto refresh of intelligent function modules Executed
Executed not can be not can be
selected. selected.
Auto refresh using QCPU standard area of
- -
multiple CPU system
Reading input/output data of all modules other
- -
than the multiple CPU system group
Auto refresh using the multiple CPU high speed
- -
transmission area of multiple CPU system
Communication with display unit - -
Whether to be
Whether to be
executed or
executed or Executed
Communication with peripheral device Executed not can be
not can be
selected.
selected.

(b) Select refresh items using SD778.

Whether to execute each bit of SD778 or not can be designated as shown below:
[ QCPU]
Bit of SD778 Executed Not Executed
b0 to b5 1 0
b15 0 1

b15 b14 to b6 b5 b4 b3 b2 b1 b0
SD778 1/0 0 1/0 1/0 1/0 1/0 1/0 1/0
I/O refresh
CC-Link refresh
CC-Link IE controller network,
MELSECNET/H refresh
Auto refresh of
intelligent function module
Auto refresh using QCPU standard
area of multiple CPU system
Reading inputs/outputs from the outside
of the multiple CPU system group
Auto refresh using the multiple CPU high speed
transmission area of multiple CPU system
Communication with peripheral devices

Example
To make only the send/receive processing with the remote I/O station faster,
designate MELSECNET/H refresh only.
(Set only b2 and b15 of SD778 to 1 (SD778: 8004H).)

7-138
 COM

Refresh between the multiple CPUs by the COM instruction is performed under 1
the following condition.
• Receiving operation from other CPUs : When b4 of SD778 (auto refresh in the
CPU shared memory) is 1. 2
• Sending operation from host CPU : When b15 of SD778 (communication
with peripheral device is executed/not
executed) is 0. 3
[ LCPU]
Bit of SD778 Executed Not Executed
4
b0 to b3, b14 1 0
b15 0 1
6
b15 b14 b13 to b4 b3 b2 b1 b0
SD778 1/0 1/0 0 1/0 0 1/0 1/0
I/O refresh 6
CC-Link refresh

Auto refresh with intelligent

function module 7
Communication with display unit
Communication with peripheral
device
8
Example:To speed up processing of the display unit only, specify communication with
the display unit only. (Write "1" to bits b14 and b15 of SD778 (SD778:C000H))

7.6.10 Select Refresh Instruction (COM)

7.6 Structure creation instructions

7-139
 COM

(4) Upon the execution of the COM instruction, the CPU module suspends the processing of the
sequence program, and refreshes the designated refresh item.
Execution of COM Execution of COM
instruction instruction

0 END 0 END 0

Refreshes the designated Refreshes the designated

refresh items refresh items

(5) The COM instruction can be used in a sequence program any number of times.
However, note that the sequence program scan time will be lengthened by the time taken for
refresh time of the communication with peripheral devices and refresh item that are selected
in SD778.
(6) Only with the Universal model QCPU and LCPU, interruption is enabled during the
execution of the COM instruction. However, note that the data can be separated if the
refresh data is used by an interrupt program etc.
(7) With the Built-in Ethernet port QCPU and LCPU, processing time may be increased if the
service process was executed by the COM instruction while the built-in Ethernet ports are in
Ethernet connection.
(8) Refresh items for the COM instruction are indicated in the following table.
CPU Module Type Name SM775 Refresh Item
Q00JCPU OFF Refreshes refresh items other than I/O
Q00CPU
ON Refreshes the refresh items selected by SD778.
Q01CPU
Q02CPU OFF Refreshes refresh items other than I/O
Q02HCPU
Q06HCPU
ON Refreshes the refresh items selected by SD778.
Q12HCPU
Q25HCPU
Q02PHCPU OFF Refreshes refresh items other than I/O
Q06PHCPU ON Refreshes the refresh items selected by SD778
Q12PHCPU OFF Refreshes refresh items other than I/O
Q25PHCPU ON Refreshes the refresh items selected by SD778.
Q12PRHCPU OFF Refreshes refresh items other than I/O
Q25PRHCPU ON Refreshes the refresh items selected by SD778.
Q00UJCPU OFF Refreshes refresh items other than I/O
Q00UCPU
Q01UCPU
Q02UCPU
Q03UDCPU
Q04UDHCPU
Q06UDHCPU
Q10UDHCPU
Q13UDHCPU
Q20UDHCPU ON Refreshes the refresh items selected by SD778.
Q26UDHCPU
Q03UDECPU
Q04UDEHCPU
Q06UDEHCPU
Q10UDEHCPU
Q20UDEHCPU
Q13UDEHCPU
Q26UDEHCPU
L02CPU OFF Refreshes refresh items other than I/O
L26CPU-BT ON Refreshes the refresh items selected by SD778

7-140
 COM

1. The COM instruction cannot be used in low speed execution type programs, 1
fixed scan execution type programs or interrupt programs.
2. For the redundant CPU, there are restrictions on use of the COM instruction.
Refer to the manual below for details. 2
• QnPRHCPU User's Manual (Redundant System)

7.6.10 Select Refresh Instruction (COM)

7.6 Structure creation instructions

7-141
 CCOM

7.6.11 Select Refresh Instruction (CCOM(P))

CCOM

Ver.
High
Basic performance Process Redundant Universal LCPU

QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later.

QnUDE(H)CPU: The serial number (first five digits) is "10102" or later.

Command
CCOM CCOM

Command
CCOMP CCOMP

Setting Internal Devices J \

Z, ZR U \G Zn Constants Other
Data Bit Word Bit Word
–– ––

Function
See 7.6.10 for details about function.

Operation Error
(1) When the CCOM(P) instruction is executed in the QnUD(H)CPU whose serial number
(first five digits) is "10101" or later, an error occurs. (Error code: 4100)

Program Example
(1) Turning on M0 enables the program to execute the select refresh, while turning off M0
disables the program to execute the select refresh.
[Ladder Mode] [List Mode]

Step Instruction Device

7-142
 IX,IXEND

7.6.12 Index modification of entire ladder (IX,IXEND)

IX,IXEND
1
High
2
Basic performance Process Redundant Universal LCPU

3
IX IX S

Ladder where index modification is performed

4
IXEND I X END

6
S : Head number of the devices where index modification data is stored (BIN 16 bits)

Setting Internal Devices J \

R, ZR U \G Zn Constants Other
Data Bit Word Bit Word 6
S –– ––

7
Function
(1) Performs index modification on all devices in the ladder up to the IXEND instruction after the 8
IX instruction, using the index modification value specified in the index modification table.
Refer to 7.6.13 for how to configure an index modification table.
The configuration of the index modification table and the corresponding index register
numbers are as shown below:

7.6.12 Index modification of entire ladder (IX,IXEND)

7.6 Structure creation instructions
Index register Index register
Device name Device name
number number
Modification value of timer Modification value of
S Z0 S +8 data register (D)
Z8
(T)

S +1 Modification value of counter S +9 Modification value of

(C)
Z1 link register (W)
Z9
Modification value of input S + 10 Modification value of
S +2 Z2 file register (R) Z10
(X)
Modification value of output Modification value of
S +3 (Y)
Z3 S + 11 buffer register I/O No. (U) Z11
Modification value of Modification value of
S +4 internal relay (M) Z4 S + 12 buffer register (G) Z12
Modification value of *1
S +5 Modification value of
latch relay (L)
Z5 S + 13 link direct device Z13
network No. (J)
Modification value of Modification value of
S +6 link relay (B)
Z6 S + 14 file register (ZR)
Z14

S +7 Modification value of Modification value of pointer

edge relay (V) Z7 S + 15 (P) Z15

*1: When using a basic model QCPU, index registers with numbers from Z10 onward cannot be used.

7-143
 IX,IXEND

(2) Index modification for device numbers is accomplished in the manner as below: By setting a
modification value to each of the devices, the set modification values are added to the all
device numbers of the devices used in the ladder between the IX and IXEND instructions.
The program is executed using the index modified device numbers.

IX D100 Modification value

D100 8 T (Z0)
X1Z2 M62Z4 Y24 Z3 D101 5 C (Z1)
SET M6Z4 D102 2 X (Z2)
D103 10 Y (Z3)
T495Z0 C270Z1B20Z6 D104 10 M (Z4)
MOV K0 D0Z8 D105 20 L (Z5)
D106 16 B (Z6)
X19Z2
D107 20 V (Z7)
Y40Z3
D108 1 D (Z8)

IXEND

X3 M72 Y2E
SET M16 Value "2" is added to X1 and X9 Processed as X3 and X1B, respectively.
Value "10 (AH)" is added to Y24 and Y40 Processed as Y2E and Y4A, respectively.
Value "10" is added to M6 and M62 Processed as M16 and M72, respectively.
T498 C275 B30
MOV K0 D1 Value "16 (10H)" is added to B20 Processed as B30
Value "8" is added to T495 Processed as T498
X1B Value "5" is added to C270 Processed as C275
Y4A Value "1" is added to D0 Processed as D1

(3) Instructions such as the PLS, PLF, and P instructions, which are executed only once
when input conditions have been established, cannot be index modified by using the IX to
IXEND instruction loop.
(4) In cases where adding the modification value causes the device number to exceed the
device range, accurate processing will not be conducted.
(5) Do not execute the IX or IXEND instructions during online program changes of sequence
programs (write during RUN). Accurate processing will not be conducted if this happens.
(6) Modification values are preset for random word devices as BIN values, and the initial device
number for which modification values have been set is designated by S .
(7) Do not execute a scan execution type program and an interrupt program simultaneously
between the IX and IXEND instructions.

7-144
 IX,IXEND

(8) Whether the program will be expanded or a user needs to create the program is depending
on your GPP function software package.
The index register should be added to the index modification ladder established with the IX
1
and IXEND instructions. *2

IX D100 2
X1Z2 M62Z4 Y24Z3
SET M6Z4
T495Z0 C270Z1 B20Z6
MOV K0 D0Z8
3
X19Z2
Y40Z3
4
IXEND

*2 : The value of Zn is returned to the previous Zn value before the execution of the IX instruction after the IXEND 6
instruction has been executed.

1. When using the IX and IXEND instructions in both a normal sequence program
6
and an interrupt sequence program, establish the interlock to avoid
simultaneous execution. The interlock assumes the area between the IX and
IXEND instructions in the normal sequence program as DI, disabling the
7
interruption.
2. The IXDEV and IXSET instructions can be used to specify modification values.
Refer to 7.6.13 for details. 8

7.6.12 Index modification of entire ladder (IX,IXEND)

7.6 Structure creation instructions

7-145
 IX,IXEND

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The IX and IXEND instructions are not used together. (Error code: 4231)
• An END, FEND, GOEND, or STOP instruction is executed prior to the execution of the
IXEND instruction, but after the execution of the IX instruction. (Error code: 4231)

Program Example
(1) The following program executes the same ladder 10 times, while changing device numbers.

[Ladder Mode] [List Mode]

Sets modification Step Instruction Device

value

Ladder which
executes index
modification

Changes
modification
value

[Operation]

Modification value 1st time 2nd time 3rd time 10th time
B0 B1 B2 B9
D100 Modification value of T
X10 X11 X12 X19
D101 Modification value of C Y30 Y31 Y32 Y39
D102 Modification value of X M0 M1 M2 M9
D103 Modification value of Y D0 D1 D2 D9
D104 Modification value of M D10 D11 D12 D19
T3 T4 T5 T12
D105 Modification value of L
C4 C5 C6 C13
D106 Modification value of B D40 D41 D42 D49
D107 Modification value of V
D108 Modification value of D

7-146
 IXDEV,IXSET

7.6.13 Designation of modification values in index modification of entire

ladders (IXDEV,IXSET) 1
IXDEV,IXSET

High
2
Basic performance Process Redundant Universal LCPU

3
IXDEV IXDEV
4
IXSET IXSET S D

Dummy contact 6

Offset designation sections 6

S : Head number of the devices where index modification data is stored (pointer only) P (Pointer)
D : Head number of the devices where index modification data will be stored (except a pointer) (BIN 16 bits)
7
Setting Internal Devices J \ Other
R, ZR U \G Zn Constants
Data Bit Word Bit Word P

S –– –– ––
8
D –– –– ––

Function

7.6.13 Designation of modification values in index modification of entire ladders (IXDEV,IXSET)

7.6 Structure creation instructions
(1) The IXDEV and IXSET instructions are used to configure an index modification table used in
the IX and IXEND instructions.
(2) The device offset value designated at the offset designation area is set at the index
modification table designated by D .
(3) The value 0 will be entered if no designation is made.
(4) Word devices are also indicated by contact (word device bit designation). Data register 10
(D10) is designated with D10.0.
(Any value from 0 to F can be used for the bit number.)
(5) Designation is made according to the method described below. *1 (The symbol is where
the offset value will be. The notation XX indicates random selection.)
Device T C X Y M L V B
Designation T C X Y M L V B
method
Device D W R U/G J ZR

Designation D .XX R U \G *2
W .XX .XX .XX J \B
method

Device P

Designation *3
IXSET S D
method

*1: When using a basic model QCPU, the devices R, U/G, J, ZR and P cannot be used.
*2: Devices following J \ designate B, W, X, or Y, and the offset value is also set in correspondence with this.
*3: When using a basic model QCPU, specify a dummy device number. S is P .

7-147
 IXDEV,IXSET

(6) If two offsets for two identical types of device have been set in the offset designation area,
the last value set will be valid.
(7) The IXDEV and IXSET instructions should be treated as a pair.
(8) Any value from 0 to 32767 is valid for ZR. (The offset value will be the remainder of the
quotient of the designated device number divided by 32768.)
(9) The dummy contacts in the offset specifying part are valid for only LD and AND located
within the range of the IXDEV-IXSET instructions. The IXDEV-IXSET instructions will not be
executed if other instructions are described.
Example

IXDEV
Non-execution processing (outputs OFF)

Non-execution processing (ignored)

Valid dummy contacts INC D50

IXSET P3 D0

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• The IXDEV and IXSET instructions have not been used as a pair. (Error code: 4231)

7-148
 IXDEV,IXSET

Program Example
1
(1) The following program changes the modification values for input (X), output (Y), data
register (D) and pointer (P).
When using a basic model QCPU, the devices R, U/G, J, ZR and P cannot be used. 2
[Ladder Mode] [List Mode]
Step Instruction Device
3

4
Index modification ladder
*
6
Index modification
table 6
D0 4 T
0 C
5 X
3 Y 7
0 M
0 L
0 B
0 V 8
8 D
0 W
0

7.6.13 Designation of modification values in index modification of entire ladders (IXDEV,IXSET)

7.6 Structure creation instructions
D15 0 P

*4: Refer to 7.6.12 for index modification using the IX to IXEND instructions.

7-149
 FIFW(P)

7.7 Data Table Operation Instructions

7.7.1 Writing data to the data table (FIFW(P))

FIFW(P)

Basic High
performance Process Redundant Universal LCPU

Command
FIFW FIFW S D

Command
FIFWP FIFWP S D

S : Data to be written into the table or the number of the device where the data is stored (BIN 16 bits)
D : Head number of the table (BIN 16 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S ––

D –– –– –– ––

Function
(1) Stores the 16-bit data designated by S in the data table designated by D .
The number of data blocks stored in the table is stored at D , and the data designated by S

is stored in sequence from D +1.

Data table Data table
D 2 Number of stored data blocks D 3
D +1 5432 D +1 5432
D +2 1234 D +2 1234
D +3 0 Data table range D +3 4321
D +4 0 (controlled by the user) D +4 0

0 0

S 4321

(2) The first time the FIFW instruction is executed, any values in the designated by D device
should be cleared.
(3) The number of data blocks to be written in the data table and the data table range should be
controlled by the user.
[See Program Example (2)]

7-150
 FIFW(P)

Operation Error
1
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• The data table range exceeds the relevant device range when the FIFW instruction is 2
executed. (Error code: 4101)

Program Example 3

(1) The following program stores the data at D0 to the data table following R0 when X10 is
turned ON. 4
[Ladder Mode] [List Mode]
Step Instruction Device
6

6
[Operation]
Table Table
R0
R1
4
123
Number of stored data blocks R0
R1
5 7
123
R2 55 R2 55
R3 4321 R3 4321
R4 11
Data table range
R4 11 8
R5 0 R5 257

D0 257

7.7.1 Writing data to the data table (FIFW(P))

7.7 Data Table Operation Instructions
(2) The following program stores the data at X20 to X2F to data table of D38 to D44 table when
X1B is turned ON, and, if there are more than 6 data blocks to be stored, turns Y60 ON and
disables the FIFW instruction.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
Table Table
D38 5 Number of stored data blocks D38 6
D39 1000 D39 1000
D40 8100 D40 8100
D41 4321 D41 4321
Data table range
D42 1234 D42 1234
D43 123 D43 123
D44 0 D44 4444
D45 0 D45 0

X20 to X2F 4444

7-151
 FIFR(P)

7.7.2 Reading oldest data from tables (FIFR(P))

FIFR(P)

Basic High
performance Process Redundant Universal LCPU

Command
FIFR FIFR S D

Command
FIFRP FIFRP S D

S : Head number of the devices where the data read from the table will be stored (BIN 16 bits)
D : Head number of the table (BIN 16 bits)

Setting Internal Devices J \

R, ZR U \G Zn Constants Other
Data Bit Word Bit Word

S ––

D –– –– ––

Function
(1) Stores the oldest data ( D +1) input to the table designated by D at the device designated by
S .
After the execution of the FIFR instruction, the data in the table is all compressed up by one
block.
Data table Data table
D 3 Number of stored D 2
5432 data blocks 1234
D +1 D +1
D +2 1234 D +2 4321
D +3 4321 D +3 0 Stores 0.
D +4 0 D +4 0

0 0

S 5432

(2) Users should attempt to avoid executing the FIFR instruction if the value stored at D is 0.
[See Program Example (1)]

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The FIFR instruction was executed when the value at D was 0. (Error code: 4100)
• The data table range exceeded the corresponding device range at execution of the FIFR
instruction. (Error code: 4101)

7-152
 FIFR(P)

Program Example
1
(1) The following program stores the R1 data from the table R0 to R7 at D0 when X10 is turned
ON.
[Ladder Mode] [List Mode] 2
Step Instruction Device

[Operation] 4
Data table Data table
R0 5 Number of stored data blocks R0 4 Number of stored data blocks
R1
R2
123
55
R1
R2
55
4321
6
R3 4321 R3 123
R4 123 R4 234 Data table
R5 234 R5 0 6
R6 0 R6 0
R7 0 R7 0

D0 123
7
(2) The following program stores the data at D0 in the data table D38 to D43, and, when the
table stores 5 data, stores the data at D39 of the data table in R0, when X1C is turned ON. 8
[Ladder Mode] [List Mode]
Step Instruction Device

7.7.2 Reading oldest data from tables (FIFR(P))

7.7 Data Table Operation Instructions
[Operation]
Data table Data table Data table
Number of Number of Number of
D38 4 stored D38 5 stored D38 4 stored
data tables data tables data tables
D39 1234 D39 1234 D39 55
D40 55 D40 55 D40 1000 Executes the FIFWP
D41 1000 D41 1000 D41 123 instruction when X1C
Data turns ON again
D42 123 D42 123 D42 4444
table
D43 0 D43 4444 D43 0
D44 0 D44 0 D44 0
D45 0 D45 0 D45 0

Executes the FIFRP

D0 4444 R0 1234
instruction when D38=5.

7-153
 FPOP(P)

7.7.3 Reading newest data from data tables (FPOP(P))

FPOP(P)

Basic High
performance Process Redundant Universal LCPU

Command
FPOP FPOP S D

Command
FPOPP FPOPP S D

S : Head number of the devices where the data read from the table will be stored (BIN 16 bits)
D : Head number of the table (BIN 16 bits)

Setting Internal Devices J \

R, ZR U \G Zn Constants Other
Data Bit Word Bit Word

S ––

D –– –– ––

Function
(1) Stores the newest data input to the table designated by D at the device designated by S .
After the execution of the FPOP instruction, the device storing the data read by the FPOP
instruction is reset to 0.
Data table Data table
D 7 Number of stored D 6
D +1 1234 data blocks D +1 1234
D +2 5432 D +2 5432

-1000 -1000
D +7 -4321 D +7 0 Stores 0.
0 0

S -4321

(2) Perform interlock to avoid executing the FPOP instruction when the value stored at D is 0.
[See Program Example (1)]

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The FPOP instruction was executed when the value of D was 0. (Error code: 4100)
• The data table range exceeded the corresponding device range at execution of the FPOP
instruction. (Error code: 4101)

7-154
 FPOP(P)

Program Example
1
(1) The following program stores the data stored last in the data table R0 to R7 at D0 when X10
is turned ON.
[Ladder Mode] [List Mode] 2
Step Instruction Device

[Operation] 4
Data table Data table
R0 5 R0 4
R1
R2
-123
1400
R1
R2
-123
1400
6
R3 1234 R3 1234
R4 5432 R4 5432
R5 3000 R5 0 Stores 0. 6
R6 0 R6 0
R7 0 R7 0

D0 3000
7
(2) The following program stores the data at D0 in the data table D38 to D43 when X1C is
turned ON, and when the number of data stores in the table reaches 5, turns X1D ON, and 8
stores the data stored last in the data table to R0.
[Ladder Mode] [List Mode]
Step Instruction Device

7.7.3 Reading newest data from data tables (FPOP(P))

7.7 Data Table Operation Instructions
[Operation]
Data table Data table Data table
D38 4 D38 5 D38 4 Since the number of
D39 1234 D39 1234 D39 1234 stored data block is 4, the
D40 55 X1C:ON D40 55 X1D:ON D40 55 FIFWP instruction is
Data table
D41 1000 D41 1000 D41 1000 executed when XIC turns ON
range
D42 123 D42 123 D42 123
D43 0 D43 4444 D43 0
D44 0 D44 0 D44 0
D45 0 D45 0 D45 0

Executes the FPOPP

D0 4444 R0 4444
instruction when D38=5.

7-155
 FDEL(P),FINS(P)

7.7.4 Deleting and inserting data from and in data tables

(FDEL(P),FINS(P))
FDEL(P),FINS(P)

Basic High
performance Process Redundant Universal LCPU

indicates an instruction symbol of FDEL/FINS.

Command
FDEL, FINS S D n

Command
FDELP, FINSP P S D n

S : Head number of the devices where data to be inserted is stored (BIN 16 bits)
Head number of the devices where the data to be deleted will be stored (BIN 16 bits)
D : Head number of the table (BIN 16 bits)
n : Location on the table where data is inserted/deleted (BIN 16 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S –– ––

D –– –– –– ––

n ––

Function
FDEL

(1) Deletes the nth block of data from the data table designated by D , and stores it at the
device designated by S .
After the execution of the FDEL instruction, the data in the table following the deleted block
is compressed forward by one block.
Data table Data table
D 4 D 3
D +1 5432 D +1 5432
D +2 3333 D +2 3333
D +3 4444 D +3 1234
D +4 1234 D +4 0 Stores 0.
D +5 0 D +5 0

0 0

If n=3, data
at D +3 is deleted. S 4444

7-156
 FDEL(P),FINS(P)

FINS

(1) Inserts the 16-bit data designated by S at the nth block of the data table designated by D . 1
After the execution of the FINS instruction, the data in the table following the inserted block
is all dropped one position.
Data table Data table 2
D 3 Number of stored D 4
D +1 5432 data blocks D +1 5432
D +2
D +3
1234
123
D +2
D +3
4444
1234
Data table range 3
D +4 0 D +4 123
D +5 0 D +4 0
4
0 0

If n=2, data is inserted to D +2.

S 4444
6
Operation Error
6
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The Nth position from D is larger than the data storage number at the execution of the 7
FDEL instruction. (Error code: 4101)

• The Nth position from D is larger than the "data storage number + 1" at the execution of 8
the FINS instruction. (Error code: 4101)
• The value of n in the case of the FDEL, FINS instruction exceeds the device range of the
table D . (Error code: 4101)
• The FDEL or FINS instruction was executed when n 0. (Error code: 4100)

7.7.4 Deleting and inserting data from and in data tables (FDEL(P),FINS(P))
7.7 Data Table Operation Instructions
• The FDEL instruction was executed when the value of D was 0. (Error code: 4100)
• The data table range exceeded the corresponding device range at execution of the FDEL
or FINS instruction. (Error code: 4101)

7-157
 FDEL(P),FINS(P)

Program Example
(1) The following program deletes the second data from the table R0 to R7 and stores the
deleted data at D0 when X10 is turned ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
Data table Data table
R0 5 R0 4
X10:ON
R1 -123 R1 -123
R2 4444 R2 3210 Data table
Data table R3 R3 range
3210 1234
range
R4 1234 R4 5432
R5 5432 R5 0
R6 0 R6 0
R7 0 R7 0

D0 4444

(2) The following program inserts the data at D0 into the third position at the table R0 to R7
when X10 is turned ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
Data table Data table
R0 4 R0 5
X10:ON
R1 1234 R1 1234
R2 4444 R2 4444
R3 -123 R3 -3210
Data table
R4 5000 R4 -123
range
R5 0 R5 5000
R6 0 R6 0
R7 0 R7 0

D0 -3210

7-158
 FROM(P),DFRO(P)

7.8 Buffer memory access instruction

1
7.8.1 Reading 1-/2-word data from the intelligent function module
(FROM(P),DFRO(P)) 2
FROM(P),DFRO(P)

High
Ver. 3
Basic performance Process Redundant Universal LCPU

Universal model QCPU: Other than Q00UJCPU

4

6
indicates an instruction symbol of FROM/DFRO.

Command
FROM, DFRO n1 n2 D n3

Command 6
FROMP, DFROP P n1 n2 D n3

n1 : Head I/O number of an intelligent function module (BIN 16 bits) 7

n2 : Head address of data to be read (BIN 16 bits)
D : Head number of the devices where the read data will be stored (BIN 16/32 bits)
n3 : Number of data blocks to be read (BIN 16 bits)

Internal Devices
8
Setting J \ Constants Other
R, ZR U \G Zn
Data Bit Word Bit Word K, H U

n1

n2 ––

7.8.1 Reading 1-/2-word data from the intelligent function module (FROM(P),DFRO(P))
7.8 Buffer memory access instruction
D –– ––

n3 ––

Function
FROM
(1) Reads the data in n3 words from the buffer memory address designated by n2 of the
intelligent function module designated by n1, and stores the data into the area starting from
the device designated by D .
Intelligent function module
buffer memory Device designated CPU module
n2 by D
n3 words n3 points

7-159
 FROM(P),DFRO(P)

DFRO

(1) Reads the data in (n3 2) words from the buffer memory address designated by n2 of the
the intelligent function module designated by n1, and stores the data into the area starting
from the device designated by D .
Intelligent function module
buffer memory CPU module
Device designated
n2 by D
n2+1
(n3 2) words (n3 2) points

Data read from intelligent function modules is also possible with the use of an
intelligent function module device.
For the intelligent function module device, refer to the QnUCPU User's Manual
(Function Explanation, Program Fundamentals) or Qn(H)/QnPH/QnPRHCPU
User's Manual (Function Explanation, Program Fundamentals).

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• There has been no exchange of signals with an intelligent function module at the
execution of the instruction. (Error code: 1412)
• An error has been detected in an intelligent function module at the execution of the
instruction. (Error code: 1402)
• The I/O number designated by n1 is not for the intelligent function module.
(Error code: 2110)

• The range of n3 points (2 n3 points for DFRO) from the device designated by D
exceeds the designated device range. (Error code: 4101)
• The address designated by n2 is outside the buffer memory range.
(Error code: 4101)

7-160
 FROM(P),DFRO(P)

Program Example
1
(1) The following program reads the digital value of CH1 of the A68AD mounted at I/O numbers
040 to 05F into D0 when X0 is turned ON. (Reads 1 word of data from address 10 of the
buffer memory.) 2
[Ladder Mode] [List Mode]
Step Instruction Device
3

4
(2) The following program reads the X-axis present value of the AD71 mounted at the I/O
numbers 040 to 05F into D0 and D1, when X0 is turned ON. (Reads data in 2 words from
the address 602 and 603 of the buffer memory.)
6
[Ladder Mode] [List Mode]
Step Instruction Device
6

7
Remark
1. The value of n1 is specified by the upper 3 digits of hexadecimal 4-digit 8
representation of the head I/O number of the slot in which an intelligent
function module is mounted.
QCPU

7.8.1 Reading 1-/2-word data from the intelligent function module (FROM(P),DFRO(P))
7.8 Buffer memory access instruction
Power
Q68 QY41
supply CPU QX10 QX10 QX10 QX10 QY10 QY10
ADV P
module

0000H 0010H 0020H 0030H 0040H 0050H 0070H 0080H Head I/O number configured in
the I/O assignment setting

Specify the head I/O number to be read

by K4 or H4.

LCPU
CPU module
(L26CPU-BT)

Power
supply CPU Built-in Built-in LX40 LX40 LX40 LX40 L60 LY10 LY10 LY10
module I/0 CC-Link C6 C6 C6 C6 AD4 R2 R2 R2

0000H 0010H 0030H 0040H 0050H 0060H 0070H 0090H 00A0H 00B0H Head I/O number
configured in the
I/O assignment
setting
Specify the head I/O number to be read
by K6 or H6.

2. QCPU and LCPU establishe the automatic interlock of the FROM/DFRO

instructions.

7-161
 TO(P),DTO(P)

7.8.2 Writing 1-/2-word data to intelligent function module (TO(P),DTO(P))

TO(P),DTO(P)

Basic High
performance Process Redundant Universal LCPU

indicates an instruction symbol of TO/DTO.

Command
TO, DTO n1 n2 S n3

Command
TOP, DTOP P n1 n2 S n3

n1 : Head I/O number of an intelligent function module (BIN 16 bits)

n2 : Head address of the area where data is written (BIN 16 bits)
S : Data to be written or head number of the devices where the data to be written is stored (BIN 16/32 bits)
n3 : Number of data blocks to be written (BIN 16 bits)

Setting Internal Devices J \ Constants Other

R, ZR U \G Zn
Data Bit Word Bit Word K, H U

n1

n2 ––

S –– ––

n3 ––

Function
TO
Writes the data stored in n3 points starting from the device designated by S into the area
starting from buffer memory address designated by n2 of the intelligent function module
designated by n1.
Intelligent function module
CPU module buffer memory
Device designated 0
by S
n2
n3 points n3 words

When a constant is designated to S , writes the same data (value designated to S ) to the area
of n3 points starting from the specified buffer memory. ( S can be designated in the following
range: -32768 to 32767 or 0H to FFFFH.)
Intelligent function module
buffer memory
CPU module 0
S 5
(When 5 is designated to S ) n2 5
5 n3 words
5 (The same data is written)

7-162
 TO(P),DTO(P)

DTO
Writes the data stored in n3 2 points starting from the device designated by S into the area 1
starting from buffer memory address designated by n2 of the intelligent function module
designated by n1.
Intelligent function module 2
CPU module buffer memory
Device designated 0
by S
n2
n2+1
3
(n3 x 2) (n3 x 2)
points words
4
When a constant is designated to S , writes the same data (value designated to S ) to the area
of n3 2 points starting from the specified buffer memory. ( S can be designated in the following 6
range: -2147483648 to 2147483647 or 0H to FFFFFFFFH.)

6
Intelligent function module
buffer memory
CPU module 0
S 70000
n2
70000
(When 70000 is designated to S ) n2+1
7
70000 (n3 x 2) words
(The same data is written)
70000

Data write to intelligent function modules is also possible with the use of an

7.8.2 Writing 1-/2-word data to intelligent function module (TO(P),DTO(P))

7.8 Buffer memory access instruction
intelligent function module device.
For the intelligent function module device, refer to the QnUCPU User's Manual
(Function Explanation, Program Fundamentals) or Qn(H)/QnPH/QnPRHCPU
User's Manual (Function Explanation, Program Fundamentals).

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• There has been no exchange of signals with an intelligent function module at the
execution of the instruction. (Error code: 1412)
• An error has been detected in an intelligent function module at the execution of the
instruction. (Error code: 1402)
• The I/O number designated by n1 is not for the intelligent function module.
(Error code: 2110)
• The n3 points (2 n3 points for DTO) of the device designated by S exceed the
designated device range. (Error code: 4101)
• The address designated by n2 is outside the buffer memory range.
(Error code: 4101)

7-163
 TO(P),DTO(P)

Program Example
(1) The following program sets the CH1 and CH2 of the Q68ADV mounted at the I/O numbers
040 to 04F to the "A/D conversion" mode, when X0 is turned ON.
(Writes 3 into the buffer memory address 0.)
[Ladder Mode] [List Mode]
Step Instruction Device

(2) The following program sets the X-axis current value of the AD71 mounted at I/O numbers
040 to 05F to 0 when X0 is turned ON. (Writes 0 to addresses 41, 42 of the buffer memory.)
[Ladder Mode] [List Mode]
Step Instruction Device

Remark
1. The value of n1 is specified by the upper 3 digits of hexadecimal 4-digit
representation of the head I/O number of the slot in which an intelligent
function module is mounted.
QCPU

Power
Q68 QY41
supply CPU QX10 QX10 QX10 QX10 QY10 QY10
ADV P
module

0000H 0010H 0020H 0030H 0040H 0050H 0070H 0080H Head I/O number configured in
the I/O assignment setting

Specify the head I/O number to be read

by K4 or H4.

LCPU
CPU module
(L26CPU-BT)

Power
supply CPU Built-in Built-in LX40 LX40 LX40 LX40 L60 LY10 LY10 LY10
module I/0 CC-Link C6 C6 C6 C6 AD4 R2 R2 R2

0000H 0010H 0030H 0040H 0050H 0060H 0070H 0090H 00A0H 00B0H Head I/O number
configured in the
I/O assignment
setting
Specify the head I/O number to be read
by K6 or H6.

2. QCPU and LCPU establishe the automatic interlock of the TO/DTO

instructions.

7-164
 PR

7.9 Display instructions

1
7.9.1 Print ASCII code instruction (PR)
PR
2

3
High
Basic performance Process Redundant Universal LCPU

4
Command
PR PR S D
6

: ASCII code or head number of the devices where the ASCII code is stored (character string)
6
S

D : Head number of the output module to which the ASCII code will be output (bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data $

S
Bit

––
Word
*1
Bit Word

–– ––
7
D (Only Y) –– –– –– ––

*1: Local devices and the file registers set for individual programs cannot be used. 8

Function

7.9.1 Print ASCII code instruction (PR)

7.9 Display instructions
(1) Outputs ASCII code stored in the device specified by S or ASCII code stored in the area
startings from the device number to an output module specified by D .
The number of characters output differs according to the ON/OFF status of SM701
(number of output characters selection).

(a) If SM701 is ON, characters 8 points (16 characters) from the device designated by S

will be the target of the operation.

Device where ASCII code is stored

Upper 8 bits Lower 8 bits

b15 b8 b7 b0 Output Y
S +0 42 H (B) 41 H (A) Head of output D
S +1 44 H (D) 43 H (C)
50 H
4F H
4EH
4DH
4CH
4BH
4AH
49 H
48 H
47 H
46 H
45 H
44 H
43 H
42 H
41 H

S +2 46 H (F) 45 H (E)
S +3 48 H (H) 47 H (G)
S +4 4A H (J) 49 H (I)
S +5 ASCII code output
4CH (L) 4B H (K)
Printer or
S +6 4E H (N) 4DH (M)
S +7 display device
50 H (P) 4F H (O) D +7
D +8
Strobe signal output
Sequence D +9
Flag indicating PR
program instruction in execution

Used as interlock

7-165
 PR

(b) If SM701 is OFF, everything from the device designated by S to the 00H code will be
the target of the operation.
Device where ASCII code is stored

Upper 8 bits Lower 8 bits

b15 b8 b7 b0 Output Y
S +0 42 H (B) 41 H (A) Head of output D
S +1 44 H (D) 43 H (C)

4CH
4B H
4A H
49 H
48 H
47 H
46 H
45 H
44 H
43 H
42 H
41 H
S +2 46 H (F) 45 H (E)
S +3 48 H (H) 47 H (G)
S +4 4A H (J) 49 H (I)
ASCII code output
S +5 4C H (L) 4B H (K)
Scheduled Printer or
S +6 4E H (N) 00 H (NULL) completion display device
S +7 50 H (P) 4F H (O) D +7
D +8
Sequence program Strobe signal output
D +9
Flag indicating PR
instruction in execution
Used as interlock

(2) The number of points used by the output module is 10 points from the Y address designated
by D .
(3) Output signals from the output module are transmitted at the rate of 30 ms per character.
For this reason, the time required to the completion of the transmission of the designated
number of characters (n) will be 30 ms n (ms).
At 10 ms interrupt intervals, the PR instruction executes data output, strobe signal ON, and
strobe signal OFF. The other instructions are executed continuously during a period
between the above processings.
Execution of sequence program PR instruction processing

Data output

ON
OFF
Strobe signal

10 ms 10 ms 10 ms 10 ms 10 ms

30 ms

(4) In addition to the ASCII code, the output module also outputs a strobe signal (10 ms ON, 20
ms OFF) from the D + 8 device.

(5) Following the execution of the PR instruction, the PR instruction execution flag ( D + 9
device) remains ON until the completion of the transmission of the designated number of
characters.
(6) The PR and PRC instructions can be used multiple times, but it is preferable to establish an
interlock with the PR instruction execution flag ( D + 9 device) so that they will not be ON
simultaneously.
(7) If the contents of the device in which ASCII codes are stored changes during the ASCII code
output, the modified data after change will be output.

7-166
 PR

Operation Error
1
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• There is no 00H code within the range of the device specified by S when SM701 is OFF.
2
(Error code: 4101)

3
Program Example
(1) The following program converts the string "ABCDEFGHIJKLMNOP" to ASCII code when X0
4
is turned ON and stores it from D0 to D7, and then outputs the ASCII code at D0 to D7 to
Y14 to Y1D when X3 is turned ON.
[Ladder Mode] 6

When X0 turns ON, converts “ABCDEFGHIJKLMOP”

to the ASCII code and stores it to D to D7. 6

When X3 turns ON, outputs the ASCII 7

code in D0 to D7 to Y14 to Y1D.

8
[List Mode]
Step Instruction Device

7.9.1 Print ASCII code instruction (PR)

7.9 Display instructions
[Timing Chart]
ON
OFF
X0
$MOV "ABCDEFGH" D0

Stores the ASCII

code for "A" to "H"
$MOV "IJKLMNOP" D4 to D0 to D3.

Stores the ASCII code for

"I" to "P" to D4 to D7.
X3

A B P
Y14
ASCII code 41H 42H 50H
Y1B
10 10
10 ms ms ms
10 ms
PR instruction
OFF
Strobe signal Y1C
ON
OFF
PR instruction in PR instruction in execution 480 ms
execution flag Y1D

7-167
 PRC

7.9.2 Print comment instruction (PRC)

PRC

High
Basic performance Process Redundant Universal LCPU

Command
PRC PRC S D

S : Head number of the device which prints the comment (Device name)
D : Head number of the output module which outputs the comment (bits)

Setting Internal Devices J \ Other

R, ZR U \G Zn Constants
Data Bit Word Bit Word P, I, J, U,

S –– ––

D (Only Y) –– –– –– –– ––

Function
(1) Outputs comment (ASCII code) at device designated by S to output module designated by
D .
The number of characters output differs according to the ON/OFF status of SM701.
• When SM701 is OFF: Comment is 32 characters
• When SM701 is ON : Comment is the upper 16 characters
The number of points used by the output module is 10 points from the Y address
designated by D .

PRC X1 Y30

Comment at X1
Output Y
A B C D E F G H I K K L M n O
Y30
Head of output

ASCII code output

Printer or
display device
Y37
Y38
Strobe signal output
Sequence Y39
program Flag indicating PRC
instruction in execution
Used as interlock

7-168
 PRC

[Timing Chart]

1
A B C n O
Y30 to Y37 Preprocessing 41H 42H 43H 4EH 4FH
(several scans) 30 ms
ON

PRC
OFF 2
ON
Y38
(Strobe signal)
OFF
3
10 10 10
ms ms ms
ON
Y39 OFF
(Flag indicating strobe 30ms x 16 = 480 ms 4
signal is being output)
ON
SM721 OFF
(File access in
progress flag) PRC instruction cannot be executed again.
6
ON
SM720 OFF
(File access
completion flag) None of Instructions other than PRC instruction (SP.FREAD, 6
instructions can SP.FWRITE, PUNROAD, PLOAD, PSWAPP) can be executed.
be executed.

(2) Output signals from the output module are transmitted at the rate of 30 ms per character. 7
For this reason, the time required to the completion of the transmission of the designated
number of characters will be 30 ms n (ms).
At 10ms interrupt intervals, the PRC instruction executes data output, strobe signal ON, and 8
strobe signal OFF. The other instructions are executed continuously during a period
between the above processings.
Execution of sequence program Processing of PRC instruction

7.9.2 Print comment instruction (PRC)

7.9 Display instructions
Data output

ON
OFF
Strobe signal

10 ms 10 ms 10 ms 10 ms 10 ms

30 ms

(3) In addition to the ASCII code, the output module also outputs a strobe signal (10 ms ON, 20
ms OFF) from the D + 8 device.
(4) Following the execution of the PRC instruction, the PRC instruction execution flag ( D + 9
device) remains ON until the completion of the transmission of the designated number of
characters.
(5) The PRC instruction can be used multiple times, but it is preferable to establish an interlock
with the PRC instruction execution flag ( D + 9 device) so that they will not be ON
simultaneously.
(6) If no comments have been registered at the device designated by S , processing will not be
performed.
(7) When a comment is read, SM720 turns ON for one scan after the instruction is completed.
SM721 turns ON during the execution of the instruction.
The PRC instruction cannot be executed while SM721 is ON. If the attempt is made, no
processing is performed.

7-169
 PRC

1. For device comments used with the PRC instruction, use comment files stored
in the memory card Standard Rom.
Comment files stored in the program memory cannot be used.
2. The comment file used by the PRC instruction is set at the "PLC File Setting"
option in the PLC parameter dialog box.
If no comment file has been set for use by the PLC file setting, it will not be
possible to output device comments with the PRC instruction.
3. Do not execute the PRC instruction during an interrupt program.
Otherwise, malfunction may occur.

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• The PRC instruction is executed while a comment is written during RUN.
(Error code: 4100)

Program Example
(1) Program which outputs the comment of Y60 to Y30 to Y39 when X0 is turned ON.
[Ladder Mode] [List Mode]
Step Instruction Device

7-170
 LEDR

7.9.3 Error display and annunciator reset instruction (LEDR)

LEDR
1
High
2
Basic performance Process Redundant Universal LCPU

3
Command
LEDR LEDR
4

Setting Internal Devices

Data Bit Word
R, ZR
Bit
J \
Word
U \G Zn Constants Other
6
–– ––

6
Function
Resets the self-diagnosis error display so that annunciator display or operation can be continued. 7
With one execution of this instruction, either error display or annunciator is reset.
(1) Operation when self-diagnosis error is generated
8
(a) If the self-diagnosis error is one which allows continued operation.
If the self-diagnosis error being displayed is one that will allow continued operation of
the CPU module, the "ERROR/ERR." LED or error indication is reset. It will be
necessary to reset SM0, SM1, and SD0 at the user program, because they are not reset

7.9.3 Error display and annunciator reset instruction (LEDR)

7.9 Display instructions
automatically.
Since the cause of the error displayed at this time has a higher priority over annunciator,
no action for resetting the annunciator is taken.

(b) When a battery error is generated.

If the LEDR instruction is executed after the battery has been replaced, the "BAT. ARM/
BAT." LED at the front of the CPU module and the error display will be reset.
SM51 is also turned OFF at this time.

7-171
 LEDR

(2) Operations when an annunciator (F) is ON.

(a) When the CPU module has no LED display
The following operations will be conducted when the LEDR instruction is executed:
1) "USER" LED flickers, and is turned OFF
2) The annunciators (F) stored in SD62 and SD64 are reset, and the F numbers for
SD65 to SD79 are moved up.
3) The data newly stored at SD64 is transmitted to SD62.
4) The data at SD63 is decremented by 1. However, if SD63 is 0, it remains 0.
Before execution After execution
SD62 200 SD62 99
Decrements 1.
SD63 15 SD63 14 Number of registered F numbers
SD64 200 SD64 99
SD65 99 SD65 5
SD66 5 SD66 255
SD67 255
F number storage area

SD77 83
SD78 83 SD78 0
SD79 0 SD79 0

(b) For CPUs with an LED display at the front

The following operations will be conducted when the LEDR instruction is executed:
1) The F number being displayed at the front of the CPU module will be reset.
2) "USER" LED flickers, and is turned off.
3) The annunciators (F) stored in SD62 and SD64 are reset, and the F numbers for
SD65 to SD79 are compressed forwards.
4) The data newly stored at SD64 is transmitted to SD62.
5) The data at SD63 is decremented by 1. However, if SD63 is 0, it remains 0.
6) The F number being stored at SD62 is displayed at the LED display. However, if the
value of SD63 is 0, nothing will be displayed.
Before execution After execution
SD62 200 SD62 0 F number is not displayed on the
LED display unit since SD63 is 0.
Decrements 1.
SD63 1 SD63 0
SD64 200 SD64 0
SD65 0 SD65 0 Number of registered F numbers
SD66 0 SD66 0
SD67 0

SD77 0
SD78 0 SD78 0
SD79 0 SD79 0

7-172
 LEDR

Remark
1. The defaults for the error item numbers set in special registers SD207 to
1
SD209 and order of priority are given in the table below:

Priority
Factor number
Meaning Remarks 2
(Hexadecimal)
Power supply cut
AC DOWN Redundant base unit power supply voltage
1 1 SINGLE PS.DOWN drop (QCPU only)
3
SINGLE PS.ERROR Redundant power supply module fault (QCPU
only)
I/O module verify error (QCPU only) 4
UNIT VERIFY ERR. Blown fuse (QCPU only)
FUSE BREAK OFF Special function module verify error (QCPU
2 2
SP. UNIT ERROR
SP. UNIT DOWN
only)
Intelligent function module verification error
6
Intelligent function module error (LCPU only)
OPERATION ERROR [Operation Errors]
LINK PARA.ERROR Link parameter error (QCPU only) 6
SFCP OPE. ERROR SFC instruction operation error (QCPU only)
3 3
SFCP EXE. ERROR SFC program execution error (QCPU only)
REMOTE PASS.FAIL
SNTP OPE.ERROR
Remote password error (LCPU only)
SNTP error (LCPU only)
7
Memory card operation error
File access error
ICM.OPE ERROR Extend instruction error (QCPU only) 8
FILE OPE. ERROR Operation status, switch mismatch (QCPU
EXTEND INST. ERROR only)
OPE. MODE DIFF. Current mode-time function execution disabled
4 4 CAN'T EXE.MODE (QCPU only)
TRK.TRANS.ERR. Tracking data transmission error (QCPU only)

7.9.3 Error display and annunciator reset instruction (LEDR)

7.9 Display instructions
TRK.SIZE ERROR Tracking capacity excess error (QCPU only)
TRK.DISCONNECT Tracking cable not connected, failure (QCPU
FLASH ROM ERROR only)
Flash ROM access count exceeded error
(LCPU only)
Constant scan setting time over error
5 5 PRG.TIME OVER Low speed execution monitoring tome over
error (QCPU only)
6 6 CHK instruction ––
7 7 Annunciators ––
8 8 LED instruction ––
9 9 BATTERY ERR. ––
10 A Clock data ––
System switching error (QCPU only)
CAN'T SWITCH
Standby system not started/stop error (QCPU
11 B STANDBY SYS.DOWN
only)
MEM.COPY EXE.
Memory copy function executed (QCPU only)
12 C DISPLAY ERROR Display unit error (LCPU only)

2. If the highest priority is given to the annunciator, it can be reset with priority by
the LEDR instruction. (Basic model QCPU, High Performance model QCPU,
Process CPU, and Redundant CPU)

7-173
 CHKST,CHK

7.10 Debugging and failure diagnosis instructions

7.10.1 Special format failure checks (CHKST,CHK)

CHKST,CHK

High
Basic performance Process Redundant Universal LCPU

Command
CHKST CHKST

X X X X
CHK CHK

Check condition (Only a contact is valid; b contact is ignored)

Only input (X) can be used

Up to 150 contacts can be connected

Setting Internal Devices J \

R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
–– ––

Function
CHKST
(1) The CHKST instruction is the instruction that starts the CHK instruction.
If the command for the CHKST instruction is OFF, execution jumps from the CHK instruction
to the next instruction.
If the command for the CHKST instruction is ON, the CHK instruction is executed.
TO
CHKST

X0 X2
When T0 is OFF,
CHK
program jumps to the
instruction next to the
CHK instruction. Y10

CHK
(1) The CHK instruction is the instruction used for the bidirectional operation as shown on the
following page to confirm the nature of the system failure.
(a) When the CHK instruction is executed, a failure diagnosis check is conducted with the
designated check conditions, and if a failure is detected, SM80 is turned ON, and the
failure number is stored at SD80 as a BCD value.
The error code "9010" will be returned if a failure is detected.
The contact number where the failure was discovered is stored at the upper 3 digits of
SD80 (see (3)), and the coil number where the failure was detected (see (2)) is stored at
the lower 1 digit of SD80.
At the detection of failure of
Contact No.: 62, Coil No.: 3
Before the detection of failure After the detection of failure
SM80 OFF SM80 ON
SD80 0 0 0 0 SD80 0 6 2 3

7-174
 CHKST,CHK

(b) The contact instruction prior to the CHK instruction does not control the execution of the
CHK instruction, but rather sets the check conditions.
1
Advance command (X4)
Advance operation
(Y50)
Advance
2
M Retract operation
(Y51)

Advance end sensor (X0)

Retract
Retract end sensor (X1)
3
turns ON at the detection turns ON at the detection
Retract command (X5)

(c) A ladder such as the one shown below can be created to perform a cycle time over 4
check for the system shown above:
T0
6
When T0 is OFF, program jumps to the instruction
CHKST next to the CHK instruction.
X000 Executes CHK instruction when T0 is ON.
CHK
X004 X005 X000

Y050
Y050 Advances conveyor 1.
6
SET Y000 Turns ON the internal relay used for failure detection.
X005 X004 X001
Y051 Retracts conveyor 1.
Y051 7
RST Y000 Turns OFF the internal relay used for failure detection.
Y050 X000 K100
T0 Cycle time
Y051 X001 check timer 8

(d) The following points should be taken into consideration when creating a ladder for use
with the CHK instruction:
1) The contact numbers for the advance edge detection sensor and the retract edge

7.10.1 Special format failure checks (CHKST,CHK)

7.10 Debugging and failure diagnosis instructions
detection sensor (X ) must always be continuous. Further, the contact number (X )
for the advance edge detection sensor should be lower than that for the retract edge.
2) Controls for the advance edge detection sensor contact number (X ) and output with
the identical number (Y ) *1 are as follows:
When advance operation is in progress .... turn ON
When retract operation is in progress........ turn OFF

*1: Output (Y ) is treated as an internal relay, and cannot be output to an external device.

7-175
 CHKST,CHK

(2) Depending on the designated contact, the CHK instruction undergoes processing identical
to that shown for the ladder below:
TO
CHKST
X X
CHK (Detection by both advance and retraction end sensors
Max. 150 contacts during advance operation of the conveyor)
X X +1 Y
Coil No. 1 SET SM80

MOV Failure No. 1 SD80

(Detection by both advance and retraction end sensors
Example X X0 during retract operation of the conveyor)
X +1 X1 X X +1 Y
Y Y0 Coil No. 2 SET SM80

Executes the same processing MOV Failure No. 2 SD80

as the ladder indicated above (Advance operation of the conveyor at the detection
by the advance end sensor)
X Y
Coil No. 3 SET SM80

MOV Failure No. 3 SD80

(Retract operation of the conveyor at the detection
by the retraction end sensor)
Y X +1
Coil No. 4 SET SM80

MOV Failure No. 4 SD80

(Advance operation of the conveyor during no detection
by the retraction end sensor)
Y X +1
Coil No. 5 SET SM80

MOV Failure No. 5 SD80

(Retract operation of the conveyer at the detection
by the advance end sensor)
Y X
Coil No. 6 SET SM80

MOV Failure No. 6 SD80

(3) Numbers 1 to 150 from the vertical bus on the left side have been allocated as contact
numbers during failure detection.
X5 X7 X9 X1A X1C
CHK

Contact No. 1 2 3 149 150

(4) Reset SM80 and SD80 prior to forcing the execution of the CHK instruction.
After the execution of the CHK instruction, it cannot be performed once again until SM80
and SD80 have been reset.
(The contents of SM80 and SD80 will be preserved until reset by user.)
(5) A CHKST instruction must be placed before the CHK instruction.
An error will be returned if an instruction other than the LD, LDI, AND or ANI instruction is
used between the CHK instruction and the CHKST instruction. (Error code: 4235)
(6) The CHK instruction can be written at any step of the program.
However, there is a limit in the number of uses of the CHK instruction.
• Can be used up to two places in all program files being executed.
• Can be used only one place in a single program file.
An error will be returned if the CHK instruction is used exceeding the number of uses
specified above. (Error code: 4235)

7-176
 CHKST,CHK

(7) Place LD and AND instructions prior to the CHK instruction to establish a check condition.
Check conditions cannot be set using other contact instructions.
If a check condition has been set with LDI or ANI, the processing for the check condition 1
they specify will not be conducted.
However, contact numbers during failure detection can also be allocated to the LDI and ANI
instructions. 2
Does not execute check

X5 X7 X9 XA X1A X1C
CHK 3
Contact No. 1 2 3 4
Contact numbers are allocated
4
(8) The failure detection method differs according to whether SM710 is ON or OFF.
(a) If SM710 is OFF, checks will be conducted of coil numbers 1 to 6 for each contact
successively. 6
When the CHK instruction is executed, checks will be in order from coil No. 1 of contact
No. 1, through coil No. 6, then move on to contact No. 2 and check the coils in order
from No. 1.
The CHK instruction will be completed when coil No. 6 from contact No. n has been
6
checked.
(b) If SM710 is ON, checks will be conducted of contact numbers 1 through n, in coil
number order. 7
When the CHK instruction is executed, checks will begin with the ladder for coil No. 1, in
order from contact No. 1 until contact No. n, then move on to the coil No. 2 ladder and
begin from contact No. 1. 8
The CHK instruction will be completed when a check has been made through contact
No. n of coil No. 6.
(9) If more than one failure is detected, the number of the first failure detected will be stored.
Failure numbers detected after this will be ignored.

7.10.1 Special format failure checks (CHKST,CHK)

7.10 Debugging and failure diagnosis instructions
(10) The CHK instruction cannot be used by a low speed execution type program.
If a low speed execution type program has been set in a program file containing the CHK
instruction, an operation error will be returned, and the CPU module operation will be
suspended.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• There is a parallel ladder. (Error code: 4235)
• There is an NOP instruction. (Error code: 4235)
• There are more than 150 contact instructions. (Error code: 4235)
• A CHK instruction is not executed following the CHKST instruction.
(Error code: 4235)
• The CHK instruction is executed when no CHKST instruction has been executed.
(Error code: 4235)
• The CHKST and CHK instruction are used in a low speed execution type program.
(Error code: 4235)
• There is an instruction other than the LD, LDI, AND or ANI instruction between the CHK
instruction and the CHKST instruction. (Error code: 4235)
• The CHK instruction is used at three places or more in all of programs being executed.
(Error code: 4235)
• The CHK instruction is used at two places or more in a single program.
(Error code: 4235)

7-177
 CHKCIR,CHKEND

7.10.2 Changing check format of CHK instruction (CHKCIR,CHKEND)

CHKCIR,CHKEND

High
Basic performance Process Redundant Universal LCPU

When the GX Developer is used (High Performance model QCPU/Process CPU/

Redundant CPU)

Command
CHKST CHKST Refer to
Section
7.10.1.
X X X X
CHK CHK

SM400
CHKCIR CHKCIR

Fn

Ladder pattern to be checked Fn Max. 9 coils

Fn

SM400
CHKEND CHKEND

Setting Internal Devices J \

R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
–– ––

Function
CHKCIR, CHKEND
(1) The check ladder pattern that will be used in the CHK instruction can be updated to any
format desired.
The actual failure checks are conducted with the CHKST and CHK instructions.
(2) Failure checks are conducted according to the check conditions designated by the CHK
instruction and the ladder pattern described between the CHKCIR and CHKEND
instructions.

Remark
Refer to 7.10.1 for more information on the CHKST and CHK instructions.

To change the check format of the CHK instruction using the CHKCIR to CHKEND
instructions, the user should create a ladder with index modification (Z0).

7-178
 CHKCIR,CHKEND

(a) The device numbers indicated at check conditions (X2 and X8 in the figure below) will
assume index modification values for the individual device numbers (with the exception
of annunciators (F)) described in the ladder patterns.
1
Example X10 in the in the figure below would be as follows:

When corresponding to check condition X2 Processing performed by ...X12

2
When corresponding to check condition X8 Processing performed by ...X18

However, the order in which failure detection is executed differs depending on whether 3
SM710 is ON or OFF.
1) If SM710 is OFF, checks will be conducted of coil numbers 1 through the end for
each contact successively. 4
[Ladder designated by CHKCIR to CHKEND] [Order of check by CPU module]

CHKST
X12 X14 Y42 X8
F0
6
X2 X8 XA

6
CHK F1
Ladder
SM400 Y60 X23 Y48 X1C equivalent to X2
CHKCIR F2

X10Z0 X12Z0 Y40Z0 X6Z0

F0
Y61 X24
7
X8Z0 X18 X1A Y48 XE

8
F1 F0

Y5EZ0 X21Z0 Y46Z0 X1AZ0 X10

F2 F1
Ladder
Y5FZ0 X22Z0 Y66 X29 Y4E X22 equivalent to X8
F2

7.10.2 Changing check format of CHK instruction (CHKCIR,CHKEND)

7.10 Debugging and failure diagnosis instructions
SM400 Y67 X2A
CHKEND

2) If SM710 is ON, checks will be conducted of contact numbers 1 through the end, in
coil number order.
[Ladder designated by CHKCIR to CHKEND] [Order of check by CPU module]

X12 X14 Y42 X8

CHKST F0

X2 X8 X18 X1A Y48 XE

CHK F0

SM400 X12 X14 XA

CHKCIR F1

X10Z0 X12Z0 Y40Z0 X6Z0 Y18 X1A X10

F0 F1

X8Z0 Y60 X23 Y48 X1C

F1 F2

Y5EZ0 X21 Z0 Y46Z0 X1AZ0 X61 X24

F2

Y5FZ0 X22Z0 Y66 X29 Y4E X22

F2

SM400 Y67 X2A

CHKEND

7-179
 CHKCIR,CHKEND

(b) Failure checks check the ON/OFF status of OUT F by using the ladder pattern in the
various check conditions.
In all check conditions, SM80 will be turned ON if even one of the OUT F is ON in a
ladder pattern.
Further, the error numbers (contact numbers and coil numbers) corresponding to the
OUT F which were found to be ON will be stored from SD80 in BCD order.

(c) The instructions that can be used in ladder patterns are as follows:
Contacts ... LD, LDI, AND, ANI, OR, ORI, ANB, ORB, MPS, MPP,MRD, and
comparative operation instructions
Coil ........... OUT F

(d) The following devices can be used for ladder pattern contacts:
Input (X), Output (Y)

(e) Only annunciators (F) can be used in ladder pattern coils.

However, since annunciators (F) are used as a dummy, any value can be set for an
annunciator (F).
Further, they can overlap with no difficulties.

(f) ON/OFF controls can be performed without error if an annunciator (F) used during the
execution of the CHK instruction has the same number as an annunciator (F) used in
some other context than the CHK instruction. They will be treated differently during the
CHK instruction than they are in the different context.

(g) Since the annunciators (F) used in the CHK instruction do not turn ON/OFF actually,
they will not turn ON/OFF if monitored by a peripheral device.

(h) A ladder pattern can be created up to 256 steps.

Further, OUT F can use up to 9 coils.

(3) Coil numbers for ladders designated with the CHKCIR through CHKEND instructions are
allocated coil numbers from 1 to 9, from top to bottom.
SM400
CHKCIR

F
Coil No. 1

F
Coil No. 2

to
F
Coil No. 8

F
Coil No. 9
SM400
CHKEND

7-180
 CHKCIR,CHKEND

(4) The CHKCIR and CHKEND instructions can be written at any step in the program desired.
It can be used in up to two locations in all program files being executed.
However, the CHKCIR and CHKEND instructions cannot be used in more than 1 location in
1
a single program file.
(5) The CHKCIR and CHKEND instructions cannot be used in low speed execution type 2
programs.
If a program file in which the CHKCIR or CHKEND instruction is described is set as a low
speed execution type program, an operation error will occur, and the High Performance
model QCPU/Process CPU/Redundant CPU operation will be suspended.
3

Operation Error 4
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
6
• The CHKCIR or CHKEND instruction appears three or more times in all program files.
(Error code: 4235)
• The CHKCIR or CHKEND instruction appears two or more times in a single program file. 6
(Error code: 4235)
• The CHKEND instruction is not executed following the execution of the CHKCIR
instruction. (Error code: 4230) 7
• The CHKEND instruction is executed although no CHKCIR instruction has been
executed. (Error code: 4230)
• The CHKST and CHK instruction are used in a low speed execution type program. 8
(Error code: 4235)
• There are 10 or more F instances in a ladder pattern. (Error code: 4235)
• A ladder pattern has 257 or more steps. (Error code: 4235)

7.10.2 Changing check format of CHK instruction (CHKCIR,CHKEND)

7.10 Debugging and failure diagnosis instructions
• A device has been encountered which cannot be used in a ladder pattern.
(Error code: 4235)
• Index modification has been conducted on a ladder pattern device.
(Error code: 4235)

7-181
 BINDA(P),DBINDA(P)

7.11 Character string processing instructions

7.11.1 Conversion from BIN 16-bit or 32-bit to decimal ASCII

(BINDA(P),DBINDA(P))
BINDA(P),DBINDA(P)

High
Basic performance Process Redundant Universal LCPU

indicates an instruction symbol of BINDA/DBINDA.

Command
BINDA, DBINDA S D

Command
BINDAP, DBINDAP P S D

S : BIN data to be converted to ASCII (BIN 16/32 bits)

D : Head number of the devices where the conversion result will be stored (character string)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S ––

D –– –– ––

Function
BINDA
(1) Converts the individual digit numbers of decimal notation of the BIN 16-bit data designated
by S into ASCII codes, and stores the results into the area starting from the device
designated by D .
b15 b8 b7 b0
D ASCII code for ten-thousands place Sign
b15 b0
D +1 ASCII code for hundreds place ASCII code for thousands place
S
D +2 ASCII code for units place ASCII code for tens place
BIN 16-bit data D +3 0 Only when
SM701 is OFF

For example, if 12345 has been designated at S , the following will be stored from D

onward:
b15 b8 b7 b0
D 31H (1) 2DH ( )
b15 b0
D +1 33H (3) 32H (2)
S 1 2 3 4 5
D +2 35H (5) 34H (4)
D +3 00H

(2) The BIN data designated at S can be in the range from 32768 to 32767.

7-182
 BINDA(P),DBINDA(P)

(3) The operation results stored at D are as follows:

(a) The sign "20H" will be stored if the BIN data is positive, and the sign "2DH" will be stored 1
if it is negative.

(b) The sign "20H" will be stored for the leading zeros of effective digits. (Zero suppression
is conducted.)
2
00325
Number of significant digits
20H is set
3
(c) The storage of data at devices specified by D +3 differs depending on the ON/OFF
status of SM701 (output number of characters conversion signal). 4
When SM701 is OFF......Stores "0"
When SM701 is ON ......Does not change

DBINDA
6
(1) Converts the individual digit numbers of decimal notation of the BIN 32-bit data designated
by S into ASCII codes, and stores the results into the area starting from the device 6
designated by D .
b15 b8b7 b0
D ASCII code for billions place Sign 7
D +1 ASCII code for ten-millions place ASCII code for hundred-mil ions place
S +1 S
D +2 ASCII code for hundred-thousands place ASCII code for millions place
Upper 16 bits Lower 16 bits
8
D +3 ASCII code for thousands place ASCII code for ten-thousands place
BIN 32-bit data D +4 ASCII code for tens place ASCII code for hundreds place
D +5 0 or 20 H ASCII code for units place
When SM701 is OFF 0
When SM701 is ON 20 H

For example, if the value 12345678 has been designated by S , the following would be

7.11.1 Conversion from BIN 16-bit or 32-bit to decimal ASCII (BINDA(P),DBINDA(P))

7.11 Character string processing instructions
stored into the area starting from D :
b15 b8b7 b0
D 20H (space) 2D H ( )
D +1 31H (1) 20 H (space)
S +1 S
D +2 33H (3) 32 H (2)
12 3 4 5 6 7 8
D +3 35H (5) 34 H (4)
D +4 37H (7) 36 H (6)
D +4 0 or 20 H 38 H (8)

(2) BIN data designated by S can be between 2147483648 to 2147483647.

(3) The operations results stored at D will be stored in the following way:
(a) The sign "20H" will be stored if the BIN data is positive, and the sign "2DH" will be stored
if it is negative.

(b) The sign "20H" will be stored for the leading zeros of effective digits. (Zero suppression
is conducted.)
0012034560
20H Number of significant digits

(c) The data stored at the upper 8 bits of the device designated by D +5 differs depending
on the ON/OFF status of SM701 (number of characters to output select signal).
When SM701 is OFF......Stores "0"
When SM701 is ON .......Stores "20H"

7-183
 BINDA(P),DBINDA(P)

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• The device specified by D exceeds the range of the corresponding device.
(For the Universal model QCPU, LCPU.) (Error code: 4101)

Program Example
(1) The following example program uses the PR instruction to output the 16-bit BIN data W0
value by decimal to Y40 to Y48 as ASCII.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
Conducts ASCII output of Y40 to Y48 by using the PR instruction when X0 goes ON.
Because SM701 is OFF, the PR instruction will output ASCII code until 00H is encountered.
b15 b8 b7 b0
D0 20 H(space) 20 H(space)
W0 PR
D1 31 H (1) 35 H (5)
5126 Y40 to Y48
D2 36 H (6) 32 H (2)
BIN value
D3 00 H is output.

(2) The following program uses the PR instruction to output the decimal value of the 32-bit BIN
data at W10 and W11 in ASCII code to Y40 to Y48.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
Conducts ASCII output of Y40 to Y48 by using the PR instruction when X0 goes ON.
Because SM701 is OFF, the PR instruction will output ASCII code until 00H is encountered.
b15 b8 b7 b0
D0 20 H (space) 2D H ( )
PR
D1 20 H (space) 20 H (space)
W11 W10 Y40 to Y48
D2 38 H (8) 33 H (3) - 3842563
3 8 4 2 5 6 3
D3 32 H (2) 34 H (4) is output.
BIN value
D4 36 H (6) 35 H (5)
D5 00 H 33 H (3)

7-184
 BINHA(P),DBINHA(P)

7.11.2 Conversion from BIN 16-bit or 32-bit data to hexadecimal

ASCII (BINHA(P),DBINHA(P)) 1
BINHA(P),DBINHA(P)

High
2
Basic performance Process Redundant Universal LCPU

3
indicates an instruction symbol of BINHA/DBINHA.

Command 4
BINHA, DBINHA S D

6
Command
BINHAP, DBINHAP P S D

S : BIN data to be converted to ASCII (BIN 16/32 bits) 6

D : Head number of the devices where the conversion result will be stored (character string)

Setting Internal Devices J \ Constants

Data Bit Word
R, ZR
Bit Word
U \G Zn
K, H
Other
7
S ––

–– –– ––
8
D

Function
BINHA

7.11.2 Conversion from BIN 16-bit or 32-bit data to hexadecimal ASCII (BINHA(P),DBINHA(P))
7.11 Character string processing instructions
(1) Converts the individual digit numbers of hexadecimal notation of the BIN 16-bit data
designated by S into ASCII codes, and stores the results into the area starting from the
device designated by D .
b15 b8b7 b0
b15 b0 D ASCII code for the 3rd digit ASCII code for the 4th digit
S D +1 ASCII code for the 1st digit ASCII code for the 2nd digit
D +2 0 Only when
BIN 16-bit data SM701 is OFF

For example, if 02A6H has been designated by S , it will be stored as follows: D

b15 b8 b7 b0
b15 b0 D 32H (2) 30H (0)
S 02A6H D +1 36H (6) 41H (A)
D +2 00H

(2) The BIN data designated by S can be in the range from 0H to FFFFH.

(3) The operation results stored at D are processed as 4-digit hexadecimal values.
For this reason, zeros which are significant digits on the left side of the value are processed
as "0". (No zero suppression is conducted.)

(4) The data to be stored at the device designated by D +2 differs depending on the ON/OFF
status of SM701 (number of characters to output select signal).
When SM701 is OFF......Stores "0"
When SM701 is ON .......Does not change

7-185
 BINHA(P),DBINHA(P)

DBINHA
(1) Converts the individual digit numbers of hexadecimal notation of the BIN 32-bit data
designated by S into ASCII codes, and stores the results into the area starting from the
device designated by D .
b15 b8b7 b0
D ASCII code for the 7th digit ASCII code for the 8th digit
S +1 S D +1 ASCII code for the 5th digit ASCII code for the 6th digit
D +2 ASCII code for the 3rd digit ASCII code for the 4th digit
Upper 16 bits Lower 16 bits
D +3 ASCII code for the 1st digit ASCII code for the 2nd digit
BIN 32-bit data D +4 0 (Only when
SM701 is OFF)

For example, if the value 03AC625EH has been designated by S , it would be stored
following D in the following manner:
b15 b8 b7 b0
D 33H (3) 30H (0)
D +1 43H (C) 41H (A)
S +1 S
D +2 32H (2) 36H (6)
0 3 A C 6 2 5EH
D +3 45H (E) 35H (5)
D +4 00H

(2) The BIN data designated by S can be in the range from 0H to FFFFFFFFH.

(3) The operation results stored at D are processed as 8-digit hexadecimal values.
For this reason, zeros which are significant digits on the left side of the value are processed
as "0". (No zero suppression is conducted.)

(4) The data to be stored at the device designated by D +2 differs depending on the ON/OFF
status of SM701 (number of characters to output select signal).
When SM701 is OFF......Stores "0"
When SM701 is ON .......Does not change

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• The device specified by D exceeds the range of the corresponding device.
(For the Universal model QCPU, LCPU.) (Error code: 4101)

7-186
 BINHA(P),DBINHA(P)

Program Example
1
(1) The following program uses the PR instruction to output the hexadecimal value of the 16-bit
BIN data at W0 in ASCII code to Y40 to Y48.
[Ladder Mode] [List Mode] 2
Step Instruction Device

6
[Operation]
Conducts ASCII output of Y40 to Y48 by using the PR instruction when X0 goes ON.
Because SM701 is OFF, The PR instruction will output ASCII code until 00H is encountered. 6
b15 b8b7 b0
W0 D0 43H (C) 39H (9) PR
9C06 H D1 36H (6) 30H (0) Y40 to Y48 7
BIN value D2 00H Outputs "9C06"

(2) The following program uses the PR instruction to output the hexadecimal value of the 32-bit
BIN data at W10 and W11 to Y40 to Y48.
8
[Ladder Mode] [List Mode]
Step Instruction Device

7.11.2 Conversion from BIN 16-bit or 32-bit data to hexadecimal ASCII (BINHA(P),DBINHA(P))
7.11 Character string processing instructions
[Operation]
Conducts ASCII output of Y40 to Y48 by using the PR instruction when X0 goes ON.
Because SM701 is OFF, The PR instruction will output ASCII code until 00H is encountered.
b15 b8b7 b0
D0 42H (B) 37H (7)
W11 W10 D1 43H (C) 33H (3) PR
7 B 3 C 5 8 1 FH D2 38H (8) 35H (5) Y40 to Y48
D3 46H (F) 31H (1) Outputs "7B3C581F"
D4 00H

7-187
 BCDDA(P),DBCDDA(P)

7.11.3 Conversion from BCD 4-digit and 8-digit to decimal ASCII data
(BCDDA(P),DBCDDA(P))
BCDDA(P),DBCDDA(P)

High
Basic performance Process Redundant Universal LCPU

indicates an instruction symbol of BCDDA/DBCDDA.

Command
BCDDA,DBCDDA S D

Command
BCDDAP,DBCDDAP P S D

S : BCD data to be converted to ASCII (BCD 4 digits/8 digits)

D : Head number of the devices where the conversion result will be stored (character string)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S ––

D –– –– ––

Function
BCDDA
(1) Converts the individual digit numbers of hexadecimal notation of the BCD 4-digit data
designated by S into ASCII codes, and stores the results into the area starting from the
device designated by D .
b15 b8 b7 b0
b15 b12 b11 b8 b7 b4 b3 b0 D ASCII code for hundreds place ASCII code for thousands place

S D +1 ASCII code for units place ASCII code for tens place
D +2 0
Thousands Hundreds Tens Units
place place place place Only when SM701 is OFF

For example, when "9105" is designated for S , the results of the operation are stored into
the area starting from D in the following manner:
b15 b8b7 b0
b15 b12b11 b8 b7 b4b3 b0 D 31H (1) 39H (9)
S 9 1 0 5 D +1 35H (5) 30H (0)
D +2 00H

(2) The BCD data designated by S can be in the range of from 0 to 9999.

(3) The results of calculation stored in the device D . All zeros on the left side of the "Number of
significant digits" are zero-suppressed.
0050
Number of significant digits
20H

7-188
 BCDDA(P),DBCDDA(P)

(4) The data to be stored at the device designated by D +2 differs depending on the ON/OFF
status of SM701 (number of characters to output select signal).
When SM701 is OFF......Stores "0" 1
When SM701 is ON .......Does not change

DBCDDA 2
(1) Converts the individual digit numbers of hexadecimal notation of the BCD 8-digit data
designated by S into ASCII codes, and stores the results into the area starting from the
device designated by D . 3
b15 b8b7 b0
S +1 S D ASCII code for millions place ASCII code for ten-millions place

b31 b28b27 b24b23 b20b19 b16 b15 b12b11 b8 b7 b4 b3 b0 D +1 ASCII code for ten-thousands place ASCII code for hundred-thousands place 4
D +2 ASCII code for hundreds place ASCII code for thousands place

D +3 ASCII code for unit place ASCII code for tens place
Ten Millions Hundred Ten Thou- Hundreds Tens Units
6
millions place thou- thou- sands place place place 0 (Only when
place sands sands place SM701 is OFF)
place place

For example, if the value 01234056 is designated by , the operation result would be
6
S

stored following D in the following manner:

b15 b8b7 b0
D 31H (1) 20H
b31 b28b27 b24b23 b20b19 b16 b15 b12 b11 b8b7 b4 b3 b0 D +1 33H (3) 32H (2) 7
0 1 2 3 4 0 5 6 D +2 30H (0) 34H (4)
D +3 36H (6) 35H (5)
S +1 S
D +4 00H
8
(2) The BCD data designated by S can be in the range of 0 to 99999999.

(3) The results of calculation stored in the device D . All zeros on the left side of the "Number of
significant digits" are zero-suppressed.

7.11.3 Conversion from BCD 4-digit and 8-digit to decimal ASCII data (BCDDA(P),DBCDDA(P))
7.11 Character string processing instructions
00012098
Number of significant digits
20H

(4) The data to be stored at the device designated by D +4 differs depending on the ON/OFF
status of SM701 (number of characters to output select signal).
When SM701 is OFF......Stores "0"
When SM701 is ON .......Does not change

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The data at S during the operation of the BCDDA instruction is outside the range of from
0 to 9999. (Error code: 4100)

• The data at S during the operation of the DBCDDA instruction is outside the range of 0 to
99999999. (Error code: 4100)
• The device specified by D exceeds the range of the corresponding device.
(For the Universal model QCPU, LCPU.) (Error code: 4101)

7-189
 BCDDA(P),DBCDDA(P)

Program Example
(1) The following program uses the PR instruction to convert BCD 4-digit data (the value at W0)
to decimal, and outputs it in ASCII format to Y40 to Y48.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
Conducts ASCII output of Y40 to Y48 by using the PR instruction when X0 goes ON.
Because SM701 is OFF, The PR instruction will output ASCII code until 00H is encountered.
b15 b8b7 b0
W0 D0 32H (2) 31H (1) PR
1 2 9 5 D1 35H (5) 39H (9) Y40 to Y48
BCD value D2 00H Outputs "1295"

(2) The following program uses the PR instruction to convert BCD 8-digit data (the values at
W10 and W11) to decimal, and outputs it in ASCII format to Y40 to 48.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
Conducts ASCII output of Y40 to Y48 by using the PR instruction when X0 goes ON.
Because SM701 is OFF, The PR instruction will output ASCII code until 00H is encountered.
b15 b8b7 b0
D0 35H (5) 33H (3)
W11 W10 D1 37H (7) 34H (4) PR
3 5 4 7 8 3 5 2 D2 33H (3) 38H (8) Y40 to Y48
BCD value D3 32H (2) 35H (5) Outputs "35478352"
D4 00H

7-190
 DABIN(P),DDABIN(P)

7.11.4 Conversion from decimal ASCII to BIN 16-bit and 32-bit data
(DABIN(P),DDABIN(P)) 1
DABIN(P),DDABIN(P)

High
2
Basic performance Process Redundant Universal LCPU

3
indicates an instruction symbol of DABIN/DDABIN.

Command 4
S D
DABIN,DDABIN
Command
DABINP,DDABINP P S D 6

S : ASCII data to be converted to BIN value or head number of the devices where the ASCII data is stored 6
(character string)
D : Head number of the devices where the conversion result will be stored (BIN 16/32 bits)

Setting
Data
Internal Devices
R, ZR
J \
U \G Zn
Constants
$
Other 7
Bit Word Bit Word

S –– –– ––

D –– –– 8

Function

7.11.4 Conversion from decimal ASCII to BIN 16-bit and 32-bit data (DABIN(P),DDABIN(P))
7.11 Character string processing instructions
DABIN
(1) Converts decimal ASCII data stored into the area starting from the device number
designated by S into BIN 16-bit data, and stores it in the device number designated by D .
b15 b8b7 b0
S ASCII code for ten-thousands place Sign data b15 b0
S +1 ASCII code for hundreds place ASCII code for thousands place D
S +2 ASCII code for units place ASCII code for tens place
BIN 16 bits

For example, if the ASCII code " 25108H" is specified for the area starting from S , the
conversion result is stored at D as shown below:
b15 b8b7 b0
S 32H (2) 2DH ( ) b15 b0
S +1 31H (1) 35H (5) D 2 5 1 0 8
S +2 38H (8) 30H (0)

(2) The ASCII data designated by from S to S +2 can be in the range of from 32768 to 32767
(3) The sign "20H" will be stored if the BIN data is positive, and the sign "2DH" will be stored if it
is negative.
(If other than "20H " and "2DH" is set, it will be processed as positive data.)
(4) ASCII code can be set for each position within the range from "30H" to "39H".
(5) If the ASCII code set for individual positions is "20H" or "00H," it will be processed as "30H".

7-191
 DABIN(P),DDABIN(P)

DDABIN
(1) Converts decimal ASCII data stored into the area starting from the device number
designated by S into BIN 32-bit data, and stores it in the device number designated by D .
b15 b8b7 b0
S ASCII code for billions place Sign data
S +1 ASCII code for ten-millions place ASCII code for hundred-millions place D +1 D
b31 b16b15 b0
S +2 ASCII code for hundred-thousands place ASCII code for millions place
Upper 16 bits Lower 16 bits
S +3 ASCII code for thousands place ASCII code for ten-thousands place
S +4 ASCII code for tens place ASCII code for hundreds place BIN 32 bits
S +5 (Ignored) ASCII code for units place

For example, if the ASCII code of 1234543210H is designated for the area starting from
S , the operation result would be stored at D +1 and D in the following manner:
b15 b8b7 b0
S 31H (1) 2DH ( )
S +1 33H (3) 32H (2)
D +1 D
S +2 35H (5) 34H (4)
12 34 5 4 3 2 1 0
S +3 33H (3) 34H (4)
S +4 31H (1) 32H (2)
S +5 30H (0)

(2) The ASCII data designated by S to S +5 can be in the range of from 2147483648 to
2147483647.
Further, data stored at the upper bytes of S +5 will be ignored.
(3) The sign "20H" will be stored if the BIN data is positive, and the sign "2DH" will be stored if it
is negative.
(If other than "20H " and "2DH" is set, it will be processed as positive data.)
(4) ASCII code can be set for each position within the range from "30H" to "39H".
(5) If the ASCII code set for individual positions is "20H" or "00H," it will be processed as "30H".

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The ASCII code designated by S to S +5 for the individual numbers is something other
than "30H" to "39H", "20H", or "00H". (Error code: 4100)

• The ASCII data designated by S to S +5 is outside the ranges shown below:

(Error code: 4100)
When DABIN instruction is used ........ 32768 to 32767
When DDABIN instruction is used...... 2147483648 to 2147483647

• The device specified by S exceeds the range of the corresponding device.

(For the Universal model QCPU, LCPU.) (Error code: 4101)

7-192
 DABIN(P),DDABIN(P)

Program Example 1
(1) The following program converts the decimal, 5-digit ASCII data and sign set at D20 through
D22 to BIN values, and stores the result at D0.
2
[Ladder Mode] [List Mode]
Step Instruction Device
3

[Operation] 4
b15 b8b7 b0
D0
D20 20H (space) 2DH ( )
276
D21 32H (2) 20H (space)
(Regarded as -00276) BIN value
6
D22 36H (6) 37H (7)
- 276

(2) The following program converts the decimal, 10-digit ASCII data and sign set at D20 through 6
D25 to BIN values and stores the result at D10 and D11.
[Ladder Mode] [List Mode]
Step Instruction Device
7

8
[Operation]
b15 b8b7 b0
D20 20H (space) 20H (space)
D21 20H (space) 20H (space)

7.11.4 Conversion from decimal ASCII to BIN 16-bit and 32-bit data (DABIN(P),DDABIN(P))
7.11 Character string processing instructions
D11 D10
D22 39H (9) 33H (3)
3 9 6 8 3 7 0
D23 38H (8) 36H (6)
(Regarded as +0003968370) BIN value
D24 37H (7) 33H (3)
D25 30H (0)
3968370

7-193
 HABIN(P),DHABIN(P)

7.11.5 Conversion from hexadecimal ASCII to BIN 16-bit and 32-bit data
(HABIN(P),DHABIN(P))
HABIN(P),DHABIN(P)

High
Basic performance Process Redundant Universal LCPU

indicates an instruction symbol of HABIN/DHABIN.

Command
HABIN,DHABIN S D

Command
HABINP,DHABINP P S D

S : ASCII data to be converted to BIN value or head number of the devices where the ASCII data is stored
(character string)
D : Head number of the devices where the conversion result will be stored (BIN 16/32 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word $

S –– –– ––

D –– ––

Function
HABIN
(1) Converts hexadecimal ASCII data stored in the area starting from the device number
designated by S into BIN 16-bit data, and stores it in the device number designated by D .
b15 b8b7 b0
b15 b0
S ASCII code for the 3rd digit ASCII code for the 4th digit
D
S +1 ASCII code for the 1st digit ASCII code for the 2nd digit
BIN 16 bits
For example, if the ASCII code of 5A8DH is designated for the area starting from S , the
operation result would be stored at D in the following manner:
b15 b8 b7 b0
b15 b0
S 41H (A) 35H (5)
D 5A8DH
S +1 44H (D) 38H (8)

(2) The ASCII data designated by S to S +1 can be in the range of from 0000H to FFFFH.
(3) The ASCII codes can be in the range of "30H" to "39H" and from "41H" to "46H".

7-194
 HABIN(P),DHABIN(P)

DHABIN
(1) Converts hexadecimal ASCII data stored in the area starting from the device number 1
designated by S into BIN 32-bit data, and stores it in the device number designated by D .

S
b15 b8b7 b0
ASCII code for the 7th digit ASCII code for the 8th digit D +1 D 2
b31 b16 b15 b0
S +1 ASCII code for the 5th digit ASCII code for the 6th digit
Upper 16 bits Lower 16 bits
S +2 ASCII code for the 3rd digit ASCII code for the 4th digit
S +3 ASCII code for the 1st digit ASCII code for the 2nd digit BIN 32 bits 3
For example, if the ASCII code of 5CB807E1H is designated for the area starting from S ,
the operation result would be stored at D +1 and D in the following manner:
b15 b8b7 b0 4
S 43H (C) 35H (5) D +1 D
b31 b16 b15 b0
S +1 38H (8) 42H (B)
5CB8H 07E1H
S +2
S +3
37H
31H
(7)
(1)
30H
45H
(0)
(E)
6
(2) The ASCII data designated by S to S +3 can be in the range of from 00000000H to
FFFFFFFFH. 6
(3) The ASCII codes can be in the range of "30H" to "39H" and from "41H" to "46H".

7
Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
8
• The ASCII codes for the individual numbers designated by S to S +3 are outside the
range of from "30H" to "39H" and from "41H" to "46H". (Error code: 4100)

• The device specified by S exceeds the range of the corresponding device.

7.11.5 Conversion from hexadecimal ASCII to BIN 16-bit and 32-bit data (HABIN(P),DHABIN(P))
7.11 Character string processing instructions
(For the Universal model QCPU, LCPU.) (Error code: 4101)

7-195
 HABIN(P),DHABIN(P)

Program Example
(1) The following program converts the hexadecimal, 4-digit ASCII data set at D20 and D21 to
BIN data, and stores the result at D0.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
b15 b8b7 b0
D0
D20 36H (6) 41H (A)
22977
D21 46H (F) 33H (3)
Regarded as A63FH BIN value
A63F (-22977 in decimal
value)

(2) The following program converts the hexadecimal, 8-digit ASCII data set at D20 to D23 to
BIN values, and stores the result at D10 and D11.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
b15 b8b7 b0
D20 46H (F) 34H (4)
D11 D10
D21 32H (2) 44H (D)
1339 1 97264
D22 37H (7) 38H (8)
Regarded as 4FD28750H BIN value
D23 30H (0) 35H (5) (1339197264 in decimal
4FD28750 value)

7-196
 DABCD(P),DDABCD(P)

7.11.6 Conversion from decimal ASCII to BCD 4-digit or 8-digit data

(DABCD(P),DDABCD(P)) 1
DABCD(P),DDABCD(P)

High
2
Basic performance Process Redundant Universal LCPU

3
indicates an instruction symbol of DABCD/DDABCD.

Command 4
DABCD,DDABCD S D

Command
DABCDP,DDABCDP P S D 6

S : ASCII data to be converted to BCD value or head number of the devices where the ASCII data is stored 6
(character string)
D : Head number of the devices where the conversion result will be stored (BCD 4 digits/8 digits)

Setting Internal Devices

R, ZR
J \
U \G Zn
Constants
Other
7
Data Bit Word Bit Word $

S –– –– ––

D –– –– 8

Function

7.11.6 Conversion from decimal ASCII to BCD 4-digit or 8-digit data (DABCD(P),DDABCD(P))
7.11 Character string processing instructions
DABCD
(1) Converts decimal ASCII data stored in the area starting from device number designated by
S into 4-digit BCD data, and stores at device number designated by D .

b15 b8b7 b0
S ASCII code for hundreds place ASCII code for thousands place
b15 b12b11 b8b7 b4b3 b0
D
S +1 ASCII code for units place ASCII code for tens place
Thousands Hundreds Tens Units
place place place place

For example, if the ASCII code of 8765H is designated for the area starting from S , the
operation results would be stored at D in the following manner:
b15 b8b7 b0
b15 b12 b11 b8 b7 b4 b3 b0
S 37H (7) 38H (8)
D 8 7 6 5
S +1 35H (5) 36H (6)

(2) The ASCII data designated by S to S +1 can be in the range of from 0 to 9999.
(3) The ASCII code set at each digit can be in the range of from "30H" to "39H".
(4) If ASCII code for individual digits is "20H" or "00H", it is processed as "30H".

7-197
 DABCD(P),DDABCD(P)

DDABCD

(1) Converts decimal ASCII data stored in the area starting from the device designated by S to
8-digit BCD data, and stores it into the area starting from the device designated by D .

b15 b8b7 b0
S ASCII code for millions place ASCII code for ten-millions place D +1 D
S +1 ASCII code for ten-thousands place ASCII code for hundred-thousands place b31 b28b27 b24 b23 b20b19 b16 b15 b12b11 b8b7 b4 b3 b0
S +2 ASCII code for hundreds place ASCII code for thousands place
S +3 ASCII code for units place ASCII code for tens place
Ten Milli- Hundred Ten Thou- Hund- Tens Units
milli- ons thou- thou- sands reds place place
ons place sands sands place place
place place place

For example, if the ASCII code of 87654321H is designated for the area starting from S , the
operation results would be stored at D +1 and D in the following manner:
b15 b8 b7 b0
S 37H (7) 38H (8)
S +1 35H (5) 36H (6) b31 b28b27 b24b23 b20b19 b16 b15 b12 b11 b8 b7 b4 b3 b0
S +2 33H (3) 34H (4) 8 7 6 5 4 3 2 1
S +3 31H (1) 32H (2)
D +1 D

(2) The ASCII data designated at S to S +3 can be in the range of from 0 to 99999999.
(3) The ASCII code set at each digit can be in the range of from "30H" to "39H".
(4) If ASCII code for individual digits is from "20H" to "00H", it is processed as "30H".

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• There are characters within the data at S that are outside the 0 to 9 range.
(Error code: 4100)

• The device specified by S exceeds the range of the corresponding device.

(For the Universal model QCPU, LCPU.) (Error code: 4101)

7-198
 DABCD(P),DDABCD(P)

Program Example
1
(1) The following program converts the decimal ASCII data set from D20 to D22 to BCD
4-digit data, and outputs the results to Y40 to Y4F.
[Ladder Mode] 2
Outputs the converted
BCD value to a display device.
3

[List Mode] 4
Step Instruction Device

6
[Operation]
b15 b8 b7 b0
Y4F Y40
D20
D21
34H (4)
34H (4)
20H (space)
39H (9)
0 4 9 4 6
Regarded BCD value
494 as 0494

(2) The following program converts the decimal ASCII data set at D20 to D23 into 8-digit BCD 7
data, stores the result at D10 and D11, and also outputs it to from Y40 to Y5F.
[Ladder Mode]
8
Outputs the converted
BCD value to a display device.

7.11.6 Conversion from decimal ASCII to BCD 4-digit or 8-digit data (DABCD(P),DDABCD(P))
7.11 Character string processing instructions
[List Mode]
Step Instruction Device

[Operation]
b15 b8 b7 b0
D20 34H (4) 20H (space)
D11 D10 DMOV Y5F Y50 Y4F Y40
D21 37H (7) 39H (9)
0 4 9 7 2 9 4 9 0 4 9 7 2 9 4 9
D22 39H (9) 32H (2)
Regarded BCD value BCD value
D23 39H (9) 34H (4) as 04972949
4972949

7-199
 COMRD(P)

7.11.7 Reading device comment data (COMRD(P))

COMRD(P)

High
Basic performance Process Redundant Universal LCPU

Command
COMRD COMRD S D

Command
COMRDP COMRDP S D

S : Head number of the devices where a comment to be read is stored (Device name)
D : Head number of the devices where the read comment will be stored (character string)

Internal Devices J \ Other

Setting BL\S,BL
R, ZR U \G Zn Constants
Data Bit Word Bit Word \TR,BL,
P,I,J,U

S ––

D –– –– –– ––

Function
(1) Reads the comment at the device number designated by S , and stores it as ASCII code
in the area starting from the device number designated by D .
b15 b8b7 b0
D ASCII code for the 2nd character ASCII code for the 1st character
D +1 ASCII code for the 4th character ASCII code for the 3rd character
Comment at device number designated by S D +2 ASCII code for the 6th character ASCII code for the 5th character
D +3 ASCII code for the 8th character ASCII code for the 7th character Stores up to 32
characters
ASCII code for the 30th character ASCII code for the 29th character
D +15 ASCII code for the 32nd character ASCII code for the 31st character
00H

For example, if the comment for the device designated by S were "NO. 1 LINE
START," the operation results would be stored following D as follows:
b15 b8b7 b0
D 4FH (O) 4EH (N)
D +1 31H (1) 2EH (.)
Comment at S D +2 4CH (L) 20 H (space)
NO.1 LINE START D +3 4EH (N) 49H (I)
D +4 20H (space) 45H (E)
D +5 54H (T) 53H (S)
D +6 52H (R) 41H (A)
D +7 20 H (space) 54H (T)

D +15 20H (space) 20H (space)

00H

7-200
 COMRD(P)

(2) If no comment has been registered for the device specified by S despite the fact that the
comment range setting is made, all of the characters for the comment are processed as
"20H" (space).
1
(3) The device number plus 1 where the final character of D is stored differs depending on the
ON/OFF status of SM701 (number of characters to output select signal). 2
When SM701 is OFF : Does not change
When SM701 is ON : Stores "0"

(4) When a comment is read, SM720 turns ON for one scan after the instruction is completed. 3
SM721 turns ON during the execution of the instruction.
While SM721 is ON, the COMRD(P) instruction cannot be executed. If the attempt is made,
no processing is performed. 4

1. The device comment used in the COMRD(P) instruction uses a comment file 6
stored in a memory card and the standard ROM.
Comment files stored in the program memory cannot be used.
2. Set the comment file used for the COMRD(P) instruction in "PLC file setting" in 6
the PLC parameter dialog box. If the comment file to be used is not set in the
PLC file setting, device comments cannot be output with the COMRD(P)
instruction. 7
3. The COMRD(P) instruction cannot be executed during the interrupt program.
No operation if executed.
8
Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and

7.11.7 Reading device comment data (COMRD(P))

7.11 Character string processing instructions
an error code is stored into SD0.
• The comment is not registered to the device number specified by S . (Error code: 4100)

• The device number specified by D is not a word device. (Error code: 4101)

• The device specified by D exceeds the range of the corresponding device.

(For the Universal model QCPU, LCPU.) (Error code: 4101)

7-201
 COMRD(P)

Program Example
(1) The following program stores the comments set at D100 into the area starting from W0 as
ASCII when X1C is turned ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
b15 b8 b7 b0
W0 49H (I) 4CH (L)
W1 45H (E) 4EH (N)
Comment at D100 W2 41H (A) 20H (space)
LINE A TARGET W3 54H (T) 20H (space)
W4 52H (R) 41H (A)
W5 45H (E) 47H (G)
W6 20H (space) 54H (T)
W7 20H (space) 20H (space)

W15 20H (space) 20H (space)

W16 00H

Caution
(1) The processing completes after several scans.
(2) The COMRD(P)/PRC instruction is not executed if the start signal (execution command) of
the COMRD(P)/PRC instruction is turned ON before completion of the instruction (while
SM721 is ON). Execute the COMRD(P)/PRC instruction when SM721 is OFF.
(3) Two or more file comments cannot be accessed simultaneously.
(4) The following instructions cannot be executed simultaneously because they use SM721 in
common.
Instruction ON During ON for One Scan After
ON after Abnormal Completion
Name Execution Completion
SP. FREAD
Designated by instruction. (Device designated by instruction) + 1
SP. FWRITE
SM721
PRC
SM720 None
COMRD

7-202
 LEN(P)

7.11.8 Character string length detection (LEN(P))

LEN(P)
1
High
2
Basic performance Process Redundant Universal LCPU

3
Command
LEN LEN S D

Command 4
LENP LENP S D

S : Character string or head number of the devices where the character string is stored (character string)
6
D : Number of the device where the length of detected character string will be stored (BIN 16 bits)

Setting
Data
Internal Devices
Bit Word
R, ZR
Bit
J \
Word
U \G Zn
Constants
$
Other 6
S –– –– ––

D –– ––
7

Function 8
(1) Detects length of character string designated by S and stores in the area starting from the
device number designated by D .

7.11.8 Character string length detection (LEN(P))

7.11 Character string processing instructions
Processes the data from the device number designated by S to the device number storing
"00H" as a character string.
b15 b8b7 b0
S 2nd character 1st character
S 4th character 3rd character
b15 b0
S 6th character 5th character
D Length of character string

S 00H nth character

Indicates the end of character string

For example, when the value "ABCDEFGHI" is stored in the area starting from S , the value
9 is stored at D .
b15 b8b7 b0
S 42H (B) 41H (A)
S +1 44H (D) 43H (C) b15 b0
"ABCDEFGHI"
S +2 46H (F) 45H (E) D 9
S +3 48H (H) 47H (G)
S +4 00H 49H (I)

7-203
 LEN(P)

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• There is no "00H" set within the relevant device range following the device number
designated by S . (Error code: 4101)

Program Example
(1) The following program outputs the length of the character string from D0 to Y40 to Y4F as
BCD 4-digit values.
[Ladder Mode]

Outputs the length of character

string to a display device.

[List Mode]
Step Instruction Device

[Operation]
b15 b8b7 b0
D0 49 H (I) 4DH (M)
D10 BCD conversion Y4F Y40
D1 53 H (S) 54 H (T)
10 0 0 1 0
D2 42 H (B) 55 H (U) BCD
"MITSUBISHI" BCD value
D3 53 H (S) 49 H (I)
(Characters "ABC"
D4 49 H (I) 48 H (H) that follow 00H are ignored)
D5 41 H (A) 00 H
D6 42 H (C) 43 H (B)

7-204
 STR(P),DSTR(P)

7.11.9 Conversion from BIN 16-bit or 32-bit to character string

(STR(P),DSTR(P)) 1
STR(P),DSTR(P)

Ver.
High
2
Basic performance Process Redundant Universal LCPU

Basic model QCPU: The upper five digits of the serial No. are "04122" or larger.
3

indicates an instruction symbol of STR/DSTR.

Command 4
STR,DSTR S1 S2 D

6
Command
STRP,DSTRP P S1 S2 D

S1 : Head number of the devices where the digits numbers for the numerical value to be converted are stored
(BIN 16 bits)
6
S2 : BIN data to be converted (BIN 16/32 bits)
D : Head number of the devices where the converted character string will be stored (character string)

Setting Internal Devices J \ Constants

7
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S1 –– ––

S2 ––
8
D –– –– –– ––

7.11.9 Conversion from BIN 16-bit or 32-bit to character string (STR(P),DSTR(P))

7.11 Character string processing instructions
Function
STR
(1) Adds a decimal point to the BIN 16-bit data designated by S2 at the location designated by
S1 , converts the data to character string data, and stores it in the area starting from the

device number designated by D .

b15 b8b7 b0
S1 Total number of digits ASCII code for the
(total number of digits -1) ASCII code for the sign
S1 Number of digits in decimal fraction D th digit
ASCII code for the ASCII code for the
(total number of digits -3) (total number of digits -2)
D th digit th digit
. ASCII code for the ASCII code for the
D (total number of digits -5) (total number of digits -4) Designated total
th digit th digit number of digits
Sign
ASCII code for the ASCII code for the
D (total number of digits -7) (total number of digits -6)
th digit th digit
S2 BIN data
D 00H

Automatically stored at
the end of the character string

S1 5
S1 +1 1
b15 b8 b7 b0
D 31 H (1) 2D ( )
1 2 . 3 D +1 2EH (.) 32H (2)
D +2 00H 33H (3)

S2 123

7-205
 STR(P),DSTR(P)

(2) The total number of digits that can be designated by S1 is from 2 to 8.

(3) The number of digits that can be designated by S1 +1 as a part of the decimal fraction is from
0 to 5.
However, the number of digits following the decimal point must be smaller than or equal to
the total number of digits minus 3.

(4) BIN data in the range between 32768 and 32767 can be designated at S2 .

(5) After conversion, character string data is stored at the device number D or later device
number as indicated below:
(a) The sign "20H" (space) will be stored if the BIN data is positive, and the sign "2DH"
(minus sign) will be stored if it is negative.

(b) If the setting for the number of digits after the decimal fraction is anything other than "0",
"2EH" (.) will automatically be stored at the position before the first of the specified
number of digits.
Total number of digits 6
Number of digits 2
in decimal fraction 1 2. 34
BIN data 1 2 3 4 Number of digits in decimal fraction
Automatically added
If the number of digits in the decimal fraction part of the number is "0", the ASCII code
"2EH" (.) will not be stored.

(c) If the total number of digits following the decimal fraction is greater than the number of
BIN data digits, a zero will be added automatically and the number converted by shifting
to the right, so that it would become "0. ".
Total number of digits 6
Number of digits
in decimal fraction 3 0 . 012
BIN data 1 2
Automatically added

(d) If the total number of digits excluding the sign and the decimal point is greater than the
number of BIN data digits, "20H" (space) will be stored between the sign and the
numeric value.
Total number of digits 8
Number of digits 1
in decimal fraction 12 . 3
BIN data 1 2 3 Filled with 20H (space)

If the number of BIN digits is greater, an error will be returned.

(e) The value "00H" is automatically stored at the end of the converted character string.

7-206
 STR(P),DSTR(P)

DSTR

(1) Adds a decimal point to the BIN 32-bit data designated by S2 at the location designated by 1
S1 , converts the data to character string data, and stores it following the device number
designated by .
D
2
S1 Total number of digits
S1 +1 Number of digits in decimal fraction b15 b8 b7 b0
ASCII code for the

3
D (total number of digits -1) ASCII code for the sign
th digit
ASCII code for the ASCII code for the
. D +1 (total number of digits -3) (total number of digits -2)
th digit th digit
ASCII code for the ASCII code for the

S2 +1 S2
Sign D +2 (total number of digits -5)
th digit
ASCII code for the
(total number of digits -4)
th digit
ASCII code for the
Designated total
number of digits
4
b31 b16 b15 b0 (total number of digits -7) (total number of digits -6)
D +3
Upper 16 bits Lower 16 bits th digit th digit
ASCII code for the ASCII code for the
BIN 32 bits D +4 (total number of digits -9)
th digit
(total number of digits -8)
th digit 6
ASCII code for the
D +5 00H (total number of digits -10)
th digit

Automatically stored at the 6

S1 8 end of the character string
S1 +1 3
b15 b8 b7 b0
D
D +1
36H
34H
(6)
(4)
2DH ( )
35H (5) 7
6 5 4 . 3 2 1 D +2 33H (3) 2EH (.)
D +3 31H (1) 32H (2)
S2 +1
8
S2 +4 00H
D
BIN data 6 5 4 3 2 1

(2) The total number of digits that can be designated by S1 is from 2 to 13.

(3) The number of digits that can be designated by S1 +1 as a part of the decimal fraction is from

7.11.9 Conversion from BIN 16-bit or 32-bit to character string (STR(P),DSTR(P))

7.11 Character string processing instructions
0 to 10.
However, the number of digits following the decimal point must be smaller than or equal to
the total number of digits minus 3.

(4) The BIN data that can be designated by S1 and S2 +1 is within the range of from
2147483648 to 2147483647.

(5) After conversion, character string data is stored at the device number following D as
indicated below:
(a) The sign "20H" (space) will be stored if the BIN data is positive, and the sign "2DH"
(minus sign) will be stored if it is negative.

(b) If the setting for the number of digits after the decimal fraction is anything other than "0",
"2EH" (.) will automatically be stored at the position before the first of the specified
number of digits.
Total number of digits 10
Number of digits 3
in decimal fraction 12345 . 678
BIN data 12 3 4 5 6 7 8
Number of digits in decimal fraction
Automatically added

If the number of digits in the decimal fraction part of the number is "0", the ASCII code
"2EH" (.) will not be stored.

7-207
 STR(P),DSTR(P)

(c) If the total number of digits following the decimal fraction is greater than the number of
BIN data digits, a zero will be added automatically and the number converted by shifting
to the right, so that it would become "0. ".
Total number of digits 13
Number of digits 10
in decimal fraction 0 . 0000054321
BIN data 5 4 3 2 1
Automatically added

(d) If the total number of digits excluding the sign and the decimal point is greater than the
number of BIN data digits, "20H" (space) will be stored between the sign and the
numeric value.

Total number of digits 13

Number of digits 2
in decimal fraction 5432 . 10
BIN data 5 4 3 2 1 0 Filled with 20H (space) codes

If the number of BIN digits is greater, an error will be returned.

(e) The value "00H" is automatically stored at the end of the converted character string.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The total number of digits designated by is outside the ranges shown below.
S1

(Error code: 4100)

When the STR instruction is in use .......2 to 8
When the DSTR instruction is in use.....2 to 13

• The number of digits designated as a part of the decimal fraction by S1 +1 is outside the
range shown below. (Error code: 4100)
When the STR instruction is in use .......0 to 5
When the DSTR instruction is in use.....0 to 10

• The relationship between the total number of digits designated by S1 and the number of
digits in the decimal fraction designated by +1 is not as shown below:
S1

(Error code: 4100)

Total number of digits minus 3 is equal to or larger than the number of digits in the decimal
fraction.

• The number of digits designated by S1 is smaller than "2 + number of digits of the BIN
data, designated by S2 ".
(Number of digits of S1 < Number of digits of the BIN data at S2 without a sign + Number
of digits of a sign (+ or -) + Number of digits of decimal point (.)) (Error code: 4100)

• The device range where the character string designated by D will be stored exceeds the
relevant device range. (Error code: 4101)

7-208
 STR(P),DSTR(P)

Program Example
1
(1) The following program converts the BIN 16-bit data stored at D10 when X0 is turned ON in
accordance with the digit designation of D0 and D1, and stores the result from D20 to D23.
[Ladder Mode] 2
Sets the data.

Sets the total number of digits.

3
Sets the number of digits in decimal fraction.

6
[List Mode]

Step Instruction Device

6

7
[Operation]

D10 12672 D20

b15
31H (1)
b8b7
20H (space)
b0
8
D21 36H (6) 32H (2)
D0 7 1267.2
D22 2E H (.) 37H (7)
D1 1 D23 00H 32H (2)

7.11.9 Conversion from BIN 16-bit or 32-bit to character string (STR(P),DSTR(P))

7.11 Character string processing instructions

7-209
 STR(P),DSTR(P)

(2) The following program converts the BIN 32-bit data stored at D10 and D11 when X0 is
turned ON in accordance with the digit designation of D0 and D1, and stores the result at
from D20 to D26.
[Ladder Mode]

Sets the data.

Sets the total number of digits.

Sets the number of digits in decimal fraction.

[List Mode]
Step Instruction Device

[Operation]
D11 D10 b15 b8b7 b0
D10 12345678 D20 30 H (0) 20 H (space)
D21 30 H (0) 2EH (.)
D0 12 0.012345678
D22 32 H (2) 31 H (1)
D1 9 D23 34 H (4) 33 H (3)
D24 36 H (6) 35 H (5)
D25 38 H (8) 37 H (7)
D26 00 H

7-210
 VAL(P),DVAL(P)

7.11.10 Conversion from character string to BIN 16-bit or 32-bit

data (VAL(P),DVAL(P)) 1
VAL(P),DVAL(P)

Ver.
High
2
Basic performance Process Redundant Universal LCPU

Basic model QCPU: The upper five digits of the serial No. are "04122" or larger
(Correspording GX Seveloper :Version 8.00 A or later). 3

indicates an instruction symbol of VAL/DVAL. 4

Command
VAL,DVAL S D1 D2

Command 6
VALP,DVALP P S D1 D2

6
S : Character string to be converted to BIN data or head number of the devices where the character string is
stored (character string)
D1 : Head number of the devices where the number of digits of the converted BIN data will be stored (BIN 16 bits)
7
D2 : Head number of the devices where the converted BIN data will be stored (BIN 16/32 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word $
8
S –– –– ––

D1 –– –– ––

D2 –– ––

7.11.10 Conversion from character string to BIN 16-bit or 32-bit data (VAL(P),DVAL(P))
7.11 Character string processing instructions
Function
VAL
(1) Converts character strings stored in the device numbers starting from that designated at S

to BIN 16-bit data, and stores the number of digits and BIN data in D1 and D2 .
For conversions from character strings to BIN, all data from the device number designated
by S to the device number where "00H" is stored will be processed as character strings.
Total number
D1 of digits
b15 b8b7 b0
S ASCII code for the 1st character ASCII code for the sign D1 +1 Number of digits
in decimal fraction
S +1 ASCII code for the 3rd character ASCII code for the 2nd character Integer value
S +2 ASCII code for the 5th character ASCII code for the 4th character . D2 ignoring decimal
point
S +3 ASCII code for the 7th character ASCII code for the 6th character
Sign 1st 2nd 7th
S +4 00H char- char- char- BIN 16 bits
acter acter acter
Indicates the end of character string

7-211
 VAL(P),DVAL(P)

For example, if the character string " 123.45" is designated for the area starting from S ,
the operation result would be stored at D1 and D2 in the following manner:
D1 7
b15 b8 b7 b0 D1 +1 2
S 31H (1) 2DH ( )
S +1 33H (3) 32 H (2)
1 2 3 . 4 5 D2 12345
S +2 34H (4) 2EH (.)
S +3 00H 35 H (5)

(2) The total number of characters that can be designated as a character string at S is from 2
to 8.

(3) From 0 to 5 characters from the character string designated at S can become the decimal
fraction part.
However, this number must not exceed the total number of digits minus 3.
(4) The range of the numerical character string that can be converted to BIN value is from
32768 to 32767, ignoring a decimal point.
Numerical value character strings, excluding the sign and the decimal point, can be
designated only within the range from "30H" to "39H".
The value ignoring a decimal point means:
Example : " 12345.6" " 123456"
(5) The sign "20H" will be stored if the numerical value is positive, and the sign "2DH" will be
stored if it is negative.
(6) "2EH" is set for the decimal point.

(7) The total number of digits stored at D1 amounts to all characters expressing numerical
values (including signs and decimal points).
The characters following the decimal point stored at D1 +1 include the number of characters
from "2EH" (.) onward.
The BIN data stored at D2 is the character string ignoring the decimal point that has been
converted to BIN data.

(8) In cases where the character string designated by S contains "20H" (space) or "30H" (0)
between the sign and the first numerical value other than "0", these "20H" and "30H" are
ignored in the conversion into a BIN value.
Total number of digits 8 Total number of digits 7
Number of digits 2 Number of digits 4
123 . 45 in decimal fraction 0 . 0012 in decimal fraction
BIN data 12345 BIN data 12
Ignored Sign Ignored

7-212
 VAL(P),DVAL(P)

DVAL

(1) Converts the character string stored in the area starting from the device designated by to
1
S

BIN 32-bit data, and stores the digits numbers and BIN data in D1 and D2 .
For conversions from character strings to BIN, all data from the device number designated
by S to the device number where "00H" is stored will be processed as character strings. 2
b15 b8 b7 b0 D1 Total number of digits
S ASCII code for the 1st character ASCII code for the sign D1 +1 Number of digits
in decimal fraction
S ASCII code for the 3rd character ASCII code for the 2nd character
3
+1
S +2 ASCII code for the 5th character ASCII code for the 4th character D2 +1 D2
S +3 ASCII code for the 7th character ASCII code for the 6th character . Integer value ignoring decimal point
S +4 ASCII code for the 9th character ASCII code for the 8th character
Sign 1st 2nd 12th BIN 32 bits
S
S
+5
+6
ASCII code for the 11th character ASCII code for the 10th character
00H ASCII code for the 12th character
char- char-
acter acter
char-
acter
4
Indicates the end of character string

b15 b8 b7 b0 D1 10 6
S 31H (1) 2D H ( ) D1 +1 3
S +1 33H (3) 32H (2)
S
S
+2
+3
35H (5)
36H (6)
34H (4)
2EH (.) 1 2 3 4 5 . 6 7 8 12 34 5 678 6
S +4 38H (8) 37H (7) D2 +1 D2
S +5 00H

7
(2) The total number of characters in the character string indicated by S is from 2 to 13.

(3) From 0 to 10 characters in the character string indicated by S can be the decimal fraction
8
part.
However, this number must not exceed the total number of digits minus 3.
(4) The range of the numerical character string that can be converted to BIN value is from

7.11.10 Conversion from character string to BIN 16-bit or 32-bit data (VAL(P),DVAL(P))
7.11 Character string processing instructions
2147483648 to 2147483647, excluding the decimal point.
Numerical value character strings, excluding the sign and the decimal point, can be
designated only within the range from "30H" to "39H".
(5) The sign "20H" will be stored if the numerical value is positive, and the sign "2DH" will be
stored if it is negative.
(6) "2EH" is set for the decimal point.
(7) The total number of digits stored at D1 amounts to all characters expressing numerical
values (including signs and decimal points).
The characters following the decimal point stored at D1 +1 include the number of characters
from "2EH" (.) onward.
The BIN data stored at D2 is the character string ignoring the decimal point that has been
converted to BIN data.

7-213
 VAL(P),DVAL(P)

(8) In cases where the character string designated by S contains "20H" (space) or "30H" (0)
between the sign and the first numerical value other than "0", these "20H" and "30H" are
ignored in the conversion into a BIN value.
Total number of digits 12
Number of digits 2
6543 . 21 in decimal fraction
BIN data 6 5 4 3 2 1
Ignored

Total number of digits 11

Number of digits 8
0 . 00054321 in decimal fraction
BIN data 5 4 3 2 1
Sign Ignored

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The number of characters in the character string designated by S1 falls outside the ranges
shown below: (Error code: 4100)
When VAL instruction is in use ........... From 2 to 8 characters
When DVAL instruction is in use ........ From 2 to 13 characters
• The number of characters in the decimal fraction portion of the character string
designated by S falls outside the ranges shown below: (Error code: 4100)
When VAL instruction is in use ........... 0 to 5
When DVAL instruction is in use ........ 0 to 10

• The total number of characters in the character string designated by S and the number of
characters in the decimal fraction part stand in a relationship that is outside the range
indicated below: (Error code: 4100)
Total number of characters minus 3 is equal to or greater than the number of characters in
the decimal fraction part.
• An ASCII code other than "20H" or "2DH" has been set for the sign.
(Error code: 4100)
• An ASCII code other than from "30H" to "39H" or "2EH" (decimal point) has been set as a
digit for one of the individual numbers. (Error code: 4100)
• There has been more than one decimal point set in the value. (Error code: 4100)

• The value of the BIN value when converted falls outside the following ranges:
(Error code: 4100)
When VAL instruction is in use ........... 32768 to 32767
When DVAL instruction is in use ........ 2147483648 to 2147483647

• No "00H" is set within the range from the device number designated by S to the last
device number of the relevant device. (Error code: 4101)

7-214
 VAL(P),DVAL(P)

Program Example
1
(1) The following program reads the character string data stored from D20 to D22 as an integer,
converts it to a BIN value, and stores it at D0 when X0 is ON.
[Ladder Mode] [List Mode] 2
Step Instruction Device

3
[Operation]
b15 b8b7 b0
4
D20 31H (1) 2DH ( ) D0 1654
D21 2E H (.) 36H (6)
D22
D23
34H (4)
00H
35H (5) D10
D11
6
2
Total number of digits
Number of digits in decimal fraction
6
Set 00H

(2) The following program reads the character string data stored from D20 to D24 as an integer, 6
converts it to a BIN value, and stores it at D0 when X0 is ON.
[Ladder Mode] [List Mode]
Step Instruction Device
7

8
[Operation]
b15 b8 b7 b0 D1 D0
D20 37H (7) 20 H (space) 7 9 1 0 0 6 1 1

7.11.10 Conversion from character string to BIN 16-bit or 32-bit data (VAL(P),DVAL(P))
7.11 Character string processing instructions
D21 31H (1) 39H (9)
D22 30H (0) 30H (0) D10 10 Total number of digits
D23 36H (6) 2EH (.) D11 3 Number of digits in decimal fraction
D24 31H (1) 31H (1)
D25 00H

Set 00H

7-215
 ESTR(P)

7.11.11 Conversion from floating decimal point to character string

data (ESTR(P))
ESTR(P)

Ver.
High
Basic performance Process Redundant Universal LCPU

Basic model QCPU: The upper five digits of the serial No. are "04122" or larger.

Command
ESTR ESTR S S2 D

Command
ESTRP ESTRP S1 S2 D

S1 : 32-bit floating decimal point data to be converted or head number of the devices where the data is stored
(real number)
S2 : Head number of the devices where display designation for the numerical value to be converted is stored (BIN 16 bits)
D : Head number of the devices where the converted character string will be stored (character string)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word E

S1 –– –– *1 ––

S2 –– –– –– –– –– ––

D –– –– –– –– –– ––

*1:Available only in multiple Universal model QCPU and LCPU

Function
(1) Converts the 32-bit floating decimal point data designated by S1 to a character string
according to the display designation specified by S2 , and stores the result into the area
starting from the device number designated by D .

(2) The post-conversion data differs depending on the display designation designated by S2 .

0: Decimal point format The converted data differs depending

S2 on the format selected at S2 .
1: Exponent format
S2 +1 Total number of digits Setting is possible in the range from 2 to 24.
S2 +2 Number of digits in decimal fraction

7-216
 ESTR(P)

When using decimal point format

b15 b8 b7 b0 1
S2 Decimal point format ASCII code for the
S2 +1 Total number of digits D (total number of digits -1) ASCII code for the sign
th digit
2
S2 +2 Number of digits in decimal fraction
ASCII code for the ASCII code for the
D +1 (total number of digits -3) (total number of digits -2)
th digit th digit
. ASCII code for the ASCII code for

Sign
D +2 (total number of digits -5) decimal point (.)
th digit (2E H) 3
ASCII code for the ASCII code for the
S1+1 S1 D +3 (total number of digits -7) (total number of digits -6)
th digit th digit
D +4 00 H 4
32-bit floating-point real number Automatically stored at the
end of character sting

7.11.11 Conversion from floating decimal point to character string data (ESTR(P))
7.11 Character string processing instructions

7-217
 ESTR(P)

For example, in a case where there are 8 digits in total, with 3 digits in the decimal fraction
part, and the value designated is 1.23456, the operation result would be stored in the area
starting from D in the following manner:
S2 0
S2 +1 8
S2 +2 b15 b8 b7 b0
3
D 20H (space) 2DH(-)
D +1 31H (1) 20H (space)
- 1 . 2 3 5 D +2 32H (2) 2EH (.)
D +3 35H (5) 33H (3)
Sign D +4 00H

S1 +1 S1 Automatically stored at the end of character sting

-1. 2 3 4 5 6

32-bit floating-point real number

(a) The total number of digits that can be designated by S2 +1 is as shown below:
When the number of decimal fraction digits is "0"
.................... Number of digits (max.: 24) 2
When the number of decimal fraction digits is other than "0"
.................... Number of digits (max.: 24) (Number of decimal fraction digits + 3)

(b) The number of digits of decimal fraction part that can be designated by S2 +2 is from 0 to
7.
However, the number of digits following the decimal point must be smaller than or equal
to the total number of digits minus 3.

(c) The converted character string data is stored at the area starting from the device
number D as indicated below:
1) The sign "20H" (space) will be stored if the 32-bit floating decimal point type real
number is positive, and the sign "2DH" (minus sign) will be stored if it is negative.
2) If the decimal fraction part of a 32-bit floating point real number data is out of the
range of the digits of decimal fraction part, the lower decimal values will be rounded
off.

S2 0: Decimal point format

S2 +1 8 (Total number of digits) Total number of digits
S2 +2 2 (Number of digits in decimal fraction)
- 1 . 2 3 4 5 6
S1 +1 S1 Number of digits in Rounded off
-1. 2 3 4 5 6 decimal fraction

3) If the number of digits following the decimal point has been set at any value other
than "0", "2EH" (.) will automatically be stored at the position before the first of the
specified number of digits.

S2 0: Decimal point format

S2 +1 8 (Total number of digits) Total number of digits
S2 +2 2 (Number of digits in decimal fraction)
- 1 . 2 3
S1 +1 S1 Number of digits
-1 . 2 3 4 5 6 in decimal fraction
Automatically added
If the number of digits in the decimal fraction part is "0", the ASCII code "2EH" (.) will
not be stored.

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 ESTR(P)

4) If the total number of digits, excluding the sign, the decimal point and the decimal
fraction part, is greater than the integer part of the 32-bit floating point type real
number data, "20H (space)" will be stored between the sign and the integer part. 1
S2 0
S2 +1 8
2
Total number of digits
S2 +2 2
- 1 . 2 3
S1+1 S1 Number of digits
-1 . 2 3 4 5 6 in decimal fraction
3
Filled with 20H
(space) codes
5) The value "00H" is automatically stored at the end of the converted character string.
4

When using exponent format

6
b15 b8b7 b0
S2 Exponent format ASCII code for the
S2 +1
S2 +2
Total number of digits
Number of digits in decimal fraction
D (total number of digits -1)th digit ASCII code for the sign
ASCII code for decimal point (.) ASCII code for the
6
D +1 (2EH) (total number of digits -2)th digit
ASCII code for the ASCII code for the
D +2 (total number of digits -5)th digit (total number of digits -4)th digit
. E
ASCII code for the ASCII code for the
7
Sign (integer part) Sign (exponent part) D +3 (total number of digits -7)th digit (total number of digits -6)th digit

S1 +1 S1 ASCII code for the sign

D +4 (Exponent part) 45H (E)
Automatically added
ASCII code for the ASCII code for the
D +5 (total number of digits -11)th digit (total number of digits -10)th digit
8
32-bit floating-point real number
D +6 00H

Automatically stored at
the end of character sting

7.11.11 Conversion from floating decimal point to character string data (ESTR(P))
7.11 Character string processing instructions
For example, in a case where there are 12 digits is total, with 4 digits in the decimal fraction
portion, and the value designated is 12.34567, the operation results would be stored in the
area starting from D in the following manner:
S2 1
S2 +1 12
b15 b8 b7 b0
S2 +2 4
D 20H (space) 2DH (-)
D +1 2EH (.) 31H (1)
D +2 33H (3) 32H (2)
- 1 . 2 3 4 6 E+ 0 1
D +3 36H (6) 34H (4)
Sign Sign D +4 2CH(+) 45H (E)
(integer part) (exponent part) D +5 31H (1) 30H (0)
D +6 00H
S1 +1 S1
-1 2 . 34 5 6 7 Automatically added

32-bit floating-point real number

7-219
 ESTR(P)

(a) The total number of digits that can be designated by S2 +1 is as shown below:
When the number of decimal fraction digits is "0"
.................... Number of digits (max.: 24) 2
When the number of decimal fraction digits is other than "0"
.................... Number of digits (max.: 24) (Number of decimal fraction digits + 7)

(b) The number of digits of dicimal fraction part that can be designated by S2 +2 is from 0 to
7.
However, the number of digits in the decimal fraction portion should be equal to or less
than the total number of digits minus 7.

(c) The converted character string data is stored at the area starting from the device
number D as indicated below:
1) If the 32-bit floating decimal point type real number data is positive in value, the sign
before the integer will be stored as ASCII code "20H" (space), and if it is a negative
value, the sign will be stored as "2DH" ( ).
2) The integer portion is fixed to one digit.
20H (space) will be stored between the integer and the sign.
1 Total number of digits (12)
S2
S2 +1 12 Fixed to 1 digit
S2 +2 4
- 1 . 2 3 4 6 E+ 0 1
S1+1 S1
-1 2. 3 4567
Filled with 20H (space) codes

3) If the decimal fraction part of the 32-bit floating point type real number is out of the
range of the digits of the decimal fraction part, the lower decimal values will be
rounded off.
S2 1
S2 +1 12 Total number of digits (12)
S2 +2 4
- 1 . 2 3 4 6 6 7 E+ 0 1
S1+1 S1
Number of digits These are cut
-1 2. 3 4 5 6 7 in decimal fraction (4)

4) If the number of digits of the decimal fraction part has been set at any value other
than "0", "2EH" (.) will automatically be stored at the position before the first of the
specified number of digits.
S2 1
S2 +1 12 Total number of digits (12)
S2 +2 4
- 1 . 2 3 4 6 E+ 0 1
S1 +1 S1 Number of digits
-1 2. 3 4 5 6 7 in decimal fraction (4)
Automatically added

If the number of digits in the decimal fraction part of the number is "0", the ASCII
code "2EH" (.) will not be stored.

7-220
 ESTR(P)

5) The ASCII code "2CH" (+) will be stored as the sign for the exponent portion of the
value if the exponent is positive in value, and the code "2DH" ( ) will be stored if the
exponent is a negative value. 1
6) The exponent portion is fixed at 2 digits.
If the exponent portion is only 1 digit, the ASCII code "30H" (0) will be stored 2
between the sign and the exponent portion of the number.
Total number of digits (12)
S2
S2 +1
1
12 Fixed to 2 digits
3
S2 +2 4
- 1 . 2 3 4 6 E+ 0 1
S1 +1
-1 2 . 3 4567
S1
4
Filled with
30H (0) code

7) The value "00H" is automatically stored at the end of the converted character string. 6

Operation Error 6
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0. 7
• The S1 value is not within the range indicated below: (Error code: 4100)
-126 128
0, 2 | | 2
S1
8
• The format designated by S2 was neither 0 nor 1. (Error code: 4100)

• The total number of digits designated by S2 + 1 is outside the ranges shown below.
(Error code: 4100)
When using decimal point format

7.11.11 Conversion from floating decimal point to character string data (ESTR(P))
7.11 Character string processing instructions
When the number of decimal fraction digits is "0"
....................... Total number of digits 2
When the number of decimal fraction digits is other than "0"
....................... Total number of digits (Number of decimal fraction digits + 3)
When using exponent format
When the number of decimal fraction digits is "0"
....................... Total number of digits 6
When the number of decimal fraction digits is other than "0"
....................... Total number of digits (Number of decimal fraction digits + 7)

• The number of digits designated for the decimal fraction portion of the value by S2 +2 was
outside the ranges indicated below: (Error code: 4100)
When using the decimal point format
....................... Number of decimal fraction digits (Total number of digits 3)
When using the exponent format
....................... Number of decimal fraction digits (Total number of digits 7)
• The value whose total digits exceeds "24" is specified. (Error code: 4100)

• The device range to store the character string designated by D exceeds the relevant
device range. (Error code: 4101)

• The device specified by S2 exceeds the range of the corresponding device.

(For the Universal model QCPU, LCPU.) (Error code: 4101)
• The value of the specified device is 0, unnormalized number, nonnumeric, and ± .
(For the Universal model QCPU, LCPU) (Error code: 4140)

7-221
 ESTR(P)

Program Example

(1) The following program converts the 32-bit floating point type real number data which had
been stored at R0 and R1 in accordance with the conversion designation that is being stored
at R10 to R12, and stores the result following D0 when X0 goes ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
R10 0 Conversion format b15 b8 b7 b0
R11 7 D0 20H (space) 20H (space)
Total number of digits Total number of digits
R12 D1 2EH (.) 30H (0)
3 Number of digits
in decimal fraction 0 . 0 3 3 D2 33H (3) 30H (0)
00H 33H (3)
R1 R0 Space Number of digits
0 . 0327 457 in decimal fraction Automatically stored

(2) The following program converts the 32-bit floating decimal point type real number data which
had been stored at D0 and D1 in accordance with the conversion designation that is being
stored at R10 to R12, and stores the result following D10 when X1C goes ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
R10 1 (exponent format) Conversion format
R11 12 Total number of digits Total number of digits
R12 4 Number of digits
in decimal fraction 3 . 2 7 4 6 E- 0 2

D1 D0 Space Number of digits

0 . 0 327 4578 in decimal fraction
b15 b8 b7 b0
D10 20H (space) 20H (space)
D11 2EH (.) 33H (3)
D12 37H (7) 32H (2)
D13 36H (6) 34H (4)
D14 2DH(-) 45H (E)
D15 32H (2) 30H (0)
D16 00H

Automatically stored

7-222
 EVAL(P)

7.11.12 Conversion from character string to floating decimal point

data (EVAL(P)) 1
EVAL(P)

Ver.
High
2
Basic performance Process Redundant Universal LCPU

Basic model QCPU: The upper five digits of the serial No. are "04122" or larger.
3
Command
EVAL EVAL S D 4
Command
EVALP EVALP S D
6
S : Character string data to be converted to 32-bit floating decimal point real number data or head number of the
devices where the character string data is stored (character string)
6
D : Head number of the devices where the converted 32-bit floating decimal point real number data will be stored
(real number)

Setting
Data
Internal Devices
Bit Word
R, ZR
Bit
J \
Word
U \G Zn
Constants
$
Other 7
S –– –– –– –– ––

D –– –– *1 –– –– ––
8
*1: Available on Universal model QCPU and LCPU

Function

7.11.12 Conversion from character string to floating decimal point data (EVAL(P))
7.11 Character string processing instructions
(1) Converts character string stored in the area starting from the device number designated by
S to 32-bit floating point type real number, and stores result at device designated by D .
(2) The designated character string can be converted to 32-bit floating point type real number
data either in the decimal point format or the exponent format.
b15 b8 b7 b0
S ASCII code for the 1st character ASCII code for the sign
S +1 ASCII code for the 3rd character ASCII code for the 2nd character D +1 D
S +2 ASCII code for the 5th character ASCII code for the 4th character
S +3 ASCII code for the 7th character ASCII code for the 6th character
32-bit floating-point
S +4 00H real number

Indicates the end

of character string

(a) When using decimal point format

b15 b8b7 b0
S 31H (1) 2DH(-)
S +1 30H (0) 2EH (.) D +1 D
S +2 38H (8) 37H (7) -1 . 0 7 8 12
S +3 32H (2) 31H (1)
S +4 32-bit floating-point
00H real number

- 1 . 0 7 8 1 2

7-223
 EVAL(P)

(b) When using exponent format

b15 b8b7 b0
S 20H (space) 2DH (-)
S +1 2EH (.) 31H (1)
S +2 32H (2) 33H (3) D +1 D
S +3 31H (1) 30H (0) -1. 320 1E + 10
S +4 2BH (+) 45H (E)
S +5 32-bit floating-point
30H (0) 31H (1) real number
S +6 00H

1 1 . 3 2 0 1 E+ 1 0

(3) Excluding the sign, decimal point, and exponent portion of the result, 6 digits of the character
string designated by S to be converted to a 32-bit floating decimal point type real number
will be effective; the 7th digit on later digit will be cut from the result.
(a) When using decimal point format
b15 b8b7 b0
S 20H (space) 2DH (-)
S +1 31H (1) 20H (space)
S +2 33H (3) 2EH (.) D +1 D
S +3 31H (1) 30H (0) -1. 3 0 1 5 6
S +4 36H (6) 35H (5)
S +5 32-bit floating-point real number
31H (1) 38H (8)
S +6 00H 32H (2)

- 1 . 3 0 1 5 6 8 1 2

These are cut

(b) When using exponent format

b15 b8b7 b0
S 20H (space) 2DH (-)
S +1 2EH (.) 31H (1)
S +2 35H (5) 33H (3) D +1 D
S +3 33H (3) 30H (0) -1 . 350 34 E- 2
S +4 31H (1) 34H (4)
S +5 45H (E) 32H (2) 32-bit floating-point
real number
S +6 30H (0) 2DH (-)
S +7 00H 32H (2)

- 1 . 3 5 0 3 4 1 2 E- 0 2

These are cut

(4) In the decimal point format, if "2BH" (+) is specified for the sign or if the designation of sign is
omitted, conversion is made assuming a positive value.
If "2DH" (-) is specified for the sign, the character string is converted assuming a negative
value.
(5) In the exponent format, if "2BH" (+) is specified for the sign in the exponent portion or if the
designation of sign is omitted, conversion is made assuming a positive value.
If "2DH" (-) is specified for the sign in the exponent portion, the character string is converted
assuming a negative value.

7-224
 EVAL(P)

(6) In a case where the ASCII code "20H (space)" or "30H" (0) exists between numbers not
including the initial zero in a character string specified by S , it will be ignored when the
conversion is done. 1
b15 b8b7 b0
S 20H (space) 2DH (-)
S +1 31H (1) 30H (0) D +1 D 2
S +2 32H (2) 2EH (.) -1 . 2 3 1
S +3 31H (1) 33H (3)
32-bit floating-point
3
S +4 00 real number

- 0 1 . 2 3 1

Ignored
4
(7) In a case where the ASCII code "30H (0) " exists between the character "E" and a number in
an exponent format character string, the "30H" would be ignored when the conversion is
performed. 6
b15 b8b7 b0
20H (space) 2DH (-)
2EH (.)
34H (4)
31H (1)
30H (0) D +1 D 6
33H (3) 35H (5) -1 . 0 4 5 3 E + 3
2BH (+) 45H (E)
33H (3)
00H
30H (0)
7
- 1 . 0 4 5 3 E+ 0 3
8
Ignored

(8) If the "20H" (space) code is contained in the character string, the code is ignored in the
conversion.

7.11.12 Conversion from character string to floating decimal point data (EVAL(P))
7.11 Character string processing instructions
(9) Up to 24 characters can be set for a character string.
The codes "20H" (space) and "30H" (0) contained in the character string are also counted as
a character.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The integer portion or the decimal fraction portion contains a character other than one in
the range of from "30H" (0) to "39H" (9). (Error code: 4100)
• There are two or more occurrences of the character "2EH" (.) in the character string
designated by D . (Error code: 4100)
• The exponent portion contains the code (character) other than "45H"(E), "2BH"(+),
"45H"(E) or "2DH"( ), or the string contains more than one exponent portion.
(Error code: 4100)
• Data after conversion is not within the following range. (Error code: 4100)
-126 128
0, 2 |data after conversion| 2

• The code "00H" does not appear in the range from S to the relevant device.
(Error code: 4101)

• The number of characters in the character string following S is either 0 or more than 24.
(Error code: 4100)

7-225
 EVAL(P)

Program Example
(1) The following program converts the character string stored in the area starting from R0 to a
32-bit floating decimal point type real number, and stores the result at D0 and D1 when X20
is turned ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
b15 b8b7 b0
R0 20H (space) 2DH (-)
R1 31H (1) 30H (0)
D1 D0
R2 32H (2) 2EH (.)
-1 . 234 5 2
R3 34H (4) 33H (3)
R4 32H (2) 35H (5)
R5 00H 31H (1)

- 0 1 . 2 3 4 5 2 1

Ignored These are cut

(2) The following program converts the character string stored in the area starting from D10 to a
32-bit floating decimal point type real number, and stores the result at D100 and D101 when
X20 is turned ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
b15 b8b7 b0
D10 20H (space) 20H (space)
D11 2EH (.) 31H (1)
D12 33H (3) 32H (2) D101 D100
D13 35H (5) 34H (4) 1 . 2 3 4 5 E -2
D14 2DH (-) 45H (E)
D15 32H (2) 30H (0)
D16 00

1 . 2 3 4 5 E - 0 2

Ignored Ignored

7-226
 ASC(P)

7.11.13 Conversion from hexadecimal BIN to ASCII (ASC(P))

ASC(P)
1
High
2
Basic performance Process Redundant Universal LCPU

Command
3
ASC ASC S D n

ASCP
Command
ASCP S D n
4

S : Head number of the devices where BIN data to be converted to a character string is stored (BIN 16 bits) 6
D : Head number of the devices where the converted character string will be stored (character string)
n : Number of characters to be stored (BIN 16 bits)

Setting Internal Devices

R, ZR
J \
Zn
Constants
Other
6
U \G
Data Bit Word Bit Word K, H

S –– –– ––

D –– –– –– 7
n ––

8
Function
(1) Converts the BIN 16-bit data stored in the area starting from the device designated by S to
ASCII by treating the BIN data in hexadecimal representation. Then, stores the converted

7.11.13 Conversion from hexadecimal BIN to ASCII (ASC(P))

7.11 Character string processing instructions
data into the area starting from the device designated by D , for the number of characters
specified by n.
b15 b12b11 b8b7 b4b3 b0 b15 b8b7 b0
S 4th digit 3rd digit 2nd digit 1st digit D ASCII code for the 2nd digit ASCII code for the 1st digit
S +1 4th digit 3rd digit 2nd digit 1st digit D +1 ASCII code for the 4th digit ASCII code for the 3rd digit
D +2 ASCII code for the 2nd digit ASCII code for the 1st digit Number of
D +3 ASCII code for the 4th digit ASCII code for the 3rd digit characters
4th digit 3rd digit 2nd digit 1st digit designated by n

BIN data ASCII code for the 2nd digit ASCII code for the 1st digit

b15 b12b11 b8b7 b4b3 b0 b15 b8b7 b0

S 1H 2H 3H 4H D 33H (3) 34H (4)
S +1 5H 6H 7H 8H D +1 31H (1) 32H (2)
S +2 FH EH DH CH D +2 37H (7) 38H (8)
S +3 AH 9H BH 6H D +3 35H (5) 36H (6) When "15" is
D +4 44H (D) 43H (C) set for n
D +5 46H (F) 45H (E)
D +6 42H (B) 36H (6)
D +7 00H 39H (9)

7-227
 ASC(P)

(2) The use of n to set the number of characters causes the BIN data range designated by S

and the character string storage device range designated by D to be set automatically.
(3) Processing will be performed accurately even if the device range where BIN data to be
converted is being stored overlaps with the device range where the converted ASCII data
will be stored.
b15 b12 b11 b8 b7 b4b3 b0 b15 b8b7 b0
D11 4H 3H 2H 1H D10 32H 31H
D12 8H 7H 6H 5H D11 34H 33H
D13 AH 9H D12 36H 35H
D13 38H 37H
D14 41H 39H

(4) If an odd number of characters has been designated by n, the ASCII code "00H" will be
automatically stored in the upper 8 bits of the final device in the range where the character
string is to be stored.
When 5 characters have been designated by n.
b15 b12b11 b8b7 b4b3 b0 b15 b8b7 b0
S 1 A 2 B S D 32H(2) 42H(B)
S +1 B S D +1 31H(1) 41H(A)
S D +2 00H 42H(B)

Stored automatically

(5) If the number of characters designated by n is "0", conversion processing will not be
conducted.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The range for the number of characters designated by n following the device number
designated by S exceeds the relevant device range. (Error code: 4101)
• The range for the number of characters designated by n following the device number
designated by D exceeds the relevant device range. (Error code: 4101)

Program Example
(1) The following program reads the BIN data being stored at D0 as hexadecimal values,
converts them to a character string, and stores the result from D10 to D14 when X0 is turned
ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
b15 b12b11 b8 b7 b4b3 b0 b15 b8b7 b0
D0 CH 7H 2H 9H D10 32H (2) 39H (9)
D1 0H 5H AH FH D11 43H (C) 37H (7)
D2 0H 0H 2H 2H D12 41H (A) 46H (F)
D13 30H (0) 35H (5)
D14 32H (2) 32H (2)

7-228
 HEX(P)

7.11.14 Conversion from ASCII to hexadecimal BIN (HEX(P))

HEX(P)
1
High
2
Basic performance Process Redundant Universal LCPU

3
Command
HEX HEX S D n

Command 4
HEXP HEXP S D n

S : Head number of the devices where a character string to be converted to BIN data is stored (character string)
6
D : Head number of the devices where the converted BIN data will be stored (BIN 16 bits)
n : Number of characters to be stored (BIN 16 bits)

Setting Internal Devices J \ Constants

6
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S –– –– ––

D –– –– ––
7
n ––

8
Function
(1) Converts the number of characters of hexadecimal ASCII data designated by n stored in the

7.11.14 Conversion from ASCII to hexadecimal BIN (HEX(P))

7.11 Character string processing instructions
area starting from the device number designated by S into BIN values and stores them in
the area starting from the device number designated by D .
b15 b8b7 b0 b15 b12b11 b8b7 b4b3 b0
S ASCII code for the 2nd digit ASCII code for the 1th digit D 4th digit 3rd digit 2nd digit 1st digit
S +1 ASCII code for the 4nd digit ASCII code for the 3th digit D +1 4th digit 3rd digit 2nd digit 1st digit
Number of S +2 ASCII code for the 2st digit ASCII code for the 1rd digit
characters
designated S +3 ASCII code for the 4st digit ASCII code for the 3rd digit
by n

BIN data

For example, if the number 9 has been designated by n, the operation would be as follows:

b15 b8b7 b0
S 33H (3) 34H (4)
When "9" S +1 31H (1) 32H (2) b15 b12b11 b8b7 b4b3 b0
is set S +2 42H (B) 36H (6) D 1H 2H 3H 4H
for n
S +3 41H (A) 39H (9) D +1 AH 9H BH 6H
S +4 38H (8) 45H (E) D +2 0H 0H 0H EH

Code "38H" remains unchanged since the designated number of characters is "9".

(2) When the number of characters is specified for n, the range of characters designated by S

as well as the device range designated by D in which the BIN data will be stored are
automatically decided.

7-229
 HEX(P)

(3) Accurate processing will be conducted even in cases where the range of devices where the
ASCII code to be converted is being stored overlaps with the range of devices that will store
the converted BIN data.
b15 b8b7 b0 b15 b12 b11 b8 b7 b4b3 b0
D10 32H (2) 31H (1) D11 4H 3H 2H 1H
D11 34H (4) 33H (3) D12 8H 7H 6H 5H
D12 36H (6) 35H (5) D13 0H 0H AH 9H
D13 38H (8) 37H (7)
D14 41H (A) 39H (9)

(4) If the number of characters designated by n is not divisible by 4, "0" will be automatically
stored after the designated number of characters in the final device number of the devices
which are storing the converted BIN values.
b15 b8b7 b0 b15 b12 b11 b8b7 b4b3 b0
S 32H (2) 42H (B) D 1 A 2 B
S +1 31H (1) 41H (A) D +1 0 0 0 8
S +2 43H (C) 38H (8)
Value "0" is automatically stored in
the area outside the range of the
designated number of characters.

(5) If the number of characters designated by n is "0", conversion processing will not be
conducted.

(6) ASCII code that can be designated by S includes from "30H" to "39H" and from "41H" to "46H".

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• Characters outside the hexadecimal character string (that is, characters that are not in the
range of from "30H" to "39H", or from "41H" to "46H") have been set by S .
(Error code: 4100)
• The range for the number of characters designated by n following the device number
designated by S exceeds the relevant device range. (Error code: 4101)
• The range for the number of characters designated by n following the device number
designated by D exceeds the relevant device range. (Error code: 4101)
• The number of characters designated by n is a negative value. (Error code: 4101)

Program Example
(1) The following program converts the character string being stored from D0 to D4 to BIN data
and stores the result from D10 to D14 when X0 goes ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
b15 b8b7 b0 b15 b12b11 b8 b7 b4b3 b0
D0 42H (B) 36H (6) 2H 5H BH 6H
D1 32H (2) 35H (5) 3H 1H 7H AH
D2 37H (7) 41H (A) 0H 0H 9H 7H
D3 33H (3) 31H (1)
D4 39H (9) 37H (7)

7-230
 RIGHT(P),LEFT(P)

7.11.15 Extracting character string data from the right or left

(RIGHT(P),LEFT(P)) 1
RIGHT(P),LEFT(P)

High
2
Basic performance Process Redundant Universal LCPU

3
indicates an instruction symbol of RIGHT/LEFT.

Command 4
RIGHT,LEFT S D n

Command
RIGHTP,LEFTP P S D n 6

S : Character string or head number of the devices where the character string is stored (character string) 6
D : Head number of the devices where the character string consisting of n characters starting from the right or
left of S will be stored (character string)
n : Number of characters to be extracted (BIN 16 bits)
7
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H $

S –– –– –– ––
8
D –– –– –– –– ––

n –– ––

7.11.15 Extracting character string data from the right or left (RIGHT(P),LEFT(P))
7.11 Character string processing instructions
Function
RIGHT
(1) Stores n number of characters from the right side of the character string (the end of the
character string) being stored in devices starting from that whose number is designated by
S , in devices starting from that whose number is designated by D .

b15 b8b7 b0
S b15 b8b7 b0
ASCII code for the 2nd character ASCII code for the 1st character
D ASCII code for the (last - n + 2)th character ASCII code for the (last - n + 1)th character
S +1 ASCII code for the 4th character ASCII code for the 3rd character
D +1 ASCII code for the (last - n + 4)th character ASCII code for the (last - n + 3)th character

ASCII code for the (last - n + 2)th character ASCII code for the (last - n + 1)th character
ASCII code for the (last - 1)th character ASCII code for the (last - 2)th character
ASCII code for the (last - n + 4)th character ASCII code for the (last - n + 3)th character
00H ASCII code for the last character

ASCII code for the (last - 1)th character ASCII code for the (last - 2)th character
00H ASCII code for the last character

When n 5
b15 b8b7 b0
b15 b8b7 b0
S 42 H (B) 41H (A)
D 32 H (2) 31 H (1)
S +1 44 H (D) 43H (C)
D +1 34 H (4) 33 H (3)
S +2 46 H (F) 45H (E)
D +2 00 H 35 H (5)
S +3 32 H (2) 31H (1)
S +4 "12345"
34 H (4) 33H (3)
S +5 00H 35H (5) ASCII code for the 5th character

"ABCDEF12345"

7-231
 RIGHT(P),LEFT(P)

(2) The NULL code (00H) indicating the end of the character string is automatically appended at
the end of the character string. Refer to 3.2.5 for the format of the character string data.

(3) If the number of characters designated by n is "0", the NULL code (00H) will be stored at D .

LEFT
(1) Stores n number of characters from the left side of the character string (the beginning of the
character string) being stored in devices starting from that whose number is designated by
S , in devices starting from that whose number designated by D .
b15 b8b7 b0
b15 b8b7 b0
S ASCII code for the 2nd character ASCII code for the 1st character
D ASCII code for the 2nd character ASCII code for the 1st character
S +1 ASCII code for the 4th character ASCII code for the 3rd character
D +1 ASCII code for the 4th character ASCII code for the 3rd character

ASCII code for the (n - 1)th character ASCII code for the (n - 2)th character
ASCII code for the (n - 1)th character ASCII code for the (n - 2)th character
ASCII code for the (n + 1)th character ASCII code for the nth character
00H ASCII code for the nth character

00H ASCII code for the last character

When n 7
b15 b8b7 b0
b15 b8b7 b0
S 42 H (B) 41H (A)
D 42 H (B) 41H (A)
S +1 44 H (D) 43H (C)
D +1 44 H (D) 43H (C)
S +2 46 H (F) 45H (E)
D +2 46 H (F) 45H (E)
S +3 32 H (2) 31H (1)
D +3 00 H 31H (1)
S +4 34 H (4) 33H (3)
ASCII code for the "ABCDEF1"
S +5 00 H 35H (5) 7th character
"ABCDEF12345"

(2) The NULL code (00H) indicating the end of the character string is automatically added to the
end of the character string.
Refer to 3.2.5 for the format of the character string data.

(3) If the number of characters designated by n is "0", the NULL code (00H) will be stored at D .

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The value of n exceeds the number of characters designated by S . (Error code: 4101)

• The range of n characters from D exceeds the relevant device. (Error code: 4101)

7-232
 RIGHT(P),LEFT(P)

Program Example
1
(1) The following program stores 4 characters of data from the rightmost of the character string
stored in the area starting from R0, and stores it into the area starting from D0 when X0 is
turned ON. 2
[Ladder Mode] [List Mode]
Step Instruction Device
3

[Operation]
4
b15 b8b7 b0
b15 b8b7 b0
R0
R1
41H (A)
31H (1)
42H (B)
32H (2)
D0 45H (E) 30H (0) 6
D1 41H (A) 46H (F)
R2 45H (E) 30H (0)
D2 00H
R3 41H (A) 46H (F)
"0EFA"
R4 00H
ASCII code for the 4th character
6
"BA210EFA"

(2) The following program stores the number of characters corresponding to the value being
stored in D0 from the left of the character string data being stored at D100 to the area 7
starting from R10 when X1C is turned ON.
[Ladder Mode] [List Mode]
Step Instruction Device 8

[Operation]

7.11.15 Extracting character string data from the right or left (RIGHT(P),LEFT(P))
7.11 Character string processing instructions
b15 b8b7 b0
b15 b8b7 b0
D100 51 H (Q) 53H (S)
R10 51 H (Q) 53H (S)
D101 4EH (N) 4FH (O)
R11 4EH (N) 4FH (O)
D102 44 H (D) 48H (H)
R12 44 H (D) 48H (H)
D103 42 H (B) 41H (A)
R13 00H
D104 00H
"SQONHD"
"SQONHDAB"
D0 6
ASCII code for the 6th character

7-233
 MIDR(P),MIDW(P)

7.11.16 Random selection from and replacement in character strings

(MIDR(P),MIDW(P))
MIDR(P),MIDW(P)

High
Basic performance Process Redundant Universal LCPU

indicates an instruction symbol MIDR/MIDW.

Command
MIDR,MIDW S1 D S2

Command
MIDRP,MIDWP P S1 D S2

S1 : Character string or head number of the devices where the character string is stored (character string)
D : Head number of the devices where a character string data obtained as the result of operation will be stored
(character string)
S2 : Head number of the devices where the location of the first character and the number of characters will be
stored (BIN 16 bits)

• S2 : Position of first character

• S2 +1: Number of characters

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word $

S1 –– –– ––

D –– –– –– ––

S2 –– ––

Function
MIDR

(1) Extracts the character string data of S2 +1 characters, starting from the position designated
by S2 , counted from the left end of the character string data designated by S1 , and stores
the extracted data into the area starting from the device designated by D .
b15 b8b7 b0
b15 b8b7 b0
S1 42 H (B) 41H (A)
D 46 H (F) 45 H (E)
S1 +1 44 H (D) 43H (C)
D +1 48 H (H) 47 H (G)
S1+2 46 H (F) 45H (E)
Position of the 5th D +2 00 H 49 H (I)
S1+3 48 H (H) 47H (G)
S1+4 character S2 "EFGHI"
4AH (J) 49H (I)
S1+5 00 H 4BH (K) ASCII code for the 5th character S2 +1
"ABCDEFGHIJK"
S2 5
S2 +1 5

7-234
 MIDR(P),MIDW(P)

(2) The NULL code (00H) indicating the end of the character string is automatically added to the
end of the character string.
Refer to 3.2.5 for the format of the character string data.
1
(3) No processing will be conducted if the number of characters designated by S2 +1 is "0".

(4) If the number of characters designated by S2 +1 is " 1", stores the data up to the final
2
character designated by S starting from the device designated by D .
b15 b8b7 b0
b15 b8b7 b0
3
S1 42 H (B) 41 H (A)
D 46H (F) 45 H (E)
S1 +1 44 H (D) 43 H (C)
D +1 48H (H) 47 H (G)
S1 +2 46 H (F) 45 H (E)
S1 +3 48 H (H) 47 H (G) Position of
the 5th
D +2
D +3
4AH (J)
00 H
49 H (I)
4B H (K)
4
S1 +4 4A H (J) 49 H (I) character S2
S1 +5 00 H 4B H (K) "EFGHIJK"

"ABCDEFGHIJK" 6
S2 5
S2 +1 1

MIDW 6
(1) Extracts the character string data of S2 +1 characters, starting from the left end of the
character string data designated by S1 , and stores the extracted data to the character string 7
data designated by D in the area starting from the position designated by S2 from the left
end.
Before execution 8
b15 b8b7 b0
b15 b8b7 b0 D 42H (B) 41 H (A)
S1 31H (1) 30H (0) D +1 44H (D) 43 H (C)
S1 +1 33H (3) 32H (2) D +2 46H (H) 45 H (E)

7.11.16 Random selection from and replacement in character strings (MIDR(P),MIDW(P))

7.11 Character string processing instructions
S1 +2 35H (5) 34H (4) D +3 48H (H) 47 H (G)
S1 +3 37H (7) 36H (6) D +4 00H 49 H (I)
S1 +4 00H 38H (8) "ABCDEFGHI"
After execution
"012345678"
b15 b8b7 b0
3 Position counted from the left D
S2 end of character string data 42H (B) 41H (A)
S2 +1 6 designated by D D +1 31H (1) 30H (0)
Number of characters counted D +2 33H (3) 32H (2)
from the left end of the character
string data designated by S1 D +3 35H (5) 34H (4)
D +4 00H 49H (I)
"AB012345I"

(2) The NULL code (00H) indicating the end of the character string is automatically added to the
end of the character string.
Refer to 3.2.5 for the format of the character string data.

(3) No processing will be conducted if the number of characters designated by S2 +1 is "0".

7-235
 MIDR(P),MIDW(P)

(4) If the number of characters designated by S2 +1 exceeds the final character from the
character string data designated by D , data will be stored up to the final character.
Before execution
b15 b8b7 b0
b15 b8b7 b0 D 42H (B) 41H (A)
S1 31H (1) 30H (0) D +1 44H (D) 43H (C)
S1 +1 33H (3) 32H (2) D +2 46H (F) 45H (E)
S1 +2 35H (5) 34H (4) D +3 48H (H) 47H (G)
S1 +3 37H (7) 36H (6) D +4 00H 49H (I)
S1 +4 00H 38H (8) "ABCDEFGHI"
"012345678" After execution
b15 b8b7 b0
Position counted from the left
S2 5 end of character string data D 42H (B) 41H (A)
S2 +1 8 designated by D D +1 44H (D) 43H (C)
Number of characters counted D +2
from the left end of character 31H (1) 30H (0)
string data designated by S1 D +3 33H (3) 32H (2)
D +4 00H 34H (4)
"ABCD01234"
Characters "35H" (5) to "37H" (7)
are not stored.

(5) If the number of characters designated by S2 +1 is " 1", stores the data up to the final
character designated by S1 to the area starting from the device designated by D .
Before execution
b15 b8b7 b0
b15 b8b7 b0 D 42H (B) 41H (A)
S1 31H (1) 30 H (0) D +1 44H (D) 43H (C)
S1 +1 33H (3) 32 H (2) D +2 46H (F) 45H (E)
S1 +2 35H (5) 34 H (4) D +3 48H (H) 47H (G)
S1 +3 00 H D +4 4AH (J) 49H (I)
"012345" D +5 00H 4B H (K)
"ABCDEFGHIJK"
Position counted from the left After execution
S2 2 end of character string data b15 b8b7 b0
S2 +1 1 designated by D
D 30H (0) 41H (A)
Number of characters counted
from the left end of character D +1 32H (2) 31H (1)
string data designated by S1 D +2 34H (4) 33H (3)
D +3 48H (H) 35H (5)
D +4 4AH (J) 49H (I)
D +5 00H 4B H (K)
"A012345HIJK"

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
For MIDR instruction

• The value of S2 exceeds the number of characters designated by S1 . (Error code: 4101)

• The S2 +1 number of characters from position D exceeds the D device range.

(Error code: 4101)

• The S2 + 0 value is 0. (Error code: 4101)

• "00H" does not exist in the specified devices that follow the device specified for S1 .
(Error code: 4101)

For MIDW instruction

• The value of S2 exceeds the number of characters designated by D . (Error code: 4101)

7-236
 MIDR(P),MIDW(P)

• The S2 +1 value exceeds the number of characters for S1 . (Error code: 4101)

• The S2 + 0 value is 0. (Error code: 4101)

1
• "00H" does not exist in the specified devices that follow the device specified for S1 .
(Error code: 4101)
2
Program Example
3
(1) The following program stores the 3rd character through the 6th character from the left of the
character string stored in the area starting from D10 at devices starting from D0 when X0 is
turned ON. 4
[Ladder Mode] [List Mode]
Step Instruction Device
6

6
[Operation]
b15 b8b7 b0 b15 b8b7 b0
D10 41 H (A) 42 H (B) D0 31 H (1) 32 H (2) 7
D11 31 H (1) 32 H (2) D1 46 H (E) 33 H (3)
D12 46 H (E) 33 H (3) D2 00 H
D13 00 H 45 H (D) "213E"
"BA213ED" 8
R0 3
R1 4

(2) The following program stores 4 characters of the character string data stored in the area

7.11.16 Random selection from and replacement in character strings (MIDR(P),MIDW(P))

7.11 Character string processing instructions
starting from D0 into the area starting from the 3rd character from the left of the character
string data in the area starting from D100 when X0 is turned ON.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
Before execution
b15 b8b7 b0 b15 b8b7 b0
D0 31H (3) 32H (2) D100 53H (S) 55H (U)
D1 45H (E) 46H (F) D101 59H (Y) 43H (C)
D2 33H (3) 30H (0) D102 31H (1) 5AH (Z)
D3 00H D103 42H (B) 30H (0)
"21FE03" D104 00H
"USCYZ10B"
R0 3
After execution
R1 4 b15 b8b7 b0
D100 53H (S) 55H (U)
D101 31H (1) 32H (2)
D102 45H (E) 46H (F)
D103 42H (B) 30H (0)
D104 00H
"US21FE0B"

7-237
 INSTR(P)

7.11.17 Character string search (INSTR(P))

INSTR(P)

High
Basic performance Process Redundant Universal LCPU

Command
INSTR INSTR S1 S2 D n

Command
INSTRP INSTRP S1 S2 D n

S1 : Character string to be searched or head number of the devices where the character string to be searched is
stored (character string)
S2 : Character string in which a search is performed or head number of the devices where the character string is
stored (character string)
D : Head number of the devices where the result of search will be stored (BIN 16 bits)

n : Location to start the search (BIN 16 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H $
S1 –– –– –– ––

S2 –– –– –– ––

D –– –– ––

n –– ––

Function
(1) Searches for the character string data designated by S1 in the area starting from the nth
character from the left of the character string data designated by S2 and stores the result of
search at the device designated by D .
As the result of search, the location of match, counted in the number of characters from the
first character of the character string data designated by S2 , is stored.
When n 3
b15 b8b7 b0 b15 b8b7 b0
S2 42H (B) 41 H (A) Searches from the S1 46 H (F) 45 H (E)
S2 +1 44H (D) 43 H (C) 3rd character S1 +1 48 H (H) 47 H (G)
S2 +2 46H (F) 45 H (E) 5th character from S1 +2 00H
S2 +3 48H (H) 47H (G) the first character
"EFGH"
S2 +4 4AH (J) 49 H (I)
S2 +5 00 H 4B H (K)
"ABCDEFGHIJK"
D 5 Stores the position of the
found character, counted
by the number of characters
from the 1st character in
the character string data
designated by S2 .

(2) If there is no matching character string data, stores "0" at D .

7-238
 INSTR(P)

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The value of n exceeds the number of characters for S2 . (Error code: 4100)
2
• 00H (NULL) does not exist within the corresponding device range after the device
designated by S1 , S2 . (Error code: 4100) 3
• The value of n is negative number or “0”. (Error code: 4100)

Program Example 4

(1) The following program searches from the 5th character from the left of the character string
data stored in devices starting from R0 for the character string data in devices starting from 6
D0, and stores the results at D100 when X0 goes ON.
[Ladder Mode] [List Mode]
Step Instruction Device
6

7
[Operation]

b15 b8b7 b0 b15 b8b7 b0

8
Not searched since
R0 49H (I) 43 H (C) the search start D0 49H (I) 43H (C)
R1 33H (3) 32 H (2) position is 5 D1 33H (3) 32H (2)
R2 32H (2) 31 H (1) Searches from D2 00 H
R3 49H (I) 43 H (C) the 5th character
"CI23"
R4 00H 4DH (M)

7.11.17 Character string search (INSTR(P))

7.11 Character string processing instructions
"CI2312CIM"

D100 0
Stores "0" because there are no matches.

(2) The following program searches from the 3rd character from the left of the character string
data being stored in devices starting from D0 for the character string data "AB", and stores
the results of the search at D100 when X1C goes ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
b15 b8b7 b0
D0 32H (2) 31H (1) Searches from the
D1 34H (4) 33H (3) 3rd character "AB" D100 5
D2 42H (B) 41H (A) 5th character from
the first character
D3 36H (6) 35H (5)
D4 42H (B) 41H (A)
D5 00H

7-239
 STRINS(P)

7.11.18 Insertion of character string (STRINS(P))

STRINS(P)

Ver.
High
Basic performance Process Redundant Universal LCPU

QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later.

QnUDE(H)CPU: The serial number (first five digits) is "10102" or later.

Command
STRINS STRINS S D n

Command
STRINSP STRINSP S D n

S : Character string to be inserted or head number (character string) of the devices where insert character
strings are stored
D : Head number (character string) of the devices where insert character strings are stored

n : Insert position (Setting range: 1 n 16383) (BIN 16 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H $

S –– –– –– ––

D –– –– –– –– ––

n –– –– ––

Function
(1) This instruction inserts the character string data specified by S to the nth device (insert
position) from the initial character string data stored in the devices specified by D .
Insert position: n 3
b15 b8b7 b0 Shifts the third character
S 31 H (1) 30 H (0) and up by the number of
b15 b8b7 b0
S ＋1 33 H (3) 32 H (2) characters specified by
S to the left and inserts D 42 H (B) 41H (A)
S ＋2 00 H 34 H (4) D ＋1 ( S )
the character string data 31 H (1) 30H (0)
specified by S . D ＋2 33 H (3) 32H (2) ( S ＋1)
D ＋3 43 H (C) 34H (4) ( S ＋2)
b15 b8b7 b0
D D ＋4 45 H (E) 44H (D)
42 H (B) 41H (A)
D ＋1 D ＋5 47 H (G) 46H (F)
44 H (D) 43H (C) Third character insertion
D ＋2 position D ＋6 00 H 48H (H)
46 H (F) 45H (E)
D ＋3 D ＋7 66 H (f) 65H (e)
48 H (H) 47H (G)
D ＋4 00 H
D ＋5 The character data stored after
62 H (b) 61H (a)
D +4 will be written over in
D ＋6 64 H (d) 63H (c) accordance with the number of
D ＋7 66 H (f) 65H (e) characters to be inserted.

(2) This instruction stores the NULL code (00H) into the device (1 word) that positions after the
last device where the character string data are stored, if the character string ( S + D ) value is
even after the insertion.
(3) This instruction stores the NULL code (00H) into the last device (high 8 bits) where the
character string data are stored, if the character string ( S + D ) value is odd after the
insertion.

(4) This instruction links the device, where the character string data are stored, specified by S

with the last device specified by D , if n is specified by the number of devices specified by D
plus one.

7-240
 STRINS(P)

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an
error code is stored into SD0.
• The number of characters in the devices specified by S , D , or the devices specified by
2
( S + D ) after the insertion exceeds 16383 characters. (Error code: 4100)
• The value specified by n is not within the specified range. (1 n 16383) 3
(Error code: 4100)

• The value specified by n exceeds the number of the devices specified by D plus one.
(Error code: 4100) 4
• The devices, that store character strings, specified by S overlaps with even one of the
devices specified by D . (Error code: 4101) 6
• The range of the devices specified by ( S + D ) in which character strings data have been
inserted exceeds the specified device range. (Error code: 4101)
• The NULL code (00H) does not exist within the specified device range after the device
6
specified by S or D . (Error code: 4101)

• The range of the devices specified by ( S + D ) in which character strings data have been 7
inserted overlaps with the range of the devices specified by S that store the character
string data. (Error code: 4101)
8
Program Example
(1) The following program inserts the character string data stored in the device D0 and up to the
fourth device from the initial character string data stored in D20 and up, when M0 is turned

7.11.18 Insertion of character string (STRINS(P))

7.11 Character string processing instructions
on.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
Befor insertion
D0 38 H (8) 35 H (5) D20 52 H (R) 50H (P)
D1 00 H 34 H (4) D21 47 H (G) 4FH (O)
D22 41 H (A) 52H (R)
D0 character string 584
D23 41 H (A) 4DH (M)
D24 43 H (C) 42H (B)
D25 00 H 44H (D)

D20 character string D20 character string PROGRAMABCD

Inserted between"O"and"G" Fourth character from the
left (Insert position)

After insertion
D20 52 H (R) 50H (P)
D21 35 H (5) 4FH (O)
D22 34 H (4) 38H (8)
D23 52 H (R) 47H (G)
D24 4DH (M) 41H (A)
D25 42 H (B) 41H (A)
D26 44 H (D) 43H (C)
D27 00 H

D20 character string PRO584GRAMABCD

7-241
 STRDEL(P)

7.11.19 Deletion of character string (STRDEL(P))

STRDEL(P)

Ver.
High
Basic performance Process Redundant Universal LCPU

QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later.

QnUDE(H)CPU: The serial number (first five digits) is "10102" or later.

Command
STRDEL STRDEL D n1 n2

Command
STRDELP STRDELP D n1 n2

D : Head number (character string) of the devices where character strings to be deleted are stored

n1 : Deletion start position (Setting range 1 n1 16383) (BIN 16 bits)

n2 : Number of characters to be deleted (Setting range 1 n2 16384-n1) (BIN 16 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

D –– –– –– ––

n1 –– ––

n2 –– ––

Function
(1) This instruction deletes n2 characters data in the devices specified by D starting from the
device (insert position) specified by n1.
Device position where character string data to be deleted: n1 3
Number of characters to be deleted: n2 5
Shifts the n1+n2th characters and up,
which are stored after the devices whose characters Stores the NULL code (00H) into
were deleted, by n2 characters to the right the empty devices after shifting.
b15 b8b7 b0 b15 b8b7 b0 b15 b8b7 b0
D 42 H (B) 41H (A) D 42 H (B) 41H (A) D 42 H (B) 41H (A)
Deletes n2 characters from
D＋1 44 H (D) 43H (C) the n1th device and up D＋1 D＋1 49 H (I) 48H (H)
D＋2 46 H (F) 45H (E) D＋2 D＋2 4BH (K) 4AH (J)
D＋3 48 H (H) 47H (G) D＋3 48 H (H) D＋3 00 H 4CH (L)
D＋4 4AH (J) 49H (I) D＋4 4AH (J) 49H (I) D＋4 00 H
D＋5 4CH (L) 4BH (K) D＋5 4CH (L) 4BH (K) D＋5 00 H
D＋6 00 H D＋6 00 H D＋6 00 H
D＋7 31 H (1) 30H (0) D＋7 31 H (1) 30H (0) D＋7 31 H (1) 30H (0)
D＋8 33 H (3) 32H (2) D＋8 33 H (3) 32H (2) D＋8 33 H (3) 32H (2)
D＋9 35 H (5) 34H (4) n1th character D＋9 35 H (5) 34H (4) D＋9 35 H (5) 34H (4)
to be deleted
D The characters of the devices other than
the shifted devices do not change.

(2) This instruction stores the NULL code (00H) into the device (one word) that positions after
the last device that stores the character string data when the character string data specified
by D is even, after the characters are deleted.
(3) This instruction stores the NULL code (00H) into the last device (high 8 bits) that stores the
character string data when the character string data specified by D is odd, after the
characters are deleted.
(4) This instruction shifts the characters stored in the devices that position after the deleted
devices by n2 characters to the right, and then stores the NULL code (00H) into the empty
device.

7-242
 STRDEL(P)

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an
error code is stored into SD0.
• The number of characters in the devices specified by D exceeds 16383. 2
(Error code: 4100)
• The value specified by n1 is not within the range. (1 n1 16383) (Error code: 4100)
• The value specified by n1 exceeds the number of characters in the devices specified by
3
D . (Error code: 4100)
• The value specified by n2 exceeds the number of characters in the devices starting from 4
n1th to the last devices position. (Error code: 4100)
• The value specified by n2 is negative. (Error code: 4100)
6
Program Example
(1) The following program deletes the fourth to the seventh characters in the character string 6
data stored in the devices D0 and up, when M0 is turned on.
[Ladder Mode] [List Mode]
7
Step Instruction Device

8
[Operation]
D0 52 H (R) 50H (P) D0 52 H (R) 50H (P) D0 52 H (R) 50H (P)
D1 47 H (G) 4FH (O) D1 47 H (G) 4FH (O) D1 44H (D) 4FH (O)

7.11.19 Deletion of character string (STRDEL(P))

7.11 Character string processing instructions
D2 41 H (A) 52H (R) D2 41 H (A) 52H (R) D2 00 H
D3 41 H (A) 4DH (M) D3 41 H (A) 4DH (M)
D0 character string PROD
D4 43 H (C) 42H (B) D4 43 H (C) 42H (B)
D5 00 H 44H (D) D5 00 H 44H (D)

D0 character string PROGRAMABCD D0 character string PROGRAMABCD

Fourth character Seven characters to be deleted
to be deleted

7-243
 EMOD(P)

7.11.20 Floating decimal point to BCD (EMOD(P))

EMOD(P)

High
Basic performance Process Redundant Universal LCPU

Command
EMOD EMOD S1 S2 D

Command
EMODP EMODP S1 S2 D

S1 : 32-bit floating decimal point real number data or head number of the devices where the floating decimal point
real number data is stored (real number)
S2 : Decimal fraction digits data (BIN 16 bits)
D : Head number of the devices where the data after break down into BCD will be stored (BIN 16 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H E
S1 –– –– *1 –– ––

S2 –– ––

D –– –– –– –– –– –– ––

*1:Available only in multiple Universal model QCPU and LCPU

Function
(1) Dissociate the 32-bit floating decimal point data designated by S1 into BCD type floating
point format based on the decimal fraction digits specified by S2 , and stores the result into
the area starting from the device designated by D .
S1 +1 S1 D Sign When positive : 0
D +1 When negative : 1
7 BCD digits BCD type floating
D +2
32-bit floating-point real number When positive : 0 point format
D +3 Sign (exponent part) When negative : 1
S2 Number of digits in decimal fraction BCD exponent
D +4 (0 to 38)

S1 +1 S1 D 0
3 . 25427 D +1 4270H
3254270H
D +2 0325H
32-bit floating-point real number
D +3 1
S2 3 D +4 3

S2 specifies the decimal fraction digits of the 32-bit floating decimal point real number data
of S1 . In the example above, a decimal fraction digit is designated as shown below:
3.25427

S2 =3

7-244
 EMOD(P)

S1 +1 S1 D 1
0 . 03542768 D +1
D +2
3542770H
1
D +3 1
S2 4 D +4 4

S1 +1 S1 D 1
2
1 . 5 4 3 2 1E + 2 D +1
D +2 1543210H

S2 3
D
D
+3
+4
1
1
3

(2) The 7th digit of the significant digits being stored at +1 and +2 is rounded off to make a
4
D D
6-digit number.
S1 +1 S1 D 0
1 . 2 3456789 D +1
D +2
1234570H 6
D +3 1 123456789
S2 3 D +4 3 Rounded off

1234570 6

Operation Error
7
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The decimal fraction digit designated by S2 is outside the range of from 0 to 7.
8
(Error code: 4100)

• The device range designated by D exceeds the range of the relevant device.
(Error code: 4101)

7.11.20 Floating decimal point to BCD (EMOD(P))

7.11 Character string processing instructions
• The 32-bit floating point real number specified by S1 is outside the following range.
-126 128
0, 2 | device | < 2 (Error code: 4100)

• The device specified by D exceeds the range of the corresponding device.

(For the Universal model QCPU, LCPU.) (Error code: 4101)
• The value of the specified device is 0, unnormalized number, nonnumeric, and ± .
(For the Universal model QCPU, LCPU) (Error code: 4140)

7-245
 EMOD(P)

Program Example
(1) The following program breaks down the 32-bit floating decimal point type real number data
stored at D0 and D1 into BCD according to the decimal fraction digits as designated by R10,
and stores the results into the area starting from D100 when X0 is turned ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
D1 D0 D100 1
0.987654 D101
9876540H
D102
D103 1
R10 3 D104 4

7-246
 EREXP(P)

7.11.21 From BCD format data to floating decimal point

(EREXP(P)) 1
EREXP(P)

High
2
Basic performance Process Redundant Universal LCPU

3
Command
EREXP EREXP S1 S2 D
4
Command
EREXPP S1 S2 D
EREXPP
6
S1 : Head number of the devices where BCD type floating point format data is stored (BIN 16 bits)
S2 : Decimal fraction digits data (BIN 16 bits) 6
D : The device where the converted 32-bit floating point real number data will be stored (real number)

Setting Internal Devices J \ Constants

R, ZR Zn Other
Data Bit Word Bit Word
U \G
K, H
7
S1 –– –– –– –– –– ––

S2 ––

D –– –– *1 –– ––
8
*1:Available only in multiple Universal model QCPU and LCPU

7.11.21 From BCD format data to floating decimal point (EREXP(P))

7.11 Character string processing instructions
Function
(1) Converts the BCD type floating point data designated by S1 to the 32-bit floating decimal
point real number data according to the decimal fraction digits specified by S2 , and stores
the result into the area starting from the device designated by D .
S1 Sign When positive: 0
S1 +1 When negative: 1 D +1 D
BCD type floating BCD 7 digits
point format S1 +2 When positive: 0
S1 +3 Sign (exponent part) When negative: 1
S1 +4 BCD exponent 32-bit floating-point
(0 to 38) real number
S2 Number of digits in decimal fraction (0 to7)

(2) The sign at S1 and the sign for the exponent part at S1 +3 is set at 0 for a positive value and
at 1 for a negative value.

(3) 0 to 38 can be set for the BCD exponent of S1 +4.

(4) 0 to 7 can be set for the decimal fraction digits of S2 .

S1 1 (Sign)
S1 +1 5423H D +1 D
BCD type floating 3215423H (BCD 7 digits)
point format S1 +2 0321H 3 . 2 1 5 4 2 3 E+ 2
S1 +3 0 (Sign (exponent part))
S1 +4 2 (BCD exponent)

S2 6 (Number of digits in decimal fraction)

7-247
 EREXP(P)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The format designated by S1 was neither 0 nor 1. (Error code: 4100)

• A value other than 0 to 9 exists in the each digit of S1 + 1 and S1 + 2. (Error code: 4100)

• The format designation made by S1 + 3 is something other than 0 or 1.

(Error code: 4100)

• The exponent data designated by S1 +4 is outside the range of from 0 to 38.

(Error code: 4100)

• The decimal fraction digit designated by S2 is outside the range of from 0 to 7.

(Error code: 4100)

• The device specified by S1 exceeds the range of the corresponding device.

(For the Universal model QCPU, LCPU.) (Error code: 4101)

Program Example
(1) The following program converts the BCD type floating decimal point format data being
stored in devices starting from D0 to 32-bit floating decimal point type real number data
based on the decimal fraction digit being stored at D10, and stores the result at D100 and
D101 when X0 goes ON.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
D0 1
D1 4567H D101 D100
D2 1234567H (BCD 7 digits)
0123H 1. 2 3 4 5 6 7
D3 1
D4 3

D10 3

7-248
 SIN(P)

7.12 Special function instructions

1
7.12.1 SIN operation on floating-point data (Single precision)
(SIN(P)) 2
SIN(P)

Ver.
High
3
Basic performance Process Redundant Universal LCPU

Basic model QCPU: The upper five digits of the serial No. are "04122" or larger.
4
Command
SIN SIN S D 6
Command
SINP S D
SINP
6
S : Angle data of which the SIN (sine) value is obtained or head number of the devices where the angle data is
stored (real number)
7
D : Head number of the devices where the operation result will be stored (real number)

Setting Internal Devices J \ Constants

R, ZR Zn Other
8
U \G
Data Bit Word Bit Word E

S –– –– *1 ––

D –– –– *1 –– ––

*1: Applicable for the Universal model QCPU, LCPU.

7.12.1 SIN operation on floating-point data (Single precision) (SIN(P))

7.12 Special function instructions
Function
(1) Returns the SIN (sine) value of the angle designated at S and stores the operation result in
the device number designated at D .
S +1 S D +1 D
SIN ( )

32-bit floating-point 32-bit floating-point

real number real number

(2) Angles designated at S are set in radian units (degrees / 180).

For conversion between degrees and radian values, see the RAD and DEG instructions.

7-249
 SIN(P)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The value of the specified device is 0. *2
(For the Basic model QCPU, High Performance model QCPU, Process CPU, Redundant
CPU) (Error code: 4100)
*2: There are CPU modules that will not result in an operation error if 0 is specified. For details, refer to 3.2.4.

• The result exceeds the following range (Operation results in an overflow)

(For the Universal model QCPU, LCPU)
2128 | Operation result | (Error code: 4141)
• The value of the specified device is 0, unnormalized number, nonnumeric, and ± .
(For the Universal model QCPU, LCPU) (Error code: 4140)

Program Example
(1) The following program conducts a SIN operation on the angles stored in the four BCD digits
from X20 to X2F and stores the results at D0 and D1 as 32-bit floating decimal point type
real numbers.
[Ladder Mode]
Inputs an angle used for SIN
operation ( 1 ).
Converts the input angle into
a 32-bit floating-point real
number ( 2 ).
Converts the converted angle
into a radian value ( 3 ).
Executes SIN operation
using the converted radian value ( 4 ).

[List Mode]
Step Instruction Device

[Operations involved when X20 to X2F designate a value of 150]

D30
X2F X20 Conversion to BIN b15 b0
0 1 5 0 150
BCD value BIN BIN value
Conversion to floating-point
FLT

D21 D20 Conversion to radian D11 D10 SIN operation D1 D0

150 2 . 6 17994 0 . 500000
32-bit floating-point RAD 32-bit floating-point SIN 32-bit floating-point
real number real number real number

7-250
 SIND(P)

7.12.2 SIN operation on floating-point data (Double precision)

(SIND(P)) 1
SIND(P)

High
2
Basic performance Process Redundant Universal LCPU

3
Command
SIND SIND S D 4
Command
SINDP S D
SINDP
6
S : Angle data of which the SIN (sine) value is obtained or head number of the devices where the angle data is
stored (real number)
D : Head number of the devices where the operation result will be stored (real number)
6
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data E

S
Bit

––
Word Bit Word

–– ––
7
D –– –– –– ––

8
Function
(1) The SIN (sine) value of the angle specified by is calculated and its result is stored into the

7.12.2 SIN operation on floating-point data (Double precision) (SIND(P))

7.12 Special function instructions
S

device specified by D .

S +3 S +2 S +1 S D +3 D +2 D +1 D
SIN ( )

64-bit floating-point 64-bit floating-point

real number real number

(2) Angles designated at S are set in radian units (degrees / 180).

For conversion between degrees and radian values, see the RADD and DEGD instructions.
(3) When the operation results in -0 or an underflow, the result is processed as 0.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The value of the specified device is not in the following range: (Error code: 4140)
-1022 1024
0,2 | value of specified device | < 2
• The value of the designated device is 0. (Error code: 4140)
• The result exceeds the following range (Operation results in an overflow):
21024 | Operation result | (Error code: 4141)

7-251
 SIND(P)

Program Example
(1) The following program conducts a SIN operation on the angles stored in the four BCD digits
from X20 to X2F and stores the results at D0 to D3 as 64-bit floating decimal point type real
numbers.
[Ladder Mode]

Inputs an angle used for

SIN operation ( 1 ).
Converts the input angle into a
64-bit floating-point real number ( 2 ).
Converts the converted angle
into a radian value ( 3 ).
Executes SIN operation using the
converted radian value ( 4 ).

[List Mode]
Step Instruction Device

[Operations involved when X20 to X2F designate a value of 150]

1 Conversion D30 2 Conversion to

X2F X20 to BIN b15 b0 floating-point D23 D22 D21 D20
0 1 5 0 150 150
BCD value BIN BIN value FLTD 64-bit floating-point
real number
3 Conversion to radian
RADD

D13 D12 D11 D10 4 SIN operation D3 D2 D1 D0

2.617994 0.500000
64-bit floating-point SIND 64-bit floating-point
real number real number

7-252
 COS(P)

7.12.3 COS operation on floating-point data (Single precision)

(COS(P)) 1
COS(P)

Ver.
High
2
Basic performance Process Redundant Universal LCPU

Basic model QCPU: The upper five digits of the serial No. are "04122" or larger.
3
Command
COS COS S D 4
Command
COS
P S D
COSP
6
S : Angle data of which the COS (cosine) value is obtained or head number of the devices where the angle data
is stored (real number) 6
D : Head number of the devices where the operation result will be stored (real number)

Setting Internal Devices J \ Constants

R, ZR Zn Other
Data Bit Word Bit Word
U \G
E
7
S –– –– *1 ––

D –– –– *1 –– ––

*1: Applicable for the Universal model QCPU, LCPU. 8

Function

7.12.3 COS operation on floating-point data (Single precision) (COS(P))

7.12 Special function instructions
(1) Returns the COS (cosine) value of the angle designated by S and stores operation result at
device number designated by D .
S +1 S D +1 D
COS ( )

32-bit floating-point 32-bit floating-point

real number real number

(2) Angles designated at S are set in radian units (degrees / 180).

For conversion between degrees and radian values, see the RAD and DEG instructions.

7-253
 COS(P)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The value of the specified device is 0. *2
(For the Basic model QCPU, High Performance model QCPU, Process CPU, Redundant
CPU) (Error code: 4100)
*2: There are CPU modules that will not result in an operation error if 0 is specified. For details, refer to 3.2.4.

• The result exceeds the following range (Operation results in an overflow)

(For the Universal model QCPU, LCPU)
2128 | Operation result | (Error code: 4141)
• The value of the specified device is 0, unnormalized number, nonnumeric, and ± .
(For the Universal model QCPU, LCPU) (Error code: 4140)

Program Example
(1) The following program performs a COS operation on the angle data designated by the 4
BCD digits from X20 to X2F, and stores results as 32-bit floating decimal point type real
numbers at D0 and D1.
[Ladder Mode]
Inputs an angle used for COS
operation ( 1 ).
Converts the input angle into
a 32-bit floating-point real
number ( 2 ).
Converts the converted angle into
a radian value ( 3 ).
Executes COS operation
using the converted radian value ( 4 ).

[List Mode]

Step Instruction Device

[Operations involved when X20 to X2F designate a value of 60]

D30
X2F X20 Conversion to BIN b15 b0
0 0 6 0 60
BCD value BIN BIN value
Conversion to floating-point
FLT

D21 D20 Conversion to radian D11 D10 COS operation D1 D0

60 1 . 04 7 198 0 . 500000
32-bit floating-point RAD 32-bit floating-point COS 32-bit floating-point
real number real number real number

7-254
 COSD(P)

7.12.4 COS operation on floating-point data (Double precision)

(COSD(P)) 1
COSD(P)

High
2
Basic performance Process Redundant Universal LCPU

3
Command
COSD COSD S D 4
Command
COSDP S D
COSDP
6
S : Angle data of which the COS (cosine) value is obtained or head number of the devices where the angle data

D
is stored (real number)

: Head number of the devices where the operation result will be stored (real number)
6
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word E
7
S –– –– ––

D –– –– –– ––

8
Function
(1) The COS (cosine) value of the angle specified by is calculated and its result is stored into

7.12.4 COS operation on floating-point data (Double precision) (COSD(P))

7.12 Special function instructions
S

the device specified by D .

S +3 S +2 S +1 S D +3 D +2 D +1 D
COS ( )
64-bit floating-point 64-bit floating-point
real number real number

(2) Angles designated at S are set in radian units (degrees / 180).

For conversion between degrees and radian values, see the RADD and DEGD instructions.
(3) When the operation results in -0 or an underflow, the result is processed as 0.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The value of the specified device is not in the following range: (Error code: 4140)
0,2-1022 | value of specified device | < 21024
• The value of the designated device is 0. (Error code: 4140)
• The result exceeds the following range (Operation results in an overflow):
21024 | Operation result | (Error code: 4141)

7-255
 COSD(P)

Program Example
(1) The following program performs a COS operation on the angle data designated by the 4
BCD digits from X20 to X2F, and stores results as 64-bit floating decimal point type real
numbers at D0 to D3.
[Ladder Mode]

Inputs an angle used for

COS operation ( 1 ).
Converts the input angle into a
64-bit floating-point real number ( 2 ).
Converts the converted angle
into a radian value ( 3 ).
Executes COS operation using the
converted radian value ( 4 ).

[List Mode]

Step Instruction Device

[Operations involved when X20 to X2F designate a value of 60]

1 Conversion D30 2 Conversion to

X2F X20 to BIN b15 b0 floating-point D23 D22 D21 D20
0 0 6 0 60 60
BCD value BIN BIN value FLTD 64-bit floating-point
real number
3 Conversion to radian
RADD

D13 D12 D11 D10 4 SIN operation D3 D2 D1 D0

1.047198 0.500000
64-bit floating-point COSD 64-bit floating-point
real number real number

7-256
 TAN(P)

7.12.5 TAN operation on floating-point data (Single precision)

(TAN(P)) 1
TAN(P)

Ver.
High
2
Basic performance Process Redundant Universal LCPU

Basic model QCPU: The upper five digits of the serial No. are "04122" or larger.
3
Command
TAN TAN S D
4
Command
TANP S D
TANP
6
S : Angle data of which the TAN (tangent) value is obtained or head number of the devices where the angle data

D
is stored (real number)

: Head number of the devices where the operation result will be stored (real number)
6
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
7
Data Bit Word Bit Word E

S –– –– *1 ––

D –– –– *1 –– ––

*1: Applicable for the Universal model QCPU, LCPU. 8

Function

7.12.5 TAN operation on floating-point data (Single precision) (TAN(P))

7.12 Special function instructions
(1) Returns the tangent (TAN) value of the angle data designated by S , and stores operation
result in device designated by D .
S +1 S D +1 D
TAN ( )

32-bit floating-point 32-bit floating-point

real number real number

(2) Angles designated at S are set in radian units (degrees / 180).

For conversion between degrees and radian values, see the RAD and DEG instructions.

(3) When angles designated by S are /2 radians, or (3/2) radians, an operation error will
be generated in the calculation of the radian value, so care must be taken to avoid such
errors.

7-257
 TAN(P)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• Operation results are outside the range shown below:
0, 2-126 |operation result| 2128
(For the Basic model QCPU, High Performance model QCPU, Process CPU, Redundant
CPU) (Error code: 4100)
• The value of the specified device is 0. *3
(For the Basic model QCPU, High Performance model QCPU, Process CPU, Redundant
CPU) (Error code: 4100)
*3: There are CPU modules that will not result in an operation error if 0 is specified. For details, refer to 3.2.4.

• The result exceeds the following range (Operation results in an overflow)

(For the Universal model QCPU, LCPU)
2128 | Operation result | (Error code: 4141)
• The value of the specified device is 0, unnormalized number, nonnumeric, and ± .
(For the Universal model QCPU, LCPU) (Error code: 4140)

Program Example
(1) The following program performs a TAN operation on the angle data set by the 4 BCD digits
from X20 to X2F, and stores the results as 32-bit floating decimal point type real numbers at
D0 and D1.
[Ladder Mode]

Inputs an angle used for TAN

operation ( 1 ).
Converts the input angle into a 32-bit
floating-point real number ( 2 ).
Converts the converted angle
into a radian value ( 3 ).
Executes TAN operation using
the converted radian value ( 4 ).

[List Mode]
Step Instruction Device

[Operations involved when X20 to X2F designate a value of 135]

D30
X2F X20 Conversion to BIN b15 b0
0 1 3 5 135
BCD value BIN BCD value
Conversion to floating-point
FLT

D21 D20 Conversion to radian D11 D10 TAN operation D1 D0

135 2 . 356 194 1 . 000000
32-bit floating-point RAD 32-bit floating-point TAN 32-bit floating-point
real number real number real number

7-258
 TAND(P)

7.12.6 TAN operation on floating-point data (Double precision)

(TAND(P)) 1
TAND(P)

High
2
Basic performance Process Redundant Universal LCPU

3
Command
TAND TAND S D
4
Command
TANDP S D
TANDP
6
S : Angle data of which the TAN (tangent) value is obtained or head number of the devices where the angle data
is stored (real number)
D : Head number of the devices where the operation result will be stored (real number)
6
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word E

S –– –– ––
7
D –– –– –– ––

8
Function
(1) The TAN (tangent) value of the angle specified by S is calculated and its result is stored into

7.12.6 TAN operation on floating-point data (Double precision) (TAND(P))

7.12 Special function instructions
the device specified by D .
S +3 S +2 S +1 S D +3 D +2 D +1 D
TAN ( )
64-bit floating-point 64-bit floating-point
real number real number

(2) Angles designated at S are set in radian units (degrees / 180).

For conversion between degrees and radian values, see the RADD and DEGD instructions.

(3) When angles designated by S are /2 radians, or (3/2) radians, an operation error will
be generated in the calculation of the radian value, so care must be taken to avoid such
errors.
(4) When the operation results in -0 or an underflow, the result is processed as 0.

7-259
 TAND(P)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The value of the specified device is not in the following range: (Error code: 4140)
0,2-1022 | value of specified device | < 21024
• The value of the designated device is 0. (Error code: 4140)
• The result exceeds the following range (Operation results in an overflow):
21024 | Operation result | (Error code: 4141)

Program Example
(1) The following program performs a TAN operation on the angle data set by the 4 BCD digits
from X20 to X2F, and stores the results as 64-bit floating decimal point type real numbers at
D0 to D3.
[Ladder Mode]

Inputs an angle used for TAN

operation ( 1 ).
Converts the input angle into a
64-bit floating-point real number ( 2 ).
Converts the converted angle into a
radian value ( 3 ).
Executes TAN operation using the
converted radian value ( 4 ).

[List Mode]

Step Instruction Device

[Operations involved when X20 to X2F designate a value of 135]

1 Conversion D30 2 Conversion to
X2F X20 to BIN b15 b0 floating-point D23 D22 D21 D20
0 1 3 5 135 135
BCD value BIN BIN value FLTD 64-bit floating-point
real number
3 Conversion to radian
RADD

D23 D22 D21 D20 4 TAN operation D23 D22 D21 D20
2.356194 -1.000000
64-bit floating-point TAND 64-bit floating-point
real number real number

7-260
 ASIN(P)

7.12.7 SIN-1 operation on floating point data (Single precision)

(ASIN(P)) 1
ASIN(P)

High
2
Basic performance Process Redundant Universal LCPU

3
Command
ASIN ASIN S D
4
Command
ASINP S D
ASINP
6
S : SIN value of which the SIN-1 (inverse sine) value is obtained or head number of the devices where the SIN
value is stored (real number)
6
D : Head number of the devices where the operation result will be stored (real number)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word E
7
S –– –– *1 ––

D –– –– *1 –– ––

*1: Applicable for the Universal model QCPU, LCPU. 8

Function

7.12.7 SIN-1 operation on floating point data (Single precision) (ASIN(P))

7.12 Special function instructions
(1) Returns the SIN-1 angle of the SIN value designated by S , and stores operation results at
word device designated by D .
S +1 S D +1 D
-1
SIN ( )

32-bit floating-point 32-bit floating-point

real number real number

(2) The SIN value designated by S can be in the range from 1.0 to 1.0.

(3) The angle (operation result) stored at D is stored in radian units.

For more information on the conversion between radian and angle data, see description of
RAD and DEG instructions.

7-261
 ASIN(P)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The value designated by S is outside the range of from 1.0 to 1.0. (Error code: 4100)
• The contents of the designated device or the result of the addition are not "0", or not within
the following range(For the Universal model QCPU, LCPU): (Error code: 4140)
0, 2-126 | Contents of designated device | < 2128
• The value of the specified device is 0. *2
(For the High Performance model QCPU, Process CPU, Redundant CPU)
(Error code: 4100)
*2: There are CPU modules that will not result in an operation error if 0 is specified. Refer to 3.2.4 for details.

• The result exceeds the following range (Operation results in an overflow)

(For the Universal model QCPU, LCPU)
2128 | Operation result | (Error code: 4141)
• The value of the specified device is 0, unnormalized number, nonnumeric, and ± .
(For the Universal model QCPU, LCPU) (Error code: 4140)

7-262
 ASIN(P)

Program Example
1
(1) The following program seeks the inverse sine of the 32-bit floating decimal point real number
at D0 and D1, and outputs the angle to the 4 BCD digits at Y40 to Y4F.
[Ladder Mode] 2
Calculates an angle (radian value)
by SIN-1 operation ( 1 ) 3
Converts the radian value
into an angle ( 2 )
Converts the angle in
32-bit floating-point real
number into an integer ( 3 ) 4
Outputs the integer-converted
angle to a display device ( 4 )

6
[List Mode]
Step Instruction Device
6

8
[Operations involved when the D0 and D1 value is 0.5]
D1 D0 SIN-1 operation D11 D10
0.5 0 . 5235988
32-bit floating-point ASIN 32-bit floating-point

7.12.7 SIN-1 operation on floating point data (Single precision) (ASIN(P))

7.12 Special function instructions
real number real number
Conversion to angle
DEG

Conversion D30
D21 D20 b15 b0 BCD operation Y4F Y40
toBIN
30 30 0 0 3 0
32-bit floating-point INT BIN value BCD BCD value
real number

7-263
 ASIND(P)

7.12.8 SIN-1 operation on floating-point data (Double precision)

(ASIND(P))
ASIND(P)

High
Basic performance Process Redundant Universal LCPU

Command
ASIND ASIND S D

Command
ASINDP S D
ASINDP

S : SIN value of which the SIN-1 (inverse sine) value is obtained or head number of the devices where the SIN
value is stored (real number)
D : Head number of the devices where the operation result will be stored (real number)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word E

S –– –– ––

D –– –– –– ––

Function
(1) The angle is calculated from the SIN (sine) value specified by S is and its result is stored
into the device specified by D .
S +3 S +2 S +1 S D +3 D +2 D +1 D
1
SIN ( )
64-bit floating-point 64-bit floating-point
real number real number

(2) The SIN value designated by S can be in the range from 1.0 to 1.0.

(3) The angle (operation result) stored at D is stored in radian units.

For more information on the conversion between radian and angle data, see description of
RADD and DEGD instructions.
(4) When the operation results in -0 or an underflow, the result is processed as 0.

7-264
 ASIND(P)

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The value of the specified device is not in the following range: (Error code: 4140) 2
0,2-1022 | value of specified device | < 21024
• The value of the designated device is 0. (Error code: 4140) 3
• The value specified by S is within the double-precision floating-point range and outside
the range of -1.0 to 1.0. (Error code: 4100)
• The result exceeds the following range (Operation results in an overflow): 4
21024 | Operation result | (Error code: 4141)

6
Program Example
(1) The following program seeks the inverse sine of the 64-bit floating decimal point real number
at D0 to D3, and outputs the angle to the 4 BCD digits at Y40 to Y4F.
6
[Ladder Mode]
7
Calculates an angle (radian value)
by SIN 1 operation ( 1 ).
Converts the radian value into
an angle ( 2 ). 8
Converts the angle in 64-bit floating-point
real number into an integer ( 3 ).
Outputs the integer-converted angle to a
display device ( 4 ).

7.12.8 SIN-1 operation on floating-point data (Double precision) (ASIND(P))

7.12 Special function instructions
[List Mode]

Step Instruction Device

[Operations involved when the D0 to D3 value is 0.5]

D3 D2 D1 D0 1 SIN 1 operation D13 D12 D11 D10
0.5 0.5235988
64-bit floating-point ASIND 64-bit floating-point
real number real number
2 Conversion to angle
DEGD

3 Conversion D30
D23 D22 D21 D20 to BIN b15 b0 4 BCD operation Y4F Y40
30 30 0 0 3 0
64-bit floating-point INTD BIN value BCD BCD value
real number

7-265
 ACOS(P)

7.12.9 COS -1 operation on floating-point data (Single precision)

(ACOS(P))
ACOS(P)

High
Basic performance Process Redundant Universal LCPU

Command
ACOS ACOS S D

Command
ACOSP S D
ACOSP

S : COS value of which the COS-1 (inverse cosine) value is obtained or head number of the devices where the
COS value is stored (real number)
D : Head number of the devices where the operation result will be stored (real number)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word E

S –– –– *1 ––

D –– –– *1 –– ––

*1: Applicable for the Universal model QCPU, LCPU.

Function
(1) Returns the COS-1 angle of the COS value designated by S , and stores operation result at
word device designated by D .
S +1 S D +1 D
COS -1 )

32-bit floating-point 32-bit floating-point

real number real number

(2) The COS value designated by S can be in the range of from 1.0 to 1.0.

(3) The angle (operation result) stored at D is stored in radian units.

For more information on the conversion between radian and angle data, see description of
RAD and DEG instructions.

7-266
 ACOS(P)

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The value designated by S is outside the range of from 1.0 to 1.0. (Error code: 4100)
2
• The contents of the designated device or the result of the addition are not "0", or not within
the following range(For the Universal model QCPU, LCPU): (Error code: 4140)
3
0, 2-126 | Contents of designated device | < 2128
• The value of the specified device is 0. *2
(For the Basic model QCPU, High Performance model QCPU, Process CPU, Redundant 4
CPU) (Error code: 4100)
*2: There are CPU modules that will not result in an operation error if 0 is specified. Refer to 3.2.4 for details.

• The result exceeds the following range (Operation results in an overflow) 6

(For the Universal model QCPU, LCPU)
2128 | Operation result | (Error code: 4141)
6
• The value of the specified device is 0, unnormalized number, nonnumeric, and ± .
(For the Universal model QCPU, LCPU) (Error code: 4140)

7
Program Example
(1) The following program seeks the inverse cosine of the 32-bit floating decimal point real 8
number at D0 and D1, and outputs the angle to the 4 BCD digits at Y40 to Y4F.
[Ladder Mode]

Calculates an angle (radian value)

7.12.9 COS -1 operation on floating-point data (Single precision) (ACOS(P))

7.12 Special function instructions
by COS-1 operation ( 1 )
Converts the radian value into an angle ( 2 )

Converts the angle in 32-bit floating-point

real number into an integer ( 3 )
Outputs the integer-converted angle
to a display device ( 4 )

[List Mode]

Step Instruction Device

[Operations involved when the D0 and D1 value is 0.5]

D1 D0 COS-1 operation D11 D10
0.5 1 . 04 7 198
32-bit floating-point ACOS 32-bit floating-point
real number real number
Conversion to angle
DEG

Conversion D30
D21 D20 to BIN b15 b0 BCD operation Y4F Y40
60 60 0 0 6 0
32-bit floating-point INT BIN value BCD BCD value
real number

7-267
 ACOSD(P)

7.12.10 COS -1 operation on floating-point data (Double precision)

(ACOSD(P))
ACOSD(P)

High
Basic performance Process Redundant Universal LCPU

Command
ACOSD ACOSD S D

Command
ACOSDP S D
ACOSDP

S : COS value of which the COS-1 (inverse cosine) value is obtained or head number of the devices where the
COS value is stored (real number)
D : Head number of the devices where the operation result will be stored (real number)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word E

S –– –– ––

D –– –– –– ––

Function
(1) The angle is calculated from the COS (cosine) value specified by S is and its result is
stored into the device specified by D .
S +3 S +2 S +1 S D +3 D +2 D +1 D
1
COS ( )
64-bit floating-point 64-bit floating-point
real number real number

(2) The COS value designated by S can be in the range of from 1.0 to 1.0.

(3) The angle (operation result) stored at D is stored in radian units.

For more information on the conversion between radian and angle data, see description of
RADD and DEGD instructions.
(4) When the operation results in -0 or an underflow, the result is processed as 0.

7-268
 ACOSD(P)

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The value of the specified device is not in the following range: (Error code: 4140) 2
0,2-1022 | value of specified device | < 21024
• The value of the designated device is 0. (Error code: 4140) 3
• The value specified by S is within the double-precision floating-point range and outside
the range of -1.0 to 1.0. (Error code: 4100)
• The result exceeds the following range (Operation results in an overflow): 4
21024 | Operation result | (Error code: 4141)

6
Program Example
(1) The following program seeks the inverse cosine of the 64-bit floating decimal point real
number at D0 to D3, and outputs the angle to the 4 BCD digits at Y40 to Y4F.
6
[Ladder Mode]

Calculates an angle (radian value) by COS 1 7

operation ( 1 ).
Converts the radian value into an angle ( 2 ).

Converts the angle in 64-bit floating-point

8
real number into an integer ( 3 ).
Outputs the integer-converted angle to a
display device ( 4 ).

7.12.10 COS -1 operation on floating-point data (Double precision) (ACOSD(P))

7.12 Special function instructions
[List Mode]

Step Instruction Device

[Operations involved when the D0 to D3 value is 0.5]

D3 D2 D1 D0 1 COS 1 operation D13 D12 D11 D10

0.5 1.047198
64-bit floating-point ACOSD 64-bit floating-point
real number real number
2 Conversion to angle
DEGD

3 Conversion D30
D23 D22 D21 D20 to BIN b15 b0 4 BCD operation Y4F Y40
60 60 0 0 6 0
64-bit floating-point INTD BIN value BCD BCD value
real number

7-269
 ATAN(P)

7.12.11 TAN -1 operation on floating-point data (Single precision)

(ATAN(P))
ATAN(P)

High
Basic performance Process Redundant Universal LCPU

Command
ATAN ATAN S D

Command
ATANP S D
ATANP

S : TAN value of which the TAN-1 (inverse tangent) value is obtained or head number of the devices where the
TAN value is stored (real number)
D : Head number of the devices where the operation result will be stored (real number)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word E

S –– –– *1 ––

D –– –– *1 –– ––

*1: Applicable for the Universal model QCPU, LCPU.

Function
(1) Returns the TAN-1 angle of the TAN value designated by S , and stores operation results at
word device designated by D .
S +1 S D +1 D
-1
TAN ( )

32-bit floating-point 32-bit floating-point

real number real number

(2) The angle (operation result) stored at D is stored in radian units.

For more information on the conversion between radian and angle data, see description of
RAD and DEG instructions.

7-270
 ATAN(P)

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The contents of the designated device or the result of the addition are not "0", or not within 2
the following range(For the Universal model QCPU, LCPU): (Error code: 4140)
0, 2-126 | Contents of designated device | < 2128
3
• The value of the specified device is 0. *2
(For the High Performance model QCPU, Process CPU, Redundant CPU)
(Error code: 4100)
4
*2: There are CPU modules that will not result in an operation error if 0 is specified. Refer to 3.2.4 for details.

• he result exceeds the following range (Operation results in an overflow)

(For the Universal model QCPU, LCPU) 6
2128 | Operation result | (Error code: 4141)
• The value of the specified device is 0, unnormalized number, nonnumeric, and ± .
(For the Universal model QCPU, LCPU) (Error code: 4140) 6

Program Example 7
(1) The following program seeks the inverse tangent of the 32-bit floating decimal point real
number at D0 and D1, and outputs the angle to the 4 BCD digits at Y40 to Y4F.
8
[Ladder Mode]

Calculates an angle (radian value)

by TAN-1 operation ( 1 )
Converts the radian value

7.12.11 TAN -1 operation on floating-point data (Single precision) (ATAN(P))

7.12 Special function instructions
into an angle ( 2 )
Converts the angle in
32-bit floating-point real
number into an integer ( 3 )
Outputs the integer-converted
angle to a display device ( 4 )

[List Mode]
Step Instruction Device

[Operations involved when D0 and D1 value is 1]

D1 D0 -1
TAN operation D11 D10
1 0 . 785398
32-bit floating-point ATAN 32-bit floating-point
real number real number
Conversion to angle
DEG

D30
D21 D20 Conversion to BIN b15 b0 BCD operation Y4F Y40
45 45 0 0 4 5
32-bit floating-point INT BIN value BCD BCD value
real number

7-271
 ATAND(P)

7.12.12 TAN -1 operation on floating-point data (Double precision)

(ATAND(P))
ATAND(P)

High
Basic performance Process Redundant Universal LCPU

Command
ATAND ATAND S D

Command
ATANDP S D
ATANDP

S : TAN value of which the TAN-1 (inverse tangent) value is obtained or head number of the devices where the
TAN value is stored (real number)
D : Head number of the devices where the operation result will be stored (real number)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word E

S –– –– ––

D –– –– –– ––

Function
(1) The angle is calculated from the TAN (tangent) value specified by S is and its result is
stored into the device specified by D .

S +3 S +2 S +1 S D +3 D +2 D +1 D
1
TAN ( )
64-bit floating-point 64-bit floating-point
real number real number

(2) The angle (operation result) stored at D is stored in radian units.

For more information on the conversion between radian and angle data, see description of
RADD and DEGD instructions.
(3) When the operation results in -0 or an underflow, the result is processed as 0.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The value of the specified device is not in the following range: (Error code: 4140)
-1022 1024
0,2 | value of specified device | < 2
• The value of the designated device is 0. (Error code: 4140)
• The result exceeds the following range (Operation results in an overflow):
21024 | Operation result | (Error code: 4141)

7-272
 ATAND(P)

Program Example
1
(1) The following program seeks the inverse tangent of the 64-bit floating decimal point real
number at D0 to D3, and outputs the angle to the 4 BCD digits at Y40 to Y4F.
[Ladder Mode] 2
1
Calculates an angle (radian value) by TAN
operation ( 1 ). 3
Converts the radian value into
an angle ( 2 ).
Converts the angle in 64-bit floating-point
real number into an integer ( 3 ). 4
Outputs the integer-converted angle
to a display device ( 4 ).

6
[List Mode]
6
Step Instruction Device

8
[Operations involved when D0 to D3 value is 1]
D3 D2 D1 D0 1 TAN 1 operation D13 D12 D11 D10
1 0.785398

7.12.12 TAN -1 operation on floating-point data (Double precision) (ATAND(P))

7.12 Special function instructions
64-bit floating-point ATAND 64-bit floating-point
real number real number
2 Conversion to angle
DEGD

3 Conversion D30
D23 D22 D21 D20 to BIN b15 b0 4 BCD operation Y4F Y40
45 45 0 0 4 5
64-bit floating-point INTD BIN value BCD BCD value
real number

7-273
 RAD(P)

7.12.13 Conversion from floating-point angle to radian

(Single precision) (RAD(P))
RAD(P)

Ver.
High
Basic performance Process Redundant Universal LCPU

Basic model QCPU: The upper five digits of the serial No. are "04122" or larger.

Command
RAD RAD S D

Command
RADP S D
RADP

S : Angle to be converted to radian units or head number of the devices where the angle is stored (real number)
D : Head number of the devices where the value converted in radian units will be stored (real number)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word E

S –– –– *1 ––

D –– –– *1 –– ––

*1: Applicable for the Universal model QCPU, LCPU.

Function
(1) Converts units of angle size from angle units designated by S to radian units, and stores
result at device number designated by D .
S +1 S D +1 D
( ) ( )rad

32-bit floating-point 32-bit floating-point

real number real number

(2) Conversion from degree to radian units is performed according to the following equation:
Radian unit = Degree unit x
180

7-274
 RAD(P)

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The contents of the designated device or the result of the addition are not "0", or not within 2
the following range(For the Universal model QCPU, LCPU): (Error code: 4140)
0, 2-126 | Contents of designated device | < 2128
3
• The value of the specified device is 0. *3
(For the Basic model QCPU, High Performance model QCPU, Process CPU, Redundant
CPU) (Error code: 4100)
4
*3: There are CPU modules that will not result in an operation error if 0 is specified. For details, refer to 3.2.4.

• The result exceeds the following range (Operation results in an overflow)

(For the Universal model QCPU, LCPU) 6
2128 | Operation result | (Error code: 4141)
• The value of the specified device is 0, unnormalized number, nonnumeric, and ± .
(For the Universal model QCPU, LCPU) (Error code: 4140) 6

Program Example
7
(1) The following program converts the angle set by the 4 BCD digits at X20 to X2F to radians,
and stores results as 32-bit floating decimal point type real number at D20 and D21.
[Ladder Mode] 8
Inputs an angle to be converted
into a radian value ( 1 )
Converts the input a 32-bit
floating-point real number ( 2 )

7.12.13 Conversion from floating-point angle to radian (Single precision) (RAD(P))

7.12 Special function instructions
Converts the converted angle into
a radian value ( 3 )

[List Mode]
Step Instruction Device

[Operations involved when X20 to X2F designate a value of 120]

Conversion D0 Conversion to Conversion
X2F X20 to BIN b15 b0 floating-point D11 D10 to radian D21 D20
0 1 2 0 120 120 2 . 094395
BCD value BIN BIN value FLT RAD

7-275
 RADD(P)

7.12.14 Conversion from floating-point angle to radian

(Double precision) (RADD(P))
RADD(P)

High
Basic performance Process Redundant Universal LCPU

Command
RADD RADD S D

Command
RADDP S D
RADDP

S : Angle to be converted to radian units or head number of the devices where the angle is stored (real number)
D : Head number of the devices where the value converted in radian units will be stored (real number)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word E

S –– –– ––

D –– –– –– ––

Function
(1) The unit expressing the size of an angle is converted into the radian unit from the degree
unit specified by S , and its result is stored into the device specified by D .

S +3 S +2 S +1 S D +3 D +2 D +1 D
( ) ( )rad

64-bit floating-point 64-bit floating-point

real number real number

(2) Conversion from degree to radian units is performed according to the following equation:
Radian unit = Degree unit x
180

(3) When the operation results in -0 or an underflow, the result is processed as 0.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The value of the specified device is not in the following range: (Error code: 4140)
-1022 1024
0,2 | value of specified device | < 2
• The value of the designated device is 0. (Error code: 4140)
• The result exceeds the following range (Operation results in an overflow):
21024 | Operation result | (Error code: 4141)

7-276
 RADD(P)

Program Example
1
(1) The following program converts the angle set by the 4 BCD digits at X20 to X2F to radians,
and stores results as 64-bit floating decimal point type real number at D20 to D23.
[Ladder Mode] 2
Inputs an angle to be converted into a
radian value ( 1 ).
Converts the input angle into a 64-bit
3
floating-point real number ( 2 ).
Converts the converted angle into a
radian value ( 3 ). 4

6
[List Mode]
Step Instruction Device
6

7
[Operations involved when X20 to X2F designate a value of 120]
1 Conversion D0 2 Conversion to 3 Conversion
X2F X20
0 1 2 0
to BIN b15
120
b0 floating-point D13 D12 D11 D10
120
to radian D23 D22 D21 D20
2.094395···
8
BCD value BIN BIN value FLTD RADD

7.12.14 Conversion from floating-point angle to radian (Double precision) (RADD(P))

7.12 Special function instructions

7-277
 DEG(P)

7.12.15 Conversion from floating-point radian to angle

(Single precision) (DEG(P))
DEG(P)

Ver.
High
Basic performance Process Redundant Universal LCPU

Basic model QCPU: The upper five digits of the serial No. are "04122" or larger.

Command
DEG DEG S D

Command
DEGP S D
DEGP

S : Radian angle to be converted to degrees or head number of the devices where the radian angle is stored
(real number)
D : Head number of the devices where the value converted in degrees will be stored (real number)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word E

S –– –– *1 ––

D –– –– *1 –– ––

*1: Applicable for the Universal model QCPU, LCPU.

Function
(1) Converts units of angle size from radian units designated by S to angles, and stores result
at device number designated by D .
S +1 S D +1 D
( )rad (

32-bit floating-point 32-bit floating-point

real number real number

(2) The conversion from radians to angles is performed according to the following equation:

Degree unit = Radian unit x 180

7-278
 DEG(P)

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The value of the specified device is 0. *2
2
(For the Basic model QCPU, High Performance model QCPU, Process CPU, Redundant
CPU) (Error code: 4100)
*2: There are CPU modules that will not result in an operation error if 0 is specified. For details, refer to 3.2.4.
3
• The result exceeds the following range (Operation results in an overflow)
(For the Universal model QCPU, LCPU)
4
2128 | Operation result | (Error code: 4141)
• The value of the specified device is 0, unnormalized number, nonnumeric, and ± .
(For the Universal model QCPU, LCPU) (Error code: 4140) 6
Program Example
6
(1) The following program converts the radian value set with 32-bit floating decimal point type
real number at D20 and D21 to angles, and stores the result as a BCD value at Y40 to Y4F.
[Ladder Mode] 7
Converts a radian value into
an angle ( 1 )
Converts the angle in 8
32-bit floating-point real
number into an integer ( 2 )
Outputs the converted integer
to a display device ( 3 )

7.12.15 Conversion from floating-point radian to angle (Single precision) (DEG(P))

7.12 Special function instructions
[List Mode]

Step Instruction Device

[Operations involved when the values at D20 and D21 are 1.435792]
Conversion Conversion D0
D21 D20 to angle D11 D10 to BIN b15 b0 BCD operation Y4F Y40
1 . 435792 82 . 26482 82 0 0 8 2
32-bit floating-point DEG 32-bit floating-point BIN BIN value BCD BCD value
real number real number

7-279
 DEGD(P)

7.12.16 Conversion from floating-point radian to angle

(Double precision) (DEGD(P))
DEGD(P)

High
Basic performance Process Redundant Universal LCPU

Command
DEGD DEGD S D

Command
DEGDP S D
DEGDP

S : Radian angle to be converted to degrees or head number of the devices where the radian angle is stored
(real number)
D : Head number of the devices where the value converted in degrees will be stored (real number)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word E

S –– –– ––

D –– –– –– ––

Function
(1) The unit expressing the size of an angle is converted into the degree unit from the radian
unit specified by S , and its result is stored into the device specified by D .
S +3 S +2 S +1 S D +3 D +2 D +1 D
( )rad ( )

64-bit floating-point 64-bit floating-point

real number real number

(2) The conversion from radians to angles is performed according to the following equation:

Degree unit = Radian unit x 180

(3) When the operation results in -0 or an underflow, the result is processed as 0.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The value of the specified device is not in the following range: (Error code: 4140)
0,2-1022 | value of specified device | < 21024
• The value of the designated device is 0. (Error code: 4140)
• The result exceeds the following range (Operation results in an overflow):
21024 | Operation result | (Error code: 4141)

7-280
 DEGD(P)

Program Example
1
(1) The following program converts the radian value set with 64-bit floating decimal point type
real number at D20 to D23 to angles, and stores the result as a BCD value at Y40 to Y4F.
[Ladder Mode] 2

Converts a radian value into an angle ( 1 ).

3
Converts the angle in 64-bit floating-point
real number into an integer ( 2 ).
Outputs the converted integer to a display
device ( 3 ). 4

[List Mode] 6
Step Instruction Device

[Operations involved when the values at D20 to D23 are 1.435792] 7

1 Conversion 2 Conversion D0
D23 D22 D21 D20 to angle D13 D12 D11 D10 to BIN b15 b0 3 BCD operation Y4F Y40

8
1.435792 82.26482 82 0 0 8 2
64-bit floating-point DEGD 64-bit floating-point INTD BIN value BCD BCD value
real number real number

7.12.16 Conversion from floating-point radian to angle (Double precision) (DEGD(P))

7.12 Special function instructions

7-281
 POW(P)

7.12.17 Exponentiation operation on floating-point data

(Single precision) (POW(P))
POW(P)

Ver.
High
Basic performance Process Redundant Universal LCPU

QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later.

QnUDE(H)CPU: The serial number (first five digits) is "10102" or later.

Command
POW POW S1 S2 D

Command
POWP POWP S1 S2 D

S1 : Exponentiation recipient data or head number of the devices where the exponentiation recipient data are
stored (real number)
S2 : Exponentiation data or head number of the devices where the data are stored (real number)

D : Head number of the devices where the operation result will be stored (real number)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word E

S1 –– –– *1 ––

S2 –– –– *1

D –– –– –– ––

*1: Available only for real number

Function
(1) This instruction raises the 32-bit floating-point data type real number specified by S1 to the
number nth specified by S2 power, and then stores the operation result into the device
specified by D .
Exponentiation data
S2 ＋1 S2

S1 ＋1 S1 D ＋1 D

Exponentiation recipient data

S1 ＋1 S1 × S1 ＋1 S1 × ……… × S1 ＋1 S1 × S1 ＋1 S1

The instruction raises S1 ＋1 S1 to S2 ＋1 S2 th power.

32-bit floating-point 32-bit floating-point

data type real number data type real number

(2) The following shows the values to be specified by and stored into S1 or S2 .
-126 128
0, 2 | Set values (Storage values) | < 2

(3) If the value resulted from the operation is 0 or an underflow occurs, the result will be
processed as 0.

7-282
 POW(P)

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an
error code is stored into SD0.
• The values specified by S1 or S2 are out of the ranges shown below. (Error code: 4140)
2
0, 2-126 | Specified value (Storage value) | < 2128

• The value of S1 or S2 is 0. (Error code: 4140) 3

• The values in the operation result is within the range shown below. (Error code: 4141)
126
2 | Value resulted from operation |
4
Program Example
6
(1) The following program raises the 32-bit floating-point data type real number data specified
by D0 and D1 to the data specified by (D10 and D11)th power, when X10 is turned on. Then
the program stores the operation result into D20 and D21.
[Ladder Mode] [List Mode]
6
Step Instruction Device

[Operation] 8
D11 D10
1.2
D1 D0 Exponentiation D21 D20
operation
0.22 0.163

7.12.17 Exponentiation operation on floating-point data (Single precision) (POW(P))

7.12 Special function instructions

7-283
 POWD(P)

7.12.18 Exponentiation operation on floating-point data

(Single precision) (POWD(P))
POWD(P)

Ver.
High
Basic performance Process Redundant Universal LCPU

QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later.

QnUDE(H)CPU: The serial number (first five digits) is "10102" or later.

Command
POWD POWD S1 S2 D

Command
POWDP POWDP S1 S2 D

S1 : Exponentiation recipient data or head number of the devices where the exponentiation recipient data are
stored (real number)
S2 : Exponentiation data or head number of the devices where the data are stored (real number)
D : Head number of the devices where the operation result will be stored (real number)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word E

S1 –– –– –– *1 ––

S2 –– –– –– *1 ––

D –– –– –– –– ––

*1: Available only for real number

Function
(1) This instruction raises the 64-bit floating-point data type real number specified by S1 to the
number nth specified by S2 power, and then stores the operation result into the device
specified by D .
Exponentiation data
S2 ＋3 S2 ＋2 S2 ＋1 S2

S1 ＋3 S1 ＋2 S1 ＋1 S1 D ＋3 D ＋2 D ＋1 D

Exponentiation recipient data

S1 ＋3 S1 ＋2 S1 ＋1 S1 × S1 ＋3 S1 ＋2 S1 ＋1 S1 × ……… × S1 ＋3 S1 ＋2 S1 ＋1 S1

S1 ＋3 S1 ＋2 S1 ＋1 S1 raised to the power of S2 ＋3 S2 ＋2 S2 ＋1 S2 is carried out.

64-bit floating-point data type real number 64-bit floating-point data type real number

(2) The following shows the values to be specified by and stored into S1 or S2

-1022 1024
0, 2 | Set values (Storage values) | < 2

(3) If the value resulted from the operation is 0 or an underflow occurs, the result will be
processed as 0.

7-284
 POWD(P)

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an
error code is stored into SD0.
• The values specified by S1 or S2 are out of the range shown below. (Error code: 4140) 2
-1022 1024
0, 2 | Set values (Storage values) | < 2

• The value of or is 0. (Error code: 4140)

S1 S2
3
• The values resulted from the operation is within the range shown below.
21024 | Value resulted from operation | (Error code: 4141)
4
Program Example
(1) The following program raises the 64-bit floating-point data type real number specified by 6
D200 to D203 to the number nth specified by D0 to D3 power, when X10 is turned on. Then
the program stores the operation result into D100 to D103.
[Ladder Mode] [List Mode] 6
Step Instruction Device

[Operation]
8
D3 D2 D1 D0
Exponentiation
3
operation
D203 D202 D201 D200 D103 D102 D101 D100

15.6 3796.416

7.12.18 Exponentiation operation on floating-point data (Single precision) (POWD(P))

7.12 Special function instructions

7-285
 SQR(P)

7.12.19 Square root operation for floating-point data

(Single precision) (SQR(P))
SQR(P)

Ver.
High
Basic performance Process Redundant Universal LCPU

Basic model QCPU: The upper five digits of the serial No. are "04122" or larger.

Command
SQR SQR S D

Command
SQRP S D
SQRP

S : Data of which the square root is obtained or head number of the devices where the data is stored
(real number)
D : Head number of the devices where the operation result will be stored (real number)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word E

S –– –– *1 ––

D –– –– *1 –– ––

*1: Applicable for the Universal model QCPU, LCPU.

Function
(1) Returns the square root of the value designated at S , and stores the operation result in the
device number designated at D .

S +1 S D +1 D
( )

32-bit floating-point 32-bit floating-point

real number real number

(2) Only positive values can be designated by S . (Operation cannot be performed on negative
numbers.)

7-286
 SQR(P)

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The value designated by S is a negative number. (Error code: 4100)
2
• The contents of the designated device or the result of the addition are not "0", or not within
the following range(For the Universal model QCPU, LCPU): (Error code: 4140)
3
0, 2-126 | Contents of designated device | < 2128
• The value of the specified device is 0. *3
(For the Basic model QCPU, High Performance model QCPU, Process CPU, Redundant 4
CPU, and Q4ARCPU) (Error code: 4100)
*3: There are CPU modules that will not result in an operation error if 0 is specified. For details, refer to 3.2.4.

• The result exceeds the following range (Operation results in an overflow) 6

(For the Universal model QCPU, LCPU)
2128 | Operation result | (Error code: 4141)
6
• The value of the specified device is 0, unnormalized number, nonnumeric, and ± .
(For the Universal model QCPU, LCPU) (Error code: 4140)

7
Program Example
(1) The following program seeks the square root of the value set by the 4 BCD digits from X20 8
to X2F, and stores the result as a 32-bit floating decimal point type real number at D0 and
D1.
[Ladder Mode]

7.12.19 Square root operation for floating-point data (Single precision) (SQR(P))
7.12 Special function instructions
Inputs data used for
square root operation ( 1 )
Converts the input data into a
32-bit floating-point real number ( 2 )
Executes square root
operation ( 3 )

[List Mode]
Step Instruction Device

[Operations involved when value designated by X20 to X2F is 650]

1 Conversion D20 2 Conversion to
X2F X20 to BIN b15 b0 floating-point D11 D10 3 SQR operation D1 D0
0 6 5 0 650 650 25 . 4951
BCD value BIN BIN value FLT SQR

7-287
 SQRD(P)

7.12.20 Square root operation for floating-point data

(Double precision) (SQRD(P))
SQRD(P)

High
Basic performance Process Redundant Universal LCPU

Command
SQRD SQRD S D

Command
SQRDP S D
SQRDP

S : Data of which the square root is obtained or head number of the devices where the data is stored
(real number)
D : Head number of the devices where the operation result will be stored (real number)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word E

S –– –– ––

D –– –– –– ––

Function
(1) Returns the square root of the value designated at S , and stores the operation result in the
device number designated at D .

S +3 S +2 S +1 S D +3 D +2 D +1 D
( )

64-bit floating-point 64-bit floating-point

real number real number

(2) Only positive values can be designated by S . (Operation cannot be performed on negative
numbers.)
(3) When the operation results in -0 or an underflow, the result is processed as 0.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The value designated by S is a negative number. (Error code: 4100)
• The value of the specified device is not in the following range: (Error code: 4140)
-1022 1024
0,2 | value of specified device | < 2
• The value of the designated device is 0. (Error code: 4140)
• The result exceeds the following range (Operation results in an overflow):
21024 | Operation result | (Error code: 4141)

7-288
 SQRD(P)

Program Example
1
(1) The following program seeks the square root of the value set by the 4 BCD digits from X20
to X2F, and stores the result as a 64-bit floating decimal point type real number at D0 to D3.
[Ladder Mode] 2

Inputs data used for square root

operation ( 1 ). 3
Converts the input data into a 64-bit
floating-point real number ( 2 ).
Executes square root operation ( 3 ).
4

[List Mode] 6
Step Instruction Device

[Operations involved when value designated by X20 to X2F is 650] 7

1 Conversion D20 2 Conversion to
X2F X20 to BIN b15 b0 floating-point D13 D12 D11 D10 3 SQR operation D3 D2 D1 D0
0 6 5 0
BCD value BIN
650
BIN value FLTD
650
SQRD
25.4951 8

7.12.20 Square root operation for floating-point data (Double precision) (SQRD(P))
7.12 Special function instructions

7-289
 EXP(P)

7.12.21 Exponent operation on floating-point data

(Single precision) (EXP(P))
EXP(P)

Ver.
High
Basic performance Process Redundant Universal LCPU

Basic model QCPU: The upper five digits of the serial No. are "04122" or larger.

Command
EXP EXP S D

Command
EXPP S D
EXPP

S : Data of which the exponential value is obtained or head number of the devices where the data is stored
(real number)
D : Head number of the devices where the operation result will be stored (real number)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word E

S –– –– *1 ––

D –– –– *1 –– ––

*1: Applicable for the Universal model QCPU, LCPU.

Function
(1) Returns the exponent of the value designated by S , and stores the results of the operation
at the device designated by D .
S +1 S D +1 D

e ( )

32-bit floating-point 32-bit floating-point

real number real number

(2) Exponent operations are calculated taking the base (e) to be "2.71828".

7-290
 EXP(P)

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• Operation results are outside the range shown below: (Error code: 4100) 2
2-126 | operation result | 2128
(For a High Performance model QCPU)
2-126 | operation result | 2128
3
(For a Basic model QCPU/Process CPU/Redundant CPU)
• The value of the specified device is 0. *3 4
(For the Basic model QCPU, High Performance model QCPU, Process CPU, Redundant
CPU) (Error code: 4100)
*3: There are CPU modules that will not result in an operation error if 0 is specified. For details, refer to 3.2.4.
6
• The result exceeds the following range (Operation results in an overflow)
(For the Universal model QCPU, LCPU)
2128 | Operation result | (Error code: 4141) 6
• The value of the specified device is 0, unnormalized number, nonnumeric, and ± .
(For the Universal model QCPU, LCPU) (Error code: 4140)
7

7.12.21 Exponent operation on floating-point data (Single precision) (EXP(P))

7.12 Special function instructions

7-291
 EXP(P)

Program Example
(1) The following program performs an exponent operation on the value set by the 2 BCD digits
at X20 to X27, and stores the results as a 32-bit floating decimal point real number at D0 and
D1.
[Ladder Mode]

Inputs the data used for

exponent operation ( 1 ).

Checks the range of the

value for operation. *4

Converts the input data into

a 32-bit floating-point real number ( 2 ).
Executes exponent operation ( 3 ).

[List Mode]
Step Instruction Device

[Operations involved when value designated by X20 to X27 is 13]

1 Conversion D20 2 Conversion to
X27 X20 to BIN b15 b0 floating-point D11 D10 3 EXP operation D1 D0
1 3 13 13 4 4 24 13 . 4
BCD value BIN BIN value FLT 32-bit floating-point EXP 32-bit floating-point
real number real number

*4: The operation result will be under 2129 if the BCD value of X20 to X27 is less than 89, from the calculation
loge 2129 = 89.4.
Because setting a value of over 90 will return an operation error, turn M0 ON if a value of over 90 has been
set to avoid the error.

Conversion from natural logarithm to common logarithm

In the CPU module, calculation is made using a natural logarithm.
To obtain a common logarithm value, enter in, S a common logarithm value
divided by 0.43429.

7-292
 EXPD(P)

7.12.22 Exponent operation on floating-point data

(Double precision) (EXPD(P)) 1
EXPD(P)

High
2
Basic performance Process Redundant Universal LCPU

3
Command
EXPD EXPD S D 4
Command
EXPDP S D
EXPDP
6
S : Data of which the exponential value is obtained or head number of the devices where the data is stored
(real number)
6
D : Head number of the devices where the operation result will be stored (real number)

Setting Internal Devices J \ Constants

R, ZR Zn Other
7
U \G
Data Bit Word Bit Word E

S –– –– ––

D –– –– –– ––
8

Function

7.12.22 Exponent operation on floating-point data (Double precision) (EXPD(P))

7.12 Special function instructions
(1) Returns the exponent of the value designated by S , and stores the results of the operation
at the device designated by D .
S +3 S +2 S +1 S D +3 D +2 D +1 D
e ( ) ( )

64-bit floating-point 64-bit floating-point

real number real number

(2) Exponent operations are calculated taking the base (e) to be "2.71828".
(3) When the operation results in -0 or an underflow, the result is processed as 0.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The value of the specified device is not in the following range: (Error code: 4140)
0,2-1022 | value of specified device | < 21024
• The value of the designated device is 0. (Error code: 4140)
• The result exceeds the following range (Operation results in an overflow):
21024 | Operation result | (Error code: 4141)

7-293
 EXPD(P)

Program Example
(1) The following program performs an exponent operation on the value set by the 2 BCD digits
at X20 to X31, and stores the results as a 64-bit floating decimal point real number at D0 to
D3.
[Ladder Mode]

Inputs data used for exponent

operation ( 1 ).
Checks the range of the value used
for operation. *1
Converts the input data into a 64-bit
floating-point real number ( 2 ).
Executes exponent operation ( 3 ).

[List Mode]
Step Instruction Device

[Operations involved when value designated by X20 to X31 is 13]

1 Conversion D20 2 Conversion to
X31 X20 to BIN b15 b0 floating-point D13 D12 D11 D10 3 EXP operation D3 D2 D1 D0
0 1 3 13 13 442413.4
BCD value BIN BIN value FLTD 64-bit floating-point EXPD 64-bit floating-point
real number real number

*1: The operation result will be under 21024 if the BCD value of X20 to X31 is less than 709, from the calculation
loge 21024 = 709.7832.
Because setting a value of over 710 will return an operation error, turn M0 ON if a value of over 710 has been
set to avoid the error.

Conversion from natural logarithm to common logarithm

In the CPU module, calculation is made using a natural logarithm.
To obtain a common logarithm value, enter in, S a common logarithm value
divided by 0.43429.

7-294
 LOG(P)

7.12.23 Natural logarithm operation on floating-point data

(Single precision) (LOG(P)) 1
LOG(P)

Ver.
High
2
Basic performance Process Redundant Universal LCPU

Basic model QCPU: The upper five digits of the serial No. are "04122" or larger.
3
Command
LOG LOG S D 4
Command
LOGP S D
LOGP
6
S : Data of which the natural logarithm is obtained or head number of the devices where the data is stored
(real number)
6
D : Head number of the devices where the operation result will be stored (real number)

Settiing Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word E
7
S –– –– *1 ––

D –– –– *1 –– ––

*1: Applicable for the Universal model QCPU, LCPU. 8

Function

7.12.23 Natural logarithm operation on floating-point data (Single precision) (LOG(P))

7.12 Special function instructions
(1) Returns the natural logarithm of the value designated by S taking (e) as base, and stores
operation results at device designated by D .
S +1 S D +1 D
log ( )

32-bit floating-point 32-bit floating-point

real number real number

(2) Only positive values can be designated by S . (Operation cannot be performed on negative
numbers.)

7-295
 LOG(P)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The value designated by S is negative. (Error code: 4100)

• The value designated by S is 0. (Error code: 4100)

• The contents of the designated device or the result of the addition are not "0", or not within
the following range(For the Universal model QCPU, LCPU): (Error code: 4140)
0, 2-126 | Contents of designated device | < 2128
• The value of the specified device is 0. *3
(For the Basic model QCPU, High Performance model QCPU, Process CPU, Redundant
CPU) (Error code: 4100)
*3: There are CPU modules that will not result in an operation error if 0 is specified. For details, refer to 3.2.4.

• The result exceeds the following range (Operation results in an overflow)

(For the Universal model QCPU, LCPU)
2128 | Operation result | (Error code: 4141)
• The value of the specified device is 0, unnormalized number, nonnumeric, and ± .
(For the Universal model QCPU, LCPU) (Error code: 4140)

Program Example
(1) The following program seeks the natural logarithm of the value "10" set by D50, and stores
the result at D30 and D31.
[Ladder Mode]

Sets data used for natural

logarithm operation ( 1 )
Converts the operation data
into a 32-bit floating-point real number ( 2 )
Executes natural logarithm operation ( 3 )

[List Mode]
Step Instruction Device

[Operation]
D50 Conversion to
1 b15 b0 2
floating-point D41 D40 3 LOG operation D31 D30
10 10 10 2 . 302585
MOV BIN value FLT 32-bit floating-point LOG 32-bit floating-point
real number real number

7-296
 LOGD(P)

7.12.24 Natural logarithm operation on floating-point data

(Double precision) (LOGD(P)) 1
LOGD(P)

High
2
Basic performance Process Redundant Universal LCPU

3
Command
LOGD LOGD S D 4
Command
LOGDP S D
LOGDP
6
S : Data of which the natural logarithm is obtained or head number of the devices where the data is stored

D
(real number)

: Head number of the devices where the operation result will be stored (real number)
6
Settiing Internal Devices J \ Constants
R, ZR U \G Zn Other
Data E
Bit Word Bit Word
7
S –– –– ––

D –– –– –– ––

8
Function
(1) Returns the natural logarithm of the value designated by taking (e) as base, and stores

7.12.24 Natural logarithm operation on floating-point data (Double precision) (LOGD(P))

7.12 Special function instructions
S

operation results at device designated by D .

S +3 S +2 S +1 S D +3 D +2 D +1 D
log ( ) ( )

64-bit floating-point 64-bit floating-point

real number real number

(2) Only positive values can be designated by S . (Operation cannot be performed on negative
numbers.)
(3) When the operation results in -0 or an underflow, the result is processed as 0.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The value designated by S is negative. (Error code: 4100)
• The value designated by S is 0. (Error code: 4100)
• The value of the specified device is not in the following range: (Error code: 4140)
-1022 1024
0,2 | value of specified device | < 2
• The value of the designated device is 0. (Error code: 4140)
• The result exceeds the following range (Operation results in an overflow):
21024 | Operation result | (Error code: 4141)

7-297
 LOGD(P)

Program Example
(1) The following program seeks the natural logarithm of the value "10" set by D50, and stores
the result at D30 to D33.
[Ladder Mode]

Sets data used for natural logarithm

operation ( 1 ).
Converts the operation data into a 64-bit
floating-point real number ( 2 ).
Executes natural logarithm operation ( 3 ).

[List Mode]
Step Instruction Device

[Operation]
D50 2 Conversion to
1 b15 b0 floating-point D43 D42 D41 D40 3 LOG operation D33 D32 D31 D30
10 10 10 2.302585
MOV BIN value FLTD 64-bit floating-point LOGD 64-bit floating-point
real number real number

7-298
 LOG10(P)

7.12.25 Common logarithm operation on floating-point data

(Single precision) (LOG10(P)) 1
LOG10(P)

High
Ver. 2
Basic performance Process Redundant Universal LCPU

QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later.

QnUDE(H)CPU: The serial number (first five digits) is "10102" or later. 3

Command 4
LOG10 LOG10 S D

Command
LOG10P LOG10P S D 6

S : Data of which the common logarithm is obtained or head number of the devices where the data are stored
(real number)
6
D : Head number of the devices where the operation result will be stored (real number)

Settiing
Data
Internal Devices
R, ZR
J \
U \G Zn
Constants
E
Other 7
Bit Word Bit Word

S –– –– –– *1 ––

D –– –– –– –– –– 8
*1: Available only for real number.

Function

7.12.25 Common logarithm operation on floating-point data (Single precision) (LOG10(P))

7.12 Special function instructions
(1) This instruction obtains the value specified by S for common logarithm (logarithm with base
10), and then stores the operation result into the device specified by D .

Log10 S ＋1 S D ＋1 D

32-bit floating-point 32-bit floating-point

data type real number data type real number

(2) Only positive values can be specified by S . (Operation cannot be performed on negative
numbers.)

(3) If the value resulted from the operation is 0 or an underflow occurs, the result will be
processed as 0.

7-299
 LOG10(P)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an
error code is stored into SD0.
• The value specified by S is negative. (Error code: 4100)

• The value specified by S is 0. (Error code: 4100)

• The value of the specified device is not in the following range. (Error code: 4140)
0,2-126 | value of specified device | < 2128

• The value specified by S is 0. (Error code: 4140)

• The value resulted from the operation is within the range shown below.
(When an overflow occurs): (Error code: 4141)
2128 | value of specified device |

Program Example
(1) The following program obtains the value for common logarithm of the 32-bit floating-point
data type real number specified by D600 or D601, when X10 is turned on. Then the program
stores the operation result into D123 or D124.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
D601 D600 D124 D123

Log10 2.806 0.448088

7-300
 LOG10D(P)

7.12.26 Common logarithm operation on floating-point data

(Double precision) (LOG10D(P)) 1
LOG10D(P)

High
Ver. 2
Basic performance Process Redundant Universal LCPU

QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later.

QnUDE(H)CPU: The serial number (first five digits) is "10102" or later. 3

Command 4
LOG10D LOG10D S D

Command
LOG10DP LOG10DP S D 6

S : Data of which the common logarithm is obtained or head number of the devices where the data are stored
(real number)
6
D : Head number of the devices where the operation result will be stored (real number)

Settiing
Data
Internal Devices
R, ZR
J \
U \G Zn
Constants
K, H
Other 7
Bit Word Bit Word

S –– –– *1 ––

D –– –– –– –– 8
*1: Available only for real number.

Function

7.12.26 Common logarithm operation on floating-point data (Double precision) (LOG10D(P))

7.12 Special function instructions
(1) This instruction obtains the value specified by S for common logarithm (logarithm with base
10),and then stores the operation result into the device specified by D .

Log10 S ＋3 S ＋2 S ＋1 S D ＋3 D ＋2 D ＋1 D

64-bit floating-point 64-bit floating-point

data type real number data type real number

(2) Only positive values can be specified by S . (Operation cannot be performed on negative
numbers.)

(3) If the value resulted from the operation is 0 or an underflow occurs, the result will be
processed as 0.

7-301
 LOG10D(P)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an
error code is stored into SD0.
• The value specified by S is negative. (Error code: 4100)

• The value specified by S is 0. (Error code: 4100)

• The value of the specified device is not in the following range: (Error code: 4140)
0,2-1022 | value of specified device | < 21024
• The value of the specified device is 0. (Error code: 4140)
• The value resulted from the operation is within the range shown below.
(When an overflow occurs): (Error code: 4141)
21024 | value of specified device |

Program Example
(1) This following program obtains the value for common logarithm of the 64-bit floating-point
data type real number specified by D600 to D603 when M0 is turned on. Then the program
stores the operation result into D123 to D126.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]

D603 D602 D601 D600 D126 D125 D124 D123

Log10 2.806 0.448088

7-302
 RND(P),SRND(P)

7.12.27 Random number generation and series updates

(RND(P),SRND(P)) 1
RND(P),SRND(P)

Ver.
High
2
Basic performance Process Redundant Universal LCPU

Basic model QCPU: The upper five digits of the serial No. are "04122" or larger.
3
Command
RND RND D 4
Command
RNDP D
RNDP
6
Command
SRND SRND S

Command 6
SRNDP S
SRNDP

7
D : Head number of the devices where random numbers will be stored (BIN 16 bits)
S : Random number serial data or the first number of the devices where the random number serial data is stored
(BIN 16 bits)

Setting Internal Devices Constants

8
J \
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

D –– ––

S ––

7.12.27 Random number generation and series updates (RND(P),SRND(P))

7.12 Special function instructions
Function
The random number generation instruction generates random numbers conforming to a certain
calculation formula. In the calculation using the formula, the result of previous calculation is used
as a coefficient.
The random series change instruction can change the random number generation pattern.

RND
Generates random number of from 0 to 32767, and stores at device designated by D .

SRND
Updates random number series according to the 16-bit BIN data being stored in device
designated by S .

7-303
 RND(P),SRND(P)

Operation Error
(1) There are no operation errors associated with the RND(P) or SRND(P) instructions.

Program Example
(1) The following program stores random number at D100 when X10 is turned ON.
[Ladder Mode] [List Mode]

Step Instruction Device

(2) The following program updates a random number series according to the contents of D0
when X10 is turned ON.
[Ladder Mode] [List Mode]

Step Instruction Device

7-304
 BSQR(P),BDSQR(P)

7.12.28 BCD 4-digit and 8-digit square roots

(BSQR(P),BDSQR(P)) 1
BSQR(P),BDSQR(P)

High
2
Basic performance Process Redundant Universal LCPU

3
BSQR/BDSQR
Command 4
BSQR,BDSQR S D

Command
BSQRP,BDSQRP P S D 6

S : Data of which the square root is obtained or the number of the device where the data is stored 6
(BSQR(P): BCD 4 digits, BDSQR(P): BCD 8 digits)
D : Head number of the devices where the square root calculation result will be stored (BCD 4 digits)

Setting Internal Devices

R, ZR
J \
U \G Zn
Constants
Other
7
Data Bit Word Bit Word K, H

S ––

D –– –– 8

Function

7.12.28 BCD 4-digit and 8-digit square roots (BSQR(P),BDSQR(P))

7.12 Special function instructions
BSQR

(1) Returns the square root of the value designated at S , and stores the operation result in the
device number designated at D .
D D +1
S Integer part . Decimal fraction part

(2) Values that can be designated at S are BCD values with a maximum of 4 digits
(from 0 to 9999).

(3) The operation results of D and D +1 are stored as their respective BCD values of between
0 and 9999.
(4) Operation results are rounded off from the fifth decimal place.
For this reason, the fourth decimal place has an error of ±1.

7-305
 BSQR(P),BDSQR(P)

BDSQR

(1) Calculates the square root of the values designated by S and S +1 and stores the results at
the device designated by D .
D D +1
( S +1 S ) Integer part . Decimal fraction part

2-word data

(2) BCD value of a maximum of 8 digits (0 to 99999999) can be designated by S and S +1.

(3) The operation results of D and D +1 are stored as their respective BCD values of between
0 and 9999.
(4) Operation results are rounded off from the fifth decimal place.
For this reason, the fourth decimal place has an error of ±1.

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• The data designated by S is not a BCD value. (Error code: 4100)

Program Example
(1) The following program calculates the square root of BCD value 1325 and outputs the integer
part to the 4 BCD digits from Y50 to Y5F, and the decimal fraction part to the 4 BCD digits
from Y40 to Y4F.
[Ladder Mode]
Sets the data used for
square root operation ( 1 )
Executes square root operation ( 2 )

Outputs the integer part of the operation

result to a display device ( 3 )

Outputs the decimal fraction part of the

operation result to a display device ( 4 )

[List Mode]
Step Instruction Device

[Operation]
D0 BSQR operation D1 Transfer Y5F Y50
1325H 1 3 2 5 0 0 3 6 0 0 3 6 Integer part
MOV BCD value BSQR BCD value BCD value

D2 Transfer Y4F Y40

4 0 0 5 4 0 0 5 Decimal fraction part
BCD value MOV BCD value

7-306
 BSQR(P),BDSQR(P)

(2) The following program calculates the square root of BCD value 74625813 and outputs the
integer part of the result to the 4 BCD digits at Y50 to Y5F, and the decimal fraction part to
the 4 BCD digits from Y40 to Y4F. 1
[Ladder Mode]

Sets the data (BCD value) used

for square root operation ( 1 )
2
Executes square root operation ( 2 )
Outputs the integer part of the
operation result to a display device ( 3 ) 3
Outputs the decimal fraction part of
the operation result to a display device ( 4 )
4

[List Mode]
6
Step Instruction Device

[Operation] 7
1 D1 D0 2 BDSQR operation D2 3 Transfer Y5F Y50
74625813 7 4 6 2 5 8 1 3 8 6 3 8 8 6 3 8 Integer part

8
BCD value DMOV BCD value BDSQR BCD value MOV BCD value

D3 4 Transfer Y4F Y40

6 2 3 3 6 2 3 3 Decimal fraction part
BCD value MOV BCD value

7.12.28 BCD 4-digit and 8-digit square roots (BSQR(P),BDSQR(P))

7.12 Special function instructions

7-307
 BSIN(P)

7.12.29 BCD type SIN operation (BSIN(P))

BSIN(P)

High
Basic performance Process Redundant Universal LCPU

Command
BSIN BSIN S D

Command
BSINP S D
BSINP

S : Data of which the SIN (sine) value is obtained or the number of the device where the data is stored
(BCD 4 digits)
D : Head number of the devices where the operation result will be stored (BCD 4 digits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S ––

D –– –– ––

Function
(1) Calculates the SIN (sine) value of value (angle) designated by S , and stores the sign of the
operation result in the device designated at D , and the operation result in the devices
designated at D +1 and D +2.
D D + 1 D + 2
SIN S Sign Integer part . Decimal fraction part

(2) The value designated at S is a BCD value which can be between 0 and 360 degrees
(in units of degrees).

(3) The sign for the operation result stored in D will be "0" if the result is a positive value, and
"1" if the result is a negative value.

(4) The operation results stored in D +1 and D +2 are BCD values between 1.000 and 1.000.
(5) Operation results are rounded off from the fifth decimal place.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The data designated by S is not a BCD value. (Error code: 4100)

• The data designated by S is not in the range of from 0 to 360. (Error code: 4100)

• The device specified by D exceeds the range of the corresponding device.

(For the Universal model QCPU, LCPU.) (Error code: 4101)

7-308
 BSIN(P)

Program Example
1
(1) The program example below calculates the SIN of 3-digit BCD data designated by X20 to
X2B, and outputs a 1-digit BCD part to the integer part from Y50 to Y53, and a 4-digit BCD
fraction part from Y40 to Y4F. 2
Y60 is turned ON if the results of the operation are negative. (If a value has been set at X20
to X2F that is greater than 360, it will be adjusted to be in the range from 0 to 360.)
[Ladder Mode] 3
Processes so that the input
angle is within 360° ( 1 )
Executes SIN operation ( 2 ) 4
Outputs the integer part of the operation
result to a display device ( 3 )
Outputs the decimal fraction part of the 6
operation result to a display device ( 4 )
Outputs the sign of the operation result
by ON or OFF ( 5 )
6

[List Mode]
7
Step Instruction Device
8

7.12.29 BCD type SIN operation (BSIN(P))

7.12 Special function instructions
[Operations involved when value designated by X20 to X2B is 590]
X2B X20 1 B/ operation D10
5 9 0 0 0 0 1
BCD value B/ BCD value
(quotient)
2 BSIN 5
D11 operation D20
0 2 3 0 0 0 0 1 Y60 ON
BCD value BSIN BCD value OUT
(remainder)
D21 3 Transfer Y53 Y50
0 0 0 0 0
BCD value MOV BCD value

D22 4 Transfer Y4F Y40

7 6 6 0 7 6 6 0
BCD value MOV BCD value

7-309
 BCOS(P)

7.12.30 BCD type COS operations (BCOS(P))

BCOS(P)

High
Basic performance Process Redundant Universal LCPU

Command
BCOS BCOS S D

Command
BCOSP S D
BCOSP

S : Data of which the COS (cosine) value is obtained or head number of the devices where the data is stored
(BCD 4 digits)
D : Head number of the devices where the operation result will be stored (BCD 4 digits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S ––

D –– –– ––

Function
(1) Calculates COS (cosine) value of value (angle) designated by S , then stores the sign for
the operation result in the word device designated by D , and the operation result in the
word device designated by D +1 and D +2.
D D +1 D +2
COS S Sign Integer part . Decimal fraction part

(2) The value designated at S is a BCD value which can be between 0 and 360 degrees
(in units of degrees).

(3) The sign for the operation result stored in D will be "0" if the result is a positive value, and
"1" if the result is a negative value.

(4) The operation results stored in D +1 and D +2 are BCD values between 1.000 and 1.000.
(5) Operation results are rounded off from the fifth decimal place.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The data designated by S is not a BCD value. (Error code: 4100)

• The data designated by S is not in the range of from 0 to 360. (Error code: 4100)

• The device specified by D exceeds the range of the corresponding device.

(For the Universal model QCPU, LCPU.) (Error code: 4101)

7-310
 BCOS(P)

Program Example
1
(1) The following program calculates the cosine of the data designated by the 3 BCD digits from
X20 to X2B and outputs the integer part of the result to 1 BCD digit from Y50 to Y53, and the
decimal fraction part of the result to the 4 BCD digits from Y40 to Y4F. 2
Y60 is turned ON if the results of the operation are negative.
[Ladder Mode]
3
Processes so that the input
angle is within 360° ( 1 )
Executes COS operation ( 2 )

Outputs the integer part of the operation

4
result to a display device ( 3 )
Outputs the decimal fraction part of the
operation result to a display device ( 4 ) 6
Outputs the sign of the operation result
by ON or OFF ( 5 )

6
[List Mode]
Step Instruction Device
7

[Operations involved when value designated by X20 to X2B is 430]

D10

7.12.30 BCD type COS operations (BCOS(P))

7.12 Special function instructions
X2B X20 1 B/ operation
4 3 0 0 0 0 1
BCD value B/ BCD value
(quotient)
2 BCOS
D11 D20 5
operation
0 0 7 0 0 0 0 0 Y60 ON
BCD value BCOS BCD value OUT
(remainder)
D21 3 Transfer Y53 Y50
0 0 0 0 0
BCD value MOV BCD value

D22 4 Transfer Y4F Y40

3 4 2 0 3 4 2 0
BCD value MOV BCD value

7-311
 BTAN(P)

7.12.31 BCD type TAN operation (BTAN(P))

BTAN(P)

High
Basic performance Process Redundant Universal LCPU

Command
BTAN BTAN S D

Command
BTANP S D
BTANP

S : Data of which the TAN (tangent) value is obtained or head number of the devices where the data is stored
(BCD 4 digits)
D : Head number of the devices where the operation result will be stored (BCD 4 digits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S ––

D –– –– ––

Function
(1) Calculates TAN (tangent) value for value (angle) designated by S , and stores the sign for
the operation result in the word device designated by D , and the operation result in the
word device designated by D +1 and D +2.
D D +1 D +2
TAN S Sign Integer part . Decimal fraction part

(2) The value designated at S is a BCD value which can be between 0 and 360 degrees
(in units of degrees).

(3) The sign for the operation result stored in D will be "0" if the result is a positive value, and
"1" if the result is a negative value.

(4) The operation results stored at D +1 and D +2 are BCD values within the range of from
57.2901 and 57.2902.
(5) Operation results are rounded off from the fifth decimal place.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The data designated by S is not a BCD value. (Error code: 4100)

• The data designated by S is not in the range of from 0 to 360. (Error code: 4100)

• The data designated by S is 90° or 270°. (Error code: 4100)

• The device specified by D exceeds the range of the corresponding device.

(For the Universal model QCPU, LCPU.) (Error code: 4101)

7-312
 BTAN(P)

Program Example
1
(1) The following program calculates the tangent of the data stored in the 3 BCD digits from X20
to X2B, and stores the integer part of the results in the 4 BCD digits from Y50 to Y53, and
the decimal fraction part in the 4 BCD digits from Y40 to Y4F. 2
Y60 is turned ON if the results of the operation are negative.
[Ladder Mode]
3
Processes so that the input
angle is within 360° ( 1 )

2
6
3

4 6
5

[List Mode]
8
Step Instruction Device

7.12.31 BCD type TAN operation (BTAN(P))

7.12 Special function instructions
[Operations involved when X20 to X2B designate a value of 390]
X2B X20 1 B/ operation D10
3 9 0 0 0 0 1
BCD value B/ BCD value
(quotient)
2 BTAN
D11 operation D20 5
0 0 3 0 0 0 0 0 Y60 OFF
BCD value BTAN BCD value OUT
(remainder)
D21 3 Transfer Y53 Y50
0 0 0 0 0
BCD value MOV BCD value

D22 4 Transfer Y4F Y40

5 7 7 4 5 7 7 4
BCD value MOV BCD value

7-313
 BASIN(P)

7.12.32 BCD type SIN -1 operations (BASIN(P))

BASIN(P)

High
Basic performance Process Redundant Universal LCPU

Command
BASIN BASIN S D

Command
BASINP S D
BASINP

S : Number of the device where data of which the SIN-1 (inverse sine) value is obtained is stored
(BCD 4 digits)
D : Head number of the devices where the operation result will be stored (BCD 4 digits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S –– –– –– ––

D –– ––

Function
(1) Returns the SIN-1 (inverse sine) value of the value designated by S and stores operation
results (angles) at device designated by D .
S S +1 S +2
SIN 1 ( Sign Integer part . Decimal fraction part ) D

(2) A sign for the operation data is set at S .

If the operation data is a positive value, this is set at "0", and if it is a negative value, it is set
at "1".

(3) The part before the decimal point and fraction part are stored at S +1 and S +2 respectively,
as BCD values.
(Settings can be between 0 and 1.0000.)

(4) Operation results stored at D are BCD values between 0 and 90 degrees, and 270 and 360
degrees (degree units).
(5) Calculation results are a value from which the decimal fraction part has been rounded.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The data designated by S is not a BCD value. (Error code: 4100)

• Data designated by S is not in the range of from 1.0000 to 1.0000.

(Error code: 4100)

• The device specified by S exceeds the range of the corresponding device.

(For the Universal model QCPU, LCPU.) (Error code: 4101)

7-314
 BASIN(P)

Program Example
1
(1) The following program performs a SIN-1 operation on the sign (positive when X0 is OFF, and
negative when X0 is ON), the BCD 1-digit integer part from X30 to X33 and the BCD 4-digit
decimal fraction part from X20 to X2F, and outputs the calculated angle in 4 BCD digits from 2
Y40 to Y4F.
[Ladder Mode]
3
Sets the sign of a SIN value ( 1 )

4
Sets the integer part of a SIN value ( 2 )

Sets the decimal fraction part of a SIN value ( 3 )

6
Executes range check for the set SIN value

6
Executes Sin-1 operation and outputs
the result of operation to Y40 to Y4F ( 4 )

7
[List Mode]
Step Instruction Device
8

7.12.32 BCD type SIN -1 operations (BASIN(P))

7.12 Special function instructions
[Operations involved when X20 to X33 designates value of 0.4753]
D0
X0 OFF 0 0 0 0
BCD value

X33 X30 Transfer D1 BASIN operation Y4F Y40

0 0 0 0 0 0 0 2 8
BCD value MOV BCD value BASIN BCD value

X2F X20 Transfer D2

4 7 5 3 4 7 5 3
BCD value MOV BCD value

7-315
 BACOS(P)

7.12.33 BCD type COS -1 operation (BACOS(P))

BACOS(P)

High
Basic performance Process Redundant Universal LCPU

Command
BACOS BACOS S D

Command
BACOSP S D
BACOSP

S : Number of the device where data of which the COS-1 (inverse cosine) value is obtained is stored
(BCD 4 digits)
D : Head number of the devices where the operation result will be stored (BCD 4 digits)

Setting Internal Devices J \

R, ZR U \G Zn Constants Other
Data Bit Word Bit Word

S –– –– ––

D ––

Function
(1) Returns the COS-1 (inverse cosine) value of the value designated by S , and stores
operation results at device designated by D .
S S +1 S +2
COS 1 ( Sign Integer part . Decimal fraction part ) D

(2) A sign for the operation data is set at S .

If the operation data is a positive value, this is set at "0", and if it is a negative value, it is set
at "1".

(3) The part before the decimal point and fraction part are stored at S +1 and S +2 respectively,
as BCD values.
(Settings can be between 0 and 1.0000.)

(4) The operation results stored at D will be a BCD value in the range of between 0 and 180°
(degree units).
(5) Calculation results are a value from which the decimal fraction part has been rounded.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The operation data designated by S is not a BCD value. (Error code: 4100)

• The operation data designated by S is not in the range of from 1.0000 to 1.0000.
(Error code: 4100)

• The device specified by S exceeds the range of the corresponding device.

(For the Universal model QCPU, LCPU.) (Error code: 4101)

7-316
 BACOS(P)

Program Example
1
(1) The following program performs a COS-1 operation on the sign (positive when X0 is OFF,
and negative when X0 is ON), the BCD 1-digit integer part from X30 to X33 and the BCD
4-digit decimal fraction part from X20 to X2F, and outputs the calculated angle in 4 BCD 2
digits from Y40 to Y4F.
[Ladder Mode]
3
Sets the sign of a COS value ( 1 )

4
Sets the integer part of a COS value ( 2 )

Sets the decimal fraction part of a COS value ( 3 )

6
Turns M0 ON when D1>1 or D1=1 and D2 0
6
Executes COS-1 operation and outputs
the result of operation to Y40 to Y4F ( 4 )
7
[List Mode]
8
Step Instruction Device

7.12.33 BCD type COS -1 operation (BACOS(P))

7.12 Special function instructions
[Operations involved if X0 and X20 to X33 designate a value of 0.7650]
1 D0
X0 ON 0 0 0 1
BCD value

X33 X30 2 Transfer D1 4 BACOS operation Y4F Y40

0 0 0 0 0 0 1 4 0
BCD value MOV BCD value BACOS BCD value

X2F X20 3 Transfer D2

7 6 5 0 7 6 5 0
BCD value MOV BCD value

7-317
 BATAN(P)

7.12.34 BCD type TAN -1 operations (BATAN(P))

BATAN(P)

High
Basic performance Process Redundant Universal LCPU

Command
BATAN BATAN S D

Command
BATANP S D
BATANP

S : Number of the device where data of which the TAN-1 (inverse tangent) value is obtained is stored
(BCD 4 digits)
D : Head number of the devices where the operation result will be stored (BCD 4 digits)

Setting Internal Devices J \

R, ZR U \G Zn Constants Other
Data Bit Word Bit Word

S –– –– ––

D ––

Function
(1) Performs TAN-1 (inverse tangent) on value designated by S and stores operation results
(angles) at device designated by D .
S S +1 S +2
TAN 1 ( Sign Integer part . Decimal fraction part ) D

(2) A sign for the operation data is set at S .

If the operation data is a positive value, this is set at "0", and if it is a negative value, it is set
at "1".

(3) The part before the decimal point and fraction part are stored at S +1 and S +2 respectively,
as BCD values.
(Values from 0 to 9999.9999 can be set.)

(4) Operation results stored at D are BCD values between 0 and 90 degrees, and 270 and 360
degrees (degree units).
(5) Calculation results are a value from which the decimal fraction part has been rounded.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The operation data designated by S is not a BCD value. (Error code: 4100)

• The device specified by S exceeds the range of the corresponding device.

(For the Universal model QCPU, LCPU.) (Error code: 4101)

7-318
 BATAN(P)

Program Example
1
(1) The following program performs a TAN-1 operation on the sign (positive when X0 is OFF,
and negative when X0 is ON), the BCD 4-digit integer part from X20 to X2F and the BCD
4-digit decimal fraction part from X30 to X3F, and outputs the calculated angle in 4 BCD 2
digits from Y40 to Y4F.
[Ladder Mode]
3
Sets the sign of a TAN value ( 1 )

4
Sets the integer part of a TAN value ( 2 )

Sets the decimal fraction part of a TAN value ( 3 )

6
Executes TAN-1 operation and outputs
the result of operation to Y40 to Y4F ( 4 )

6
[List Mode]
Step Instruction Device
7

[Operations involved when X0 and X20 to X2F designate a value of 1.2654]

7.12.34 BCD type TAN -1 operations (BATAN(P))

7.12 Special function instructions
1 D0
X0 OFF 0 0 0 0
BCD value

X2F X20 2 Transfer D1 4 BATAN operation Y4F Y40

0 0 0 1 0 0 0 1 0 0 5 2
BCD value MOV BCD value BATAN BCD value

X3F X30 3 Transfer D2

2 6 5 4 2 6 5 4
BCD value MOV BCD value

7-319
 LIMIT(P),DLIMIT(P)

7.13 Data Control Instructions

7.13.1 Upper and lower limit controls for BIN 16-bit and BIN 32-bit
data (LIMIT(P),DLIMIT(P))
LIMIT(P),DLIMIT(P)

Basic High
performance Process Redundant Universal LCPU

indicates an instruction symbol of LIMIT/DLIMIT.

Command
LIMIT, DLIMIT S1 S2 S3 D

Command
P S1 S2 S3 D
LIMITP, DLIMITP

S1 : Lower limit value (minimum output threshold value) (BIN 16/32 bits)
S2 : Upper limit value (maximum output threshold value) (BIN 16/32 bits)
S3 : Input value to be controlled by the upper and lower limit control (BIN 16/32 bits)
D : Head number of the devices where the output value controlled by the upper and lower limit control will be
stored (BIN 16/32 bits)

Settng Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S1 ––

S2 ––

S3 ––

D –– ––

Function
LIMIT
(1) Controls the output value to be stored at the device designated by D by checking whether
the input value (BIN 16 bits) designated by S3 is within the range of upper and lower limit
values specified by S1 and S2 or not.
Output value is controlled in the way shown below:
• When S1 Lower limit value S3 Input value .................... S1 Lower limit value D Output value

• When S2 Upper limit value S3 Input value .................... S2 Upper limit value D Output value

• When S1 Lower limit value S3 Input value S2 Upper ......... S3 Input value D Output value
Output value ( D )

Value designated by S2
Value designated Input value( S3 )
by S1

(2) Values in the range from 32768 and 32767 can be designated at S1 , S2 , and S3 .

7-320
 LIMIT(P),DLIMIT(P)

(3) When control based only on upper limit values is performed, the lower limit value designated
at is set at " 32678".
S1
1
(4) When control based only on lower limit values is performed, the upper limit value designated
at S2 is set at "32767".
DLIMIT 2
(1) The function controls the output value to be stored at the device designated by ( D , D +1) by
checking whether the input value (BIN 32 bits) designated by ( S3 , S3 +1) is within the range 3
of upper and lower limit values specified by ( S1 , S1 +1) and ( S2 , S2 +1) or not.
S1 +1 S1
When Lower limit value
S3 +1 S3
Input value
S1 +1 S1
Lower limit value
D +1 D
Output value
4
S2 +1 S2 S3 +1 S3 S2 +1 S2 D +1 D
When Upper limit value Input value Upper limit value Output value
S1 +1 S1 S3 +1 S3 S2 +1 S2 S3 +1 S3 D +1 D 6
When Lower limit value Input value Upper limit value Input value Output value

Output value ( D +1, D ) 6

Value designated by S2 +1, S2
Output value ( S3 +1, S3 ) 7
0

Value designated by S1 +1, S1 8

(2) The values designated by ( S1 , S1 +1), ( S2 , S2 +1), or ( S3 , S3 +1) are within the range of
2147483648 to 2147483647.
(3) To perform controls based only on the upper limit value, set the lower limit value designated

7.13.1 Upper and lower limit controls for BIN 16-bit and BIN 32-bit data (LIMIT(P),DLIMIT(P))
7.13 Data Control Instructions
by ( S1 , S1 +1) to " 2147483648".
(4) To perform controls based only on the lower limit value, set the upper limit value designated
by ( S2 , S2 +1) to "2147483647".

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• The lower limit value designated by S1 is larger than the upper limit value designated by
S2 . (Error code: 4100)

7-321
 LIMIT(P),DLIMIT(P)

Program Example
(1) The following program conducts limit controls from 500 to 5000 on the data set as BCD
values from X20 to X2F, and stores the result at D1 when X0 is turned ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]

• D1 becomes 500 if D0 500.

Example D0 400 D1 500
• D1 becomes the value of D0 when 500 D0 5000.
Example D0 1300 D1 1300
• D1 becomes 5000 when 5000 D0.
Example D0 9600 D1 5000
(2) The following program conducts limit value controls from 10000 to 1000000 on the data set
as BCD values from X20 to X3F when X0 is turned ON.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
• (D11, D10) become 10000 if (D1, D0) are less than 10000.
Example (D1,D0) 400 (D11,D10) 10000
• (D11, D10) become the value of (D1, D0) if 10000 (D1, D0) 1000000.
Example (D1,D0) 345678 (D11,D10) 345678
• (D11, D10) become 1000000 if 1000000 (D1, D0).
Example (D1,D0) 9876543 (D11,D10) 1000000

7-322
 BAND(P),DBAND(P)

7.13.2 BIN 16-bit and 32-bit dead band controls (BAND(P),DBAND(P))

BAND(P),DBAND(P)
1
Basic High
performance Process Redundant Universal LCPU
2

3
indicates an instruction symbol of BAND/DBAND.

Command
BAND,DBAND S1 S2 S3 D
4
Command
P S1 S2 S3 D
BANDP,DBANDP
6
S1 : Lower limit value of dead band (no output band) (BIN 16/32 bits)
S2 : Upper limit value of dead band (no output band) (BIN 16/32 bits) 6
S3 : Input value to be controlled by a dead band control (BIN 16/32 bits)
D : Head number of the devices where the output value controlled by the dead band control will be stored
(BIN 16/32 bits)
7
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S1 ––
8
S2 ––

S3 ––

D –– ––

7.13.2 BIN 16-bit and 32-bit dead band controls (BAND(P),DBAND(P))

7.13 Data Control Instructions
Function
BAND
(1) Controls the output value to be stored at the device designated by D by checking whether
the input value (BIN 16 bits) designated by S3 is within the range of dead band upper and
lower limit values specified by S1 and S2 or not.
Output value is controlled in the way shown below:

• When S1 Lower limit value S3 Input value .......... S3 Input value - S1 Lower D Output value

• When S2 Upper limit value S3 Input value ......... S3 Input value - S2 Upper D Output value

• When S1 Lower limit value S3 Input value S2 Upper ..... 0 D Output value
Output value ( D )
Dead band
lower limit value ( S1 )

Input value ( S2 )
0
Dead band upper
limit value ( S3 )

(2) The values that can be designated by S1 , S2 , and S3 are in the range of from 32768 to
32767.

7-323
 BAND(P),DBAND(P)

(3) The output value stored at D is a signed 16-bit BIN value. Therefore, if the operation results
exceed the range of from 32768 to 32767, the following will take place:

Dead band lower limit value S1 .................10

When :
Input value S3 ............................................ 32768

Output value 32768 10 8000H AH 7FF6H 32758

DBAND

(1) Controls the output value to be stored at the device designated by D by checking whether
the input value (BIN 32 bits) designated by ( S3 , S3 +1) is within the range of dead band upper
and lower limit values specified by ( S1 , S1 +1) and ( S2 , S2 +1) or not.
Output value is controlled in the way shown below:
S1 +1 S1 S3 +1 S3 S3 +1 S3 S1 +1 S1 D +1 D
When Lower limit value Input value Input value Lower limit value Output value
S2 +1 S2 S3 +1 S3 S3 +1 S3 S2 +1 S2 D +1 D
When Upper limit value Input value Input value Upper limit value Output value
S1 +1 S1 S3 +1 S3 S2 +1 S2 D +1 D
When Lower limit value Input value Upper limit value 0 Output value

Output value ( D +1, D )

Dead band lower
limit value ( S1 , S1 +1)

Input value ( S3 , S3 +1)

0
Dead band upper
limit value ( S2 , S2 +1)

(2) The values designated by ( S1 , S1 +1), ( S2 , S2 +1), or ( S3 , S3 +1) are within the range of from
2147483648 to 2147483647.

(3) The output value stored at D , D +1 is a signed 32-bit BIN value. Therefore, if the operation
results exceed the range of from 2147483648 to 2147483647, the following takes place:

Dead band lower limit value ( S1 , S1 +1).....1000

When :
Input value ( S3 , S3 +1) ............................... 2147483648

Output value 2147483648 1000 80000000H 000003E8H

7FFFFC18H 2147482648

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• The lower limit value designated by S1 is greater than the upper limit value designated by
S2 . (Error code: 4100)

7-324
 BAND(P),DBAND(P)

Program Example
1
(1) The following program performs the dead band control by applying the lower and upper
limits of 0 and 1000 for the data set in BCD at X20 to X2F and stores the result of control at
D1 when X0 is turned ON. 2
[Ladder Mode] [List Mode]
Step Instruction Device
3

6
[Operation]

• "0" is stored at D1 if 0 D0 1000.

Example D0 500 D1 0
6
• The value of (D0) 1000 is stored at D1 if 1000 D0.
Example D0 7000 D1 6000 7
(2) The following program performs the dead band control by applying the lower and upper
limits of 10000 and 10000 for the data set at D0 and D1 and stores the result of control at
D10 and D11 when X0 is turned ON 8
[Ladder Mode] [List Mode]
Step Instruction Device

7.13.2 BIN 16-bit and 32-bit dead band controls (BAND(P),DBAND(P))

7.13 Data Control Instructions
[Operation]

• The value (D1, D0) ( 10000) is stored at (D11, D10) if (D1, D0) ( 10000).
Example (D1, D0) 12345 (D11, D10) 2345
• The value 0 is stored at (D11, D10) if 10000 (D1, D0) 10000.
Example (D1, D0) 6789 (D11, D10) 0
• The value (D1, D0) 10000 is stored at (D11, D10) if 10000 (D1, D0).
Example (D1, D0) 50000 (D11, D10) 40000

7-325
 ZONE(P),DZONE(P)

7.13.3 Zone control for BIN 16-bit and BIN 32-bit data
(ZONE(P),DZONE(P))
ZONE(P),DZONE(P)

Basic High
performance Process Redundant Universal LCPU

indicates an instruction symbol of ZONE/DZONE.

Command
ZONE,DZONE S1 S2 S3 D

Command
P S1 S2 S3 D
ZONEP,DZONEP

S1 : Negative bias value to be added to an input value (BIN 16/32 bits)

S2 : Positive bias value to be added to an input value (BIN 16/32 bits)
S3 : Input value used for a zone control (BIN 16/32 bits)
D : Head number of the devices where the output value controlled by the zone control will be stored
(BIN 16/32 bits).

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S1 ––

S2 ––

S3 ––

D –– ––

Function
ZONE

(1) Adds bias value designated by S1 or S2 to input value designated by S3 , and stores at
device number designated by D .
Bias values are calculated in the following manner:

• When S3 Input value 0....... S3 Input value + S1 Negative bias value D Output value

• When S3 Input value 0................................................................... 0 D Output value

• When S3 Input value 0....... S3 Input value + S2 Positive bias value D Output value

Output value ( D )

Positive bias value ( S2 )

Input value ( S3 )
0
Negative bias value ( S1 )

7-326
 ZONE(P),DZONE(P)

(2) The values that can be designated by S1 , S2 , and S3 are in the range of from 32768 to
32767.
1
(3) The output value stored at D is a signed 16-bit BIN value. Therefore, if the operation results
exceed the range of 32768 to 32767, the following will take place:
2
Negative bias value S1 .............................. 100
When :
Input value S3 ............................................ 32768
3
Output value 32768 + ( 100) 8000H + FF9C 7F9CH 32668

DZONE
4
(1) Adds bias value designated by ( S1 , S1 +1) or ( S2 , S2 +1) to input value designated by ( S3 ,
S3 +1), and stores the result at device number designated by ( D , D +1).
Addition of the bias value is performed as follows: 6
S3 +1 S3 S3 +1 S3 S1 +1 S1 D +1 D
When Input value 0 Input value + Negative bias value Output value
S3 +1 S3 D +1 D 6
When Input value 0 0 Output value
S3 +1 S3 S3 +1 S3 S2 +1 S2 D +1 D
When Input value 0 Input value + Positive bias value Output value
7
Output value ( D +1, D )

Positive bias value 8

( S2 , S2 +1)
Input value
0 ( S3 , S3 +1)
Negative bias value
( S1 , S1 +1)

7.13.3 Zone control for BIN 16-bit and BIN 32-bit data (ZONE(P),DZONE(P))
7.13 Data Control Instructions
(2) The values designated by ( S1 , S1 +1), ( S2 , S2 +1), or ( S3 , S3 +1) are within the range of from
2147483648 to 2147483647.

(3) The value stored at ( D , D +1) is a signed 32-bit BIN value.

Therefore, if the operation results exceed the range of from 2147483648 to 2147483647,
the following takes place:

Negative bias value ( S1 , S1 +1).................. 1000

When :
Input value ( S3 , S3 +1) ............................... 2147483648

Output value 2147483648 + ( 1000) 80000000H + FFFFFC18H

7FFFFC18 2147482648.

Operation Error
(1) There are no operation errors associated with the ZONE(P) or DZONE(P) instructions.

7-327
 ZONE(P),DZONE(P)

Program Example
(1) The following program performs zone control by applying negative and positive bias values
of 100 to 100 for the data set at D0 and stores the result of control at D1 when X0 is turned
ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]

• The value (D0) + ( 100) is stored at D1 if D0 0.

Example D0 200 D1 300
• The value 0 is stored at D1 if D0 0.
• The value of (D0) + 100 is stored at D1 if 0 D0.
Example D0 700 D1 800
(2) The following program performs zone control by applying negative and positive bias values
of 10000 to 10000 for the data set at D0 and D1 and stores the result of control at D10 and
D11 when X1 is turned ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]

• The value (D1, D0) + ( 10000) is stored at (D11, D10) if (D1, D0) 0.
Example (D1,D0) 12345 (D11,D10) 22345
• The value 0 is stored at (D11, D10) if (D1, D0) 0.
• The value (D1, D0) + 10000 is stored at (D11, D10) if 0 (D1, D0).
Example (D1,D0) 50000 (D11,D10) 60000

7-328
 (SCL(P),DSCL(P))

7.13.4 Scaling (Point-by-point coordinate data) (SCL(P),DSCL(P))

(SCL(P),DSCL(P))
1
Ver.
High
Basic Process Redundant Universal LCPU
2
performance

QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later.

QnUDE(H)CPU: The serial number (first five digits) is "10102" or later.

3
indicates an instruction symbol of SCL/DSCL.

SCL/DSCL
Command
4
S1 S2 D
Command
SCLP/DSCLP P S1 S2 D 6

S1 : Input values for scaling or head number of the device where input values are stored(BIN 16/32 bits)
6
S2 : Head number of the devices where scaling conversion data are stored(BIN 16/32 bits)
D : Head number of the devices where output values depending on scaling are stored(BIN 16/32 bits).

Setting Internal Devices

R, ZR
J \
U \G Zn
Constants
Other
7
Data Bit Word Bit Word K, H

S1 –– ––

S2 –– –– –– –– 8
D –– –– ––

Function

7.13.4 Scaling (Point-by-point coordinate data) (SCL(P),DSCL(P))

7.13 Data Control Instructions
SCL(P)
(1) This instruction executes scaling for the scaling conversion data (16-bit data units) specified
by S2 with the input value specified by S1 , and then stores the operation result into the
devices specified by D .
The scaling conversion is executed based on the scaling conversion data stored in the
device specified by S2 and up.
Scaling conversion data component Y
Setting item Device assignment
Number of coordinate points S2

X coordinate S2 ＋1 Point 2
Point 1 Output Point 3
Y coordinate S2 ＋2 value： D

X coordinate S2 ＋3
Point 2 Point n
Y coordinate S2 ＋4

Point 1

Point n−1
X coordinate S2 ＋2n−1
X
Point n Input value： S1
Y coordinate S2 ＋2n
Operation error Operable range Operation error
※n indicates the number of coordinates
specified by (S2).

(2) If the value does not result in an integer, this instruction rounds the value to the whole
number.
(3) Set the X coordinate of the scaling conversion data in ascending order.

(4) Set the input value S1 within the range of the scaling conversion data (within the range of S2
devices).

7-329
 (SCL(P),DSCL(P))

(5) If some specified points have same X coordinates, the Y coordinate data of the highest point
number will be output.
(6) Specify the number of coordinate points of scaling conversion data from 1 to 32767.
DSCL(P)
(1) This instruction executes scaling for the scaling conversion data (32-bit data units) specified
by S2 with the input value specified S1 , and then stores the operation result into the devices
specified by D .
The scaling conversion is executed based on the scaling conversion data stored in the
device specified by S2 and up.
Scaling conversion data component
Setting item Device assignment
Y
Number of coordinate points S2 ＋1 ，S2

X coordinate S2 ＋3 ，S2 ＋2 Operation Operable range Operation error

Point 1 error
Y coordinate S2 ＋5 ，S2 ＋4 Input value： S1
X
X coordinate S2 ＋7 ，S2 ＋6
Point 2 Point n−1
Y coordinate S2 ＋9 ，S2 ＋8

Output D Point n
X coordinate value：
S2 ＋4n−1 ， S2 ＋4n−2
Point n Point 1
Y coordinate S2 ＋4n＋1 ， S2 ＋4n
Point 2
※n indicates the number of coordinates
specified by (S2).

(2) If the value does not result in an integer, this instruction rounds the value to the whole
number.
(3) Set the X coordinate of the scaling conversion data in ascending order.

(4) Set the input value S1 within the range of the scaling conversion data (within the range of S2

and S2 +1 devices).
(5) If some specified points have same X coordinates, the Y coordinate data of the highest point
number will be output.
(6) Specify the number of coordinate points of scaling conversion data from 1 to 32767.

7-330
 (SCL(P),DSCL(P))

(1) There are two searching methods that depend on whether SM750 is on or off. 1
SM750 Searching method Range of number of searches

OFF Sequential search 1 Number of times 32767

2
ON Binary search 1 Number of times 15

(2) When the scaling conversion data are set in ascending order, the searching
methods change from one to the other depending on the SM750 status.
3
Therefore, the processing speed also changes. The number of searches
determines the processing speed. Fewer number of serches make the
processing run faster.
4
(a) If the data processing speed with the sequential search rises:
If the number of coordinates is highest and the input value S1 is within
6
the coordinate range from 1 to 15 point, the number of sequential
searches will be 15 or smaller. Therefore, the data processing speed with
the sequential search will rise.
(b) If the data processing speed with the binary search rises:
6
f the maximum number of searches is 15 and the input value S1 is out of
the coordinate range, 16 or over, the number of binary searches will be 7
equal to the number of sequential numbers or smaller. Therefore, the
data processing speed with the binary search will rise.
Number of coordinate points=32767 Number of sequential searches=32767
Number of binary searches=15
8
The processing speed with binary search
rises since the number of binary searches is
smaller than the number of sequential searches.

7.13.4 Scaling (Point-by-point coordinate data) (SCL(P),DSCL(P))

7.13 Data Control Instructions
S1 S1
Number of sequential searches=1
Number of binary searches=15

The processing speed with sequential searches

rises since the number of binary searches is
larger than the number of sequential searches.

7-331
 (SCL(P),DSCL(P))

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an
error code is stored into SD0.
• The X coordinates of the scaling conversion data positioned before the point specified by
S1 are not set in ascending order. (However, this error is not detected when SM750 is on.)
(Error code: 4100)

• The input value specified by S1 is out of the range of the scaling conversion data set.
(Error code: 4100)

• The number of X and Y coordinates of the device specified by S2 is out of the range from
1 to 32767. (Error code: 4100)

• The number of X and Y coordinates of the device specified by S2 is out of the specified
range. (Error code: 4101)

Program Example
(1) The following program executes scaling for the scaling conversion data of which the devices
specified at D100 and up are set with the input value specified at D0, and then outputs the
data at D20.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]

Scaling conversion data component

Setting item Device Setting contents
Number of coordinate points D100 K5 Y

X coordinate D101 K5
Point 1
Y coordinate D102 K13
Point 2
X coordinate D103 K10
Point 2 Point 1 （10，15） Point 3
Y coordinate D104 K15 （5，13） （17，13）

X coordinate D105 K17 D20＝11

Point 3 （Output value） Point 4
Y coordinate D106 K13 （20，8）
Point 5
X coordinate D107 K20 （25，4）
Point 4
Y coordinate D108 K8

X coordinate D109 K25 X

Point 5 D0＝18
Y coordinate D110 K22 （Output value）

7-332
 SCL2,DSCL2

7.13.5 Scaling (Point-by-point coordinate data)

(SCL2(P),DSCL2(P)) 1
SCL2,DSCL2

High
Ver. 2
Basic performance Process Redundant Universal LCPU

QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later.

QnUDE(H)CPU: The serial number (first five digits) is "10102" or later. 3

indicates an instruction symbol of SCL2/DSCL2. 4

Command
SCL2/DSCL2 S1 S2 D
Command 6
SCL2P/DSCL2P P S1 S2 D

6
S1 : Input values for scaling or head number of the device where input values are stored(BIN 16/32 bits)
S2 : Head number of the devices where scaling conversion data are stored(BIN 16/32 bits)
D : Head number of the devices where output values depending on scaling are stored(BIN 16/32 bits). 7
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S1 –– –– 8
S2 –– –– –– ––

D –– –– ––

7.13.5 Scaling (Point-by-point coordinate data) (SCL2(P),DSCL2(P))

7.13 Data Control Instructions
Function
SCL2(P)
(1) This instruction executes scaling for the scaling conversion data (16-bit data units) specified
by S2 with the input value specified by S1 , and then stores the operation result into the
devices specified by D .
The scaling conversion is executed based on the scaling conversion data stored in the
device specified by S2 and up.
Scaling conversion data component Y
Setting item Device assignment
Number of coordinate points S2

Point 1 S2 ＋1
Point 2
S2 Output Point 3
Point 2 ＋2
D Point n−1
X coordinate value：
Point n
Point n S2 ＋n

Point 1
Point 1 S2 ＋n＋1

Point 2 S2 ＋n＋2
Y coordinate X
Input value： S1
Point n S2 ＋2n Operation error Operable range Operation error
※n indicates the number of coordinates
specified by (S2).

(2) If the value does not result in an integer, this instruction rounds the value to the whole
number.
(3) Set the X coordinate of the scaling conversion data in ascending order.

7-333
 SCL2,DSCL2

(4) Set the input value S1 within the range of the scaling conversion data (within the range of S2
devices).
(5) If some specified points have same X coordinates, the Y coordinate data of the highest point
number will be output.
DSCL2(P)
(1) This instruction executes scaling for the scaling conversion data (32-bit data units) specified
by S2 with the input value specified S1 , and then stores the operation result into the devices
specified by D .
The scaling conversion is executed based on the scaling conversion data stored in the
device specified by S2 and up.
Scaling conversion data component
Setting item Device assignment
Y
Number of coordinate points S2 ＋1 ， S2

Point 1 S2 ＋3 ， S2 ＋2
Operation Operable range Operation error
error
Point 2 S2 ＋5 ， S2 ＋4 Input value： S1
X coordinate X

Point n−1
Point n S2 ＋2n＋1 ， S2 ＋2n

Point 1 S2 ＋2n＋3 ， S2 ＋2n＋2

Output D Point n
Point 2 S2 ＋2n＋5 ， S2 ＋2n＋4
value：
Y coordinate
Point 1
Point n S2 ＋4n＋1 ， S2 ＋4n Point 2
※n indicates the number of coordinates
specified by (S2).

(2) If the value does not result in an integer, this instruction rounds the value to the whole
number.
(3) Set the X coordinate of the scaling conversion data in ascending order.

(4) Set the input value S1 within the range of the scaling conversion data (within the range of S2

and S2 +1 devices).
(5) If some specified points have same X coordinates, the Y coordinate data of the highest point
number will be output.
(6) Specify the number of coordinate points of scaling conversion data from 1 to 32767.

When the coordinates of the scaling conversion data are set in ascending order,
the searching methods change from one to the other depending on the SM750
status. Therefore, the processing speed also change. The number of searches
determines the processing speed. Fewer number of searches make the
processing run faster.
For details, refer to Section 7.13.4.

7-334
 SCL2,DSCL2

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an
error code is stored into SD0.
• The X coordinates are not set in ascending order. (Error code: 4100) 2
• The input value specified by S1 is out of the range of the scaling conversion data set.
(Error code: 4100)
3
• The number of X and Y coordinates of the device specified by S2 is out of the range from
1 to 32767. (Error code: 4100)

• The number of X and Y coordinates of the device specified by S2 is out of the specified 4
range. (Error code: 4101)

Program Example 6
(1) The following program executes scaling for the scaling conversion data of which the devices
specified at D110 and up are set with the input value specified at D0, and then outputs the 6
data at D200.
[Ladder Mode] [List Mode]
Step Instruction Device 7

8
[Operation]

Scaling conversion data component

Setting item Device Setting contents

7.13.5 Scaling (Point-by-point coordinate data) (SCL2(P),DSCL2(P))

7.13 Data Control Instructions
Number of coordinate points D110 K5 Y
Point 1 D111 K7

Point 2 D112 K13 D0=11

X coordinate (Input value)
Point 3 D113 K15 X

Point 4 D114 K18 Point 2

(13, -7) Point 4
Point 5 D115 K20
(18, -11)
Point 1 D116 K-14 D200=-9 Point 3
Y coordinate (15, -9)
(Output value) Point 5
Point 2 D117 K-7 (20, -13)
Point 3 D118 K-15 Point 1
(7, -14)
Point 4 D119 K-11

Point 5 D120 K-18

7-335
 RSET(P)

7.14 File register switching instructions

7.14.1 Switching file register numbers (RSET(P))

RSET(P)

Ver.
Basic High
performance Process Redundant Universal LCPU

Universal model QCPU: Other than Q00UJCPU

Command
RSET RSET S

Command
RSETP S
RSETP

S : Block number data used to change the block number or the number of the device where the block number
data is stored (BIN 16 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S ––

Function
(1) Changes the file register block number used in the program to the block number stored in
the device designated at S .
Following the block number change, all file registers used in the sequence program are
processed to the file register of the block number after the change.
Example
When switching block number from block No. 0 to block No. 1
Processing executed to file registers

S Setting of a
block number

R0 Block 0 R0 Block 1 R0 Block n

File register

R32767
(
Presently
used file
register
) (
used after the
execution of
RSET
R32767 instruction
) R32767

When a file register (R) is refreshed and the block No. of the file register is
switched with the RSET instruction, follow restrictions.
For the restrictions on file registers, refer to Section 3.10.

7-336
 RSET(P)

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The block number designated by S does not exist. (Error code: 4100)
2
• There is no file register for the specified block No. (Error code: 4101)
3
Program Example
4
(1) The following program compares R0 of block No. 0 and block No. 1.
[Ladder Mode]
6
Designates block No. 0

Executes reading R0 of block No.0

6
Designates block No. 1

Executes reading R0 of block No.1

7
Compares the read values
8

7.14.1 Switching file register numbers (RSET(P))

7.14 File register switching instructions
[List Mode]

Step Instruction Device

[Operation]
Block No. 0 Block No. 1
R0 -3216 756 R0
R1 5001 9330 R1
R2 128 D0 D1 -1762 R2
R3 -7981 -3216 756 3911 R3
R4 9610 -5 R4
R5 0 -3781 R5
Y41 turns ON since D0<D1

7-337
 QDRSET(P)

7.14.2 Setting files for file register use (QDRSET(P))

QDRSET(P)

Ver.
High
Basic performance Process Redundant Universal LCPU

Universal model QCPU: Other than Q00UJCPU

Command
QDRSET QDRSET S

Command
QDRSETP S
QDRSETP

S : Character string data of the drive No./file name in which the file register is set, or head number of the devices
where the character string data is stored (character string)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word $

S –– –– ––

Function
(1) Changes the file register file name used in the program to the file name being stored at the
device designated by S .
After the file names have been changed, all the file registers being used by the sequence
program process the file register of the block No. 0 of the renamed file.
Block number switches are performed by the RSET instruction.

Example
When switching from Drive No. 1/File name B to Drive No. 3/File name A

Processing executed to file registers

Setting of a drive number
S and file name

Drive 1 Drive 1 Drive 1 Drive 2 Drive 3 Drive 4

File name File name File name File name File name File name
A B C A A A
File name of file
(
File name of
the presently )
used file register
( register used after
the execution of
QDRSET instruction
)

7-338
 QDRSET(P)

(2) Drive number can be designated from 1 to 4.

(The drive number cannot be designated as drive 0 (program memory/internal memory).)
Note that available drives vary depending on the CPU module used.
1
Refer to the manual of the CPU module and check the drives that can be specified.
(3) It is not necessary to designate the extension (.QDR) with the file name. 2
(4) A file name setting can be deleted by designating the NULL character (00H) for the file
name.
(5) File names designated with this instruction will be given priority even if a drive number and 3
file name have been designated in the parameters.

4
1. If the file name is changed with the QDRSET instruction, the file name returns
to the name specified by the parameter when the CPU module is switched from
STOP to RUN. To maintain the file name even after the CPU mode is changed 6
from STOP to RUN, execute the QDRSET instruction with the SM402 special
relay, which turns ON during one scan when the CPU enters from STOP to
RUN mode. 6
2. For refreshing a file register, do not change the file name of the file register with
the QDRSET instruction. For restrictions on file registers, refer to Section 3.10.
7
Operation Error
8
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• File name does not exist at the drive number designated by S . (Error code: 2410)

7.14.2 Setting files for file register use (QDRSET(P))

7.14 File register switching instructions

7-339
 QDRSET(P)

Program Example
(1) The following program compares R0 of ABC in block No. 1 and R0 of DEF in block No. 1.
[Ladder Mode]

[List Mode]
Step Instruction Device

[Operation]
Block No. 0 Block No. 1
R0 -3216 756 R0
R1 5001 9330 R1
R2 128 D0 D1 -1762 R2
R3 -7981 -3216 756 3911 R3
R4 9610 -5 R4
R5 0 -3781 R5
Y41 turns ON since D0<D1

7-340
 QCDSET(P)

7.14.3 File setting for comments (QCDSET(P))

QCDSET(P)
1
High
2
Basic performance Process Redundant Universal LCPU

3
Command
QCDSET QCDSET S

Command 4
QCDSETP S
QCDSETP

6
S : Character string data of the drive No./file name in which the comment file is set, or head number of the
devices where the character string data is stored (character string)

Setting
Data
Internal Devices
Bit Word
R, ZR
Bit
J \
Word
U \G Zn
Constants
$
Other 6
S –– –– ––

7
Function
(1) Changes the file register file name used in the program to the file name being stored at the
8
device designated by S .
After the file name change, comment data being used by the sequence program perform
processing in relation to the comment data of the file name after the change.

7.14.3 File setting for comments (QCDSET(P))

7.14 File register switching instructions
Example
When switching from Drive No. 1/File name B to Drive No. 3/File name A

Processing executed to file registers

Setting of a drive number
S and file name

Drive 1 Drive 1 Drive 1 Drive 2 Drive 3 Drive 4

File name File name File name File name File name File name
A B C A A A
File name of file
(presently used
comment file )
File name of the
( register used after
the execution of
QCDSET instruction
)
(2) Drive number can be designated from 1 to 4.
(The drive number cannot be designated as drive 0 (program memory/internal memory).)
Note that available drives vary depending on the CPU module used.
Refer to the manual of the CPU module and check the drives that can be specified.
(3) It is not necessary to designate the extension (.QCD) with the file name.

7-341
 QCDSET(P)

(4) A file name setting can be deleted by designating the NULL character (00H) for the file
name.
(5) File names designated with this instruction will be given priority even if a drive number and
file name have been designated in the parameters.

If the file name is changed with the QCDSET instruction, the file name returns to
the name specified by the parameter when the CPU module is switched from
STOP to RUN.
To maintain the file name even after the CPU mode is changed from STOP to
RUN, execute the QCDSET instruction with the SM402 special relay, which turns
ON during one scan when the CPU enters from STOP to RUN mode.

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• File name does not exist at the drive number designated by S . (Error code: 2410)

Program Example
(1) The following program switches object file to file name ABC. QCD at drive No. 0 when X0 is
ON, and to DEF. QCD at drive No. 1 when X1 is ON.
[Ladder Mode]

Switches to ABC at drive No. 1

Switches to DEF at drive No. 3

[List Mode]
Step Instruction Device

Caution
(1) This instruction will not be executed even when the execution command of this instruction is
ON while SM721 (file access in execution) is ON for the Universal model QCPU and LCPU.
Execute this instruction when SM721 is OFF.

7-342
 DATERD(P)

7.15 Clock instructions

1
7.15.1 Reading clock data (DATERD(P))
DATERD(P)
2
Basic High
Process Redundant Universal LCPU
3
performance

4
Command
DATERD DATERD D

Command 6
DATERDP D
DATERDP

6
D : Head number of the devices where the read clock data will be stored (BIN 16 bits)

Setting Internal Devices J \

Data Bit Word
R, ZR
Bit Word
U \G Zn Constants Other
7
D –– ––

8
Function
(1) Reads "year, month, day, hour, minute, second, and day of week" from the clock element of
the CPU module and stores it as BIN value to the device designated by D or later device.

7.15.1 Reading clock data (DATERD(P))

7.15 Clock instructions
D Year (1980 to 2079)
D +1 Month (1 to 12)
D +2 Day (1 to 31)
Clock element D +3 Hour (24-hour clock) (0 to 23)
D +4 Minute (0 to 59)
D +5 Second (0 to 59)
D +6 Day of week (0 to 6)

(2) The "year" at D is stored as 4-digit year indication.

(3) The "day of week" at D +6 is stored as 0 to 6 to represent the days Sunday to Saturday.
Day of week Sun Mon Tue Wed Thu Fri Sat
Stored data 0 1 2 3 4 5 6

(4) Compensation is made automatically for leap years.

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• The device specified by D exceeds the range of the corresponding device.
(For the Universal model QCPU, LCPU.) (Error code: 4101)

7-343
 DATERD(P)

Program Example
(1) The following program outputs the following clock data as BCD values:
Year ..........Y70 to Y7F
Month........Y68 to Y6F
Day ...........Y60 to Y67
Hour..........Y58 to Y5F
Minute.......Y50 to Y57
Second .....Y48 to Y4F
Week ........Y44 to Y47

[Ladder Mode]

Outputs "Year"

Outputs "Month"

Outputs "Day"

Outputs "Hour"

Outputs "Minute"

Outputs "Second "

Outputs "Day of week"

[List Mode]
Step Instruction Device

[Operation]
BCD Y7F Y70
2 0 0 5 (Year)

D0 2005
Y6F Y68 Y67 Y60
D1 12
1 2 2 4 (Month, Day)
Clock data D2 24
2005, 12, 24, 12:57:39, Sunday D3 12
Y5F Y58 Y57 Y50
D4 57
1 2 5 7 (Hour, Minute)
D5 39
D6 0
Y4F Y48 Y47 Y44
BIN 3 9 0 (Second, Day of week)

7-344
 DATEWR(P)

7.15.2 Writing clock data (DATEWR(P))

DATEWR(P)
1
Basic High
performance Process Redundant Universal LCPU
2

Command
3
DATEWR DATEWR S

Command
DATEWRP S
4
DATEWRP

S : Head number of the devices where clock data to be written into the clock device is stored (BIN 16 bits) 6
Setting Internal Devices J \
R, ZR U \G Zn Constants Other
Data Bit Word Bit Word

S –– –– 6

Function 7
(1) Writes clock data stored in the device number designated by S or later device number to
the clock element of the CPU module. 8
S Year
S +1 Month
S +2 Day
S +3 Hour Clock element

7.15.2 Writing clock data (DATEWR(P))

7.15 Clock instructions
S +4 Minute
S +5 Second
S +6 Day of week

(2) Each item is set as a BIN value.

(3) The "year" at S is designated by using four-digit year indication between 1980 to 2079.

(4) S +1 designates the "month" in values of from 1 to 12 (January to December).

(5) S +2 designates the "day" in values of from 1 to 31.

(6) S +3 designates the "hour" in values of from 0 to 23 (using 24-hour clock, from 0 hours to 23
hundred hours). (Uses the 24-hour clock.)

(7) S +4 designates the "minute" in values of from 0 to 59.

(8) S +5 designates the "second" in values of from 0 to 59.

(9) S +6 designates the "day of week" in values of from 0 to 6 (Sunday to Saturday).

Day of week Sun Mon Tue Wed Thu Fri Sat
Stored data 0 1 2 3 4 5 6

7-345
 DATEWR(P)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• Individual items of data have been set outside the setting range.
(Error code: 4100)

• The device specified by S exceeds the range of the corresponding device.

(For the Universal model QCPU, LCPU.) (Error code: 4101)

Program Example
(1) The following program writes the following clock data to the clock element as BCD values
when X40 is turned ON.
Year ............... X30 to X3F Hour................. X18 to X1F
Month............. X28 to X2F Minute.............. X10 to X17
Day ................ X20 to X27 Second ............ X8 to XF
Week ............. X4 to X7
[Ladder Mode]

Sets "Year"

Sets "Month"

Sets "Day"

Sets "Hour"

Sets "Minute"

Sets "Second "

Sets "Day of week"

Writes the clock data (D0 to D6)

to the clock element

[List Mode]
Step Instruction Device

[Operation]
X3F X38 X37 X30 BIN
(Year) 2 0 0 0

D0 2000
X2F X28 X27 X20
D1 12
(Month, Day) 1 2 2 4
D2 24 Clock data
D3 12 2000, 12, 24 12:57:39 Sunday
X1F X18 X17 X10
D4 57
(Hour, Minute) 1 2 5 7
D5 39
D6 0
XF X8 X7 X4
(Second, Day of week) 3 9 0 BIN

7-346
 DATE+(P)

7.15.3 Clock data addition operation (DATE+(P))

DATE+(P)
1
Basic High
performance Process Redundant Universal LCPU
2

3
Command
DATE+ DATE+ S1 S2 D

Command 4
DATE+P S1 S2 D
DATE+P

S1 : Head number of the devices where the clock data to be adjusted by addition is stored (BIN 16 bits)
6
S2 : Head number of the devices where the time data to be added for adjustment is stored (BIN 16 bits)
D : Head number of the devices where the result of addition of clock (time) data will be stored (BIN 16 bits)
6
Setting Internal Devices J \
R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
S1 –– ––
7
S2 –– ––

D –– ––
8
Function
(1) Adds the time data designated by to the clock data designated by , and stores the

7.15.3 Clock data addition operation (DATE+(P))

7.15 Clock instructions
S2 S1

result into the area starting from the device designated by D .

Data range Data range Data range
S1 Hour (0 to 23) S2 Hour (0 to 23) D Hour (0 to 23)
S1 +1 Minute (0 to 59) + S2 +1 Minute (0 to 59) D +1 Minute (0 to 59)
S1 +2 Second (0 to 59) S2 +2 Second (0 to 59) D +2 Second (0 to 59)

For example, adding the time 7:48:10 to 6:32:40 would result in the following operation:
S1 Hour: 6 S2 Hour: 7 D Hour: 14
S1 +1 Minute: 32 + S2 +1 Minute: 48 D +1 Minute: 20
S1 +2 Second: 40 S2 +2 Second: 10 D +2 Second: 50

(2) If the results of the addition of time exceed 24 hours, 24 hours will be subtracted from the
sum to make the final operation result.
For example, if the time 20:20:20 were added to 14:20:30, the result would not be 34:40:50,
but would instead be 10:40:50.
S1 Hour: 14 S2 Hour: 20 D Hour: 10
S1 +1 Minute: 20 + S2 +1 Minute: 20 D +1 Minute: 40
S1 +2 Second: 30 S2 +2 Second: 20 D +2 Second: 50

Remark
See 7.15.2 for further information regarding the data that can be set for hours,
minutes, and seconds.

7-347
 DATE+(P)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The data set by S1 and S2 is outside the setting range. (Error code: 4100)

• The device specified by S1 or S2 or D exceeds the range of the corresponding device.

(For the Universal model QCPU, LCPU.) (Error code: 4101)

Program Example

(1) The following program adds 1 hour to the clock data read from the clock element, and stores
the results in the area starting from D100 when X20 is ON.
[Ladder Mode]

Reads data in the clock element to D0 or later

Sets the time to D0 or later

[List Mode]
Step Instruction Device

[Operation]
• Time data read operation triggered by DATERDP instruction.
Clock element D0 95 Year
D1 5 Month
D2 15 Day
D3 10 Hour
D4 23 Minute Time data
D5 41 Second
D6 2 Day of week

• Addition triggered by DATE+P instruction.

D3 Hour: 10 D10 Hour: 1 D100 Hour: 11
D4 Minute: 23 + D11 Minute: 0 D101 Minute: 23
D5 Second: 41 D12 Second: 0 D102 Second: 41

7-348
 DATE-(P)

7.15.4 Clock data subtraction operation (DATE-(P))

DATE-(P)
1
Basic High
performance Process Redundant Universal LCPU
2

3
Command
DATE- DATE- S1 S2 D

Command 4
DATE-P DATE-P S1 S2 D

6
S1 : Head number of the devices where the clock time data to be adjusted by substraction is stored (BIN 16 bits)
S2 : Head number of the devices where time data to be subtracted for adjustment is stored (BIN 16 bits)
D : Head number of the devices where the result of subtraction of clock (time) data will be stored (BIN 16 bits) 6
Setting Internal Devices J \
R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
S1 –– –– 7
S2 –– ––

–– ––
8
D

Function

7.15.4 Clock data subtraction operation (DATE-(P))

7.15 Clock instructions
(1) Subtracts the time data designated by S2 from the clock data designated by S1 , and stores
the result into the area starting from the device designated by D .
Data range Data range Data range
S1 Hour (0 to 23) S2 Hour (0 to 23) D Hour (0 to 23)
S1 +1 Minute (0 to 59) S2 +1 Minute (0 to 59) D +1 Minute (0 to 59)
S1 +2 Second (0 to 59) S2 +2 Second (0 to 59) D +2 Second (0 to 59)

For example, if the clock time 3:50:10 were subtracted from the clock time 10:40:20, the
operation would be performed as follows:
S1 Hour: 10 S2 Hour: 3 D Hour: 6
S1 +1 Minute: 40 S2 +1 Minute: 50 D +1 Minute: 50
S1 +2 Second: 20 S2 +2 Second: 10 D +2 Second: 10

(2) If the subtraction results in a negative number, 24 will be added to the result to make a final
operation result.
For example, if the clock time 10:42:12 were subtracted from 4:50:32, the result would not
be 6:8:20, but rather would be 18:8:20.
S1 Hour: 4 S2 Hour: 10 D Hour: 18
S1 +1 Minute: 50 S2 +1 Minute: 42 D +1 Minute: 8
S1 +2 Second: 32 S2 +2 Second: 12 D +2 Second: 20

Remark
See 7.15.2 for further information regarding the data that can be set for hours,
minutes, and seconds.

7-349
 DATE-(P)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The data set by S1 and S2 is outside the setting range. (Error code: 4100)

• The device specified by S1 or S2 or D exceeds the range of the corresponding device.

(For the Universal model QCPU, LCPU.) (Error code: 4101)

Program Example
(1) The following program subtracts the time data stored in devices starting from D10 from the
clock data read from the clock element when X1C is turned ON, and stores the result at
devices starting from R10.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
• Time data read operation triggered by DATERDP instruction.
Clock device D100 95 Year
D101 4 Month
D102 20 Day
D103 3 Hour
D104 21 Minute Time data
D105 20 Second
D106 1 Day of week

• Subtraction as triggered by DATE-P instruction (when 10 hours, 40 minutes, and 10

seconds have been designated by D10 to D12).
D103 Hour: 3 D10 Hour: 10 R10 Hour: 16
D104 Minute: 21 D11 Minute: 40 R11 Minute: 41
D105 Second: 20 D12 Second: 10 R12 Second: 10

3:21:20 - 10:40:10 -8:41:10 16:41:10

24 is added to this value

7-350
 SECOND(P)

7.15.5 Time data conversion (from Hour/Minute/Second to Second)

(SECOND(P)) 1
SECOND(P)

Basic High
performance Process Redundant Universal LCPU
2

SECOND
Command 4
SECOND S D

Command
SECONDP SECONDP S D 6

S : Head number of the devices where the clock data before conversion is stored (BIN 16 bits) 6
D : Head number of the devices where the clock data after conversion will be stored (BIN 32 bits)

Setting Internal Devices J \

Data Bit Word
R, ZR
Bit Word
U \G Zn Constants Other
7
S –– –– ––

D ––
8

Function
(1) Converts the time data stored in the area starting from the device designated by to

7.15.5 Time data conversion (from Hour/Minute/Second to Second) (SECOND(P))

7.15 Clock instructions
S

seconds and stores the conversion result into the device designated by D .
Data range
D +1 D
S Hour (0 to 23)
S +1 Minute (0 to 59) Second
S +2 Second (0 to 59)

For example, if the value were 4 hours, 29 minutes, and 31 seconds, the conversion would
be made as follows:
D 1 D
S 4
S +1 29 16171
S +2 31

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The data set by S and is outside the setting range. (Error code: 4100)

• The device specified by S exceeds the range of the corresponding device.

(For the Universal model QCPU, LCPU.) (Error code: 4101)

7-351
 SECOND(P)

Program Example
(1) The following program converts the clock time data read from the clock element into second
when X20 is turned ON, and stores the result at D100 and D101.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
• Time data read operation triggered by DATERDP instruction.
Clock device D10 95 Year
D11 4 Month
D12 20 Day
D13 20 Hour
D14 21 Minute Time data
D15 23 Second
D16 5 Day of week

• Conversion to seconds as triggered by the SECONDP instruction.

D13 20
D14 21 D101,D100 73283
D15 23

7-352
 HOUR(P)

7.15.6 Time data conversion (from Second to Hour/Minute/Second)

(HOUR(P)) 1
HOUR(P)

Basic High
performance Process Redundant Universal LCPU
2

HOUR
Command 4
HOUR S D

Command
HOURP HOURP S D 6

S : Head number of the devices where clock data before conversion is stored (BIN 32 bits) 6
D : Head number of the devices where the clock data after conversion will be stored (BIN 16 bits)

Setting Internal Devices J \ Constants

Data Bit Word
R, ZR
Bit Word
U \G Zn
K, H
Other
7
S ––

–– –– –– ––
8
D

Function
(1) Converts the data in seconds stored in the device number designated by S to an hour/

7.15.6 Time data conversion (from Second to Hour/Minute/Second) (HOUR(P))

7.15 Clock instructions
minute/second format, and stores the conversion result into the area starting from the device
designated by D .
Data range Data range
S 1 S
D Hour (0 to 23)
Second (0 to 86399) D +1 Minute (0 to 59)
D +2 Second (0 to 59)
For example, if 45325 seconds were the value designated, the conversion operation would
be conducted as follows:
S +1 S
D 12
45325 D +1 35
D +2 25

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The data set by S and is outside the setting range. (Error code: 4100)

• The device specified by D exceeds the range of the corresponding device.

(For the Universal model QCPU, LCPU.) (Error code: 4101)

7-353
 HOUR(P)

Program Example
(1) The following program converts the seconds stored at D0 and D1 into an hour, minute,
second format, and stores the result at devices starting from D100 when X20 is turned ON.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
• Conversion to hour minute, and second format by the HOURP instruction (when the value
40000 seconds has been designated by D1 and D0).
D100 11
D1,D0 40000 D101 6
D102 40

7-354
 (DT=,DT<>,DT>,DT<=,DT<,DT>=)

7.15.7 Date comparison (DT=,DT<>,DT>,DT<=,DT<,DT>=)

(DT=,DT<>,DT>,DT<=,DT<,DT>=)
1
Ver.
High
2
Basic performance Process Redundant Universal LCPU

QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later.

QnUDE(H)CPU: The serial number (first five digits) is "10102" or later.

3
indicates an instruction symbol of DT=/DT<>/DT</DT<=/DT>/DT>=.

LD n 4
Command
AND n

Command
6
OR
n 6
S1 : Head number of the devices where the data to be compared are stored (BIN 16 bits)

S2 : Head number of the devices where the data to be compared are stored (BIN 16 bits) 7
n : Value of the data to be compared or the number of the stored data to be compared (BIN 16 bits)

Setting Internal Devices J \ Constants

Data Bit Word
R, ZR
Bit Word
U \G Zn
K, H
Other
8
S1 –– –– –– ––

S2 –– –– –– ––

n –– ––

7.15.7 Date comparison (DT=,DT<>,DT>,DT<=,DT<,DT>=)

7.15 Clock instructions
Function
(1) This instruction compares the date data specified by S1 with those specified by S2 , or the
date data specified by S1 with current date data. Setting n can determine the data to be
compared.
(a) Comparison of given date data

• This instruction treats the date data specified by S1 and S2 as a normally open
contact, and then compares the data in accordance with the value of n.
Data range Data range
S1 Year （1980∼2079） S2 Year （1980∼2079）
Comparison Comparison
S1 ＋1 Month （1∼12） S2 ＋1 Month （1∼12）
operator operation result
S1 ＋2 Day （1∼31） S2 ＋2 Day （1∼31）

(b) Comparison of current date data

• This instruction treats the date data specified by S1 and the current date data as a
normally open contact, and then compares the data in accordance with the value of
n.

• Time data specified by S2 is treated as dummy data, and is ignored.

Data range
S1 Year (1980 to 2079)
Comparison Comparison
S1 +1 Month (1 to 12) Current date
operator operation result
S1 +2 Day (1 to 31)

7-355
 (DT=,DT<>,DT>,DT<=,DT<,DT>=)

When either S1 or S2 corresponds to any of the following in comparing given or

current date data with given date data, the operation error (error code: 4101) or a
malfunction may occurs.
• The range of the devices to be used for the index modification is specified over
the range of the device specified by S1 or S2 .
• File registers are specified by S1 or S2 without a register set.

(2) This instruction sets BIN values for each item.

(3) This instruction sets the year of four digits selected from 1980 to 2079 with the BIN value
specified by S1 or S2 .
(4) This instruction sets the month selected from 1 to 12 (January to December) with the BIN
value specified by S1 +1 or S2 +1.
(5) This instruction sets the day selected from 1 to 31 (1st to 31st) for with the BIN value
specified by S1 +2 or S2 +2.
(6) This instruction specifies the following values at n so that the data to be compared can be
specified.
The bit configuration specified at n is as follows.
This instruction specifies 0 at bits from 3rd to 14th.
The instruction will be non-conductive status without
specifying 0 regardless of the operation result.

b15 b14 b3 b2 b1 b0
0/1 0 0/1 0/1 0/1

Day
If this instruction specifies 1 (on) at 15th bit, the Month
instruction compares S1 with the current date in
accordance with the bit condition specified at 0 to 2nd Year
bit.

(a) Date data to be compared (from 0 to 2nd bit)

• 0: Does not compare specified date data (year/month/day).
• 1: Compares specified date data (year/month/day).

(b) Operation data to be compared (15th bit)

• 0: Compares the date data specified by S1 with the date data specified by S2 .

• 1: Compares the date data specified by S1 with the current date data.

• Ignores the date data specified by S2 .

7-356
 (DT=,DT<>,DT>,DT<=,DT<,DT>=)

(c) The following table shows processing details of bits to be compared.

n value for n value for 1
comparison of comparison of Date to be
Processing details
specified date data specified date data compared
with given date data with current date data
2
0001H 8001H Day Comparison of days ( S1 +2)
0002H 8002H Month Comparison of months ( S1 +1)
0003H 8003H Month, day Comparison of months ( S1 +1) and days ( S1 +2) 3
0004H 8004H Year Comparison of years ( S1 )
0005H 8005H Year, day Comparison of years ( S1 ) and days ( S1 +2)
4
0006H 8006H Year, month Comparison of years ( S1 ) and months ( S1 +1)

Comparison of years ( S1 ), months ( S1 +1),

0007H 8007H Year, month, day
and days ( S1 +2) 6
No comparison of years ( S1 ), months ( S1 +1),
Other than 0001H to 0007H,8001H to 8007H No objects
and days ( S1 +2) (Non-conductive)
6
(7) If the data stored in the devices to be compared are not recognized as date data, SM709 will
be turned on after the instruction execution and no-conductive status will be made. Even if
they are not recognized as date data but the range of the devices is within the setting range,
SM709 will not be turned on.
7
Moreover, if the range of devices specified by S1 to S1 +2 or S2 to S2 +2 exceeds the range of
specified devices, SM709 will be turned on after the instruction execution and no-conductive
status will be made. 8
Once SM709 is turned on, on-status will be retained till when the CPU modules are reset or
powered off. Therefore, turn off SM709 if necessary.
(8) The following table shows the comparison operation results for each instruction.

7.15.7 Date comparison (DT=,DT<>,DT>,DT<=,DT<,DT>=)

7.15 Clock instructions
Instruction Comparison Instruction Comparison
Condition Condition
symbols in operation result symbols in operation result

DT= S1
= S2 DT= S1 S2

DT<> S1 S2 DT<> S2 = S1

DT> S1 > S2 DT> S1 S2

No-conductive
Conductive status
DT<= DT<= status
S1 S2 S1 > S2

DT< S1 < S2 DT< S1 S2

DT>= S1 S2 DT>= S1 < S2

7-357
 (DT=,DT<>,DT>,DT<=,DT<,DT>=)

(a) The following figure shows the comparison example of dates.

A B C

2006/1/1 2007/1/1 2008/1/1 2009/1/1

(2006/9/22) (2007/6/23) (2008/8/8)

The following table shows the conductive states resulting from performing the
comparison operation of the dates A, B, and C shown above.
Even if the objects to be compared are under the same condition, the comparison
operation results vary depending on the objects selected.
Comparison Comparison condition
objects A<B B<C A<C

Day

Month

Month, day

Year
Month, day
Year, month
Year, month, day

No objects

: Conductive : No-conductive

(b) Even if the dates to be compared do not exist practically, this instruction executes the
comparison operation for the objects with the settable dates in accordance with the
following condition.
• Date A: 2006/02/30 (This date is settable, though it does not exist.)
• Date B: 2007/03/29
• Date C: 2008/02/31 (This date is settable, though it does not exist.)
Comparison Comparison condition
objects A<B B<C A<C

Day

Month

Month, day

Year
Month, day
Year, month
Year, month, day

No objects

: Conductive : No-conductive

7-358
 (DT=,DT<>,DT>,DT<=,DT<,DT>=)

Operation Error
1
(1) Any operation errors do not occur in DT=,DT<>,DT>,DT<=,DT<,DT>= instruction.

Program Example 2
(1) The following program compares the data stored in D0 with the data (year, month, and day)
stored in D10, and makes Y33 be conductive status when the data stored in D0 meet the 3
data stored in D10.
[Ladder Mode] [List Mode]
Step Instruction Device 4

6
(2) The following program compares the data stored in D0 with the current date data (year and
month), and makes Y33 be conductive status when the data stored in D0 do not meet the
current date data, when M0 is turned on. 6
[Ladder Mode] [List Mode]
Step Instruction Device
7

8
(3) The following program compares the data stored in D0 with the data (year and day) stored in
D10, and makes Y33 be conductive status when the data value stored in D10 is smaller than
the data value stored in D0, when M0 is turned on.
[Ladder Mode] [List Mode]

7.15.7 Date comparison (DT=,DT<>,DT>,DT<=,DT<,DT>=)

7.15 Clock instructions
Step Instruction Device

(4) The following program compares the data stored in D0 with the current date data (year), and
makes Y33 be conductive status when the value of the current date data is the data value
stored in D0 or larger.
[Ladder Mode] [List Mode]
Step Instruction Device

7-359
 (TM=,TM<>,TM>,TM<=,TM<,TM>=)

7.15.8 Clock comparison (TM=,TM<>,TM>,TM<=,TM<,TM>=)

(TM=,TM<>,TM>,TM<=,TM<,TM>=)

Ver.
High
Basic performance Process Redundant Universal LCPU

QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later.

(TM=,TM<>,TM>,TM<=,TM<,TM>=)
QnUDE(H)CPU: The serial number (first five digits) is "10102" or later.

indicates an instruction symbol of DT＝/DT＜＞/DT＜/DT＜＝/DT＞/DT＞＝.

LD S1 S2 n
Command
AND S1 S2 n
Command

OR
S1 S2 n

S1 : Head number of the devices where the data to be compared are stored (BIN 16 bits)
S2: Head number of the devices where the data to be compared are stored (BIN 16 bits)
n : Value of the data to be compared or the number of the stored data to be compared (BIN 16 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S1 –– –– –– ––

S2 –– –– –– ––

n –– ––

Function
(1) This instruction compares the clock data specified by S1 with those specified by S1 , or the
clock data specified by S1 with the current time data. Setting n determines the data to be
compared.
(a) Comparison of given clock data

• This instruction treats the clock data specified by S1 and the clock data specified by
S1 as a normally open contact, and compares the data in accordance with the value

of n.
Data range Data range
S1 Hour （0∼23） S2 Hour （0∼23）
Comparison Comparison
S1 ＋1 Minute （0∼59） S2 ＋1 Minute （0∼59）
operator operation result
S1 ＋2 Second （0∼59） S2 ＋2 Second （0∼59）

7-360
 (TM=,TM<>,TM>,TM<=,TM<,TM>=)

(b) Comparison of current time data

• This instruction treats the clock data specified by S1 and the current time data as a 1
normally open contact, and compares the data in accordance with the value of n.

• This instruction treats the clock data specified by as dummy data and ignores the
data.
S1
2
Data range
（0∼23）
3
S1 Hour
Comparison Comparison
S1 ＋1 Minute （0∼59） Current time
operator operation result
S1 ＋2 Second （0∼59）

4
When either S1 or S1 corresponds to any of the following conditions in comparing
given or current time data with specified clock data, the operation error (error 6
code: 4101) or a malfunction may occurs.
• The range of the devices to be used for the index modification is specified over
the range of the device specified by S1 or S1 . 6
• File registers are specified by S1 or S1 without a register set.

7
(2) This instructions set BIN values for each item.
(3) This instructions sets the time selected from 0 to 23 (midnight to 23 o'clock) with the BIN
value specified by S1 or S1 . (Uses the 24-hour clock.) 8
(4) This instructions sets the minute selected from 0 to 59 (0 to 59 minutes) with BIN value
specified by S1 +1 or S1 +1.
(5) This instructions sets the second selected from 0 to 59 (0 to 59 seconds) with BIN value

7.15.8 Clock comparison (TM=,TM<>,TM>,TM<=,TM<,TM>=)

7.15 Clock instructions
specified by S1 +2 or S1 +2.
(6) This instructions specifies the following values at n so that the data to be compared can be
specified.
The bit configuration specified at n is as follows.
This instruction specifies 0 at bits from 3rd to 14th.
The instruction will be non-conductive status without
specifying 0 regardless of the operation result.

b15 b14 b3 b2 b1 b0
0/1 0 0/1 0/1 0/1

Second
If this instruction specifies 1 (on) at 15th bit, the Minute
instruction compares S1 with the current date in
accordance with the bit condition specified at 0 to 2nd Hour
bit.

(a) Clock data to be compared (from 0 to 2nd bit)

• 0: Does not compare specified clock data (hour/minute/second).
• 1: Compares specified clock data (hour/minute/second).

(b) Operation data to be compared (15th bit)

• 0: Compares the clock data specified by S1 with the clock data specified by S1 .

• 1: Compares the clock data specified by S1 with the current time data.
Ignores the clock data specified by S1 .

7-361
 (TM=,TM<>,TM>,TM<=,TM<,TM>=)

(c) The following table shows processing details of bits to be compared.

n value for n value for
comparison of comparison of Time to be
Processing details
pecified clock data with specified clock data with compared
given clock data current time data
0001H 8001H Second Comparison of seconds ( S1 +2)
0002H 8002H Minute Comparison of minutes ( S1 +1)

Minute, Comparison of minutes ( S1 +1) and seconds

0003H 8003H
second days ( S1 +2)
0004H 8004H Hour Comparison of hours ( S1 )

Hour, Comparison of hours ( S1 ) and

0005H 8005H
second seconds ( S1 +2)
0006H 8006H Hour, minute Comparison of hours ( S1 ) and minutes ( S1 +1)

Hour, minute, Comparison of hours ( S1 ), minutes ( S1 +1),

0007H 8007H
second and seconds ( S1 +2)

Other than 0001H to 0007H, No comparison of hours ( S1 ), minutes ( S1 +1),

No objects
8001H to 8007H and seconds ( S1 +2) (Non-conductive)

(7) If the data stored in the devices to be compared are not recognized as date data, SM709 will
be turned on after the instruction execution and no-conductive status will be made. Once
SM709 is turned on, on-status will be retained till when the CPU modules are reset or
powered off. Therefore, turn off SM709 if necessary.
Moreover, if the range of devices specified by S1 to S1 +2 or S1 to S1 +2 exceeds the range of
specified devices, SM709 will be turned on and no-conductive status will be made.
(8) The following table shows the comparison operation results for each instruction.
Instruction Comparison Instruction Comparison
Condition Condition
symbols in operation result symbols in operation result

TM= S1
= S2 TM= S1 S2

TM<> S1 S2 TM<> S2 = S1

TM> S1 > S2 TM> S1 S2 No-conductive

Conductive status
TM<= TM<= status
S1 S2 S1 > S2

TM< S1 < S2 TM< S1 S2

TM>= S1 S2 TM>= S1 < S2

7-362
 (TM=,TM<>,TM>,TM<=,TM<,TM>=)

(a) The following figure shows the comparison example of time.

A B C
1
0 Midnight 6:00 N00n 18:00 0 Midnight
4:50:55 14:08:58 22:47:05

The following table shows the conductive states resulting from performing the 2
comparison operation of the dates A, B, and C shown above.
Even if the objects to be compared are under the same condition, the comparison
operation results vary depending on the objects selected. 3
Comparison condition
Comparison objects
A<B B<C A<C
Second
4
Month

Month, day 6
Hour

Hour, second

Hour, minute
6
Hour, minute, second

No objects
7
: Conductive : No-conductive

8
Operation Error
(1) Any operation errors do not occur in TM=,TM<>,TM>,TM<=,TM<,TM>=instruction.

7.15.8 Clock comparison (TM=,TM<>,TM>,TM<=,TM<,TM>=)

7.15 Clock instructions

7-363
 (TM=,TM<>,TM>,TM<=,TM<,TM>=)

Program Example
(1) The following program compares the data stored in D0 with the data (hour, minute, and
second) stored in D10, and makes Y33 be conductive status when the data stored in D0
meet the data stored in D10.
[Ladder Mode] [List Mode]
Step Instruction Device

(2) The following program compares the data stored in D0 with the current time data (hour and
minute), and makes Y33 be conductive status when the data stored in D0 do not meet the
current date data, when M0 is turned on.
[Ladder Mode] [List Mode]
Step Instruction Device

(3) The following program compares the data stored in D0 with the data (hour and second)
stored in D10, and makes Y33 be conductive status when the data value stored in D10 is
smaller than the data value stored in D0, when M0 is turned on.
[Ladder Mode] [List Mode]
Step Instruction Device

(4) The following program compares the data stored in D0 with the current time data (hour), and
makes Y33 be conductive status when the value of the current time data is the data value
stored in D0 or larger.
[Ladder Mode] [List Mode]
Step Instruction Device

7-364
 S(P).DATERD

7.16 Expansion Clock Instructions

1
7.16.1 Reading expansion clock data (S(P).DATERD)
S(P).DATERD
2
Ver. Ver. Ver.

3
High
Basic performance Process Redundant Universal LCPU

High performance model QCPU, Process CPU, Redundant CPU:

The serial number (first five digits) is "07032" or later.

4
Command
S.DATERD S.DATERD D 6
Command
SP.DATERD D
SP.DATERD
6
D : Head number of the devices where the read clock data will be stored (BIN 16 bits)

Setting Internal Devices J \

7
R, ZR U \G Zn Constants Other
Data Bit Word Bit Word

D –– ––
8

Function
(1) Reads "year, month, day, hour, minute, second, day of the week, and millisecond" from the

7.16.1 Reading expansion clock data (S(P).DATERD)

7.16 Expansion Clock Instructions
clock element of the CPU module, and stores it as BIN value into the device specified by D
or later device.
D Year (1980 to 2079)
D +1 Month (1 to 12)
D +2 Day (1 to 31)
D +3 Hour (24-hour clock) (0 to 23)
Clock element
D +4 Minute (0 to 59)
D +5 Second (0 to 59)
D +6 Day of week (0 to 6)
D +7 Millisecond (0 to 999)

(2) The "year" at D is stored as 4-digit year indication.

(3) The "day of the week" at D +6 is stored as 0 to 6 to represent the days Sunday to Saturday.

Day of week Sunday Monday Tuesday Wednesday Thursday Friday Saturday

Stored data 0 1 2 3 4 5 6

(4) Compensation is made automatically for leap years.

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• The device specified by D exceeds the range of the corresponding device.
(For the Universal model QCPU, LCPU.) (Error code: 4101)

7-365
 S(P).DATERD

Program Example
(1) The following program outputs the following clock data as BCD values:
Year .................... Y70 to Y7F
Month.................. Y68 to Y6F
Day ..................... Y60 to Y67
Hour.................... Y58 to Y5F
Minute................. Y50 to Y57
Second ............... Y48 to Y4F
Week .................. Y44 to Y47
Millisecond.......... Y38 to Y43
[Ladder Mode]

Outputs "Year"

Outputs "Month"

Outputs "Day"

Outputs "Hour"

Outputs "Minute"

Outputs "Second"

Outputs "Day of Week"

Outputs "Millisecond"

[List Mode]
Step Instruction Device

[Operation]
BCD Y7F Y70
2 0 0 5 (Year)

D0 2005
Y6F Y68 Y67 Y60
D1 12
1 2 2 4 (Month, Day)
Clock data D2 24
2005, 12, 24 12:57:39 Sunday 530 D3 12
Y5F Y58 Y57 Y50
D4 57
1 2 5 7 (Hour, Minute)
D5 39
D6 0
Y4F Y48 Y47 Y44
D7 530
3 9 0 (Second, Day of week)
BIN
Y43 Y38
5 3 0 (Millisecond)

7-366
 S(P).DATERD

Caution
1
(1) This instruction reads clock data and stores those to a specified device even if a wrong clock
data is set to the CPU module. (example: Feb. 30th)
When setting clock data with the DATEWR instruction or GX Developer, make sure to set a 2
correct data.
(2) Time error of reading a clock data of millisecond is a maximum of 2ms. (Difference between
the data memorized by clock element inside of the CPU module and the data read by this 3
function.)
(3) Specifying digit for the bit device can be used only when the following conditions (a) and (b)
are met. 4
(a) Digit specification: K4

(b) Head of device: multiple of 16

6
When the above conditions (a) and (b) are not met, INSTRCT CODE ERR.
(error code: 4004) will occur.

7.16.1 Reading expansion clock data (S(P).DATERD)

7.16 Expansion Clock Instructions

7-367
 S(P).DATE+

7.16.2 Expansion clock data addition operation (S(P).DATE+)

S(P).DATE+

Ver. Ver. Ver.

High
Basic performance Process Redundant Universal LCPU

High performance model QCPU, Process CPU, Redundant CPU:

The serial number (first five digits) is "07032" or later.

Command
S.DATE+ S.DATE+ S1 S2 D

Command
SP.DATE+ S1 S2 D
SP.DATE+

S1 : Head number of the devices where the clock data to be adjusted by addition is stored (BIN 16 bits)

S2 : Head number of the devices where the time data to be added for adjustment is stored (BIN 16 bits)

D : Head number of the devices where the result of addition of clock (time) data will be stored (BIN 16 bits)

Setting Internal Devices J \

R, ZR U \G Zn Constants Other
Data Bit Word Bit Word

S1 –– ––

S2 –– ––

D –– ––

Function
(1) Adds the time data designated by S2 to the clock data designated by S1 , and stores the
result into the area starting from the device designated by D .
Setting data Setting data Setting data
S1 Hour (0 to 23) S2 Hour (0 to 23) D Hour (0 to 23)
S1 +1 Minute (0 to 59) S2 +1 Minute (0 to 59) D +1 Minute (0 to 59)
S1 +2 Second (0 to 59) + S2 +2 Second (0 to 59) D +2 Second (0 to 59)
S1 +3 -- S2 +3 -- D +3 --
S1 +4 Millisecond (0 to 999) S2 +4 Millisecond (0 to 999) D +4 Millisecond (0 to 999)

For example, adding the time 7:48:10:500 to 6:32:40:875 would result in the following
operation:
S1 Hour: 6 S2 Hour: 7 D Hour: 14
S1 +1 Minute: 32 S2 +1 Minute: 48 D +1 Minute: 20
S1 +2 Second: 40 + S2 +2 Second: 10 D +2 Second: 51
S1 +3 -- S2 +3 -- D +3 --
S1 +4 Millisecond: 875 S2 +4 Millisecond: 500 D +4 Millisecond: 375

7-368
 S(P).DATE+

(2) If the results of the addition of time exceed 24 hours, 24 hours will be subtracted from the
sum to make the final operation result.
For example, when the time 20:20:20:500 is added to 14:20:30:875, the result is not
1
34:40:51:375, but 10:40:51:375.
S1
S1 +1
Hour: 14
Minute: 20
S2
S2 +1
Hour: 20
Minute: 20
D
D
Hour: 10
+1 Minute: 40
2
S1 +2 Second: 30 + S2 +2 Second: 20 D +2 Second: 51
S1 +3 -- S2 +3 -- D +3 --
S1 +4 Millisecond: 875 S2 +4 Millisecond: 500 D +4 Millisecond: 375 3

Devices, S1 +3, S2 +3, and D +3 are not used for operation. 4

A clock data read by the S(P).DATERD instruction can be directly added.

D
D +1
Hour
Minute
6
D +2 Second
D +3 Day of week
D +4 Millisecond 6
When the clock data is read by the S(P).DATERD instruction,
day of week is inserted between "second" and "millisecond".
If the S(P).DATE+ instruction is used to read the clock data,
the data can be directly used for addition since it does not perform
7
the calculation for the day of a week.

8
Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.

7.16.2 Expansion clock data addition operation (S(P).DATE+)

7.16 Expansion Clock Instructions
• The data set by S1 and S2 is outside the range. (See Function (1).) (Error code: 4100)
• The device specified by S1 , S2 or D exceeds the range of the corresponding device.
(For the Universal model QCPU, LCPU.) (Error code: 4101)

Caution
(1) Specifying digit for the bit device can be used only when the following conditions (a) and (b)
are met.
(a) Digit specification: K4

(b) Head of device: multiple of 16

When the above conditions (a) and (b) are not met, INSTRCT CODE ERR.
(error code:4004) will occur.

7-369
 S(P).DATE+

Program Example
(1) The following program adds 1 hour to the clock data read from the clock element, and stores
the results into the area starting from D100 when X20 is turned ON.
[Ladder Mode]

Reads out the clock element

data to D0 or later.

Sets the time to D10 or later.

[List Mode]

Step Instruction Device

[Operation]
• Time data read operation by the SP.DATERD instruction
Clock element D0 05 Year
D1 5 Month
D2 17 Day
D3 10 Hour
D4 23 Minute Time data
D5 41 Second
D6 2 Day of week
100 Millisecond Time data

• Addition by the SP.DATE+ instruction

D3 Hour: 10 D10 Hour: 1 D100 Hour: 11
D4 Minute: 23 D11 Minute: 0 D101 Minute: 23
D5 Second: 41 + D12 Second: 0 D102 Second: 41
D6 2 (Tuesday) D13 -- D103 --
D7 Millisecond: 100 D14 Millisecond: 0 D104 Millisecond: 100

7-370
 S(P).DATE-

7.16.3 Expansion clock data subtraction operation (S(P).DATE-)

S(P).DATE-
1
Ver. Ver. Ver.
High
2
Basic performance Process Redundant Universal LCPU

High performance model QCPU, Process CPU, Redundant CPU:

The serial number (first five digits) is "07032" or later.

3
Command
S.DATE- S.DATE- S1 S2 D
4
Command
SP.DATE- SP.DATE- S1 S2 D

6
S1 : Head number of the devices where the clock time data to be adjusted by substraction is stored (BIN 16 bits)

S2 : Head number of the devices where time data to be subtracted for adjustment is stored (BIN 16 bits) 6
D : Head number of the devices where the result of subtraction of clock (time) data will be stored (BIN 16 bits)

Setting Internal Devices J \

Data Bit Word
R, ZR
Bit Word
U \G Zn Constants Other
7
S1 –– ––

–– ––
8
S2

D –– ––

Function

7.16.3 Expansion clock data subtraction operation (S(P).DATE-)

7.16 Expansion Clock Instructions
(1) Subtracts the time data designated by S2 from the clock data designated by S1 , and stores
the result into the area starting from the device designated by D .
Setting data Setting data Setting data
S1 Hour (0 to 23) S2 Hour (0 to 23) D Hour (0 to 23)
S1 +1 Minute (0 to 59) S2 +1 Minute (0 to 59) D +1 Minute (0 to 59)
S1 +2 Second (0 to 59) - S2 +2 Second (0 to 59) D +2 Second (0 to 59)
S1 +3 -- S2 +3 -- D +3 --
S1 +4 Millisecond (0 to 999) S2 +4 Millisecond (0 to 999) D +4 Millisecond (0 to 999)

For example, when the clock time 3:50:10:500 is subtracted from the clock time
10:40:20:875, the operation is performed as follows:
S1 Hour: 10 S2 Hour: 3 D Hour: 6
S1 +1 Minute: 40 S2 +1 Minute: 50 D +1 Minute: 50
S1 +2 Second: 20 - S2 +2 Second: 10 D +2 Second: 10
S1 +3 -- S2 +3 -- D +3 --
S1 +4 Millisecond: 875 S2 +4 Millisecond: 500 D +4 Millisecond: 375

7-371
 S(P).DATE-

(2) If the subtraction results in a negative number, 24 will be added to the result to make a final
operation result.
For example, when the clock time 10:42:12:500 is subtracted from 4:50:32:875, the result is
not 6:8:20:375, but 18:8:20:375.
S1 Hour: 4 S2 Hour: 10 D Hour: 18
S1 +1 Minute: 50 S2 +1 Minute: 42 D +1 Minute: 8
S1 +2 Second: 32 - S2 +2 Second: 12 D +2 Second: 20
S1 +3 -- S2 +3 -- D +3 --
S1 +4 Millisecond: 875 S2 +4 Millisecond: 500 D +4 Millisecond: 375

Devices, S1 +3, S2 +3, and D +3 are not used for operation.

A clock data read by S(P).DATERD instruction can be directly subtracted.
D Hour
D +1 Minute
D +2 Second
D +3 Day of week
D +4 Millisecond

When the clock data is read by the S(P).DATERD instruction,

day of week is inserted between "second" and "millisecond".
If the S(P).DATE- instruction is used to read the clock data,
the data can be directly used for subtraction since it does not
perform the calculation for the day of the week.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The data set by S1 and S2 is outside the range. (See Function (1).) (Error code: 4100)
• The device specified by S1 , S2 or D exceeds the range of the corresponding device.
(For the Universal model QCPU, LCPU.) (Error code: 4101)

Caution
(1) Specifying digit for the bit device can be used only when the following conditions (a) and (b)
are met.
(a) Digit specification: K4

(b) Head of device: multiple of 16

When the above conditions (a) and (b) are not met, INSTRCT CODE ERR.
(error code:4004) will occur.

7-372
 S(P).DATE-

Program Example
1
(1) The following program subtracts the time data stored in the area starting from D10 from the
clock data read from the clock element when X1C is turned ON, and stores the result into
the area starting from D100. 2
[Ladder Mode]

Reads out the clock element

data to D0 or later.
3

Sets the time to D10 or later. 4

6
[List Mode]
Step Instruction Device
7

[Operation]

7.16.3 Expansion clock data subtraction operation (S(P).DATE-)

7.16 Expansion Clock Instructions
• Time data read operation by the SP.DATERD instruction
Clock element D0 05 Year
D1 2 Month
D2 23 Day
D3 8 Hour
D4 42 Minute Time data
D5 1 Second
D6 3 Day of week
D7 997 Millisecond Time data

• Subtraction by the SP.DATE- instruction

D3 Hour: 8 D10 Hour: 10 D100 Hour: 22
D4 Minute: 42 D11 Minute: 40 D101 Minute: 1
D5 Second: 1 - D12 Second: 10 D102 Second: 51
D6 3 (Wednesday) D13 -- D103 --
D7 Millisecond: 997 D14 Millisecond: 500 D104 Millisecond: 497

8:42:1:997 - 10:40:10:500 -2:1:51:497

Adds 24 to this value

22:1:51:497

7-373
 7.17 Program control instructions
(1) Processing when the execution type is converted with the program control instruction is as
follows.

Executed Instruction
Execution type before change
PSCAN PSTOP POFF PLOW

No change-remains Output turned OFF in

Scan execution type
scan type execution. next scan.
Becomes stand-by type. Becomes stand-by type
Becomes low speed
Initial execution type from the next scan after
Becomes scan execution type.
that.
execution type.
No change-remains
Stand-by type Ignored
stand-by type
Low speed execution
Low speed execution
Low speed execution type execution is
type execution is
type execution is stopped, and output is
stopped, becomes scan No change -remains low
Low speed execution type stopped, becomes turned OFF in the next
execution type from the speed execution type.
stand-by type from next scan. Becomes
next scan.
scan. stand-by type from the
(Execution from step 0)
next scan after that.
Output turned OFF in
next scan.
Becomes scan Becomes low speed
Fixed scan execution type Becomes stand-by type. Becomes stand-by type
execution type. execution type.
from the next scan after
that.

Once the fixed scan execution type program is changed to another execution
type, it cannot be returned to the fixed scan execution type.

7-374
(2) As program execution type conversions by PSCAN and PSTOP instructions occur at the
END processing, such conversions are impossible during program execution.
When different execution types have been set for the same program in the same scan, the
execution type will be that specified by the execution switching command that was executed
1
last.
END processing END processing END processing
Execution
2
program name GHI "ABC" GHI GHI *1 DEF *1 GHI

PSTO executes "ABC"

PSCAN executes "DEF"
Converts "DEF" into the scan execution
type program and "ABC" to the stand-by 3
type program

*1: The order of "GHI" and "DEF" program execution is determined by the program settings parameters.
Switching from the fixed scan execution type program to the execution type program is 4
performed in the following timing.

(a) For the Universal model QCPU, LCPU

The execution type is changed when the execution of the fixed scan execution type is 6
stopped at the END processing after the program control instruction execution.

(b) Basic model QCPU, High Performance model QCPU, Process CPU, and Redundant 6
CPU
The execution of the fixed scan execution type is stopped at the execution of the
program control instruction, and the execution type is changed at the END processing. 7
(3) When the POFF instruction is executed, the output is turned OFF at the next scan, and the
execution type will be the stand-by type at the second next scan and later.
If executed prior to the output OFF processing, the program control instruction is ignored. 8

7.17 Program control instructions

7-375
 PSTOP(P)

7.17.1 Program standby instruction (PSTOP(P))

PSTOP(P)

High
Basic performance Process Redundant Universal LCPU

Command
PSTOP PSTOP S

Command
PSTOPP PSTOPP S

S : Character string for the name of the program file to be set in the stand-by status or head number of the
devices where the character string data is stored (character string)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word $

S –– –– ––

Function
(1) Places the file name program stored in the device designated by S in the stand-by status.
(2) Only the programs stored in the drive No. 0 (program memory/internal RAM) can be set as
the stand-by type.
(3) The specified program is placed in the stand-by status when END processing is performed.
(4) This instruction will be given priority even in cases when a program execution type has been
designated in the parameters.
(5) It is not necessary to designate the extension (.QPG) with the file name.
(Only .QPG files will be acted on.)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The program with the file name specified by S does not exist. (Error code: 2410)
• The program type of the file name specified by S is the SFC program. (Error code: 2412)
• The file name storage destination device of S exceeds the range of the corresponding
device. (Error code: 4101)

Program Example
(1) The following program places the program with the file name ABC in the stand-by status
when X0 goes ON.
[Ladder Mode] [List Mode]

Step Instruction Device

7-376
 POFF(P)

7.17.2 Program output OFF standby instruction (POFF(P))

POFF(P)
1
High
2
Basic performance Process Redundant Universal LCPU

3
Command
POFF POFF S

Command 4
POFFP POFFP S

S : File name of the program to be set in the standby status by turning OFF the output, or the device where the
6
file name is stored (character string)

Setting Internal Devices Constants

Data Bit Word
R, ZR
Bit
J \
Word
U \G Zn
$
Other 6
S –– –– ––

7
Function
(1) Changes the execution type of the program with the file name stored in the device 8
designated by S .
• Scan execution type: Turns OFF outputs at the next scan (Non-execution
processing). Programs are set as the stand-by type after
the subsequent scan.

7.17.2 Program output OFF standby instruction (POFF(P))

7.17 Program control instructions
• Low speed execution type: Stops the execution of the low speed execution type
program and turns OFF outputs at the next scan. Programs
are set as the stand-by type after the subsequent scan.
(2) Only the programs stored in the drive No. 0 (program memory) can be set as the stand-by
type.
(3) This instruction will be given priority even in cases when a program execution type has been
designated in the parameters.
(4) It is not necessary to designate the extension (.QPG) with the file name.
(Only .QPG files will be acted on.)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The program with the file name specified by S does not exist.
(Error code: 2410)

• The file name storage destination device of S exceeds the range of the corresponding
device. (Error code: 4101)

7-377
 POFF(P)

Remark
1. Non-execution processing is identical to the processing that is conducted when
the condition contacts for the individual coil instructions are in the OFF state.

The operation results for the individual coil instructions following non-execution
processing will be as follows, regardless of the ON/OFF status of the individual
contacts:
OUT instruction ...... Forced OFF
SET instruction
RST instruction
SFT instruction ...... Maintains status
Basic instruction
Application instruction
PLS instruction Processing identical to
Pulse generation ...... when condition contacts
instruction ( P) are OFF
Current value of low speed/high speed timer ...... 0
Current value of retentive timer
...... Preserves
Current value of counter

Program Example
(1) The following program makes the program with the file name ABC non-executionable and
places it in the standby status when X0 is turned ON.
[Ladder Mode] [List Mode]

Step Instruction Device

7-378
 PSCAN(P)

7.17.3 Program scan execution registration instruction (PSCAN(P))

PSCAN(P)
1
High
2
Basic performance Process Redundant Universal LCPU

3
Command
PSCAN PSCAN S

PSCANP
Command
PSCANP S
4

S : File name of the program to be set as a scan execution type, or head number of the devices where the file
6
name is stored (character string)

Setting Internal Devices J \ Constants

Data Bit Word
R, ZR
Bit Word
U \G Zn
$
Other
6
S –– –– ––

7
Function
(1) Sets the program whose file name is being stored at the device designated by S in the scan 8
execution type.
(2) Only the programs stored in the drive No. 0 (program memory/internal RAM) can be set as
the scan execution type.

7.17.3 Program scan execution registration instruction (PSCAN(P))

7.17 Program control instructions
(3) Designated programs assume the scan execution type with END processing.
Example
When programs A, B, and C exist and program A performs "PSCAN" of program D.
A B C END A B C D END

Execution of Program D
PSCAN is executed
Scan Scan

(4) This instruction will be given priority even in cases when a program execution type has been
designated in the parameters.
(5) It is not necessary to designate the extension (.QPG) with the file name.
(Only .QPG files will be acted on.)

7-379
 PSCAN(P)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The program with the file name specified by S does not exist.
(Error code: 2410)

• The file name storage destination device of S exceeds the range of the corresponding
device. (Error code: 4101)
• The specified file name is the SFC program, and the SFC program for the other file name
has been already started. (Dual activation error of the SFC program)
(For the Universal model QCPU, LCPU) (Error code: 4131)
(For the High Performance model QCPU, Process CPU, Redundant CPU)
(Error code: 2504)

Program Example
(1) The following program sets the program with file name ABC as scan execution type when
X0 is turned ON.
[Ladder Mode] [List Mode]

Step Instruction Device

7-380
 PLOW(P)

7.17.4 Program low speed execution registration instruction

(PLOW(P)) 1
PLOW(P)

High
2
Basic performance Process Redundant Universal LCPU

3
Command
PLOW PLOW S
4
Command
PLOWP PLOWP S

6
S : File name of the program to be set as a low speed execution type, or head number of the devices where the
file name is stored (character string)

Setting Internal Devices J \ Constants

6
R, ZR U \G Zn Other
Data Bit Word Bit Word $

S –– –– ––
7

Function 8
(1) Sets the program whose file name is being stored at the device designated by S in
low-speed execution type.
(2) Only the programs stored in the drive No. 0 (program memory/internal RAM) can be set as
the low speed execution type.

7.17.4 Program low speed execution registration instruction (PLOW(P))

7.17 Program control instructions
(3) Designated programs assume the low speed execution type with END processing.
Example
When programs A, B, and C exist and program A performs "PLOW" of program D.
(Assume that the constant scan has been set.)
Waiting for constant
A B C END A B C END D

Execution of Program D
PLOW is executed

Scan Scan

(4) This instruction will be given priority even in cases when a program execution type has been
designated in the parameters.
(5) It is not necessary to designate the extension (.QPG) with the file name.
(Only .QPG files will be acted on.)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The program with the designated file name does not exist. (Error code: 2410)
• There is a CHK instruction contained within the program whose file name has been
designated. (Error code: 4235)

7-381
 PLOW(P)

Program Example
(1) The following program sets the program with file name ABC as low-speed execution type
when X0 is turned ON.
[Ladder Mode] [List Mode]

Step Instruction Device

7-382
 PCHK

7.17.5 Program execution status check instruction (PCHK)

PCHK
1
High
2
Basic performance Process Redundant Universal LCPU

3
LDPCHK PCHK File name

ANDPCHK
Command
PCHK File name
4
Command
ORPCHK
6
PCHK File name

6
S : File name of the program whose execution status will be checked (character string)

Setting Internal Devices J \ Constants

Data Bit Word
R, ZR
Bit Word
U \G Zn
$
Other
7
S –– ––

8
Function
(1) Checks whether the program of the specified file name is in execution or not
(non-execution).

7.17.5 Program execution status check instruction (PCHK)

7.17 Program control instructions
(2) The instruction is in conduction when the program of the specified file name is in execution,
and the instruction is in non-conduction when the program is in non-execution.
(3) Specify the file name without an extension (.QPG).
For example, specify "ABC" when the file name is ABC.QPG.

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• The program with the designated file name does not exist. (Error code: 2410)

Program Example
(1) Program that keeps Y10 ON when the program file "ABC.QPG" is being executed.

PCHK "ABC" Y10

Execution

Non-execution

7-383
 PCHK

Remark
Non-execution indicates that the program execution type is a stand-by type.
Execution indicates that the program execution type is a scan execution type
(including during output OFF (during non-execution processing)), low speed
execution type or fixed scan execution type.

The PCHK instruction is in conduction when the program of the specified file
name (target program) is in execution, and the instruction is in non-conduction
when the program is in non-execution.
When the target program is set to non-execution (stand-by type) with the POFF
instruction, the PCHK instruction is in conduction while the non-execution
processing of the target program is being performed.
At the END processing of the scan where the non-execution processing is
completed, the target program is put into non-execution (stand-by type), and the
PCHK instruction is brought into non-conduction.
Therefore, note that if the PCHK instruction is executed for the program where the
non-execution processing has been completed by the POFF instruction, the
PCHK instruction may be brought into conduction.

The following chart shows the operation performed when program A executes the
POFF instruction of program B and program C executes the PCHK instruction of
program B with the programs being executed in order of program A, program B
and program C.
Program B execution type change
(Scan execution type to stand-by type)

END processing END processing END processing

Scan Scan Scan Scan

execution execution execution execution
Program A Scan Scan
execution execution
Program B Scan Scan Scan
execution execution execution
Program C
POFF instruction is Non-execution processing
executed in program B is performed.
Continuity
PCHK B
Non-continuity

7-384
 WDT(P)

7.18 Other instructions

1
7.18.1 Resetting watchdog timer (WDT(P))
WDT(P)
2
Basic High
Process Redundant Universal LCPU
3
performance

4
Command
WDT WDT

Command 6
WDTP WDTP

6
Setting Internal Devices J \
R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
–– ––
7

Function
8
(1) Resets watchdog timer during the execution of a sequence program.
(2) Used in cases where the scan time exceeds the value set for the watchdog timer due to
prevailing conditions.
If the scan time exceeds the watchdog timer setting value on every scan, change the

7.18.1 Resetting watchdog timer (WDT(P))

7.18 Other instructions
watchdog timer settings at the peripheral device parameter settings.
(3) Make sure that the setting for t1 from step 0 to the WDT instruction and the setting for t2
from the WDT instruction to the END (FEND) instruction do not exceed the setting value of
the watchdog timer.
Step 0 END (FEND)
WDT

T1 T2

(4) The WDT instruction can be used two or more times during a single scan, but care should be
taken in such cases, because of the time required until the output goes OFF during the
generation of an error.
(5) Scan time values stored at the special register will not be cleared even if the WDT or WDTP
instruction is executed.
Accordingly, there are times when the value for the scan time for the special register is
greater than the value of the watchdog timer set at the parameters.

7-385
 WDT(P)

Operation Error

(1) There are no operation errors associated with the WDT(P) instruction.

Program Example
(1) The following program has a watchdog timer setting of 200 ms, when due to the execution
conditions program execution requires 300 ms from step 0 to the END (FEND) instruction.
[When WDT instruction is used]

Program where
Program where scan time is
scan time is 150 ms.
300 ms.
WDT
END
Program where
scan time is
150 ms.

END

7-386
 DUTY

7.18.2 Timing pulse generation (DUTY)

DUTY
1
Basic High
performance Process Redundant Universal LCPU
2

3
Command
DUTY DUTY n1 n2 D

4
n1 : Number of scans for ON (BIN 16 bits)
n2 : Number of scans for OFF (BIN 16 bits)
D : User timing clock (SM420 to SM424, SM430 to M434) (bits)
6
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

n1 ––
6
n2 ––

D *1 –– ––

*1: Only SM420 to SM424, SM430 to SM434 can be used. 7

Function 8
(1) Turns the user timing clock (SM420 to SM424, SM430 to M434), designated by D , ON for
the duration equivalent to the number of scans specified by n1, and OFF for the duration
equivalent to the number of scans specified by n2.

7.18.2 Timing pulse generation (DUTY)

7.18 Other instructions
ON
SM420 to SM424 OFF
SM430 to SM434 n1 scans n2 scans

(2) Scan execution type programs use SM420 to SM424, and low speed execution type
programs use SM430 to SM434.
(3) The following will take place if both n1 and n2 have been set for 0:

(a) n1 0, n2 0 SM420 to SM424 and SM430 to SM434 will stay OFF.

(b) n1 0, n2 0 SM420 to SM424 and SM430 to SM434 will stay ON.

(4) The data designated by n1, n2, and D is registered with the system when the DUTY
instruction is executed, and the timing pulse is turned ON and OFF by END processing.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The device designated by D is not from SM420 to SM424 or SM430 to SM434.
(Error code: 4101)
• The values of n1 and n2 are less than 0. (Error code: 4100)

7-387
 DUTY

Program Example
(1) The following program turns SM420 ON for 1 scan, and OFF for 3 scans if X0 is ON.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
ON
OFF
X0
ON
OFF
SM420
1 scan 3 scans

7-388
 TIMCHK

7.18.3 Time check instruction (TIMCHK)

TIMCHK
1
Ver.
High
Basic
2
performance Process Redundant Universal LCPU

Basic model QCPU: The upper five digits of the serial No. are "04122" or larger.

3
command
TIMCHK TIMCHK S1 S2 D

4
S1 : Device where the measured current value will be stored (BIN 16 bits)
S2 : Device where the set value of measurement is stored (BIN 16 bits)
D : Device to be turned ON at time-out (bits) 6
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S1 –– –– –– 6
S2 ––

D –– –– ––
7

Function 8
(1) Measures the ON time of the device used as a condition, and turns ON the device specified
by S2 if the condition device remains ON for longer than the time set to the device specified
by D .

7.18.3 Time check instruction (TIMCHK)

7.18 Other instructions
(2) The current value of the device specified by S1 is cleared to 0 and the device specified by D
is turned OFF at the leading edge of the execution command.
The current value of the device designated by S1 and the ON status of the device
designated by D are retained after the execution command turns OFF.
(3) Set the set value of measurement in units of 100ms.

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• The device that cannot be specified has been specified. (Error code: 4100)

Program Example
(1) Program where the ON time of X0 is set to 5s, the current value storage device to D0, and
the device that will turn ON at time-out to Y10.
[Ladder Mode] [List Mode]

Step Instruction Device

7-389
 ZRRDB(P)

7.18.4 Direct 1-byte read from file register (ZRRDB(P))

ZRRDB(P)

Basic High
performance Process Redundant Universal LCPU

Command
ZRRDB ZRRDB n D

Command
ZRRDBP ZRRDBP n D

n : Serial byte number for the file register to be read (BIN 32 bits)
D : Number of the device where the read data will be stored (BIN 16 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

n ––

D –– ––

Function
(1) Reads the serial byte number designated by n that does not signify a block number, and
stores at the lower 8 bits of the device designated by D .
The upper 8 bits designated by D will become 00H.
File register
ZR0 Area for
block No. 0
ZR32767
ZR32768 Area for
block No. 1 b15 b8B7 B0
n Serial byte number D 00H
ZR65535 Read-out contents
ZR65536 Area for
block No. 2

(2) The correspondence between file register numbers and serial byte numbers is as indicated
below:
b15 b8b7 b0
ZR0 Serial byte No. 1 Serial byte No. 0
ZR1 Serial byte No. 3 Serial byte No. 2
ZR2 Serial byte No. 5 Serial byte No. 4

ZR2500 Serial byte No. 5001 Serial byte No. 5000

ZR2501 Serial byte No. 5003 Serial byte No. 5002
ZR2502 Serial byte No. 5005 Serial byte No. 5004
ZR2503 Serial byte No. 5007 Serial byte No. 5006

Data when an even

number is designated
Data when an odd
number is designated

7-390
 ZRRDB(P)

(a) If the value of n has been designated as 23560, the data at the lower 8 bits of ZR11780
will be read.
1
Read destination
designation b15 b8 b7 b0 b15 b8 b7 b0
n 23560 ZR11780 43H 21H D 00H 21H
Data is stored 2
(b) If the value of n has been designated as 43257, the data at the upper 8 bits of ZR21628
will be read.
3
Read destination
designation b15 b8 b7 b0 b15 b8 b7 b0
n 43257 ZR21628 93H 42H D 00H 93H
Data is stored 4
Operation Error
6
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• A device number (serial byte number) that exceeds the range of allowable designations 6
has been designated. (Error code: 4101)

Program Example 7
(1) The following program reads the lower bits of ZR16000 and the upper bits of R16003, and
stores results at D100 and D101 when X0 is ON. 8
[Ladder Mode] [List Mode]
Step Instruction Device

7.18.4 Direct 1-byte read from file register (ZRRDB(P))

7.18 Other instructions
[Operation]
b15 b8 b7 b0 b15 b8 b7 b0
Serial byte No. 32000
R16000 8FH 25H D100 00H 25H
(Lower bits of R16000)
R16001 42H 32H D101 00H 93H
R16002 12H 34H
Serial byte No. 32007
R16003 93H 00H
(Upper bits of R16003)

7-391
 ZRWRB(P)

7.18.5 File register direct 1-byte write (ZRWRB(P))

ZRWRB(P)

Basic High
performance Process Redundant Universal LCPU

Command
ZRWRB ZRWRB n S

Command
ZRWRBP ZRWRBP n S

n : Serial byte number for the file register to be written (BIN 32 bits)
D : Number of the device where the data to be written is stored (BIN 16 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

n ––

S ––

Function
(1) Writes the lower bits of data stored in the device designated by S that does not signify a
block number to the file register of the serial byte number designated by n.
The upper 8 bits of data in the device designated by are ignored. S

File register
ZR0 Area for
ZR32767 block No. 0
ZR32768 Area for
Write destination block No. 1
designation Writing the data b15 b8b7 b0
n Serial byte number S Ignored
ZR65535
Contents to
ZR65536 Area for be written
block No. 2

(2) The correspondence between file register numbers and serial byte numbers is as indicated
below:
b15 b8b7 b0
ZR0 Serial byte No. 1 Serial byte No. 0
ZR1 Serial byte No. 3 Serial byte No. 2
ZR2 Serial byte No. 5 Serial byte No. 4

ZR2500 Serial byte No. 5001 Serial byte No. 5000

ZR2501 Serial byte No. 5003 Serial byte No. 5002
ZR2502 Serial byte No. 5005 Serial byte No. 5004
ZR2503 Serial byte No. 5007 Serial byte No. 5006

Storage destination
when an even number is designated
Storage destination
when an odd number is designated

7-392
 ZRWRB(P)

If n 12340 is specified, the data will be written to the lower 8 bits of ZR11170.

Write destination
designation b15 b8 b7 b0 b15 b8 b7 b0
1
n 12340 ZR11170 43H 21H S Ignored 54H

2
b15 b8 b7 b0
43H 54H

If n 43257 is specified, the data will be written to the upper 8 bits of ZR21628. 3
Write destination
designation b15 b8 b7 b0 b15 b8 b7 b0
n 43257 ZR21628 12H 50H S Ignored 43H 4

b15
43H
b8 b7
50H
b0
6

Operation Error 6
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
7
• A device number (serial byte number) that exceeds the range of allowable designations
has been designated. (Error code: 4101)

8
Program Example
(1) The following program writes the data at the lower bits of D100 and D101 to the lower bits of
R16000 and the upper bits of R16003 when X0 is turned ON.

7.18.5 File register direct 1-byte write (ZRWRB(P))

7.18 Other instructions
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
b15 b8 b7 b0 b15 b8 b7 b0
Serial byte No. 32000 D100 10H
R16000 54H 59H Ignored
(Lower bits of R16000)
R16001 4AH BAH
R16002 ABH 80H b15 b8 b7 b0
Serial byte No. 32007 D101 Ignored 01H
R16003 99H 77H
(Upper bits of R16003)

b15 b8 b7 b0
R16000 54H 10H
R16001 4AH BAH
R16002 ABH 80H
R16003 01H 77H

7-393
 ADRSET(P)

7.18.6 Indirect address read operations (ADRSET(P))

ADRSET(P)

Basic High
performance Process Redundant Universal LCPU

Command
ADRSET ADRSET S D

Command
ADRSETP ADRSETP S D

S : Number of the device whose indirect address is read out (Device name)
D : Number of the device where the indirect address of the device designated by S will be stored (BIN 32 bits)

Setting Internal Devices J \

R, ZR U \G Zn Constants Other
Data Bit Word Bit Word

S ––

D ––

Function
(1) Stores the indirect address of the device designated by S at D +1 and D .
The address stored at the device designated by D is used when an indirect device address
is performed by the sequence program.

ADRSET W100 D100 Stores the address of W100 address to D101 and D100.

MOV K1234 @D100

Writes 1234 to the address
specified by D100 and D101.
Reads the contents of D100.

Device area
D0
D1

D100
Address of W100
D101 W100 1234

(2) A bit device designation cannot be made at S .

Operation Error
(1) There are no operation errors associated with the ADRSET(P) instruction.

Remark
See Section 3.4 for further information on indirect designations.

7-394
 KEY

7.18.7 Numerical key input from keyboard (KEY)

KEY
1
High
2
Basic performance Process Redundant Universal LCPU

Command
3
KEY KEY S n D1 D2

4
S : Head number of the devices (X) to which a numeral will be input (bits)
n : Number of digits of the numeral to be input (BIN 16 bits)
: Head number of the devices where the input numeral will be stored (BIN 16 bits)
6
D1

D2 : Number of the bit device to turn ON at the completion of input (bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S (Only X) –– –– –– –– 6
n ––

–– –– –– ––
7
D1

D2 –– ––

8
Function
(1) Fetches ASCII data from the 8 points of input (X) designated by S , converts it to
hexadecimal values and stores the result in the area starting from the device designated by

7.18.7 Numerical key input from keyboard (KEY)

7.18 Other instructions
D1 .
Designation of
n the number of Input module
digits to be input
S
S +1
S +2
S +3 "0" (30H) to "9" (39H)
b15 b12 b11 b8b7 b4 b3 b0 S +4
S +5 "A" (41H) to "F" (46H)
D1 Number of digits that are input
S +6
D1 +1 5 digits 6 digits 7 digits 8 digits S +7
D1 +2 1 digit 2 digits 3 digits 4 digits S +8 Strobe signal

For example, in a case where the number of digits (n) has been set at 5, and the values "31",
"33", "35", "37" and "39" have been input through X10 to X18 of the input module, the
following will take place:
Number of digits
5 Input module
of input data D0
The first input value
X10
X11
X12
b15 b12b11 b8 b7 b4 b3 b0 X13 " 1 3 5 7 9 "
X14 (31H)(33H)(35H)(37H)(39H)
D10 5 X15
X16
D11 3H 5H 7H 9H X17
D12 0H 0H 0H 1H X18 Strobe signal

7-395
 KEY

(2) Numerical input to input (X) designated by S undergoes bit development at S through
S +7 and is input as the ASCII code corresponding to the numbers.
ASCII code which can be input is from 30H (0) to 39H (9), and from 41H (A) to 46H (F).
(3 H) (1 H)
Input module
b7 b4 b3 b0
"1"(31 H)= 0 0 1 1 0 0 0 1
S
S +1
S +2
S +3
S +4
S +5
S +6
S +7

(3) After ASCII code is input to S to S +7, the strobe signal at S +8 goes ON to incorporate the
designated numbers internally.
The strobe signal should be held at its ON or OFF status for more than one scan of the
sequence program.
If this time is less than 1 scan, there will be cases when the data is correctly incorporated.

Execution command
Condition contact for ON for 1 scan OFF for 1 scan
the execution of KEY or longer or longer
instruction

Strobe signal ( S +8)

ASCII code input
31H 32H 33H 34H
( S to S +7)

Fetches "1" Fetches "2" Fetches "3" Fetches "4"

(4) Be sure to keep the execution command (condition contact for the KEY instruction) ON until
the specified number of digits has been input.
The KEY instruction cannot be executed if the execution command turns OFF.

(5) The digits for the numbers actually fetched to D1 will be stored at the device designated by
D1 , and these will be converted to the ASCII codes input at D1 +1 and D1 +2, converted to
hexadecimal BIN values, and stored.

Execution command
Condition contact for the
execution of KEY instruction
Strobe signal ( S 8)

ASCII code input

31H 33H 35H 37H 39H
( S to S 7)

D1 1 2 3 4 5
D1 1 0 0 0 1 0 0 1 3 0 1 3 5 1 3 5 7 3 5 7 9
D1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

(6) The number of digits that can be designated by n is from 1 to 8.

7-396
 KEY

(7) Fetching of the input data is completed when any of the inputs shown below has been made.
At the completion, the bit device designated by is turned ON.
D2
1
• When the number of digits specified by n has been input
• When the "0DH" code has been input
For example, the operations at the location designated if n 5 will be as indicated below: 2

Execution command
3
Strobe signal
( S +8)
ASCII code input
When the
designated ( S to S +7)
31H 42H 35H 37H 39H
4
number of digits
are input
D1 1 2 3 4 5
D1 +1 0 0 0 1 0 0 1 B 0 1 B 5 1 B 5 7 B 5 7 9 6
D1 +2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Processing
completed ( D2 ) 6

Execution command 7
Strobe signal
( S +8)
When 0DH code
is input
ASCII code input
( S to S +7)
31H 42H 35H 0DH 8

D1 1 2 3 3
D1 +1 0 0 0 1 0 0 1 B 0 1 B 5 0 1 B 5
D1 +2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

7.18.7 Numerical key input from keyboard (KEY)

7.18 Other instructions
Processing
completed ( D2 )

If input processing is to be performed a second time, it is necessary to clear the number of

digits input and the input data stored at D1 , and turn OFF the designated device at the user
program.
If D1 is not cleared and D2 not turned OFF, the next input processing cannot be performed.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The device designated by D is not an input (X) device. (Error code: 4100)
• The number of digits designated by n are outside the range of from 1 to 8.
(Error code: 4100)

7-397
 KEY

Program Example
(1) The following program fetches data of the 5 or fewer digits from the numerical key pad
connected to X20 to X28, and stores it to the area starting from D0 when X0 is turned ON.
[Ladder Mode]

Clears the previous input data

Sets the number of digits to be input

Resets the data input completion fag

[List Mode]

Step Instruction Device

[Operation]
Input module

X20
" 1 2 3 4 5" X21
X22 b15 b12b11 b8 b7 b4 b3 b0
X23 D0 5
X24 D1 2H 3H 4H 5H
X25 D2 0H 0H 0H 1H
X26
Numerical keypad X27
(Strobe signal) X28

7-398
 ZPUSH(P),ZPOP(P)

7.18.8 Batch save or recovery of index register

(ZPUSH(P),ZPOP(P)) 1
ZPUSH(P),ZPOP(P)

Basic High
performance Process Redundant Universal LCPU
2

Command
indicates an instruction symbol of ZPUSH/ZPOP.
4
ZPUSH, ZPOP D

ZPUSHP, ZPOPP
Command
P D
6

D : Head number of the devices to/from which contents of an index register are saved/recovered (BIN 16 bits)
6
Setting Internal Devices J \
R, ZR U \G Zn Constants Other
Data Bit Word Bit Word

D –– ––
7

8
Function
ZPUSH

(1) Saves the contents of the following index registers to after the device specified by .

7.18.8 Batch save or recovery of index register (ZPUSH(P),ZPOP(P))

7.18 Other instructions
D

(When contents of an index register are saved, D + 0 (the number of saves made) is
increased by 1.)
• Basic model QCPU: Z0 to Z9
• High Performance model QCPU/Process CPU/Redundant CPU:
Z0 to Z15
• Universal model QCPU/LCPU: Z0 to Z19
(2) The ZPOP instruction is used for data recovery. Nesting is possible within the ZPUSH to
ZPOP cycle.
(3) If nesting has been done, each time the ZPUSH instruction is executed, the field used
following D will be added to, so a field large enough to accommodate the number of times
the instruction will be used should be maintained from the beginning.
(4) The composition of the field used following D is as shown below:
• When Basic model QCPU is used
D +0 Number of saves
+1 Z0
+2 Z1
1st nesting
(15 words for the 1st nesting)
+10 Z9
+11 Reserved by the
+15 system (5 words)
+16 Z0
+17 Z1
2nd nesting

7-399
 ZPUSH(P),ZPOP(P)

• When using a High Performance model QCPU/Process CPU/Redundant CPU

D +0 Number of saves
+1 Z0
+2 Z1
1st nesting
(18 words for the 1st nesting)
+16 Z15
+17 Reserved by the
+18 system (2 words)
+19 Z0
+20 Z1
2nd nesting

• When using Universal model QCPU/LCPU

D +0 Number of saves
+1 Z0
+2 Z1
1st nesting
(22 words for the 1st nesting)
+20 Z19
+21 Reserved by the
+22 system (2 words)
+23 Z0
+24 Z1
2nd nesting

ZPOP
(1) Recovers the contents saved in the area starting from the device designated by D to the
index register. (When the saved content is read out to the index register, D + 0 (the number
of saves made) is decreased by 1.)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The range for the number of points to be used at D and later by the ZPUSH(P) instruction
exceeds the corresponding device range. (Error code: 4101)
• The contents of D + 0 (number of saves made) is 0 in the ZPOP(P) instruction.
(Error code: 4100)

Program Example
(1) The following program saves the contents of the index register to the fields following D0
before calling the subroutine following P0 that uses the index register.
[Ladder Mode] [List Mode]
Step Instruction Device

7-400
 UNIRD(P)

7.18.9 Reading Module Information (UNIRD(P))

UNIRD(P)
1
Basic High
performance Process Redundant Universal LCPU
2

3
Command
UNIRD UNIRD n1 D n2

Command 4
UNIRDP UNIRDP n1 D n2

n1 : Value obtained by dividing the head I/O number of the reading module information source by 16 (0 to FFn) 6
(BIN 16 bits)
D : Head number of the devices where the module information will be stored (device name)
n2 : The number of points of read data (0 to 256) (BIN 16 bits)

Setting Internal Devices J \ Constants

6
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

n1 –– ––

D –– –– –– ––
7
n2 –– ––

8
Function
(1) Reads the module information as much as designated by n2 from the module designated by
n1 (value obtained by dividing the head I/O number by 16), and stores that information into

7.18.9 Reading Module Information (UNIRD(P))

7.18 Other instructions
the area starting from the device designated by D .
(Reads the status of the actually installed modules instead of the module type designated by
I/O assignment.)

7-401
 UNIRD(P)

Remark
The value of n1 is designated by the higher 3 digits of the head I/O number of the
slot from which the module information is read, when it is expressed in 4 digits in
hexadecimal notation.
QCPU

Power
Q68 QY41
supply CPU QX10 QX10 QX10 QX10 QY10 QY10
ADV P
module

0000H 0010H 0020H 0030H 0040H 0050H 0070H 0080H Head I/O number configured in
the I/O assignment setting

Specify the head I/O number to be read

by K4 or H4.

LCPU
CPU module
(L26CPU-BT)

Power
supply CPU Built-in Built-in LX40 LX40 LX40 LX40 L60 LY10 LY10 LY10
module I/0 CC-Link C6 C6 C6 C6 AD4 R2 R2 R2

0000H 0010H 0030H 0040H 0050H 0060H 0070H 0090H 00A0H 00B0H Head I/O number
configured in the
I/O assignment
setting
Specify the head I/O number to be read
by K6 or H6.

7-402
 UNIRD(P)

The details of the module information are described as follows:

Bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 1

Individual module
information

Meaning 2
Bit Item
QCPU LCPU
b0 000: 16 points 001: 32 points

b1 Number of I/O points

010: 48 points 011: 64 points 3
100: 128 points 101: 256 points
b2 110: 512 points 111: 1024 points
b3 000: Input module
001: Output module
000: Input module
001: Output module
4
b4 Module type
010: I/O mixed module 011: Intelligent function module
b5 011: Intelligent function module 111: CPU Built-in I/O

b6
External supply power status 1: External supply power is connected.0:
Fixed to 0
6
(For future expansion) External supply power is not connected.
Presence/absence of fuse 1: Some modules have fuse blown.0:
b7 Fixed to 0
blown Normal
6
1: Module information on the extension
Online module replacement base unit is tried to be read during
status/ online module change or from the
b8
execution from the standby CPU module of standby system in the
Fixed to 0 7
system redundant system.*1
0: Other than above

b9 Minor/medium error status 1: Minor/medium error occurred 0: Normal 8

b10 00: No module error 01: Minor error
Module error status
b11 10: Medium error 11: Serious error

b12 Module standby status 1: Normal 0: Module error occurred

7.18.9 Reading Module Information (UNIRD(P))

7.18 Other instructions
b13 Empty Fixed to 0

b14 Q module 1: A series module 0: Q series module Fixed to 0

b15 Module installation status 1: Modules are installed. 0: No modules are installed.

*1: The Universal model QCPU used in the multiple CPU system is turned ON during the online
module change of the module controlled by the other CPU.

7-403
 UNIRD(P)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
[High Performance model QCPU, Process CPU, Redundant CPU and Universal model
QCPU, L26CPU-BT]
• When n1 is other than 0 to FFH (Error code: 4100)
• When n2 is other than 0 to 256 (Error code: 4100)
• When a total of n1 and n2 is equal to or greater than 257 (Error code: 4100)
[Q00/Q01CPU/L02CPU]
• When n1 is other than 0 to 3FH (Error code: 4100)
• When n2 is other than 0 to 64 (Error code: 4100)
• When a total of n1 and n2 is equal to or greater than 65 (Error code: 4100)
[Q00JCPU]
• When n1 is other than 0 to FH (Error code: 4100)
• When n2 is other than 0 to 16 (Error code: 4100)
• When n1 and n2 is equal to or greater than 17 (Error code: 4100)
[QCPU/LCPU]
• When the number of points specified by n2 for the devices specified in (D) and below is
outside the range of that device. (Error code: 4101)

7-404
 UNIRD(P)

Program Example
1
(1) The following program stores the module information at I/O numbers 10H to 20H into the
devices starting from D0 when X10 is turned ON.
Card information Device
2
X/Y0 module information D0
X/Y10 module information
X/Y20 module information
D1
3
:
X/YFE0 module information
X/YFF0 module information
4
[Ladder Mode] [List Mode]
Step Instruction Device
6

6
Readout result (When read to D0)

(a) 32-point intelligent function module for Q series 7

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
D0 1 0 0 1 0 0 0 0 0 0 0 1 1 0 0 1

32-point module 8
Intelligent function module
No external power supply connected
No blown-fuse error existing

7.18.9 Reading Module Information (UNIRD(P))

7.18 Other instructions
Execution other than during online module
change or from the standby system
No module error existing

Module ready status

(Empty)
Q series module
Module installed

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

D1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

All of these bits turn 0 because information is stored to "D0."

A module is installed as latter 16 points of a 32-point module.

• With a 48- or 64-point module, the same contents as those of D1 are stored in D2 or D2
and D3 respectively.

7-405
 UNIRD(P)

(b) 32-point module for A series

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

D0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0

For an A series module, all of these bits turn 0 because information is not stored.

A series module

Module is installed

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

D1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

All of these bits turn 0 because information is stored to "D0."

A module is installed as latter 16 points of a 32-point module.

• With a 48- or 64-point module, the same contents as those of D1 are stored in D2 or D2
and D3 respectively.

(c) Empty slot

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

For an empty slot, all of these bits turn 0.

(d) Performing online module replacement

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

D0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0

Performing online module replacement

(e) Module information on the extension base unit is tried to be read from the standby
system of the redundant system in separate mode.

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

D0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0

Execution from the standby system

(Module information on the extension base unit is tried
to be read from the standby system of the redundant
system in separate mode.)

7-406
 UNIRD(P)

(6) L series 32-point intelligent function module

D0
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
1 0 0 1 0 0 0 0 0 0 0 1 1 0 0 1
1
32-point module
Intelligent function module 2
(Empty)
(Empty)
(Empty) 3
No module errors
Module preparation complete
(Empty)
4
Module connected

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 6

D1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

6
All 0, because information is stored in "D0".

The module is mounted as the second 16 points of a 32-point module

7.18.9 Reading Module Information (UNIRD(P))

7.18 Other instructions

7-407
 7.18.10 Reading module model name (TYPERD(P))

Ver.
High
Basic performance Process Redundant Universal LCPU

Universal model QCPU: The serial number (first five digits) is "11043" or later.

Command
TYPERD TYPERD n D

Command
TYPERDP TYPERDP n D

.
Setting Internal device J \ Constant
R, ZR U \G Zn Others
data Bit Word *6 Bit Word K, H

n –– –– ––

D –– –– –– ––

Set Data

Setting data Description Setting range Set by Data type

Value obtained by dividing the start I/O number of a module 0 to FFH,
n User BIN 16 bits
whose model name is to be read by 16 3E0 to 3E3H *1

D +0 Execution result of the instruction Within each BIN 16 bits

D System
D +1 to D +9 Module model name device range Character string

*1: Universal model QCPU only.

Function
(1) This instruction reads the module information stored in the area starting from the I/O number
specified by "n", and stores it in the area starting from the device specified by D .
The following 6 modules (Q series only) support the instruction.
• CPU module
• Input module
• Output module
• I/O combined module
• Intelligent function module
• GOT (bus connection)
For the LCPU, the following four models are supported.
• CPU module
• Input module
• Output module
• Intelligent function module

7-408
(2) Specify the start I/O number of a module whose model name is to be read by "n" as follows:
• Specify the value obtained by dividing the start I/O number of the target module by 16.
Universal model QCPU
1

Power CPU
supply module QX10 QX10 QX10 QX10
Q68 QY41
QY10 QY10
2
ADV P
module

3E00H 0000H 0010H 0020H 0030H 0040H 0050H 0070H 0080H Start I/O number configured in 3
the I/O assignment setting

Specify the start I/O number by K3 or H3.

When the target module is a CPU module itself, 4

specify the start I/O number by H3E0.

LCPU (L26CPU-BT)
6
Power
supply CPU Built-in Built-in LX40 LX40 LX40 LX40 L60A LY10 LY10 LY10
module I/0 CC-Link C6 C6 C6 C6 D4 R2 R2 R2
6
0000H 0010H 0030H 0040H 0050H 0060H 0070H 0090H 00A0H 00B0H Head I/O number
configured in the

7
I/O assignment
setting
Specify the head I/O number to be read
by K6 or H6.
Specify H3E0 to read the module name of the CPU module.
8
1. On the LCPU, if the built-in I/O or first I/O on the built-in CC-Link is specified,
then the model name of the CPU module is read.

7.18.10 Reading module model name (TYPERD(P))

7.18 Other instructions
• When the target module occupies two slots
The start I/O number to be specified may differ from that of the mounted module.
For the start I/O number, refer to the manual of each module.
Specify the value obtained by dividing the start I/O number of the target module by 16.

Example) QJ71GP21S-SX
Specify a value to which 0010H, start I/O number of the mounted module, is added.

Power
supply CPU QJ71G P21S-SX Empty Empty Empty Empty Empty Empty
module module

3E00H 0000H 0010H 0030H 0040H 0050H 0060H 0070H 0080H Start I/O number configured in
the I/O assignment setting

Specify the start I/O number by K1 or H1.

7-409
 • When the target module is a CPU module in multiple CPU systems
Specify the value obtained by dividing the start I/O number of the target CPU module by
16.

Power
Q20UDH Q20UDH Q20UDH QY41 Q68 QY41
supply CPU QY10 QY10
CPU CPU CPU P ADV P
module module

3E00H 3E10H 3E20H 3E30H 0000H 0010H 0020H 0030H 0040H Start I/O number configured in
the I/O assignment setting

Specify the start I/O number by H3E3.

Or, the model name can be read by specifying the start I/O number of a module controlled
by another CPU.

(3) D +0 and D +1 to D +9 store the execution result of the instruction and module model
name, respectively.
A value stored in D is as follows:

(a) When the model name has been written to the target module (example: QJ71GP21-SX)
b15 to b8 b7 to b0

○+0
D 0 Stores 0.
○+1
D 4AH (J) 51H (Q) Indicates that the model name
that has been written to
Nine words are used. ○+2
D 31H (1) 37H (7) the target module is stored.

○+3
D 50H (P) 47H (G) Stores the model name that has been
written to the target module
○+4
D 31H (1) 32H (2) (stored in ASC II).
○+5
D 53H (S) 2DH (-)
○+6
D 00H 58H (X)

○+7
D 00H 00H
00H 00H Stores the remaining model name and
○+8
D
00H to the 12th to 17th devices and
○+9
D 00H 00H the 18th device, respectively.

The following table shows the examples of model names stored in D +1 to D +9.
Target module Stored model name
CPU module Q06UDEHCPU
Intelligent function module QJ71GP21-SX
GOT GOT1000

7-410
(b) When the model name has not been written to the target module (example: QX40)
b15 to b8 b7 to b0 1
○+0
D 1 Stores 1.
○+1
D 4AH (N) 49H (I) Indicates that the character
string consists of module type and
Nine words are used. ○+2
D 55H (U) 50H (P) the number of points is stored. 2
○+3
D 5FH (_) 54H (T) Stores the character string consists
of module type and the number of points.
○+4
D 36H (6) 31H (1) (stored in ASC II).
○+5
D 00H 00H
3
○+6
D 00H 00H
○+7
D 00H 00H
○+8
D 00H 00H Stores the remaining model name and
00H to the 12th to 17th devices and 4
○+9
D 00H 00H the 18th device, respectively.

The following table shows the examples of character strings stored in D +1 to D +9.. 6
Target module Stored character string
Input module INPUT_16
Output module OUTPUT_32 6
I/O combined module MIXED_64
Intelligent function module INTELLIGENT_128

[Character string indicating module type]

7
• Input module: INPUT
• Output module: OUTPUT 8
• I/O combined module: MIXED
• Intelligent function module*1: INTELLIGENT
• 1: Includes the QI60 and GOT.

7.18.10 Reading module model name (TYPERD(P))

7.18 Other instructions
[Character string indicating the number of points]
• 16 points:_16
• 32 points:_32
• 48 points:_48
• 64 points:_64
• 128 points:_128
• 256 points:_256
• 512 points:_512
• 1024 points:_1024

7-411
 (c) Others
• The specified slot is empty or the target module is during online module change.
• The specified value (n) is not the start I/O number.
• The specified value (n) is within the allowable setting range, but cannot be set in the
I/O assignment setting screen of the PLC parameter dialog box.
b15 to b8 b7 to b0

○+0
D -1 Stores -1.
○+1
D Indicates that the model
00H 00H
name is not stored.
Nine words are used. ○+2
D 00H 00H
○+3
D 00H 00H

○+4
D 00H 00H
○+5
D 00H 00H
○+6
D 00H 00H
○+7
D 00H 00H
○+8
D 00H 00H Stores 00H.

○+9
D 00H 00H

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an
error code is stored into SD0.
• The target module cannot be communicated due to a failure. (Error code: 2110)

• Devices by 10 words starting from the device specified by D exceed the device range.
(Error code: 4101)
• The specified value (n) is except 0 to FFH and 3E0 to 3E3H. (Universal model QCPU)
(Error code: 4101)
• The specified value (n) is except 0 to FFH and 3E0H. (LCPU)
(Error code: 4101)

Program Example
(1) The following program stores the model name of a module having the start I/O number
0020H in the area starting from the device specified by D when X0 is turned on.
[Ladder Mode] [List Mode]
Step Instruction Device

7-412
 TRACE,TRACER

7.18.11 Trace Set/Reset (TRACE,TRACER)

TRACE,TRACER
1
Ver.
High
2
Basic performance Process Redundant Universal LCPU

Universal model QCPU: Other than Q00UJCPU

3
Command
TRACE TRACE

Command 4
TRACER TRACER

6
Setting Internal Devices J \
R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
–– ––
6
Function
7
The sampling trace function collects the specified device data of a CPU module consecutively at
the specified timing.
With the sampling trace function, the traced results obtained through the specified number of 8
trace operations will be stored in the trace file when SM800, SM801, and SM802 are turned ON.
Trace ends by
TRACE number of trace TRACER
Trace start request Trigger condition enabled after trigger Trace reset

7.18.11 Trace Set/Reset (TRACE,TRACER)

7.18 Other instructions
Number of trace
after trigger

Total number of traces

SM800
(Preparation for trace)

SM801
(Starting trace)

SM802
(During the execution of trace)

SM803
(Trigger for trace)

SM804
(After the execution of trace
trigger)

SM805
(Completion of trace)

7-413
 TRACE,TRACER

TRACE
(1) The TRACE instruction turns ON SM803, executes sampling by the number of times set for
"After trigger number of times" in the Trace condition settings, latches the data and stops
sampling trace.
(2) The sampling is stopped if SM801 is turned OFF during the trace execution.
(3) After the TRACE instruction is executed and the trace is completed, SM805 is turned ON.
(4) Once the TRACE instruction is executed, the second and the subsequent TRACE
instructions are ignored.
When the TRACER instruction is executed, the TRACE instruction is enabled again.

TRACER
(1) The TRACER instruction resets the TRACE instruction. When the TRACER instruction is
executed, the TRACE instruction is enabled again.
(2) When the TRACER instruction is executed, SM803 to SM805 are turned OFF.

Remark
1. For details of the trace, refer to the QnUCPU User's Manual (Function
Explanation, Program Fundamentals) or Qn(H)/QnPH/QnPRHCPU User's
Manual (Function Explanation, Program Fundamentals).
2. For trace execution with Programinng Tool, refer to the Operating Manual.

Operation Error
(1) There are no operation errors associated with the TRACE or TRACER instruction.

Program Example
(1) The following program executes the TRACE instruction when X0 is turned ON, and resets
the TRACE instruction with the TRACER instruction when X1 is turned ON.
[Ladder Mode] [List Mode]
Step Instruction Device

7-414
 SP.FWRITE

7.18.12 Writing Data to Designated File (SP.FWRITE)

SP.FWRITE
1
Ver.
High
2
Basic performance Process Redundant Universal LCPU

Universal model QCPU: Other than Q00UJCPU/Q00UCPU/Q01UCPU

3
Command
SP.FWRITE SP.FWRITE U0 S0 D0 S1 S2 D1

4
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H $

S0 –– –– ––
6
D0 –– –– –– –– ––

S1 –– –– –– –– –– 6
S2 –– –– –– ––

D1 *1 *1 –– –– –– ––
*1: Local devices and the devices designated for individual programs cannot be used. 7

Setting
Meaning Setting Range Set by Data Type
8
Data
U0 Dummy –– ––

S0 Drive designation 2 User

Head number of the devices storing the control data. The following control data is required.

7.18.12 Writing Data to Designated File (SP.FWRITE)

7.18 Other instructions
Device Item Contents/Setting Data Setting Range Set by
Execution/ Designate the execution type.
0000H
D0 completion 0000H : Write binary data
0100H User
type 0100H : Write data after CSV format conversion
D0 +1 (Not used) Used by system –– System
Writing Contains the number of actually written data
result (No. against the data designated by S2 . The unit
D0 +2 –– System
of written of the value depends on data type specified at
data) D0 +7.

D0 +3 (Not used) –– –– ––
Set the file position when binary data writing
is specified by D0 .
BIN 16 bits
00000000H :Starting at the beginning of the file
D0 00000001H to FFFFFFFEH:
From the specified position
The unit of the value depends
on data type specification.
FFFFFFFFH : Addition starts from the end
of the file.
When CSV format write is specified at D0
D0 +4 File • For the High Performance model QCPU of 00000000H to
which the first 5 digits of the serial number User
D0 +5 position FFFFFFFFH
are "01111" or lower, always set the
beginning (0H) of the file.
• For the High Performance model QCPU/
Process CPU/Redundant CPU/Universal
model QCPU of which the first 5 digits of
the serial number are "01112" or higher, set
the file position.
00000000H to FFFFFFFEH
: Starting at the beginning of
the file
FFFFFFFFH : Addition starts at the end of the file.

7-415
 SP.FWRITE

Setting
Meaning Setting Range Set by Data Type
Data

When binary write is specified at D0 , always

set 0.
When CSV format write is specified at D0 ,
No. of set the number of columns where data will be 0H to
D0 +6 columns written. FFFFH User
D0 designation 0 : No columns. Regarded as (0 to 65535)
one row.
Other than 0 : Set to the specified number of
columns.
Data type 0: Word
D0 +7 0,1 User
specification 1: Byte
Head number of the devices storing a file name. A file name is expressed as follows:
Device Item Contents/Setting Data Setting Range Set by
Designate the character string of a file name.
• When omitting an extension, also omit
the "." (Period). BIN 16 bits
S1 File name • Limit the file name within 8 characters +
S1 to Character
character period + 3 characters. User
S1 + string
string • When 9 or more characters are used,
the extension is ignored regardless of its
presence, and "BIN" or "CSV" is
automatically assigned as an extension.
Head number of the devices storing the data. Written data is expressed as follows:
Device Item Contents/Setting Data Setting Range Set by
Designate the number of data to request
No. of writing (word units).
1 to 480
S2 S2 request This data should be designated in units of
words even when byte is designated by 1 to 32767 *2
write data User
D0 +7.

S2 +1 to 0000H to
Write data Data to request writing.
S2 + FFFFH

Bit device that turned ON at the completion of the processing.

( D1 +1 is also turned ON at error completion.)
Device Item Contents/Setting Data Setting Range Set by
Completion Indicates the completion of the processing.
D1 ––
D1 signal ON: Completed OFF: Not completed Bit

Indicates whether the processing is normally

Error System
completed or abnormally completed.
D1 +1 completion ––
ON: Error completion
signal
OFF: Normal completion

*2: Indicates the range applicable only for the Universal model QCPU and LCPU.

7-416
 SP.FWRITE

Caution 1
(1) For only QCPU, only the ATA card drive (2) can be set as S0 (drive designation).
Note that when the Flash card is loaded, the SP.FWRITE instruction cannot be used to
perform writing.
2
The SRAM card, standard RAM or standard ROM drive cannot be set.
For only LCPU, only the SD memory card drive (2) can be set as (drive designation).
S0
3
(2) For CSV setting, the data written are decimal values.
Example Character "A" (41H) "65" is written.
Handling range: -32768 to 32767
4
(3) For binary write, the word-specified file position setting range is 00000000H to 7FFFFFFFH
and FFFFFFFFH.
6

7.18.12 Writing Data to Designated File (SP.FWRITE)

7.18 Other instructions

7-417
 SP.FWRITE

Function
(1) The designated number of data is written to the designated file.
Set the execution/completion type in the control data to designate whether to write binary
data without any conversion or to convert binary data into CSV format data before writing it.
(For QCPU, writing is only supported for ATA cards. For LCPU, it is only supported for SD
memory cards.)

(2) The execution completion bit device ( D1 ) is automatically turned ON at the END processing
after the completion of the instruction is detected. The bit device is turned OFF at the
execution of the END instruction in the next scan.
Use this bit device as the execution completion flag for the SP.FWRITE instruction.
When this instruction is completed abnormally, the error completion device ( D1 +1) is turned
ON/OFF in synchronization with the processing complete ( D1 ) device. Use this device as the
error completion flag for this instruction.
SM721 is turned ON during the execution of the instruction.
This instruction cannot be executed while SM721 is ON. (If an attempt is made, no
processing is performed.)
When an error is detected at the execution of the instruction (before SM721 is turned ON),
the processing complete device ( D1 ), the error completion device ( D1 +1), and SM721 are
not turned ON.

(3) Be sure to use in units of words to designate the No. of request write data ( S2 ) and the file
position ( D0 +4 and D0 +5).
The following shows the method for writing binary data when No. of request write data and
file position are specified.
Control data
D0+0 H0000 Execution/completion type
D0+1 - (Not used)
D0+2 K3 Number of written
result data
D0+3 - (Not used)
D0+4 K1
Head position of the file to be written
D0+5
D0+6 - Designation of the number of columns
D0+7 K0 Data type specification

Data device File data (in byte unites)

D1+0 K3 H00
One word
H00 shift
D1+1 H33 22 H22
Total H33
D1+2 H55 44 H44
Data to
be written H55
D1+2 H77 66 H66
H77
H00
H00
H00

7-418
 SP.FWRITE

(4) When writing binary data

(a) If the extension of the target file is omitted, ".BIN" is used as an extension.
1
(b) When the designated file does not exist, a new file is created and the data is added/
saved from the beginning of the file.
The attributes of this new file are set using the archive attributes.
2
(c) When the size of the data exceeds that of the existing area in the file during the writing,
the excess data is added/saved.
(d) If the file position specified is greater than the existing file size: 3
• The High Performance model QCPU of which the first 5 digits of the serial number
are "01111" or lower results in an error.
• The High Performance model QCPU/Process CPU/Redundant CPU/Universal 4
model QCPU/LCPU of which the first 5 digits of the serial number are "01112" or
higher performs writing at point 0 and is completed normally.

(e) An error occurs when the saving space becomes full while data is added and saved.
6
In such a case, the data that is successfully added/saved remains in the medium.
The error completion is indicated after as much data as possible is added/saved.
(5) When writing data after CSV format conversion
6
(a) If the extension is omitted, ".CSV" is used as an extension.
(b) When the existing file is specified: 7
[High Performance model QCPU of which the first 5 digits of the serial number are
"01111" or lower]
File contents are all deleted and data are saved, starting at the beginning. 8
[High Performance model QCPU/Process CPU/Redundant CPU/Universal model
QCPU/LCPU of which the first 5 digits of the serial number are "01112" or higher]
• When other than FFFFFFFFH is set at ( D0 +4, D0 +5), file contents are all deleted and
data are saved, starting at the beginning.

7.18.12 Writing Data to Designated File (SP.FWRITE)

7.18 Other instructions
• When FFFFFFFFH is set at ( D0 +4, D0 +5), data are saved, starting at the end of the
file.
(c) When the designated file does not exist, a new file is created and the data is added/
saved from the beginning of the file.
The attributes of this new file are set using the archive attributes.
(d) An error occurs when the saving space becomes full while data is added and saved.
In such a case, the data that is successfully added/saved remains in the medium.
The error completion is indicated after as much data as possible is added/saved.

7-419
 SP.FWRITE

(e) When the designated number of columns is "0", the data is stored as single-row data in
CSV format file.

Example
When data is written after CSV format conversion and the designated No. of columns is
"0":

SP.FWRITE U0 K2 D10 D20 D99 M0 * Designation in word units

D10 H0100 Execution/completion type

D11 - Not used
D12 K0 Number of written result data (In normal completion,
it is the same number as the number of data to be written.)
D13 - Not used
D14 K0
D15 K0
D16 K0 Designation of the number of columns
D17 K0 Data type specification

File name (If a file name consists of 8 or less

D20 H4241 characters, "00"s are filled in the remaining area.)
D21 H4443 "ABCDE"
D22 H0045

Number of data to be written

D099 K7
Data to be written
D100 K0
D101 K10
D102 K20
D103 K30
D104 K40
D105 K-50
D106 K100

Data to be written to the file

0 , 10 , 20 , 30 , 40 , -50 , 100 CR LF

Data to be read out to EXCEL file

7-420
 SP.FWRITE

(f) When data is written after CSV format conversion and the designated number of
columns is other than "0", the data is stored as table data with designated number of
columns in a CSV format file.
1

Example
2
When data is written after CSV format conversion and the designated No. of columns is
other than "0":

SP.FWRITE U0 K2 D10 D20 D99 M0

3
* Designation in word units

4
D10 H0100 Execution/completion type
D11 K0 In the module
D12 K0 Number of written result data (In normal completion,
it is the same number as the number of data to be written.) 6
D13 K0 Not used
D14 K0
D15 K0 6
D16 K3 No. of columns designation
D17 K0 Data type specification

7
D20 H4241 File name
D21 H4443 "ABCD"
D22 H0000 8
Number of data to be written
D099 K7
Data to be written
D100 K0
D101 K10

7.18.12 Writing Data to Designated File (SP.FWRITE)

7.18 Other instructions
D102 K20
D103 K30
D104 K40
D105 K-50
D106 K100

Data to be written to the file

0 , 10 , 20 CR LF
30 , 40 , -50 CR LF
100 CR LF

Data to be read to EXCEL file

7-421
 SP.FWRITE

(g) When data is added by the High Performance model QCPU/Process CPU/Redundant
CPU/Universal model QCPU/LCPU of which the first 5 digits of the serial number are
01112 or higher:

[Specify the file to which data will be written.] (If a file exists, delete it and create a new
file again.)
Execution type = CSV format File position = 0H (New file is created)
Column designation = 4H*3*5 Write head device = D0
Data type specification = Word Number of data = 6H*3

Device data
(Data to be written)
Column Column Column Column K6 D0 Number of write points
1 2 3 4
K1 D1
Starting row Row 1 1 , 2 , 3 , 4 CR LF K2 D2
K3 D3
*3 K4 D4
Row 2 5 , 6 CR LF
K5 D5
K6 D6
K5 D7
K7 D8
K8 D9
K9 D10
K10 D11
K11 D12
K12 D13

[In the addition mode, make addition from the end of the file.]
Execution type = CSV format File position = FFFFFFFH (Continuation mode)
Column designation = 3H*3*5 Write head device = D7
Data type specification = Word Number of data = 8H*3
Device data
(Data to be written)
K6 D0

Column Column Column Column K1 D1

1 2 3 4 *5 K2 D2
Row 1 1 , 2 , 3 , 4 CR LF K3 D3
K4 D4
K5 D5
Row 2 5 , 6 CR LF K6 D6
K8 D7 Number of write points
*4 *5 K7 D8
Present starting row Row 3 7 , 8 , 9 CR LF K8 D9
K9 D10
K10 D11
Row 4 10 , 11 , 12 CR LF K11 D12
K12 D13
*3 K13 D14
Row 5 13 , 14 CR LF K14 D15
*3: Unless the "number of write points" is set to an integral multiple of "column designation", the
column numbers will be random.
*4: Since the last data is always followed by the line feed code, addition normally starts at the
beginning of the new row in the addition mode.
*5: If, in the addition mode, "column designation" is changed from that in the previous writing, the
column numbers are shifted.

(h) Do not execute the SP.FWRITE instruction in an interrupt program.

(If execute it, the operation is not guaranteed.)

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 SP.FWRITE

(i) Below is the method for calculating the file size (total number of bytes) when a CSV
format file is written to the ATA card.
1
Total number of bytes = Total bytes excluding final line + bytes of final line

2
(Number of bytes on a line = number of columns*1 + 1 + total bytes of all data values on
line*2)
*1: For all lines but the final line, this is the specified number of columns. The number of columns on the final
line depends on the number of columns specified via the amount of data written. It is calculated as
3
follows.
(1) The number of lines excluding the final line is calculated.
Number of lines excluding final line = Amount of data in write request + number of columns 4
(remainders discarded)
(2) The number of columns in the final line is calculated.
Number of columns in final line = Amount of data in write request - number of lines excluding final
line* number of columns) 6
*2: The number of bytes for each data value is calculated as shown below.
Sign of Data
Bytes per Data Value Byte Count Range Examples
Value
6
1 to 5 (word specified) 12345: 5 bytes
Positive Num. digits
1 to 3 (byte specified) 67: 2 bytes

Negative Num. digits + 1

2 to 6 (word specified) -12345: 6 bytes 7
2 to 4 (byte specified) -67: 3 bytes

7.18.12 Writing Data to Designated File (SP.FWRITE)

7.18 Other instructions

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 SP.FWRITE

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• Drive specified by drive designation device S0 contains the medium other than the ATA
card. (QCPU) (Error code: 4100)
• Drive specified by drive designation device S0 contains the medium other than the SD
Memory card. (LCPU) (Error code: 4100)
• Values specified in control data D0 and the subsequent devices are out of the setting
range. (Error code: 4100)
• Value designated by "No. of request write data" ( S2 ) is out of the setting range, or
exceeds the device range designated by ( S2 +1) or the subsequent devices.
(Error code: 4101)
• Empty space in the ATA card is insufficient. (QCPU) (Error code: 4100)
• Empty space in the SD Memory card is insufficient. (LCPU) (Error code: 4100)
• No free space is found when an attempt is made to create a new file.
(Error code: 4100)
• Invalid device is designated. (Error code: 4004)
• Access error occurred in the ATA card. (QCPU) (Error code: 4100)
• Access error occurred in the SD Memory card. (LCPU) (Error code: 4100)
• An unusable value is set for a file name ( S1 ). (Error code: 4100)
• The attribute of a file name ( S1 ) is "read only". (Error code: 4100)

• The device specified by D0 or D1 exceeds the range of the corresponding device.

(For the Universal model QCPU, LCPU.) (Error code: 4101)

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 SP.FWRITE

Program Example
1
(1) When X10 is turned ON, the following program adds four bytes of binary data (00H, 01H,
02H, and 03H) to file "ABCD.BIN" in the memory card inserted to drive 2.
• Assume that 8 points from D0 are reserved for the control data devices. 2
[Ladder Mode]

Sets the execution/completion type 3

Sets the designation of the number of columns

Sets the file name 4

Sets the number of request write data

6
Sets the data to be written.

6
Normal completion display

7
Error completion display

[List Mode]

7.18.12 Writing Data to Designated File (SP.FWRITE)

7.18 Other instructions
Step Instruction Device

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 SP.FWRITE

(2) When X10 is turned ON, the following program creates a file named "ABCD.CSV" in the
memory card inserted to drive 1, and writes four bytes of data (00H, 01H, 02H, and 03H) as
two-column table data in CSV format.
• The written file is displayed as follows:
[Ladder Mode]

Sets the execution/completion type

Sets the designation of the number of columns

Sets the data type specified

Sets the file name

Sets the number of request write data

Sets the data to be written.

Normal completion display

Error completion display

[List Mode]
Step Instruction Device

• Assume that 8 points from D0 are reserved for the control data devices.
0 , 1 , CR LF Contents of the file to be written
2 , 3 , CR LF

Data to be read to the EXCEL file

7-426
 SP.FREAD

7.18.13 Reading Data from Designated File (SP.FREAD)

SP.FREAD
1
Ver.
High
2
Basic performance Process Redundant Universal LCPU

Universal model QCPU: Other than Q00UJCPU/Q00UCPU/Q01UCPU

Command
3
SP.FREAD SP.FREAD U0 S0 D0 S1 D1 D2

4
Setting Internal Devices J \ Constants
R, RZ U \G Zn Other
Data Bit Word Bit Word K, H $

S0 –– –– ––
6
D0 –– –– –– –– ––

S1 –– –– –– –– ––
6
D1 –– –– –– ––

D2 *1 *1 –– –– –– ––
*1: Local devices and the devices designated for individual programs cannot be used. 7

Setting
Data
Meaning Setting Range Set by Data Type 8
U0 Dummy –– ––

S0 Drive designation 2 User

Head number of the devices storing the control data

The following control data is required.

7.18.13 Reading Data from Designated File (SP.FREAD)

7.18 Other instructions
Device Item Contents/Setting Data Setting Range Set by
Execution/ Designate the execution type.
0000H
completion 0000H: Read binary data User
D0 0100H
type 0100H: Read data after CSV format conversion
BIN 16 bits
D0 +1 (Not used) Used by system –– System
D0
Designate the number of data to request
reading.
No. of (Unit: Word) 1 to 480
+2 request User
D0
read data Even when byte is specified at D0 +7 by data 1 to 32767*2
type specification, specify the value in units of
words (16 bits), not in units of bit devices.

D0 +3 (Not used) –– –– ––

*2: Indicates the range applicable for the Universal model QCPU, LCPU.

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 SP.FREAD

Setting
Meaning Setting Range Set by Data Type
Data
Designate the file position to start reading when
binary data reading is designated by D0 .
00000000H: Starting at the beginning of the file
00000001H to FFFFFFFEH
:From the designated position
The unit for the value is
determined by word/byte unit
designation.
FFFFFFFFH: Setting disabled

When CSV format read is specified at D0

• For the High Performance model QCPU of
+4 which the first 5 digits of the serial number
D0 File 00000000H to
are "01111" or lower, always set the User
position FFFFFFFFH
D0 +5 beginning (0H) of the file.
• For the High Performance model QCPU/
Process CPU/Redundant CPU/Universal
model QCPU/LCPU of which the first 5 digits
D0 of the serial number are "01112" or higher, set
the file position (Row).
00000000H: Read starts at the beginning of
the file.
00000001H to FFFFFFFEH
:Read starts at the specified row.
FFFFFFFFH: Read continues, starting at the
previous read position.
When binary read is specified at D0 , always
set 0.
When CSV format read is specified at D0 , set
No. of
the number of columns from where data will 0H to FFFFH BIN 16 bits
+6 columns User
D0 be read. (0 to 65535)
designation
0: No columns. Regarded as one row.
Other than 0: Regarded as the specified
number of columns.
Data type 0: Word
D0 +7 0,1 User
specification 1: Byte
Head number of the devices storing a file name. A file name is expressed as follows:
Device Item Contents/Setting Data Setting Range Set by
Designate the character string of a file name.
• When omitting an extension, also omit
the "." (Period).
S1 File name • Limit the file name within 8 characters +
S1 to Character
character period + 3 characters. User
S1 +
string
string • When 9 or more characters are used,
the extension is ignored regardless of its
presence, and "BIN" or "CSV" is
automatically assigned as an extension.
Head number of the devices for storing the read data.
Device Item Contents/Setting Data Setting Range Set by
Contains the number of actually read data
Reading
against the data designated by D0 +2. The
D1 result (No. of –– System
D1 unit on the value depends on data type
read data)
specification.

D1 +1 to Reading
Read data –– System
data
D1 +

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 SP.FREAD

Setting
Data
Meaning Setting Range Set by Data Type
1
Bit device that turned ON at the completion of the processing.
( D2 +1 is also turned ON at error completion.)
Device Item Contents/Setting Data Setting Range Set by 2
Indicates the completion of the processing.
Completion
D2 D2 ON: Completed –– Bit
signal
OFF: Not completed
Indicates whether the processing is normally System 3
Error
completed or abnormally completed.
D2 +1 completion ––
ON: Error completion
signal
OFF: Normal completion
4

Caution
6
(1) At S0 (drive designation), only the ATA card drive (2) can be set.(For QCPU)
Note that when the Flash card is loaded, the SP.FREAD instruction cannot be used to
perform read. 6
The SRAM card, standard RAM or standard ROM drive cannot be set.
At S0 (drive designation), only the SD Memory card drive (2) can be set.(For LCPU)
(2) For CSV setting, the data written are decimal values. 7
Example
Character "A" (41H) "65" is written.
Handling range: -32768 to 32767
8
(3) For binary read, the word-specified file position setting range is 00000000H to 7FFFFFFFH.

Function

7.18.13 Reading Data from Designated File (SP.FREAD)

7.18 Other instructions
(1) Data is read from the designated file.
Set the execution/completion type in the control data to designate whether to read binary
data without any conversion or to convert binary data into CSV format data before reading it.
(For QCPU, reading is only supported for ATA cards. For LCPU, it is only supported for SD
memory cards.)
(2) The execution completion bit device ( D2 ) is automatically turned ON at the END processing
after the completion of the instruction is detected. The bit device is turned OFF at the
execution of the END instruction in the next scan.
Use this bit device as the execution completion flag for the SP.FWRITE instruction.
When this instruction is completed abnormally, the error completion device ( D2 +1) is turned
ON/OFF in synchronization with the execution completion ( D2 ) device. Use this device as
the error completion flag for this instruction.
SM721 is turned ON during the execution of the instruction.
This instruction cannot be executed while SM721 is ON. (If an attempt is made, no
processing is performed.)
When an error is detected at the execution of the instruction (before SM721 is turned ON),
the processing complete device ( D1 ), the error completion device ( D1 +1), and SM721 are
not turned ON.

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 SP.FREAD

(3) Be sure to use word units to designate the number of request read data ( D0 +2), file position
( D0 +4 and D0 +5), and read data device size ( D1 ).
The following shows how the individual device data is read in binary data reading operation.
Control data
D0+0 H0000 Execution/completion type
D0+1 - (Not used)
D0+2 K3 Number of request read data
D0+3 - (Not used)
D0+4 K1
D0+5 Location to start reading in the file
D0+6 - Designation of columns
D0+7 K0 Data type specification

Data device File data (in byte units)

D1+0 K3 H00
H11
D1+1 H33 22 H22
Total H33
D1+2 H55 44 H44
Read data
H55
D1+3 H77 66 H66
H77
H88
H99
HAA

(4) When reading binary data

(a) If the extension of the target file is omitted, ".BIN" is used as an extension.

(b) When the designated file does not exist, an error occurs.

(c) If the position specified is greater than the existing file size:
• The High Performance model QCPU of which the first 5 digits of the serial number
are "01111" or lower results in an error.
• The High Performance model QCPU/Process CPU/Redundant CPU/Universal
model QCPU/LCPU of which the first 5 digits of the serial number are '01112' or
higher will perform reading at point 0 and will be completed normally.

(5) When reading data after CSV format conversion

(a) The elements in CSV format file (cells for EXCEL) are read by each row. The numerical
value and character strings are converted into binary data and stored in the device.
(b) If the extension is omitted, ".CSV" is used as an extension.
(c) When the designated file does not exist, an error occurs.

(d) The elements designated by the number of request read data ( D0 +2) are read from the
beginning of the file.
When the last data of the file is reached before the specified number of data are read:
• The High Performance model QCPU of which the first 5 digits of the serial number
are "01111" or lower results in an error.
• The High Performance model QCPU/Process CPU/Redundant CPU/Universal
model QCPU/LCPU whose the first 5 digits of the serial number are '01112' or higher
reads the data up to the point where the reading is possible.

7-430
 SP.FREAD

(e) When the designated number of columns is 0, the data is read by ignoring the rows in
CSV format file.
1
Example When data is read after CSV format conversion and the designated No. of
columns is 0:
2
Data created by EXCEL
3
Main / sub item Measured value
Length
Temperature 4

Data saved in the CSV format 6

Main / sub item , , Measured value CR LF
Length , 1 , 3 CR LF
Temperature , -21 , CR LF
6
Data to be read into devices

SP.FREAD U0 K2 D10 D20 D99 M0 7

Data that was read
File name

Control data
Control data
8

D10 H0100 Execution/completion type

D11 - Number of unused read data

7.18.13 Reading Data from Designated File (SP.FREAD)

7.18 Other instructions
D12 K9 Request
D13 - Not used
D14 K0
D15 K0
D16 K0 Designation of the number of columns
D17 K0 Data type specification

D20 H4241 File name

D21 H4443 "ABCDE"
D22 H0045
Loaded data
Stores the number of read data
D099 K9 Number of read result data
Main/sub item D100 K0 Conversion data (0) is stored since "Main/sub item" is nonnumeric data.
Data between , and , D101 K0 Conversion data (0) is stored since " " is nonnumeric data.
Measured value D102 K0 Conversion data (0) is stored since "Measured value" is nonnumeric data.
Length D103 K0 Conversion data (0) is stored since "Length" is nonnumeric data.
Read D104 K1
1 Since " 1 " is a numeric value, it is converted to a binary value.
data
3 D105 K3 Since " 3 " is a numeric value, it is converted to a binary value.
Temperature D106 K0 Conversion data (0) is stored since "Temperature" is nonnumeric data.
-21 D107 K-21 Since " -21 " is a numeric value, it is converted to a binary value.
Data between , and CR D108 K0 Conversion data (0) is stored since " " is nonnumeric data.

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 SP.FREAD

If the number of columns varies in each row, the data is also read by ignoring the rows.

Such file cannot be created using EXCEL. This happens when CSV file is
modified by a user.

Example If the number of columns varies in each row when the data is read:

Main / sub item , , Measured value , Excess CR LF

Length CR LF
Temperature , -21 , CR LF

Data to be read into devices

SP.FREAD U0 K2 D10 D20 D99 M0

Data that was read
File name
Control data
Control data

D10 H0100 Execution/completion type

D11 - Not used
D12 K7 Number of request read data
D13 - Not used
D14 K0
D15 K0
D16 K0 Designation of the number of columns
D17 K0 Data type specification

D20 H4241 File name

D21 H4443 "ABCD"
D22 H0000
Loaded data
Stores the number of read data
D099 K7 Number of read result data
Main/sub item D100 K0 Conversion data (0) is stored since "Main/sub item" is nonnumeric data.
Data between , and , D101 K0 Conversion data (0) is stored since " " is nonnumeric data.
Measured value D102 K0 Conversion data (0) is stored since "Measured value" is nonnumeric data.
Read
data Excess D103 K0 Conversion data (0) is stored since "Excess" is nonnumeric data.
Length D104 K0 Conversion data (0) is stored since "Length" is nonnumeric data.
Temperature D105 K0 Conversion data (0) is stored since "Temperature" is nonnumeric data.
-21 D106 K-21 Since " -21 " is a numeric value, it is converted to a binary value.

7-432
 SP.FREAD

(f) When data is read after CSV format conversion and the designated number of columns
is other than 0, the data is read as the table with designated number of columns in CSV
format file. The elements outside of the designated columns are ignored.
1

Example When data is read after CSV format conversion and the designated No. of
columns is other than "0":
2

Data created by EXCEL 3

Main / sub item Measured value
Length 4
Temperature

Data saved in the CSV format

6
Main / sub item , , Measured value CR LF
Length , 1 , 3 CR LF
Temperature , -21 , CR LF
6
Elements outside the designated
number of columns are ignored.
7
Data to be read into devices

SP.FREAD U0 K2 D10 D20 D99 M0

Data that was read 8

File name
Control data
Control data

7.18.13 Reading Data from Designated File (SP.FREAD)

7.18 Other instructions
D10 H0100 Execution/completion type
D11 - Not used
D12 K6 Number of request read data
D13 - Not used
D14 K0
D15 K0
D16 K2 Designation of the number of columns
D17 K0 Data type specification

D20 H4241 File name

D21 H4443 "ABCD"
D22 H0000
Loaded data
Stores the number of read data
D099 K6 Number of read result data
Main/sub item D100 K0 Conversion data (0) is stored since "Main/sub item" is nonnumeric data.
Data between , and , D101 K0 Conversion data (0) is stored since " " is nonnumeric data.
Length D102 K0 Conversion data (0) is stored since "Length" is nonnumeric data.
Read
data 1 D103 K1 Since " 1 " is a numeric value, it is converted to a binary value.
Temperature D104 K0 Conversion data (0) is stored since "Temperature" is nonnumeric data.
-21 D105 K-21 Since " -21 " is a numeric value, it is converted to a binary value.

7-433
 SP.FREAD

If the number of columns varies in each row, the elements outside of the designated columns are
ignored and "0" is added to the places where elements do not exist.

Example

If the number of columns varies in each row when the data is read:

Main / sub item , , Measured value , Excess CR LF

Length CR LF
Temperature , -21 , CR LF Elements outside the designated
number of columns are ignored.

Data to be read into devices

SP.FREAD U0 K2 D10 D20 D99 M0

Data that was read

File name
Control data
Control data

D10 H0100 Execution/completion type

D11 - Not used
D12 K6 Number of request read data
D13 - Not used
D14 K0
D15 K0
D16 K2 Designation of the number of columns
D17 K0 Data type specification

D20 H4241 File name

D21 H4443 "ABCD"
D22 H0000
Loaded data
Stores the number of read data
D099 K6 Number of read result data
Main/sub item D100 K0 Conversion data (0) is stored since "Main/sub item" is nonnumeric data.
Data between , and , D101 K0 Conversion data (0) is stored since " " is nonnumeric data.

Read Length D102 K0 Conversion data (0) is stored since "Length" is nonnumeric data.
data No data D103 K0 No data Since no element exists here, conversion data (D) is added.
Temperature D104 K0 Conversion data (0) is stored since "Temperature" is nonnumeric data.
-21 D105 K-21 Since " -21 " is a numeric value, it is converted to a binary value.

7-434
 SP.FREAD

(g) With the High Performance model QCPU/Process CPU/Redundant CPU/Universal

model QCPU/LCPU whose first 5 digits of the serial number are "01112" or later, it is
possible to divide read operation into multiple times.
1
[Specify the row desired to start read.]
Execution type
Column designation
= CSV format Starting row number
= 4H Read head device
= 2H
= D0
2
Data type specification = Word Number of data = 6H
Device data

3
(Data to be read out)
Column Column Column Column K6 D0 Number of read points
1 2 3 4
K5 D1
Row 1 1 , 2 , 3 , 4 CR LF K6 D2
K7 D3 4
K8 D4
Starting row Row 2 5 , 6 , 7 , 8 CR LF
K9 D5
K10 D6
D7
6
Row 3 9 , 10 , 11 , 12 CR LF D8

Next starting D9
position D10 6
D11
D12
Row 4 13 , 14 , 15 , 16 CR LF
7
D13

Row 5 17 , 18 , 19 , CR LF

8
[In the continuation mode, read continues from the end of the previous read position.]
Execution type = CSV format Starting row number = FFFFFFFH (Continuation mode)
Column designation = 4H Read head device = D7
Data type specification = Word Number of data = 5H
Device data

7.18.13 Reading Data from Designated File (SP.FREAD)

7.18 Other instructions
(Data to be read out)
K6 D0

Column Column Column Column K5 D1

1 2 3 4 K6 D2
Row 1 1 , 2 , 3 , 4 CR LF K7 D3
K8 D4
K9 D5
Row 2 5 , 6 , 7 , 8 CR LF K10 D6
K5 D7 Number of read points
Present starting

K11 D8
position

K12 D9
K13 D10
Row 3 9 , 10 , 11 , 12 CR LF K14 D11
K15 D12
D13
Row 4 13 , 14 , 15 , 16 CR LF
Next starting
position

Row 5 17 , 18 , 19 , 20 CR LF

• When read is performed in the continuation mode, the previous addition cannot be made
normally if the "execution type", "column designation" and "Data type specification"
settings differ from those at the previous time.
• The previous addition cannot be made normally if the SP.FREAD instruction or
SP.FWRITE instruction with another setting is executed while data is being read
continuously in the continuation mode.

7-435
 SP.FREAD

(h) When data is read after CSV format conversion, the numerical values that are out of
range or the elements other than numerical values in the object CSV format file are
converted into 0H.

(i) When data is read after CSV format conversion, numerical values are read and
converted as follows:
Numerical Values in
-32768 to -1 0 to 32767 32768 to 65535
CSV Format

Without
32768 to 65535 0 to 32767 32768 to 65535
Word a sign
device With a
-32768 to -1 0 to 32767 -32768 to -1
sign

(j) Do not execute this instruction in an interrupt program.

(Otherwise, a malfunction may result.)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• Drive specified by drive designation device ( S0 ) contains the medium other than the ATA
card. (For QCPU) (Error code: 4100)
• Drive specified by drive designation device ( S0 ) contains the medium other than the SD
Memory card. (For LCPU) (Error code: 4100)
• Values designated in control data ( D0 ) and the subsequent devices are out of the setting
range. (Excluding D0 +2) (Error code: 4100)
• Value designated by number of data blocks to be read ( D0 +2) is out of the setting range.
(Error code: 4101)
• Invalid device is designated. (Error code: 4004)
• File name designated by file name character string ( S1 ) or the subsequent devices does
not exist in the designated drive. (Error code: 2410)
• Size of read data exceeds the size of reading device. (Error code: 4101)
• When binary data is read, the number of data in the file is less than the size designated by
the number of request read data ( D0 +2).
(High Performance model QCPU of which the first 5 digits of the serial number are '01111'
or lower) (Error code: 4100)
• Access error occurred in the ATA card. (For QCPU) (Error code: 4100)
• Access error occurred in the SD Memory card. (For LCPU) (Error code: 4100)
• The device specified by D0 or D2 exceeds the range of the corresponding device.
(For the Universal model QCPU, LCPU.) (Error code: 4101)

7-436
 SP.FREAD

Program Example
1
(1) The following program reads 4 bytes of binary data from the beginning of file "ABCD.BIN" in
the memory card inserted to drive 2 when X10 is turned ON.
• Assume that 8 points from (D0) are reserved for the control data devices. 2
• Assume that 100 bytes from D20 are reserved for the reading devices.
[Ladder Mode] 3
Sets the execution/completion type

Sets the number of request read data 4

Sets the file position

Sets the file name 6

Normal completion display 6

Error completion display

7

[List Mode]

Step Instruction Device

7.18.13 Reading Data from Designated File (SP.FREAD)

7.18 Other instructions

7-437
 SP.FREAD

(2) The following program reads file "ABCD.CSV" in the PC card inserted to slot 0 as
two-column table data in CSV format when X10 is turned ON.
• Assume that 8 points from (D0) are reserved for the control data devices.
• Assume that 100 bytes from D20 are reserved for the reading devices.
• Assume that the target CSV format file contains numerical values only.
[Ladder Mode]

Sets the execution/completion type

Sets the number of request read data

Sets the designation of number of columns

Sets the file name

Normal completion display

Error completion display

[List Mode]
Step Instruction Device

7-438
 SP.DEVST

7.18.14 Writing Data to Standard ROM (SP.DEVST)

SP.DEVST
1
High
2
Basic performance Process Redundant Universal LCPU

3
Command
SP.DEVST SP.DEVST n1 S n2 D
4
n1: Write offset of the device data storage file (specified in units of 16-bit words) (BIN 32-bit)
S : Head device number written to the standard ROM (device name)

n2: The number of write points (BIN 16-bit)

6
D : D +0 : FCompletion device (bit)
D +1 : FError completion device (bit)
6
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K,H

n1 –– –– ––
7
S –– –– –– ––

n2 –– –– ––

D *1 –– *1 –– –– –– 8
*1:Devices assigned as local devices can not be used.

Function

7.18.14 Writing Data to Standard ROM (SP.DEVST)

7.18 Other instructions
(1) Writes device data for the number of points specified at n2 of the device S to the write
offset, which is specified for n1, of the device data storage file in the standard ROM.
n1 is the offset from the head of device data storage file and specified by word offset (in units
of 16-bit words).
Standard ROM

Head device Write offset n1 Device data

number S storage file
Write offset of device
data stofage file

Write
offset 16-bit
+0
Number of
+1
n2 points
+2

(2) Since the device data write position completion device ( D +0) in the standard ROM
automatically turns ON at execution of the END instruction, which detects the completion of
this instruction, and turns OFF with the END instruction of next scan, it is used as an
execution completion flag of this instruction.
(3) When this instruction is completed in error, the error completion device ( D +1) turns ON/
OFF at the same timing with the completion device ( D +0). This device is used as an error
completion flag of this instruction.

7-439
 SP.DEVST

(4) SM721 turns ON during execution of this instruction.

When SM721 has already turned ON, this instruction can not be executed. (If executed, no
processing is performed.)

(5) When an error is detected at execution of this instruction, the completion device ( D +0),
error completion device ( D +1) and SM721 do not turn ON.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The write offset specified at n1 is out of the device data storage file range.
(Error code: 4100)
• The number of n2 points from the write offset specified at n1 is out of the device data
storage file range. (Error code: 4100)
• The range for the number of n2 points from the device S exceeds the corresponding
device. (Error code: 4141)
• The device data storage file is not set at "PLC file" of PLC parameter on GX Developer.
(Error code: 2410)
• The device specified by D exceeds the range of the corresponding device.
(Error code: 4101)

Program Example
(1) The program which writes the ten points of data from D100 to the device data storage file in
the standard ROM when M0 turns ON.
[Ladder Mode] [List Mode]

Step Instruction Device

Caution
(1) The value written to the standard ROM is the value at execution of this instruction.
(2) The standard ROM write count index (SD687 and SD688) is increased by the execution of
the SP.DEVST instruction. If the standard ROM write count index exceeds hundred
thousand times, FLASH ROM ERROR (error code: 1610) occurs.
(3) To prevent the number of ROM writes from increasing due to executing instruction
carelessly, set the specification of writing to standard ROM instruction count (SD695) to
restrict the number of writes a day.
Exceeding the number of writes (the default values are 36 times.) set causes OPERATION
ERROR (error code: 4113).

7-440
 (S(P).DEVLD)

7.18.15 Read Data from Standard ROM (S(P).DEVLD)

(S(P).DEVLD)
1
High
2
Basic performance Process Redundant Universal LCPU

3
Command
S.DEVLD S.DEVLD n1 D n2

Command 4
SP.DEVLD SP.DEVLD n1 D n2

n1 : Read offset of the device data storage file (specified in units of 16-bit words) (BIN 32-bit)
6
D : Head device number read from the standard ROM (device name)
n2 : The number of reading points (BIN 16-bit)

Setting Internal Devices

R, ZR
J \
U \G Zn
Constants
Other
6
Data Bit Word Bit Word E

n1 –– –– ––

D –– –– –– –– 7
n2 –– –– ––

8
Function
(1) Reads device data for the number of points specified at n2 from the read offset, which is
specified for n1, of the device data storage file in the standard ROM, and stores the data to

7.18.15 Read Data from Standard ROM (S(P).DEVLD)

7.18 Other instructions
the device specified for D .
n1 is the offset from the head of device data storage file and specified by word offset (in units
of 16-bit words).
Standard ROM

Head device Read offset n1 Device data storage file

number D Read offset of device data
storge file

Read
offset 16-bit
+0
Number of
n2 points +1
+2

7-441
 (S(P).DEVLD)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The address specified at n1 is out of the standard ROM range. (Error code: 4100)
• The number of n2 points from the address specified at n1 is out of the standard ROM
range. (Error code: 4100)
• The range for the number of n2 points from the device D exceeds the corresponding
device. (Error code: 4101)
• The device data storage file is not set at "PLC file" of PLC parameter on GX Developer.
(Error code: 2410)

Program Example
(1) The program which reads the ten points of data from D100 to the device data storage file in
the standard ROM when M0 turns ON.
[Ladder Mode] [List Mode]

Step Instruction Device

7-442
 PLOADP

7.18.16 Load Program from Memory Card (PLOADP)

PLOADP
1
High
2
Basic performance Process Redundant Universal LCPU

3
Command
PLOADP PLOADP S D

4
S : Drive No. storing the program to be loaded, character string data of the file name, or head number of the
devices storing the character string data (BIN 16 bits) *1
6
D : Device that turns ON for 1 scan by the instruction completion (bits)

Setting Internal Devices J \ Constants

R, ZR Zn Other
Data Bit Word Bit Word
U \G
$
6
S –– –– ––

D *2 –– –– –– ––

*1: Designated as "<Drive No.>:<File Name>". Example) 1:MAIN 7

*2: Local devices cannot be used.

8
Function
(1) The program stored in the memory card or standard ROM is transferred to the program
memory (drive 0).

7.18.16 Load Program from Memory Card (PLOADP)

7.18 Other instructions
If the transferred program is not registered to the program setting of the PLC parameter
dialog box, its program setting in the CPU module is set to the standby type.
At this time, the program setting of the PLC parameter dialog box does not change.
(To transfer a program with the PLOADP instruction, a continuous free space is required in
the program memory.)
(2) The program added using the PLOADP instruction is assigned the lowest number among
the unused program Nos.
(To assign a program number manually, store the program number to be assigned in
SD720.)
The following example assumes that "MAIN6" is added by the PLOADP instruction.

(a) When the program Nos. have been set consecutively, the new program is added at the
end of the preset program Nos.
When programs No. 1 to 5 have been set, the new program is added as program No. 6.
Program No. Program name Program No. Program name
1 MAIN1 1 MAIN1
2 MAIN2 Adds "MAIN6" by the 2 MAIN2
3 MAIN3 PLOADP instruction. 3 MAIN3
4 MAIN4 4 MAIN4
5 MAIN5 5 MAIN5
6 MAIN6 Added at the end.

7-443
 PLOADP

(b) When there are multiple open program Nos., the program designated by the PLOADP
instruction is added to the lowest number among them to be added.
(The open program Nos. are made when programs are deleted by the PUNLOADP
instruction.)
When programs No. 2 and 4 are open, the new program is added as program No. 2.
Program No. Program name Program No. Program name
1 MAIN1 1 MAIN1
2 Empty Adds "MAIN6" by the 2 MAIN6 Added to the smallest program
3 MAIN3 PLOADP instruction. 3 MAIN3 number which is empty.
4 Empty 4 Empty
5 MAIN5 5 MAIN5

(3) Drive Nos. 1, 2, and 4 can be specified. (Drive 3 cannot be specified.)

• Drive 1: Memory card (RAM)
• Drive 2: Memory card (ROM)
• Drive 4: Standard ROM
(4) An extension (.QPG) need not be specified for the file name.
(5) The bit device specified by D is turned ON during the END processing of the scan where
this instruction is completed. The bit device is turned OFF at the next END processing.
(6) The PLOADP, PUNLOADP and PSWAPP instructions cannot be executed simultaneously.
If two or more of the above instructions are executed simultaneously, the instruction
executed later will not be executed.
When using the above instructions, provide interlocks manually to avoid simultaneous
execution.
(7) Do not execute this instruction in an interrupt program.
(Otherwise, a malfunction may result.)
(8) To execute the program that was transferred to the program memory with the PLOADP
instruction, execute the scan execution type with the PSCAN instruction (See Section
7.17.3).
(9) The PLC file settings of the loaded program are set as follows:
(a) File usage for each program
All the usage of file register, device initial value, comment, and local device of the
program transferred by this instruction are set as "Use PLC file setting".
However, an error will be returned if both of the conditions below are met when the
program is transferred using this instruction.
• Setting is made so that local devices are used in the PLC file setting.
• The number of programs in the program memory exceeds the number of programs
set at the parameters.
To use local devices in the program transferred by this instruction, register a dummy
program file in the parameter, delete the dummy file with the PUNLOADP instruction,
and then load the program with the PLOADP instruction.

(b) I/O refresh setting

Nothing is set for both input and output for the I/O refresh setting of the program
transferred by this instruction.

7-444
 PLOADP

(10) The "PLOADP instruction" and "Write during RUN" processing cannot be executed
simultaneously.
1
(a) When a write during RUN request is given during processing of the PLOADP
instruction, write during RUN is delayed.
Write during RUN is started after the processing of the PLOADP instruction is
2
completed.

(b) When the PLOADP instruction is executed during write during RUN, the processing of
the PLOADP instruction is delayed. 3
The processing of the PLOADP instruction is started after completion of write during
RUN.
4
Operation Error
6
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• File name does not exist at the drive number designated by S . (Error code: 2410) 6
• The drive No. designated by S is invalid. (Error code: 4100)
• There is not enough memory to load the specified program in drive 0.
(Error code: 2413) 7
• The number of files registered in the program memory is as much number as the one
indicated in the table below. (Error code: 4101)
• The program No. stored in SD720 is already used, or larger than the largest program
8
number shown in the table below. (Error code: 4101)
• The program file which has the same name as the program file to be loaded already
exists. (Error code: 2410)

7.18.16 Load Program from Memory Card (PLOADP)

7.18 Other instructions
• The file size of the local devices cannot be reserved. (Error code: 2401)
CPU Model Name Program Memory (No. of Files) Largest Program No.
Q02 (H) CPU 28 28
Q06HCPU 60 60
Q12HCPU 124 124
Q25HCPU 124 124
Q12PHCPU 124 124
Q25PHCPU 124 124

Program Example
(1) The following program transfers "ABCD.QPG" stored in drive 4 to drive 0 and places the
program in standby status when M0 is turned ON.
[Ladder Mode] [List Mode]

Step Instruction Device

7-445
 PUNLOADP

7.18.17 Unload Program from Program Memory (PUNLOADP)

PUNLOADP

High
Basic performance Process Redundant Universal LCPU

Command
PUNLOADP PUNLOADP S D

S : Character string data of the program file name to be unloaded, or head number of the devices storing the
character string data (BIN 16 bits)
D : Device turned ON for 1 scan on completion of the instruction (bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word $

S –– –– ––

D *1 –– –– –– ––

*1: Local devices cannot be used.

Function
(1) The standby program stored in the program memory (drive 0) is deleted from the program
memory.
(The program set as the "scan execution type" with the PSCAN instruction or the program
set as the "low speed execution type" with the PLOW instruction cannot be deleted.)
(2) The program No. deleted by the PUNLOADP instruction is made "Empty".
When programs No. 1 to 5 have been set in the program setting of the PLC parameter dialog
box, deleting program No. 2 with this instruction makes program No. 2 open.
Program No. Program name Program No. Program name
1 MAIN1 1 MAIN1
2 MAIN2 Deletes "MAIN2" by the 2 Empty Program No. 2
3 MAIN3 PUNLOADP instruction. 3 MAIN3 is deleted.
4 MAIN4 4 MAIN4
5 MAIN5 5 MAIN5

(3) An extension (.QPG) need not be specified for the file name.
(4) The bit device specified by D is turned ON during the END processing of the scan where
this instruction is completed. The bit device is turned OFF at the next END processing.
(5) The PLOADP, PUNLOADP and PSWAPP instructions cannot be executed simultaneously.
If two or more of the above instructions are executed simultaneously, the instruction
executed later will not be executed.
When using the above instructions, provide interlocks manually to avoid simultaneous
execution.

7-446
 PUNLOADP

(6) When the Programmable Controller is powered OFF, then ON or the CPU module is reset
after execution of the PUNLOADP instruction, the following operation is performed.
1
(a) When boot setting has been made in the PLC parameter dialog box, the program where
the boot setting has been made is transferred to the program memory.
When the program deleted by the PUNLOADP instruction is not to be executed, delete
2
the corresponding program name from the boot setting and program setting of the PLC
parameter dialog box.

(b) When boot setting has not been made in the PLC parameter dialog box, "FILE SET 3
ERROR (error code: 2400)" occurs.
1) When the program deleted by the PUNLOADP instruction is not to be executed,
delete the corresponding program name from the program setting of the PLC 4
parameter dialog box.
2) When the program deleted by the PUNLOADP instruction is to be executed again,
write the corresponding program to the CPU module. 6
(7) Do not execute this instruction in an interrupt program.
(Otherwise, a malfunction may result.)
6
(8) The program to be deleted from the program memory by this instruction should be set to the
"standby execution type" with the PSTOP instruction beforehand. (See Section 7.17.1)
(9) The "PUNLOADP instruction" and "write during RUN" processing cannot be executed 7
simultaneously.
(a) When a write during RUN request is given during processing of the PUNLOADP
instruction, write during RUN is delayed. 8
Write during RUN is started after the processing of the PUNLOADP instruction is
completed.

(b) When the PUNLOADP instruction is executed during write during RUN, the processing

7.18.17 Unload Program from Program Memory (PUNLOADP)

7.18 Other instructions
of the PUNLOADP instruction is delayed.
The processing of the PUNLOADP instruction is started after completion of write during
RUN.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The file name designated by S does not exist. (Error code: 2410)
• The program designated by S is not in standby status or is being executed.
(Error code: 4101)

Program Example
(1) The following program deletes "ABCD.QPG" stored in drive 0 from the memory when M0
turns from OFF to ON.
[Ladder Mode] [List Mode]

Step Instruction Device

7-447
 PSWAPP

7.18.18 Load + Unload (PSWAPP)

PSWAPP

High
Basic performance Process Redundant Universal LCPU

Command
PSWAPP PSWAPP S1 S2 D

S1 : Character string data of the file name of the program to be unloaded, or head number of the devices storing
the character string data (BIN 16 bits)
S2 : Drive No. storing the program to be loaded, character string data of the file name, or head number of the
devices storing the character string data (BIN 16 bits) *1
D : Device turned ON for 1 scan on completion of the instruction (bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word $

S1 –– –– ––

S2 –– –– ––

D *2 –– –– –– ––

*1: Designated as "<Drive No.>:<File Name>". Example) 1:MAIN

*2: Local devices cannot be used.

Function
(1) The standby type program stored in the program memory (drive 0) designated by S1 is
deleted from the program memory, and at the same time, the program stored in the memory
card or standard ROM designated by S2 is transferred to the program memory and placed in
standby status.
(When the program is transferred to the program memory, the program must have a
continuous free space.)
The program set as the "scan execution type" with the PSCAN instruction or the program set
as the "low speed execution type" with the PLOW instruction cannot be deleted.
(2) The program to be transferred to the program memory by the PSWAPP instruction will have
the program No. of the program to be deleted from the program memory.
(If there is an open program No. before the program to be deleted from the program
memory, the program to be transferred to the program memory will not have the open
program No.)
When program No. 2 is "Empty", the program transferred to the program memory is
registered as program No. 3 by the program swapping of program No. 3 with this instruction.
Program No. Program name Program No. Program name
1 MAIN1 1 MAIN1
2 Empty Swaps "MAIN3" with "MAIN6" 2 Empty
3 MAIN3 by the PSWAPP instruction. 3 MAIN6 MAIN6 enters
4 MAIN4 4 MAIN4
5 MAIN5 5 MAIN5

7-448
 PSWAPP

(3) Drive Nos. 1, 2, and 4 can be specified. (Drive 3 cannot be specified.)

• Drive 1: Memory card (RAM)
1
• Drive 2: Memory card (ROM)
• Drive 4: Standard ROM
(4) An extension (.QPG) need not be specified for the file name.
2
(5) The bit device specified by D is turned ON during the END processing of the scan where
this instruction is completed. The bit device is turned OFF at the next END processing.
3
(6) The PLOADP, PUNLOADP and PSWAPP instructions cannot be executed simultaneously.
If two or more of the above instructions are executed simultaneously, the instruction
executed later will not be executed. 4
When using the above instructions, provide interlocks manually to avoid simultaneous
execution.
(7) When the Programmable Controller is powered OFF, then ON or the CPU module is reset 6
after execution of the PSWAPP instruction, the following operation is performed.
(a) When boot setting has been made in the PLC parameter dialog box, the program where
the boot setting has been made is transferred to the program memory. 6
When the program replaced by the PSWAPP instruction is to be executed, change the
boot setting and program setting of the PLC parameter dialog box for the corresponding
program name. 7
(b) When boot setting has not been made in the PLC parameter dialog box, "FILE SET
ERROR (error code: 2400)" occurs.
1) When the program replaced by the PSWAPP instruction is to be executed, change
8
the program setting of the PLC parameter dialog box for the corresponding program
name.
2) To execute the program set in the program setting of the PLC parameter dialog box,

7.18.18 Load + Unload (PSWAPP)

7.18 Other instructions
write the corresponding program to the CPU module again.

(8) Do not execute this instruction in an interrupt program.

(Execution of this instruction in an interrupt program can cause a malfunction.)
(9) The PLC file settings of the program on which the PSWAPP instruction has been conducted
are set as follows:
(a) File usage for each program
All the usage of file register, device initial value, comment, and local device of the
program after the execution of the PSWAPP instruction are set as "Use PLC file
setting".

(b) I/O refresh setting

Nothing is set for both input and output for the I/O refresh setting of the program after
the PSWAPP instruction has been executed.

(10) The "PSWAPP instruction" and "write during RUN" processing cannot be executed
simultaneously.
(a) When a write during RUN request is given during processing of the PSWAPP
instruction, write during RUN is delayed.
Write during RUN is started after the processing of the PSWAPP instruction is
completed.
(b) When the PSWAPP instruction is executed during write during RUN, the processing of
the PSWAPP instruction is delayed.
The processing of the PSWAPP instruction is started after completion of write during
RUN.

7-449
 PSWAPP

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The drive No. or the file name designated by S1 or S2 does not exist.
(Error code: 2410)
• The drive No. designated by S1 is invalid. (Error code: 4100)
• There is not enough memory to load the specified program in drive 0.
(Error code: 2413)
• The program designated by S1 is not in standby status or is being executed.
(Error code: 4101)

Program Example
(1) The following program deletes "EFGH.QPG" stored in drive 0 from the memory, transfers
"ABCD.QPG" stored in drive 4 to drive 0, and places the program in standby status when M0
is turned from OFF to ON.
[Ladder Mode] [List Mode]

Step Instruction Device

7-450
 RBMOV(P)

7.18.19 High-speed Block Transfer of File Register (RBMOV(P))

RBMOV(P)
1
Ver.
High
2
Basic performance Process Redundant Universal LCPU

Universal model QCPU: Other than Q00UJCPU

Command 3
RBMOV RBMOV S D n

4
Command
RBMOVP RBMOVP S D n

D
: Head number of the devices where the data to be transferred is stored (BIN 16 bits)
: Head number of the devices of transfer destination (BIN 16 bits)
6
n : Number of data to be transferred (BIN 16 bits)

Setting Internal Devices J \ Constants

Data Bit Word
R, ZR
Bit Word
U \G Zn
K, H
Other
6
S –– ––

D –– ––

n ––
7

Function 8
(1) Transfers in batch 16-bit data of n points from the device designated by S to location n
points from the device designated by D .

7.18.19 High-speed Block Transfer of File Register (RBMOV(P))

7.18 Other instructions
b15 b0 b15 b0
S 1234H D 1234H
S +1 5678H Block D +1 5678H
S +2 7FF0H transfer D +2 7FF0H
n n

S +(n-2) 6FFFH D +(n-2) 6FFFH

S +(n-1) 553FH D +(n-1) 553FH

(2) The transfer is available even if there is an overlap between the source and destination
devices.
For the transmission to the smaller number of device, the data is transferred from S . For the
transmission to the larger number of device, the data is transferred from S +(n-1).
However, as shown in the example below, when transferring data from R to ZR, or from ZR
to R, the range to be transferred (source) and the range of destination must not overlap.
• ZR transfer range ((specified head No. of ZR) to (specified head No. of ZR + the number
of transfers -1))
R transfer range ((specified head No. of R + file register block No. 32768) to (specified
head No. of R + file register block No. 32768 + the number of transfers -1))

7-451
 RBMOV(P)

Example

Transfer ranges of ZR and R overlap when transferring 10000 points of data from ZR30000
(source) to R10 (block No.1 of the destination).
• ZR transfer range (30000) to (30000+10000-1) (30000) to (39999)
• R transfer range (10+(1 32768)) to (10+(1 32768)+10000-1)
(32778) to (42777)
Therefore, the range 32778 to 39999 overlaps.

Source of transfer Destination of transfer

ZR0 R0

Overlapped Block No. 0

ZR30000 R32767
ZR39999 R10

R10009 Block No. 1

(3) When S is a word device and D is a bit device, the number of bits designated by the bit
device digit specification will be transferred. If K1Y30 has been designated by D , the lower
four bits of the word device designated by S will be transferred.
b15 b4b3b2b1b0 D +2 D +1 D
S R100 1011
Y3B Y38Y37 Y34Y33 Y30
S +1 R101 0011 n 011100111011
n
S +2 R102 0111

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The device range of n points from S or D exceeds the corresponding device range.
(Error code: 4101)
• The file register is not specified for either S or D . (Error code: 4101)

7-452
 RBMOV(P)

Program Example
1
(1) The following program outputs the lower four bits of data in R66 to R69 to Y30 through Y3F
in units of 4 points.
[Ladder Mode] [List Mode] 2
Step Instruction Device
3

Before execution
(source of transfer) After execution
4
b15 b4b3 b0 (destination of transfer)
R66 1110 1 1 1 0 1 Y33 to Y30
R67
R68
00000
10011
0
0
0
0
0
1
0
1
Y37 to Y34
Y3B to Y38
6
R69 0 110 1 1 1 0 1 Y3F to Y3C

Ignored 6
(2) The following program outputs the data in X20 to X2F to R100 to R103 in units of 4 points.
[Ladder Mode] [List Mode]
7
Step Instruction Device

X2F X2C X2B X28X27 X24X23 X20

Before
10 0 0 0 1 1 10 1 10 0 10 0
execution
After execution

7.18.19 High-speed Block Transfer of File Register (RBMOV(P))

7.18 Other instructions
(destination of transfer)
b15 b4 b3 b0
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 R100

0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 R101
4 points
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 R102

0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 R103

Filled with 0s

7-453
 RBMOV(P)

The RBMOV (P) instruction is useful to batch transfer a large quantity of file
register data with the QnHCPU/QnPHCPU/QnPRHCPU.
For the QnUCPU, the processing speed of the RBMOV instruction is equivalent to
that of the BMOV instruction.
The comparison of processing speed between the RBMOV and BMOV
instructions is as follows:

(1)Transfer from file registers to internal devices/internal devices to file registers

Target memory where 1 word 1000 words 10000 words
CPU Instruction
file register is stored Min. Max. Min. Max. Min. Max.

Standard RAM 20.0 µs 91.0 µs 775.0 µs

RBMOV SRAM card 22.0 µs 305.0 µs 2900.0 µs
QnHCPU
Flash card *1 22.5 µs 405.0 µs 3950.0 µs
QnPHCPU
Standard RAM 7.5 µs 76.2 µs 720.0 µs
QnPRHCPU
BMOV SRAM card 384.0 µs 3900.0 µs
8.0 µs
Flash card *1 418.0 µs 4250.0 µs
Standard RAM 45.5 µs 215.0 µs 1850.0 µs
RBMOV SRAM card
49.5 µs 540.0 µs 5150.0µs
Flash card *1
QnCPU
Standard RAM 17.5 µs 177.0 µs 1700.0 µs
BMOV SRAM card 500.0 µs 5050.0 µs
18.0 µs
Flash card *1 572.0 µs 5800.0 µs

Standard RAM 12.2 µs 34.9 µs 121.5 µs 145.1 µs 1111.5 µs 1135.1 µs

RBMOV SRAM card*2 - - - - - -

Q00UCPU Flash card *2 - - - - - -

Q01UCPU Standard RAM 7.3 µs 13.8 µs 116.5 µs 124.2 µs 1106.5 µs 1114.2 µs
BMOV SRAM card*2 - - - - - -
Flash card *2 - - - - - -
Standard RAM 9.4 µs 31.3 µs 118.5 µs 141.3 µs 1108.5 µs 1131.3 µs
RBMOV SRAM card 9.4 µs 31.4 µs 178.5 µs 201.3 µs 1708.5 µs 1731.3 µs
Flash card *1 9.4 µs 32.1 µs 278.5 µs 301.3 µs 2708.5 µs 2731.3 µs
Q02UCPU
Standard RAM 5.0 µs 11.6 µs 114.5 µs 122.3 µs 1104.5 µs 1112.3 µs
BMOV SRAM card 5.1 µs 11.7 µs 174.5 µs 182.3 µs 1704.5 µs 1712.3 µs
Flash card *1 5.0 µs 11.6 µs 274.5 µs 282.3 µs 2704.5 µs 2712.3 µs
Standard RAM 11.3 µs 16.8 µs 120.7 µs 127.1 µs 1110.7 µs 1117.1 µs
RBMOV SRAM card 11.2 µs 16.7 µs 180.7 µs 187.1 µs 1710.7 µs 1717.1 µs
Flash card *1 11.3 µs 16.8 µs 280.7 µs 287.1 µs 2710.7 µs 2717.1 µs
Q03UD(E)CPU
Standard RAM 4.8 µs 6.6 µs 114.7 µs 117.1 µs 1104.7 µs 1107.1 µs
BMOV SRAM card 4.8 µs 6.6 µs 147.7 µs 177.1 µs 1704.7 µs 1707.1 µs
Flash card *1 4.8 µs 6.5 µs 274.7 µs 277.1 µs 2704.7 µs 2707.1 µs
Standard RAM 9.2 µs 15.1 µs 61.0 µs 68.6 µs 531.0 µs 538.6 µs
Q04UD(E)HCPU
RBMOV SRAM card 9.4 µs 15.6 µs 165.0 µs 172.6 µs 1576.0 µs 1583.6 µs
Q06UDE(H)CPU
Q10UDE(H)CPU Flash card *1 9.4 µs 15.7 µs 260.0 µs 267.6 µs 2526.0 µs 2533.6 µs
Q13UDE(H)CPU Standard RAM 4.1 µs 5.6 µs 56.0 µs 58.6 µs 526.0 µs 528.6 µs
Q20UDE(H)CPU
BMOV SRAM card 4.5 µs 6.1 µs 160.0 µs 162.6 µs 1571.0 µs 1573.6 µs
Q26UDE(H)CPU
Flash card *1 4.3 µs 6.2 µs 255.0 µs 257.6 µs 2521.0 µs 2523.6 µs

*1 : When file registers are stored in the Flash card, no processing is performed for transfer from
internal devices to file registers.
*2 : Unusable for the Q00UCPU and Q01UCPU.

7-454
 RBMOV(P)

(2)Transfer from file registers to file registers

CPU Instruction
Target memory where 1 word 1000 words 10000 words 1
file register is stored Min. Max. Min. Max. Min. Max.
Standard RAM 20.0 µs 91.0 µs 775.0 µs
RBMOV
QnHCPU
QnPHCPU
SRAM card 22.5 µs 545.0 µs 5300.0 µs 2
Standard RAM 7.5 µs 77.0 µs 720.0 µs
QnPRHCPU BMOV
SRAM card 8.5 µs 692.0 µs 7050.0 µs

RBMOV
Standard RAM 45.5 µs 215.0 µs 1850.0 µs 3
SRAM card 50.0 µs 870.0 µs 8350.0 µs
QnCPU
Standard RAM 17.5 µs 179.0 µs 1700.0 µs
BMOV
SRAM card 18.5 µs 839.0 µs 8600.0 µs 4
Standard RAM 12.6 µs 35.3 µs 232.5 µs 256.1 µs 2211.5 µs 2235.1 µs
RBMOV
Q00UCPU SRAM card*2 - - - - - -
Q01UCPU
BMOV
Standard RAM 7.7 µs 14.2 µs 227.5 µs 234.2 µs 2206.5 µs 2214.2 µs
6
SRAM card*2 - - - - - -
Standard RAM 9.6 µs 31.5 µs 228.5 µs 252.3 µs 2208.5 µs 2231.3 µs
RBMOV

Q02UCPU
SRAM card 9.6 µs 31.5 µs 378.5 µs 401.3 µs 3708.5 µs 3731.3 µs
6
Standard RAM 5.2 µs 11.8 µs 224.5 µs 232.3 µs 2204.5 µs 2212.3 µs
BMOV
SRAM card 5.2 µs 11.8 µs 374.5 µs 382.3 µs 3704.5 µs 3712.3 µs

RBMOV
Standard RAM 11.2 µs 16.7 µs 230.7 µs 237.1 µs 2210.7 µs 2217.1 µs
7
SRAM card 11.6 µs 16.7 µs 380.7 µs 387.1 µs 3710.7 µs 3717.1 µs
Q03UD(E)CPU
Standard RAM 4.9 µs 6.7 µs 224.7 µs 227.1 µs 2204.7 µs 2207.1 µs
BMOV

Q04UD(E)HCPU
SRAM card

Standard RAM
5.2 µs

9.3 µs
6.7 µs

15.5 µs
374.7 µs

118.0 µs
377.1 µs

124.6 µs
3704.7 µs

1102.0 µs
3707.1 µs

1107.6 µs
8
RBMOV
Q06UDE(H)CPU
SRAM card 9.7 µs 15.5 µs 365.0 µs 371.6 µs 3571.0 µs 3578.6 µs
Q10UDE(H)CPU
Standard RAM 4.3 µs 6.2 µs 113.0 µs 115.6 µs 1096.0 µs 1098.6 µs
Q13UDE(H)CPU
Q20UDE(H)CPU BMOV
SRAM card 4.5 µs 6.1 µs 360.0 µs 362.6 µs 3566.0 µs 3568.6 µs

7.18.19 High-speed Block Transfer of File Register (RBMOV(P))

7.18 Other instructions
Q26UDE(H)CPU

*1 : Unusable for the Q00UCPU and Q01UCPU.

7-455
 7.18.20 User Message (UMSG)

High
Basic performance Process Redundant Universal LCPU

Command
UMSG UMSG S

S : String to display on display unit, or lead number (string) of device storing string to display

Internal Device Indirect J \ Constants

Setting
R, ZR Specifica- U \G Zn Real Others
Data Bit Word Bit Word K, H
tion String

S –– –– *1 ––
*1: Only strings can be used

Function
(1) The string data specified by S is displayed as a user message in the display unit.
The string specified directly by S (surrounded by double quotation marks (")) or the string
from the device number specified by S until the device number storing "00H" is displayed.
b15 to b8 b7 to b0
S 2nd char 1st char
S +1 4th char 3rd char User message
S +2 6th char 5th char Process A complete.
S +3 8th char 7th char
S +4 10th char 9th char
Run UMSG
instruction Message appears
00H on display unit.

Indicates end of string.

(2) Strings of up to 128 single-byte characters can be displayed in the display unit.

7-456
 (3) The user message is displayed when the UMSG instruction command is rising.
If the string is changed while the command is on, then the modified user message will
appear in the display unit.
1
(4) The string specified by the UMSG instruction is displayed upon END processing. If two or
more UMSG instructions are executed, then the last UMSG instruction executed before the
END is valid. If two or more programs are running, then the last UMSG instruction to be
2
executed is valid.
(5) This instruction is not processed if it is run when no display unit is mounted.
3
(6) If the "ESC" key on the display unit is pressed while a user message is being displayed, the
displayed message will disappear.
To display the message again, execute "User Message" from the menu screen on the 4
display unit.
(7) If a NULL code (00H) is specified as the argument to this instruction, then any message
currently being displayed will disappear. 6
The procedure for specifying a NULL code (00H) in the instruction parameter is as follows.

6
Specifying a NULL code(00H)

See the MELSEC-L CPU Module User's Manual (Function Explanation, Program Fundamentals)
for details about the display unit. 7

Operation Error 8
(1) The following will cause a computation error, setting the error flag (SM0), and storing an
error code in SD0.
• When there is no NULL code (00H) within the range of the target device following the

7.18.20 User Message (UMSG)

7.18 Other instructions
device number specified by S (Error code: 4101)

• When more than 128 single-byte characters are specified in the S string
(Error code: 4100)

7-457
 Program Example
(1) This program displays the string stored after D10 on the display unit, when X10 is set to
"on".
[Circuit Mode] [List Mode]

Step Instruction Device

[Action]

b15 to b8 b7 to b0
D10 4CH (i) 69H (L)
D11 6EH (e) 65H (n)
D12 2DH (A) 41H (-)
User message
D13 20H (w) 77H ( ) Line-A Working
D14 6FH (r) 72H (o)
D15 6BH (i) 69H (k)
D16 6EH (g) 67H (n) Run UMSG
instruction
D17 00H

(2) This program displays "Line-A Working" on the display unit when M0 is set to "on".
[Circuit Mode] [List Mode]

Step Instruction Device

"Line-A Working"
"Line-A Working"

[Action]

b15 to b8 b7 to b0
60H 82H
89H 83H
"Line-A Working"

43H 83H User message

93H 83H Line-A Working
40H 81H
5EH 89H
5DH 93H Run UMSG
instruction
86H 92H
0000 H

7-458
(3) This program displays "Line-B stop" on the display unit when X10 is set to "on", and clears
the message when X10 is set to "off".
[Ladder Mode] [List Mode]
1
"Line-B stop" Step Instruction Device
2
"Line-B stop"

3
[Action]

X10 set to "on" X10 set to "off" 4

User message
Line-B stop

7.18.20 User Message (UMSG)

7.18 Other instructions

7-459
MEMO

7-460
I INDEX

Index-1
 INDEX

0 to 9 BIN block data comparisons . . . . . . . . . . . . . . . . 6-15

Bit device output reverse . . . . . . . . . . . . . . . . . . 5-40
16-bit and 32-bit data checks . . . . . . . . . . . . . . . .7-69 Bit device shifts . . . . . . . . . . . . . . . . . . . . . . . . . 5-44
16-bit and 32-bit data exchanges . . . . . . . . . . . .6-127 Bit processing instructions . . . . . . . . . . . . . . . . . 7-59
16-bit and 32-bit data exclusive NOR operations Bit set and reset for word devices . . . . . . . . . . . . 7-59
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-27 Bit tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-61
16-bit and 32-bit data searches . . . . . . . . . . . . . .7-66 Block 16-bit data exchanges . . . . . . . . . . . . . . . 6-129
16-bit and 32-bit data transfers . . . . . . . . . . . . .6-107 Block 16-bit data transfers . . . . . . . . . . . . . . . . 6-118
16-bit and 32-bit exclusive OR operations . . . . . . .7-19 Block addition and subtraction . . . . . . . . . . . . . . . 6-59
16-bit and 32-bit negation transfers . . . . . . . . . .6-115 Block exclusive NOR operations . . . . . . . . . . . . . 7-33
1-bit shift to right or left of n-bit data . . . . . . . . . . .7-49 Block exclusive OR operations . . . . . . . . . . . . . . 7-25
1-word shift to right or left of n-word data . . . . . . .7-54 Block logical products . . . . . . . . . . . . . . . . . . . . . 7-9
4-bit dissociation of 16-bit data . . . . . . . . . . . . . .7-77 Block logical sum operations . . . . . . . . . . . . . . . . 7-17
4-bit linking of 16-bit data . . . . . . . . . . . . . . . . . .7-79 Block switching method . . . . . . . . . . . . . . . . . . . 3-46
7-segment decode . . . . . . . . . . . . . . . . . . . . . . .7-75 Buffer memory access instruction . . . . . . . . . . . 7-159

A C
A5B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6 Calculation of averages for 16-bit or 32-bit data
A6B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-103
Addition and subtraction of floating decimal point Calculation of totals for 16-bit data . . . . . . . . . . . . 7-99
data (Double precision) . . . . . . . . . . . . . . . . . . . .6-50 Calculation of totals for 32-bit data . . . . . . . . . . . 7-101
Addition and subtraction of floating decimal point CC-Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
data (Single precision) . . . . . . . . . . . . . . . . . . . .6-46 Changing check format of CHK instruction . . . . . 7-178
AnACPU and AnUCPU dedicated instructions Character string data comparisons . . . . . . . . . . . 6-11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . App-147 Character string length detection . . . . . . . . . . . . 7-203
Annunciator output . . . . . . . . . . . . . . . . . . . . . . .5-28 Character string processing instructions . . . . . . . 7-182
Arithmetic Operation Instructions . . . . . . . . . . . . .6-22 Character string search . . . . . . . . . . . . . . . . . . 7-238
Association Instructions . . . . . . . . . . . . . . . . . . .5-10 Character string transfers . . . . . . . . . . . . . . . . . 6-113
Clock comparison . . . . . . . . . . . . . . . . . . . . . . 7-360
B Clock data addition operation . . . . . . . . . . . . . . 7-347
Clock data subtraction operation . . . . . . . . . . . . 7-349
BASIC INSTRUCTIONS . . . . . . . . . . . . . . . . . . . .6-1 Clock instructions . . . . . . . . . . . . . . . . . . . . . . 7-343
Basic model QCPU . . . . . . . . . . . . . . . . . . . . . . .1-5 Common logarithm operation on floating-point data
Batch reset of bit devices . . . . . . . . . . . . . . . . . .7-64 (Double precision) . . . . . . . . . . . . . . . . . . . . . . 7-301
Batch save or recovery of index register . . . . . . .7-399 Common logarithm operation on floating-point data
BCD 4-digit addition and subtraction operations . .6-34 (Single precision) . . . . . . . . . . . . . . . . . . . . . . . 7-299
BCD 4-digit and 8-digit square roots . . . . . . . . . .7-305 Comparison Operation Instructions . . . . . . . . . . . . 6-2
BCD 4-digit multiplication and division operations Complement of 2 of BIN 16- and 32-bit data
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-42 (sign reversal) . . . . . . . . . . . . . . . . . . . . . . . . . . 6-95
BCD 8-digit addition and subtraction operations . .6-38 Conditions for Execution of Instructions . . . . . . . . 3-33
BCD 8-digit multiplication and division operations Configuration of Instructions . . . . . . . . . . . . . . . . . 3-2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-44 Contact Instructions . . . . . . . . . . . . . . . . . . . . . . . 5-2
BCD type COS operations . . . . . . . . . . . . . . . .7-310 Conversion from ASCII to hexadecimal BIN . . . . 7-229
BCD type COS-1 operation . . . . . . . . . . . . . . . .7-316 Conversion from BCD 4-digit and 8-digit data to
BCD type SIN operation . . . . . . . . . . . . . . . . . .7-308 BIN data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-76
BCD type SIN-1 operations . . . . . . . . . . . . . . . .7-314 Conversion from BCD 4-digit and 8-digit to decimal
BCD type TAN operation. . . . . . . . . . . . . . . . . .7-312 ASCII data . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-188
BCD type TAN-1 operations . . . . . . . . . . . . . . . .7-318 Conversion from BIN 16 and 32-bit data to
BIN 16 and 32 bits data sort operations . . . . . . . .7-95 floating decimal point (Double precision) . . . . . . . 6-82
BIN 16-bit addition and subtraction operations. . . .6-22 Conversion from BIN 16 and 32-bit data to
BIN 16-bit and 32-bit dead band controls . . . . . .7-323 floating decimal point (Single precision) . . . . . . . . 6-79
BIN 16-bit data comparisons . . . . . . . . . . . . . . . . .6-2 Conversion from BIN 16 and 32-bit data to Gray
BIN 16-bit multiplication and division operations . .6-30 code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-91
BIN 32-bit addition and subtraction operations. . . .6-26 Conversion from BIN 16-bit or 32-bit data to
BIN 32-bit block data comparisons . . . . . . . . . . . .6-18 hexadecimal ASCII . . . . . . . . . . . . . . . . . . . . . 7-185
BIN 32-bit data block addition and subtraction Conversion from BIN 16-bit or 32-bit to character
operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-62 string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-205
BIN 32-bit data comparisons . . . . . . . . . . . . . . . . .6-4 Conversion from BIN 16-bit or 32-bit to decimal
BIN 32-bit multiplication and division operations . .6-32 ASCII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-182

Index - 2
 Conversion from BIN 16-bit to BIN 32-bit data . . . 6-89 Date comparison . . . . . . . . . . . . . . . . . . . . . . 7-355
Conversion from BIN 32-bit to BIN 16-bit data . . . 6-90 Debugging and failure diagnosis instructions . . . 7-174
Conversion from BIN data to 4-digit and 8-digit BCD Decoding from 8 to 256 bits . . . . . . . . . . . . . . . . 7-71
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-74 Deleting and inserting data from and in data tables
Conversion from block BCD 4-digit data to block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-156
BIN 16-bit data . . . . . . . . . . . . . . . . . . . . . . . . 6-101 Deletion of character string . . . . . . . . . . . . . . . 7-242
Conversion from block BIN 16-bit data to BCD Designating Data . . . . . . . . . . . . . . . . . . . . . . . . 3-3
4-digit data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-99 Designation of modification values in index
Conversion from character string to BIN 16-bit or modification of entire ladders . . . . . . . . . . . . . . 7-147
32-bit data . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-211 Destination (D) . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Conversion from character string to floating decimal Device range check . . . . . . . . . . . . . . . . . . . . . 3-27
point data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-223 Direct 1-byte read from file register . . . . . . . . . . 7-390
Conversion from decimal ASCII to BCD 4-digit or Display instructions . . . . . . . . . . . . . . . . . . . . . 7-165
8-digit data . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-197 Dissociation or linking of random data . . . . . . . . . 7-81
Conversion from decimal ASCII to BIN 16-bit and Double precision to Single precision conversion
32-bit data . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-191 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-105
Conversion from floating decimal point data to
BIN16- and 32-bit data (Double precision) . . . . . . 6-87
E
Conversion from floating decimal point data to
BIN16- and 32-bit data (Single precision) . . . . . . . 6-84 Encoding from 256 to 8 bits . . . . . . . . . . . . . . . . 7-73
Conversion from floating decimal point to character End main routine program . . . . . . . . . . . . . . . . . 5-51
string data . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-216 End sequence program . . . . . . . . . . . . . . . . . . . 5-53 I
Conversion from floating-point angle to radian Error display and annunciator reset instruction
(Double precision) . . . . . . . . . . . . . . . . . . . . . . 7-276 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-171
Conversion from floating-point angle to radian Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
(Single precision) . . . . . . . . . . . . . . . . . . . . . . 7-274 Expansion clock data addition operation . . . . . . 7-368
Conversion from floating-point radian to angle Expansion clock data subtraction operation . . . . 7-371
(Double precision) . . . . . . . . . . . . . . . . . . . . . . 7-280 Expansion Clock Instructions . . . . . . . . . . . . . . 7-365
Conversion from floating-point radian to angle Exponent operation on floating-point data
(Single precision) . . . . . . . . . . . . . . . . . . . . . . 7-278 (Double precision) . . . . . . . . . . . . . . . . . . . . . 7-293
Conversion from hexadecimal ASCII to BIN 16-bit Exponent operation on floating-point data
and 32-bit data . . . . . . . . . . . . . . . . . . . . . . . . 7-194 (Single precision) . . . . . . . . . . . . . . . . . . . . . . 7-290
Conversion from hexadecimal BIN to ASCII . . . . 7-227 Exponentiation operation on floating-point data
Conversion of Gray code to BIN 16 and 32-bit data (Single precision) . . . . . . . . . . . . . . . . . 7-282,7-284
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-93 Extracting character string data from the right or left
COS operation on floating-point data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-231
(Double precision) . . . . . . . . . . . . . . . . . . . . . . 7-255
COS operation on floating-point data
(Single precision) . . . . . . . . . . . . . . . . . . . . . . 7-253 F
COS-1 operation on floating-point data
File register direct 1-byte write . . . . . . . . . . . . . 7-392
(Double precision) . . . . . . . . . . . . . . . . . . . . . . 7-268
File register switching instructions . . . . . . . . . . 7-336
COS-1 operation on floating-point data
File setting for comments. . . . . . . . . . . . . . . . . 7-341
(Single precision) . . . . . . . . . . . . . . . . . . . . . . 7-266
Fixed cycle pulse output . . . . . . . . . . . . . . . . . 6-166
Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26
Floating decimal point data comparisons
Counter 1-phase input up or down . . . . . . . . . . 6-147
(Double precision) . . . . . . . . . . . . . . . . . . . . . . . 6-8
Counter 2-phase input up or down . . . . . . . . . . 6-150
Floating decimal point data comparisons
Counting Step Number . . . . . . . . . . . . . . . . . . . 3-34
(Single precision) . . . . . . . . . . . . . . . . . . . . . . . . 6-6
CPU module . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Floating decimal point to BCD . . . . . . . . . . . . . 7-244
CPU performance comparison
Floating-point data transfer (Double precision)
counters . . . . . . . . . . . . . . . . . . . . . . . . . App-145
Data that can be used by instructions . . . . . App-143
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-111
Floating-point data transfer (Single precision)
display instructions . . . . . . . . . . . . . . . . . . App-145
I/O control mode . . . . . . . . . . . . . . . . . . . App-142
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-109
Floating-point sign invertion (Double precision)
Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . App-144
Usable devices . . . . . . . . . . . . . . . . . . . . App-141
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-98
Floating-point sign invertion (Single precision) . . . 6-97
FOR to NEXT instruction loop . . . . . . . . . . . . . 7-105
D Forced end of FOR to NEXT instruction loop . . . 7-108
From BCD format data to floating decimal point
Data Control Instructions . . . . . . . . . . . . . . . . . 7-320 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-247
Data conversion instructions . . . . . . . . . . . . . . . 6-74
Data dissociation and linking in byte units . . . . . . 7-85
Data processing instructions . . . . . . . . . . . . . . . 7-66 G
Data Table Operation Instructions . . . . . . . . . . . 7-150
GX Developer . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Data Transfer Instructions . . . . . . . . . . . . . . . . 6-107
GX Works2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

Index-3
H List of instructions for reading from the CPU
shared memory of another CPU . . . . . . . . . . . . . 2-60
High Performance model QCPU . . . . . . . . . . . . . .1-5 List of instructions for reading/writing routing
High-speed Block Transfer of File Register . . . . .7-451 information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-59
How to Read Instruction Tables . . . . . . . . . . . . . . .2-4 List of instructions for Redundant system
HOW TO READ INSTRUCTIONS . . . . . . . . . . . . .4-1 (For Redundant CPU) . . . . . . . . . . . . . . . . . . . . 2-62
List of instructions for writing to the CPU shared
I memory of host CPU . . . . . . . . . . . . . . . . . . . . . 2-60
List of logical operation instructions . . . . . . . . . . . 2-29
I/O refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-145 List of master control instructions . . . . . . . . . . . . . 2-9
I/O Refresh Instructions . . . . . . . . . . . . . . . . . .6-145 List of other convenient instructions . . . . . . . . . . . 2-28
Identical 16-bit data block transfers . . . . . . . . . .6-122 List of other instructions . . . . . . . . . . . . . . . . 2-9,2-57
Identical 32-bit data block transfers . . . . . . . . . .6-125 List of output instructions . . . . . . . . . . . . . . . . . . . 2-8
Incrementing and decrementing 16-bit BIN data . .6-70 List of program branch instructions . . . . . . . . . . . 2-27
Incrementing and decrementing 32-bit BIN data . .6-72 List of program control instructions . . . . . . . . . . . 2-56
Index modification of entire ladder . . . . . . . . . . .7-143 List of program execution control instructions . . . . 2-27
Indexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-12 List of rotation instructions . . . . . . . . . . . . . . . . . 2-32
Indexing with 16-bit index registers . . . . . . . . . . .3-12 List of shift instructions . . . . . . . . . . . . . . . . . 2-8,2-33
Indexing with 32-bit . . . . . . . . . . . . . . . . . . . . . .3-13 List of special function instructions . . . . . . . . . . . . 2-46
Indirect address read operations . . . . . . . . . . . .7-394 List of structure creation instructions . . . . . . . . . . 2-38
Indirect Specification . . . . . . . . . . . . . . . . . . . . .3-23 List of switching instructions . . . . . . . . . . . . . . . . 2-51
Insertion of character string . . . . . . . . . . . . . . . .7-240 List of table operation instructions . . . . . . . . . . . . 2-40
Instructions whose designation format has been List of termination instructions . . . . . . . . . . . . . . . . 2-9
changed . . . . . . . . . . . . . . . . . . . . . . . . . . App-146 Load + Unload . . . . . . . . . . . . . . . . . . . . . . . . . 7-448
Intelligent function module. . . . . . . . . . . . . . . . . . .1-7 Load Program from Memory Card . . . . . . . . . . . 7-443
Intelligent function module device . . . . . . . . . . . . .1-7 Logical products with 16-bit and 32-bit data . . . . . . 7-3
Interrupt disable/enable instructions, interrupt Logical sums of 16-bit and 32-bit data . . . . . . . . . 7-11
program mask . . . . . . . . . . . . . . . . . . . . . . . . .6-136
M
J
Master Control Instructions . . . . . . . . . . . . . . . . . 5-47
Jump to END . . . . . . . . . . . . . . . . . . . . . . . . . .6-135 Matrix input . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-170
Maximum value search for 16- and 32-bit data . . . 7-89
MELSECNET(II/,B) . . . . . . . . . . . . . . . . . . . . . . . 1-6
L MELSECNET/10 . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
MELSECNET/H . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
L series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5
Minimum value search for 16- and 32-bit data . . . . 7-92
Ladder block series connection and parallel
Multiplication and division of floating decimal point
connection . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-10
data (Double precision) . . . . . . . . . . . . . . . . . . . 6-56
LCPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5
Multiplication and division of floating decimal point
Leading edge and trailing edge outputs . . . . . . . .5-37
data (Single precision) . . . . . . . . . . . . . . . . . . . . 6-54
Left rotation of 16-bit data . . . . . . . . . . . . . . . . . .7-38
Left rotation of 32-bit data . . . . . . . . . . . . . . . . . .7-44
Linking character strings . . . . . . . . . . . . . . . . . . .6-66 N
List of arithmetic operation instructions . . . . . . . . .2-16
List of association instructions . . . . . . . . . . . . . . . .2-7 Natural logarithm operation on floating-point data
List of bit processing instructions . . . . . . . . . . . . .2-34 (Double precision) . . . . . . . . . . . . . . . . . . . . . . 7-297
List of buffer memory access instructions . . . . . . .2-41 Natural logarithm operation on floating-point data
List of character string processing instructions. . . .2-43 (Single precision) . . . . . . . . . . . . . . . . . . . . . . . 7-295
List of clock instructions . . . . . . . . . . . . . . . . . . .2-52 n-bit shift to right or left of 16-bit data . . . . . . . . . . 7-46
List of comparison operation instructions . . . . . . .2-10 n-bit shift to right or left of n-bit data . . . . . . . . . . . 7-51
List of contact instructions . . . . . . . . . . . . . . . . . . .2-6 n-bit shift to right or left of n-word data . . . . . . . . . 7-56
List of data control instructions . . . . . . . . . . . . . .2-49 No operations . . . . . . . . . . . . . . . . . . . . . . . . . . 5-57
List of data conversion instructions. . . . . . . . . . . .2-22 Number of devices and number of transfers (n) . . . . 3-2
List of data processing instructions. . . . . . . . . . . .2-35 Numerical key input from keyboard . . . . . . . . . . 7-395
List of data transfer instructions . . . . . . . . . . . . . .2-24
List of debugging and failure diagnosis instructions O
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-42
List of display instructions . . . . . . . . . . . . . . . . . .2-41 Operation Processing Time
List of expansion clock instructions . . . . . . . . . . .2-55 Basic Model QCPU . . . . . . . . . . . . . . . . . . . .App-3
List of I/O refresh instructions . . . . . . . . . . . . . . .2-27 High Performance Model QCPU/Process
List of instructions for Multiple CPU high-speed CPU/Redundant CPU . . . . . . . . . . . . . . . . .App-21
transmission dedicated . . . . . . . . . . . . . . . . . . . .2-61 LCPU . . . . . . . . . . . . . . . . . . . . . . . . . . .App-114
List of instructions for Network refresh . . . . . . . . .2-59 Universal Model QCPU . . . . . . . . . . . . . . . .App-50
Operation result conversions. . . . . . . . . . . . . . . . 5-17

Index - 4
 Operation results inversion . . . . . . . . . . . . . . . . . 5-15 R
Operation results push,read,pop . . . . . . . . . . . . . 5-12
Operation start . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Ramp signal . . . . . . . . . . . . . . . . . . . . . . . . . . 6-161
Other Convenient Instructions . . . . . . . . . . . . . 6-147 Random number generation and series updates
Other instructions . . . . . . . . . . . . . . . . . . 5-55,7-385 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-303
Out instruction (excluding timers, counters, and Random selection from and replacement in
annunciators) . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 character strings . . . . . . . . . . . . . . . . . . . . . . . 7-234
Read Data from Standard ROM . . . . . . . . . . . . 7-441
Reading 1-/2-word data from the intelligent
P function module . . . . . . . . . . . . . . . . . . . . . . . 7-159
parallel connection . . . . . . . . . . . . . . . . . . . . . . . 5-2 Reading clock data . . . . . . . . . . . . . . . . . . . . . 7-343
Pointer branch instructions . . . . . . . . . . . . . . . . 6-132 Reading Data from Designated File . . . . . . . . . 7-427
Print ASCII code instruction . . . . . . . . . . . . . . . 7-165 Reading device comment data . . . . . . . . . . . . . 7-200
Print comment instruction . . . . . . . . . . . . . . . . . 7-168 Reading Devices from Another CPU . . . . . . . . . 10-17
Process CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Reading expansion clock data . . . . . . . . . . . . . 7-365
Program Branch Instructions . . . . . . . . . . . . . . 6-132 Reading from Other CPU Shared Memory . . . . . . 9-12
Program control instructions . . . . . . . . . . . . . . . 7-374 Reading Module Information . . . . . . . . . . . . . . 7-401
Program Execution Control Instructions . . . . . . . 6-136 Reading module model name . . . . . . . . . . . . . 7-408
Program execution status check instruction . . . . 7-383 Reading newest data from data tables . . . . . . . 7-154
Program low speed execution registration instruction Reading oldest data from tables . . . . . . . . . . . . 7-152
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-381 Reading routing information . . . . . . . . . . . . . . . . . 8-6
Program output OFF standby instruction . . . . . . 7-377 Reading/Writing Routing Information. . . . . . . . . . . 8-6 I
Program scan execution registration instruction Recovery from interrupt programs . . . . . . . . . . 6-143
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-379 Redundant CPU . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Program standby instruction . . . . . . . . . . . . . . . 7-376 Refresh instruction . . . . . . . . . . . . . . . . . . . . . 7-134
Programing Tool . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Refresh instruction for the designated module . . . . 8-2
Pulse conversions of direct outputs . . . . . . . . . . . 5-42 Registering routing information . . . . . . . . . . . . . . . 8-8
Pulse conversions of edge relay operation results Resetting devices (except for annunciators). . . . . 5-32
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 Resetting watchdog timer . . . . . . . . . . . . . . . . 7-385
Pulse density measurement . . . . . . . . . . . . . . . 6-164 Return from subroutine programs . . . . . . . . . . . 7-115
Pulse NOT operation start . . . . . . . . . . . . . . . . . . 5-7 Right rotation of 16-bit data . . . . . . . . . . . . . . . . 7-35
pulse NOT parallel connection . . . . . . . . . . . . . . . 5-7 Right rotation of 32-bit data . . . . . . . . . . . . . . . . 7-41
pulse NOT series connection . . . . . . . . . . . . . . . . 5-7 Rotary table shortest direction control . . . . . . . . 6-158
Pulse operation start . . . . . . . . . . . . . . . . . . . . . . 5-5 Rotation instruction . . . . . . . . . . . . . . . . . . . . . . 7-35
pulse parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
pulse series connection . . . . . . . . . . . . . . . . . . . . 5-5 S
Pulse width modulation . . . . . . . . . . . . . . . . . . 6-168
Scaling (Point-by-point coordinate data)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-329,7-333
Q Select Refresh Instruction . . . . . . . . . . . 7-137,7-142
Q series . . . . . . . . . ...................... 1-5 SEQUENCE INSTRUCTIONS . . . . . . . . . . . . . . . 5-1
Q3B. . . . . . . . . . . . ...................... 1-6 Sequence program stop . . . . . . . . . . . . . . . . . . 5-55
Q3DB . . . . . . . . . . ...................... 1-6 Serial number access method . . . . . . . . . . . . . . 3-47
Q3RB . . . . . . . . . . ...................... 1-6 series connection . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Q3SB . . . . . . . . . . ...................... 1-6 Setting and resetting the annunciators . . . . . . . . 5-35
Q5B. . . . . . . . . . . . ...................... 1-6 Setting and resetting the master control . . . . . . . 5-47
Q6B. . . . . . . . . . . . ...................... 1-6 Setting devices (except for annunciators) . . . . . . 5-30
Q6RB . . . . . . . . . . ...................... 1-6 Setting files for file register use . . . . . . . . . . . . 7-338
Q6WRB . . . . . . . . . ...................... 1-6 Shift instruction. . . . . . . . . . . . . . . . . . . . . . . . . 7-46
QA1S6B . . . . . . . . ...................... 1-6 Shift Instructions . . . . . . . . . . . . . . . . . . . . . . . . 5-44
QA6ADP . . . . . . . . ...................... 1-6 SIN operation on floating-point data
QA6ADP+A5B/A6B . ...................... 1-6 (Double precision) . . . . . . . . . . . . . . . . . . . . . 7-251
QA6B . . . . . . . . . . ...................... 1-6 SIN operation on floating-point data
QnCPU . . . . . . . . . ...................... 1-5 (Single precision) . . . . . . . . . . . . . . . . . . . . . . 7-249
QnHCPU . . . . . . . . ...................... 1-5 SIN-1 operation on floating point data
QnPHCPU . . . . . . . ...................... 1-5 (Single precision) . . . . . . . . . . . . . . . . . . . . . . 7-261
QnPRHCPU . . . . . . ...................... 1-5 SIN-1 operation on floating-point data
QnU(D)(H)CPU . . . . ...................... 1-5 (Double precision) . . . . . . . . . . . . . . . . . . . . . 7-264
QnUCPU . . . . . . . . ...................... 1-5 Single precision to Double precision conversion
QnUD(H)CPU . . . . . ...................... 1-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-103
QnUDE(H)CPU . . . . ...................... 1-5 Source (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Special format failure checks . . . . . . . . . . . . . . 7-174
Special function instructions . . . . . . . . . . . . . . . 7-249
Special function timer . . . . . . . . . . . . . . . . . . . 6-155

Index-5
 Square root operation for floating-point data
(Double precision) . . . . . . . . . . . . . . . . . . . . . .7-288
Square root operation for floating-point data
(Single precision) . . . . . . . . . . . . . . . . . . . . . . .7-286
standard device registers (Z) . . . . . . . . . . . . . . . .3-26
Structure creation instructions . . . . . . . . . . . . . .7-105
Subroutine calls between program files . . . . . . .7-120
Subroutine output OFF calls between program files
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-125
Subroutine program call . . . . . . . . . . . . . . . . . .7-129
Subroutine program calls . . . . . . . . . . . . . . . . .7-110
Subroutine program output OFF calls . . . . . . . . .7-116
Subset Processing . . . . . . . . . . . . . . . . . . . . . . .3-25
Switching file register numbers . . . . . . . . . . . . .7-336
System Switching Instruction . . . . . . . . . . . . . . . .11-2

T
TAN operation on floating-point data
(Double precision) . . . . . . . . . . . . . . . . . . . . . .7-259
TAN operation on floating-point data
(Single precision) . . . . . . . . . . . . . . . . . . . . . . .7-257
TAN-1 operation on floating-point data
(Double precision) . . . . . . . . . . . . . . . . . . . . . .7-272
TAN-1 operation on floating-point data
(Single precision) . . . . . . . . . . . . . . . . . . . . . . .7-270
Teaching timer . . . . . . . . . . . . . . . . . . . . . . . . .6-153
Termination Instructions . . . . . . . . . . . . . . . . . . .5-51
Time check instruction . . . . . . . . . . . . . . . . . . .7-389
Time data conversion (from Hour/Minute/Second to
Second) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-351
Time data conversion (from Second to
Hour/Minute/Second) . . . . . . . . . . . . . . . . . . . .7-353
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-22
Timing pulse generation . . . . . . . . . . . . . . . . . .7-387
Trace Set/Reset . . . . . . . . . . . . . . . . . . . . . . . .7-413
Types of Instructions . . . . . . . . . . . . . . . . . . . . . .2-2

U
Universal model QCPU . . . . . . . . . . . . . . . . . . . . .1-5
Unload Program from Program Memory . . . . . . .7-446
Upper and lower byte exchanges . . . . . . . . . . . .6-131
Upper and lower limit controls for BIN 16-bit and
BIN 32-bit data. . . . . . . . . . . . . . . . . . . . . . . . .7-320
User Message . . . . . . . . . . . . . . . . . . . . . . . . .7-456

W
Write to Host CPU Shared Memory . . . . . . . . . . . .9-4
Writing 1-/2-word data to intelligent function module
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-162
Writing clock data . . . . . . . . . . . . . . . . . . . . . . .7-345
Writing Data to Designated File . . . . . . . . . . . . .7-415
Writing Data to Standard ROM . . . . . . . . . . . . .7-439
Writing data to the data table . . . . . . . . . . . . . . .7-150
Writing Devices to Another CPU . . . . . . . . . . . .10-13
Writing to host station CPU shared memory . . . . . .9-7

Z
Zone control for BIN 16-bit and BIN 32-bit data . .7-326

Index - 6
 INSTRUCTION INDEX

Symbols BKBIN(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-101

BKCMP …. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15
$+(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-66 BKCMP … P . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15
$< . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 BKOR(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17
$<= . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 BKRST(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-64
$<> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 BKXNR(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-33
$= . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 BKXOR(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-25
$> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 BMOV(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-118
$>= . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 BREAK(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-108
$MOV(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-113 BRST(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-59
-(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 BSET(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-59
*(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30 BSFL(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-49
+(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 BSFR(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-49
/(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30 BSIN(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-308
<. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 BSQR(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-305
<= . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 BTAN(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-312
<> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 BTOW(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-85
=. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 BXCH(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-129 I
>. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
>= . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
C
A CALL(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-110
CCOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-142
ACOS(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-266 CHK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-174
ACOSD(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-268 CHKCIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-178
ADRSET(P) . . . . . . . . . . . . . . . . . . . . . . . . . . 7-394 CHKEND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-178
ANB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 CHKST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-174
AND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 CJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-132
ANDF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 CML(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-115
ANDFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 COM . . . . . . . . . . . . . . . . . . . . . . . . . . 7-134,7-137
ANDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 COMRD(P) . . . . . . . . . . . . . . . . . . . . . . . . . . 7-200
ANDPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 COS(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-253
ANI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 COSD(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-255
ASC(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-227
ASIN(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-261
ASIND(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-264 D
ATAN(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-270 D-(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26
ATAND(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-272 D(P).DDRD . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17
D(P).DDWR . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
B D*(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32
D+(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26
B-(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-34 D/(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32
B*(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-42 D< . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
B+(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-34 D<=. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
B/(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-42 D<>. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
BACOS(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-316 D= . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
BAND(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-323 D> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
BASIN(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-314 D>=. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
BATAN(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-318 DABCD(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-197
BCD(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-74 DABIN(P). . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-191
BCDDA(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-188 DAND(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
BCOS(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-310 DATE-(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-349
BDSQR(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-305 DATE+(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-347
BIN(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-76 DATERD(P) . . . . . . . . . . . . . . . . . . . . . . . . . . 7-343
BINDA(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-182 DATEWR(P) . . . . . . . . . . . . . . . . . . . . . . . . . 7-345
BINHA(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-185 DB-(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-38
BK-(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-59 DB*(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-44
BK+(P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-59 DB+(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-38
BKAND(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 DB/(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-44
BKBCD(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-99

Index-7
 DBAND(P). . . . . . . . . . . . . . . . . . . . . . . . . . . .7-323 DXOR(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19
DBCD(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-74 DZONE(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-326
DBCDDA(P) . . . . . . . . . . . . . . . . . . . . . . . . . .7-188
DBIN(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-76
E
DBINDA(P) . . . . . . . . . . . . . . . . . . . . . . . . . . .7-182
DBINHA(P) . . . . . . . . . . . . . . . . . . . . . . . . . . .7-185 E-(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-46
DBK-(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-62 E*(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-54
DBK+(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-62 E+(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-46
DBKCMP … . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 E/(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-54
DBKCMP … P . . . . . . . . . . . . . . . . . . . . . . . . . .6-18 E< . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
DBL(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-89 E<= . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
DCML(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-115 E<> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
DDABCD(P) . . . . . . . . . . . . . . . . . . . . . . . . . .7-197 E= . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
DDABIN(P) . . . . . . . . . . . . . . . . . . . . . . . . . . .7-191 E> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
DDEC(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-72 E>= . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
DEC(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-70 ECALL(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-120
DECO(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-71 ECON(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-103
DEG(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-278 ED-(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-50
DEGD(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-280 ED*(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-56
DELTA(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-42 ED+(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-50
DFLT(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-79 ED/(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-56
DFLTD(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-82 ED< . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
DFMOV(P) . . . . . . . . . . . . . . . . . . . . . . . . . . .6-125 ED<= . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
DFRO(P) . . . . . . . . . . . . . . . . . . . . . . . . .7-159,9-12 ED<> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
DGBIN(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-93 ED= . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
DGRY(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-91 ED> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
DHABIN(P) . . . . . . . . . . . . . . . . . . . . . . . . . . .7-194 ED>= . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-136 EDCON(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-105
DINC(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-72 EDMOV(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-111
DINT(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-84 EDNEG(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-98
DINTD(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-87 EFCALL(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-125
DIS(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-77 EGF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18
DLIMIT(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-320 EGP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18
DMAX(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-89 EI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-136
DMEAN(P) . . . . . . . . . . . . . . . . . . . . . . . . . . .7-103 EMOD(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-244
DMIN(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-92 EMOV(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-109
DMOV(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-107 ENCO(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-73
DNEG(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-95 END . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-53
DOR(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-11 ENEG(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-97
DRCL(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-44 EREXP(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-247
DRCR(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-41 ESTR(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-216
DROL(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-44 EVAL(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-223
DROR(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-41 EXP(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-290
DSCL(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-329 EXPD(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-293
DSCL2(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-333
DSER(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-66
DSFL(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-54 F
DSFR(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-54
FCALL(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-116
DSORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-95
FDEL(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-156
DSTR(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-205
FEND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-51
DSUM(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-69
FF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-40
DT< . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-355
FIFR(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-152
DT<= . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-355
FIFW(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-150
DT<> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-355
FINS(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-156
DT= . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-355
FLT(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-79
DT> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-355
FLTD(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-82
DT>= . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-355
FMOV(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-122
DTEST(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-61
FOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-105
DTO(P) . . . . . . . . . . . . . . . . . . . . . . . . . . .7-162,9-7
FPOP(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-154
DUTY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-387
FROM(P) . . . . . . . . . . . . . . . . . . . . . . . . 7-159,9-12
DVAL(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-211
DWSUM(P) . . . . . . . . . . . . . . . . . . . . . . . . . . .7-101
DXCH(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-127 G
DXNR(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-27
GBIN(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-93

Index - 8
 GOEND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-135 MTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-170
GRY(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-91
N
H
NDIS(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-81
HABIN(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-194 NEG(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-95
HEX(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-229 NEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-105
HOUR(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-353 NOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-57
NOPLF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-57
NUNI(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-81
I
IMASK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-136 O
INC(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-70
INSTR(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-238 OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
INT(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-84 ORB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
INTD(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-87 ORF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
INV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 ORFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
IRET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-143 ORI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
IX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-143 ORP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
IXDEV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-147 ORPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
IXEND . . .
IXSET . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . 7-143
. . . . . . . . . . . . . . . . . . . . . . . . . . . 7-147
OUT . . .
OUT C . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26
I
OUT F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28
OUT T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22
J
OUTH T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22
JMP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-132
P
K
PAGE n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-57
KEY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-395 PCHK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-383
PLF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37
PLOADP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-443
L PLOW(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-381
PLS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37
LD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 PLSY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-166
LDF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 POFF(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-377
LDFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 POW(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-282
LDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 POWD(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-284
LDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 PR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-165
LDPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 PRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-168
LEDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-171 PSCAN(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-379
LEFT(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-231 PSTOP(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-376
LEN(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-203 PSWAPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-448
LIMIT(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-320 PUNLOADP . . . . . . . . . . . . . . . . . . . . . . . . . . 7-446
LOG(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-295 PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-168
LOG10(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-299
LOG10D(P) . . . . . . . . . . . . . . . . . . . . . . . . . . 7-301
LOGD(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-297 Q
QCDSET(P) . . . . . . . . . . . . . . . . . . . . . . . . . . 7-341
M QDRSET(P) . . . . . . . . . . . . . . . . . . . . . . . . . . 7-338
MAX(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-89
MC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-47 R
MCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-47
MEAN(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-103 RAD(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-274
MEF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 RADD(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-276
MEP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 RAMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-161
MIDR(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-234 RBMOV(P). . . . . . . . . . . . . . . . . . . . . . . . . . . 7-451
MIDW(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-234 RCL(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-38
MIN(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-92 RCR(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-35
MOV(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-107 RET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-115
MPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 RFS(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-145
MPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 RIGHT(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-231
MRD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 RND(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-303

Index-9
 ROL(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-38 TRACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-413
ROR(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-35 TRACER . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-413
ROTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-158 TTMR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-153
RSET(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-336 TYPERD(P) . . . . . . . . . . . . . . . . . . . . . . . . . . 7-408
RST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-32
RST F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-35
U

S UDCNT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-147
UDCNT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-150
S(P).DATE- . . . . . . . . . . . . . . . . . . . . . . . . . . .7-371 UMSG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-456
S(P).DATE+ . . . . . . . . . . . . . . . . . . . . . . . . . .7-368 UNI(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-79
S(P).DATERD . . . . . . . . . . . . . . . . . . . . . . . . .7-365 UNIRD(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-401
S(P).DEVLD . . . . . . . . . . . . . . . . . . . . . . . . . .7-441
S(P).RTREAD . . . . . . . . . . . . . . . . . . . . . . . . . . .8-6
V
S(P).RTWRITE . . . . . . . . . . . . . . . . . . . . . . . . . .8-8
S(P).TO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-4 VAL(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-211
S(P).ZCOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-2
SCJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-132
SCL(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-329 W
SCL2(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-333
WAND(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
SECOND(P) . . . . . . . . . . . . . . . . . . . . . . . . . .7-351
WDT(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-385
SEG(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-75
WOR(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
SER(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-66
WORD(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-90
SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-30
WSUM(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-99
SET F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-35
WTOB(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-85
SFL(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-46
WXNR(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-27
SFR(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-46
WXOR(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19
SFT(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-44
SFTBL(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-51
SFTBR(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-51 X
SFTWL(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-56
SFTWR(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-56 XCALL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-129
SIN(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-249 XCH(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-127
SIND(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-251
SORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-95 Z
SP.CONTSW. . . . . . . . . . . . . . . . . . . . . . . . . . .11-2
SP.DEVST . . . . . . . . . . . . . . . . . . . . . . . . . . .7-439 ZONE(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-326
SP.FREAD . . . . . . . . . . . . . . . . . . . . . . . . . . .7-427 ZPOP(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-399
SP.FWRITE. . . . . . . . . . . . . . . . . . . . . . . . . . .7-415 ZPUSH(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-399
SPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-164 ZRRDB(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-390
SQR(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-286 ZRWRB(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-392
SQRD(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-288
SRND(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-303
STMR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-155
STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-55
STR(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-205
STRDEL(P) . . . . . . . . . . . . . . . . . . . . . . . . . . .7-242
STRINS(P) . . . . . . . . . . . . . . . . . . . . . . . . . . .7-240
SUM(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-69
SWAP(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-131

T
TAN(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-257
TAND(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-259
TEST(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-61
TIMCHK . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-389
TM< . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-360
TM<= . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-360
TM<> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-360
TM= . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-360
TM> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-360
TM>= . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-360
TO(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-162,9-7

Index - 10
Warranty
Please confirm the following product warranty details before using this product.
1. Gratis Warranty Term and Gratis Warranty Range
If any faults or defects (hereinafter "Failure") found to be the responsibility of Mitsubishi occurs during use of the
product within the gratis warranty term, the product shall be repaired at no cost via the sales representative or
Mitsubishi Service Company.
However, if repairs are required onsite at domestic or overseas location, expenses to send an engineer will be
solely at the customer's discretion. Mitsubishi shall not be held responsible for any re-commissioning,
maintenance, or testing on-site that involves replacement of the failed module.
[Gratis Warranty Term]
The gratis warranty term of the product shall be for one year after the date of purchase or delivery to a designated
place.
Note that after manufacture and shipment from Mitsubishi, the maximum distribution period shall be six (6) months,
and the longest gratis warranty term after manufacturing shall be eighteen (18) months. The gratis warranty term of
repair parts shall not exceed the gratis warranty term before repairs.
[Gratis Warranty Range]
(1) The range shall be limited to normal use within the usage state, usage methods and usage environment, etc.,
which follow the conditions and precautions, etc., given in the instruction manual, user's manual and caution
labels on the product.
(2) Even within the gratis warranty term, repairs shall be charged for in the following cases.
1. Failure occurring from inappropriate storage or handling, carelessness or negligence by the user. Failure
caused by the user's hardware or software design.
2. Failure caused by unapproved modifications, etc., to the product by the user.
3. When the Mitsubishi product is assembled into a user's device, Failure that could have been avoided if
functions or structures, judged as necessary in the legal safety measures the user's device is subject to or
as necessary by industry standards, had been provided.
4. Failure that could have been avoided if consumable parts (battery, backlight, fuse, etc.) designated in the
instruction manual had been correctly serviced or replaced.
5. Failure caused by external irresistible forces such as fires or abnormal voltages, and Failure caused by force
majeure such as earthquakes, lightning, wind and water damage.
6. Failure caused by reasons unpredictable by scientific technology standards at time of shipment from
Mitsubishi.
7. Any other failure found not to be the responsibility of Mitsubishi or that admitted not to be so by the user.
2. Onerous repair term after discontinuation of production
(1) Mitsubishi shall accept onerous product repairs for seven (7) years after production of the product is
discontinued.
Discontinuation of production shall be notified with Mitsubishi Technical Bulletins, etc.
(2) Product supply (including repair parts) is not available after production is discontinued.
3. Overseas service
Overseas, repairs shall be accepted by Mitsubishi's local overseas FA Center. Note that the repair conditions at
each FA Center may differ.
4. Exclusion of loss in opportunity and secondary loss from warranty liability
Regardless of the gratis warranty term, Mitsubishi shall not be liable for compensation of damages caused by any
cause found not to be the responsibility of Mitsubishi, loss in opportunity, lost profits incurred to the user by Failures
of Mitsubishi products, special damages and secondary damages whether foreseeable or not , compensation for
accidents, and compensation for damages to products other than Mitsubishi products, replacement by the user,
maintenance of on-site equipment, start-up test run and other tasks.
5. Changes in product specifications
The specifications given in the catalogs, manuals or technical documents are subject to change without prior notice.
Microsoft, Windows, Windows NT are registered trademarks of Microsoft Corporation in the United States and other
countries.
Pentium and Celeron are trademarks of Intel Corporation in the United States and other countries.
Ethernet is a trademark of Xerox Co., Ltd. in the United States.
CompactFlash is a trademark of SanDisk Corporation.
VxWorks, Tornado, WindPower, WindSh and WindView are registered trademarks of Wind River Systems, Inc.
Other company names and product names used in this document are trademarks or registered trademarks of respective
owners.

SH(NA)-080809ENG-D 1/2
 SAFETY PRECAUTIONS
(Always read these cautions before using the product)

Before using this product, please read this manual and the related manuals introduced in this manual,
and pay full attention to safety to handle the product correctly.

Please store this manual in a safe place and make it accessible when required. Always forward a copy of
the manual to the end user.

A-1
 CONDITIONS OF USE FOR THE PRODUCT
(1) Mitsubishi programmable controller ("the PRODUCT") shall be used in conditions;
i) where any problem, fault or failure occurring in the PRODUCT, if any, shall not lead to any
major or serious accident; and
ii) where the backup and fail-safe function are systematically or automatically provided
outside of the PRODUCT for the case of any problem, fault or failure occurring in the
PRODUCT.

(2) The PRODUCT has been designed and manufactured for the purpose of being used in
general industries.
MITSUBISHI SHALL HAVE NO RESPONSIBILITY OR LIABILITY (INCLUDING, BUT NOT
LIMITED TO ANY AND ALL RESPONSIBILITY OR LIABILITY BASED ON CONTRACT,
WARRANTY, TORT, PRODUCT LIABILITY) FOR ANY INJURY OR DEATH TO PERSONS OR
LOSS OR DAMAGE TO PROPERTY CAUSED BY the PRODUCT THAT ARE OPERATED OR
USED IN APPLICATION NOT INTENDED OR EXCLUDED BY INSTRUCTIONS, PRECAUTIONS,
OR WARNING CONTAINED IN MITSUBISHI'S USER, INSTRUCTION AND/OR SAFETY
MANUALS, TECHNICAL BULLETINS AND GUIDELINES FOR the PRODUCT.
("Prohibited Application")
Prohibited Applications include, but not limited to, the use of the PRODUCT in;
• Nuclear Power Plants and any other power plants operated by Power companies, and/or
any other cases in which the public could be affected if any problem or fault occurs in the
PRODUCT.
• Railway companies or Public service purposes, and/or any other cases in which
establishment of a special quality assurance system is required by the Purchaser or End
User.
• Aircraft or Aerospace, Medical applications, Train equipment, transport equipment such
as Elevator and Escalator, Incineration and Fuel devices, Vehicles, Manned transportation,
Equipment for Recreation and Amusement, and Safety devices, handling of Nuclear or
Hazardous Materials or Chemicals, Mining and Drilling, and/or other applications where
there is a significant risk of injury to the public or property.

A-2
REVISIONS
*The manual number is given on the bottom left of the back cover.

Print Date *Manual Number Revision

Dec., 2008 SH (NA)-080809ENG-A First edition

Mar., 2009 SH (NA)-080809ENG-B Partial corrections

Section 3.3, 3.8, 5.1.3, 6.1.7, 6.2.14, 7.3.3, 7.11.18, 7.11.19, 7.12.1.5,12.7, 7.12.11, 7.12.25,
7.12.26, 7.13.4, 7.13.5, 7.15.7, 7.15.8

Jul., 2009 SH (NA)-080809ENG-C Revision because of function support by the Universal model QCPU having a
serial number "11043" or later
Partial corrections
Section 2.1, 2.5.6, 2.5.18, 2.5.20, 7.6.9, 7.12.7, 7.12.11, 12.1.3, 12.1.4, APPENDIX 1.2, 1.3, 1.4.2,
3, 5.1
Additions
Section 2.5.16, 7.16, 7.18.10
Modification
Section 2.5.21 2.5.22, Section 2.5.22 2.5.21, Section 9.13 7.6.10,
Section 9.14 7.6.1, Section 9.15 7.16, Section 9.15.1 7.16.1, Section 9.15.2 7.16.2,
Section 9.15.3 7.16.3, Section 9.1 7.18.9, Section 9.2 7.18.11, Section 9.3 7.18.12,
Section 9.4 7.18.13, Section 9.5 7.18.14, Section 9.6 7.18.15, Section 9.7 7.18.16,
Section 9.8 7.18.17, Section 9.9 7.18.18, Section 9.10 7.18.19, Section 9.11 9.1,
Section 9.11.1 9.1.1, Section 9.11.2 9.1.2, Section 9.12 9.2, Section 9.12.1 9.2.1,
Chapter 10 11, Chapter 11 10

Jan., 2010 SH (NA)-080809ENG-D Model Additions

L02CPU, L26CPU-BT
Partial corrections
SAFETY PRECAUTIONS, INTRODUCTION, MANUALS, Chapter 1, Section 2.3.2, 2.4.1, 2.4.2,
2.4.3, 2.4.4, 2.5.1, 2.5.6, 2.5.18, 3.2.4, 3.3, 3.4, 3.5.1, 3.5.2, 3.6, 3.8, 3.10, Chapter 4, 5, 6, 7, 8, 9,
10, 11, 12, APPENDIX 1.1, 2.1, 3, 4, INDEX, Warranty
Additions
CONDITIONS OF USE FOR THE PRODUCT, Section 2.6.1, 2.6.2, 2.7.1, 2.7.2, 2.8.1, 2.9.1,
7.18.20, 7.18.21, APPENDIX 1.5
Modification
Section 2.5.19 2.6, Section 2.5.20 2.7, Section 2.5.21 2.8, Section 2.5.22 2.9

Japanese Manual Version SH-080804-D

This manual confers no industrial property rights or any rights of any other kind, nor does it confer any patent licenses.
Mitsubishi Electric Corporation cannot be held responsible for any problems involving industrial property rights which may
occur as a result of using the contents noted in this manual.
© 2008 MITSUBISHI ELECTRIC CORPORATION

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 INTRODUCTION
This document is the MELSEC-Q/L Programming Manual (Common Instructions). It describes the common
instructions required for programming of the QCPU and LCPU.

• "Common instructions" are all instructions except for dedicated instructions for such intelligent function
modules as QJ71C24N and QJ71E71-100; PID control instructions; SFC instructions; ST instructions;
instructions for socket communication features; trigger logging instructions; and dedicated instructions for
LPCU positioning/counter functionality.

Please read this manual and other relevant manuals carefully before using this product. Please familiarize
yourself with the functions and performance of the Q series and L series sequencers in order to handle this
product correctly.

■ Relevant CPU module

CPU module Model
Basic model QCPU Q00JCPU, Q00CPU, Q01CPU
High Perfomance model QCPU Q02CPU, Q02HCPU, Q06HCPU, Q12HCPU, Q25HCPU
Process CPU Q02PHCPU, Q06PHCPU, Q12PHCPU, Q25PHCPU
Redundant CPU Q12PRHCPU, Q25PRHCPU
Q00UJCPU, Q00UCPU, Q01UCPU, Q02UCPU, Q03UDCPU,
Q04UDHCPU, Q06UDHCPU, Q10UDHCPU, Q13UDHCPU,
Universal model QCPU Q20UDHCPU, Q26UDHCPU, Q03UDECPU, Q04UDEHCPU,
Q06UDEHCPU, Q10UDEHCPU, Q13UDEHCPU,
Q20UDEHCPU
LCPU L02CPU, L26CPU-BT

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MEMO

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 CONTENTS
SAFETY PRECAUTIONS ..................................................................................................................A - 1
CONDITIONS OF USE FOR THE PRODUCT ..................................................................................A - 2
REVISIONS .......................................................................................................................................A - 3
INTRODUCTION ...............................................................................................................................A - 4
CONTENTS .......................................................................................................................................A - 6
MANUALS........................................................................................................................................A - 17

Common Instructions 1/2

1. GENERAL DESCRIPTION 1 - 1 to 1 - 8
1.1 Related Programming Manuals 1-2
1.2 Abbreviations and Generic Names 1-5

2. INSTRUCTION TABLES 2 - 1 to 2 - 62
2.1 Types of Instructions 2-2
2.2 How to Read Instruction Tables 2-4
2.3 Sequence Instructions 2-6
2.3.1 Contact instructions ...................................................................................................... 2 - 6
2.3.2 Association instructions ................................................................................................ 2 - 7
2.3.3 Output instructions........................................................................................................ 2 - 8
2.3.4 Shift instructions ........................................................................................................... 2 - 8
2.3.5 Master control instructions............................................................................................ 2 - 9
2.3.6 Termination instructions ............................................................................................... 2 - 9
2.3.7 Other instructions ......................................................................................................... 2 - 9
2.4 Basic instructions 2 - 10
2.4.1 Comparison operation instructions ............................................................................. 2 - 10
2.4.2 Arithmetic operation instructions ................................................................................ 2 - 16
2.4.3 Data conversion instructions ...................................................................................... 2 - 22
2.4.4 Data transfer instructions............................................................................................ 2 - 24
2.4.5 Program branch instructions....................................................................................... 2 - 27
2.4.6 Program execution control instructions ...................................................................... 2 - 27
2.4.7 I/O refresh instructions ............................................................................................... 2 - 27
2.4.8 Other convenient instructions ..................................................................................... 2 - 28
2.5 Application Instructions 2 - 29
2.5.1 Logical operation instructions ..................................................................................... 2 - 29
2.5.2 Rotation instructions ................................................................................................... 2 - 32
2.5.3 Shift instructions ......................................................................................................... 2 - 33
2.5.4 Bit processing instructions.......................................................................................... 2 - 34
2.5.5 Data processing instructions ...................................................................................... 2 - 35
2.5.6 Structure creation instructions .................................................................................... 2 - 38
2.5.7 Data table operation instructions ................................................................................ 2 - 40
2.5.8 Buffer memory access instructions............................................................................. 2 - 41
2.5.9 Display instructions..................................................................................................... 2 - 41
2.5.10 Debugging and failure diagnosis instructions ............................................................. 2 - 42

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 2.5.11 Character string processing instructions .................................................................... 2 - 43
2.5.12 Special function instructions ....................................................................................... 2 - 46
2.5.13 Data control instructions ............................................................................................. 2 - 49
2.5.14 Switching instructions ................................................................................................. 2 - 51
2.5.15 Clock instructions ....................................................................................................... 2 - 52
2.5.16 Expansion clock instruction ........................................................................................ 2 - 55
2.5.17 Program control instructions....................................................................................... 2 - 56
2.5.18 Other instructions ....................................................................................................... 2 - 57
2.6 Instructions for Data Link 2 - 59
2.6.1 Instructions for Network refresh.................................................................................. 2 - 59
2.6.2 Instructions for Reading/Writing Routing Information ................................................. 2 - 59
2.7 Multiple CPU dedicated instruction 2 - 60
2.7.1 Instructions for Writing to the CPU Shared Memory of Host CPU.............................. 2 - 60
2.7.2 Instructions for Reading from the CPU Shared Memory of Another CPU .................. 2 - 60
2.8 Multiple CPU high-speed transmission dedicated instruction 2 - 61
2.8.1 Instructions for Multiple CPU high-speed transmission dedicated ............................. 2 - 61
2.9 Redundant system instructions (For Redundant CPU) 2 - 62
2.9.1 Instructions for Redundant system (For Redundant CPU) ......................................... 2 - 62

3. CONFIGURATION OF INSTRUCTIONS 3 - 1 to 3 - 48
3.1 Configuration of Instructions 3-2
3.2 Designating Data 3-3
3.2.1 Using bit data................................................................................................................ 3 - 3
3.2.2 Using word (16 bits) data.............................................................................................. 3 - 4
3.2.3 Using double word data (32 bits).................................................................................. 3 - 6
3.2.4 Using real number data ................................................................................................ 3 - 8
3.2.5 Using character string data......................................................................................... 3 - 11
3.3 Indexing 3 - 12
3.4 Indirect Specification 3 - 23
3.5 Reducing Instruction Processing Time 3 - 25
3.5.1 Subset Processing...................................................................................................... 3 - 25
3.5.2 Operation processing with standard device registers (Z) (Universal model QCPU and
LCPU only) ................................................................................................................. 3 - 26
3.6 Cautions on Programming (Operation Errors) 3 - 27
3.7 Conditions for Execution of Instructions 3 - 33
3.8 Counting Step Number 3 - 34
3.9 Operation when the OUT, SET/RST, or PLS/PLF Instructions Use the Same Device 3 - 40
3.10 Precautions for Use of File Registers 3 - 45

4. HOW TO READ INSTRUCTIONS 4 - 1 to 4 - 4

5. SEQUENCE INSTRUCTIONS 5 - 1 to 5 - 60
5.1 Contact Instructions 5-2
5.1.1 Operation start, series connection, parallel connection (LD,LDI,AND,ANI,OR,ORI).... 5 - 2

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 5.1.2 Pulse operation start, pulse series connection, pulse parallel connection
(LDP,LDF,ANDP,ANDF,ORP,ORF) ............................................................................. 5 - 5
5.1.3 Pulse NOT operation start, pulse NOT series connection, pulse NOT parallel connection
(LDPI,LDFI,ANDPI,ANDFI,ORPI,ORFI) ....................................................................... 5 - 7
5.2 Association Instructions 5 - 10
5.2.1 Ladder block series connection and parallel connection (ANB,ORB) ........................ 5 - 10
5.2.2 Operation results push,read,pop (MPS,MRD,MPP) ................................................... 5 - 12
5.2.3 Operation results inversion (INV) ............................................................................... 5 - 15
5.2.4 Operation result conversions (MEP,MEF) .................................................................. 5 - 17
5.2.5 Pulse conversions of edge relay operation results (EGP,EGF).................................. 5 - 18
5.3 Output Instructions 5 - 20
5.3.1 Out instruction (excluding timers, counters, and annunciators) (OUT)....................... 5 - 20
5.3.2 Timers (OUT T,OUTH T) ............................................................................................ 5 - 22
5.3.3 Counter (OUT C) ........................................................................................................ 5 - 26
5.3.4 Annunciator output (OUT F) ....................................................................................... 5 - 28
5.3.5 Setting devices (except for annunciators) (SET) ........................................................ 5 - 30
5.3.6 Resetting devices (except for annunciators) (RST).................................................... 5 - 32
5.3.7 Setting and resetting the annunciators (SET F,RST F) .............................................. 5 - 35
5.3.8 Leading edge and trailing edge outputs (PLS,PLF).................................................... 5 - 37
5.3.9 Bit device output reverse (FF) .................................................................................... 5 - 40
5.3.10 Pulse conversions of direct outputs (DELTA(P)) ........................................................ 5 - 42
5.4 Shift Instructions 5 - 44
5.4.1 Bit device shifts (SFT(P))............................................................................................ 5 - 44
5.5 Master Control Instructions 5 - 47
5.5.1 Setting and resetting the master control (MC,MCR)................................................... 5 - 47
5.6 Termination Instructions 5 - 51
5.6.1 End main routine program (FEND)............................................................................. 5 - 51
5.6.2 End sequence program (END) ................................................................................... 5 - 53
5.7 Other instructions 5 - 55
5.7.1 Sequence program stop (STOP) ................................................................................ 5 - 55
5.7.2 No operations (NOP,NOPLF,PAGE n) ....................................................................... 5 - 57

6. BASIC INSTRUCTIONS 6 - 1 to 6 - 172

6.1 Comparison Operation Instructions 6-2
6.1.1 BIN 16-bit data comparisons (=,<>,>,<=,<,>=) ............................................................. 6 - 2
6.1.2 BIN 32-bit data comparisons (D=,D<>,D>,D<=,D<,D>=) ............................................. 6 - 4
6.1.3 Floating decimal point data comparisons (Single precision)
(E=,E<>,E>,E<=,E<,E>=) ............................................................................................. 6 - 6
6.1.4 Floating decimal point data comparisons (Double precision)
(ED=,ED<>,ED>,ED<=,ED<,ED>=) ............................................................................. 6 - 8
6.1.5 Character string data comparisons ($=,$<>,$>,$<=,$<,$>=) ..................................... 6 - 11
6.1.6 BIN block data comparisons (BKCMP … ,BKCMP … P) ............................................ 6 - 15
6.1.7 BIN 32-bit block data comparisons (DBKCMP … ,DBKCMP … P) ............................ 6 - 18
6.2 Arithmetic Operation Instructions 6 - 22
6.2.1 BIN 16-bit addition and subtraction operations (+(P),-(P)) ......................................... 6 - 22
6.2.2 BIN 32-bit addition and subtraction operations (D+(P),D-(P)) .................................... 6 - 26

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 6.2.3 BIN 16-bit multiplication and division operations (*(P),/(P))........................................ 6 - 30
6.2.4 BIN 32-bit multiplication and division operations (D*(P),D/(P)) .................................. 6 - 32
6.2.5 BCD 4-digit addition and subtraction operations (B+(P),B-(P)) .................................. 6 - 34
6.2.6 BCD 8-digit addition and subtraction operations (DB+(P),DB-(P)) ............................. 6 - 38
6.2.7 BCD 4-digit multiplication and division operations (B*(P),B/(P)) ................................ 6 - 42
6.2.8 BCD 8-digit multiplication and division operations (DB*(P),DB/(P)) ........................... 6 - 44
6.2.9 Addition and subtraction of floating decimal point data
(Single precision) (E+(P),E-(P)).................................................................................. 6 - 46
6.2.10 Addition and subtraction of floating decimal point data
(Double precision) (ED+(P),ED-(P)) ........................................................................... 6 - 50
6.2.11 Multiplication and division of floating decimal point data
(Single precision) (E*(P),E/(P))................................................................................... 6 - 54
6.2.12 Multiplication and division of floating decimal point data
(Double precision) (ED*(P),ED/(P)) ............................................................................ 6 - 56
6.2.13 Block addition and subtraction (BK+(P),BK-(P))......................................................... 6 - 59
6.2.14 BIN 32-bit data block addition and subtraction operations (DBK+(P),DBK-(P)) ........ 6 - 62
6.2.15 Linking character strings ($+(P)) ................................................................................ 6 - 66
6.2.16 Incrementing and decrementing 16-bit BIN data (INC(P),DEC(P)) ............................ 6 - 70
6.2.17 Incrementing and decrementing 32-bit BIN data (DINC(P),DDEC(P)) ....................... 6 - 72
6.3 Data conversion instructions 6 - 74
6.3.1 Conversion from BIN data to 4-digit and 8-digit BCD (BCD(P),DBCD(P)) ................. 6 - 74
6.3.2 Conversion from BCD 4-digit and 8-digit data to BIN data (BIN(P),DBIN(P)) ............ 6 - 76
6.3.3 Conversion from BIN 16 and 32-bit data to floating decimal point (Single precision)
(FLT(P),DFLT(P)) ....................................................................................................... 6 - 79
6.3.4 Conversion from BIN 16 and 32-bit data to floating decimal point (Double precision)
(FLTD(P),DFLTD(P)) .................................................................................................. 6 - 82
6.3.5 Conversion from floating decimal point data to BIN16- and 32-bit data (Single precision)
(INT(P),DINT(P)) ........................................................................................................ 6 - 84
6.3.6 Conversion from floating decimal point data to BIN16- and 32-bit data (Double precision)
(INTD(P),DINTD(P)) ................................................................................................... 6 - 87
6.3.7 Conversion from BIN 16-bit to BIN 32-bit data (DBL(P)) ............................................ 6 - 89
6.3.8 Conversion from BIN 32-bit to BIN 16-bit data (WORD(P))........................................ 6 - 90
6.3.9 Conversion from BIN 16 and 32-bit data to Gray code (GRY(P),DGRY(P)) .............. 6 - 91
6.3.10 Conversion of Gray code to BIN 16 and 32-bit data (GBIN(P),DGBIN(P))................. 6 - 93
6.3.11 Complement of 2 of BIN 16- and 32-bit data (sign reversal) (NEG(P),DNEG(P)) ...... 6 - 95
6.3.12 Floating-point sign invertion (Single precision) (ENEG(P)) ........................................ 6 - 97
6.3.13 Floating-point sign invertion (Double precision) (EDNEG(P)) .................................... 6 - 98
6.3.14 Conversion from block BIN 16-bit data to BCD 4-digit data (BKBCD(P))................... 6 - 99
6.3.15 Conversion from block BCD 4-digit data to block BIN 16-bit data (BKBIN(P)) ......... 6 - 101
6.3.16 Single precision to Double precision conversion (ECON(P)) ................................... 6 - 103
6.3.17 Double precision to Single precision conversion (EDCON(P))................................. 6 - 105
6.4 Data Transfer Instructions 6 - 107
6.4.1 16-bit and 32-bit data transfers (MOV(P),DMOV(P))................................................ 6 - 107
6.4.2 Floating-point data transfer (Single precision) (EMOV(P)) ....................................... 6 - 109
6.4.3 Floating-point data transfer (Double precision) (EDMOV(P)) ................................... 6 - 111
6.4.4 Character string transfers ($MOV(P))....................................................................... 6 - 113
6.4.5 16-bit and 32-bit negation transfers (CML(P),DCML(P)) .......................................... 6 - 115
6.4.6 Block 16-bit data transfers (BMOV(P)) ..................................................................... 6 - 118
6.4.7 Identical 16-bit data block transfers (FMOV(P)) ....................................................... 6 - 122

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 6.4.8 Identical 32-bit data block transfers (DFMOV(P))..................................................... 6 - 125
6.4.9 16-bit and 32-bit data exchanges (XCH(P),DXCH(P)) ............................................. 6 - 127
6.4.10 Block 16-bit data exchanges (BXCH(P)) .................................................................. 6 - 129
6.4.11 Upper and lower byte exchanges (SWAP(P)) .......................................................... 6 - 131
6.5 Program Branch Instructions 6 - 132
6.5.1 Pointer branch instructions (CJ,SCJ,JMP) ............................................................... 6 - 132
6.5.2 Jump to END (GOEND)............................................................................................ 6 - 135
6.6 Program Execution Control Instructions 6 - 136
6.6.1 Interrupt disable/enable instructions, interrupt program mask (DI,EI,IMASK) .......... 6 - 136
6.6.2 Recovery from interrupt programs (IRET) ................................................................ 6 - 143
6.7 I/O Refresh Instructions 6 - 145
6.7.1 I/O refresh (RFS(P)) ................................................................................................. 6 - 145
6.8 Other Convenient Instructions 6 - 147
6.8.1 Counter 1-phase input up or down (UDCNT1) ......................................................... 6 - 147
6.8.2 Counter 2-phase input up or down (UDCNT2) ......................................................... 6 - 150
6.8.3 Teaching timer (TTMR) ............................................................................................ 6 - 153
6.8.4 Special function timer (STMR).................................................................................. 6 - 155
6.8.5 Rotary table shortest direction control (ROTC) ........................................................ 6 - 158
6.8.6 Ramp signal (RAMP)................................................................................................ 6 - 161
6.8.7 Pulse density measurement (SPD) .......................................................................... 6 - 164
6.8.8 Fixed cycle pulse output (PLSY) .............................................................................. 6 - 166
6.8.9 Pulse width modulation (PWM) ................................................................................ 6 - 168
6.8.10 Matrix input (MTR).................................................................................................... 6 - 170

7. APPLICATION INSTRUCTIONS 7 - 1 to 7 - 460

7.1 Logical operation instructions 7-2
7.1.1 Logical products with 16-bit and 32-bit data (WAND(P),DAND(P)).............................. 7 - 3
7.1.2 Block logical products (BKAND(P)) .............................................................................. 7 - 9
7.1.3 Logical sums of 16-bit and 32-bit data (WOR(P),DOR(P))......................................... 7 - 11
7.1.4 Block logical sum operations (BKOR(P)).................................................................... 7 - 17
7.1.5 16-bit and 32-bit exclusive OR operations (WXOR(P),DXOR(P)) .............................. 7 - 19
7.1.6 Block exclusive OR operations (BKXOR(P)) .............................................................. 7 - 25
7.1.7 16-bit and 32-bit data exclusive NOR operations (WXNR(P),DXNR(P)).................... 7 - 27
7.1.8 Block exclusive NOR operations (BKXNR(P))............................................................ 7 - 33
7.2 Rotation instruction 7 - 35
7.2.1 Right rotation of 16-bit data (ROR(P),RCR(P)) .......................................................... 7 - 35
7.2.2 Left rotation of 16-bit data (ROL(P),RCL(P)) .............................................................. 7 - 38
7.2.3 Right rotation of 32-bit data (DROR(P),DRCR(P)) ..................................................... 7 - 41
7.2.4 Left rotation of 32-bit data (DROL(P),DRCL(P))......................................................... 7 - 44
7.3 Shift instruction 7 - 46
7.3.1 n-bit shift to right or left of 16-bit data (SFR(P),SFL(P)) ............................................. 7 - 46
7.3.2 1-bit shift to right or left of n-bit data (BSFR(P),BSFL(P)) .......................................... 7 - 49
7.3.3 n-bit shift to right or left of n-bit data (SFTBR(P),SFTBL(P)) ...................................... 7 - 51
7.3.4 1-word shift to right or left of n-word data (DSFR(P),DSFL(P)) .................................. 7 - 54
7.3.5 n-bit shift to right or left of n-word data (SFTWR(P),SFTWL(P)) ................................ 7 - 56
7.4 Bit processing instructions 7 - 59

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 7.4.1 Bit set and reset for word devices (BSET(P),BRST(P)) ............................................. 7 - 59
7.4.2 Bit tests (TEST(P),DTEST(P)).................................................................................... 7 - 61
7.4.3 Batch reset of bit devices (BKRST(P)) ....................................................................... 7 - 64
7.5 Data processing instructions 7 - 66
7.5.1 16-bit and 32-bit data searches (SER(P),DSER(P))................................................... 7 - 66
7.5.2 16-bit and 32-bit data checks (SUM(P),DSUM(P))..................................................... 7 - 69
7.5.3 Decoding from 8 to 256 bits (DECO(P)) ..................................................................... 7 - 71
7.5.4 Encoding from 256 to 8 bits (ENCO(P)) ..................................................................... 7 - 73
7.5.5 7-segment decode (SEG(P)) ...................................................................................... 7 - 75
7.5.6 4-bit dissociation of 16-bit data (DIS(P))..................................................................... 7 - 77
7.5.7 4-bit linking of 16-bit data (UNI(P)) ............................................................................. 7 - 79
7.5.8 Dissociation or linking of random data (NDIS(P),NUNI(P)) ........................................ 7 - 81
7.5.9 Data dissociation and linking in byte units (WTOB(P),BTOW(P)) .............................. 7 - 85
7.5.10 Maximum value search for 16- and 32-bit data (MAX(P),DMAX(P)) .......................... 7 - 89
7.5.11 Minimum value search for 16- and 32-bit data (MIN(P),DMIN(P)) ............................. 7 - 92
7.5.12 BIN 16 and 32 bits data sort operations (SORT,DSORT) .......................................... 7 - 95
7.5.13 Calculation of totals for 16-bit data (WSUM(P)) ......................................................... 7 - 99
7.5.14 Calculation of totals for 32-bit data (DWSUM(P))..................................................... 7 - 101
7.5.15 Calculation of averages for 16-bit or 32-bit data (MEAN(P),DMEAN(P)) ................. 7 - 103
7.6 Structure creation instructions 7 - 105
7.6.1 FOR to NEXT instruction loop (FOR,NEXT)............................................................. 7 - 105
7.6.2 Forced end of FOR to NEXT instruction loop (BREAK(P))....................................... 7 - 108
7.6.3 Subroutine program calls (CALL(P)) ........................................................................ 7 - 110
7.6.4 Return from subroutine programs (RET) .................................................................. 7 - 115
7.6.5 Subroutine program output OFF calls (FCALL(P)) ................................................... 7 - 116
7.6.6 Subroutine calls between program files (ECALL(P)) ................................................ 7 - 120
7.6.7 Subroutine output OFF calls between program files (EFCALL(P))........................... 7 - 125
7.6.8 Subroutine program call (XCALL)............................................................................. 7 - 129
7.6.9 Refresh instruction (COM)........................................................................................ 7 - 134
7.6.10 Select Refresh Instruction (COM)............................................................................. 7 - 137
7.6.11 Select Refresh Instruction (CCOM(P)) ..................................................................... 7 - 142
7.6.12 Index modification of entire ladder (IX,IXEND)......................................................... 7 - 143
7.6.13 Designation of modification values in index modification of entire ladders
(IXDEV,IXSET) ......................................................................................................... 7 - 147
7.7 Data Table Operation Instructions 7 - 150
7.7.1 Writing data to the data table (FIFW(P))................................................................... 7 - 150
7.7.2 Reading oldest data from tables (FIFR(P))............................................................... 7 - 152
7.7.3 Reading newest data from data tables (FPOP(P)) ................................................... 7 - 154
7.7.4 Deleting and inserting data from and in data tables (FDEL(P),FINS(P)).................. 7 - 156
7.8 Buffer memory access instruction 7 - 159
7.8.1 Reading 1-/2-word data from the intelligent function module
(FROM(P),DFRO(P))................................................................................................ 7 - 159
7.8.2 Writing 1-/2-word data to intelligent function module (TO(P),DTO(P)) ..................... 7 - 162
7.9 Display instructions 7 - 165
7.9.1 Print ASCII code instruction (PR) ............................................................................. 7 - 165
7.9.2 Print comment instruction (PRC) .............................................................................. 7 - 168
7.9.3 Error display and annunciator reset instruction (LEDR) ........................................... 7 - 171

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 7.10 Debugging and failure diagnosis instructions 7 - 174
7.10.1 Special format failure checks (CHKST,CHK) ........................................................... 7 - 174
7.10.2 Changing check format of CHK instruction (CHKCIR,CHKEND) ............................. 7 - 178
7.11 Character string processing instructions 7 - 182
7.11.1 Conversion from BIN 16-bit or 32-bit to decimal ASCII (BINDA(P),DBINDA(P))...... 7 - 182
7.11.2 Conversion from BIN 16-bit or 32-bit data to hexadecimal ASCII
(BINHA(P),DBINHA(P)) ............................................................................................ 7 - 185
7.11.3 Conversion from BCD 4-digit and 8-digit to decimal ASCII data
(BCDDA(P),DBCDDA(P))......................................................................................... 7 - 188
7.11.4 Conversion from decimal ASCII to BIN 16-bit and 32-bit data
(DABIN(P),DDABIN(P)) ............................................................................................ 7 - 191
7.11.5 Conversion from hexadecimal ASCII to BIN 16-bit and 32-bit data
(HABIN(P),DHABIN(P)) ............................................................................................ 7 - 194
7.11.6 Conversion from decimal ASCII to BCD 4-digit or 8-digit data
(DABCD(P),DDABCD(P))......................................................................................... 7 - 197
7.11.7 Reading device comment data (COMRD(P)) ........................................................... 7 - 200
7.11.8 Character string length detection (LEN(P)) .............................................................. 7 - 203
7.11.9 Conversion from BIN 16-bit or 32-bit to character string (STR(P),DSTR(P)) ........... 7 - 205
7.11.10 Conversion from character string to BIN 16-bit or 32-bit data (VAL(P),DVAL(P)) .... 7 - 211
7.11.11 Conversion from floating decimal point to character string data (ESTR(P))............. 7 - 216
7.11.12 Conversion from character string to floating decimal point data (EVAL(P)) ............. 7 - 223
7.11.13 Conversion from hexadecimal BIN to ASCII (ASC(P)) ............................................. 7 - 227
7.11.14 Conversion from ASCII to hexadecimal BIN (HEX(P)) ............................................. 7 - 229
7.11.15 Extracting character string data from the right or left (RIGHT(P),LEFT(P)).............. 7 - 231
7.11.16 Random selection from and replacement in character strings
(MIDR(P),MIDW(P)) ................................................................................................. 7 - 234
7.11.17 Character string search (INSTR(P)) ......................................................................... 7 - 238
7.11.18 Insertion of character string (STRINS(P))................................................................. 7 - 240
7.11.19 Deletion of character string (STRDEL(P)) ................................................................ 7 - 242
7.11.20 Floating decimal point to BCD (EMOD(P)) ............................................................... 7 - 244
7.11.21 From BCD format data to floating decimal point (EREXP(P)) .................................. 7 - 247
7.12 Special function instructions 7 - 249
7.12.1 SIN operation on floating-point data (Single precision) (SIN(P)) .............................. 7 - 249
7.12.2 SIN operation on floating-point data (Double precision) (SIND(P)) .......................... 7 - 251
7.12.3 COS operation on floating-point data (Single precision) (COS(P)) .......................... 7 - 253
7.12.4 COS operation on floating-point data (Double precision) (COSD(P)) ...................... 7 - 255
7.12.5 TAN operation on floating-point data (Single precision) (TAN(P))............................ 7 - 257
7.12.6 TAN operation on floating-point data (Double precision) (TAND(P))........................ 7 - 259
7.12.7 SIN-1 operation on floating point data (Single precision) (ASIN(P)) ......................... 7 - 261
7.12.8 SIN-1 operation on floating-point data (Double precision) (ASIND(P)) ..................... 7 - 264
7.12.9 COS -1 operation on floating-point data (Single precision) (ACOS(P)) .................... 7 - 266
7.12.10 COS -1 operation on floating-point data (Double precision) (ACOSD(P)) ................ 7 - 268
7.12.11 TAN -1 operation on floating-point data (Single precision) (ATAN(P))...................... 7 - 270
7.12.12 TAN -1 operation on floating-point data (Double precision) (ATAND(P)).................. 7 - 272
7.12.13 Conversion from floating-point angle to radian (Single precision) (RAD(P)) ............ 7 - 274
7.12.14 Conversion from floating-point angle to radian (Double precision) (RADD(P)) ........ 7 - 276
7.12.15 Conversion from floating-point radian to angle (Single precision) (DEG(P)) ............ 7 - 278
7.12.16 Conversion from floating-point radian to angle (Double precision) (DEGD(P)) ........ 7 - 280

A-12
 7.12.17 Exponentiation operation on floating-point data (Single precision) (POW(P)).......... 7 - 282
7.12.18 Exponentiation operation on floating-point data (Single precision) (POWD(P)) ....... 7 - 284
7.12.19 Square root operation for floating-point data (Single precision) (SQR(P)) ............... 7 - 286
7.12.20 Square root operation for floating-point data (Double precision) (SQRD(P)) ........... 7 - 288
7.12.21 Exponent operation on floating-point data (Single precision) (EXP(P)).................... 7 - 290
7.12.22 Exponent operation on floating-point data (Double precision) (EXPD(P))................ 7 - 293
7.12.23 Natural logarithm operation on floating-point data (Single precision) (LOG(P)) ....... 7 - 295
7.12.24 Natural logarithm operation on floating-point data (Double precision)
(LOGD(P)) ................................................................................................................ 7 - 297
7.12.25 Common logarithm operation on floating-point data (Single precision)
(LOG10(P))............................................................................................................... 7 - 299
7.12.26 Common logarithm operation on floating-point data (Double precision)
(LOG10D(P)) ............................................................................................................ 7 - 301
7.12.27 Random number generation and series updates (RND(P),SRND(P)) ..................... 7 - 303
7.12.28 BCD 4-digit and 8-digit square roots (BSQR(P),BDSQR(P)) ................................... 7 - 305
7.12.29 BCD type SIN operation (BSIN(P))........................................................................... 7 - 308
7.12.30 BCD type COS operations (BCOS(P)) ..................................................................... 7 - 310
7.12.31 BCD type TAN operation (BTAN(P)) ........................................................................ 7 - 312
7.12.32 BCD type SIN -1 operations (BASIN(P)) ................................................................... 7 - 314
7.12.33 BCD type COS -1 operation (BACOS(P)) ................................................................. 7 - 316
7.12.34 BCD type TAN -1 operations (BATAN(P)) ................................................................ 7 - 318
7.13 Data Control Instructions 7 - 320
7.13.1 Upper and lower limit controls for BIN 16-bit and BIN 32-bit data
(LIMIT(P),DLIMIT(P))................................................................................................ 7 - 320
7.13.2 BIN 16-bit and 32-bit dead band controls (BAND(P),DBAND(P)) ............................ 7 - 323
7.13.3 Zone control for BIN 16-bit and BIN 32-bit data (ZONE(P),DZONE(P))................... 7 - 326
7.13.4 Scaling (Point-by-point coordinate data) (SCL(P),DSCL(P)).................................... 7 - 329
7.13.5 Scaling (Point-by-point coordinate data) (SCL2(P),DSCL2(P))................................ 7 - 333
7.14 File register switching instructions 7 - 336
7.14.1 Switching file register numbers (RSET(P))............................................................... 7 - 336
7.14.2 Setting files for file register use (QDRSET(P)) ......................................................... 7 - 338
7.14.3 File setting for comments (QCDSET(P)) .................................................................. 7 - 341
7.15 Clock instructions 7 - 343
7.15.1 Reading clock data (DATERD(P)) ............................................................................ 7 - 343
7.15.2 Writing clock data (DATEWR(P)) ............................................................................. 7 - 345
7.15.3 Clock data addition operation (DATE+(P)) ............................................................... 7 - 347
7.15.4 Clock data subtraction operation (DATE-(P)) ........................................................... 7 - 349
7.15.5 Time data conversion (from Hour/Minute/Second to Second) (SECOND(P)) .......... 7 - 351
7.15.6 Time data conversion (from Second to Hour/Minute/Second) (HOUR(P))............... 7 - 353
7.15.7 Date comparison (DT=,DT<>,DT>,DT<=,DT<,DT>=) .............................................. 7 - 355
7.15.8 Clock comparison (TM=,TM<>,TM>,TM<=,TM<,TM>=).......................................... 7 - 360
7.16 Expansion Clock Instructions 7 - 365
7.16.1 Reading expansion clock data (S(P).DATERD) ....................................................... 7 - 365
7.16.2 Expansion clock data addition operation (S(P).DATE+)........................................... 7 - 368
7.16.3 Expansion clock data subtraction operation (S(P).DATE-)....................................... 7 - 371
7.17 Program control instructions 7 - 374
7.17.1 Program standby instruction (PSTOP(P)) ................................................................ 7 - 376

A-13
 7.17.2 Program output OFF standby instruction (POFF(P))................................................ 7 - 377
7.17.3 Program scan execution registration instruction (PSCAN(P)) .................................. 7 - 379
7.17.4 Program low speed execution registration instruction (PLOW(P)) ........................... 7 - 381
7.17.5 Program execution status check instruction (PCHK)................................................ 7 - 383
7.18 Other instructions 7 - 385
7.18.1 Resetting watchdog timer (WDT(P))......................................................................... 7 - 385
7.18.2 Timing pulse generation (DUTY) .............................................................................. 7 - 387
7.18.3 Time check instruction (TIMCHK)............................................................................. 7 - 389
7.18.4 Direct 1-byte read from file register (ZRRDB(P))...................................................... 7 - 390
7.18.5 File register direct 1-byte write (ZRWRB(P)) ............................................................ 7 - 392
7.18.6 Indirect address read operations (ADRSET(P)) ....................................................... 7 - 394
7.18.7 Numerical key input from keyboard (KEY) ............................................................... 7 - 395
7.18.8 Batch save or recovery of index register (ZPUSH(P),ZPOP(P)) .............................. 7 - 399
7.18.9 Reading Module Information (UNIRD(P))................................................................. 7 - 401
7.18.10 Reading module model name (TYPERD(P))............................................................ 7 - 408
7.18.11 Trace Set/Reset (TRACE,TRACER) ........................................................................ 7 - 413
7.18.12 Writing Data to Designated File (SP.FWRITE)......................................................... 7 - 415
7.18.13 Reading Data from Designated File (SP.FREAD) .................................................... 7 - 427
7.18.14 Writing Data to Standard ROM (SP.DEVST)............................................................ 7 - 439
7.18.15 Read Data from Standard ROM (S(P).DEVLD)........................................................ 7 - 441
7.18.16 Load Program from Memory Card (PLOADP).......................................................... 7 - 443
7.18.17 Unload Program from Program Memory (PUNLOADP) ........................................... 7 - 446
7.18.18 Load + Unload (PSWAPP) ....................................................................................... 7 - 448
7.18.19 High-speed Block Transfer of File Register (RBMOV(P)) ........................................ 7 - 451
7.18.20 User Message (UMSG) ............................................................................................ 7 - 456

Common Instructions 2/2

8. INSTRUCTIONS FOR DATA LINK 8 - 1 to 8 - 10

8.1 Network refresh instructions 8-2
8.1.1 Refresh instruction for the designated module (S(P).ZCOM)....................................... 8 - 2
8.2 Reading/Writing Routing Information 8-6
8.2.1 Reading routing information (S(P).RTREAD) ............................................................... 8 - 6
8.2.2 Registering routing information (S(P).RTWRITE)......................................................... 8 - 8

9. Multiple CPU dedicated instruction 9 - 1 to 9 - 18

9.1 Writing to the CPU Shared Memory of Host CPU 9-2
9.1.1 Write to Host CPU Shared Memory (S(P).TO) ............................................................. 9 - 4
9.1.2 Writing to host station CPU shared memory (TO(P), DTO(P))..................................... 9 - 7
9.2 Reading from the CPU Shared Memory of another CPU 9 - 11
9.2.1 Reading from Other CPU Shared Memory (FROM(P), DFRO(P)) ............................. 9 - 12

10. QCPU INSTRUCTIONS 10 - 1 to 10 - 20

10.1 Overview 10 - 2
10.2 Writing Devices to Another CPU (D(P).DDWR) 10 - 13
10.3 Reading Devices from Another CPU (D(P).DDRD) 10 - 17

A-14
11. QCPU INSTRUCTIONS 11 - 1 to 11 - 4
11.1 System Switching Instruction (SP.CONTSW) 11 - 2

12. ERROR CODES 12 - 1 to 12 - 88

12.1 Error Code List 12 - 2
12.1.1 Error codes ................................................................................................................. 12 - 3
12.1.2 Reading an error code................................................................................................ 12 - 3
12.1.3 Error code list (1000 to 1999) ..................................................................................... 12 - 4
12.1.4 Error code list (2000 to 2999) ................................................................................... 12 - 21
12.1.5 Error code list (3000 to 3999) ................................................................................... 12 - 42
12.1.6 Error code list (4000 to 4999) ................................................................................... 12 - 58
12.1.7 Error code list (5000 to 5999) ................................................................................... 12 - 72
12.1.8 Error code list (6000 to 6999) ................................................................................... 12 - 74
12.1.9 Error code list (7000 to 10000) ................................................................................. 12 - 82
12.2 Canceling of Errors 12 - 87

APPENDICES App - 1 to App - 274

Appendix 1 OPERATION PROCESSING TIME App - 2
Appendix 1.1 Definition .....................................................................................................App - 2
Appendix 1.2 Operation Processing Time of Basic Model QCPU.....................................App - 3
Appendix 1.3 Operation Processing Time of High Performance Model QCPU/Process CPU/
Redundant CPU ........................................................................................App - 21
Appendix 1.4 Operation Processing Time of Universal Model QCPU.............................App - 50
Appendix 1.4.1 Subset instruction processing time............................................................App - 50
Appendix 1.4.2 Processing time of instructions other than subset instruction ...................App - 66
Appendix 1.5 Operation Processing Time of LCPU .....................................................App - 114
Appendix 1.5.1 Subset instruction processing time..........................................................App - 114
Appendix 1.5.2 Processing time of instructions other than subset instruction .................App - 121
Appendix 2 CPU PERFORMANCE COMPARISON App - 141
Appendix 2.1 Comparison of Q, LCPU with AnNCPU, AnACPU, and AnUCPU...........App - 141
Appendix 2.1.1 Usable devices ........................................................................................App - 141
Appendix 2.1.2 I/O control mode......................................................................................App - 142
Appendix 2.1.3 Data that can be used by instructions .....................................................App - 143
Appendix 2.1.4 Timer comparison....................................................................................App - 144
Appendix 2.1.5 Comparison of counters ..........................................................................App - 145
Appendix 2.1.6 Comparison of display instructions..........................................................App - 145
Appendix 2.1.7 Instructions whose designation format has been changed (Except dedicated
instructions for AnACPU and AnUCPU)..................................................App - 146
Appendix 2.1.8 AnACPU and AnUCPU dedicated instructions........................................App - 147
Appendix 3 SPECIAL RELAY LIST App - 148
Appendix 4 SPECIAL REGISTER LIST App - 195
Appendix 5 APPLICATION PROGRAM EXAMPLES App - 274
n
Appendix 5.1 Concept of Programs which Perform Operations of X , X ....................App - 274
n

A-15
 INDEX Index - 1 to Index - 10
INDEX Index- 2
INSTRUCTION INDEX Index- 7

A-16
 MANUALS

To understand the main specifications, functions, and usage of the CPU module, refer to the basic manuals.
Read other manuals as well when using a different type of CPU module and its functions.
Order each manual as needed, referring to the following list.

The numbers in the "CPU module" and the respective modules are as follows.
Nunber CPU module
1) Basic model QCPU
2) High Perfomance model QCPU
3) Process CPU
4) Redundant CPU
5) Universal model QCPU
6) LCPU

:Basic manual, :Other CPU module manuals

Manual name CPU module
Description
< Manual number (model code) > 1) 2) 3) 4) 5) 6)
■User’s manual
Specifications of the hardware (CPU modules,
QCPU User's Manual
power supply modules, base units, extension cables,
(Hardware design, Maintenance and Inspection)
and memory cards), system maintenance and
< SH-080483ENG (13JR73) >
inspection, troubleshooting, and error codes
QnUCPU User’s Manual
(Function Explanation, Program Fundamentals) Functions, methods, and devices for programming
< SH-080807ENG (13JZ27) >
Qn(H)/QnPH/QnPRHCPU User's Manual
(Function Explanation, Program Fundamentals) Functions, methods, and devices for programming
< SH-080808ENG (13JZ28) >
QnUCPU User's Manual
Functions for the communication via built-in Ethernet
(Communication via Built-in Ethernet Port)
port of the CPU module
< SH-080811ENG (13JZ29) >
Specifications of the hardware (CPU modules,
MELSEC-L CPU Module User's Manual
power supply modules, and memory cards), system
(Hardware design, Maintenance and Inspection)
maintenance and inspection, troubleshooting, and
< SH-080890ENG (13JRZ36) >
error codes
MELSEC-L CPU Module User's Manual
(Function Explanation, Program Fundamentals) Functions, methods, and devices for programming
< SH-080889ENG (13JZ35) >
MELSEC-L CPU Module User's Manual
(Built-In I/O Function) Built-in I/O Functionality of the CPU
< SH-080892ENG (13JZ38) >
MELSEC-L CPU Module User's Manual
Functions for the communication via built-in Ethernet
(Communication via Built-in Ethernet Port)
port of the CPU module
< SH-080891ENG (13JZ37) >
MELSEC-L CPU Module User's Manual
(Data Logging Function) Data Logging Functionality of the CPU Module
< SH-080893ENG (13JZ39) >

A-17
 :Basic manual, :Other CPU module manuals
Manual name CPU module
Description
< Manual number (model code) > 1) 2) 3) 4) 5) 6)
■Programming Manual
MELSEC-Q /L Programming Manual (Common How to use sequence instructions, basic instructions,
Instructions) and application instructions
< SH-080809ENG (13JW10) >
System configuration, performance specifications,
MELSEC-Q /L/QnA Programming Manual (SFC)
functions, programming, debugging, and error codes
< SH-080041 (13JF60) >
for SFC (MELSAP3) programs
MELSEC-Q /L Programming Manual (MELSAP-L) Programming methods, specifications, and functions
< SH-080072 (13JC03) > for SFC (MELSAP-L) programs
MELSEC-Q /L Programming Manual
(Structured Text) Programming methods using structured languages
< SH-080366E (13JF68) >
MELSEC-Q /L/QnA Programming Manual
(PID Control Instructions) Dedicated instructions for PID control
< SH-080040 (13JF59) >
QnPH/QnPRHCPU Programming Manual
Describes the dedicated instructions for performing
(Process Control Instructions)
process control.
< SH-080316E (13JF59) >

Related Manuals

Manual name
Description
< Manual number (model code) >
CC-Link IE Controller Network Reference Manual Specifications, procedures and settings before system operation, parameter
< SH-080668ENG (13JV16) > setting, programming, and troubleshooting of the CC-Link IE controller network module
Q Corresponding MELSECNET/H Network System Reference Explains the specifications for a MELSECNET/H network system for PLC to PLC
Manual (PLC to PLC network) network. It explains the procedures and settings up to operation, setting the
< SH-080049 (13JF92) > parameters, programming and troubleshooting.
Q Corresponding MELSECNET/H Network System Refer- Explains the specifications for a MELSECNET/H network system for remote I/O
ence Manual (Remote I/O network) network. It explains the procedures and settings up to operation, setting the
< SH-080124 (13JF96) > parameters, programming and troubleshooting.
Type MELSECNET, MELSECNET/B Data Link System
Describes the general concept, specifications, and part names and settings for
Reference Manual
MELSECNET (II) and MELSECNET/B.
< IB-66530 (13JF70) >
Describes various functions of the Ethernet module: e-mail function, PLC CPU
Q Corresponding Ethernet Interface Module
status monitoring, communication via MELSECNET/H or MELSECNET/10
User's Manual (Application)
network system, communication using data link instructions, file transfer (using
< SH-080010 (13JF70) >
FTP) and other functions.

A-18
8
7
INSTRUCTIONS
FOR DATA LINK 7

Reference
7
Category Processing Details
section
Network refresh instructions Refreshes the specified network module. Section 8.1
Routing information Reading the data specified by routing parameters. Section 8.2.1 7
read/write instructions Writing routing data to the area specified by routing parameters. Section 8.2.2

Remark
7
In this chapter, instruction names are abbreviated as follows if not specified
particularly. 8
• S(P).ZCOM ZCOM • S(P).RTWRITE RTWRITE
• S(P).RTREAD RTREAD

8-1
 ZCOM

8.1 Network refresh instructions

8.1.1 Refresh instruction for the designated module

(S(P).ZCOM)
ZCOM

Basic High
performance Process Redundant Universal LCPU

Command
S.ZCOM S.ZCOM Jn

Command
SP.ZCOM SP.ZCOM Jn

Command
S.ZCOM S.ZCOM Un

Command
SP.ZCOM SP.ZCOM Un

Jn : Network No. of host station (BIN 16 bits) (QCPU only)

Un : Head I/O number of host station network module (BIN 16 bits)

Setting Internal Devices J \

R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
–– ––

The ZCOM instruction is used to perform refresh at any timing during execution of a
sequence program.
The targets of refresh performed by the ZCOM instruction are indicated below.
• Refresh of CC-Link IE controller network (when refresh parameters are set) (QCPU only)
• Refresh of MELSECNET/H (when refresh parameters are set) (QCPU only)
• Auto refresh of CC-Link (when refresh device is set)
• Auto refresh of intelligent function module (when auto refresh is set)

Function
(1) When the ZCOM instruction is executed, the CPU module temporarily suspends processing
of the sequence program and conducts refresh processing of the network modules
designated by Jn/Un. (Specification cannot be made via Jn for LCPU.)
Execution of ZCOM Execution of ZCOM Execution of ZCOM
instruction instruction instruction
0 END END

Refresh Refresh Refresh Refresh Refresh

processing processing processing processing processing

8-2
 ZCOM

(2) The ZCOM instruction does not perform the following processing.
(a) Communication processing between CPU module and programming tool 1
(b) Monitor processing of other station

(c) Read processing of buffer memory of other intelligent function module by serial 2
communication module.

(d) Low-speed cyclic data transmission of MELSECNET/H

3
(3) PLC to PLC network*1 (QCPU only)
(a) When the scan time for the sequence program of host station is longer than the scan
time for the other station, the ZCOM instruction is used to ensure the data reception 4
from the other station.
(1) Example of data communications when the ZCOM instruction is not used
6
Control station 0 END 0 END 0 END
program

Link scan
6

Normal station
program
0 END 0 END 0
7
(2) Example of data communications when the ZCOM instruction is used

Control station 0 END 0 END 0 END 8

program

Link scan

8.1.1 Refresh instruction for the designated module (S(P).ZCOM)

8.1 Network refresh instructions
Normal station 0 END 0 END 0
program
ZCOM ZCOM ZCOM

For details of the transmission delay time on the PLC to PLC network*1, refer to the
manual below:
• CC-Link IE Controller Network Reference Manual
• Q Corresponding MELSECNET/H Network System Reference Manual
(PLC to PLC network)

(b) When the link scan time is longer than the sequence program scan time, data
communications will not be faster even if the ZCOM instruction is used.
END
Sequence program 0 ZCOM END 0 ZCOM END 0 ZCOM 0 ZCOM END

Link scan

*1 : Controller network in CC-Link IE controller network.

8-3
 ZCOM

(4) Remote I/O network (QCPU only)

The link refresh of the remote master station is performed by the "END processing" of the
CPU module.
Since link scan is performed at completion of link refresh, link scan 'synchronizes' with the
program of the CPU module.
When the ZCOM instruction is used at the remote master station, link refresh is performed at
the point of ZCOM instruction execution, and link scan is performed at completion of link
refresh.
Hence, use of the ZCOM instruction at the remote master station speeds up send/receive
processing to/from the remote I/O station.
(1) When the ZCOM instruction is not used

Remote master 0 END 0 END 0 END 0

station program
Link refresh

Link scan
Link refresh
Remote I/O station
network refresh
I/O refresh
I/O module
Auto refresh
Intelligent
function module

(2) When the ZCOM instruction is used

ZCOM ZCOM ZCOM

Remote master 0 END 0 END END 0

0
station program
Link refresh

Link scan
Link refresh

Remote I/O station

network refresh
I/O refresh
I/O module
Auto refresh
Intelligent
function module

For details of the transmission delay time on the remote I/O network, refer to the manual
below:
• Q Corresponding MELSECNET/H Network System Reference Manual
(Remote I/O network)
(5) The ZCOM instruction can be used as many times as desired in sequence programs.
However, note that each execution of a refresh operation will lengthen the sequence
program scan time by the amount of time required for the refresh operation.

8-4
 ZCOM

(6) Designating "Un" in the argument enables the target designation of the intelligent function as
well as the network modules.
In this case, the auto refresh is performed for the buffer memory of the intelligent function
modules. (It replaces the FROM/TO instructions.)
1
(7) Only with the Universal model QCPU and LCPU, interruption of processing is enabled
during the execution of the ZCOM instruction. However, when refresh data are used in an
interrupted program, the data can split.
2

1. The ZCOM instruction cannot be used in a fixed cycle execution type program
3
or interrupt program.
2. The Redundant CPU has restrictions on use of the ZCOM instruction.
Refer to the manual below for details. 4
• QnPRHCPU User's Manual (Redundant System)

6
Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
6
an error code is stored into SD0.
• When the specified network number is not connected to the host station
(Error code: 4102)
7
• When the module specified with the head I/O number is not a network module or link
module (Basic model QCPU, High Performance model QCPU, Process CPU, and
Redundant CPU) (Error code: 2111)
8
• When the module specified with the head I/O number is not a network module or link
module (Universal model QCPU, LCPU) (Error code: 4102)

8.1.1 Refresh instruction for the designated module (S(P).ZCOM)

8.1 Network refresh instructions
To conduct only communication with peripheral device, use the COM instruction
(refer to Section 7.6.9, 9.1).

Program Example
(1) The following program conducts a link refresh for the network module of network No. 6 while
X0 is ON.
[Ladder Mode] [List Mode]
Step Instruction Device

(2) The following program conducts a link refresh for the network module mounted to the
position whose head I/O number is a X/Y30 to X/Y4F while X0 is ON.
[Ladder Mode] [List Mode]
Step Instruction Device

8-5
 RTREAD

8.2 Reading/Writing Routing Information

8.2.1 Reading routing information (S(P).RTREAD)

RTREAD

High
Basic performance Process Redundant Universal LCPU

Command
S.RTREAD S.RTREAD n D

Command
SP.RTREAD n D
SP.RTREAD

n : Transfer destination network No. (1 to 239) (BIN 16 bits)

D : Head number of the devices that stores the read data (Device name)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

n –– ––

D –– –– –– ––

Function
(1) Reads data from transfer destination network number specified by n, using routing
information set by the routing parameters, and stores it into the area starting from D .
(2) If no data for the transfer destination network number specified by n is set at the routing
parameters, stores 0 into the area starting from D .
(3) The contents of the data stored in the area starting from D is as indicated below.
(Individual data ranges)
D +0 Relay network number (1 to 239)
+1 Relay station number (1 to 120)
+2 Dummy

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• When data specified by n is other than 1 to 239. (Error code: 4100)
• The device specified by D exceeds the range of the corresponding device.
(For the Universal model QCPU only.) (Error code: 4101)

8-6
 RTREAD

Program Example
1
(1) The following program reads the routing information for the network number specified by D0
when X0 is turned ON.
[Ladder Mode] [List Mode] 2
Step Instruction Device

4
[Operation] [Content of routing parameter setting]
D0 1 Transfer Relay network Relay station
destination
network number number number 6
D1 10 1 10 3
D2 3 2 10 2

6
D3 Dummy 3 10 1

8.2.1 Reading routing information (S(P).RTREAD)

8.2 Reading/Writing Routing Information

8-7
 RTWRITE

8.2.2 Registering routing information (S(P).RTWRITE)

RTWRITE

High
Basic performance Process Redundant Universal LCPU

Command
S.RTWRITE S.RTWRITE n S

Command
SP.RTWRITE n S
SP.RTWRITE

n : Transfer destination network No. (1 to 239) (BIN 16 bits)

S : Head number of the devices where the data to be written is stored (Device name)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

n –– ––

S –– –– –– ––

Function
(1) Registers routing data of S or later in the area for the transfer destination network number
specified by n in the routing parameters.
(2) The following shows the contents of data to be set at S or later.
(Individual data ranges)
S +0 Relay network number (0 to 239)
+1 Relay station number (0 to 120)
+2 Dummy

(3) If data for the transfer destination network number specified by n is set in the routing
parameters, it is used to update the data in the area starting from S .
(4) If all data in S or later ( S +0 to S +2) is 0, the data for the transfer destination network
number specified by n is deleted from the routing parameters.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• When data specified by n is other than 1 to 239. (Error code: 4100)
• When the data of S or later exceeds each setting ranges. (Error code: 4100)
• When the total number of routing information registered in the routing parameter of the
network parameters and routing information registered with the RTWRITE instruction
exceeds 64. (Error code: 4100)
• The device specified by S exceeds the range of the corresponding device.
(For the Universal model QCPU only.) (Error code: 4101)

8-8
 RTWRITE

Program Example
1
(1) The following program writes the routing information specified by D1 to D3 to the network
module of the network number specified by D0 when X0 is turned ON.
[Ladder Mode] [List Mode] 2
Step Instruction Device

4
[Operation] [Content of routing parameter setting]
D0 1 Transfer
destination
Relay network Relay station
network number number number
6
D1 20 1 20 1
D2 1 2 10 2
D3 Dummy 3 10 1 6

8.2.2 Registering routing information (S(P).RTWRITE)

8.2 Reading/Writing Routing Information

8-9
MEMO

8-10
 MULTIPLE

9
9
CPU DEDICATED
INSTRUCTION 7

7
Reference
Category Processing Details
section
Writing to the CPU shared Writes device data of the host CPU to the CPU shared
memory of host CPU memory of the host CPU module.
Section 9.1 7
Reading from the CPU shared Reads device data from the CPU shared memory of another
Section 9.2
memory of another CPU CPU module to the host CPU.

9-1
 9.1 Writing to the CPU Shared Memory of Host CPU

The S.TO or TO instruction is used to write to the CPU shared memory of the host station in the
multiple CPU system.

The following table indicates the usability of the S.TO and TO instructions.

CPU Module Type Name S.TO Instruction TO Instruction

Q00JCPU Unusable Unusable
Basic model QCPU
Q00CPU, Q01CPU Usable Usable
Q02CPU, Q02HCPU,
High Performance model QCPU Q06HCPU, Q12HCPU, Usable Unusable
Q25HCPU
Q02PHCPU, Q06PHCPU,
Process CPU Usable Unusable
Q12PHCPU, Q25PHCPU
Redundant CPU Q12PRHCPU, Q25PRHCPU Unusable Unusable
Q00UJCPU Unusable Unusable
Q00UCPU, Q01UCPU,
Q02UCPU, Q03UDCPU,
Q04UDHCPU, Q06UDHCPU,
Q10UDHCPU, Q13UDHCPU,
Q20UDHCPU, Q26UDHCPU,
Universal model QCPU Q03UDECPU,
Usable Usable
Q04UDEHCPU,
Q06UDEHCPU,
Q10UDEHCPU,
Q13UDEHCPU,
Q20UDEHCPU,
Q26UDEHCPU
LCPU L02CPU, L26CPU-BT Unusable Unusable

(1) Operation of S.TO instruction

The S.TO instruction can write data to the CPU shared memory of the host CPU module.
The following figure shows the processing performed when the S.TO instruction is executed
in CPU No. 1.

Intelligent
CPU No. 1 CPU No. 2 function module

Device Data CPU Device CPU Buffer

memory write shared memory shared memory
memory memory

[ SP.TO H3E0 n2 n3 n4 D ]

Designation of CPU shared memory in CPU No. 1

9-2
(2) Operation of the TO instruction
The TO instruction can write device memory data to the following memories.
9
• CPU shared memory of host CPU module
• Buffer memory of intelligent function module
7
The following figure shows the processing performed when the TO instruction is executed in
CPU No. 1.
7
Intelligent
CPU No. 1 CPU No. 2 function module

Device
memory
Data
write
CPU
shared
Device
memory
CPU
shared
Buffer
memory
7
memory memory

7
Writes data

7
[ TO H3E0 n2 S n3 ]

Designation of CPU shared memory in CPU No. 1

7

[ TO H0 n2 S n3 ]
7
Designation of intelligent function module

9.1 Writing to the CPU Shared Memory of Host CPU

Both of the S.TO and TO instructions can be used for the Basic model QCPU
(Q00CPU or Q01CPU) and Universal model QCPU to write data to the CPU
shared memory. However, use of the TO instruction is recommended, since use of
S.TO instruction reduces the number of steps and processing time.

Remark
Refer to Section 7.8.2 when writing to the buffer memory of the intelligent function
module by the TO instruction.

9-3
 S(P).TO

9.1.1 Write to Host CPU Shared Memory (S(P).TO)

S(P).TO

Ver. Ver.
High
Basic performance Process Redundant Universal LCPU

Basic model QCPU:The first 5 digits of serial No is "04122" or higher.

Hight performance modele QCPU:Function version B or later.

Command
S.TO S.TO n1 n2 n3 n4 D

Command
SP.TO SP.TO n1 n2 n3 n4 D

n1 : Head I/O number of the host CPU (BIN 16 bits)

n2 : CPU shared memory address of the write destination host CPU (BIN 16 bits)
•Basic model QCPU: 0 to 511
•High Performance model QCPU, Process CPU, Universal model QCPU: 0 to 4095
n3 : Head number of the devices where data to be written is stored (BIN 16 bits)
n4 : Number of data blocks to be written (BIN 16 bits)
•Basic model QCPU: 1 to 320
•High Performance model QCPU, Process CPU: 1 to 256
•Universal model QCPU: 1 to 2048
D : Device of the host CPU which is turned ON for one scan by the completion of writing (bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

n1 –– –– ––

n2 –– –– ––

n3 –– –– –– ––

n4 –– –– ––

D –– –– ––

Function
(1) Writes device data of words n3 to n4 to the CPU shared memory address specified by n2 of
the host CPU module or later address.
When writing is completed, the completion bit specified by D turns ON.

Host CPU

CPU shared memory

Device memory of host CPU (n1)
n3 n2

n4
Writes the
data of n4
words

9-4
 S(P).TO

(a) CPU shared memory address of the Basic model QCPU

CPU shared memory address
9
0(0H) Host CPU operation information area
96(60H) Write designation
System area prohibited area
192(C0H) *1
7
Host CPU refresh area

Write designation
permitted area
User free area 7
511(1FFH)

(b) CPU shared memory address of the High Performance model QCPU, Process CPU and 7
Universal model QCPU*2
CPU shared memory address

0(0H) Host CPU operation information area

7
512(200H) Write designation
System area prohibited area
2048(800H)
Host CPU refresh area
*1
7
Write designation
permitted area
User free area
7
4095(0FFFH)

*1 : Usable as a user free area when auto refresh setting is not made.
In addition, even when auto refresh setting is made, the auto refresh send range or later is 7
usable as a user free area.
*2 : Data cannot be written to the multiple CPU high speed transmission area of the Universal
model QCPU with the S(P).TO instruction.

(2) When the number of write points is 0, no processing is performed and the completion device

9.1.1 Write to Host CPU Shared Memory (S(P).TO)

9.1 Writing to the CPU Shared Memory of Host CPU
does not turn ON, either.
(3) The S.TO instruction can be executed once to one scan for each CPU.
When execution condition is established at two or more places at the same time, the S.TO
instruction executed later is not processed since handshake is established automatically.
(4) The number of data that can be written varies depending on the target CPU module.
CPU module Number of Write Points
Basic model QCPU 1 to 320
High Performance model QCPU Process CPU 1 to 256
Universal model QCPU 1 to 2048

Writing data to CPU shared memory can be performed using the intelligent
function module device.
For intelligent function module device, refer to the QnUCPU User's Manual
(Function Explanation, Program Fundamentals) or Qn(H)/QnPH/QnPRHCPU
User's Manual (Function Explanation, Program Fundamentals).

9-5
 S(P).TO

Operation Error
In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an
error code is stored into SD0.

(1) When the specified data is outside the following range (Error code: 4101)
• When the number of write points (n4) is outside the specified range of the setting data.
• When the head of the CPU shared memory address (n2) of the write destination host
CPU exceeds the CPU shared memory address range
• When the CPU shared memory address (n2) + the number of write points (n4) of the write
destination host CPU exceeds the CPU shared memory address range
• When the head number of the devices (n3) where the data to be written is stored + the
number of write points (n4) exceeds the device range
(2) When the host CPU operation information area, system area or host CPU refresh area is
specified to the CPU shared memory address (n2) of the write destination
(High Performance model QCPU, Process CPU) (Error code: 4101)
(Basic model QCPU, Universal model QCPU) (Error code: 4111)
(3) When the head I/O number (n1) of the host CPU is other than that of the host CPU
(High Performance model QCPU, Process CPU) (Error code: 2107)
(Basic model QCPU, Universal model QCPU) (Error code: 4112)
(4) No CPU module is installed at the position specified by the head I/O number of the CPU
module. (Error code: 2110)
(5) When the head I/O number (n1) of the host CPU is other than 3E0H/3E1H/3E2H/3E3H
(Error code: 4100)
(6) When the specified instruction is improper (Error code: 4002)
(7) When the specified number of devices is wrong (Error code: 4003)
(8) When the unusable device is specified (Error code: 4004)

Program Example
(1) The following program stores 10 points of data from D0 into address 800H of the CPU
shared memory of CPU No. 1 when X0 is turned ON.
[Ladder Mode] [List Mode]
Step Instruction Device

Remark
The n1 is specified by the first 3 digits of the hexadecimal 4 digits which represent
the head I/O number of the slot mounted to the CPU module.
CPU Slot Slot 0 Slot 1 Slot 2
Head I/O number 3E00 3E10 3E20 3E30
n1 3E0 3E1 3E2 3E3

9-6
 TO(P), DTO(P)

9.1.2 Writing to host station CPU shared memory (TO(P), DTO(P))

9
Ver.
High
Basic Process Redundant Universal LCPU
7
performance

Q00CPU/Q01CPU whose first 5 digits of the serial No. is "04122" or higher

TO(P), DTO(P)

indicates an instruction symbol of TO/DTO.

7
Command
TO,DTO n1 n2 S n3

Command 7
TOP,DTOP P n1 n2 S n3

7
n1 : Head I/O number of the host CPU (BIN 16 bits)
• Basic model QCPU : 3E0H
• Universal model QCPU: 3E0H to 3E3H
n2 : CPU shared memory address of the write destination host CPU (BIN 16 bits) 7
• Basic model QCPU : 192 to 511
• Universal model QCPU: 2048 to 4095, 10000 to 24335*2
S : Data to be written or head number of the devices where the data to be written is stored (BIN 16 bits)
n3 : Number of data blocks to be written (BIN 16 bits)
7
• Basic model QCPU : TO(P): 1 to 320, DTP(P) : 1 to 160
• Universal model QCPU: TO(P): 1 to 14336*2, DTP(P) : 1 to 7168*2

Setting Internal Devices J \ Constants Other

7
R, ZR U \G Zn
Data Bit Word Bit Word K, H U

n1

n2 ––

9.1.2 Writing to host station CPU shared memory (TO(P), DTO(P))

9.1 Writing to the CPU Shared Memory of Host CPU
S –– ––

n3 ––

*2: The setting range varies depending on the auto refresh setting range of the multiple CPU high speed
transmission function.

Function
TO
(1) Writes device data of words S to n3 to the CPU shared memory address specified by n2 of
the host CPU module or later address.
Host CPU
CPU shared memory
Device memory of host CPU (n1)
S n2

n3
Writes the
data of n3
words

9-7
 TO(P), DTO(P)

When a constant is specified to S , writes the same data (value specified to S ) to the area
of n3 words from the specified CPU shared memory.

CPU shared memory

of host CPU (n1)
Constant n2 5
S 5 5
(When "5" is designated 5
Writes the n3 words
for S ) same data to
the area of n3
words
5

(a) CPU shared memory addresses of the Basic model QCPU

CPU shared memory address

0(0H) Host CPU operation information area

96(60H) Write designation
System area prohibited area
192(C0H) *2
Host CPU refresh area

Write designation
permitted area
User free area

511(1FFH)

(b) CPU shared memory address of the Universal model QCPU*3

CPU shared memory address

0(0H) Host CPU operation information area

512(200H) Write designation
System area prohibited area
2048(800H) *2
Host CPU refresh area

User free area

4096(1000H) Write designation

Unusable permitted area
10000(2710H)

Multiple CPU high speed

transmission area

24335(5F0FH)

*2 : Usable as a user free area when auto refresh setting is not made.
In addition, even when auto refresh setting is made, the auto refresh send range or later is
usable as a user free area.
*3 : With Q02UCPU, data can not be written to the multiple CPU high speed transmission area.

(2) No processing is performed when the number of write points is 0.

(3) The number of write data varies depending on the target CPU module.
CPU module Number of Write Points
Basic model QCPU 1 to 320
Universal model QCPU 1 to 14336

9-8
 TO(P), DTO(P)

DTO
(1) Writes device data of words S to (n3×2) to the CPU shared memory address specified by
n2 of the host CPU module or later address. 9
Host CPU
CPU shared memory

S
Device memory
n2
of host CPU (n1) 7

n3 2
Writes the
data of (n3 2)
7
words

When a constant is specified to S , writes the same data (value specified to S ) to the area 7
of (n3×2) words from the specified CPU shared memory.

CPU shared memory

n2
of host CPU (n1) 7
Constant 5
S 5 5
(When "5" is designated 5
(n3 2)
for S )
Writes the same
data to the area words 7
of (n3 2) words
5

7
(2) No processing is performed when the number of write points is 0.
(3) The number of data that can be written varies depending on the target CPU module.
CPU mode Number of Write Points 7
Basic model QCPU 1 to 160
Universal model QCPU 1 to 7168

9.1.2 Writing to host station CPU shared memory (TO(P), DTO(P))

9.1 Writing to the CPU Shared Memory of Host CPU
Writing data to CPU shared memory can be performed using the intelligent
function module device.
For intelligent function module device, refer to the QnUCPU User's Manual
(Function Explanation, Program Fundamentals) or Qn(H)/QnPH/QnPRHCPU
User's Manual (Function Explanation, Program Fundamentals).

9-9
 TO(P), DTO(P)

Operation Error
In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an
error code is stored into SD0.

(1) When the specified data is outside the following range (Error code: 4101)
• When the number of write points (n3) is outside the specified range of the setting data.
• When the CPU shared memory address (n2) of the write destination host CPU + the
number of write points (n3) exceeds the CPU shared memory range
• When the head number of the devices that stores the data to be written ( S ) + the number
of write points (n3) exceeds the device range
• When the head of CPU shared memory address (n2) of the write destination host CPU is
outside the write permitted area.
(2) When the head of CPU shared memory address (n2) of the write destination host CPU is an
invalid value. (Error code: 4111)
(3) When the I/O number specified in (n1) is other than that of the host CPU (Exclude the case
when the multiple CPU high speed transmisson area of other CPU is used.)
(Error code: 4112)
(4) No CPU module is installed at the position specified by the head I/O number of the CPU
module. (Error code: 2110)

Program Example
(1) The following program stores 10 points of data from D0 into address 10000 of the CPU
shared memory of CPU No. 1 when X0 is turned ON.
[Ladder Mode] [List Mode]
Step Instruction Device

(2) The following program stores 20 points of data from D0 into address 10000 of the CPU
shared memory of CPU No. 4 when X0 is turned ON.
[Ladder Mode] [List Mode]
Step Instruction Device

Remark
The n1 is specified by the first 3 digits of the hexadecimal 4 digits which represent
the head I/O number of the slot mounted to the CPU module.
CPU Slot Slot 0 Slot 1 Slot 2
Head I/O number 3E00 3E10 3E20 3E30
n1 3E0 3E1 3E2 3E3

9-10
9.2 Reading from the CPU Shared Memory of another CPU
9
The FROM(P)/DFRO(P) instruction of Multiple CPU system can be read from the following
memories.
7
• Buffer memory of intelligent function module
• CPU shared memory of other CPU module
• CPU shared memory of host CPU module (applicable for the Basic model QCPU and 7
Universal model QCPU)

The following figure shows the processing performed when the FROM(P) instruction is executed 7
in CPU No. 1.

7
Intelligent
CPU No. 1 CPU No. 2 function module
Data read
7
*1
Device Data CPU Device CPU Buffer
memory read shared
memory
memory shared
memory
memory 7

7
Reads data

[ FROM H3E1 n1 n2 D n3]

9.2 Reading from the CPU Shared Memory of another CPU

Designation of CPU shared memory of CPU No. 2

[ FROM H3E0 n1 n2 D n3]

Designation of CPU shared memory of CPU No. 1

[ FROM H0 n1 n2 D n3]

Designation of intelligent function module

*1 : Applicable for the Basic model QCPU and Universal model QCPU

Remark
Refer to Section 7.8.1 for reading the buffer memory of the intelligent function
module with the FROM/DFRO instruction.

9-11
 FROM(P),DFRO(P)

9.2.1 Reading from Other CPU Shared Memory (FROM(P),

DFRO(P))
FROM(P),DFRO(P)

Ver. Ver.
High
Basic performance Process Redundant Universal LCPU

Basic model QCPU:The first 5 digits of serial No is "04122" or higher.

High performance model QCPU:Function version B or later.
(1) When Basic model QCPU, Universal model QCPU is used

indicates an instruction symbol of FROM/DFRO.

Command
FROM,DFRO n1 n2 D n3

Command
FROMP,DFROP P n1 n2 D n3

n1 : Head I/O number of the reading target CPU module (BIN 16 bits)
• Basic model QCPU : 3E0H to 3E2H
• Universal model QCPU: 3E0H to 3E3H
n2 : Head address of data to be read (BIN 16 bits)
• Basic model QCPU : 0 to 512
• Universal model QCPU: 0 to 4095, 10000 to 24335*1
D : Head number of the devices where the read data is stored (BIN 16 bits)
n3 : Number of read data (BIN 16 bits)
• Basic model QCPU : FROM(P): 1 to 512, DFRO(P) : 1 to 256
• Universal model QCPU: FROM(P): 1 to 14336*1, DRRO(P) : 1 to 7168*1

Setting Internal Devices J \ Constants Other

R, ZR U \G Zn
Data Bit Word Bit Word K, H U

n1 ––

n2 –– ––

D –– –– –– ––

n3 –– ––

*1: The setting range varies depending on the auto refresh setting range of the multiple CPU high speed
communication function.

Function
FROM
(1) Reads the data of n3 words from the CPU shared memory address designated by n2 of the
CPU module designated by n1, and stores that data into the area starting from the device
designated by D .
CPU shared memory of
Device memory the designated CPU (n1)
n2
D

n3
Reads the
data of n3
words

9-12
 FROM(P),DFRO(P)

(a) CPU shared memory address of the Basic model QCPU

CPU shared memory address

0(0H) Host CPU operation information area 9

96(60H)
System area
192(C0H) *2
Host CPU refresh area Read designation
permitted area
7
User free area

511(1FFH) 7
(b) CPU shared memory address of the Universal model QCPU*3
CPU shared memory address
7
0(0H) Host CPU operation information area
512(200H)

2048(800H)
System area
7
*2
Host CPU refresh area

User free area 7

4096(1000H) Read designation
Unusable permitted area
10000(2710H) 7
Multiple CPU high speed
transmisson area
7
24335(5F0FH)
*2 : Usable as a user free area when auto refresh setting is not made.
When auto refresh setting is made, the auto refresh send range and later are usable as a user
free area.
*3 : With Q02UCPU, data can not be written to the multiple CPU high speed transmission area.

9.2.1 Reading from Other CPU Shared Memory (FROM(P), DFRO(P))

9.2 Reading from the CPU Shared Memory of another CPU
(2) When 0 is specified in n3 as the number of data to be read, no processing is performed.
(3) The number of data to be read changes depending on the target CPU module.
CPU Module Number of Read Points
Basic model QCPU 1 to 512
Universal model QCPU 1 to 14336

DFRO
(1) Reads the data of (n3×2) words from the CPU shared memory address designated by n2 of
the CPU module designated by n1, and stores that data into the area starting from the
device designated by D .
CPU shared memory of the
Device memory designated CPU (n1)
n2
D

n3
Reads the data
of (n3 2)
words

9-13
 FROM(P),DFRO(P)

(2) When 0 is specified in n3 as the number of data to be read, no processing is performed.

(3) The number of data to be read changes depending on the target CPU module.
CPU Module Number of Read Points
Basic model QCPU 1 to 256
Universal model QCPU 1 to 7168

Read of data from the CPU shared memory can also be performed using the
intelligent function module devices.
For intelligent function module device, refer to the QnUCPU User's Manual
(Function Explanation, Program Fundamentals) or Qn(H)/QnPH/QnPRHCPU
User's Manual (Function Explanation, Program Fundamentals).

Operation Error
In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an
error code is stored into SD0.
(1) When the specified data is outside the following range. (Error code: 4101)
• The head of the CPU shared memory address (n2) which performs reading is outside the
CPU shared memory range.
• The address of the CPU shared memory (n2) which performs reading plus the number of
read points (n3) is outside the CPU shared memory range.
• The read data storage device number (D) plus the number of read points (n3) is outside
the specified device range.
(2) The CPU module does not exist in the position specified by the CPU module head I/O
number. (Error code: 2110)
(3) When the head of the CPU shared memory address (n2) which performs reading is an
invalid value. (4097 to 9999) (Error code: 4101)

9-14
 FROM(P),DFRO(P)

Program Example
9
(1) The following program stores 10 points of data from address C0H of the CPU shared
memory of CPU No. 2 into the area starting from D0 when X0 is turned ON.
[Ladder Mode] [List Mode] 7
Step Instruction Device

(2) The following program stores 20 points of data from address 10000 of the CPU shared
memory of CPU No. 4 into the area starting from D0 when X0 is turned ON.
7
[Ladder Mode] [List Mode]
Step Instruction Device 7

7
Remark
The n1 is specified by the first 3 digits of the hexadecimal 4digits which represent 7
the head I/O number of the slot mounted to the CPU module.
CPU Slot Slot 0 Slot 1 Slot 2
Head I/O number 3E00 3E10 3E20 3E30 7
n1 3E0 3E1 3E2 3E3

The QCPU provides automatic interlocks for the FROM and TO instructions.

9.2.1 Reading from Other CPU Shared Memory (FROM(P), DFRO(P))

9.2 Reading from the CPU Shared Memory of another CPU

9-15
 FROM(P),DFRO(P)

(2) When High Performance model QCPU, Process CPU is used

Command
FROM FROM n1 n2 D n3

Command
FROMP FROMP n1 n2 D n3

n1 : Head I/O number of the reading target CPU module (BIN 16 bits)
n2 : Head address of data to be read (BIN 16 bits)

D : Head number of the devices where the read data is stored (BIN 16 bits)
n3 : Number of read data (BIN 16 bits)

Setting Internal Devices J \ Constants Other

R, ZR U \G Zn
Data Bit Word Bit Word K, H U

n1 ––

n2 –– ––

D –– –– –– ––

n3 –– ––

Function
(1) Reads the data of n3 words from the CPU shared memory address designated by n2 of the
CPU module designated by n1, and stores that data into the area starting from the device
designated by D .
CPU shared memory of
Device memory the designated CPU (n1)
n2
D

n3
Reads the
data of n3
words
CPU shared memory address of the High Performance model QCPU and Process CPU
CPU shared memory address

0(0H) Host CPU operation information area

512(200H)
System area
2048(800H) *1
Host CPU refresh area Read designation
permitted area

User free area

4095(0FFFH)
*1 : Usable as a user free area when auto refresh setting is not made.
When auto refresh setting is made, the auto refresh send range and later are usable as a user
free area.

(2) When 0 is specified in n3 as the number of data to be read, no processing is performed.

(3) The number of data to be read changes depending on the target CPU module.
CPU Module Number of Read Points
High Performance model QCPU
1 to 4096
Process CPU

9-16
 FROM(P),DFRO(P)

Read of data from the CPU shared memory can also be performed using the 9
intelligent function module devices.
For intelligent function module device, refer to the QnUCPU User's Manual
(Function Explanation, Program Fundamentals) or Qn(H)/QnPH/QnPRHCPU 7
User's Manual (Function Explanation, Program Fundamentals).

7
Operation Error
In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an
7
error code is stored into SD0.
(1) When the specified data is outside the following range. (Error code: 4101)
7
• The head address of the CPU shared memory (n2) from which read will be performed is
outside the CPU shared memory range.
• The address of the CPU shared memory (n2) from which data is read plus the number of 7
read points (n3) is outside the CPU shared memory range.
• The read data storage device number (D) plus the number of read points (n3) is outside
the specified device range. 7
(2) The CPU module does not exist in the position specified by the CPU module head I/O
number. (Error code: 2110)
(3) When the head of read CPU shared memory address (n2) is an invalid value. 7
(4097 to 9999) (Error code: 4101)

Program Example

9.2.1 Reading from Other CPU Shared Memory (FROM(P), DFRO(P))

9.2 Reading from the CPU Shared Memory of another CPU
(1) The following program stores data of 10 points from address 800H of the CPU shared
memory of CPU No. 2. into the area starting from D0 when X0 is turned ON.
[Ladder Mode] [List Mode]
Step Instruction Device

Remark
The n1 is specified by the first 3 digits of the hexadecimal 4digits which represent
the head I/O number of the slot mounted to the CPU module.
CPU Slot Slot 0 Slot 1 Slot 2
Head I/O number 3E00 3E10 3E20 3E30
n1 3E0 3E1 3E2 3E3

The QCPU provides automatic interlocks for the FROM and TO instructions.

9-17
MEMO

9-18
10
7

QCPU INSTRUCTIONS 10

Category Processing Details

Reference 7
section
Write instruction to another CPU Writes devices to another CPU. Section 10.2
Read instruction from another
Reads devices from another CPU. Section 10.3
7
CPU

10-1
 10.1 Overview
The multiple CPU high-speed transmission dedicated instruction directs the Universal model
QCPU to write/read device data to/from the Universal model QCPU in another CPU.
The following shows an operation when CPU No.1 writes device data to CPU No.2 with the
multiple CPU high-speed transmission dedicated instruction.

CPU No.1 CPU No.2

User program

DP.DDWR U3E1 D0 D100 D200 M0

D0 D0

D100
Writing
D200

The multiple CPU high-speed transmission dedicated instruction in either host

CPU or another CPU (target CPU module of instruction) is available only for the
following CPU modules.
• Q03UDCPU, Q04UDHCPU, Q06UDHCPU
The first five digits of serial numeber is 10012 or higer.
• Q10UDHCPU, Q13UDHCPU, Q20UDHCPU, Q26UDHCPU
• QnUDE (H) CPU

(1) Parameter setting and system configuration to execute the multiple CPU high-speed
transmission dedicated instruction
The multiple CPU high-speed transmission dedicated instruction can be executed in the
following parameter setting and system configuration.
• CPU No.1 uses QnUD(H)CPU or QnUDE(H)CPU.
• The multiple CPU high speed main base unit (Q3 DB) is used.
• "Use multiple CPU high speed transmission" is selected in the Multiple CPU settings
screen of PLC parameter.

10-2
 (2) Writable/readable devices
(a) Writable/readable device names 7
The following table shows the devices that can be written to/read from the Univesal
model QCPU in another CPU with the multiple CPU high-speed transmission dedicated
instruction. 10
Setting of target
Category Type Device name Remarks
device
Requirements for the setting
• Digits are specified by 16 bits (4 digits). 7
Bit device X, Y, M, L, B, F, SB
Internal user device • The start bit device is multiples of
16(10H).
Word device T, ST, C, D, W, SW –– 7
Requirements for the setting
• Digits are specified by 16 bits (4 digits).
Bit device SM
• The start bit device is multiples of
Internal system device
16(10H).
7
Word device SD ––
File register Word device R, ZR ––

:Settable :Settable with conditions

7

SB, SW, SM, and SD include system information area. Take care not to destroy
7
the system information when writing data to the devices above with the
D(P).DDWR instruction of the multiple CPU high-speed transmission dedicated
instruction.
7

(3) Specification method of a device and writable/readable device range

There are two methods for specifying a device in another CPU: device specification and

10.1 Overview
string specification. They differ in writable/readable device range to another CPU.

(a) Device specification

The device specification is a method to directly specify a device in another CPU to be
written/read.

Program for device specification with the DP.DDWR instruction

X0
DP.DDWR H3E1 D0 D100 D200 M0

Directly specifies "D200", a

device in another CPU to be
written.
In the device specification, data can be written/read within the device range of host CPU.
For example, when data register in host CPU is 12k points and data register in another CPU
is 16k points, data can be written/read by 12k points from the start of the data register in
another CPU.

10-3
 Writable/readable device range in device specification
Host CPU Another CPU
D0 D0

Data register Data register

Writable/readable
(12k points) (16k points)

D12287 D12287
D12288
Not writable/not readable
D16383

(b) String specification

The string specification is a method to specify a device in another CPU to be written/
read by character string.
Program for string specification with the DP.DDWR instruction
X0
DP.DDWR H3E1 D0 D100 "D200" M0

Specifies "D200", a device in another CPU

to be written by characer string.
In the string specification, data can be written to/read from all device ranges of another
CPU.
For example, when data register in host CPU is 12k points and data register in another
CPU is 16k points, data can be written/read by 16k points from the start of the data
register in another CPU.
Writable/readable device range in string specification
Host CPU Another CPU
D0 D0

Data register Data register

to to
(12k points) (16k points)
Writable/readable

D12287

D16383

Remark
The following explains precautions for string specification.
• The number of characters that can be specified is 32.
• Whether "0" is appended at the start of the device number or not, the devices
are processed as the same.
• For example, both "D1" and "D0001" are processed as "D1".
• Whether a device is specified by upper case character or lower-case character,
they are processed as the same.
• For example, both "D1" and "d1" are processed as "D1".
• If a device not existing in another CPU is specified by a character string, the
instruction will be completed abnormally.

10-4
(4) Managing the multiple CPU high speed transmission area
(a) The multiple CPU high speed transmission area is managed by blocks in units of 16 7
words.
The following table shows the number of blocks that can be used in each CPU and the
number of blocks used in the instruction. 10
*1
System area
C Number of CPU modules
1k points 2k points
2 46 110 7
3 22 54
4 14 35

*1: For setting of the system area, refer to the QCPU User's Manual (Multiple CPU System). 7
(b) The following shows configuration of the multiple CPU high speed transmission area
when the multiple CPU system is configured with three CPU modules and the system
area size is 1k word.
7
Multiple CPU high speed Multiple CPU high speed Multiple CPU high speed
transmission area in transmission area in transmission area in
CPU No.1 CPU No.2
Area to be sent from CPU No.1 to CPU No.s 2 and 3
CPU No.3
7
22 Send area to Receive area from 22
blocks CPU No.2 CPU No.1 blocks
22 Send area to
blocks CPU No.3
Receive area from 22
blocks
7
CPU No.1

Area to be sent from CPU No.2 to CPU No.s 1 and 3

22 Receive area to Send area to 22 7

blocks CPU No.2 CPU No.1 blocks
22 Send area to Receive area to 22
blocks CPU No.3 CPU No.2 blocks

Area to sent from CPU No.3 to CPU No.s 1 and 2

10.1 Overview
22 Receive area to Send area to 22
blocks CPU No.3 CPU No.1 blocks
22 Receive area to Send area to 22
blocks CPU No.3 CPU No.2 blocks

(5) The number of blocks used for the instruction

The number of blocks used for the instruction depends on the number of write points.
The following table shows the number of blocks used for the instruction.
Number of write/read points specified by
D(P).DDWR instruction D(P).DDRD instruction
the instruction
1 to 4 1
5 to 20 2
21 to 36 3
37 to 52 4 1
53 to 68 5
69 to 84 6
85 to 100 7

10-5
 (6) The multiple CPU high-speed transmission dedicated instructions that can be executed
concurrently
For the Universal model QCPU, the multiple CPU high-speed transmission dedicated
instructions can be concurrently executed within the range satisfying the following formula.
The number of blocks that Total number of blocks used for the
can be used in each CPU instructions concurrently executed

When the number of blocks used for the multiple CPU high-speed transmission dedicated
instructions exceeds the total number of blocks in the multiple CPU high speed transmission
area, the instruction will not be executed in the scan (no processing) but executed at the
next scan.
Note that the instruction will be completed abnormally when the number of empty blocks in
the multiple CPU high speed transmission area is less than the setting values of SD796 to
SD799 (maximum number of used blocks for multiple CPU high-speed transmission
dedicated instruction setting) at the execution of the instruction.
The following table shows execution possibility of the multiple CPU high-speed transmission
dedicated instructions when the number of empty blocks in the multiple CPU high speed
transmission area is less than the number of blocks used for the multiple CPU high-speed
transmission dedicated instructions or the setting values of SD796 to SD799.
Magnitude relation between the number of blocks
used for the instructions*1 and
the number of empty Number of blocks used Number of blocks used
Number of empty blocks*2 Number of empty blocks*2
Magnitude relation blocks for the instruction*1 for the instruction*1
between SD setting value
and the number of empty blocks
SD setting value*3 Number of empty blocks*2 Executed Not executed (no processing)
SD setting value*3 Number of empty blocks*2 Completed abnormally

*1:The number of blocks used for the multiple CPU high-speed transmission dedicated instruction.
*2:The number of empty blocks in the multiple CPU high-speed transmission area.
*3:Setting values from SD796 of SD799.

10-6
(7) Interlock when using the multiple CPU high-speed transmission dedicated instruction
(a) Special relays SM796 to SM799 (maximum number of used blocks for multiple CPU 7
high-speed transmission dedicated instruction setting) can be used as an interlock for
the multiple CPU high-speed transmission dedicated instruction.
When executing the multiple CPU high-speed transmission dedicated instructions 10
concurrently, use SM796 to SM799 as an interlock for the instructions.

7
When using special relays SM796 to SM799, set the maximum number of blocks
for the instruction used for each CPU to special registers SD796 to SD799. (For
example, when the maximum number of blocks for the multiple CPU high-speed 7
transmission dedicated instruction to be executed to CPU No.3 is 5, set 5 to
SD798.)
When the multiple CPU high speed transmission area becomes equal to or less 7
than the number of blocks set at SD796 to SD799, the corresponding special
relay (SM796 to SM799) turns on.
CPU No.1
Multiple CPU high speed transmission area Multiple CPU high speed transmission area
CPU No.2
7
SM
Execution Send area Receive area
command 797
(1 2) (1 2)
DP.DDWR H3E1
7
Number of request blocks:4 During use

Number of empty blocks:

Turns on when the number of empty blocks
is less than the number of blocks used for
2
7
the DP.DDWR instruction.
Lnsufficient for writing a request from
(The DP.DDWR instruction is not executed.)
the DP.DDWR instruction.

Empty area of the request blocks in send area (1 2) has been increased.
CPU No.1 CPU No.2

10.1 Overview
Multiple CPU high speed transmission area Multiple CPU high speed transmission area

SM
Execution 797 Send area Receive area
command (1 2) (1 2)
DP.DDWR H3E1
During use

Number of request blocks:4

Number of empty blocks:
8

Turns off as empty blocks by the number of blocks

used for the DP.DDWR instruction became available
(The DP.DDWR instruction can be written.)
The request from the DP.DDWR instruction can be written.

10-7
 (b) Program example when SM796 to SM799 are used as an interlock
The following shows a program that executes the D.DDWR instruction to CPU No.2 at
the rise of X0, and executes the D.DDWR instruction to CPU No.3 at the rise of X1.
The maximum number of used blocks for multiple CPU hight speed transmission dedicated
SM402
0 MOV K7 SD797
Turn-on for one Maximum number of
scan after RUN used blocks
(CPU No.2)

MOV K7 SD798
Maximum number of
used blocks
(CPU No.3)

SM402
8 MOV K100 D1
Turn-on for one Mumber of write points
scan after RUN to CPU No.2

MOV K100 D3
Mumber of write points
to CPU No.3

The DDWR instruction is executed to CPU No.2 at the rise of X0

X0
11 SET M0
Execution command of the During execution the
DDWR instruction to CPU No.2 DDWR instruction to
CPU No.3

M0 SM797
14 D.DDWRH3E1 D0 ZR0 ZR0 M1
During execution Number of used Completion Write data Write data Completion
of the DDWR blocks information status to CPU No.2 to CPU No.2 devaice
instruction to (CPU No.2) (CPU No.2) (CPU No.2)
CPU No.3

RST M0
During execution of the
DDWR instruction to CPU No.2

The DDWR instruction is executed to CPU No.3 at the rise of X1

X1
29 SET M3
During execution of the DDWR During execution the
instruction to CPU No.3 DDWR instruction to
CPU No.3

M3 SM798
32 D.DDWRH3E2 D2 ZR1000 ZR1000 M4
During execution Number of used Completion Write data Write data Completion
of the DDWR blocks information status to CPU No.3 to CPU No.3 device
instruction to (CPU No.3) (CPU No.3) (CPU No.3)
CPU No.3

RST M3
During execution of the
DDWR instruction to CPU No.3

10-8
 (8) Program example when the multiple CPU high-speed transmission dedicated instructions
are executed to CPU modules by turns
When the multiple CPU high-speed transmission dedicated instructions are executed to
7
Universal model QCPUs by turns, release an interlock to prevent the concurrent execution.
Use the cyclic transmission area device (from U3En\G10000) as an interlock.
The following shows a program example when the multiple CPU high-speed transmission 10
dedicated instructions are executed at CPU No.s 1 and 2 by turns.

Program example when the multiple CPU high-speed transmission dedicated instruction is 7
executed at CPU No.1

SM402

Turn-on for one scan

MOV K7 SD797
Maximum number
7
after RUN of used blocks
(CPU No.2)

X0 7
SET M0
Write command During execution of the
DDWR instruction

U3E0\G10000.0 is turned on while CPU No.1 is executing the DP.DDWR instruction. 7

M0 U3E1\G10000.0 SM797 U3E0\
SET G10000.0
During execution
of the DDWR
CPU No.2 is
during execution
Number of used
blocks information
CPU No.1 is during
execution of the 7
instruction of the instruction (CPU No.2) instruction

MOV K100 D1 7
Number of
write points

10.1 Overview
DP.DDWR H3E1 D0 ZR100 ZR100 M1
Completion Completion
status device

RST M0
During execution of
the DDWR instruction

U3E0\G10000.0 is turned on while CPU No.1 is executing the DP.DDWR instruction.

M1 U3E0\
SET G10000.0
Completion device CPU No.1 is during of
the instruction

10-9
 Program example when the multiple CPU high-speed transmission dedicated instruction is
executed at CPU No.2
SM402
MOV K1 SD796
Turn-on for one Maximum number of
scan after RUN used blocks
(CPU No.1)

X20
SET M0
Read instruction During execution the
DDRD instruction
U3E1\G10000.0 is turned on while CPU No.2 is executing the DP.DDRD instruction.

M0 U3E0\G10000.0 SM796 U3E1\

SET G10000.0
During execution CPU No.1 is Number of used CPU No.2 is during
of the DDWR during execution blocks information execution of the
instruction of the instruction (CPU No.1) instruction

MOV K50 D1
Read instruction

DP.DDRD H3E0 D0 D1000 D1000 M1

Completion Completion
status devaice

RST M0
During execution of
the DDRD instruction

U3E1\G10000.0 is turned off at the completion of the DP.DDRD instruction.

M1 U3E1\
RST G10000.0
Completion device CPU No.2 is during of
execution the instruction

(9) Program example when data exceeding 100 words are written/read with the multiple CPU
high-speed transmission dedicated instruction
The maximum number of write/read points that can be processed with the multiple CPU
high-speed transmission dedicated instruction is 100 words. Data exceeding 100 words can
be written/read by executing the multiple CPU high-speed transmission dedicated
instruction at several times.
The following shows a program example using the D(P).DDWR instruction of the multiple
CPU high-speed transmission dedicated instruction. The similar program can be used when
using the D(P).DDRD instruction of the multiple CPU high-speed transmission dedicated
instruction.

10-10
 (a) Program example when one D(P).DDWR instruction is executThe following shows a
program example that writes ZR0 to ZR999 (1000 points) in CPU No.1 to ZR0 to ZR999
in CPU No.2 with the D.DDWR instruction.
7
In the following program example, the next D.DDWR instruction is executed after the
completion device of the D.DDWR instruction (M2) turns on so that only one D.DDWR
instruction may be executed.
10
Program example when one D(P).DDWR instruction is executed
The maximum number of used blocks for multiple CPU high-speed
transmission dedicated instruction setting is set to CPU No.2 7
SM402
0 MOV K7 SD797
Turn-on for one Maximum number of
scan after used blocks
(CPU No.2) 7
MOV K100 D1
Number of
write points 7
Data writing is started at the rise of the write command (X0)

X0 M0
7
37 RST Z2
Write During
comman writing
7
SET M0
During writing

68
M0
SET M1
7
During During execution of
writing the DDWR instruction

M4

10.1 Overview
Execution request of the next
DDWR instruction

The DDWR instruction is executed

M1 SM797
71 D.DDWR H3E1 D0 ZR0Z2 ZR0Z2 M2
During execution Number of used Completion Write source/write Completion
of the DDWR blocks information status destination device
instruction (CPU No.2)

RST M1
During execution of the
DDWR instruction
When the DDWR instruction is completed abnomally, the annunciator is turned on and data writing is stopped
M2 M3
98 SET F0
Completion Error
device completion
device
RST M0
During
writing
Next data writing is requested at nomal completion of the DDWR instruction
M2 M3
134 + K100 Z2
Completion Error
device completion
device
< Z2 K1000 PLS M4
Execution request of the
next DDWR instruction
= Z2 K1000 RST M0
During writing

173 END

10-11
 (b) Program example when the D(P).DDWR instructions are executed concurrently
The following shows a program example that writes ZR0 to ZR999 (1000 points) in CPU
No.1 to ZR0 to ZR999 in CPU No.2 with the D.DDWR instruction.
As shown on the program example, multiple CPU device write/read instructions can be
executed concurrently.
When reading/writing devices with the multiple CPU high-speed transmission dedicated
instructions concurrently, the more the total number of blocks in the multiple CPU high
speed transmission area (send area), the more the time taken to complete reading/
writing with the multiple CPU high-speed transmission dedicated instruction can be
shortened.

Program example when the D(P).DDWR instructions are executed concurrently

The maximum number of used blocks for multiple CPU high-speed

transmission dedicated instruction setting is set to CPU No.2
SM402
0 MOV K7 SD797
Turn-on for one Maximum number of
scan after RUN used blocks
(CPU No.2)
MOV K100 D1
Number of
write points 1
MOV K100 D3
Number of
Data writing is started at the rise of the write command (X0) write points 2
X0 M0
39 RST Z2
Write During
comma writing
SET M0
During writing
First DDWR instruction, Second DDWR instruction
M0
70 SET M1
During During execution of
writing the DDWR instruction 1
M7
SET M2
Execution request of the next During execution of
DDWR instruction the DDWR instruction 2
The first DDWR instruction is executed
M1 SM797
94 D.DDWR H3E1 D0 ZR0Z2 ZR0Z2 M3
During execution Number of used Completion Write source write Completion
of the DDWR blocks information status 1 destination device 1
instruction 1 (CPU No.2)
RST M1
The second DDWR instruction is executed During execution of the
DDWR instruction 1
M2 SM797
126 D.DDWR H3E1 D2 ZR100Z2 ZR100Z2 M5
During execution Number of used 3 Completion Write source write Completion
of the DDWR blocks information status 2 destination device 2
instruction 2 (CPU No.2)
RST M2
During execution of the
DDWR instruction 2
When the DDWR instruction is completed abnomally, the annunciator is turned on and data writing is stopped
M3 M4
158 SET F0
Completion Error DDWR instruction
device 1 completion error display
device 1
M5 M6
RST M0
Completion Error During
device 2 completion writing
device 2
Next data writing is requested at nomal completion of the second DDWR instruction
M5 M6
197 + K200 Z2
Completion Error
device 2 completion
device 2 < Z2 K1000 PLS M7
Execution request of the
next DDWR instruction
= Z2 K1000 RST M0
During writing
241 END

10-12
 D(P).DDWR

10.2 Writing Devices to Another CPU (D(P).DDWR)

7
D(P).DDWR

Ver.
Basic High
performance Process Redundant Universal LCPU 10
Q03UDCPU, Q04UDHCPU, Q06UDHCPU: that the first 5 digits of serial number is 10012 or higer QnUDE(H)CPU.

7
Command
D.DDWR D.DDWR n S1 S2 D1 D2

Command
7
DP.DDWR DP.DDWR n S1 S2 D1 D2

7
Setting Internal device J \ Constant
R, ZR U \G Zn Others
data Bit Word*5 Bit Word K, H

n *1 –– –– –– 7
S1 *2 –– *3 *4 –– –– ––

S2 *2 –– –– –– ––

D1 *2 –– –– –– ––
7
D2 *2 *6 –– *4 –– –– ––

*1: Index modification cannot be made to setting data n.

*2: Index modification cannot be made to setting data from S1 to D2 .
7
*3: Local devices cannot be used.
*4: File registers cannot be used per program.
*5: FD @ (indirect specification) cannot be used.
*6: FX and FY cannot be used.

10.2 Writing Devices to Another CPU (D(P).DDWR)

Set Data

Setting data Description Data type

The result of dividing the start I/O number of another CPU by 16
n BIN 16 bits
CPU No.1: 3E0H, CPU No.2: 3E1H, CPU No.3: 3E2H, CPU No.4: 3E3H
S1 Start device of the host CPU that stores control data
Device name
S2 Start device of the host CPU that stores data to be written

Device*7
S
D1 Start device of another CPU that stores write data Character
string*8*9
D2 Completion device Bit

*7: By specifying a file register (R, ZR), data can be written to devices in another CPU, outside the range of host
CPU.
*8: By specifying the start device by " ", devices can be written to devices in another CPU, outside the range of
host CPU.
*9: Indexed devices cannot be specified (e.g. D0Z0).

10-13
 D(P).DDWR

Control Data

Device Item Setting data Setting range Set by

An execution result upon completion of the
instruction is stored.
S1 +0 Completion status –– System
0000(H): No errors (normal completion)
Other than 0000(H): Error code (error completion)
Number of write
S1 +1 Set the number of write points in units of words. 1 to 100 User
points

Function
(1) In multiple CPU system, data stored in a device specified by host CPU ( S2 ) or later is stored
by the number of write points specified by ( D2 +1) into a device specified by another CPU (n)
( D1 ) or later.
Strat devaice number of the Start device nimber of the strage
storageiocation for write data iocation where write data has stored
S2 D1
Host CPU Another CPU n
(CPU that repuests writing) (CPU to be read)

Number of write points

S1 +1

(2) Whether to complete the D(P).DDWR instruction normally can be checked by the
completion device ( D2 +0) and completion status display device ( D2 +1).

(a) Completion device ( D2 +0)

Turns on at END processing in the scan where the instruction has been completed, and
turns off at the next END processing.

(b) Completion status display device ( D2 +1)

This device turns on/off depending on the status upon completion of the instruction.
• Normal completion: Off
• Error completion: Turns on at END processing in the scan where the instruction has
been completed, and turns off at the next END processing (At error completion, an
error code is stored at control data ( S1 +0): Completion status)).

10-14
 D(P).DDWR

(3) The number of blocks used for the instruction depends on the number of write points (refer
to Section 12.1).
Number of blocks used for the instruction
7
Number of write points D(P).DDWR
specified by the instruction instruction
1 to 4 1 10
5 to 20 2
21 to 36 3
37 to 52
53 to 68
4
5
7
69 to 84 6
85 to 100 7
7
(4) The instruction will be completed abnormally when there are no empty blocks in the multiple
CPU high speed transmission area.
Set the number of blocks used for the instruction at special registers (SD796 to SD799), and
use the special relays (SM796 to SM799)as an interlock prevent error completion (refer to
7
Section 12.1).

7
Operation Error
In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an
error code is stored into SD0.
7
(1) Specified another CPU is wrong or the multiple CPU high-speed transmission dedicated
instruction cannot be used in the setting (Error code: 4350) 7
• The reserved CPU has been specified.
• Unmounted CPU has been specified.
• Another CPU start I/O number divided by 16n is out of 3E0H to 3E3H.

10.2 Writing Devices to Another CPU (D(P).DDWR)

• The instruction was executed without setting "Use multiple CPU high speed
transmission".
• The instruction was executed with the Q02UCPU.
• Host CPU has been specified.
• The CPU where the instruction cannot be executed has been specified.
(2) The instruction cannot be executed with the CPU. (Error code: 4351)
• Another CPU does not support this instruction.
(3) The number of devices is wrong. (Error code: 4352)
(4) The device that cannot be used for the instruction has been specified. (Error code: 4353)
(5) A device has been specified by the character string that cannot be used. (Error code: 4354)

(6) The number of write points ( S1 +1)is other than 0 to 100. (Error code 4354)

10-15
 D(P).DDWR

In any of the following cases, the instruction is completed abnormally, and an error code is
stored into a device specified at completion status storage device ( S1 +0).
(1) The request of the instruction to the target CPU is more than the acceptable value (no empty
blocks exist in the multiple CPU high speed transmission area).
(Error code: 0010H)

(2) A device for another CPU specified at S1 cannot be used at another CPU, or is out of device
range. (Error code: 1001H)
(3) The number of write points set with the D(P).DDWR instruction is 0.
(Error code: 1080H)
(4) The response of the instruction from another CPU cannot be returned (no empty blocks exist
in the multiple CPU high speed transmission area). (Error code: 1003H)

Program Example
(1) This program stores data by 10 words starting from D0 in host CPU into W10 or later in CPU
No.2 when X0 turns on.
[Ladder mode]

[Ladder mode]

Caution
(1) Digit specification of bit device is possible for n, S2 , and D1 . Note that when the digit
specification of bit device is made to S2 or D1 , the following conditions must be met.
• Digits are specified by 16 bits (4 digits).
• The start bit device is multiples of 16 (10H).
(2) Execute this instruction after checking that the write target CPU is powered on. Not doing so
may end up no processing.
(3) If changing a range of the device specified at setting data between after execution of the
instruction and turn-on of the completion device, data to be stored by system (completion
status, completion device) cannot be stored normally.
(4) SB, SW, SM, and SD include system information area. Take care not to destroy the system
information when writing data to the devices above with the D(P).DDWR instruction of the
multiple CPU high-speed transmission dedicated instruction.

10-16
 D(P).DDRD

10.3 Reading Devices from Another CPU (D(P).DDRD)

7
D(P).DDRD

Ver.
Basic High
performance Process Redundant Universal LCPU 10
Q03UDCPU, Q04UDHCPU, Q06UDHCPU: that the first 5 digits of serial number is 10012 or higer
QnUDE(H)CPU.
7
Command
D.DDRD D.DDRD n S1 S2 D1 D2
7
Command
DP.DDRD DP.DDRD n S1 S2 D1 D2

7
Setting Internal device J \ Constant
R, ZR Zn Others
data Bit Word*5 Bit Word
U \G
K, H 7
*1 –– –– ––
n

S1 *2 –– *3 *4 –– –– ––

S2 *2 –– –– –– –– 7
S *2
D1 –– –– –– ––

D2 *2 *6 –– *4 –– –– ––

*1: Index modification cannot be made to setting data n. 7

*2: Index modification cannot be made to setting data from S1 to D2 .
*3: Local devices cannot be used.
*4: File registers cannot be used per program.
*5: FD @ (indirect specification) cannot be used.
*6: FX and FY cannot be used.

10.3 Reading Devices from Another CPU (D(P).DDRD)

Set Data

Setting data Description Data type

The result of dividing the start I/O number of another CPU by 16
n BIN 16 bits
CPU No.1: 3E0H, CPU No.2: 3E1H, CPU No.3: 3E2H, CPU No.4: 3E3H
S1 Start device of the host CPU that stores control data
Device name
S2 Start device of another CPU that stores data to be read

Device*7
S
D1 Start device of the host CPU that stores read data Character
string*8*9
D2 Completion device Bit

*7: By specifying a file register (R, ZR), data can be read to devices in another CPU, outside the range of host
CPU.
*8: By specifying the start device by " ", devices can be read to devices in another CPU, outside the range of host
CPU.
*9: Indexed devices cannot be specified (e.g. D0Z0).

10-17
 D(P).DDRD

Control Data

Device Item Setting data Setting range Set by

An execution result upon completion of the
instruction is stored.
S1 +0 Completion status –– System
0000(H): No errors (normal completion)
Other than 0000(H): Error code (error completion)
Number of read
S1 +1 Set the number of read points in units of words. 1 to 100 User
points

(1) In multiple CPU system, data stored in a device specified by another CPU (n) ( D1 ) or later is
stored by the number of read points specified by ( S1 +1) into a device specified by host CPU
( S2 ) or later.
Strat device number of the storage
Start device number of the location where read has been stored
storage location for read data
D2 Host CPU Another CPU n S1
(CPU that requests reading) (CPU to be read)

Number of read points

S1 +1

(2) Whether to complete the D(P).DDRD instruction normally can be checked by the completion
device ( D2 +0) and completion status display device ( D2 +1).
(a) END processing in scan data that CPU completed the instruction turns on the device
and the next END processing turns off the device.

(b) This device turns on/off depending on the status upon completion of the instruction.
• Normal completion: Off
• Error completion: Turns on at END processing in the scan where the instruction has
been completed, and turns off at the next END processing (At error completion, an
error code is stored at control data ( S1 +0): Completion status)).

(3) The number of blocks used for the instruction depends on the number of read points (refer to
Section 12.1).
Number of blocks used for the instruction
Number of read points
D(P).DDRD instruction
specified by the instruction
1 to 100 1

(4) The instruction will be completed abnormally when there are no empty blocks in the multiple
CPU high speed transmission area.
Set the number of blocks used for the instruction at special registers (SD796 to SD799), and
use the special relays (SM796 to SM799)as an interlock prevent error completion (refer to
Section 12.1).

10-18
 D(P).DDRD

Operation Error
7
In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an
error code is stored into SD0.
(1) Specified another CPU is wrong or the multiple CPU high-speed transmission dedicated
10
instruction cannot be used in the setting (Error code: 4350).
• The reserved CPU has been specified.
7
• Unmounted CPU has been specified.
• The result of dividing the start I/O number of another CPU by 16n is outside the range of
3E0H to 3E3H. 7
• The instruction was executed without setting "Use multiple CPU high speed
transmission".
• The instruction was executed with the Q02UCPU. 7
• Host CPU has been specified.
• The CPU where the instruction cannot be executed has been specified.
7
(2) The instruction cannot be executed with the CPU. (Error code: 4351)
• Another CPU does not support this instruction.
(3) The number of devices is wrong. (Error code: 4352)
7
(4) The device that cannot be used for the instruction has been specified. (Error code: 4353)
(5) A device has been specified by the character string that cannot be used.(Error code: 4354) 7
(6) The number of read points ( S1 +1)is other than 0 to 100. (Error code: 4355)

In any of the following cases, the instruction is completed abnormally, and an error code is

10.3 Reading Devices from Another CPU (D(P).DDRD)

stored into a device specified at completion status storage device ( S1 +0).
(1) The request of the instruction to the target CPU is more than the acceptable value (no empty
blocks exist in the multiple CPU high speed transmission area). (Error code: 0010H)

(2) A device for another CPU specified at S2 cannot be used at another CPU, or is out of device
range. (Error code: 1001H)
(3) The number of read points set with the D(P).DDRD instruction is 0. (Error code: 1081H)
(4) The response of the instruction from another CPU cannot be returned (no empty blocks exist
in the multiple CPU high speed transmission area). (Error code: 1003H)

10-19
 D(P).DDRD

Program Example
(1) This program stores data by 10 words starting from D0 in CPU No.2 into W10 or later in host
CPU when X0 turns on.
[Ladder mode]

[List mode]

Caution
(1) Digit specification of bit device is possible for n, S2 , and D1 . Note that when the digit
specification of bit device is made to S2 or D1 , the following conditions must be met.
• Digits are specified by 16 bits (4 digits).
• The start bit device is multiples of 16 (10H).
(2) Execute this instruction after checking that the read target CPU is powered on. Not doing so
may end up no processing.
(3) If changing a range of the device specified at setting data between after execution of the
instruction and turn-on of the completion device, data to be stored by system (completion
status, completion device) cannot be stored normally.

10-20
11
7

QCPU INSTRUCTIONS 7

11

Category Processing Details

Reference 7
section
Switches between the control system and standby system at
System switching instruction the END processing of the scan executed with the Section 11.1 7
SP.CONTSW instruction.

11-1
 SP.CONTSW

11.1 System Switching Instruction (SP.CONTSW)

SP.CONTSW

High
Basic performance Process Redundant Universal LCPU

Command
SP.CONTSW SP.CONTSW S D

S : Value other than 0 and used to identify the processing that issued the system switching request (BIN 16 bits)
D : Error completion device number (bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S –– –– ––

D *1 –– –– ––

*1: The bit specification for the word device is available.

Function
(1) Switches between the control system and standby system at the END processing of the
scan executed with the SP.CONTSW instruction.
(2) When using the SP.CONTSW instruction for system switching, the "manual switching enable
flag (SM1592)" must have been turned ON (enabled) in advance.
(3) S is provided to identify the processing block of the program where system switching
occurred when multiple SP.CONTSW instructions are used.
At S , specify a value within the ranges -32768 to -1 and 1 to 32767 (1H to FFFFH).
The S value specified for the SP.CONTSW instruction is stored into the "system switching
instruction argument (SD6)" of the error common information when the system switching is
normally completed. *2
When multiple SP.CONTSW instructions are executed during the same scan, the argument
of the SP.CONTSW instruction executed first is stored into the system switching instruction
argument (SD6).
(4) When system switching is normally completed, the S value specified for the SP.CONTSW
instruction is stored into the "system switching instruction argument (SD1602)" of the new
control system CPU module. *3
By reading the SD1602 value from the new control system CPU module, which the
SP.CONTSW instruction was used for system switching can be confirmed.

*2 : The S value specified for the SP.CONTSW instruction can be confirmed in the error common information
of the PLC diagnostics dialog box on GX Developer.
*3 : The new control system CPU module means the CPU module that was switched from the standby system
to the control system by the SP.CONTSW instruction.

11-2
 SP.CONTSW

(5) The error completion device is turned ON by the control system CPU module when system
switching by the SP.CONTSW instruction was unsuccessful.
7
(a) When OPERATION ERROR is detected due to any of the following reasons at the
execution of the SP.CONTSW instruction, the error completion device is turned ON
during the instruction execution.
7
• 0 is specified at S of the executed SP.CONTSW instruction.
• The "manual switching enable flag (SM1592)" is OFF.
• The SP.CONTSW instruction was executed by the standby system in the separate
11
mode.
• The SP.CONTSW instruction was executed in the debug mode. 7
(b) If systems could not be switched due to any of the reasons given in the following table,
the error completion device turns ON when system switching is executed in the END
processing. 7
Reason No. Reasons for System Switching Failure
0 Normally completed
1 Tracking cable is disconnected or faulty.
7
Hardware fault, power-off, reset or watchdog timer error occurred in the standby
2
system.
3 Watchdog timer error occurred in the control system. 7
4 Preparations being made for tracking transfer.
5 Communication time-out.
6 Stop error occurred in the standby system. (Excluding watchdog timer error) 7
7 Operating status different between the control system and standby system.
8 Memory copy being executed from the control system to the standby system.
9 Write during RUN being executed.
10 Network fault detected by the standby system.

11.1 System Switching Instruction (SP.CONTSW)

When the error completion device was turned ON due to unsuccessful system
switching, 16 is stored into the "reason(s) for system switching (SD1588)" and the reason
No. of the above table into the "reason(s) for system switching failure (SD1589)".

(6) Use a user program or GX Developer to turn OFF the error completion bit that has turned
ON.
If normal system switching is performed by the execution of the SP.CONTSW instruction
with the error completion device ON, the error completion device of the new standby system
CPU module is also turned OFF.
When system switching is performed due to a factor other than the SP.CONTSW instruction,
however, the error completion device is not turned OFF.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The value specified at S is 0 at execution of the SP.CONTSW instruction.
(Error code: 4100)
• The manual switching enable flag (SM1592) is OFF (disable) at execution of the
SP.CONTSW instruction. (Error code: 4120)
• The SP.CONTSW instruction was executed by the standby system CPU module in the
separate mode. (Error code: 4121)
• The SP.CONTSW instruction was executed in the debug mode. (Error code: 4121)

11-3
 SP.CONTSW

(2) If system switching was unsuccessful, the error flag (SM0) is turned ON and an error code is
stored into SD0.
• The tracking cable is disconnected or faulty. (Error code: 6220)
• Hardware fault, power-off, reset or watchdog timer error occurred in the standby system.
(Error code: 6220)
• Watchdog timer error occurred in the control system. (Error code: 6220)
• Preparations are being made for tracking transfer. (Error code: 6220)
• Communication time-out occurred. (Error code: 6220)
• Stop error, excluding watchdog timer error, occurred in the standby system.
(Error code: 6220)
• The operating status differs between the control system and standby system.
(Error code: 6220)
• Memory copy is being executed from the control system to the standby system.
(Error code: 6220)
• Write during RUN is being executed. (Error code: 6220)
• Network fault was detected by the standby system. (Error code: 6220)

Program Example
(1) The following program executes system switching on the leading edge of the system
switching command (M100).
If the system switching command (M100) remains ON, the SP.CONTSW instruction is also
executed by the new control system CPU module after system switching. Therefore, M101 is
added to the execution conditions as a consecutive switching prevention flag.

[Ladder Mode] [List Mode]

Step Instruction Device

11-4
12
6

ERROR CODES 6

12

12-1
 12.1 Error Code List
The CPU module uses the self diagnostics function to display error information (on the LED) and
stores the information into the special relay SM and special register SD, when an error occurs in
the following situations:
• When the Progammable Controller is powered ON.
• When the CPU module is switched from STOP to RUN.
• While the CPU module is running.
If an error occurs when a communication request is issued from the peripheral device, intelligent
function module or network system to the CPU module, the CPU module returns the error code
(4000H to 4FFFH) to the request source.
The following describes the description of errors which occur in the CPU module and the
corrective actions for the errors.

(1) How to read the error code list

The following describes how to read Section 12.1.3 Error code list (1000 to 1999) to Section
12.1.9 Error code list (7000 to 10000). The list contains errors in QCPU and LCPU.

(a) Error code, common information and individual information

The error code is stored in SD0. The common information is stored in SD5 to SD15. The
individual information is stored in SD16 to SD26.

(b) Compatible CPU

• QCPU: All the Q series CPU modules
• Q00J/Q00/Q01: Basic model QCPU
• Qn(H): High Performance model QCPU
• QnPH: Process CPU
• QnPRH: Redundant CPU
• QnU: Universal model QCPU
• Q00UJ/Q00U/Q01U: Q00UJCPU, Q00UCPU, and Q01UCPU
• LCPU: All the L series CPU modules
• CPU module model: Only the specified model (Example: Q02UCPU, L26CPU-BT)

12-2
12.1.1 Error codes
1
Errors are detected by the self diagnostic function of the CPU module or detected during
communication with the CPU module.
The relation between the error detection pattern, error detection location and error code is shown 2
in Table 12.1.

3
Table12.1Reference destination
Error detection pattern Error detection location Error code Reference
Detection by the self 12
diagnostics function of CPU CPU module 1000 to 10000*1*2 Section 12.1.3 to 12.1.9
module
• User’s Manual (Hardware design,
CPU module 4000H to 4FFFH Maintenance and Inspection) for the CPU 6
module used
User's manuals for the serial communication
Serial communication module, etc. 7000H to 7FFFH
module, etc.
CC-Link module User's manuals for the CC-Link system master/
6
B000H to BFFFH
(the built-in CC-Link function included) local module
• User's manuals for the Ethernet interface

Ethernet module
module
• QnUCPU User's Manual (Communication via
7
Detection at communication C000H to CFFFH
(the built-in Ethernet function included) Built-in Ethernet Port)
with CPU module
• MELSEC-L CPU Module User's Manual
(Built-In Ethernet Function)
CC-Link IE Controller Network Reference
8
CC-Link IE controller network E000H to EFFFH
Manual
• MELSECNET/H mode
Q Corresponding MELSECNET/H Network
System Reference Manual
MELSECNET/H network module F000H to FFFFH
• MELSECNET/10 mode
For QnA/Q4AR MELSECNET/10 Network

12.1.1 Error codes

12.1 Error Code List
System Reference Manual

*1: CPU module error codes are classified into minor, moderate, major errors as shown below.
• Minor error: Errors that may allow the CPU module to continue the operation, e.g., battery error.
• Moderate error: Errors that may cause the CPU module to stop the operation, e.g., WDT error.
(Error code: 1300 to 10000)
• Major error: Errors that may cause the CPU module to stop the operation, e.g., RAM error.
(Error code: 1000 to 1299)
Determine the error level, i.e. whether the operation can be continued or stopped, by referring to
"Operating Statuses of CPU" described in Section 12.1.3 to 12.1.9 "Error Code List"
*2: When detected an error code without being noted in the reference table, please contact your local
Mitsubishi representive.

12.1.2 Reading an error code

When an error occurs, reading an error code, error message or the like can be executed with GX
Developer.
For the details of the operation method, refer to the operating manual for GX Developer.

12-3
 12.1.3 Error code list (1000 to 1999)

The following shows the error messages from the error code 1000 to 1999, the contents and
causes of the errors, and the corrective actions for the errors.
Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
[MAIN CPU DOWN]
Runaway or failure of the CPU module
• Malfunctioning due to noise or other reason
• Hardware failure
■Collateral information QCPU
• Common Information:-
• Take noise reduction measures.
• Individual Information:-
• Reset the CPU module and run it again. If the
■Diagnostic Timing
• Always same error code is displayed again, the cause is
1000 a hardware failure of the CPU module. (Please
[CPU UNIT DOWN] consult your local Mitsubishi representative,
Runaway or failure of the CPU module
explaining a detailed description of the
• Malfunctioning due to noise or other reason
problem.)
• Hardware failure
■Collateral information LCPU
• Common Information:-
• Individual Information: Failure information
■Diagnostic Timing
• Always
[MAIN CPU DOWN]
Runaway or failure of the CPU module
• Take noise reduction measures. RUN:
• Malfunctioning due to noise or other reason
• Reset the CPU module and run it again. If the Off
• Hardware failure
same error code is displayed again, the cause is ERR.:
• The devices outside the range was accessed
a hardware failure of the CPU module. (Please Flicker
even though device checks are prohibited
consult your local Mitsubishi representative,
(SM237 is on). (This error occurs only when any
explaining a detailed description of the CPU Status: QCPU
of the BMOV, FMOV, or DFMOV instructions is
problem.) Stop
executed. (Universal model QCPU only))
• Check the devices specified by BMOV, FMOV,
■Collateral information
and DFMOV instructions and correct the device
• Common Information:-
settings.
• Individual Information:-
• (Universal model QCPU only)
■Diagnostic Timing
• Always
1001
[CPU UNIT DOWN]
Runaway or failure of the CPU module
• Malfunctioning due to noise or other reason • Take noise reduction measures.
• Hardware failure • Reset the CPU module and run it again. If the
• The devices outside the range was accessed same error code is displayed again, the cause is
even though device checks are prohibited a hardware failure of the CPU module. (Please
(SM237 is on). (This error occurs only when any consult your local Mitsubishi representative,
LCPU
of the BMOV, FMOV, or DFMOV instruction is explaining a detailed description of the
executed.) problem.)
■Collateral information • Check the devices specified by BMOV, FMOV,
• Common Information:- or DFMOV instruction, and correct the device
• Individual Information: Failure information settings.
■Diagnostic Timing
• Always

12-4
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
[MAIN CPU DOWN]
Runaway or failure of the CPU module 1
• Malfunctioning due to noise or other reason
• Hardware failure
■Collateral information QCPU
• Common Information:-
• Individual Information:-
2
■Diagnostic Timing
• Always
1002
[CPU UNIT DOWN]
Runaway or failure of the CPU module
3
• Malfunctioning due to noise or other reason
• Hardware failure
■Collateral information
• Common Information:-
LCPU
12
• Individual Information: Failure information
• Diagnostic Timing
• Always
[MAIN CPU DOWN] 6
Runaway or failure of the CPU module
• Malfunctioning due to noise or other reason
• Hardware failure
■Collateral information QCPU 6
• Common Information:-
• Take noise reduction measures. RUN:
• Individual Information:-
• Reset the CPU module and run it again. If the Off
■Diagnostic Timing

1003
• Always same error code is displayed again, the cause is
a hardware failure of the CPU module. (Please
ERR.:
Flicker 7
[CPU UNIT DOWN]
consult your local Mitsubishi representative,
Runaway or failure of the CPU module
explaining a detailed description of the CPU Status:
• Malfunctioning due to noise or other reason
problem.) Stop
• Hardware failure
■Collateral information LCPU
8
• Common Information:-
• Individual Information: Failure information
• Diagnostic Timing
• Always
[MAIN CPU DOWN]
Runaway or failure of the CPU module
• Malfunctioning due to noise or other reason

12.1.3 Error code list (1000 to 1999)

12.1 Error Code List
• Hardware failure
■Collateral information QCPU
• Common Information:-
• Individual Information:-
■Diagnostic Timing
• Always
1004
[CPU UNIT DOWN]
Runaway or failure of the CPU module
• Malfunctioning due to noise or other reason
• Hardware failure
■Collateral information LCPU
• Common Information:-
• Individual Information: Failure information
• Diagnostic Timing
• Always

12-5
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
[MAIN CPU DOWN]
Runaway or failure of the CPU module • Take noise reduction measures.
• Malfunctioning due to noise or other reason • Reset the CPU module and run it again. If the
• Hardware failure same error code is displayed again, the cause is
■Collateral information a hardware failure of the CPU module. (Please QCPU
• Common Information:- consult your local Mitsubishi representative,
• Individual Information:- explaining a detailed description of the
■Diagnostic Timing problem.)
• Always
[MAIN CPU DOWN]
Boot operation was performed in the transfer
destination without formatting.
• Before performing boot operation by the Qn(H)
■Collateral information
1005 parameter, select "Clear program memory" to QnPH
• Common Information:-
clear the program memory. QnPRH
• Individual Information:-
■Diagnostic Timing
• At power-on
[CPU UNIT DOWN]
Runaway or failure of the CPU module
• Malfunctioning due to noise or other reason
• Hardware failure
■Collateral information LCPU
• Common Information:-
• Individual Information: Failure information RUN:
• Diagnostic Timing Off
• Always ERR.:
[MAIN CPU DOWN] Flicker
Runaway or failure of the CPU module
• Malfunctioning due to noise or other reason CPU Status:
• Hardware failure Stop
■Collateral information QCPU
• Common Information:-
• Take noise reduction measures.
• Individual Information:-
• Reset the CPU module and run it again. If the
■Diagnostic Timing
• Always same error code is displayed again, the cause is
1006 a hardware failure of the CPU module. (Please
[CPU UNIT DOWN] consult your local Mitsubishi representative,
Runaway or failure of the CPU module
explaining a detailed description of the
• Malfunctioning due to noise or other reason
problem.)
• Hardware failure
■Collateral information LCPU
• Common Information:-
• Individual Information: Failure information
• Diagnostic Timing
• Always
1007 [MAIN CPU DOWN]
Runaway or failure of the CPU module
• Malfunctioning due to noise or other reason
• Hardware failure Qn(H)
■Collateral information QnPH
1008 • Common Information:- QnPRH
• Individual Information:-
■Diagnostic Timing
• Always

12-6
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
[MAIN CPU DOWN]
• The power supply module detected an incorrect 1
power waveform.
• When using the redundant base unit, the • Correct the voltage waveform applied to the
redundant power supply module failure in both power supply module.
systems and/or the redundant base unit failure • Reset the CPU module and run it again. If the
same error code is detected again, the cause is
Q00J/Q00/Q01*8 2
are detected. Qn(H)*10
• The voltage waveform that is outside the a failure of the power supply module, CPU QnPH
specification was applied to the power supply module, main base unit, extension base unit, or QnPRH
module.
■Collateral information
extension cable. (Please consult your local
Mitsubishi representative, explaining a detailed
QnU
3
• Common Information:- description of the problem.)
• Individual Information:-
1009
■Diagnostic Timing
• Always 12
[CPU UNIT DOWN]
• A failure was detected on the power supply
• Correct the voltage waveform applied to the
module or CPU module.
• The voltage waveform that is outside the
power supply module.
• Reset the CPU module and run it again.
6
specification was applied to the power supply
• If the same error code is displayed again, the
module. LCPU
cause is a hardware failure of the power supply
■Collateral information
• Common Information:-
• Individual Information: Failure information
module or CPU module. (Please consult your
local Mitsubishi representative, explaining a
RUN:
Off 6
detailed description of the problem.) ERR.:
• Diagnostic Timing
Flicker
• Always
[END NOT EXECUTE]
Entire program was executed without the
CPU Status: 7
Stop
execution of an END instruction.
• When the END instruction is executed it is read
as another instruction code, e.g. due to noise.
• The END instruction has been changed to QCPU
8
1010
another instruction code somehow. LCPU
■Collateral information
• Common Information:-
• Take noise reduction measures.
• Individual Information:-
• Reset the CPU module and run it again. If the
■Diagnostic Timing
• When an END instruction executed same error code is displayed again, the cause is
a hardware failure of the CPU module. (Please
[SFCP. END ERROR] consult your local Mitsubishi representative,

12.1.3 Error code list (1000 to 1999)

12.1 Error Code List
The SFC program cannot be normally terminated
explaining a detailed description of the
due to noise or other reason.
problem.)
• The SFC program cannot be normally
terminated due to noise or any similar cause. Q00J/Q00/Q01*8
• The SFC program cannot be normally QnPH
1020
terminated for any other reason. QnU
■Collateral information LCPU
• Common Information:-
• Individual Information:-
■Diagnostic Timing
• When SFC program is executed

12-7
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
[MAIN CPU DOWN]
Runaway or failure of the CPU module
• Malfunction due to noise etc.
• Hardware failure
■Collateral information QnU
• Common Information:-
• Individual Information:- • Take noise reduction measures.
■Diagnostic Timing • Reset the CPU module and run it again. If the
• Always same error code is displayed again, the cause is
1035
[CPU UNIT DOWN] a failure of the CPU module. (Please consult
Runaway or failure of the CPU module your local Mitsubishi representative, explaining
• Malfunction due to noise etc. a detailed description of the problem.)
• Hardware failure
■Collateral information LCPU
• Common Information:-
• Individual Information: Failure information
• Diagnostic Timing
• Always
1040 [CPU UNIT DOWN]
Runaway or failure of the CPU module (built-in I/
1041
O). • Take noise reduction measures. RUN:
• Malfunction due to noise etc. • Reset the CPU module and run it again. If the Off
• Hardware failure same error code is displayed again, the cause is ERR.:
LCPU
■Collateral information a failure of the CPU module. (Please consult Flicker
1042 • Common Information:- your local Mitsubishi representative, explaining
• Individual Information: Failure information a detailed description of the problem.) CPU Status:
■Diagnostic Timing Stop
• Always
[RAM ERROR]
The sequence program storing program memory
in the CPU module is faulty.
■Collateral information
QCPU
1101 • Common Information:-
LCPU
• Individual Information:-
■Diagnostic Timing • Take noise reduction measures.
• At power-on/At reset/When an END instruction • Reset the CPU module and run it again. If the
executed same error code is displayed again, the cause is
[RAM ERROR] a hardware failure of the a CPU module.
• The work area RAM in the CPU module is (Please consult your local Mitsubishi
faulty. representative, explaining a detailed description
• The standard RAM in the CPU module is faulty. of the problem.)
■Collateral information QCPU
1102
• Common Information:- LCPU
• Individual Information:-
■Diagnostic Timing
• At power-on/At reset/When an END instruction
executed
[RAM ERROR]
The device memory in the CPU module is faulty.
■Collateral information
• Common Information:- QCPU
• Individual Information:- LCPU
• Take noise reduction measures.
■Diagnostic Timing
• At power-on/At reset/When an END instruction • When indexing is performed, check the value of
RUN:
executed index register to see if it is within the device
Off
range.
[RAM ERROR] ERR.:
• Reset the CPU module and run it again. If the
1103 • The device memory in the CPU module is faulty. Flicker
same error code is displayed again, the cause is
• The device out of range is accessed due to
a hardware failure of the a CPU module.
indexing, and the device for system is CPU Status:
(Please consult your local Mitsubishi
overwritten. Stop Qn(H)*13
representative, explaining a detailed description
■Collateral information QnPH*13
of the problem.)
• Common Information:- QnPRH*15
• Individual information:-
■Diagnostic Timing
• At power-on/At reset/When an END instruction
executed

12-8
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
[RAM ERROR]
The address RAM in the CPU module is faulty.
Q00J/Q00/Q01
1
■Collateral information
Qn(H)
1104 • Common Information:-
QnPH
• Individual Information:-
2
QnPRH
■Diagnostic Timing
• At power-on/At reset
[RAM ERROR] • Take noise reduction measures.
The CPU memory in the CPU module is faulty.
• Reset the CPU module and run it again. If the
■Collateral information
• Common Information:-
same error code is displayed again, the cause is Q00J/Q00/Q01 3
a hardware failure of the CPU module. (Please QnU
• Individual Information:-
consult your local Mitsubishi representative,
■Diagnostic Timing
explaining a detailed description of the
• At power-on/At reset
1105 [RAM ERROR]
problem.) 12
The CPU shared memory in the CPU module is
faulty. Qn(H)*8
■Collateral information QnPH
• Common Information:- QnPRH 6
• Individual Information:- QnU
■Diagnostic Timing
• At power-on/At reset
• Check the battery to see if it is dead or not. If 6
dead, replace the battery.
[RAM ERROR]
• Take noise reduction measures.
The program memory was corrupted due to battery
• Format the program memory, write all files to the
exhaustion.
■Collateral information
PLC, then reset the CPU module, and RUN it Qn(H)
7
1106 again. QnPH*12
• Common Information:-
If the same error code is displayed again, the RUN: QnPRH
• Individual Information:-
cause is a hardware failure of the CPU module. Off
■Diagnostic Timing
• STOP→RUN/When an END instruction executed (Please consult your local Mitsubishi
representative, explaining a detailed description
ERR.:
Flicker
8
of the problem.)
CPU Status:
[RAM ERROR] Stop
1107 The work area RAM in the CPU module is faulty. QnPRH
■Collateral information
• Common Information:-
• Individual Information:-

12.1.3 Error code list (1000 to 1999)

12.1 Error Code List
1108 ■Diagnostic Timing
• At power-on/At reset

[RAM ERROR] Qn(H)*13

The work area RAM in the CPU module is faulty. QnPH*13
■Collateral information QnPRH*15
1109 • Common Information:-
• Individual Information:-
■Diagnostic Timing The cause is a hardware failure of the CPU
• Always module. (Please consult your local Mitsubishi
[TRK. CIR. ERROR] representative, explaining a detailed description of
A fault was detected by the initial check of the the problem.)
tracking hardware.
■Collateral information
1110
• Common Information:-
• Individual Information:-
■Diagnostic Timing
• At power-on/At reset QnPRH
[TRK. CIR. ERROR]
A tracking hardware fault was detected.
■Collateral information
1111 • Common Information:-
• Individual Information:-
■Diagnostic Timing
• At power-on/At reset

12-9
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU

[TRK. CIR. ERROR]

• A tracking hardware fault was detected during
running.
• Start after checking that the tracking cable is
1112 • The tracking cable was disconnected and
connected.
reinserted without the standby system being
• If the same error code is displayed again, the
powered off or reset.
cause is the hardware failure of the tracking
• The tracking cable is not secured by the
cable or CPU module. (Please consult your local
connector fixing screws.
Mitsubishi representative, explaining a detailed
• The error occurred at a startup since the
description of the problem.)
redundant system startup procedure was not
• Confirm the redundant system startup
followed.
procedure, and execute a startup again. For
■Collateral information
details, refer to the QnPRHCPU User's Manual
1113 • Common Information:-
(Redundant System).
• Individual Information:-
■Diagnostic Timing
• During running

[TRK. CIR. ERROR]

A fault was detected by the initial check of the
tracking hardware. The cause is a hardware failure of the CPU
QnPRH
■Collateral information module. (Please consult your local Mitsubishi
1115
• Common Information:- representative, explaining a detailed description of
• Individual Information:- the problem.)
■Diagnostic Timing
• At power-on/At reset
[TRK. CIR. ERROR]
• A tracking hardware fault was detected during
running.
• The tracking cable was disconnected and • Start after checking that the tracking cable is
RUN:
reinserted without the standby system being connected. If the same error code is displayed
Off
powered off or reset. again, the cause is a hardware failure of the
ERR.:
• The tracking cable is not secured by the tracking cable or CPU module. (Please consult
Flicker
connector fixing screws. your local Mitsubishi representative, explaining
1116
• The error occurred at a startup since the a detailed description of the problem.)
CPU Status:
redundant system startup procedure was not • Confirm the redundant system startup
Stop
followed. procedure, and execute a startup again. For
■Collateral information details, refer to the QnPRHCPU User's Manual
• Common Information:- (Redundant System).
• Individual Information:-
■Diagnostic Timing
• During running
[RAM ERROR]
The memory of the CPU module in the Multiple • Take noise reduction measures.
CPU high speed transmission area is faulty. Reset the CPU module and run it again. If the
■Collateral information same error code is displayed again, the cause is a
1150 QnU*20
• Common Information:- hardware failure of the CPU module. (Please
• Individual Information:- consult your local Mitsubishi representative,
■Diagnostic Timing explaining a detailed description of the problem.)
• At power-on/At reset

[RAM ERROR] • Take noise reduction measures.

The program memory in the CPU module is Format the program memory, write all files to the
overwritten. CPU module, and run it again.
■Collateral information If the same error code is displayed again, the
1160
• Common Information:- cause is a hardware failure of the CPU module.
• Individual Information:- (Please consult your local Mitsubishi
■Diagnostic Timing representative, explaining a detailed description of
• At program execution the problem.) QnU
[RAM ERROR] LCPU
The data of the device memory built in the CPU Take noise reduction measures.
module is overwritten. If the same error code is displayed again, the
■Collateral information cause is a hardware failure of the CPU module.
1161
• Common Information:- (Please consult your local Mitsubishi
• Individual Information:- representative, explaining a detailed description of
■Diagnostic Timing the problem.)
• Always

12-10
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
• Take noise reduction measures.
• For GX Works2, select "Transfer cache memory 1
to program memory" in the Options dialog box.
[RAM ERROR]
For GX Developer, select "Online change T/C
Data in the program memory of the CPU module
setting value change program memory transfer
were overwritten.
■Collateral information
settings" in the Options dialog box. 2
1163 Format the program memory, write all files to the QnU
• Common Information:-
CPU module, and run it again.
• Individual Information:-
If the same error code is displayed again, the
■Diagnostic Timing
• When instruction executed cause is a hardware failure of the CPU module.
(Please consult your local Mitsubishi
3
representative, explaining a detailed description of
the problem.)
[RAM ERROR]
The destruction of the data stored in the standard
12
RAM is detected.
■Collateral information QnU*22
1164
• Common Information:-
• Individual Information:-
L26CPU-BT
6
■Diagnostic Timing
• When instruction executed
[RAM ERROR]
The RAM of the CPU module (built-in I/O) is faulty. 6
■Collateral information
1170 • Common Information:-
Take noise reduction measures.
• Common Information: Failure information
■Diagnostic Timing
• At power-on/At reset
If the same error code is displayed again, the
cause is a hardware failure of the CPU module.
RUN:
Off 7
(Please consult your local Mitsubishi ERR.: LCPU
[RAM ERROR] Flicker
representative, explaining a detailed description of
The RAM of the CPU module (built-in I/O) is faulty.
the problem.)

1171
■Collateral information
• Common Information:-
CPU Status: 8
Stop
• Common Information: Failure information
• Diagnostic Timing
• Always
[RAM ERROR]
The RAM of the CPU module (built-in I/O) is faulty.
■Collateral information
1172 • Common Information:- LCPU

12.1.3 Error code list (1000 to 1999)

12.1 Error Code List
• Individual information: Failure information
■Diagnostic Timing
• At power-on/At reset
[OPE. CIRCUIT ERR.]
The operation circuit for index modification in the
CPU module does not operate normally.
■Collateral information
1200
• Common Information:-
• Individual Information:-
■Diagnostic Timing The cause is a hardware failure of the CPU
• At power-on/At reset module. (Please consult your local Mitsubishi QCPU
[OPE. CIRCUIT ERR.] representative, explaining a detailed description of LCPU
The hardware (logic) in the CPU module does not the problem.)
operate normally.
■Collateral information
1201
• Common Information:-
• Individual Information:-
■Diagnostic Timing
• At power-on/At reset

12-11
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
[OPE. CIRCUIT ERR.]
The operation circuit for sequence processing in
the CPU module does not operate normally.
■Collateral information QCPU
1202
• Common Information:- LCPU
• Individual Information:-
■Diagnostic Timing
• At power-on/At reset
[OPE. CIRCUIT ERR.]
The operation circuit for index modification in the
CPU module does not operate normally.
■Collateral information
1203
• Common Information:-
RUN:
• Individual Information:-
Off
■Diagnostic Timing The cause is a hardware failure of the CPU
• When an END instruction executed ERR.:
module. (Please consult your local Mitsubishi
Flicker QnPRH
[OPE. CIRCUIT ERR.] representative, explaining a detailed description of
The hardware (logic) in the CPU module does not the problem.)
CPU Status:
operate normally.
Stop
■Collateral information
1204
• Common Information:-
• Individual Information:-
■Diagnostic Timing
• When an END instruction executed
[OPE. CIRCUIT ERR.]
The operation circuit for sequence processing in
the CPU module does not operate normally.
■Collateral information
1205 QnPRH
• Common Information:-
• Individual Information:-
■Diagnostic Timing
• When an END instruction executed
• Check FUSE. LED of the output modules and
[FUSE BREAK OFF]
replace the module whose LED is lit.
There is an output module with a blown fuse.
A blown fuse can also be located with the
■Collateral information
programming tool. Qn(H)
• Common Information: Module No. (Slot No.)
Check SD1300 to SD1331 to ensure that the bit QnPH
[For Remote I/O network]
for the module with a blown fuse is "1". QnPRH
• Network No./Station No.
• When a GOT is bus-connected to the main base RUN: QnU
• Individual Information:-
unit or extension base unit, check the Off/On
■Diagnostic Timing
connection status of the extension cable and the ERR.:
• Always
earth status of the GOT. Flicker/On
1300
[FUSE BREAK OFF]
There is an output module with a blown fuse. CPU Status:
■Collateral information Check ERR. LED of the output modules and Stop/
• Common Information: Module No. (Slot No.) replace the module whose LED is lit. Continue*1
• [For Remote I/O (A blown fuse can be identified with the
Q00J/Q00/Q01
• network]Network No./ programming tool. Check SD130 to SD137 to
• Station No. ensure that the bit for the module with a blown
• Individual Information:- fuse is "1".)
■Diagnostic Timing
• Always

12-12
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
[I/O INT. ERROR]
An interruption has occurred although there is no
Any of the mounted modules is experiencing a
1
interrupt module.
hardware fault. Therefore, check the mounted
■Collateral information QCPU
modules and change the faulty module. (Please
• Common Information:-
2
consult your local Mitsubishi representative,
• Individual Information:- RUN:
explaining a detailed description of the problem.)
■Diagnostic Timing Off
• During interrupt ERR.:
1310 [I/O INT. ERROR] Flicker
An interruption occurred although none of the
modules can issue an interruption (including an
• Reset the CPU module and run it again. If the
same error code is displayed again, the cause is CPU Status:
3
interruption from the built-in I/O) a hardware failure of the CPU module, I/O Stop
■Collateral information module, intelligent function module, or END LCPU

12
• Common Information:- cover. (Please consult your local Mitsubishi
• Individual Information:- representative, explaining a detailed description
■Diagnostic Timing of the problem.)
• During interrupt

6
[I/O INT. ERROR]
An interrupt request from other than the interrupt
module was detected.
■Collateral information Take action so that an interrupt will not be issued Q00J/Q00/Q01*8
• Common Information:- from other than the interrupt module. QnU
• Individual Information:-
■Diagnostic Timing
6
• During interrupt
• Correct the interrupt pointer setting in the PLC
system setting of the PLC Parameter dialog box.
• Take measures not to issue an interruption from
7
the modules where the interrupt pointer setting
is not configured in the PLC system setting of Q00J/Q00/Q01*7
the PLC Parameter dialog box.
• Correct the interrupt setting of the network
QnPRH
QnU
8
parameter.
• Correct the interrupt setting of the intelligent
function module buffer memory.
1311 [I/O INT. ERROR] • Correct the basic program of the QD51.
An interrupt request was detected from the module RUN:
• Correct the interrupt pointer setting in the PLC
for which Interrupt Pointer Setting has not been Off
System tab of the PLC Parameter dialog box.
configured in the PLC Parameter dialog box. ERR.:
• Take measures not to issue an interruption from

12.1.3 Error code list (1000 to 1999)

12.1 Error Code List
■Collateral information Flicker
• Common Information:- the modules where the interrupt pointer setting
• Individual Information:- is not configured in the PLC System tab of the
CPU Status:
■Diagnostic Timing PLC Parameter dialog box.
Stop
• During interrupt • Correct the Interrupt Setting of the network
parameter.
• Correct the interrupt setting of the intelligent LCPU
function module buffer memory.
• Reset the CPU module and run it again. If the
same error code is displayed again, the cause is
a hardware failure of the CPU module, I/O
module, intelligent function module, or END
cover. (Please consult your local Mitsubishi
representative, explaining a detailed description
of the problem.)

[LAN CTRL. DOWN]

1320 The H/W self-diagnostics detected a LAN
controller failure.
The cause is a failure of the CPU module. (Please
■Collateral information QnU*21
consult your local Mitsubishi representative,
• Common Information:- LCPU
explaining a detailed description of the problem.)
• Individual Information:-
1321 ■Diagnostic Timing
• At power-on/At reset

12-13
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
[SP. UNIT DOWN]
• There was no response from the intelligent
function module/special function module in the
initial processing. When the unsupported module is mounted,
• The size of the buffer memory of the intelligent remove it.
function module/special function module is If the corresponding module is supported, this
invalid. suggests the intelligent function module/special
QCPU
• The unsupported module is mounted. function module, CPU module and/or base unit is
■Collateral information expecting a hardware fault (Please consult your
• Common Information: Module No. (Slot No.) local Mitsubishi representative, explaining a
• Individual Information:- detailed description of the problem.)
■Diagnostic Timing
• At power-on/At reset/When intelligent function
module is accessed

1401 [SP. UNIT DOWN]

• There was no response from the intelligent
function module in the initial processing.
• The buffer memory size of the intelligent function
module is invalid.
• Reset the CPU module and run it again. If the
• There was no response form the intelligent
same error code is displayed again, the cause is
function module.
a hardware failure of the CPU module, I/O RUN:
• The start I/O No. of the targeted intelligent
module, intelligent function module, or END Off/On LCPU
function module is stored as a common
cover.(Please consult your local Mitsubishi ERR.:
information upon error.
representative, explaining a detailed description Flicker/On
■Collateral information
of the problem.)
• Common information: Module No. (Slot No.)
CPU Status:
• Individual Information:-
Stop/
■Diagnostic Timing
• At power-on/At reset/When intelligent function Continue*6
module is accessed
[SP. UNIT DOWN]
The intelligent function module/special function
module was accessed in the program, but there
The cause is a hardware failure of the intelligent
was no response.
function module/special function module, CPU
■Collateral information
module, or base unit. (Please consult your local QCPU
• Common Information: Module No. (Slot No.)
Mitsubishi representative, explaining a detailed
• Individual Information: Program error location
description of the problem.)
■Diagnostic Timing
• When an intelligent function module access
1402 instruction is executed
[SP. UNIT DOWN]
The intelligent function module was accessed by • Reset the CPU module and run it again. If the
the program, but there was no response. same error code is displayed again, the cause is
■Collateral information a hardware failure of the CPU module, I/O
• Common information: Module No. (Slot No.) module, intelligent function module, or END LCPU
• Individual information: Program error location cover. (Please consult your local Mitsubishi
■Diagnostic Timing representative, explaining a detailed description
• When an intelligent function module access of the problem.)
instruction is executed

12-14
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
When the unsupported module is mounted,
[SP. UNIT DOWN]
• The unsupported module is mounted. remove it. If the module supports the feature, the 1
■Collateral information cause is a hardware failure of the intelligent
• Common Information: Module No. (Slot No.) function module, special function module, CPU
• Individual Information:- module, or base unit. (Please consult your local
■Diagnostic Timing
• When an END instruction executed
Mitsubishi representative, explaining a detailed 2
description of the problem.)
[SP. UNIT DOWN]
• There was no response from the intelligent
function module/special function module when 3
the END instruction is executed. QCPU
• An error is detected at the intelligent function
module/special function module. The cause is a failure of the CPU module, base
• The I/O module (intelligent function module/
special function module) is nearly removed,
unit, or the intelligent function module/special
function module in the access destination. (Please
12
RUN:
completely removed, or mounted during consult your local Mitsubishi representative, Off/On
running. explaining a detailed description of the problem.) ERR.:

1403
■Collateral information
• Common Information: Module No. (Slot No.)
Flicker/On
6
• Individual Information:- CPU Status:
■Diagnostic Timing Stop/
• Always
[SP. UNIT DOWN]
Continue*6
6
• There was no response from the intelligent
function module when the END instruction is
executed.
• An error is detected in the intelligent function
• Reset the CPU module and run it again. If the 7
module.
same error code is displayed again, the cause is
• The I/O module (intelligent function module/
a hardware failure of the CPU module, I/O
special function module) is nearly removed, LCPU
module, or END cover. (Please consult your
completely removed, or mounted during
running.
local Mitsubishi representative, explaining a 8
detailed description of the problem.)
■Collateral information
• Common Information: Module No. (Slot No.)
• Individual Information:-
■Diagnostic Timing
• Always
[CONTROL-BUS. ERR.]
When performing a parameter I/O allocation the

12.1.3 Error code list (1000 to 1999)

12.1 Error Code List
intelligent function module/special function module
could not be accessed during initial
communications. (On error occurring, the head I/O
number of the corresponding intelligent function
1411 module/special function module is stored in the
common information.)
■Collateral information
Reset the CPU module and run it again. If the RUN:
• Common Information: Module No. (Slot No.)
same error code is displayed again, the cause is a Off
• Individual Information:-
failure of the intelligent function module/special ERR.:
■Diagnostic Timing
• At power-on/At reset function module, CPU module, or base unit. Flicker QCPU
(Please consult your local Mitsubishi
[CONTROL-BUS. ERR.] representative, explaining a detailed description of CPU Status:
The FROM/TO instruction is not executable, due to
the problem.) Stop
a control bus error with the intelligent function
module/special function module. (On error
occurring, the program error location is stored in
1412 the individual information.)
■Collateral information
• Common Information: Module No. (Slot No.)
• Individual Information: Program error location
■Diagnostic Timing
• During execution of FROM/TO instruction set

12-15
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
• Remove the CPU module from the main base
[CONTROL-BUS. ERR.]
unit if it does not support a multiple CPU system
In a multiple CPU system, a CPU module
configuration. Alternatively, replace the CPU
incompatible with the multiple CPU system is
module that does not support a multiple system
mounted. Q00J/Q00/Q01 *8
configuration with the one that does.
■Collateral information Qn(H)*8
• The cause is a failure of the intelligent function
• Common Information:- QnPH
module, CPU module, or base unit. (Please
• Individual Information:-
consult your local Mitsubishi representative,
■Diagnostic Timing
explaining a detailed description of the
• Always
1413 problem.)
[CONTROL-BUS. ERR.]
An error is detected on the system bus.
Reset the CPU module and run it again. If the
• Self-diagnosis error of the system bus.
same error code is displayed again, the cause is a
• Self-diagnosis error of the CPU module
failure of the intelligent function module, CPU
■Collateral information QCPU
module, or base unit. (Please consult your local
• Common Information:-
Mitsubishi representative, explaining a detailed
• Individual Information:-
description of the problem.)
■Diagnostic Timing
• Always
• Remove the CPU module from the main base
[CONTROL-BUS. ERR.]
unit if it does not support the multiple CPU
• Fault of a loaded module was detected.
system configuration. Or replace the CPU
• In a multiple CPU system, a CPU module
module that does not support a multiple system
incompatible with the multiple CPU system is Q00J/Q00/Q01*8
configuration with the one that does. Reset the
mounted. RUN: Qn(H)*8
CPU module and run it again. If the same error
■Collateral information Off QnPH
code is displayed again, the cause is a failure of
• Common Information: Module No. (Slot No.) ERR.: QnU
the intelligent function module, CPU module, or
• Individual Information:- Flicker
base unit. (Please consult your local Mitsubishi
1414 ■Diagnostic Timing
representative, explaining a detailed description
• Always CPU Status:
of the problem.)
Stop
[CONTROL-BUS. ERR.]
An error is detected on the system bus. Q00J/Q00/Q01*8
■Collateral information Qn(H)
• Common Information: Module No. (Slot No.) QnPH
• Individual Information:- QnPRH
■Diagnostic Timing QnU
• Always
[CONTROL-BUS. ERR.]
Fault of the main or extension base unit was
Reset the CPU module and run it again. If the Q00J/Q00/Q01
detected.
same error code is displayed again, the cause is a Qn(H)*8
■Collateral information
failure of the intelligent function module, CPU QnPH
• Common Information: Module No. (Slot No.)
module, or base unit. QnPRH
• Individual Information:-
(Please consult your local Mitsubishi QnU
■Diagnostic Timing
representative, explaining a detailed description of
• When an END instruction executed
the problem.)
1415 [CONTROL-BUS. ERR.]
Fault of the main or extension base unit was
detected.
■Collateral information
Qn(H)*13
• Common Information: Module No. (Slot No.)
• Individual Information:- QnPH*13
■Diagnostic Timing
• At power-ON/At reset/When an END instruction
executed

12-16
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
[CONTROL-BUS. ERR.]
An error was detected on the system bus. 1
■Collateral information Qn(H)*8
• Common Information: Module No. (Slot No.) QnPH
• Individual Information:- QnU
■Diagnostic Timing
• At power-on/At reset
2
1416 [CONTROL-BUS. ERR.]
An error was detected on the system bus in the
Reset the CPU module and run it again.
multiple CPU system.
■Collateral information
If the same error code is displayed again, the Q00CPU*8 3
cause is a failure of the intelligent function module, Q01CPU*8
• Common Information: Module No. (Slot No.)
CPU module, or base unit. (Please consult your QnU
• Individual Information:-
local Mitsubishi representative, explaining a
■Diagnostic Timing
• At power-on/At reset
detailed description of the problem.) 12
[CONTROL-BUS. ERR.]
A reset signal error was detected on the system
bus.

1417
■Collateral information
QnPRH
6
• Common Information:-
• Individual Information:-
■Diagnostic Timing
• Always
6
[CONTROL-BUS.ERR.]
In the redundant system, the control system
Reset the CPU module and run it again. If the RUN:
cannot access the extension base unit because it
same error code is displayed again, the cause is a

1418
has failed to acquire an access right.
■Collateral information
hardware failure of the CPU module, Q6†WRB, or
Off
ERR.:
QnPRH*15
7
extension cable. (Please consult your local Flicker
• Common Information:-
Mitsubishi representative, explaining a detailed
• Individual Information:-
description of the problem.) CPU Status:
■Diagnostic Timing
• At power-ON/At reset/At Switching execution Stop 8
[MULTI-C.BUS ERR.]
The error of host CPU is detected in the Multiple
Reset the CPU module and run it again. If the
CPU high speed bus.
same error code is displayed again, the cause is a
■Collateral information
1430 failure of the CPU module. (Please consult your
• Common Information:-
local Mitsubishi representative, explaining a
• Individual Information:-
detailed description of the problem.)
■Diagnostic Timing

12.1.3 Error code list (1000 to 1999)

12.1 Error Code List
• At power-on/At reset

[MULTI-C.BUS ERR.] • Take noise reduction measures.

The communication error with other CPU is • Check the main base unit mounting status of the
detected in the Multiple CPU high speed bus. CPU module.
■Collateral information • Reset the CPU module and run it again. If the
1431 QnU*20
• Common Information: Module No. (CPU No.) same error code is displayed again, the cause is
• Individual Information:- a failure of the CPU module. (Please consult
■Diagnostic Timing your local Mitsubishi representative, explaining
• At power-on/At reset a detailed description of the problem.)
[MULTI-C.BUS ERR.]
The communication time out with other CPU is
Reset the CPU module and run it again. If the
detected in the Multiple CPU high speed bus.
same error code is displayed again, the cause is a
■Collateral information
1432 failure of the CPU module. (Please consult your
• Common Information: Module No. (CPU No.)
local Mitsubishi representative, explaining a
• Individual Information:-
detailed description of the problem.)
■Diagnostic Timing
• At power-on/At reset

12-17
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU

[MULTI-C.BUS ERR.] • Take noise reduction measures.

1433 • Check the main base unit mounting status of the
The communication error with other CPU is
detected in the Multiple CPU high speed bus. CPU module.
■Collateral information • Reset the CPU module and run it again. If the
1434
• Common Information: Module No. (CPU No.) same error code is displayed again, the cause is
• Individual Information:- a failure of the CPU module. (Please consult
■Diagnostic Timing your local Mitsubishi representative, explaining
1435
• Always a detailed description of the problem.)

Reset the CPU module and run it again. If the

same error code is displayed again, the cause is a
1436 [MULTI-C.BUS ERR.] failure of the CPU module. (Please consult your
The error of the Multiple CPU high speed main local Mitsubishi representative, explaining a
RUN:
base unit is detected. (The error of the Multiple detailed description of the problem.)
Off
CPU high speed bus is detected.) • Take noise reduction measures. ERR.:
■Collateral information • Check the main base unit mounting status of the Flicker QnU*20
• Common Information:- CPU module.
• Individual Information:- • Reset the CPU module and run it again. If the CPU Status:
1437 ■Diagnostic Timing same error code is displayed again, the cause is Stop
• At power-on/At reset: a failure of the CPU module. (Please consult
your local Mitsubishi representative, explaining
a detailed description of the problem.)
[MULTI-C.BUS ERR.]
An error of the multiple CPU high speed main base
unit was detected. (An error of the multiple CPU Reset the CPU module and run it again. If the
high speed bus was detected.) same error code is displayed again, the cause is a
1439 ■Collateral information failure of the CPU module. (Please consult your
• Common Information:- local Mitsubishi representative, explaining a
• Individual Information:- detailed description of the problem.)
■Diagnostic Timing
• At power-on/At reset:
[AC/DC DOWN]
• A momentary power supply interruption has RUN:
occurred. On
• The power supply went off. ERR.:
QCPU
1500 ■Collateral information Check the power supply. Off
LCPU
• Common Information:-
• Individual Information:- CPU Status:
■Diagnostic Timing Continue
• Always
[SINGLE PS. DOWN]
The power supply voltage of either of redundant
power supply modules on the redundant base unit
Qn(H)*10
dropped. Check the power supplied to the redundant power
QnPH*10
1510 ■Collateral information supply modules mounted on the redundant base
QnPRH
• Common Information: Base No./Power supply No. unit. RUN:
• Individual Information:- On QnU*17
■Diagnostic Timing ERR.:
• Always On
[SINGLE PS. ERROR]
On the redundant base unit, the one damaged CPU Status:
redundant power supply module was detected. The cause is a hardware failure of the redundant Continue Qn(H)*10
■Collateral information power supply module. (Please consult your local QnPH*10
1520
• Common Information: Base No./Power supply No. Mitsubishi representative, explaining a detailed QnPRH
• Individual Information:- description of the problem.) QnU*17
■Diagnostic Timing
• Always

12-18
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU

[BATTERY ERROR*3]
• The battery voltage in the CPU module has 1
dropped below stipulated level.
• Change the battery.
• The lead connector of the CPU module battery
• Engage the battery connector when a program
is not connected.
1600
• The lead connector of the CPU module battery
memory, standard RAM, or the back-up power
function is used.
QCPU
LCPU
2
is not securely engaged.
• Check the lead connector of the CPU module RUN:
■Collateral information
for looseness. Firmly engage the connector if it On
• Common Information: Drive Name
is loose. ERR.:
• Individual Information:-
■Diagnostic Timing
Off 3
• Always
CPU Status
[BATTERY ERROR*3] Continue
Voltage of the battery on memory card has
dropped below stipulated level. Qn(H)
12
■Collateral information QnPH
1601 Change the battery.
• Common Information: Drive Name QnPRH
• Individual Information:-
■Diagnostic Timing
QnU*19
6
• Always
[FLASH ROM ERROR]
The number of writing to flash ROM (standard
ROM and system securement area) exceeds
RUN:
On
6
100,000 times.
ERR.:
(Number of writings > 100,000 times) QnU
1610 Change the CPU module. On
■Collateral information LCPU
• Common Information:-
CPU Status:
7
• Individual Information:-
Continue
■Diagnostic Timing
• When writing to ROM
[BUS TIMEOUT ERR.]
An error was detected on the system bus.
8
• Self-diagnosis error of the system bus
• Self-diagnosis error of the CPU module
1700 ■Collateral information
• Common Information:-
Reset the CPU module and run it again. If the
• Individual Information:-
same error code is displayed again, the cause is a
■Diagnostic Timing
• Always hardware failure of the CPU module, I/O module,

12.1.3 Error code list (1000 to 1999)

12.1 Error Code List
intelligent function module, or END cover. (Please
[UNIT BUS ERROR] consult your local Mitsubishi representative,
• An error was detected on the system bus.
explaining a detailed description of the problem.)
• An error was detected in the connected module.
■Collateral information
1710 RUN:
• Common Information: Module No. (Slot No.)
Off
• Individual Information:-
ERR.:
■Diagnostic Timing
Flicker LCPU
• Always
[END COVER ERR.] CPU Status:
A failure was detected on the END cover.
Stop
■Collateral information
• Common Information:-
1720
• Individual Information:- • Replace the END cover.
■Diagnostic Timing • Reset the CPU module and run it again. If the
• At power-ON/At reset/When an END instruction same error code is displayed again, the cause is
executed a failure of the intelligent function module, CPU
[SYSTEM RST ERR.] module, or END cover. (Please consult your
An error was detected in the system bus. local Mitsubishi representative, explaining a
■Collateral information detailed description of the problem.)
1730 • Common Information:-
• Individual Information:-
■Diagnostic Timing
• At power-ON/At reset

12-19
 *1 CPU operations when an error occurred can determined with a parameter. (LED indication varies according to the status
of the CPU module)
*3 The BAT. LED turns on or flashes if the BATTERY ERROR occurs.
*6 Intelligent function module operations when an error occurred can be selected with a parameter from either to stop or
continue.
*7 This applies when the function version is A or later.
*8 This applies when the function version is B or later.
*10 This applies when the first five digits of the serial number is "04101" or later.
*12 This applies when the first five digits of the serial number is "07032" or later.
*13 This applies when the first five digits of the serial number is "08032" or later.
*15 This applies when the first five digits of the serial number is "09012" or later.
*17 This applies when the first five digits of the serial number is "10042" or later.
*19 This applies to the Universal model QCPU except for the Q00UJCPU, Q00UCPU, and Q01UCPU.
*20 This applies to the Universal model QCPU except for the Q00UJCPU, Q00UCPU, Q01UCPU, and Q02UCPU.
*21 This applies to the Built-in Ethernet port QCPU.
*22 This applies to the Q10UD(E)HCPU, Q13UD(E)HCPU, Q20UD(E)HCPU, and Q26UD(E)HCPU.

12-20
 12.1.4 Error code list (2000 to 2999)
1
The following shows the error messages from the error code 2000 to 2999, the contents and
causes of the errors, and the corrective actions for the errors.
2
Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
[UNIT VERIFY ERR.]
In a multiple CPU system, a CPU module
3
incompatible with the multiple CPU system is
mounted. Replace the CPU module incompatible with the
Qn(H)*8
■Collateral information
• Common information: Module No.(Slot No.)
multiple CPU system with a CPU module
compatible with the multiple CPU system.
QnPH 12
• Individual information:-
■Diagnostic Timing
• When an END instruction executed
[UNIT VERIFY ERR.] 6
The I/O module status is different from the I/O
• Read common information of the error using
module information at power ON.
the programming tool to identify the numeric
• I/O module (or intelligent function module) is not
installed properly or installed on the base unit.
value (module No.). Check the module
corresponding to the value and replace it as
RUN: 6
■Collateral information Off/On
necessary. Q00J/Q00/Q01
• Common information: Module No. (Slot No.) [For ERR.:
• Monitor SD150 to SD157 using the
Remote I/O network] Flicker/On
programming tool to identify the module whose
7
2000 • Network No./Station No.
data bit it is "1". Then check the module and
• Individual information:- CPU Status:
replace it as necessary.
■Diagnostic Timing Stop/
• When an END instruction executed
Continue*1

[UNIT VERIFY ERR.]

• Read common information of the error using
the programming tool to identify the numeric
8
I/O module information power ON is changed. value (module No.). Check the module
• I/O module (or intelligent function module/ corresponding to the value and replace it as
special function module) not installed properly or necessary.
Qn(H)
installed on the base unit. • Monitor SD1400 to SD1431 with the
QnPH
■Collateral information programming tool to identify the module whose
QnPRH
• Common information: Module No. (Slot No.)[For data bit it is "1". Then check the module and
QnU
Remote I/O network]Network No./Station No. replace it as necessary.

12.1.4 Error code list (2000 to 2999)

12.1 Error Code List
• Individual information:- • When a GOT is bus-connected to the main
■Diagnostic Timing base unit or extension base unit, check the
• Always connection status of the extension cable and
the grounding status of the GOT.
[UNIT VERIFY ERR.] RUN:
During operation, a module was mounted on the
Off/On
slot where the empty setting of the CPU module
ERR.:
was made. During operation, do not mount a module on the
Flicker/On Q00J/Q00/Q01*8
2001 ■Collateral information slot where the empty setting of the CPU module
QnU
• Common information: Module No. (CPU No.) was made.
CPU Status:
• Individual information:-
Stop/
■Diagnostic Timing
• Always Continue*6

[BASE LAY ERROR]

• More than applicable number of extension base
units have been used. RUN:
Q00J/Q00/Q01*8
• When a GOT was bus-connected, the CPU Off
• Use the allowable number of extension base QnPRH
module was reset while the power of the GOT ERR.:
units or less. Q00UJ
2010 was OFF. Flicker
• Power on the programmable controller and Q00UCPU
■Collateral information
GOT again. Q01UCPU
• Common information: Base No. CPU Status:
Q02UCPU
• Individual information:- Stop
■Diagnostic Timing
• At power-on/At reset

12-21
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
[BASE LAY ERROR]
The QA1S6†B, QA6†B, or QA6ADP+A5†B/
A6†B was used as the base unit. Q00J/Q00/Q01*8
■Collateral information Do not use the QA1S6†B, QA6†B, or QnPH
2011
• Common information: Base No. QA6ADP+A5†B/A6†B as the base unit. QnPRH
• Individual information:- QnU
■Diagnostic Timing
• At power-on/At reset
[BASE LAY ERROR]
The GOT is bus-connected to the main base unit
of the redundant system.
The following errors were detected in the
redundant system.
• The base unit other than the Q6†WRB is • Remove the bus connection cable for the GOT
connected to the extension stage No.1. connected to the main base unit.
• The base unit is connected to any one of the • Use the Q6†WRB (fixed to the extension stage
extension stages No.2 to No.7, although the No.1)
Q6†WRB does not exist in the extension stage • Use the redundant CPU compatible with the
No.1. extension base unit for the other system.
• The other system CPU module is incompatible • Do not use the Q5†B, QA1S6†B, QA6†B or
2012
with the extension base unit. QA6ADP+A5†B/A6†B for the base unit.
• The Q5†B, QA1S6†B, QA6†B or • Use the main base unit which has the same
QA6ADP+A5†B/A6†B is connected. number of slots.
• The number of slots of the main base unit for • The cause is a hardware failure of the
both systems is different. Q6†WRB. (Please consult your local
• Information of the Q6†WRB cannot be read Mitsubishi representative, explaining a detailed
correctly. description of the problem.)
■Collateral information
• Common information: Base No.
• Individual information:-
■Diagnostic Timing
• At power-on/At reset RUN: QnPRH*15
[BASE LAY ERROR] Off
Stage number of the Q6†WRB is recognized as ERR.:
other than extension stage No.1 in the redundant Flicker
The cause is a hardware failure of the Q6†WRB.
system.
(Please consult your local Mitsubishi
2013 ■Collateral information CPU Status:
representative, explaining a detailed description
• Common information: Base No. Stop
of the problem.)
• Individual information:-
■Diagnostic Timing
• At power-on/At reset
[EXT.CABLE ERR.]
The following errors were detected in the
redundant system. Check to see if the extension cable between the
• At power-on/reset, the standby system has main base unit and the Q6†WRB is connected
detected the error in the path between the correctly. If not, connect it after turning OFF the
control system and the Q6†WRB. main base unit where the extension cable will be
• The standby system detected an error in the connected.
2020
path to the Q6†WRB in the END processing. If the cable is properly connected, the cause is a
■Collateral information hardware failure of the CPU module, Q6†WRB,
• Common information:- or extension cable. (Please consult your local
• Individual information:- Mitsubishi representative, explaining a detailed
■Diagnostic Timing description of the problem.)
• At power-on/At reset/When an END instruction
executed
[NO END COVER]
No END cover.
■Collateral information
2030 • Common information:- • Attach an END cover.
• Individual information:- • Reset the CPU module and run it again. If the
■Diagnostic Timing same error code is displayed again, the cause
• At power-on/At reset is a hardware failure of the CPU module, I/O
LCPU
[NO END COVER] module, intelligent function module, or END
No END cover. cover. (Please consult your local Mitsubishi
■Collateral information representative, explaining a detailed
2031 • Common information:- description of the problem.)
• Individual information:-
■Diagnostic Timing
• When an END instruction executed

12-22
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
• Read common information of the error using
the programming tool to identify the numeric 1
value (module No.). Check the module
[UNIT BAD CONNECT]
corresponding to the value and replace it as
• The I/O module status is different from that
necessary.
obtained at power-on.
• The I/O module (including the intelligent function
• Monitor SD1400 to SD1431 using the 2
programming tool to identify the module of
module) is nearly disconnected or is completely
which data bit is "1". Check the module and
2040 disconnected during running. LCPU
replace it as necessary.
■Collateral information
• Common information: Module No. (Slot No.)
• Reset the CPU module and run it again. If the
same error code is displayed again, the cause
3
• Individual information:-
is a hardware failure of the CPU module, I/O
■Diagnostic Timing
• Always module, intelligent function module, or END
cover. (Please consult your local Mitsubishi
representative, explaining a detailed 12
description of the problem.)
[SP. UNIT LAY ERR.]
The slot where the QI60 is mounted was assigned
as other than an intelligent function module or 6
interrupt module in the I/O assignment tab of the
Qn(H)*8
PLC parameter dialog box. Make setting again to match the PLC parameter I/
QnPH
■Collateral information O assignment with the actual loading status.
• Common information: Module No. (Slot No.)
QnPRH
6
• Individual information:-
■Diagnostic Timing
• At power-on/At reset
[SP. UNIT LAY ERR.] 7
• The I/O module was assigned as an intelligent
function module in the I/O assignment tab of the
PLC parameter dialog box. Or vice versa. RUN:
• In the I/O assignment setting of PLC parameter,
a module other than CPU (or nothing) was
Off 8
ERR.:
allocated to the location of a CPU module or Flicker
vice versa.
• Make the PLC parameter's I/O assignment
• In the I/O assignment setting of the PLC CPU Status:
setting again so it is consistent with the actual Qn(H)
parameter, switch setting was made to the Stop
status of the intelligent function module and the QnPH
module that has no switch setting.
CPU module. QnPRH
• In the I/O assignment setting of the PLC
• Delete the switch setting in the I/O assignment QnU
parameter dialog box, the number of points

12.1.4 Error code list (2000 to 2999)

12.1 Error Code List
setting of the PLC parameter.
assigned to the intelligent function module is
less than the number of points of the mounted
2100
module.
■Collateral information
• Common information: Module No. (Slot No.)
• Individual information:-
■Diagnostic Timing
• At power-on/At reset
[SP. UNIT LAY ERR.]
• In the I/O assignment tab of the PLC parameter
dialog box, the I/O module was assigned to the
slot for an intelligent function module. Or vice
versa.
• In the parameter I/O allocation settings, a
module other than CPU (or nothing) was
allocated to a location reserved for a CPU
module or vice versa. Reset the parameter I/O allocation setting to
• In the I/O assignment setting of the PLC conform to the actual status of the intelligent Q00J/Q00/Q01
parameter dialog box, the number of points function module and the CPU module.
assigned to the intelligent function module is
less than the number of points of the mounted
module.
■Collateral information
• Common information: Module No. (Slot No.)
• Individual information:-
■Diagnostic Timing
• At power-on/At reset

12-23
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
[SP. UNIT LAY ERR.]
• In the I/O Assignment tab of the PLC Parameter
dialog box, an intelligent function module was
assigned to the slot for an I/O module. Or vice • Set the parameter again in the I/O Assignment
versa. tab of the PLC Parameter dialog box according
• In the I/O Assignment tab of the PLC Parameter to the CPU module mounted.
dialog box, an intelligent function module was • Delete the switch setting.
assigned to the slot for an I/O module. • Reset the CPU module and run it again. If the
2100 • In the I/O Assignment tab of the PLC Parameter same error code is displayed again, the cause LCPU
dialog box, the number of points assigned to the is a hardware failure of the CPU module, I/O
intelligent function module is less than that of the module, intelligent function module, or END
mounted module. cover. (Please consult your local Mitsubishi
■Collateral information representative, explaining a detailed
• Common information: Module No. (Slot No.) description of the problem.)
• Individual information:-
■Diagnostic Timing
• At power-on/At reset
[SP. UNIT LAY ERR.]
13 or more A-series special function modules
(except for the A1SI61) that can initiate an
interrupt to the CPU module have been installed. Reduce the A series special function modules
2101 ■Collateral information (except the A1SI61) that can make an interrupt Qn(H)
• Common information: Module No. (Slot No.) start to the CPU module to 12 or less.
• Individual information:-
■Diagnostic Timing
• At power-on/At reset
[SP. UNIT LAY ERR.]
RUN:
Seven or more A1SD51S have been installed.
Off
■Collateral information
ERR.:
2102 • Common information: Module No. (Slot No.) Keep the number of A1SD51S to six or fewer. Qn(H)
Flicker
• Individual information:-
■Diagnostic Timing
• At power-on/At reset CPU Status:
Stop
[SP. UNIT LAY ERR.]
• Reduce the number of QI60/A1SI61 modules
• Two or more QI60/A1SI61 modules are mounted
mounted in the single CPU system to one.
in a single CPU system.
• Change the number of QI60/A1SI61 modules
• Two or more QI60/A1SI61 modules are set to
set to the same control CPU to only one in the
the same control CPU in a multiple CPU system.
multiple CPU system.
• Two or more A1SI61 modules are loaded in a Qn(H)*8
• Reduce the number of A1SI61 modules to only
multiple CPU system. QnPH
one in the multiple CPU system. When using
■Collateral information
an interrupt module with each QCPU in a
• Common information: Module No. (Slot No.)
multiple CPU system, replace it with the QI60.
• Individual information:-
(Use one A1SI61 module + max. three QI60
■Diagnostic Timing
• At power-on/At reset modules or only the QI60 modules.)

[SP. UNIT LAY ERR.]

2103 Two or more QI60, A1SI61 interrupt modules have
been mounted.
■Collateral information Qn(H)
Install only 1 QI60, A1SI61 module.
• Common information: Module No. (Slot No.) QnPRH
• Individual information:-
■Diagnostic Timing
• At power-on/At reset
[SP. UNIT LAY ERR.]
Two or more QI60 modules are mounted.
■Collateral information
• Common information: Module No. (Slot No.) Reduce the QI60 modules to one. Q00J/Q00/Q01*10
• Individual information:-
■Diagnostic Timing
• At power-on/At reset

12-24
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
[SP. UNIT LAY ERR.]
Two or more QI60 modules where interrupt pointer 1
setting has not been made are mounted.
• Reduce the QI60 modules to one.
■Collateral information Q00J/Q00/Q01*8
2103 • Make interrupt pointer setting to the second
• Common information: Module No. (Slot No.) QnU
2
QI60 module and later.
• Individual information:-
■Diagnostic Timing
• At power-on/At reset
[SP. UNIT LAY ERR.]
• Two or more MELSECNET/H modules are
mounted.
3
• Reduce the number of MELSECNET/H
• Two or more CC-Link IE controller network
modules to one.
modules are mounted.
• Reduce the number of CC-Link IE controller
2106 • Two or more Ethernet modules are mounted.
■Collateral information
network modules to one.
• Reduce the number of Ethernet modules to
Q00UJCPU
12
• Common information: Module No. (Slot No.)
one.
• Individual information:-
■Diagnostic Timing
• At power-on/At reset 6
[SP. UNIT LAY ERR.]
• Five or more MELSECNET/H and CC-Link IE
controller network modules in total are mounted
in the entire system. • Reduce the number of MELSECNET/H and
CC-Link IE controller network modules to four
6
• Two or more MELSECNET/H modules are
mounted in the entire system. or less in total in the entire system.
RUN:
• Two or more CC-Link IE controller network • Reduce the number of MELSECNET/H
Off Q00UCPU
modules are mounted in the entire system.
• Two or more Ethernet modules are mounted in
modules to one in the entire system.
• Reduce the number of CC-Link IE controller
ERR.: Q01UCPU 7
Flicker
the entire system. network modules to one in the entire system.
■Collateral information • Reduce the number of Ethernet modules to one
CPU Status:
• Common information: Module No. (Slot No.)
• Individual information:-
in the entire system.
Stop 8
■Diagnostic Timing
• At power-on/At reset
[SP. UNIT LAY ERR.]
• Three or more MELSECNET/H and CC-Link IE
controller network modules in total are mounted
2106 in the entire system. • Reduce the MELSECNET/H and CC-Link IE
• Three or more Ethernet interface modules are controller network modules up to two or less in

12.1.4 Error code list (2000 to 2999)

12.1 Error Code List
mounted in the entire system. the entire system. Q02UCPU
■Collateral information • Reduce the Ethernet interface modules up to
• Common information: Module No. (Slot No.) two or less in the entire system.
• Individual information:-
■Diagnostic Timing
• At power-on/At reset
[SP. UNIT LAY ERR.]
• Five or more MELSECNET/H and CC-Link IE
controller network modules in total are mounted
in the entire system. • Reduce the MELSECNET/H and CC-Link IE
• Five or more Ethernet interface modules are controller network modules up to four or less in
mounted in the entire system. the entire system. QnU*20
■Collateral information • Reduce the Ethernet interface modules up to
• Common information: Module No. (Slot No.) four or less in the entire system.
• Individual information:-
■Diagnostic Timing
• At power-on/At reset

12-25
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
[SP. UNIT LAY ERR.]
• Three or more CC-Link IE controller network
modules are mounted in the entire system.
• Five or more MELSECNET/H and CC-Link IE • Reduce the CC-Link IE controller network
controller network modules in total are mounted modules up to two or less in the entire system. Qn(H)*15
in the entire system. • Reduce the total number of the MELSECNET/ QnPH*17
■Collateral information H and CC-Link IE controller network modules QnPRH*17
• Common information: Module No. (Slot No.) up to four or less in the entire system.
• Individual information:-
■Diagnostic Timing
• At power-on/At reset
[SP. UNIT LAY ERR.]
• Five or more MELSECNET/H modules have
been installed.
• Five or more Ethernet interface modules have • Reduce the number of MELSECNET/H
Qn(H)
been installed. modules to four or less.
QnPH
■Collateral information • Reduce the number of Ethernet modules to four
QnPRH
• Common information: Module No. (Slot No.) or less.
• Individual information:-
■Diagnostic Timing
2106 • At power-on/At reset
[SP. UNIT LAY ERR.]
• Two or more MELSECNET/H modules were
installed.
• Two or more Ethernet modules were installed. • Reduce the MELSECNET/H modules to one or
• Three or more CC-Link modules were installed. less.
Q00J/Q00/Q01
■Collateral information • Reduce the Ethernet modules to one or less.
• Common information: Module No. (Slot No.) • Reduce the CC-Link modules to two or less. RUN:
• Individual information:- Off
■Diagnostic Timing ERR.:
• At power-on/At reset Flicker

[SP. UNIT LAY ERR.]

CPU Status:
• The same network number or same station
Stop
number is duplicated in the MELSECNET/H
Q00J/Q00/Q01
network system.
Qn(H)
■Collateral information • Check the network number and station number.
QnPH
• Common information: Module No. (Slot No.)
QnPRH
• Individual information:-
■Diagnostic Timing
• At power-on/At reset
[SP. UNIT LAY ERR.]
The start X/Y set in the PLC parameter's I/O
assignment settings is overlapped with the one for
Make the PLC parameter's I/O assignment setting
another module.
again so it is consistent with the actual status of
■Collateral information QCPU
the intelligent function module/special function
• Common information: Module No. (Slot No.)
modules.
• Individual information:-
■Diagnostic Timing
• At power-on/At reset
• Configure the start X/Y again in the I/O
2107
[SP. UNIT LAY ERR.] Assignment tab of the PLC Parameter dialog
The start X/Y configured in the I/O Assignment tab box according to the intelligent function module
of the PLC Parameter dialog box is overlapped and I/O modules connected.
with that for another module. • Reset the CPU module and run it again. If the
■Collateral information same error code is displayed again, the cause LCPU
• Common information: Module No. (Slot No.) is a hardware failure of the CPU module, I/O
• Individual information:- module, intelligent function module, or END
■Diagnostic Timing cover. (Please consult your local Mitsubishi
• At power-on/At reset representative, explaining a detailed
description of the problem.)

12-26
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
[SP. UNIT LAY ERR.]
• Network module A1SJ71LP21, A1SJ71BR11, 1
A1SJ71AP21, A1SJ71AR21, or A1SJ71AT21B
RUN:
dedicated for the A2USCPU has been installed.
Off
• Network module A1SJ71QLP21 or
2
Replace the network module for the A2USCPU or ERR.:
A1SJ71QBR11 dedicated for the Q2ASCPU has
2108 the network module for the Q2ASCPU with the Flicker Qn(H)
been installed.
MELSECNET/H module.
■Collateral information
CPU Status:
• Common information: Module No. (Slot No.)
Stop
• Individual information:-
■Diagnostic Timing
3
• At power-on/At reset
[SP. UNIT ERROR]
• The location designated by the FROM/TO
instruction set is not the intelligent function 12
module/special function module.
• Read the individual information of the error
• The module that does not include buffer memory
using the programming tool to identify the
has been specified by the FROM/TO instruction.
• The intelligent function module/special function
numeric value (program error location). Correct
the FROM/TO instruction corresponding to the
Q00J/Q00/Q01 6
module, Network module being accessed is Qn(H)*8
value as necessary.
faulty. QnPH
• The cause is a hardware fault of the intelligent
• Station not loaded was specified using the QnPRH
instruction whose target was the CPU share
memory.
function module/special function module in the
access destination. (Please consult your local RUN:
QnU 6
Mitsubishi representative, explaining a detailed Off/On
■Collateral information
description of the problem.) ERR.:
• Common information: Module No. (Slot No.)
Flicker/On
2110 • Individual information: Program error location
■Diagnostic Timing
7
• When instruction executed CPU Status:
Stop/
[SP. UNIT ERROR] • Read the individual information of the error
Continue*1
• A module other than intelligent function modules
is specified with the FROM/TO instruction.
using the programming tool to identify the
numeric value (program error location). Correct
8
• The module specified with the FROM/TO the FROM/TO instruction corresponding to the
instruction does not have the buffer memory. value as necessary.
• The intelligent function module being accessed • Reset the CPU module and run it again. If the
LCPU
is faulty. same error code is displayed again, the cause
■Collateral information is a hardware failure of the CPU module, I/O
• Common information: Module No. (Slot No.) module, intelligent function module, or END
• Individual information: Program error location cover. (Please consult your local Mitsubishi

12.1.4 Error code list (2000 to 2999)

12.1 Error Code List
■Diagnostic Timing representative, explaining a detailed
• When instruction executed description of the problem.)
[SP. UNIT ERROR]
• The location designated by a link direct device • Read the individual information of the error
(J†\†) is not a network module. using the programming tool to identify the RUN:
• The I/O module (intelligent function module/ numeric value (program error location). Correct Off/On
special function module) was nearly removed, the FROM/TO instruction corresponding to the ERR.:
completely removed, or mounted during value as necessary. Flicker/On
2111 QCPU
running. • The cause is a hardware fault of the intelligent
■Collateral information function module/special function in the access CPU Status:
• Common information: Module No. (Slot No.) destination. (Please consult your local Stop/
• Individual information: Program error location Mitsubishi representative, explaining a detailed Continue*1
■Diagnostic Timing description of the problem.)
• When instruction executed

12-27
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
[SP. UNIT ERROR]
• The module other than intelligent function
module/special function module is specified by
the intelligent function module/special function
module dedicated instruction. Or, it is not the Read the individual information of the error using
corresponding intelligent function module/ the programming tool to identify the numeric
special function module. value (program error location). Check the
• There is no network No. specified by the intelligent function module/special function QCPU
network dedicated instruction. Or the relay module dedicated instruction (instruction for a
target network does not exit. network) corresponding to the value and correct it
■Collateral information as necessary. RUN:
• Common information: Module No. (Slot No.) Off/On
• Individual information: Program error location ERR.:
■Diagnostic Timing Flicker/On
2112 • When instruction executed/STOP→RUN
• Read the individual information of the error CPU Status:
using the programming tool to identify the Stop/
[SP. UNIT ERROR]
numeric value (program error location). Check Continue*1
• The module other than intelligent function
the intelligent function module dedicated
module was specified with an intelligent function
instruction corresponding to the value and
module dedicated instruction. Or there is no
correct it as necessary.
relevant intelligent function module.
• Reset the CPU module and run it again. If the LCPU
■Collateral information
same error code is displayed again, the cause
• Common information: Module No. (Slot No.)
is a hardware failure of the CPU module, I/O
• Individual information: Program error location
module, intelligent function module, or END
■Diagnostic Timing
• When instruction executed/STOP→RUN cover. (Please consult your local Mitsubishi
representative, explaining a detailed
description of the problem.)

[SP. UNIT ERROR] RUN:

Read the individual information of the error using
The module other than network module is Off/On
the programming tool to identify the numeric
specified by the network dedicated instruction. ERR.:
value (program error location). Check the
■Collateral information Flicker/On Qn(H)
2113 intelligent function module/special function
• Common information: FFFFH (fixed) QnPH
module dedicated instruction (instruction for a
• Individual information: Program error location CPU Status:
network) corresponding to the value and correct it
■Diagnostic Timing Stop/
as necessary.
• When instruction executed/STOP→RUN Continue*1
[SP. UNIT ERROR]
An instruction, which on execution specifies other
stations, has been used for specifying the host
CPU. (An instruction that does not allow the host Q00J/Q00/Q01 *8

2114
CPU to be specified). Qn(H) *8
■Collateral information QnPH
• Common information: Module No. (Slot No.) QnU
• Individual information: Program error location
■Diagnostic Timing
• When instruction executed/STOP→RUN
[SP. UNIT ERROR]
An instruction, which on execution specifies the
host CPU, has been used for specifying other RUN:
CPUs. (An instruction that does not allow other Read individual information of the error using the Off/On
Q00J/Q00/Q01 *8
stations to be specified). programming tool to identify the numeric value ERR.:
2115 Qn(H) *8
■Collateral information (program error location). Check the error step Flicker/On
• Common information: Module No. (Slot No.) corresponding to the value and correct it as QnPH
• Individual information: Program error location necessary. CPU Status:
■Diagnostic Timing Stop/Continue
• When instruction executed/STOP→RUN
[SP. UNIT ERROR]
• An instruction that does not allow the under the
control of another CPU to be specified is being
used for a similar task.
Q00J/Q00/Q01 *8
• Instruction was executed for the A or QnA
2116 Qn(H) *8
module under control of another CPU.
QnPH
■Collateral information
• Common information: Module No. (Slot No.) QnU
• Individual information: Program error location
■Diagnostic Timing
• When instruction executed/STOP→RUN

12-28
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
[SP. UNIT ERROR]
A CPU module that cannot be specified in the 1
instruction dedicated to the multiple CPU system Read individual information of the error using the *8
Q00J/Q00/Q01
was specified. programming tool to identify the numeric value
2117 (program error location). Check the error step Qn(H) *8
■Collateral information
• Common information: Module No. (Slot No.)
• Individual information: Program error location
corresponding to the value and correct it as
necessary.
QnPH
QnU
2
■Diagnostic Timing RUN:
• When instruction executed/STOP→RUN Off/On
[SP. UNIT ERROR]
When the online module change setting is set to
ERR.:
Flicker/On
3
be "enabled" in the PLC parameter in a multiple • When performing the online module change in
CPU system, intelligent function module controlled a multiple CPU system, correct the program so CPU Status:

2118
by other CPU using the FROM instruction/
intelligent function module device (U†\G†) is
that access will not be made to the intelligent
function module controlled by the other CPU.
Stop/Continue
Qn(H)*8
QnPH
12
specified. • When accessing the intelligent function module
controlled by the other CPU in a multiple CPU QnU*20
■Collateral information
• Common information: Module No. (Slot No.) system, set the online module change setting to
• Individual information: Program error location be "disabled" by parameter. 6
■Diagnostic Timing
• When instruction executed
[SP. UNIT LAY ERR.]
The locations of the Q5†B/Q6†B, QA1S6†B/ 6
QA6†B, and QA6ADP+A5†B/A6†B are
improper. Q00J/Q00/Q01*7
2120 ■Collateral information Check the location of the base unit. Qn(H)
• Common information:-
• Individual information:-
QnPH
7
■Diagnostic Timing
• At power-on/At reset
[SP. UNIT LAY ERR.]
The CPU module is installed to other than the CPU
RUN:
off 8
slot and slots 0 to 2. ERR.:
■Collateral information Check the loading position of the CPU module Flicker Qn(H)
2121
• Common information:- and reinstall it at the correct slot. QnPH
• Individual information:- CPU Status:
■Diagnostic Timing Stop
• At power-on/At reset
[SP. UNIT LAY ERR.]

12.1.4 Error code list (2000 to 2999)

12.1 Error Code List
The QA1S6†B/QA6†B and QA6ADP+A5†B/
A6†B are used for the main base unit.
Qn(H)
■Collateral information
2122 Replace the main base unit with a usable one. QnPH
• Common information:-
QnPRH
• Individual information:-
■Diagnostic Timing
• At power-on/At reset

12-29
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
[SP. UNIT LAY ERR.]
• A module is mounted on the 65th slot or later
• Remove the module mounted on the 65th slot
slot.
or later slot.
• A module is mounted on the slot whose number
• Remove the module mounted on the slot
is greater than the number of slots specified at
whose number is greater than the number of
[Slots] in [Standard setting] of the base setting.
slots specified at [Slots] in [Standard setting] of Qn(H)
• A module is mounted on the slot whose number
the base setting. QnPH
of I/O points exceeds 4096 points.
• Remove the module mounted on the slot QnPRH
• A module is mounted on the slot whose number
whose number of I/O points exceeds 4096 QnU*20
of I/O points strides 4096 points.
points.
■Collateral information
• Replace the module with the one whose
• Common information:-
number of occupied points does not exceed
• Individual information:-
4096 points.
■Diagnostic Timing
• At power-on/At reset
[SP. UNIT LAY ERR.]
• A module is mounted on after the 25th slot (on
after the 17th slot for the Q00UJ).
• A module is mounted on the slot whose number
• Remove the module mounted on after the 25th
is later than the one set in the "Base setting" on
(on after the 17th slot for the Q00UJ).
the I/O assignment tab of PLC parameter in GX
• Remove the module mounted on the slot
Developer. RUN:
whose number is later than the one set in the
• A module is mounted on the slot for which I/O Off
"Base setting" on the I/O assignment tab of
points greater than 1024 (greater than 256 for ERR.:
PLC parameter in GX Developer.
2124 the Q00UJ) is assigned. Flicker Q00UJ/Q00U/Q01U
• Remove the module mounted on the slot for
• A module is mounted on the slot for which I/O
which I/O points greater than 1024 (greater
points is assigned from less than 1024 to greater CPU Status:
than 256 for the Q00UJ) is assigned.
than 1024 (from less than 256 to greater than Stop
• Replace the end module with the one whose
256 for the Q00UJ).
number of occupied points is within 1024
■Collateral information
(within 256 for the Q00UJ).
• Common information:-
• Individual information:-
■Diagnostic Timing
• At power-on/At reset
[SP. UNIT LAY ERR.]
• A module is mounted on the 37th slot or later
• Remove the module mounted on the 37th slot
slot.
or later slot.
• A module is mounted on the slot whose number
• Remove the module mounted on the slot
is greater than the number of slots specified at
whose number is greater than the number of
[Slots] in [Standard setting] of the base setting.
slots specified at [Slots] in [Standard setting] of
• A module is mounted on the slot whose number
the base setting.
of I/O points exceeds 2048 points. Q02UCPU
• Remove the module mounted on the slot
• A module is mounted on the slot whose number
whose number of I/O points exceeds 2048
of I/O points strides 2048 points.
points.
■Collateral information
• Replace the module with the one whose
• Common information:-
number of occupied points does not exceed
• Individual information:-
2048 points.
■Diagnostic Timing
• At power-on/At reset

12-30
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
[SP. UNIT LAY ERR.]
• A module is mounted on the 25th slot or later
• Remove the module mounted on the 25th slot
1
slot. (The 17th slot or later slot for the Q00J.)
or later slot. (The 17th slot or later slot for the
• A module is mounted on the slot whose number
Q00J.)
is greater than the number of slots specified at
2
• Remove the module mounted on the slot
[Slots] in [Standard setting] of the base setting.
whose number is greater than the number of
• A module is mounted on the slot whose number
slots specified at [Slots] in [Standard setting] of
of I/O points exceeds 1024 points. (256 points
the base setting.
for the Q00J.) Q00J/Q00/Q01
• Remove the module mounted on the slot
• A module is mounted on the slot whose number
of I/O points strides 1024 points. (256 points for
whose number of I/O points exceeds 1024 3
points (greater than or equal to 256 points for
the Q00J.)
the Q00J).
■Collateral information
• Replace the module with the one whose
• Common information:-
• Individual information:-
number of occupied points does not exceed
1024 points (within 256 points for the Q00J).
12
■Diagnostic Timing
• At power-on/At reset
• Reduce the number of connectable modules to
[SP. UNIT LAY ERR.] 10. 6
• The number of connectable modules has • Remove the module whose number of points RUN:
exceeded 10. exceeds 4096 points. Off
• A module is installed exceeding the I/O points of • Replace the module to installed at end with the ERR.:
2124 4096. one whose number of occupied points does not Flicker 6
• A module is installed crossing the I/O points of exceed 4096 points.
L26CPU-BT
4096. • Reset the CPU module and run it again. If the CPU Status:
■Collateral information same error code is displayed again, the cause Stop
• Common information:-
• Individual information:-
is a hardware failure of the CPU module, I/O
module, intelligent function module, or END
7
■Diagnostic Timing cover. (Please consult your local Mitsubishi
• At power-on/At reset representative, explaining a detailed
description of the problem.)
• Reduce the number of connectable modules to
8
[SP. UNIT LAY ERR.] 10.
• The number of connectable modules has • Remove the module whose number of points
exceeded 10. exceeds 1024 points.
• A module is installed exceeding the I/O points of • Replace the module with the one whose
1024. number of occupied points does not exceed
• A module is installed crossing the I/O points of 1024 points.
L02CPU
1024. • Reset the CPU module and run it again. If the

12.1.4 Error code list (2000 to 2999)

12.1 Error Code List
■Collateral information same error code is displayed again, the cause
• Common information:- is a hardware failure of the CPU module, I/O
• Individual information:- module, intelligent function module, or END
■Diagnostic Timing cover. (Please consult your local Mitsubishi
• At power-on/At reset representative, explaining a detailed
description of the problem.)
[SP. UNIT LAY ERR.]
• A module which the QCPU cannot recognise
has been installed. • Install a usable module.
• There was no response from the intelligent • The intelligent function module/special function
function module/special function module. module is experiencing a hardware fault.
QCPU
■Collateral information (Please consult your local Mitsubishi
• Common information: Module No. (Slot No.) representative, explaining a detailed
RUN:
• Individual information:- description of the problem.)
Off
■Diagnostic Timing
• At power-on/At reset ERR.:
2125 Flicker
[SP. UNIT LAY ERR.]
• A module which the LCPU cannot recognize has • Connect an applicable module.
CPU Status:
been connected. • Reset the CPU module and run it again. If the
Stop
• There was no response from the intelligent same error code is displayed again, the cause
function module. is a hardware failure of the CPU module, I/O
LCPU
■Collateral information module, intelligent function module, or END
• Common information: Module No. (Slot No.) cover. (Please consult your local Mitsubishi
• Individual information:- representative, explaining a detailed
■Diagnostic Timing description of the problem.)
• At power-on/At reset

12-31
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
[SP. UNIT LAY ERR.]
The CPU module configuration in the multiple CPU
system is either of the following.
• Mount modules on the available slots so that
• There are empty slots between the QCPU and
the empty slots will be located on the right-hand
QCPU/motion controller.
side of the CPU module.
• A module other than the High Performance
• Remove the modules mounted on the left of the
model QCPU/Process CPU (including the
High Performance model QCPU or Process Qn(H)*8
2126 motion controller) is mounted on the left-hand
CPU. Mount a High Performance model QCPU QnPH
side of the High Performance model QCPU/
or Process CPU on those slots.
Process CPU.
Mount the motion CPU on the right-hand side
■Collateral information
of the High Performance model QCPU/Process
• Common information: Module No. (Slot No.)
CPU.
• Individual information:-
■Diagnostic Timing
• At power-on/At reset
[SP.UNIT LAY ERR.]
The unusable module is mounted on the extension
base unit in the redundant system.
■Collateral information • Remove the unusable module from the
2128 QnPRH*15
• Common information: Module No. (Slot No.) extension base unit.
• Individual information:-
■Diagnostic Timing
• At power-on/At reset
[SP. UNIT VER. ERR.]
In a multiple CPU system, the control CPU of the
RUN:
intelligent function module incompatible with the
• Change the intelligent function module for the Off
multiple CPU system is set to other than CPU
one compatible with the multiple CPU system ERR.:
No.1. Q00J/Q00/Q01
(function version B). Flicker
2150 ■Collateral information QnPH
• Change the setting of the control CPU of the
• Common information: Module No. (Slot No.) QnU*18
intelligent function module incompatible with CPU Status:
• Individual information:-
the multiple CPU system to CPU No.1. Stop
■Diagnostic Timing
• At power-on/At reset/At writing to programmable
controller
[SP. UNIT VER. ERR.]
Either of the following modules incompatible with
the redundant system has been mounted in a
redundant system.
Ensure that the module supports the use in a
• MELSECNET/H modules
redundant system when using any of the following
• Ethernet modules
modules.
2151 • CC-Link IE controller network modules QnPRH
• MELSECNET/H modules
■Collateral information
• Ethernet modules
• Common information: Module No. (Slot No.)
• CC-Link IE controller network modules
• Individual information:-
■Diagnostic Timing
• At power-on/At reset/At writing to programmable
controller
• Disconnect the module that cannot be
[SYSTEM LAY ERR.]
recognized.
A module which the LCPU cannot recognize is
• Reset the CPU module and run it again. If the
connected.
same error code is displayed again, the cause
■Collateral information
2170 is a hardware failure of the CPU module, I/O LCPU
• Common information:-
module, intelligent function module, or END
• Individual information:-
cover. (Please consult your local Mitsubishi
■Diagnostic Timing
representative, explaining a detailed
At power-on/At reset
description of the problem)

12-32
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
[MISSING PARA.]
There is no parameter file in the drive specified as 1
valid parameter drive by the DIP switches. • Check and correct the valid parameter drive
Qn(H)
■Collateral information settings made by the DIP switches.
QnPH
• Common information: Drive name • Set the parameter file to the drive specified as
2
QnPRH
• Individual information:- valid parameter drive by the DIP switches.
■Diagnostic Timing
• At power-on/At reset/STOP→RUN
[MISSING PARA.]
There is no parameter file at the program memory.
■Collateral information
3
• Common information: Drive name Set the parameter file to the program memory. Q00J/Q00/Q01
• Individual information:-
■Diagnostic Timing
• At power-on/At reset/STOP→RUN 12
2200 [MISSING PARA.]
Parameter file does not exist in all drives where
parameters will be valid.
■Collateral information
Set a parameter file in a drive to be valid. QnU
6
• Common information: Drive name
• Individual information:-
■Diagnostic Timing
• At power-on/At reset/STOP→RUN
6
[MISSING PARA.]
There is no parameter file in the program memory.
■Collateral information
• Common information: Drive name
• Individual information:-
Write parameter files to the program memory of
the CPU module. RUN:
LCPU 7
■Diagnostic Timing off
• At power-on/At reset/At writing to programmable ERR.:

8
controller Flicker
[BOOT ERROR]
Q00J/Q00/Q01*8
The contents of the boot file are incorrect. CPU Status:
Qn(H)
■Collateral information Stop
QnPH
2210 • Common information: Drive name Check the boot setting.
QnPRH
• Individual information:-
QnU
■Diagnostic Timing
• At power-on/At reset LCPU

[BOOT ERROR]

12.1.4 Error code list (2000 to 2999)

12.1 Error Code List
File formatting is failed at a boot. • Reboot.
Qn(H)
■Collateral information • The cause is a hardware failure of the CPU
QnPRH
2211 • Common information: Drive name module. (Please consult your local Mitsubishi
QnU
• Individual information:- representative, explaining a detailed
LCPU
■Diagnostic Timing description of the problem.)
• At power-on/At reset
[BOOT ERROR]
The file was booted from the SD memory card to
the program memory or standard ROM but it was
not booted to the CPU module due to either of the
following reasons.
• The passwords for the password 32 do not
match between transfer source file and • Check the setting of the password 32 for the
destination file. transfer source file and destination files.
2213 LCPU
• The password 32 is not configured for the • Delete the boot setting from the parameter file
transfer source file while it is configured for the of the SD memory card.
destination file.
■Collateral information
• Common information: File name/Drive name
• Individual information:-
■Diagnostic Timing
• At power-on/At reset

12-33
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
[RESTORE ERROR]
• The device information (number of points)
backed up by the device data backup function is
different from that configured in the PLC
Parameter dialog box. • Set the number of device points at the time of
Perform a restoration per power-on and reset until backup to be identical to the device point value
the number of device points is identical to the set in the PLC Parameter dialog box. Then turn
2220
value set in the PLC Parameter dialog box or until on from off or reset the power supply.
the backup data are deleted. • Delete the backed up data, turn the power
■Collateral information supply from off to on, and reset.
• Common information: File name/Drive name
• Individual information:-
■Diagnostic Timing
• At power-on/At reset
[RESTORE ERROR]
• The device information backuped by the device
data backup function is incomplete. (The power
may have been off or the CPU module may have QnU
been reset during performing the backup.) LCPU
Do not return the data when this error occurs. Also,
2221 delete the incomplete device information at the Reset the CPU module and run it again.
time of this error occurrence.
■Collateral information
• Common information: File name/Drive name
• Individual information:-
■Diagnostic Timing
• At power-on/At reset
[RESTORE ERROR]
The model name of the restoration destination
RUN:
CPU module is different from the one of the
Off
backup source CPU module. Execute a restore for the CPU module whose
ERR.:
2225 ■Collateral information name is same as the backup source CPU
Flicker
• Common information:- module.
• Individual information:-
CPU Status:
■Diagnostic Timing
Stop
• At power-on/At reset
[RESTORE ERROR]
• The backup data file is corrupted.(The backup
data file does not match the check code.)
• Reading the backup data from the SRAM card
did not end successfully.
• Since the write protect switch of the SRAM card • Execute a restore of other backup data
is set to on (write inhibited), the checked because the backup data may be corrupted.
QnU
"Restore for the first time only" setting cannot be • Set the write protect switch of the SRAM card
performed. to off (write enabled).
■Collateral information
• Common information:-
• Individual information:-
■Diagnostic Timing
• At power-on/At reset
2226
[RESTORE ERROR]
• The backup data file is corrupted. (The backup
data file does not match the check code.)
• Reading the backup data from the SD memory
card did not end successfully.
• The "Restore for the first time only" setting • Restore with any other backup data because
cannot be enabled because the write protect the backup data may have been corrupted.
LCPU
switch of the SD memory card has been set to • Set the write protect switch of the SD memory
on (write-prohibited). card to off (write-enabled).
■Collateral information
• Common information:-
• Individual information:-
■Diagnostic Timing
• At power-on/At reset

12-34
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
[RESTORE ERROR]
Writing the backup data to the restoration
RUN:
Off
1
destination drive did not end successfully.
ERR.:
■Collateral information Execute a restore for the other CPU module too QnU
2227 Flicker
• Common information: File name/Drive name because the CPU module may be damaged. LCPU
• Individual information:-
■Diagnostic Timing
CPU Status: 2
Stop
• At power-on/At reset
[ICM. OPE. ERROR]
• A memory card was removed without switching
the memory card in/out switch OFF.
3
• The memory card in/out switch was turned on • Remove memory card after placing the memory Qn(H)
although a memory card is not inserted. card in/out switch OFF. QnPH
QnPRH
■Collateral information
• Common information: Drive name
• Turn on the card insert switch after inserting a
memory card. QnU*19 12
• Individual information:-
■Diagnostic Timing
2300 • When memory card is inserted or removed
[ICM. OPE. ERROR] 6
• A memory card was removed without turning off
the SD memory card lock switch.
■Collateral information • Turn off the SD memory card lock switch first
• Common information: Drive name
• Individual information:-
and then remove the memory card.
LCPU
6
■Diagnostic Timing
• When memory card is inserted or removed
• Format memory card.
• Reformat memory card.
7
If the memory card is a flash card, write data to
[ICM. OPE. ERROR]
• The memory card has not been formatted.
the flash card in any of the following methods.
1)Write program memory to the ROM Qn(H)
8
• Memory card format status is incorrect.
2)Write data to the CPU module (flash ROM) QnPH
■Collateral information
3) Back up data to the flash card QnPRH
• Common information: Drive name RUN:
4)Write image data to an external device, such
Off/On QnU*19
• Individual information:-
as a memory card writer. LCPU
■Diagnostic Timing ERR.:
• When memory card is inserted or removed Flicker/On
If the same error code is displayed again, the
cause is a failure of the memory card. (Please
CPU Status:

12.1.4 Error code list (2000 to 2999)

12.1 Error Code List
consult your local Mitsubishi representative,
Stop/
explaining a detailed description of the problem.)
Continue*1
[ICM. OPE. ERROR]
2301 • The QCPU file does not exist in the Flash card.
Qn(H)
■Collateral information
QnPH
• Common information: Drive name • Write the QCPU file the Flash card
QnPRH
• Individual information:-
QnU*19
■Diagnostic Timing
• When memory card is inserted or removed
[ICM. OPE. ERROR]
• SRAM card failure is detected. (It occurs when
automatic format is not set.)
• Writing parameters was performed during • Format SRAM card after changing battery of
setting file registers. SRAM card.
■Collateral information • Before operation, set the parameter for the file QnU*19
• Common information: Drive name register to "Not available" and write it to the
• Individual information:- CPU module.
■Diagnostic Timing
• When memory card is inserted or removed/
When writing to the memory card
[ICM. OPE. ERROR]
A memory card that cannot be used with the CPU
Qn(H)
module has been installed.
• Format the memory card. QnPH
■Collateral information
2302 • Reformat the memory card. QnPRH
• Common information: Drive name
• Check the memory card. QnU*19
• Individual information:-
LCPU
■Diagnostic Timing
• When memory card is inserted or removed

12-35
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
[FILE SET ERROR]
Automatic write to standard ROM was performed
on the CPU module that is incompatible with
• Execute automatic write to standard ROM on
automatic write to standard ROM.
the CPU module which is compatible with
(Memory card where automatic write to standard
automatic write to standard ROM.
ROM was selected in the boot file was fitted and
• Write parameters and programs to the standard Qn(H)*8
the parameter enable drive was set to the memory
ROM using the programming tool. QnPH
card.)
• Change the memory card for the one where RUN: QnPRH
■Collateral information
automatic write to standard ROM has not been Off
• Common information: File name/Drive name
set, and perform boot operation from the ERR.:
• Individual information:-
2400 memory card. Flicker
■Diagnostic Timing
• At power-on/At reset/At writing to programmable
controller CPU Status:
Stop
[FILE SET ERROR] • Read the individual information of the error
The file specified with a parameter does not exist. using the programming tool to identify the
■Collateral information numeric value (parameter No.). Check the drive
• Common information: File name/Drive name name and file name of the parameter QCPU
• Individual information: Parameter number corresponding to the value, and correct it as LCPU
■Diagnostic Timing necessary.
• At power-on/At reset/At writing to programmable • Create the specified file and write it to the CPU
controller module.

12-36
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
[FILE SET ERROR]
Program memory capacity was exceeded by 1
performing boot operation or automatic write to
standard ROM.
Qn(H)*8
■Collateral information
• Common information: File name/Drive name
• Individual information: Parameter number • Check and correct the parameters (boot
QnPH
QnPRH 2
■Diagnostic Timing setting).
• At power-on/At reset/At writing to programmable • Delete unnecessary files in the program
controller
[FILE SET ERROR]
memory.
• Choose "Clear program memory" for boot in the RUN:
3
Program memory capacity was exceeded by parameter so that boot is started after the Off
performing boot operation. program memory is cleared. ERR.:
■Collateral information
• Common information: File name/Drive name
Flicker QnU
LCPU
12
• Individual information: Parameter number CPU Status:
■Diagnostic Timing Stop
• At power-on/At reset/At writing to programmable
controller 6
[FILE SET ERROR] • Read the individual information of the error
The file specified by parameters cannot be made. using the programming tool to identify the
■Collateral information numeric value (parameter No.). Check the drive
• Common information: File name/Drive name name and file name of the parameter QCPU 6
• Individual information: Parameter number corresponding to the value, and correct it as LCPU
■Diagnostic Timing necessary.
• At power-on/At reset/At writing to programmable • Check the space remaining in the memory
2401 controller card. 7
[FILE SET ERROR]
• Although setting is made to use the device data
storage file, there is no empty capacity required
for creating the device data storage file in the
standard ROM.
8
• When the latch data backup function (to
standard ROM) is used, there is no empty
capacity required for storing backup data in
standard ROM. (The parameter number Secure the empty capacity of the standard ROM.
"FFFFH" is displayed for the individual
RUN:
information of the error.)
Off
■Collateral information

12.1.4 Error code list (2000 to 2999)

12.1 Error Code List
ERR.:
• Common information: File name/Drive name QnU
Flicker
• Individual information: Parameter number LCPU
■Diagnostic Timing
CPU Status:
• At power-on/At reset/At writing to programmable
Stop
controller
[FILE SET ERROR]
• Standard RAM capacity is insufficient that error
history of the module cannot be stored.
■Collateral information
• Common information: File name/Drive name Secure sufficient space in the standard RAM.
• Individual information: Parameter number
■Diagnostic Timing
• At power-on/At reset/At writing to programmable
controller

12-37
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
[FILE SET ERROR]
When the extended data register and extended
link register are configured in the File Register
RUN:
Extended Setting in the Device tab of the PLC
• Correct the size for the file register file in the Off
Parameter dialog box, the size of the file register
PLC File tab of the PLC Parameter dialog box. ERR.:
file is smaller than that specified in the PLC File QnU
2406 • Correct the setting for the File Register Flicker
tab. LCPU
Extended Setting in the Device tab of the PLC
■Collateral information
Parameter dialog box. CPU Status:
• Common information: File name/Drive name
Stop
• Individual information: Parameter number
■Diagnostic Timing
• STOP→RUN
[FILE OPE. ERROR]
• The specified program does not exist in the • Read individual information of the error using
program memory. the programming tool to identify the numeric
• This error may occur when the ECALL, value (program error location). Check the error
Qn(H)
EFCALL, PSTOP, PSCAN, POFF or PLOW step corresponding to the value and correct it
QnPH
instruction is executed. as necessary.
2410 QnPRH
• The specified file does not exist. Create the specified file and write it to the CPU
QnU
■Collateral information module.
LCPU
• Common information: File name/Drive name • If the specified file does not exist, write the file
• Individual information: Program error location to the target memory. Or correct the file RUN:
■Diagnostic Timing specification by a instruction. Off/On
• When instruction executed ERR.:
[FILE OPE. ERROR] Flicker/On
• The file cannot be specified by the program,
such as comment file. CPU Status:
• The specified program exists in the program Stop/
memory, but has not been registered in the Continue*1
Read individual information of the error using the Qn(H)
program setting of the PLC Parameter dialog
programming tool to identify the numeric value QnPH
box. This error may occur when the ECALL,
2411 (program error location). Check the error step QnPRH
EFCALL, PSTOP, PSCAN, POFF or PLOW
corresponding to the value and correct it as QnU
instruction is executed.
necessary. LCPU
■Collateral information
• Common information: File name/Drive name
• Individual information: Program error location
■Diagnostic Timing
• When instruction executed
[FILE OPE. ERROR]
This SFC program file cannot be specified with the
Read individual information of the error using the Qn(H)
program.
programming tool to identify the numeric value QnPH
■Collateral information
2412 (program error location). Check the error step RUN: QnPRH
• Common information: File name/Drive name
corresponding to the value and correct it as Off/On QnU
• Individual information: Program error location
necessary. ERR.: LCPU
■Diagnostic Timing
• When instruction executed Flicker/On

[FILE OPE. ERROR] Read individual information of the error using the
CPU Status:
The file specified in the program was not written. programming tool to identify the numeric value
Stop/
■Collateral information (program error location). Check the error step Qn(H)
Continue*1
2413 • Common information: File name/Drive name corresponding to the value and correct it as QnPH
• Individual information: Program error location necessary. QnPRH
■Diagnostic Timing Check to ensure that the designated file has not
• When instruction executed been write protected.

12-38
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
[CAN'T EXE. PRG.]
• Any of the program files are using a device that
• Read the common information of the error
1
is out of the range configured in the Device tab
using the programming tool to identify the
of the PLC Parameter dialog box.
numeric value (file name). Verify the device
• After changing the device setting in the PLC
2
assignments of the program file corresponding
Parameter dialog box, only the parameters were QCPU
to the value with its parameter setting, and
written to the CPU module. LCPU
correct them as necessary.
■Collateral information
• Whenever a device setting is changed, write
• Common information: File name/Drive name
both the parameter and program file to the CPU

2500
• Individual information:-
■Diagnostic Timing
module. 3
• At power-on/At reset/STOP→RUN
[CAN'T EXE. PRG.]
After changing the index modification setting in the
PLC Parameter dialog box, only the parameters
Whenever an index modification setting is
12
were written to the CPU module.
changed in the PLC Parameter dialog box, batch- QnU
■Collateral information RUN:
write the parameter and program file to the CPU LCPU
• Common information: File name/Drive name Off
• Individual information:-
module.
ERR.: 6
■Diagnostic Timing Flicker
• At power-on/At reset/STOP→RUN
[CAN'T EXE. PRG.] CPU Status:
More than one program files exist although no Stop
Qn(H)
6
program name is entered in the Program tab of the
PLC Parameter dialog box. Enter the program names in the Program tab of QnPH
■Collateral information the PLC Parameter dialog box. Or delete QnPRH
• Common information: File name/Drive name
• Individual information:-
unnecessary programs. QnU
LCPU
7
■Diagnostic Timing
• At power-on/At reset/STOP→RUN
2501
[CAN'T EXE. PRG.]
• There are three or more program files.
8
• The program name differs from the program
contents. • Delete unnecessary program files.
■Collateral information • Match the program name with the program Q00J/Q00/Q01
• Common information: File name/Drive name contents.
• Individual information:-
■Diagnostic Timing
• At power-on/At reset/STOP→RUN

12.1.4 Error code list (2000 to 2999)

12.1 Error Code List

12-39
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
[CAN'T EXE. PRG.]
The program file is incorrect.
Or the contents of the file are not programs.
■Collateral information Ensure that the program version is ***.QPG and QCPU
• Common information: File name/Drive name the file contents are programs. LCPU
• Individual information:-
■Diagnostic Timing
• At power-on/At reset/STOP→RUN
2502
[CAN'T EXE. PRG.]
The program file is not the one for the redundant
CPU. Create a program with GX Developer or PX
■Collateral information Developer specifying the redundant CPU
QnPRH
• Common information: File name/Drive name (Q12PRH/Q25PRH) as the PLC type, and write it
• Individual information:- to the CPU module.
■Diagnostic Timing
• At power-on/At reset/STOP→RUN
RUN:
[CAN'T EXE. PRG.]
Off
There are no program files at all.
ERR.:
■Collateral information
• Check program configuration. Flicker QCPU
2503 • Common information: File name/Drive name
• Check parameters and program configuration. LCPU
• Individual information:-
CPU Status:
■Diagnostic Timing
Stop
• At power-on/At reset/STOP→RUN
[CAN'T EXE. PRG.]
Two or more SFC normal programs or control
Qn(H)
programs have been designated.
QnPH
■Collateral information • Check program configuration.
QnPRH
• Common information: File name/Drive name • Check parameters and program configuration.
QnU
• Individual information:-
LCPU
■Diagnostic Timing
2504 • At power-on/At reset/STOP→RUN
[CAN'T EXE. PRG.]
There are two or more SFC programs.
■Collateral information
• Common information: File name/Drive name Reduce the SFC programs to one. Q00J/Q00/Q01*8
• Individual information:-
■Diagnostic Timing
• At power-on/At reset/STOP→RUN
Check for illegal accesses. If any illegal access is
identified, take actions such as disabling
[REMOTE PASS.FAIL] communication of the connection.
RUN:
The count of remote password mismatches If it was identified not illegal, clear the error and
On
reached the upper limit. perform the following. (Clearing the error also
ERR.:
■Collateral information clears the remote password mismatch counts.)
2700 On
• Common information:- • Check if the remote password sent is correct.
• Individual information:- • Check if the remote password has been locked.
CPU Status:
■Diagnostic Timing • Check if concurrent access was made from
• Always Continue
multiple devices to one connection by UDP.
QnU*21
• Check if the upper limit of the remote password
LCPU
mismatch count is too low.

[SNTP OPE.ERROR] RUN:

Time setting failed when the programmable • Check if the time setting function is set up Off/On
controller was powered ON or reset. correctly. ERR.:
■Collateral information • Check if the specified SNTP server is operating Flicker/On
2710
• Common information:- normally, or if any failure has occurred on the
• Individual information:- network connected to the specified SNTP CPU Status:
■Diagnostic Timing server computer. Stop/
• When time setting function is executed Continue*1

12-40
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
• Do not detach the display unit during operation.
[DISPLAY ERROR]
The display unit was attached or detached while • Ensure that the display unit is securely 1
the CPU module is on. attached to the CPU module.
■Collateral information • Reset the CPU module and run it again. If the
2900
• Common information:- same error is displayed again, the CPU module
• Individual information:- or display unit is faulty. (Please consult your 2
■Diagnostic Timing local Mitsubishi representative, explaining a
• Always detailed description of the problem.)
[DISPLAY ERROR] RUN:
A failure was detected in the display unit. On 3
(in a initial processing) ERR.:
■Collateral information On LCPU
2901
• Common information:- • Ensure that the display unit is securely
• Individual information:-
■Diagnostic Timing
attached to the CPU module.
• Reset the CPU module and run it again. If the
CPU Status: 12
Continue
• At power-on/At reset same error code is displayed again, the cause
[DISPLAY ERROR] is a failure of the CPU module or display unit.
A failure was detected in the display unit.
(during operation)
(Please consult your local Mitsubishi
representative, explaining a detailed 6
■Collateral information description of the problem.)
2902
• Common information:-
• Individual information:-
■Diagnostic Timing 6
• Always
*1 CPU operations when an error occurred can be determined with a parameter. (LED indication varies according to the
CPU status.)
*6 Intelligent function module operations when an error occurred can be selected with a parameter from either to stop or 7
continue.
*7 This applies when the function version is A or later.
*8
*10
This applies when the function version is B or later.
This applies when the first five digits of the serial number is "04101" or later.
8
*15 This applies when the first five digits of the serial number is "09102" or later.
*17 This applies when the first five digits of the serial number is "10042" or later.
*18 This applies to the Universal model QCPU except for the Q00UJCPU.
*19 This applies to the Universal model QCPU except for the Q00UJCPU, Q00UCPU, and Q01UCPU.
*20 This applies to the Universal model QCPU except for the Q00UJCPU, Q00UCPU, Q01UCPU, and Q02UCPU.
*21 This applies to the Built-in Ethernet port QCPU.

12.1.4 Error code list (2000 to 2999)

12.1 Error Code List

12-41
 12.1.5 Error code list (3000 to 3999)

The following shows the error messages from the error code 3000 to 3999, the contents and
causes of the errors, and the corrective actions for the errors.

Error LED Status Corresponding

Error Contents and Cause Corrective Action
Code CPU Status CPU
[PARAMETER ERROR]
In a multiple CPU system, the intelligent function
module under control of another CPU is specified
in the interrupt pointer setting of the PLC
• Specify the head I/O number of the intelligent
parameter. Qn(H)*8
function module under control of the host CPU.
■Collateral information QnPH
• Delete the interrupt pointer setting of the
• Common information: File name/Drive name QnU*18
parameter.
• Individual information: Parameter number
■Diagnostic Timing
• At power-on/At reset/STOP→RUN/At writing to
programmable controller
[PARAMETER ERROR]
The PLC parameter settings for timer time limit
setting, the RUN-PAUSE contact, the common
pointer number, general data processing, number
of empty slots, system interrupt settings, baud rate
setting, and service processing setting are outside
the range for the CPU module. QCPU
■Collateral information
• Common information: File name/Drive name
• Individual information: Parameter number
■Diagnostic Timing
• At power-on/At reset/STOP→RUN/At writing to
programmable controller
[PARAMETER ERROR] RUN:
In a program memory check, the check capacity Off
has not been set within the range applicable for the ERR.:
3000 CPU module. • Read the individual information of the error Flicker
■Collateral information using the programming tool to identify the QnPH
• Common information: File name/Drive name numeric value (parameter No.). Check the CPU Status: QnPRH*12
• Individual information: Parameter number parameters corresponding to the value, and Stop
■Diagnostic Timing correct them as necessary.
• At power-on/At reset/STOP→RUN/At writing to • Rewrite corrected parameters to the CPU
programmable controller module, reload the CPU power supply and/or
[PARAMETER ERROR] reset the module.
The parameter setting in the individual information • If the same error occurs, the cause is a
of the error (SD16) is invalid. hardware failure. (Please consult your local
■Collateral information Mitsubishi representative, explaining a detailed
• Common information: File name/Drive name description of the problem.) QCPU
• Individual information: Parameter number
■Diagnostic Timing
• At power-on/At reset/STOP→RUN/At writing to
programmable controller
[PARAMETER ERROR]
The ATA card is set to the memory card slot when
the specified drive for the file register is set to
"memory card (ROM)" and [Use the following file]
or [Use the same file name as the program] (either
one is allowed) is set in the PLC file setting.
QnU*19
■Collateral information
• Common information: File name/Drive name
• Individual information: Parameter number
■Diagnostic Timing
• At power-on/At reset/STOP→RUN/At writing to
programmable controller

12-42
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
[PARAMETER ERROR]
Any of the values for the Timer Limit Setting, RUN- • Read the individual information of the error 1
PAUSE Contacts, Common Pointer No., Points using the programming tool to identify the
Occupied by Empty Slot, System Interrupt Setting, numeric value (parameter No.). Check the
or Service Processing Setting option configured in parameters corresponding to the value, and

3000
the PLC Parameter dialog box are outside the
range of the CPU module.
correct them as necessary.
• If the error occurs even after correcting the LCPU
2
■Collateral information parameters, the cause is a failure of the
• Common information: File name/Drive name program memory of the CPU module, standard
• Individual information: Parameter number
■Diagnostic Timing
RAM, or SD memory card. (Please consult your
local Mitsubishi representative, explaining a
3
• At power-on/At reset/STOP→RUN/At writing to detailed description of the problem.)
programmable controller
[PARAMETER ERROR]
The parameter settings are corrupted. 12
■Collateral information
• Common information: File name/Drive name QCPU
3001
• Individual information: Parameter number LCPU
■Diagnostic Timing 6
• At power-on/At reset/STOP→RUN/At writing to
programmable controller
[PARAMETER ERROR]
When "Use the following file" is selected for the file 6
register in the PLC file setting of the PLC
parameter dialog box, the specified file does not
exist although the file register capacity has been
Qn(H)
set.
■Collateral information
QnPH 7
QnPRH
• Common information: File name/Drive name
• Read the individual information of the error RUN:
• Individual information: Parameter number
using the programming tool to identify the Off
■Diagnostic Timing
• At power-on/At reset/STOP→RUN/At writing to numeric value (parameter No.). Check the ERR.: 8
programmable controller parameters corresponding to the value, and Flicker
correct them as necessary.
[PARAMETER ERROR] • Rewrite corrected parameters to the CPU CPU Status:
When "Use the following file" is selected for File
module, reload the CPU power supply and/or Stop
Register in the PLC File tab of the PLC Parameter
reset the module.
dialog box and "Capacity" is not set, the file
• If the same error occurs, the cause is a
register file does not exist in the specified memory.
hardware failure. (Please consult your local QnU*18
3002 ■Collateral information
Mitsubishi representative, explaining a detailed LCPU

12.1.5 Error code list (3000 to 3999)

12.1 Error Code List
• Common information: File name/Drive name
description of the problem.)
• Individual information: Parameter number
■Diagnostic Timing
• At power-on/At reset/STOP→RUN/At writing to
programmable controller
[PARAMETER ERROR]
When "Use the following file" is selected for a
device data storage file in the PLC File tab of the
PLC Parameter dialog box and "Capacity" is not
set, the device data storage file does not exist in
the specified memory. QnU
■Collateral information LCPU
• Common information: File name/Drive name
• Individual information: Parameter number
■Diagnostic Timing
• At power-on/At reset/STOP→RUN/At writing to
programmable controller
[PARAMETER ERROR]
The automatic refresh range of the multiple CPU
system exceeded the file register capacity.
Qn(H)*8
■Collateral information Change the file register file for the one refresh-
3003 QnPH
• Common information: File name/Drive name enabled in the whole range.
• Individual information: Parameter number QnU*18
■Diagnostic Timing
• When an END instruction executed

12-43
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
• Read the individual information of the error
[PARAMETER ERROR]
using the programming tool to identify the
The number of device points set in the Device tab
numeric value (parameter No.). Check the
of the PLC Parameter dialog box is outside the
parameters corresponding to the value, and
range of the specifications of the CPU module.
correct them as necessary.
■Collateral information
3003 • If the error still occurs after correcting the
• Common information: File name/Drive name
parameter settings, the cause is a failure of the
• Individual information: Parameter number
program memory of the CPU module or
■Diagnostic Timing
memory card. (Please consult your local
• At power-on/At reset/STOP→RUN/At writing to
programmable controller Mitsubishi representative, explaining a detailed
QCPU
description of the problem.)
LCPU
[PARAMETER ERROR]
The parameter file is incorrect.
Alternatively, the contents of the file are not
parameters.
■Collateral information Ensure that the parameter file version is ***.QPA
3004
• Common information: File name/Drive name and the file contents are parameters.
• Individual information: Parameter number
■Diagnostic Timing
• At power-on/At reset/STOP→RUN/At writing to
programmable controller
• Read the individual information of the error
using the programming tool to identify the
numeric value (parameter No.). Check the
[PARAMETER ERROR]
parameters corresponding to the value, and
The contents of the parameter are broken.
correct them as necessary.
■Collateral information Qn(H)*15
• Write the modified parameter items to the CPU
3005 • Common information: File name/Drive name QnPH*17
module again, and power-on the programmable
• Individual information: Parameter number QnPRH*17
controller or reset the CPU module.
■Diagnostic Timing
• At power-on/At reset/STOP→RUN • If the same error occurred, the cause is a
hardware failure. (Please consult your local
RUN:
Mitsubishi representative, explaining a detailed
Off
description of the problem.)
ERR.:
• Delete the setting of the Q02CPU' s high speed Flicker
[PARAMETER ERROR]
interrupt.
• The high speed interrupt is set in a Q02CPU.
To use high speed interrupts, change the CPU CPU Status:
• The high speed interrupt is set in a multiple CPU
module to one of the Q02H/Q06H/Q12H/ Stop
system.
Q25HCPU.
• The high speed interrupt is set when
• To use a multiple CPU system, delete the
aQA1S6†B or QA6†B is used.
setting of the high-speed interrupt.
• No module is installed at the I/O address
3006 To use high speed interrupts, change the Qn(H)*16
designated by the high speed interrupt.
system to a single CPU system.
■Collateral information
• To use either the QA1S6†B or QA6†B, delete
• Common information: File name/Drive name
the setting of the high speed interrupt.
• Individual information: Parameter number
• To use high speed interrupts, do not use the
■Diagnostic Timing
• At power-on/At reset/STOP→RUN/At writing to QA1S6†B/QA6†B.
programmable controller • Re-examine the I/O address designated by the
high speed interrupt setting.
[PARAMETER ERROR]
The parameter file in the drive specified as valid
parameter drive by the DIP switches is
inapplicable for the CPU module.
Create parameters using the programming tool
■Collateral information
3007 and write them to the drive specified as a QnPRH
• Common information: File name/Drive name
parameter-valid drive by the DIP switches.
• Individual information: Parameter number
■Diagnostic Timing
• At power-on/At reset/STOP→RUN/At writing to
programmable controller
[PARAMETER ERROR]
In a multiple CPU system, the modules for AnS, A,
Q2AS and QnA have been set to multiple control
CPUs. Re-set the parameter I/O assignment to control
■Collateral information them under one CPU module. (Change the
3009 Qn(H)*8
• Common information: File name/Drive name parameters of all CPUs in the multiple CPU
• Individual information: Parameter number system.)
■Diagnostic Timing
• At power-on/At reset/STOP→RUN/At writing to
programmable controller

12-44
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
[PARAMETER ERROR]
The parameter-set number of CPU modules differs 1
from the actual number in a multiple CPU system. The number of CPU modules in the multiple CPU
■Collateral information system must be the same as the value derived as
Qn(H)*8
3010 • Common information: File name/Drive name follows: (the number of CPU modules set in the
• Individual information: Parameter number
■Diagnostic Timing
multiple CPU setting) - (the number of PLC
(empty) slots set in the I/O assignment).
QnPH
2
• At power-on/At reset/STOP→RUN/At writing to
programmable controller
[PARAMETER ERROR]
Multiple CPU setting or control CPU setting differs
3
from that of the reference CPU settings in a
multiple CPU system.
Match the multiple CPU setting or control CPU Q00/Q01*8
3012
■Collateral information
• Common information: File name/Drive name
setting in the PLC parameter with that of the
reference CPU (CPU No.1) settings.
Qn(H)*8 12
• Individual information: Parameter number QnU
■Diagnostic Timing
• At power-on/At reset/STOP→RUN/At writing to
programmable controller 6
[PARAMETER ERROR]
Multiple CPU auto refresh setting is any of the
followings in a multiple CPU system.
• When a bit device is specified as a refresh
Check the following for the refresh setting in the 6
device, a number other than a multiple of 16 is
Multiple CPU settings dialog box, and correct it.
specified for the refresh-starting device.
• When specifying the bit device, specify a
• The device specified is other than the one that
multiple of 16 for the refresh starting device. Qn(H)*8
may be specified.
• The number of send points is an odd number.
• Specify the device that may be specified for the QnPH 7
refresh device.
■Collateral information
• Set the number of send points to an even
• Common information: File name/Drive name RUN:
number.
• Individual information: Parameter number
■Diagnostic Timing
Off
ERR.: 8
• At power-on/At reset/STOP→RUN/At writing to Flicker
programmable controller
[PARAMETER ERROR] CPU Status:
In a multiple CPU system, the multiple CPU auto Stop
refresh setting is any of the following.
• The total number of transmission points is
greater than the maximum number of refresh Check the following for the refresh setting in the

12.1.5 Error code list (3000 to 3999)

12.1 Error Code List
points. Multiple CPU settings dialog box, and correct it.
Q00/Q01*8
■Collateral information • The total number of transmission points is
• Common information: File name/Drive name within the maximum number of refresh points.
3013
• Individual information: Parameter number
■Diagnostic Timing
• At power-on/At reset/STOP→RUN/At writing to
programmable controller
[PARAMETER ERROR]
Check the following in the refresh setting in the
In a multiple CPU system, the multiple CPU auto
Multiple CPU settings dialog box, and correct the
refresh setting is any of the following.
setting.
• The device specified is other than the one that
• Specify the device that may be specified for the
may be specified.
refresh device.
• The number of send points is an odd number.
• Set the number of send points to an even
• The total number of send points is greater than
number.
the maximum number of refresh points.
• Set the total number of send points within the
• The setting of the refresh range crosses over the
range of the maximum number of refresh
boundary between the internal user device and QnU*18
points.
the extended data register (D) or extended link
• Set the refresh range so that it does not cross
register (W).
over the boundary between the internal user
• No device is set in the host CPU send range.
device and the extended data register (D) or
■Collateral information
extended link register (W).
• Common information: File name/Drive name
• For the send range of the host CPU, refresh
• Individual information: Parameter number
target device must be specified. If a send range
■Diagnostic Timing
is not necessary, delete the applicable send
• At power-on/At reset/STOP→RUN/At writing to
programmable controller range.

12-45
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
[PARAMETER ERROR]
• In a multiple CPU system, the online module
change parameter (multiple CPU system
parameter) settings differ from those of the
reference CPU.
• Match the online module change parameter
• In a multiple CPU system, the online module
with that of the reference CPU.
change setting is enabled although the CPU Qn(H)
• If the CPU module that does not support online
3014 module mounted does not support online QnPH
module change is mounted, replace it with the
module change parameter. QnU*20
CPU module that supports online module
■Collateral information
change.
• Common information: File name/Drive name
• Individual information: Parameter number
■Diagnostic Timing
• At power-on/At reset/STOP→RUN/At writing to
programmable controller
[PARAMETER ERROR]
In a multiple CPU system configuration, the CPU
verified is different from the one set in the
parameter setting. Read the individual information of the error using
■Collateral information the programming tool to identify the numeric
3015 • Common information: File name/Drive name value (parameter No./CPU No.). Check the
• Individual information: Parameter number/CPU parameters and its configuration corresponding to
No. the value, and correct them as necessary.
■Diagnostic Timing
• At power-on/At reset/STOP→RUN/At writing to
programmable controller RUN:
Off
[PARAMETER ERROR] QnU*20
ERR.:
The CPU module incompatible with multiple CPU
Flicker
synchronized boot-up is set as the target for the
synchronized boot-up in the [Multiple CPU
CPU Status:
synchronous startup setting].
Delete the CPU module incompatible with Stop
■Collateral information
3016 multiple CPU synchronized boot-up from the
• Common information: File name/Drive name
setting.
• Individual information: Parameter number/CPU
No.
■Diagnostic Timing
• At power-on/At reset/At writing to programmable
controller
Write the parameters configured in the PLC
parameter and Network parameter dialog boxes
[PARAMETER ERROR]
and remote password to a parameter-valid drive,
The parameter file is damaged.
and power on the system again or reset the CPU
■Collateral information
module.
3040 • Common information:-
If the same error occurs, the cause is a hardware
• Individual information:-
failure.
■Diagnostic Timing
(Please consult your local Mitsubishi
• At power-on/At reset Qn(H)*12
representative, explaining a detailed description
QnPH*12
of the problem.)
QnPRH*12
[PARAMETER ERROR]
Write the intelligent function module parameter to
Parameter file of intelligent function module is
the parameter-valid drive, and power on the
damaged.
system again or reset the CPU module.
■Collateral information
3041 If the same error occurs, the cause is a hardware
• Common information:-
failure. (Please consult your local Mitsubishi
• Individual information:-
representative, explaining a detailed description
■Diagnostic Timing
• At power-on/At reset of the problem.)

12-46
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
• Write the parameters configured in the PLC
parameter and Network parameter dialog 1
boxes and remote password to a parameter-
valid drive, and power on the system again or
reset the CPU module.
If the same error occurs, the cause is a 2
hardware failure. (Please consult your local
[PARAMETER ERROR]
Mitsubishi representative, explaining a detailed RUN:
The system file that have stored the remote
description of the problem.) Off
password setting information is damaged.

3042
■Collateral information
• When a valid drive for parameter is set to other
than [program memory], set the parameter file
ERR.:
Flicker
Qn(H)*12
QnPH*12
3
• Common information:-
(PARAM) at the boot file setting to be able to QnPRH*12
• Individual information:-
transmit to the program memory. CPU Status:
■Diagnostic Timing
• At power-on/At reset Write the PLC parameter, network parameter,
and remote password to a parameter-valid
Stop
12
drive, and power on the system again or reset
the CPU module.
If the same error occurs, the cause is a
hardware failure. (Please consult your local 6
Mitsubishi representative, explaining a detailed
description of the problem.)

6
[LINK PARA. ERROR]
In a multiple CPU system, the CC-Link IE
controller network module controlled by another • Delete the network parameter of the CC-Link IE
CPU is specified as the head I/O number of the controller network module controlled by another
Qn(H)*15
CC-Link IE controller network module. CPU.
■Collateral information
• Common information: File name/Drive name
• Change the setting to the head I/O number of
the CC-Link IE controller network module
QnPRH*17
QnU
7
• Individual information: Parameter number controlled by host CPU.
■Diagnostic Timing
• At power-on/At reset/STOP→RUN
[LINK PARA. ERROR]
8
The network parameter of the CC-Link IE
controller network operating as the normal station
is overwritten to the control station. Alternatively,
the network parameter for the CC-Link IE
controller network module that is operating as a
normal station has been changed to the control
Reset the CPU module.
station. (The network parameter is updated on the RUN:

12.1.5 Error code list (3000 to 3999)

12.1 Error Code List
module by resetting.) Off
■Collateral information ERR.:
• Common information: File name/Drive name Flicker
3100
• Individual information: Parameter number
■Diagnostic Timing CPU Status:
• At power-on/At reset/STOP→RUN Stop
[LINK PARA. ERROR] Qn(H)*15
• The number of modules actually mounted is • Check the network parameters and actual QnPH*17
different from that is set in Network parameter mounting status, and if they differ, make them QnPRH*17
for the CC-Link IE controller network module. matched. If any of the network parameters is QnU
• The head I/O number of the actually mounted corrected, write it to the CPU module.
module is different from the one set in the • Check the set number of extension base units.
network parameter of the CC-Link IE controller • Check the connection status of the extension
network. base units and extension cables.
• Parameter-set data cannot be used. Check the connection of the GOT if it is bus-
• The network type of CC-Link IE controller connected to the main base unit or extension
network is overwritten during power-on. (When base unit.
changing the network type, switch RESET to
RUN.) If an error occurs even after taking the above
■Collateral information measures, the cause is a hardware failure.
• Common information: File name/Drive name (Please consult your local Mitsubishi
• Individual information: Parameter number representative, explaining a detailed description
■Diagnostic Timing of the problem.)
• At power-on/At reset/STOP→RUN

12-47
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
• Check the network parameters and actual
mounting status, and if they differ, make them
[LINK PARA. ERROR] matched. If any of the network parameters is
• The CC-Link IE controller network module is corrected, write it to the CPU module.
specified for the head I/O number of network • Check the set number of extension base units.
parameter in the MELSECNET/H. • Check the connection status of the extension
• The MELSECNET/H module is specified for the base units and extension cables.
head I/O number of network parameter in the Check the connection of the GOT if it is bus-
CC-Link IE controller network. connected to the main base unit or extension
■Collateral information base unit.
• Common information: File name/Drive name
• Individual information: Parameter number If an error occurs even after taking the above
■Diagnostic Timing measures, the cause is a hardware failure.
• At power-on/At reset/STOP→RUN (Please consult your local Mitsubishi
representative, explaining a detailed description Qn(H)*15
of the problem.) QnPH*17
• Check the network parameters and actual QnPRH*17
mounting status, and if they differ, make them QnU
[LINK PARA. ERROR]
matched. If any of the network parameters is
• Although the CC-Link IE controller network
corrected, write it to the CPU module.
module is mounted, network parameter for the
• Check the set number of extension base units.
CC-Link IE controller network module is not set.
• Check the connection status of the extension
• Although the CC-Link IE controller network and
base units and extension cables.
MELSECNET/H modules are mounted, network
Check the connection of the GOT if it is bus-
parameter for the MELSECNET/H module is not RUN:
connected to the main base unit or extension
set. Off
base unit.
■Collateral information ERR.:
• Common information: File name/Drive name
3100 If an error occurs even after taking the above Flicker
• Individual information: Parameter number
measures, the cause is a hardware failure.
■Diagnostic Timing
(Please consult your local Mitsubishi CPU Status:
• At power-on/At reset/STOP→RUN
representative, explaining a detailed description Stop
of the problem.)
[LINK PARA. ERROR]
In a multiple CPU system, the MELSECNET/H
under control of another CPU is specified as the • Delete the MELSECNET/H network parameter
head I/O number in the network setting parameter of the MELSECNET/H under control of another Q00/Q01*8
of the MELSECNET/H. CPU. Qn(H)*8
■Collateral information • Change the setting to the head I/O number of QnPH
• Common information: File name/Drive name the MELSECNET/H under control of the host QnU*18
• Individual information: Parameter number CPU.
■Diagnostic Timing
• At power-on/At reset/STOP→RUN
[LINK PARA. ERROR]
The network parameter of the MELSECNET/H
operating as the normal station is overwritten to
the control station.
Or, the network parameter of the MELSECNET/H
Qn(H)*8
operating as the control station is overwritten to
QnPH
the normal station. (The network parameter is Reset the CPU module.
QnPRH
updated on the module by resetting.)
QnU
■Collateral information
• Common information: File name/Drive name
• Individual information: Parameter number
■Diagnostic Timing
• At power-on/At reset/STOP→RUN

12-48
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
• Check the network parameters and actual
[LINK PARA. ERROR]
• The number of modules actually mounted is mounting status, and if they differ, make them 1
different from that is set in Network parameter matched. If any of the network parameters is
for MELSECNET/H. corrected, write it to the CPU module.
• The head I/O number of actually installed • Check the set number of extension base units.
modules is different from that designated in the • Check the connection status of the extension 2
network parameter of MELSECNET/H. base units and extension cables.
• Parameter-set data cannot be used. Check the connection of the GOT if it is bus-
• The network type of MELSECNET/H is connected to the main base unit or extension

3
3100 QCPU
overwritten during power-on. (When changing base unit.
the network type, switch RESET to RUN.)
• The mode switch of MELSECNET/H module*12 If an error occurs even after taking the above
is outside the range. measures, the cause is a hardware failure.
■Collateral information
• Common information: File name/Drive name
(Please consult your local Mitsubishi
representative, explaining a detailed description 12
• Individual information: Parameter number of the problem.)
■Diagnostic Timing • Set the mode switch of MELSECNET/H
• At power-on/At reset/STOP→RUN module*12 within the range.
[LINK PARA. ERROR]
6
The link refresh range exceeded the file register
capacity. Qn(H)*8
■Collateral information
• Common information: File name/Drive name
Change the file register file for the one that
enables entire range refresh.
QnPH
QnPRH 6
• Individual information: Parameter number QnU *18
■Diagnostic Timing RUN:
• When an END instruction executed Off
[LINK PARA. ERROR] ERR.: 7
• When the station number of the MELSECNET/H Flicker
module is 0, the PLC-to-PLC network parameter
has been set. CPU Status:
• When the station number of the MELSECNET/H
Correct the type or station number of the
Stop
Qn(H)*8
8
module is other than 0, the remote master
MELSECNET/H module in the network parameter QnPH
parameter setting has been made.
to meet the used system. QnPRH
■Collateral information
• Common information: File name/Drive name
• Individual information: Parameter number
3101 ■Diagnostic Timing
• At power-on/At reset/STOP→RUN
• Check the network parameters and mounting

12.1.5 Error code list (3000 to 3999)

12.1 Error Code List
status, and if they differ, match the network
parameters and mounting status.
If any network parameter has been corrected,
write it to the CPU module.
[LINK PARA. ERROR]
• Confirm the setting of the number of extension
The refresh parameter for the CC-Link IE controller
stages of the extension base units.
network is outside the range. Qn(H)*15
• Check the connection status of the extension
■Collateral information QnPH*17
base units and extension cables.
• Common information: File name/Drive name QnPRH*17
When the GOT is bus-connected to the main
• Individual information: Parameter number QnU
base unit and extension base units, also check
■Diagnostic Timing
• At power-on/At reset/STOP→RUN their connection status.

If the error occurs after the above checks, the

cause is a hardware fault. (Please consult your
local Mitsubishi representative, explaining a
detailed description of the problem.)

12-49
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
[LINK PARA. ERROR]
• Check the network parameters and mounting
• The network No. specified by a network
status, and if they differ, match the network
parameter is different from that of the actually
parameters and mounting status.
mounted network.
If any network parameter has been corrected,
• The head I/O No. specified by a network
write it to the CPU module.
parameter is different from that of the actually
• Confirm the setting of the number of extension
mounted I/O unit.
stages of the extension base units.
• The network class specified by a network
• Check the connection status of the extension
parameter is different from that of the actually
base units and extension cables. QCPU
mounted network.
When the GOT is bus-connected to the main
• The network refresh parameter of the
base unit and extension base units, also check
MELSECNET/H, MELSECNET/10 is out of the
their connection status.
specified area.
■Collateral information
If the error occurs after the above checks, the
• Common information: File name/Drive name
cause is a hardware fault. (Please consult your
• Individual information: Parameter number
local Mitsubishi representative, explaining a
■Diagnostic Timing
• At power-on/At reset/STOP→RUN detailed description of the problem.)

[LINK PARA. ERROR]

A multi-remote I/O network was configured using a
module that does not support the MELSECNET/H
multi-remote I/O network.
Use a module that supports the MELSECNET/H
■Collateral information QnPH
multi-remote I/O network.
• Common information: File name/Drive name
• Individual information: Parameter number
■Diagnostic Timing
• At power-on/At reset/STOP→RUN
[LINK PARA. ERROR]
• The system A of the MELSECNET/H remote
master station has been set to other than Station
No. 0.
• Set the system A of the MELSECNET/H remote
• The system B of the MELSECNET/H remote
master station to Station No. 0. RUN:
master station has been set to Station No. 0. QnPRH
• Set the system B of the MELSECNET/H remote Off
■Collateral information
master station to any of Station No. 1 to 64. ERR.:
• Common information: File name/Drive name
3101 Flicker
• Individual information: Parameter number
■Diagnostic Timing
• At power-on/At reset/STOP→RUN CPU Status:
Stop
[LINK PARA. ERROR]
Since the number of points of the B/W device set
in [Device] of the PLC parameter is lower than the
number of B/W refresh device points shown in the
following table when parameters of the
MELSECNET/H are not set, the refresh between
the CPU module and the MELSECNET/H cannot
be performed.
Refresh No. of refresh device No. of refresh device
device points of B device points of W device Qn(H)*14
Set the refresh parameter of the MELSECNET/H
8192 points 8192 points
QnPH*14
1 (8192 points×1
module)
(8192 points×1
module)
in accordance with the number of points of B/W
8192 points 8192 points devices set in [Device] of the PLC parameter. QnPRH*14
No. of (4096 points×2 (4096 points×2
mounted
2
modules) modules) QnU
network 6144 points 6144 points
modules 3 (2048 points×3 (2048 points×3
modules) modules)
8192 points 8192 points
4 (2048 points×4 (2048 points×4
modules) modules)

■Collateral information
• Common information: File name/Drive name
• Individual information: Parameter number
■Diagnostic Timing
• At power-on/At reset/STOP→RUN
[LINK PARA. ERROR]
The setting of the network refresh range crosses
over the boundary between the internal user
device and the extended data register (D) or Set the network refresh range so that it does not
extended link register (W). cross over the boundary between the internal
QnU
■Collateral information user device and the extended data register (D) or
• Common information: File name/Drive name extended link register (W).
• Individual information: Parameter number
■Diagnostic Timing
• At power-on/At reset/STOP→RUN

12-50
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
[LINK PARA. ERROR]
A CC-Link IE controller network parameter error 1
was detected. Qn(H)*15
■Collateral information QnPH*17
• Common information: File name/Drive name QnPRH*17
• Individual information: Parameter number
■Diagnostic Timing
QnU 2
• At power-on/At reset/STOP→RUN • Correct and write the network parameters.
• If the error occurs after correction, it suggests a
[LINK PARA. ERROR] hardware fault. (Please consult your local
• The network module detected a network
parameter error.
Mitsubishi representative, explaining a detailed 3
description of the problem.)
• A MELSECNET/H network parameter error was
detected.
QCPU
■Collateral information
• Common information: File name/Drive name 12
• Individual information: Parameter number
■Diagnostic Timing
• At power-on/At reset/STOP→RUN
[LINK PARA. ERROR] 6
The station No. specified in pairing setting are not
correct.
• The stations are not numbered consecutively.
• Pairing setting has not been made for the CPU
Refer to the troubleshooting of the network
module, and if the error is due to incorrect pairing
QnPRH
6
module at the normal station.
setting, reexamine the pairing setting of the
■Collateral information
network parameter.
• Common information: File name/Drive name
• Individual information: Parameter number
■Diagnostic Timing
7
• At power-on/At reset/STOP→RUN
[LINK PARA. ERROR] RUN:
The CC-Link IE controller network module whose
first 5 digits of serial No. is "09041" or earlier is
Off
ERR.: 8
3102 mounted. Flicker
Mount the CC-Link IE controller network module
■Collateral information QnU
whose first 5 digits of serial No. is "09042" or later.
• Common information: File name/Drive name CPU Status:
• Individual information: Parameter number Stop
■Diagnostic Timing
• At power-on/At reset/STOP→RUN
[LINK PARA. ERROR]

12.1.5 Error code list (3000 to 3999)

12.1 Error Code List
Group cyclic function in CC-Link IE controller
network that does not correspond to group cyclic
function is set.
Set group cyclic function in function version D or
■Collateral information QnU*10
later of CC-Link IE controller network.
• Common information: File name/Drive name
• Individual information: Parameter number
■Diagnostic Timing
• At power-on/At reset/STOP→RUN
[LINK PARA. ERROR]
Paring setting in CC-Link IE controller network
modules installed in CPUs except for redundant Q00J/Q00/Q01
CPUs was performed.
Examine the paring setting for the network Qn(H)*17
■Collateral information
parameter in the control station. QnPH*17
• Common information: File name/Drive name
• Individual information: Parameter number QnU*17
■Diagnostic Timing
• At power-on/At reset/STOP→RUN
[LINK PARA. ERROR]
• LB/LW own station send range at LB/LW4000 or
later was set.
• LB/LW setting (2) was performed.
Correct the network range assignments of the
■Collateral information Q00J/Q00/Q01
network parameter for the control station.
• Common information: File name/Drive name
• Individual information: Parameter number
■Diagnostic Timing
• At power-on/At reset/STOP→RUN

12-51
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
[LINK PARA. ERROR]
In a multiple CPU system, Ethernet interface
module under control of another station is • Delete the Ethernet network parameter of
specified to the start I/O number of the Ethernet Ethernet interface module under control of Q00/Q01*8
network parameter. another station. Qn(H)*8
■Collateral information • Change the setting to the start I/O number of QnPH
• Common information: File name/Drive name Ethernet interface module under control of the QnU*18
• Individual information: Parameter number host station.
■Diagnostic Timing
• At power-on/At reset/STOP→RUN
[LINK PARA. ERROR]
• Although the number of modules has been set to
one or greater number in the Ethernet module
count parameter setting, the number of actually
mounted module is zero.
• The start I/O No. of the Ethernet network
parameter differs from the I/O No. of the actually QCPU
mounted module.
3103 ■Collateral information
• Common information: File name/Drive name
• Individual information: Parameter number
■Diagnostic Timing
• At power-on/At reset/STOP→RUN
[LINK PARA. ERROR]
• In the redundant system, although "Ethernet
(Main base)" is selected for Network type, the
Ethernet module is mounted on the extension
base unit.
RUN:
• In the redundant system, although "Ethernet
• Correct and write the network parameters. Off
(Extension base)" is selected for Network type,
• If the error occurs after correction, it suggests a ERR.: QnPRH*15
the Ethernet module is mounted on the main
hardware fault. (Please consult your local Flicker
base unit.
Mitsubishi representative, explaining a detailed
■Collateral information
description of the problem.) CPU Status:
• Common information: File name/Drive name
Stop
• Individual information: Parameter number
■Diagnostic Timing
• At power-on/At reset/STOP→RUN
[LINK PARA. ERROR]
• The Ethernet, MELSECNET/H and
MELSECNET/10 use the same network number.
• The network number, station number or group
number set in the network parameter is out of
range.
• The specified I/O number is outside the range of
3104 the used CPU module. QCPU
• The Ethernet-specific parameter setting is not
normal.
■Collateral information
• Common information: File name/Drive name
• Individual information: Parameter number
■Diagnostic Timing
• At power-on/At reset/STOP→RUN
[LINK PARA. ERROR]
In a multiple CPU system, the CC-Link module
under control of another station is specified as the • Delete the CC-Link network parameter of the
head I/O number of the CC-Link network CC-Link module under control of another Q00/Q01*8
parameter. station. Qn(H)*8
3105
■Collateral information • Change the setting to the start I/O number of QnPH
• Common information: File name/Drive name the CC-Link module under control of the host QnU*18
• Individual information: Parameter number station.
■Diagnostic Timing
• At power-on/At reset/STOP→RUN

12-52
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
[LINK PARA. ERROR]
• Although one or more CC-Link modules were 1
configured in the Network Parameter dialog box,
no CC-Link modules are installed in the system.
The start I/O number in the common parameters
is different from that of the actually mounted
module.
2
QCPU
• The station type of the CC-Link module count
L02CPU
setting parameters is different from that of the
actually mounted station.
■Collateral information
3
• Common information: File name/Drive name
• Individual information: Parameter number
■Diagnostic Timing
• At power-on/At reset/STOP→RUN 12
[LINK PARA. ERROR]
• Although two or more CC-Link modules were
configured in the Network Parameter dialog box,
only one CC-Link modules are installed in the 6
system. The start I/O number of the common • Correct and write the network parameters.
parameter specified in the Network Parameter • If the error occurs after correction, it suggests a
3105 dialog box does not correspond to the system. hardware fault. (Please consult your local
• The station type specified in the Network
Parameter dialog box for CC-Link does not
Mitsubishi representative, explaining the
detailed description of the problem.)
L26CPU-BT 6
correspond to the system.
■Collateral information
• Common information: File name/Drive name
• Individual information: Parameter number
7
■Diagnostic Timing
At power-on/At reset/STOP→RUN
[LINK PARA. ERROR]
• CC-Link module whose station type is set to RUN: 8
"master station (compatible with redundant Off
function)" is mounted on the extension base unit ERR.:
in the redundant system. Flicker
• CC-Link module whose station type is set to
"master station (extension base)" is mounted on CPU Status: QnPRH*15
the main base unit in the redundant system. Stop
■Collateral information

12.1.5 Error code list (3000 to 3999)

12.1 Error Code List
• Common information: File name/Drive name
• Individual information: Parameter number
■Diagnostic Timing
• At power-on/At reset/STOP→RUN
[LINK PARA. ERROR]
The CC-Link link refresh range exceeded the file
Qn(H)*8
register capacity.
QnPH
■Collateral information Change the file register file for the one refresh-
QnPRH
• Common information: File name/Drive name enabled in the whole range.
QnU
• Individual information: Parameter number
LCPU
■Diagnostic Timing
• When an END instruction executed
[LINK PARA. ERROR]
The network refresh parameter for CC-Link is out
of range.
■Collateral information QCPU
Check the parameter setting.
• Common information: File name LCPU
3106
• Individual information: Parameter number
■Diagnostic Timing
• At power-on/At reset/STOP→RUN
[LINK PARA. ERROR]
The setting of the network refresh range crosses
over the boundary between the internal user
device and the extended data register (D) or Set the network refresh range so that it does not
extended link register (W). cross over the boundary between the internal QnU
■Collateral information user device and the extended data register (D) or LCPU
• Common information: File name extended link register (W).
• Individual information: Parameter number
■Diagnostic Timing
• At power-on/At reset/STOP→RUN

12-53
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
[LINK PARA. ERROR]
• The CC-Link parameter setting is incorrect.
• The set mode is not allowed for the version of
the mounted CC-Link module.
QCPU
3107 ■Collateral information Check the parameter setting.
LCPU
• Common information: File name
• Individual information: Parameter number
■Diagnostic Timing
• At power-on/At reset/STOP→RUN
[SFC PARA. ERROR]
The parameter setting is illegal.
• The block 0 does not exist although "Autostart
Q00J/Q00/Q01*8
Block 0" was selected in the SFC tab in the PLC
QnPH
Parameter dialog box.
3200 QnPRH
■Collateral information
QnU
• Common information: File name
LCPU
• Individual information: Parameter number
■Diagnostic Timing
• STOP→RUN
[SFC PARA. ERROR]
The block parameter setting is illegal.
■Collateral information
3201 • Common information: File name
• Individual information: Parameter number
■Diagnostic Timing RUN:
Read common information of the error using the
• STOP→RUN Off
programming tool to identify the numeric value
ERR.: Qn(H)
[SFC PARA. ERROR] (program error location). Check the error step
Flicker QnPH
The number of step relays specified in the device corresponding to the value, and correct it as
QnPRH
setting of the PLC parameter dialog box is less necessary.
CPU Status:
than that used in the program.
3202 Stop
■Collateral information
• Common information: File name
• Individual information: Parameter number
■Diagnostic Timing
• STOP→RUN
[SFC PARA. ERROR]
For the execution type of the SFC program, other
than "Scan" is selected in the Program tab of the Qn(H)
PLC Parameter dialog box. QnPH
3203 ■Collateral information QnPRH
• Common information: File name QnU
• Individual information: Parameter number LCPU
■Diagnostic Timing
• At power-on/At reset/STOP→RUN*5
[SP. PARA ERROR]
The start I/O number in the intelligent function
module parameter set on GX Configurator differs
from the actual I/O number.
■Collateral information QCPU
3300 Check the parameter setting.
• Common information: File name LCPU
• Individual information: Parameter number*4
■Diagnostic Timing
• At power-on/At reset/STOP→RUN/At writing to
programmable controller

12-54
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
[SP. PARA ERROR]
• The refresh setting of the intelligent function 1
module exceeded the file register capacity.
• The intelligent function module set in GX Q00J/Q00/Q01
Configurator differs from the actually mounted • Change the file register file for the one which Qn(H)*8
module.
■Collateral information
allows refresh in the whole range.
• Check the parameter setting.
QnPH 2
QnPRH
• Common information: File name • Check the auto refresh setting. QnU
• Individual information: Parameter number*4 LCPU
■Diagnostic Timing
• At power-on/At reset/STOP→RUN/At writing to
3
programmable controller
[SP. PARA ERROR]
The intelligent function module's refresh parameter
setting is outside the available range.
12
■Collateral information
3301 • Check the parameter setting. QCPU
• Common information: File name
• Check the auto refresh setting. LCPU
number*4
• Individual information: Parameter
■Diagnostic Timing 6
• At power-on/At reset/STOP→RUN/At writing to
programmable controller
[SP. PARA ERROR]
The setting of the refresh parameter range crosses
RUN:
6
over the boundary between the internal user
Off
device and the extended data register (D) or
Set the refresh parameter range so that it does ERR.:
extended link register (W).
■Collateral information
not cross over the boundary between the internal
user device and the extended data register (D) or
Flicker QnU
LCPU
7
• Common information: File name
extended link register (W). CPU Status:
• Individual information: Parameter number*4
Stop
■Diagnostic Timing
• At power-on/At reset/STOP→RUN/At writing to
programmable controller
8
[SP. PARA ERROR]
The intelligent function module's refresh parameter
are abnormal.
■Collateral information
QCPU
3302 • Common information: File name Check the parameter setting.
*4 LCPU
• Individual information: Parameter number
■Diagnostic Timing

12.1.5 Error code list (3000 to 3999)

12.1 Error Code List
• At power-on/At reset/STOP→RUN/At writing to
programmable controller
[SP. PARA ERROR]
In a multiple CPU system, the automatic refresh
setting or other parameter setting was made to the • Delete the automatic refresh setting or other
intelligent function module under control of another parameter setting of the intelligent function
Q00/Q01*8
station. module under control of another CPU.
Qn(H)*8
3303 ■Collateral information • Change the setting to the automatic refresh
QnPH
• Common information: File name/Drive name setting or other parameter setting of the
• Individual information: Parameter number intelligent function module under control of the QnU*18
■Diagnostic Timing host CPU.
• At power-on/At reset/STOP→RUN/At writing to
programmable controller

12-55
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
[REMOTE PASS. ERR.]
The head I/O number of the target module of the
Qn(H)*8
remote password is set to other than 0H to 0FF0H.
QnPH
■Collateral information Change the head I/O number of the target module
QnPRH
• Common information:- to be within the 0H to 0FF0H range.
• Individual information:- QnU*15
■Diagnostic Timing LCPU
• At power-on/At reset/STOP→RUN
[REMOTE PASS. ERR.]
The head I/O number of the target module of the
remote password is set to other than 0H to 07E0H.
■Collateral information Change the head I/O number of the target module
Q02UCPU
• Common information:- to be within the 0H to 07E0H range.
3400 • Individual information:-
■Diagnostic Timing
• At power-on/At reset/STOP→RUN
[REMOTE PASS. ERR.]
For the start I/O number of the module targeted by
the remote password, the value outside the
following range is specified. Correct the start I/O number value of the module
Q00JCPU: 0H to 1E0H targeted by the remote password within the
Q00CPU/Q01CPU: 0H to 3E0H following range. Q00J/Q00/Q01*8
■Collateral information • Q00JCPU: 0H to 1E0H
• Common information:- • Q00CPU/Q01CPU: 0H to 3E0H
• Individual information:-
■Diagnostic Timing RUN:
• At power-on/At reset/STOP→RUN
Off
[REMOTE PASS. ERR.] ERR.:
Position specified as the head I/O number of the Flicker
remote password file is incorrect due to one of the
following reasons: CPU Status:
• Module is not loaded. Stop
• Other than a the intelligent function module (I/O
module)
• The intelligent function module installed is other
Install the serial communication module, modem Qn(H)*8
than a serial communication module, modem
interface module, or Ethernet module of function QnPH
interface module, or Ethernet module.
version B or later in the position specified with the QnPRH
• The function version of the serial communication
start I/O No. of the remote password. QnU
module and Ethernet module installed is A.
• The intelligent function module where remote
password is available is not mounted.
■Collateral information
3401 • Common information:-
• Individual information:-
■Diagnostic Timing
• At power-on/At reset/STOP→RUN
[REMOTE PASS. ERR.]
The position specified with the start I/O number of
the remote password is invalid due to one of the
following reasons:
• No module In a position specified with a start I/O number of
• The intelligent function module installed is other the remote password, install the intelligent
LCPU
than a serial communication module. function module where the remote password is
■Collateral information available.
• Common information:-
• Individual information:-
■Diagnostic Timing
• At power-on/At reset/STOP→RUN

12-56
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
[REMOTE PASS. ERR.]
Any of the following modules is not mounted on the 1
slot specified for the head I/O number of the
remote password. Mount the following modules according to the
• Serial communication module of function position specified with the start I/O number of the
version B or later
• Ethernet module of function version B or later
remote password.
• Serial communication module of function
2
Q00J/Q00/Q01*8
• Modem interface module of function version B or version B or later
later • Ethernet module of function version B or later
RUN:
■Collateral information
• Common information:-
• Modem interface module of function version B
or later
Off 3
ERR.:
• Individual information:-
3401 Flicker
■Diagnostic Timing
• At power-on/At reset/STOP→RUN
[REMOTE PASS. ERR.]
CPU Status:
Stop
12
Serial communication module, modem interface
module or Ethernet module of function version B or
later controlled by another CPU was specified in a
multiple CPU system.
• Change it for the Ethernet module of function
version B or later connected by the host CPU.
Qn(H)*8
QnPH
6
■Collateral information
• Delete the remote password setting. QnU*18
• Common information:-
• Individual information:-
■Diagnostic Timing
• At power-on/At reset/STOP→RUN
6
*4 The parameter No. can be derived by "dividing the start I/O number of the intelligent function module set by GX
Configurator" by 10H.
*5 The diagnostic timing of CPU modules except for Universal QCPU and LCPU can be performed only when switching the 7
CPU module status from STOP to RUN.
*8 The function version is B or later.
*12 This applies when the first five digits of the serial number is "07032" or later.
*14 This applies when the first five digits of the serial number is "08102" or later. 8
*15 This applies when the first five digits of the serial number is "09102" or later.
*16 This applies when the first five digits of the serial number is "09082" or later.
*17 This applies when the first five digits of the serial number is "10042" or later.
*18 The Universal model QCPU except the Q00UJCPU.
*19 This applies to the Universal model QCPU except for the Q00UJCPU, Q00UCPU, and Q01UCPU.
*20 This applies to the Universal model QCPU except for the Q00UJCPU, Q00UCPU, Q01UCPU, and Q02UCPU.

12.1.5 Error code list (3000 to 3999)

12.1 Error Code List

12-57
 12.1.6 Error code list (4000 to 4999)

The following shows the error messages from the error code 4000 to 4999, the contents and
causes of the errors, and the corrective actions for the errors.

Error
LED Status Corresponding
Code Error Contents and Cause Corrective Action
CPU Status CPU
(SD0)
[INSTRCT. CODE ERR]
• The program contains an instruction code that
cannot be decoded.
• An unusable instruction is included in the
program.
QCPU
4000 ■Collateral information
LCPU
• Common information: Program error location
• Individual information:-
■Diagnostic Timing
• At power-on/At reset/STOP→RUN/When
instruction executed
[INSTRCT. CODE ERR]
The program contains a dedicated instruction for
Q00J/Q00/Q01*8
SFC although it is not an SFC program.
Qn(H)
■Collateral information
QnPH
4001 • Common information: Program error location
QnPRH
• Individual information:-
QnU
■Diagnostic Timing
• At power-on/At reset/STOP→RUN/When LCPU
instruction executed
[INSTRCT. CODE ERR]
• The name of dedicated instruction specified by
RUN:
the program is incorrect.
Read common information of the error using the Off
• The dedicated instruction specified by the
programming tool to identify the numeric value ERR.:
program cannot be executed by the specified
(program error location). Check the error step Flicker
module.
4002 corresponding to the value, and correct it as
■Collateral information
necessary. CPU Status:
• Common information: Program error location
Stop
• Individual information:-
■Diagnostic Timing
• At power-on/At reset/STOP→RUN/When
instruction executed
[INSTRCT. CODE ERR]
The number of devices for the dedicated
instruction specified by the program is incorrect. QCPU
■Collateral information LCPU
4003 • Common information: Program error location
• Individual information:-
■Diagnostic Timing
• At power-on/At reset/STOP→RUN/When
instruction executed
[INSTRCT. CODE ERR]
The device which cannot be used by the dedicated
instruction specified by the program is specified.
■CollateralCollateral information
4004 • Common information: Program error location
• Individual information:-
■Diagnostic Timing
• At power-on/At reset/STOP→RUN/When
instruction executed

12-58
 Error
LED Status Corresponding
Code Error Contents and Cause Corrective Action
CPU Status CPU
(SD0)
[MISSING END INS.] 1
There is no END (FEND) instruction in the
program.
■Collateral information QCPU
2
4010
• Common information: Program error location LCPU
• Individual information:-
■Diagnostic Timing
• At power-on/At reset/STOP→RUN
[CAN'T SET(P)]
• The total points of the pointers used in the
3
program exceeded 4096 points.
• The total points of the local pointers used in the Qn(H)
QnPH
program exceeded the start number of the
common pointer. QnPRH 12
■Collateral information QnU*19
• Common information: Program error location LCPU
• Individual information:-
■Diagnostic Timing 6
• At power-on/At reset/STOP→RUN
4020
[CAN'T SET(P)]
• The total points of the pointers used in the RUN:
program exceeded 512 points. Read common information of the error using the
programming tool to identify the numeric value
Off
ERR.:
6
• The total points of the local pointers used in the
program exceeded the start number of the (program error location). Check the error step Flicker
common pointer. corresponding to the value, and correct it as Q00UJ/Q00U/Q01U
■Collateral information
• Common information: Program error location
necessary. CPU Status:
Stop
7
• Individual information:-
■Diagnostic Timing
• At power-on/At reset/STOP→RUN
[CAN'T SET(P)]
8
• The common pointer Nos. assigned to files
overlap.
• The local pointer Nos. assigned to files overlap.
4021 ■Collateral information
• Common information: Program error location
• Individual information:-
■Diagnostic Timing
QCPU

12.1.6 Error code list (4000 to 4999)

12.1 Error Code List
• At power-on/At reset/STOP→RUN
LCPU
[CAN'T SET(I)]
The allocation pointer Nos. assigned by files
overlap.
■Collateral information
4030
• Common information: Program error location
• Individual information:-
■Diagnostic Timing
• At power-on/At reset/STOP→RUN

12-59
 Error
LED Status Corresponding
Code Error Contents and Cause Corrective Action
CPU Status CPU
(SD0)
[OPERATION ERROR]
The instruction cannot process the contained data. Read common information of the error using the
■Collateral information programming tool to identify the numeric value
QCPU
• Common information: Program error location (program error location). Check the error step
LCPU
• Individual information:- corresponding to the value, and correct it as
■Diagnostic Timing necessary.
• When instruction executed
[OPERATION ERROR]
An error occurred on the SP.FREAD or • Take measurements against noise.
SP.FWRITE instruction during accessing the ATA • Reset and restart the CPU module. If the same Qn(H)
or SD memory card. error code is displayed again, the cause is a QnPH
■Collateral information hardware failure of the ATA card or SD memory QnPRH
4100
• Common information: Program error location card. (Please consult your local Mitsubishi QnU*19
• Individual information:- representative, explaining a detailed LCPU
■Diagnostic Timing description of the problem.)
• When instruction executed
[OPERATION ERROR]
The file being accessed by other functions with
• Stop the file accessed with other functions to
SP.FWRITE instruction was accessed.
execute SP.FWRITE instruction.
■Collateral information QnU*19
• Stop the access with other functions and the
• Common information: Program error location LCPU
SP.FWRITE instruction to execute at same
• Individual information:-
time.
■Diagnostic Timing
• When instruction executed
[OPERATION ERROR] RUN:
• The number of setting data dealt with the Off/On
instruction exceeds the applicable range. ERR.:
• The storage data and constant of the device Flicker/On
specified by the instruction exceeds the
applicable range. CPU Status:
• When writing to the host CPU shared memory, Stop/
the write prohibited area is specified for the write
Continue*1
destination address.
• The range of storage data of the device
specified by the instruction is duplicated.
• The device specified by the instruction exceeds QCPU
the range of the number of device points. LCPU
• The interrupt pointer No. specified by the
instruction exceeds the applicable range. Read common information of the error using the
• A link direct device, intelligent function module programming tool to identify the numeric value
4101 device, and cyclic transmission area device are (program error location). Check the error step
specified for both (S) and (D) with the BMOV corresponding to the value, and correct it as
instruction. necessary.
■Collateral information
• Common information: Program error location
• Individual information:-
■Diagnostic Timing
• When instruction executed
[OPERATION ERROR]
• The storage data of file register specified by the
instruction exceeds the applicable range. Or, file
register is not set.
QnU*18
■Collateral information
LCPU
• Common information: Program error location
• Individual information:-
■Diagnostic Timing
• When instruction executed

12-60
 Error
LED Status Corresponding
Code Error Contents and Cause Corrective Action
CPU Status CPU
(SD0)
[OPERATION ERROR] 1
• The block data that crosses over the boundary
between the internal user device and the
extended data register (D) or extended link
2
Read common information of the error using the
register is specified (including 32-bit binary, real
programming tool to identify the numeric value
number (single precision, double precision), QnU
4101 (program error location). Check the error step
indirect address, and control data). LCPU
corresponding to the value, and correct it as RUN:
■Collateral information
necessary. Off/On
• Common information: Program error location
• Individual information:-
ERR.: 3
Flicker/On
■Diagnostic Timing
• When instruction executed
CPU Status:
[OPERATION ERROR]
In a multiple CPU system, the link direct device
Stop/
12
Continue*1
(J†\†) was specified for the network module • Delete from the program the link direct device *8
Q00/Q01
under control of another station. which specifies the network module under
Qn(H)*8
4102 ■Collateral information control of another CPU.
• Common information: Program error location • Using the link direct device, specify the network
QnPH
QnU*18
6
• Individual information:- module controlled by the own station.
■Diagnostic Timing
• When instruction executed
[OPERATION ERROR] 6
• The network No. or station No. specified for the
dedicated instruction is wrong.
• The link direct device (J†\†) setting is incorrect.
• The module No./network No./number of
character strings exceeds the range that can be
7
QCPU
specified.
■Collateral information
• Common information: Program error location
• Individual information:- 8
■Diagnostic Timing
• When instruction executed
[OPERATION ERROR]
• The module number specified with a dedicated
instruction is incorrect.
• The module number, network number, or the
4102
number of character strings specified with a RUN:

12.1.6 Error code list (4000 to 4999)

12.1 Error Code List
dedicated instruction exceeded the allowable Off/On
Read common information of the error using the LCPU
range. ERR.:
programming tool to identify the numeric value
■Collateral information Flicker/On
(program error location). Check the error step
• Common information: Program error location
corresponding to the value, and correct it as
• Individual information:- CPU Status:
necessary.
■Diagnostic Timing Stop/
• When instruction executed Continue*1
[OPERATION ERROR]
The character string (" ") specified by a dedicated
instruction cannot be used for the character string.
■Collateral information QnU
• Common information: Program error location LCPU
• Individual information:-
■Diagnostic Timing
• When instruction executed
[OPERATION ERROR]
The configuration of the PID dedicated instruction
Q00J/Q00/Q01*8
is incorrect.
Qn(H)
■Collateral information
4103 QnPRH
• Common information: Program error location
QnU
• Individual information:-
LCPU
■Diagnostic Timing
• When instruction executed
[OPERATION ERROR]
RUN:
PLOADP/PUNLOADP/PSWAPP instructions were
Off/On
executed while setting program memory check. • Delete the setting for the program memory
ERR.:
■Collateral information check.
4105 Flicker/On QnPH*12
• Common information: Program error location • When using the program memory check, delete
• Individual information:- PLOADP/PUNLOADP/PSWAPP instructions.
CPU Status:
■Diagnostic Timing
• When instruction executed Stop/Continue

12-61
 Error
LED Status Corresponding
Code Error Contents and Cause Corrective Action
CPU Status CPU
(SD0)

[OPERATION ERROR] RUN:

33 or more multiple CPU dedicated instructions Off/On Q00/Q01*8
were executed from one CPU module. Using the multiple CPU dedicated instruction ERR.: Qn(H)*8
■Collateral information completion bit, provide interlocks to prevent one Flicker/On QnPH
4107
• Common information: Program error location CPU module from executing 33 or more multiple Q00UCPU
• Individual information:- CPU dedicated instructions. CPU Status: Q01UCPU
■Diagnostic Timing Stop/ Q02UCPU
• When instruction executed Continue*1
[OPERATION ERROR] RUN:
With high speed interrupt setting PR, PRC,
Off/On
UDCNT1, UDCNT2, PLSY or PWM instruction is
Delete the high-speed interrupt setting. ERR.:
executed.
When using high-speed interrupt, delete the PR, Flicker/On
4109 ■Collateral information Qn(H)*21
PRC, UDCNT1, UDCNT2, PLSY and PWM
• Common information: Program error location
instructions. CPU Status:
• Individual information:-
Stop/
■Diagnostic Timing
• When instruction executed Continue*1

[OPERATION ERROR]
An attempt was made to perform write/read to/from
the CPU shared memory write/read disable area of
the own station CPU module with the instruction.
Q00/Q01*8
4111 ■Collateral information
RUN: QnU
• Common information: Program error location
Off/On
• Individual information:- Read common information of the error using the
ERR.:
■Diagnostic Timing programming tool to identify the numeric value
Flicker/On
• When instruction executed (program error location). Check the error step
[OPERATION ERROR] corresponding to the value, and correct it as
CPU Status:
The CPU module that cannot be specified with the necessary.
Stop/
multiple CPU dedicated instruction was specified.
Continue*1
■Collateral information Q00/Q01*8
4112
• Common information: Program error location QnU*18
• Individual information:-
■Diagnostic Timing
• When instruction executed
[OPERATION ERROR]
• When the SP.DEVST instruction is executed, the
number of writing to the standard ROM of the • Check that the number of execution of the
day exceeds the value specified by SD695. SP.DEVST instruction is proper.
• The value outside the specified range is set to • Execute the SP.DEVST instruction again on or
QnU
4113 SD695. after the following day. Or change the value in
LCPU
■Collateral information SD695. RRUN:
• Common information: Program error location • Correct the value of SD695 so that it does not Off/On
• Individual information:- exceed the range. ERR.:
■Diagnostic Timing Flicker/On
• When instruction executed
[OPERATION ERROR] CPU Status:
A built-in I/O instruction that is disabled with a Stop/Continue
parameter was executed.
• Enable the built-in I/O function with parameters.
■Collateral information
4116 • Prohibit executions of a built-in I/O instruction LCPU
• Common information: Program error location
that is disabled with a parameter.
• Individual information:-
■Diagnostic Timing
• When instruction executed

12-62
 Error
LED Status Corresponding
Code Error Contents and Cause Corrective Action
CPU Status CPU
(SD0)
[OPERATION ERROR] 1
Since the manual system switching enable flag
(SM1592) is off, a manual system switching cannot
be executed by the control system switching
To execute control system switching by the SP.
4120
instruction (SP. CONTSW).
■Collateral information
CONTSW instruction, turn on the manual system
switching enable flag (SM1592).
2
• Common information: Program error location
• Individual information:- RUN:
■Diagnostic Timing Off/On
• When instruction executed ERR.:
Flicker/On 3
[OPERATION ERROR] • Reexamine the interlock signal for the SP. QnPRH
• In the separate mode, the control system CONTSW instruction, and make sure that the CPU Status:
switching instruction (SP. CONTSW) was SP. CONTSW instruction is executed in the Stop/
executed in the standby system CPU module.
• In the debug mode, the control system switching
control system only. (Since the SP. CONTSW
instruction cannot be executed in the standby
Continue*1 12
4121 instruction (SP. CONTSW) was executed. system, it is recommended to provide an
■Collateral information interlock using the operation mode signal or
• Common information: Program error location like.)
• Individual information:-
■Diagnostic Timing
• As the SP. CONTSW instruction cannot be
executed in the debug mode, reexamine the
6
• When instruction executed interlock signal related to the operation mode.
[OPERATION ERROR]
• The dedicated instruction was executed to the
module mounted on the extension base unit in
6
the redundant system.
• The instruction for accessing the intelligent • Delete the dedicated instruction for the module
function module mounted on the extension base mounted on the extension base unit.
4122 unit from the standby system at separate mode
was executed.
• Delete the instruction for accessing the
intelligent function module mounted on the
QnPRH*15 7
■Collateral information extension base unit from the standby system.
• Common information: Program error location
• Individual information:-
■Diagnostic Timing 8
• When instruction executed
[OPERATION ERROR]
Instructions to read SFC step comment
(S(P).SFCSCOMR) and SFC transition condition
comment (S(P).SFCTCOMR) are executed for the
comment file in ATA card. Qn(H)*11
Target comment file is to be other than the
4130 ■Collateral information QnPH*12
comment file in ATA card.
• Common information: Program error location QnPRH

12.1.6 Error code list (4000 to 4999)

12.1 Error Code List
• Individual information:-
■Diagnostic Timing
RUN:
• When instruction executed/When an END
Off/On
instruction executed
ERR.:
[OPERATION ERROR] Flicker/On
The SFC program is started up by the instruction
while the other SFC program has not yet been CPU Status:
completed. Check the SFC program specified by the Stop/Continue
4131 ■Collateral information instruction. Or, check the executing status of the
• Common information: Program error location SFC program.
• Individual information:-
■Diagnostic Timing
• When instruction executed
[OPERATION ERROR]
An Operation was performed with special values of
input data (-0, unnormalized number, nonnumeric,
QnU
± ∞) is performed.
LCPU
4140 ■Collateral information
• Common information: Program error location Read the individual information of the error using
• Individual information:- the programming tool to identify the numeric
■Diagnostic Timing value (program error location). Check the
• When instruction executed intelligent function module dedicated instruction
[OPERATION ERROR] corresponding to the value and correct it as
Overflow occurs at operation. necessary.
■Collateral information
4141 • Common information: Program error location
• Individual information:-
■Diagnostic Timing
• When instruction executed

12-63
 Error
LED Status Corresponding
Code Error Contents and Cause Corrective Action
CPU Status CPU
(SD0)
[FOR-NEXT ERROR]
The NEXT instruction was not executed although a
FOR instruction has been executed.
Alternatively, there are fewer NEXT instructions
than FOR instructions.
4200
■Collateral information
• Common information: Program error location
• Individual information:-
Read the individual information of the error using
■Diagnostic Timing
• When instruction executed the programming tool to identify the numeric
value (program error location). Check the error
[FOR-NEXT ERROR] RUN:
step corresponding the value and correct it as
The NEXT instruction was executed although no Off
necessary.
FOR instruction has been executed. ERR.:
QCPU
Alternatively, there are more NEXT instructions Flicker
LCPU
than FOR instructions.
4201
■Collateral information CPU Status:
• Common information: Program error location Stop
• Individual information:-
■Diagnostic Timing
• When instruction executed
[FOR-NEXT ERROR]
More than 16 nesting levels are programmed.
■Collateral information
4202 • Common information: Program error location Keep nesting levels at 16 or under.
• Individual information:-
■Diagnostic Timing
• When instruction executed
[FOR-NEXT ERROR]
A BREAK instruction was executed although no
FOR instruction has been executed prior to that.
■Collateral information
4203
• Common information: Program error location
• Individual information:-
■Diagnostic Timing
• When instruction executed
[CAN'T EXECUTE(P)]
The CALL instruction is executed, but there is no
subroutine at the specified pointer.
■Collateral information
4210
• Common information: Program error location
RUN:
• Individual information:-
Read common information of the error using the Off
■Diagnostic Timing
• When instruction executed programming tool to identify the numeric value ERR.:
QCPU
(program error location). Check the error step Flicker
[CAN'T EXECUTE(P)] LCPU
corresponding to the value, and correct it as
There was no RET instruction in the executed
necessary. CPU Status:
subroutine program.
Stop
■Collateral information
4211
• Common information: Program error location
• Individual information:-
■Diagnostic Timing
• When instruction executed
[CAN'T EXECUTE(P)]
The RET instruction exists before the FEND
instruction of the main routine program.
■Collateral information
4212
• Common information: Program error location
• Individual information:-
■Diagnostic Timing
• When instruction executed

12-64
 Error
LED Status Corresponding
Code Error Contents and Cause Corrective Action
CPU Status CPU
(SD0)
[CAN'T EXECUTE(P)] 1
More than 16 nesting levels are programmed.
■Collateral information
4213 • Common information: Program error location Keep nesting levels at 16 or under.
• Individual information:-
■Diagnostic Timing
2
• When instruction executed
[CAN'T EXECUTE(I)]
Though an interrupt input occurred, the
corresponding interrupt pointer does not exist.
RUN:
Off
3
■Collateral information ERR.:
4220 QCPU
• Common information: Program error location Flicker
LCPU
12
• Individual information:-
Read common information of the error using the
■Diagnostic Timing CPU Status:
• When instruction executed programming tool to identify the numeric value
Stop
(program error location). Check the error step
[CAN'T EXECUTE(I)] corresponding to the value, and correct it as
An IRET instruction does not exist in the executed
interrupt program.
necessary.
6
■Collateral information
4221
• Common information: Program error location
• Individual information:-
■Diagnostic Timing
• When instruction executed
6
[CAN'T EXECUTE(I)]
The IRET instruction exists before the FEND
instruction of the main routine program.
■Collateral information
7
• Common information: Program error location
• Individual information:-
■Diagnostic Timing
• When instruction executed Read common information of the error using the 8
programming tool to identify the numeric value
[CAN'T EXECUTE(I)] QCPU
4223 (program error location). Check the error step
• The IRET instruction was executed in the fixed LCPU
corresponding to the value, and correct it as
scan execution type program.
necessary.
• The STOP instruction was executed in the fixed
scan execution type program.
■Collateral information
• Common information: Program error location RUN:

12.1.6 Error code list (4000 to 4999)

12.1 Error Code List
• Individual information:- Off
■Diagnostic Timing ERR.:
• When instruction executed Flicker
[CAN'T EXECUTE(I)]
The interrupt pointer for the module mounted on CPU Status:
the extension base unit is set in the redundant Stop
system. Delete the setting of interrupt pointer for the
4225 ■Collateral information module mounted on the extension base unit, QnPRH*12
• Common information:- since it cannot be used.
• Individual information:-
■Diagnostic Timing
• At power-on/At reset
[INST. FORMAT ERR.]
The number of CHK and CHKEND instructions is
Read common information of the error using the
not equal.
programming tool to identify the numeric value
■Collateral information Qn(H)
4230 (program error location). Check the error step
• Common information: Program error location QnPH
corresponding to the value, and correct it as
• Individual information:-
necessary.
■Diagnostic Timing
• When instruction executed

12-65
 Error
LED Status Corresponding
Code Error Contents and Cause Corrective Action
CPU Status CPU
(SD0)
[INST. FORMAT ERR.]
The number of IX and IXEND instructions is not
equal.
■Collateral information
4231 QCPU
• Common information: Program error location
• Individual information:-
RUN:
■Diagnostic Timing
• When instruction executed Read common information of the error using the Off
programming tool to identify the numeric value ERR.:
[INST. FORMAT ERR.] (program error location). Check the error step Flicker
The configuration of the check conditions for the
corresponding to the value, and correct it as
CHK instruction is incorrect.
necessary. CPU Status:
Alternatively, a CHK instruction has been used in a
Stop
low speed execution type program. Qn(H)
4235
■Collateral information QnPH
• Common information: Program error location
• Individual information:-
■Diagnostic Timing
• When instruction executed
[MULTI-COM. ERROR]
• The multiple CPU high-speed transmission
dedicated instruction used in the program
specifies the wrong CPU module. Or, the setting
in the CPU module is incompatible with the
multiple CPU high-speed transmission
dedicated instruction.
• The reserved CPU is specified.
• The uninstalled CPU is specified.
• The head I/O number of the target CPU/16 (n1)
is outside the range of 3E0H to 3E3H.
4350 • The CPU module where the instruction cannot
be executed is specified.
• The instruction is executed in a single CPU
system.
• The host CPU is specified.
• The instruction is executed without setting the
"Use multiple CPU high speed communication".
■Collateral information
• Common information: Program error location RUN:
• Individual information:- Read common information of the error using the Off
■Diagnostic Timing programming tool to identify the numeric value ERR.:
• When instruction executed (program error location). Check the error step Flicker QnU*20
[MULTI-COM. ERROR] corresponding to the value, and correct it as
• The multiple CPU high-speed transmission necessary. CPU Status:
dedicated instruction specified by the program Stop
cannot be executed to the specified target CPU
module.
• The instruction name is wrong.
4351 • The instruction unsupported by the target CPU
module is specified.
■Collateral information
• Common information: Program error location
• Individual information:-
■Diagnostic Timing
• When instruction executed
[MULTI-COM. ERROR]
The number of devices for the multiple CPU high-
speed transmission dedicated instruction specified
by the program is wrong.
4352 ■Collateral information
• Common information: Program error location
• Individual information:-
■Diagnostic Timing
• When instruction executed

12-66
 Error
LED Status Corresponding
Code Error Contents and Cause Corrective Action
CPU Status CPU
(SD0)
[MULTI-COM. ERROR] 1
The device which cannot be used for the multiple
CPU high-speed transmission dedicated
instruction specified by the program is specified.
4353 ■Collateral information
• Common information: Program error location
2
• Individual information:-
■Diagnostic Timing
• When instruction executed
[MULTI-COM. ERROR]
3
The character string which cannot be handled by
RUN:
the multiple CPU high-speed transmission
Read common information of the error using the Off

4354
dedicated instruction is specified.
■Collateral information
programming tool to identify the numeric value ERR.: 12
(program error location). Check the error step Flicker QnU*20
• Common information: Program error location
corresponding to the value, and correct it as
• Individual information:-
necessary. CPU Status:
■Diagnostic Timing
• When instruction executed Stop
6
[MULTI-COM. ERROR]
The number of read/write data (number of request/
receive data) for the multiple CPU high-speed
transmission dedicated instruction specified by the 6
program is not valid.
4355
■Collateral information
• Common information: Program error location
• Individual information:-
■Diagnostic Timing
7
• When instruction executed
[SFCP. CODE ERROR]
No SFCP or SFCPEND instruction in SFC
program.
8
Qn(H)
■Collateral information
4400 QnPH
• Common information: Program error location
QnPRH
• Individual information:-
■Diagnostic Timing
• STOP→RUN
[CAN'T SET(BL)]
The block number designated by the SFC program

12.1.6 Error code list (4000 to 4999)

12.1 Error Code List
exceeds the range.
■Collateral information
4410
• Common information: Program error location
RUN:
• Individual information:-
Off
■Diagnostic Timing
• At power-on/At reset/STOP→RUN ERR.:
Write the program to the CPU module again using
Flicker
[CAN'T SET(BL)] the programming tool.
Block number designations overlap in SFC Q00J/Q00/Q01*8
CPU Status:
program. Qn(H)
Stop
■Collateral information QnPH
4411
• Common information: Program error location QnPRH
• Individual information:- QnU
■Diagnostic Timing LCPU
• At power-on/At reset/STOP→RUN
[CAN'T SET(S)]
A step number designated in an SFC program
exceeds the range.
■Collateral information
4420
• Common information: Program error location
• Individual information:-
■Diagnostic Timing
• At power-on/At reset/STOP→RUN

12-67
 Error
LED Status Corresponding
Code Error Contents and Cause Corrective Action
CPU Status CPU
(SD0)
[CAN'T SET(S)]
Total number of steps in all the SFC programs
exceeded the maximum value.
■Collateral information
4421
• Common information: Program error location
RUN:
• Individual information:- Q00J/Q00/Q01*8
Off
■Diagnostic Timing Qn(H)
• At power-on/At reset/STOP→RUN ERR.:
Write the program to the CPU module again using QnPH
Flicker
[CAN'T SET(S)] the programming tool. QnPRH
Step number designations overlap in SFC QnU
CPU Status:
program. LCPU
Stop
■Collateral information
4422
• Common information: Program error location
• Individual information:-
■Diagnostic Timing
• At power-on/At reset/STOP→RUN
[CAN'T SET(S)]
The total number of (maximum step No.+1) of
each block exceeds the total number of step
relays. Correct the total number of step relays so that it
4423 ■Collateral information does not exceed the total number of (maximum
• Common information: Program error location step No.+1) of each block.
• Individual information:-
■Diagnostic Timing
• At power-on/At reset/STOP→RUN
[SFC EXE. ERROR]
The SFC program cannot be executed.
• The data of the block data setting is illegal.
• Write the program to the CPU module again
• The SFC data device of the block data setting is
using the programming tool.
beyond the device setting range set in the PLC
• After correcting the setting of the SFC data
Parameter dialog box.
4430 device, write it to the CPU module.
■Collateral information RUN:
• Correct the device setting range in the PLC
• Common information: File name/Drive name Off
Parameter dialog box, and write it to the CPU
• Individual information:- ERR.: Q00J/Q00/Q01*8
module.
■Diagnostic Timing Flicker QnU
• At power-on/At reset/STOP→RUN/When SFC LCPU
program is executed CPU Status:
[SFC EXE. ERROR] Stop
The SFC program cannot be executed.
• The block parameter setting is abnormal.
■Collateral information
4431
• Common information: File name/Drive name
• Individual information:-
■Diagnostic Timing
• At power-on/At reset/STOP→RUN Write the program to the CPU module again using
[SFC EXE. ERROR] the programming tool.
The SFC program cannot be executed.
• The structure of the SFC program is illegal.
■Collateral information
4432
• Common information: File name/Drive name
• Individual information:-
■Diagnostic Timing
• At power-on/At reset/STOP→RUN

12-68
 Error
LED Status Corresponding
Code Error Contents and Cause Corrective Action
CPU Status CPU
(SD0)
[SFCP. FORMAT ERR.] 1
The numbers of BLOCK and BEND instructions in
an SFC program are not equal.
■Collateral information
2
4500
• Common information: Program error location
• Individual information:-
■Diagnostic Timing
• STOP→RUN Qn(H)
[SFCP. FORMAT ERR.]
The configuration of the STEP* to TRAN* to TSET
QnPH
QnPRH
3
RUN:
to SEND instructions in the SFC program is
Off
incorrect.
ERR.:
4501 ■Collateral information
• Common information: Program error location
Write the program to the CPU module again using
the programming tool.
Flicker 12
• Individual information:-
CPU Status:
■Diagnostic Timing
Stop
• STOP→RUN
[SFCP. FORMAT ERR.] 6
The structure of the SFC program is illegal.
Q00J/Q00/Q01*8
• STEPI* instruction does not exist in the block of
Qn(H)
the SFC program.
4502 ■Collateral information
• Common information: Program error location
QnPH
QnPRH
6
QnU
• Individual information:-
LCPU
■Diagnostic Timing
• STOP→RUN
[SFCP. FORMAT ERR.]
7
The structure of the SFC program is illegal.
• The step specified in the TSET instruction does
not exist.
• In jump transition, the host step number was
Q00J/Q00/Q01*8 8
Qn(H)
specified as the destination step number.
QnPH
■Collateral information
• Write the program to the CPU module again QnPRH
• Common information: Program error location
using the programming tool.
• Individual information:-
• Read common information of the error using
■Diagnostic Timing
4503 • STOP→RUN the programming tool to identify the numeric
value (program error location). Check the error
[SFCP. FORMAT ERR.] step corresponding to the value, and correct it

12.1.6 Error code list (4000 to 4999)

12.1 Error Code List
The structure of the SFC program is illegal.
as necessary.
• The step specified in the TSET instruction does
not exist.
QnU
■Collateral information
LCPU
• Common information: Program error location RUN:
• Individual information:- Off
■Diagnostic Timing ERR.:
• When instruction executed Flicker
[SFCP. FORMAT ERR.]
The structure of the SFC program is illegal. CPU Status:
Q00J/Q00/Q01*8
• The step specified in the TAND instruction does Stop
Qn(H)
not exist.
Write the program to the CPU module again using QnPH
4504 ■Collateral information
the programming tool. QnPRH
• Common information: Program error location
QnU
• Individual information:-
LCPU
■Diagnostic Timing
• When instruction executed
[SFCP. FORMAT ERR.]
The structure of the SFC program is illegal.
• In the operation output of a step, the SET Sn/
Read common information of the error using the
BLmSn or RST Sn/BLmSn instruction was
programming tool to identify the numeric value Q00J/Q00/Q01*8
specified for the host step.
4505 (program error location). Check the error step QnU
■Collateral information
corresponding to the value, and correct it as LCPU
• Common information: Program error location
necessary.
• Individual information:-
■Diagnostic Timing
• When instruction executed

12-69
 Error
LED Status Corresponding
Code Error Contents and Cause Corrective Action
CPU Status CPU
(SD0)
[SFCP. FORMAT ERR.]
The structure of the SFC program is illegal. RUN:
• In a reset step, the host step number was Off
specified as the destination step. ERR.: Q00J/Q00/Q01*8
4506 ■Collateral information Flicker QnU
• Common information: Program error location LCPU
• Individual information:- CPU Status:
■Diagnostic Timing Stop
• When instruction executed
[SFCP. OPE. ERROR]
The SFC program contains data that cannot be
Read common information of the error using the
processed.
programming tool, check error step
■Collateral information
4600 corresponding to its numerical value (program
• Common information: Program error location RUN:
error location), and correct the problem.
• Individual information:- Off/On
■Diagnostic Timing ERR.:
• When instruction executed Qn(H)
Flicker/On
QnPH
[SFCP. OPE. ERROR] QnPRH
Exceeds device range that can be designated by CPU Status:
the SFC program. Stop/
■Collateral information Continue*1
4601
• Common information: Program error location
• Individual information:-
■Diagnostic Timing
• When instruction executed

[SFCP. OPE. ERROR] RUN:

The START instruction in an SFC program is Off/On
Read common information of the error using the
preceded by an END instruction. ERR.:
programming tool to identify the numeric value Qn(H)
■Collateral information Flicker/On
4602 (program error location). Check the error step QnPH
• Common information: Program error location
corresponding to the value, and correct it as QnPRH
• Individual information:- CPU Status:
necessary.
■Diagnostic Timing Stop/
• When instruction executed Continue*1
[SFCP. EXE. ERROR]
The active step information at presumptive start of
the SFC program is incorrect.
■Collateral information
4610
• Common information: Program error location
• Individual information:- Read common information of the error using the RUN:
■Diagnostic Timing programming tool to identify the numeric value On
• STOP→RUN (program error location). Check the error step ERR.: Qn(H)
[SFCP. EXE. ERROR] corresponding to the value, and correct it as On QnPH
Key-switch was reset during RUN when necessary. QnPRH
presumptive start was designated for SFC The program is automatically subjected to an CPU Status:
program. initial start. Continue
4611 ■Collateral information
• Common information: Program error location
• Individual information:-
■Diagnostic Timing
• STOP→RUN

12-70
 Error
LED Status Corresponding
Code Error Contents and Cause Corrective Action
CPU Status CPU
(SD0)
[BLOCK EXE. ERROR] 1
Startup was executed at a block in the SFC
Read common information of the error using the
program that was already started up.
programming tool to identify the numeric value Qn(H)
■Collateral information
2
4620 (program error location). Check the error step QnPH
• Common information: Program error location
corresponding to the value, and correct it as QnPRH
• Individual information:-
necessary.
■Diagnostic Timing
• When instruction executed
[BLOCK EXE. ERROR]
Startup was attempted at a block that does not • Read common information of the error using Q00J/Q00/Q01*8
3
exist in the SFC program. the programming tool to identify the numeric Qn(H)
■Collateral information value (program error location). Check the error QnPH
4621
12
• Common information: Program error location step corresponding to the value, and correct it QnPRH
• Individual information:- as necessary. QnU
■Diagnostic Timing • Turn on SM321 if it is off. LCPU
• When instruction executed

6
[STEP EXE. ERROR] RUN:
The step specified in the SFC program is already
Read common information of the error using the Off
activated.
programming tool to identify the numeric value ERR.: Qn(H)
■Collateral information
4630 (program error location). Check the error step Flicker QnPH
• Common information: Program error location
• Individual information:-
■Diagnostic Timing
corresponding to the value, and correct it as
necessary. CPU Status:
QnPRH
6
Stop
• When instruction executed
[STEP EXE. ERROR]
• Startup was attempted at the step that does not
exist in the SFC program.
7
Or, the step that does not exist in the SFC
program was specified for end.
• Forced transition was executed based on the
transition condition that does not exit in the SFC
• Read common information of the error using
the programming tool to identify the numeric
Q00J/Q00/Q01*8
Qn(H)
8
program. value (program error location). Check the error QnPH
4631
Or, the transition condition for forced transition step corresponding to the value, and correct it QnPRH
that does not exit in the SFC program was as necessary. QnU
canceled. • Turn on SM321 if it is off. LCPU
■Collateral information
• Common information: Program error location
• Individual information:-

12.1.6 Error code list (4000 to 4999)

12.1 Error Code List
■Diagnostic Timing
• When instruction executed
[STEP EXE. ERROR]
There were too many simultaneous active steps in
blocks that can be designated by the SFC
program.
4632 ■Collateral information
• Common information: Program error location RUN:
• Individual information:- Read common information of the error using the Off Qn(H)
■Diagnostic Timing programming tool to identify the numeric value ERR.: QnPH
• When instruction executed (program error location). Check the error step Flicker QnPRH
[STEP EXE. ERROR] corresponding to the value, and correct it as QnU
There were too many simultaneous active steps in necessary. CPU Status: LCPU
all blocks that can be designated. Stop
■Collateral information
4633
• Common information: Program error location
• Individual information:-
■Diagnostic Timing
• When instruction executed
*1 CPU operations when an error occurred can be determined with a parameter. (LED indication varies according to the
CPU module status.)
*8 This applies if the function version is B or later.
*10 This applies when the first five digits of the serial number is "04101" or later.
*11 This applies when the first five digits of the serial number is "07012" or later.
*12 This applies when the first five digits of the serial number is "07032" or later.
*15 This applies when the first 5 digits of the serial No. is "09102" or later
*18 This applies to the Universal model QCPU except for the Q00UJCPU.
*19 This applies to the Universal model QCPU except for the Q00UJCPU, Q00UCPU, and Q01UCPU.
*20 This applies to the Universal model QCPU except for the Q00UJCPU, Q00UCPU, Q01UCPU, and Q02UCPU.
*21 This applies to the Built-in Ethernet port QCPU.

12-71
 12.1.7 Error code list (5000 to 5999)

The following shows the error messages from the error code 5000 to 5999, the contents and
causes of the errors, and the corrective actions for the errors.

Error LED Status Corresponding

Error Contents and Cause Corrective Action
Code CPU Status CPU
[WDT ERROR]
• The scan time of the initial execution type • Read the individual information of the error
program exceeded the initial execution using the programming tool to identify the
monitoring time specified in the PLC RAS tab of numeric value (time). Check the value and Qn(H)
the PLC Parameter dialog box. shorten the scan time. QnPH
■Collateral information • Change the initial execution monitoring time or QnPRH
• Common information: Time (value set) the WDT value in the PLC RAS tab of the PLC QnU
• Individual information: Time (value actually Parameter dialog box. LCPU
measured) • Resolve the endless loop caused by jump
■Diagnostic Timing transition.
• Always
[WDT ERROR]
5000 • The power supply of the standby system is
• Since power-off of the standby system increases
turned OFF.
the control system scan time, reset the WDT
• The tracking cable is disconnected or connected
value, taking the increase of the control system
without turning off or resetting the standby
scan time into consideration.
system.
• If the tracking cable was disconnected during
• The tracking cable is not secured by the
operation, securely connect it and restart the QnPRH
connector fixing screws.
CPU module. If the same error code is displayed
■Collateral information
again, the cause is a hardware failure of the
• Common information: Time (value set)
tracking cable or CPU module. (Please consult
• Individual information: Time (value actually RUN:
your local Mitsubishi representative, explaining a
measured) Off
detailed description of the problem.)
■Diagnostic Timing ERR.:
• Always Flicker
[WDT ERROR]
• Read the individual information of the error
• The scan time of the program exceeded the CPU Status:
using the programming tool to identify the
WDT value specified in the PLC RAS tab of the Stop
numeric value (time). Check the value and
PLC Parameter.
shorten the scan time.
■Collateral information QCPU
• Change the initial execution monitoring time or
• Common information: Time (value set) LCPU
the WDT value in the PLC RAS tab of the PLC
• Individual information: Time (value actually
Parameter.
measured)
• Resolve the endless loop caused by jump
■Diagnostic Timing
transition.
• Always
[WDT ERROR]
• The power supply of the standby system is
5001 • Since power-off of the standby system increases
turned OFF.
the control system scan time, reset the WDT
• The tracking cable is disconnected or connected
value, taking the increase of the control system
without turning off or resetting the standby
scan time into consideration.
system.
• If the tracking cable was disconnected during
• The tracking cable is not secured by the
operation, securely connect it and restart the QnPRH
connector fixing screws.
CPU module. If the same error code is displayed
■Collateral information
again, the cause is a hardware failure of the
• Common information: Time (value set)
tracking cable or CPU module. (Please consult
• Individual information: Time (value actually
your local Mitsubishi representative, explaining a
measured)
detailed description of the problem.)
■Diagnostic Timing
• Always

12-72
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
[PRG. TIME OVER]
• The program scan time exceeded the constant 1
scan time specified in the PLC RAS tab of the
Qn(H)
PLC Parameter dialog box.
QnPH
■Collateral information
2
QnPRH
• Common information: Time (value set)
QnU
• Individual information: Time (value actually
LCPU
measured)
• Review the constant scan setting time.
■Diagnostic Timing
• To secure sufficient excess time, correct the
• Always
[PRG. TIME OVER]
value for "Constant scanning" and "Low Speed 3
Program Execution Time" in the PLC Parameter
• The low speed program execution time specified
dialog box.
in the PLC RAS setting of the PLC parameter

5010
exceeded the excess time of the constant scan.
■Collateral information
Qn(H)
QnPH
12
• Common information: Time (value set)
QnPRH
• Individual information: Time (value actually
measured) RUN:
■Diagnostic Timing On 6
• Always ERR.:
[PRG. TIME OVER] On
The program scan time exceeded the constant
scan setting time specified in the PLC RAS setting CPU Status:
Continue
6
of the PLC parameter.
• Review the constant scan setting time in the
■Collateral information
PLC parameter so that the excess time of Q00J/Q00/Q01
• Common information: Time (value set)
constant scan can be fully secured.
• Individual information: Time (value actually
measured)
7
■Diagnostic Timing
• Always
[PRG. TIME OVER]
The scan time of the low speed execution type
8
program exceeded the low speed execution watch
time specified in the PLC RAS setting of the PLC Read the individual information of the error using
parameter dialog box. the programming tool to identify the numeric value
Qn(H)
5011 ■Collateral information (time). Check the value and shorten the scan time.
QnPH
• Common information: Time (value set) Change the low speed execution watch time in the
• Individual information: Time (value actually PLC RAS setting of the PLC parameter dialog box.
measured)

12.1.7 Error code list (5000 to 5999)

12.1 Error Code List
■Diagnostic Timing
• Always

12-73
 12.1.8 Error code list (6000 to 6999)

The following shows the error messages from the error code 6000 to 6999, the contents and
causes of the errors, and the corrective actions for the errors.

Error LED Status Corresponding

Error Contents and Cause Corrective Action
Code CPU Status CPU
[FILE DIFF.]
In a redundant system, the control system and
standby system do not have the same programs
and parameters. • Match the programs and parameters of the
The file type detected as different between the two control system and standby system.
systems can be checked by the file name of the • Verify the CPU module by either of the following
error common information. procedures 1) or 2) to clarify the differences
• The program is different. between the files of both systems. Correct
(File name = ********.QPG) wrong files and write them to the CPU module
• The PLC parameters/network parameters/ again.
redundant parameters are different. 1) After reading the programs and parameters of
(File name = PARAM.QPA) System A using GX Developer or PX
• The remote password is different. Developer, verify them with those of System
(File name = PARAM.QPA) B.
• The intelligent function module parameters are 2) Verify the programs and parameters of GX
different. Developer or PX Developer saved in the
6000 (File name = IPARAM.QPA) offline environment with those written to the
• The device initial values are different. CPU modules of both systems.
(File name = ********.QDI) • When the size of the area, which is used for RUN:
• The size of the area, which is used for enabling enabling writing multiple program blocks to the Off
writing multiple program blocks to the CPU CPU module during running, do not match, ERR.:
module during running, do not match. perform either of corrective actions 1) or 2). Flicker
(File name = MBOC.QMB) 1) Using the memory copy function, copy the
(This can be detected from the standby system of program memory from the control system to CPU Status:
the redundant system.) the standby system. Stop
■Collateral information 2) Format the CPU module program memories of
• Common information: File name both systems. (For both systems, specify the
QnPRH
• Individual information:- same values for the size of the area, which is
■Diagnostic Timing used for enabling writing multiple program
• At power-on/At reset/At tracking cable blocks to the CPU module during running.)
connection/At changing to backup mode/At
completion of write during RUN/At system
switching/At switching both systems into RUN
[FILE DIFF.]
In the redundant system, the valid-parameter drive
setting (SW2, SW3) set by the DIP switches differs
between the control system and standby system.
Match the valid-parameter drive settings (SW2,
■Collateral information
6001 SW3) for both the control and standby systems
• Common information:-
using the DIP switches.
• Individual information:-
■Diagnostic Timing
• At power-on/At reset/At tracking cable
connection/At operation mode change
[OPE. MODE DIFF.]
The operational status of the control system and
standby system in the redundant system is not the RUN:
same. On
(This can be detected from the standby system of ERR.:
Synchronise the operation statuses of the control
6010 the redundant system.) On
system and standby system.
■Collateral information
• Common information:- CPU Status:
• Individual information:- Continue
■Diagnostic Timing
• Always

12-74
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
[OPE. MODE DIFF.]
At power-on/reset, the RUN/STOP switch settings 1
of the control system and standby system are not
the same in a redundant system.
(This can be detected from the control system or
2
Set the RUN/STOP switches of the control system
6020 standby system of the redundant system.)
and standby system to the same setting.
■Collateral information
• Common information:-
• Individual information:-
■Diagnostic Timing
• At power-on/At reset 3
[UNIT LAY. DIFF.]
• In a redundant system, the module configuration
differs between the control system and standby
system. 12
• The network module mode setting differs
• Match the module configurations of the control
between the two systems.
system and standby system.
(This can be detected from the control system or
6030
standby system of the redundant system.)
• In the redundant setting of the network
parameter dialog box, match the mode setting of
6
■Collateral information
System B to that of System A.
• Common information: Module No.
• Individual information:-
■Diagnostic Timing
• At power-on/At reset/At tracking cable
6
connection/At operation mode change
[UNIT LAY. DIFF.]
In a redundant system, the CPU module model
name differs between the control system and
7
standby system.
(This can be detected from the standby system of

6035
the redundant system.)
■Collateral information
Match the model names of the control system and
standby system.
RUN:
Off 8
• Common information:- ERR.:
• Individual information:- Flicker QnPRH
■Diagnostic Timing
• At power-on/At reset/At tracking cable CPU Status:
connection/At operation mode change Stop
[UNIT LAY. DIFF.]
A difference in the remote I/O configuration of the

12.1.8 Error code list (6000 to 6999)

12.1 Error Code List
MELSECNET/H multiplexed remote I/O network
between the control system and standby system of
a redundant system was detected.
(This can be detected from the control system or Check the network cables of the MELSECNET/H
6036
standby system of the redundant system.) multiplexed remote I/O network for disconnection.
■Collateral information
• Common information: Module No.
• Individual information:-
■Diagnostic Timing
• Always
[CARD TYPE DIFF.]
In the redundant system, the memory card
insertion status (inserted/not inserted) differs
between the control system and standby system. Match the memory card insertion status (inserted/
6040 ■Collateral information not inserted) of the control system and standby
• Common information:- system.
• Individual information:-
■Diagnostic Timing
• At power-on/At reset
[CARD TYPE DIFF.]
In the redundant system, the memory card type
differs between the control system and standby
system.
Match the memory card types of the control
6041 ■Collateral information
system and standby system.
• Common information:-
• Individual information:-
■Diagnostic Timing
• At power-on/At reset

12-75
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
[CAN'T EXE. MODE]
The function inexecutable in the debug mode or
operation mode (backup/separate mode) was RUN:
executed. On
(This can be detected from the control system or ERR.:
Execute the function executable in the debug
6050 standby system of the redundant system.) On
mode or operation mode (backup/separate mode).
■Collateral information
• Common information:- CPU Status:
• Individual information:- Continue
■Diagnostic Timing
• Always
[CPU MODE DIFF.]
In a redundant system, the operation mode
(backup/separate) differs between the control
system and standby system.
(This can be detected from the standby system of
the redundant system.)
6060
■Collateral information
• Common information:-
• Individual information:-
■Diagnostic Timing
• At power-on/At reset/At tracking cable
connection Match the operation modes of the control system
and standby system.
[CPU MODE DIFF.]
In a redundant system, the operation mode
RUN:
(backup/separate) differs between the control
Off
system and standby system.
ERR.:
(This can be detected from the standby system of
Flicker
6061 the redundant system.)
■Collateral information
CPU Status: QnPRH
• Common information:-
Stop
• Individual information:-
■Diagnostic Timing
• When an END instruction executed
[CPU MODE DIFF.]
Both System A and B are in the same system
status (control system).
(This can be detected from the system B of the
redundant system.)
Power the CPU module (System B) which resulted
6062 ■Collateral information
in a stop error, OFF and then ON.
• Common information:-
• Individual information:-
■Diagnostic Timing
• At power-on/At reset/At tracking cable
connection
[TRK. TRANS. ERR.]
• An error (e.g. retry limit exceeded) occurred in
tracking data transmission.
(This error may be caused by tracking cable
removal or other system power-off (including • Check the CPU module or tracking cable. If the RUN:
reset).) error still occurs, this indicates the CPU module On
• The error occurred at a startup since the or tracking cable is faulty. (Please consult your ERR.:
6100 redundant system startup procedure was not local Mitsubishi representative, explaining a On
followed. detailed description of the problem.)
■Collateral information • Confirm the redundant system startup CPU Status:
• Common information: Tracking transmission procedure, and execute a startup again. Continue
data classification
• Individual information:-
■Diagnostic Timing
• Always

12-76
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
[TRK. TRANS. ERR.]
• A timeout error occurred in tracking (data 1
transmission).
(This error may be caused by tracking cable
removal or other system power-off (including
reset).)
• The error occurred at a startup since the
2
redundant system startup procedure was not
6101 followed.
(This can be detected from the control system or
standby system of the redundant system.)
3
■Collateral information
• Common information: Tracking transmission
data classification
• Individual information:- 12
■Diagnostic Timing
• Always
[TRK. TRANS. ERR.]
A data sum value error occurred in tracking (data 6
reception).
(This can be detected from the control system or
standby system of the redundant system.)
6102
■Collateral information
• Common information:-
6
• Individual information:-
■Diagnostic Timing
• Always
[TRK. TRANS. ERR.]
• Check the CPU module or tracking cable. If the RUN: 7
error still occurs, this indicates the CPU module On
• A data error (other than sum value error)
or tracking cable is faulty. (Please consult your ERR.:
occurred in tracking (data reception).
local Mitsubishi representative, explaining a On QnPRH
• (This error may be caused by tracking cable
removal or other system power-off (including
detailed description of the problem.)
• Confirm the redundant system startup CPU Status:
8
reset).)
procedure, and execute a startup again. Continue
• The error occurred at a startup since the
redundant system startup procedure was not
6103
followed.
(This can be detected from the control system or
standby system of the redundant system.)
■Collateral information

12.1.8 Error code list (6000 to 6999)

12.1 Error Code List
• Common information:-
• Individual information:-
■Diagnostic Timing
• Always
[TRK. TRANS. ERR.]
• An error (e.g. retry limit exceeded) occurred in
tracking (data transmission).
(This error may be caused by tracking cable
removal or other system power-off (including
reset).)
• The error occurred at a startup since the
redundant system startup procedure was not
6105 followed.
(This can be detected from the control system or
standby system of the redundant system.)
■Collateral information
• Common information: Tracking transmission
data classification
• Individual information:-
■Diagnostic Timing
• Always

12-77
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
[TRK. TRANS. ERR.]
• A timeout error occurred in tracking (data
transmission).
(This error may be caused by tracking cable
removal or other system power-off (including
reset).)
• The error occurred at a startup since the
redundant system startup procedure was not
6106 followed.
(This can be detected from the control system or
standby system of the redundant system.) • Check the CPU module or tracking cable. If the
■Collateral information error still occurs, this indicates the CPU module
• Common information: Tracking transmission or tracking cable is faulty. (Please consult your
data classification local Mitsubishi representative, explaining a
• Individual information:- detailed description of the problem.)
■Diagnostic Timing • Confirm the redundant system startup
• Always procedure, and execute a startup again.
[TRK. TRANS. ERR.]
A data sum value error occurred in tracking (data
reception).
(This can be detected from the control system or
standby system of the redundant system.)
6107
■Collateral information
• Common information:-
• Individual information:-
■Diagnostic Timing
• Always
[TRK. TRANS. ERR.]
• A data error (other than sum value error)
RUN:
occurred in tracking (data reception).
On
(This error may be caused by tracking cable
ERR.:
removal or other system power-off (including
• Check the CPU module or tracking cable. If the On QnPRH
reset).)
error still occurs, this indicates the CPU module
• The error occurred at a startup since the
or tracking cable is faulty. (Please consult your CPU Status:
redundant system startup procedure was not
6108 local Mitsubishi representative, explaining a Continue
followed.
detailed description of the problem.)
(This can be detected from the control system or
• Confirm the redundant system startup
standby system of the redundant system.)
procedure, and execute a startup again.
■Collateral information
• Common information:-
• Individual information:-
■Diagnostic Timing
• Always
[TRK. SIZE ERROR]
The tracking capacity exceeded the allowed range.
(This can be detected from the control system or
standby system of the redundant system.)
■Collateral information
6110 Reexamine the tracking capacity.
• Common information: Reason(s) for tracking
size excess error
• Individual information:-
■Diagnostic Timing
• When an END instruction executed
[TRK. SIZE ERROR]
The control system does not have enough file
register capacity for the file registers specified in
the tracking settings.
(This can be detected from the control system or Switch to the file registers of which capacity is
6111 standby system of the redundant system.) greater than the file registers specified in the
■Collateral information tracking settings.
• Common information:-
• Individual information:-
■Diagnostic Timing
• When an END instruction executed

12-78
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
[TRK. SIZE ERROR]
File registers greater than those of the standby 1
system were tracked and transmitted from the RUN:
control system. On
(This can be detected from the standby system of Switch to the file registers of which capacity is ERR.:
6112 the redundant system.)
■Collateral information
greater than the file registers specified in the
tracking settings.
On 2
• Common information:- CPU Status:
• Individual information:- Continue
■Diagnostic Timing
• When an END instruction executed 3
[TRK. CABLE ERR.]
• A start was made without the tracking cable
being connected.
• A start was made with the tracking cable faulty. 12
• As the tracking hardware on the CPU module Make a start after connecting the tracking cable. If RUN:
side was faulty, communication with the other the same error still occurs, this indicates the Off
system could not be made via the tracking tracking cable or CPU module side tracking ERR.:
6120 cable. transmission hardware is faulty. Flicker 6
(This can be detected from the control system or (Please consult your local Mitsubishi
standby system of the redundant system.) representative, explaining a detailed description of CPU Status:
■Collateral information the problem.) Stop
• Common information:-
• Individual information:-
6
■Diagnostic Timing
• At power-on/At reset
[TRK. DISCONNECT]
• The tracking cable was removed. • If the tracking cable was removed, connect the
7
• The tracking cable became faulty while the CPU tracking cable to the connectors of the CPU
module is running. modules of the two systems. RUN:
• The CPU module side tracking hardware
became faulty.
• When the error is not resolved after connecting
the tracking cable to the connectors of the CPU
On
ERR.: 8
6130 (This can be detected from the control system or modules of the two systems and resetting the On
standby system of the redundant system.) error, the tracking cable or CPU module side
■Collateral information tracking hardware is faulty. CPU Status:
QnPRH
• Common information:- (Please consult your local Mitsubishi Continue
• Individual information:- representative, explaining a detailed description of
■Diagnostic Timing the problem.)
• Always

12.1.8 Error code list (6000 to 6999)

12.1 Error Code List
[TRK.INIT. ERROR]
• The other system did not respond during initial
communication at power-on/reset.
• Power off and then on or reset the CPU module
• The error occurred at a startup since the RUN:
where the error occurred. If the same error still
redundant system startup procedure was not Off
occurs, this indicates the CPU module is faulty.
followed. ERR.:
(Please consult your local Mitsubishi
6140 (This can be detected from the control system or Flicker
representative, explaining a detailed description
standby system of the redundant system.)
of the problem.)
■Collateral information CPU Status:
• Confirm the redundant system startup
• Common information:- Stop
procedure, and execute a startup again.
• Individual information:-
■Diagnostic Timing
• At power-on/At reset
[CONTROL EXE.]
The standby system has been switched to the
control system in a redundant system. (Detected
by the CPU that was switched from the standby
system to the control system.)
Since this error code does not indicate the error
RUN:
information of the CPU module but indicates its
On
status, the error code and error information are not
ERR.:
stored into SD0 to 26, but are stored into the error
6200 - Off
log every system switching.
(To check the error information, obtain the error log
CPU Status:
using the programming tool.)
No error
■Collateral information
• Common information: Reason(s) for system
switching
• Individual information:-
■Diagnostic Timing
• Always

12-79
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
[STANDBY]
The control system has been switched to the
standby system in a redundant system. (Detected
by the CPU that was switched from the control
system to the standby system.)
Since this error code does not indicate the error
RUN:
information of the CPU module but indicates its
On
status, the error code and error information are not
ERR.:
stored into SD0 to 26, but are stored into the error
6210 - Off
log every system switching.
(To check the error information, obtain the error log
CPU Status:
using the programming tool.)
No error
■Collateral information
• Common information: Reason(s) for system
switching
• Individual information:-
■Diagnostic Timing
• Always
[CAN'T SWITCH]
The system cannot be switched due to a standby
system error, tracking cable failure, or online
module change being executed in the separate
mode. Causes for switching system at control
system are as follows:
• System switching by SP.CONTSW instruction • Check the status of the standby system and
6220 • System switching request from network module resolve the error.
■Collateral information • Complete the online module change.
• Common information: Reason(s) for system
switching
• Individual information: Reason(s) for system
switching failure RUN:
■Diagnostic Timing On
• At switching execution ERR.:
[STANDBY SYS. DOWN] On
Any of the following errors was detected in the
• Check whether the standby system is on or not, QnPRH
backup mode. CPU Status:
and if it is not on, power it on.
• The standby system has not started up in the Continue
• Check whether the standby system has been
redundant system.
reset or not, and if it has been reset, unreset it.
• The standby system has developed a stop error
• Check whether the standby system has
in the redundant system.
developed a stop error or not, and if it has
• The CPU module in the debug mode was
6300 developed the error, remove the error factor and
connected to the operating control system.
restart it.
(This can be detected from the control system of
• When the CPU module in the debug mode was
the redundant system.)
connected to the control system operating in the
■Collateral information
backup mode, make connection so that the
• Common information:-
control system and standby system are
• Individual information:-
combined correctly.
■Diagnostic Timing
• Always
• The standby system exists but the control
[CONTROL SYS. DOWN] system does not exist.
Any of the following errors was detected in the • Check whether the system other than the
backup mode. standby system is on or not, and if it is not on,
• The control system has not started up in the power it on.
redundant system. • Check whether the system other than the
• The control system has developed a stop error standby system has been reset or not, and if it is
in the redundant system. has been reset, unreset it. RUN:
• The CPU module in the debug mode was • Check whether the system other than the Off
connected to the operating standby system. standby system has developed a stop error or ERR.:
6310 • The error occurred at a startup since the not, and if has developed the error, remove the Flicker
redundant system startup procedure was not error factor, set the control system and standby
followed. system to the same operating status, and CPU Status:
(This can be detected from the standby system of restart. Stop
the redundant system.) • When the CPU module in the debug mode was
■Collateral information connected to the control system operating in the
• Common information:- backup mode, make connection so that the
• Individual information:- control system and control system are combined
■Diagnostic Timing correctly.
• Always • Confirm the redundant system startup
procedure, and execute a startup again.

12-80
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
6311 [CONTROL SYS. DOWN]
• As consistency check data has not transmitted 1
from the control system in a redundant system,
the other system cannot start as a standby
system. • Replace the tracking cable. If the same error still RUN:
• The error occurred at a startup since the
redundant system startup procedure was not
occurs, this indicates the CPU module is faulty.
(Please consult your local Mitsubishi
Off
ERR.:
2
followed. representative, explaining a detailed description Flicker QnPRH
6312 of the problem.)
(This can be detected from the standby system of
the redundant system.)
■Collateral information
• Confirm the redundant system startup
procedure, and execute a startup again.
CPU Status:
Stop
3
• Common information:-
• Individual information:-
■Diagnostic Timing
• At power-on/At reset 12
[CONTROL SYS. DOWN]
The control system detected the error of the
system configuration and informed it to the
standby system (host system) in the redundant Restart the system after checking that the 6
system. connection between base unit and the system
6313 QnPRH*15
■Collateral information configuration (type/number/parameter of module)
• Common information:- are correct.
• Individual information:-
■Diagnostic Timing
RUN:
Off 6
• At power-on/At reset ERR.:
Flicker
[PRG. MEM. CLEAR]
The memory copy from control system to standby
system was executed, and the program memory
CPU Status: 7
Stop
was cleared.
After the memory copy from the control system to
■Collateral information
6400 the standby system is completed, turn off and then
• Common information:-
• Individual information:-
on or reset the system. 8
■Diagnostic Timing
• At execution of the memory copy from control
system to standby system
[MEM. COPY EXE.] QnPRH
The memory copy from control system to standby
system was executed. RUN:
(This can be detected from the control system of On

12.1.8 Error code list (6000 to 6999)

12.1 Error Code List
the redundant system.) ERR.:
6410 ■Collateral information - On
• Common information:-
• Individual information:- CPU Status:
■Diagnostic Timing Continue
• At execution of the memory copy from control
system to standby system
[TRK. PARA. ERROR]
The file register file specified in the tracking setting
of the PLC parameter dialog box does not exist.
Read the individual information of the error using
■Collateral information
6500 the programming tool. Check the drive name and
• Common information: File name/Drive name
file name and correct them.
• Individual information: Parameter number
RUN:
■Diagnostic Timing
• At power-on/At reset Off
ERR.:
[TRK. PARA. ERROR] Flicker QnPRH
The file register range specified in the device detail
setting of the tracking setting of the PLC parameter
CPU Status:
dialog box exceeded the specified file register file
Read the individual information of the error using Stop
capacity.
6501 the programming tool, and increase the file register
■Collateral information
capacity.
• Common information: File name/Drive name
• Individual information: Parameter number
■Diagnostic Timing
• At power-on/At reset
*15 This applies when the first five digits of the serial number of the CPU module is "09102" or later.

12-81
 12.1.9 Error code list (7000 to 10000)

The following shows the error messages from the error code 7000 to 10000, the contents and
causes of the errors, and the corrective actions for the errors.

Error LED Status Corresponding

Error Contents and Cause Corrective Action
Code CPU Status CPU
[MULTI CPU DOWN]
• In the operating mode of a multiple CPU system,
a CPU error occurred at the CPU where "All
station stop by stop error of CPU " was selected.
• Read the individual information of the error
• In a multiple CPU system, a CPU module
using the programming tool. Check the error in
incompatible with the multiple CPU system was
the CPU module, and remove the error.
mounted.
• Remove the CPU module from the main base
• Any CPU module other than CPU No.1 was
unit if it does not support the multiple CPU
disconnected from the base unit during
system configuration.
operation. Or any CPU module other than CPU
• Check the mounting status of CPU modules
No.1 was reset.
other than CPU No.1 and whether the CPU
■Collateral information Q00/Q01*8
modules were reset.
• Common information: Module No. (CPU No.) Qn(H)*8
7000
• Individual information:- QnPH
■Diagnostic Timing
QnU*18
• Always
[MULTI CPU DOWN]
In a multiple CPU system, CPU other than CPU
No.1 cannot be started up due to stop error of the
CPU No.1 at power-on, which occurs to CPU No.2
Read the individual information of the error using
to No.4.
the programming tool. Check the error in the CPU
■Collateral information
module, and remove the error.
• Common information: Module No. (CPU No.)
• Individual information:-
■Diagnostic Timing
• At power-on/At reset RUN:
Off
[MULTI CPU DOWN]
• Reset the CPU module and RUN it again. If the ERR.:
• There is no response from the target CPU
same error is displayed again, this suggests the Flicker
module in a multiple CPU system during initial
hardware fault of any of the CPU modules.
communication.
(Please consult your local Mitsubishi CPU Status:
• In a multiple CPU system, a CPU module
representative, explaining a detailed description Stop Q00/Q01*8
incompatible with the multiple CPU system was
of the problem.) Qn(H)*8
mounted.
• Remove the CPU module from the main base QnPH
■Collateral information
unit if it does not support the multiple CPU
• Common information: Module No. (CPU No.)
system configuration. Or, replace the CPU
• Individual information:-
module incompatible with the multiple CPU
7002 ■Diagnostic Timing
system with the compatible one.
• At power-on/At reset
[MULTI CPU DOWN]
There is no response from the target CPU module
in a multiple CPU system during initial
communication.
■Collateral information QnU*18
• Common information: Module No. (CPU No.)
• Individual information:-
Reset the CPU module and RUN it again. If the
■Diagnostic Timing
• At power-on/At reset same error is displayed again, this suggests the
hardware fault of any of the CPU modules. (Please
[MULTI CPU DOWN] consult your local Mitsubishi representative,
There is no response from the target CPU module
explaining a detailed description of the problem.)
in a multiple CPU system at initial communication
stage. Q00/Q01*8
7003 ■Collateral information Qn(H)*8
• Common information: Module No. (CPU No.) QnPH
• Individual information:-
■Diagnostic Timing
• At power-on/At reset

12-82
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
• Check the system configuration to see if
[MULTI CPU DOWN]
In a multiple CPU system, a data error occurred in modules are mounted in excess of the number 1
communication between the CPU modules. of I/O points.
■Collateral information • When there are no problems in the system Q00/Q01*8
7004
• Common information: Module No. (CPU No.) configuration, this indicates the CPU module QnU*18
• Individual information:- hardware is faulty. (Please consult your local 2
■Diagnostic Timing Mitsubishi representative, explaining a detailed
• Always description of the problem.)
[MULTI EXE. ERROR]
• In a multiple CPU system, a faulty CPU module 3
was mounted.
• In a multiple CPU system, a CPU module
incompatible with the multiple CPU system was
• Read the individual information of the error
mounted. (The CPU module compatible with the
multiple CPU system was used to detect an
using the programming tool and replace the 12
faulty CPU module. Q00/Q01*8
error.)
• Replace the CPU module with the one Qn(H)*8
• In a multiple CPU system, any of the CPU No. 2
compatible with the multiple CPU system. QnPH
to 4 was reset with power ON. (The CPU whose
reset state was cancelled was used to detect an
• Do not reset any of the No. 2 to 4 CPU modules.
• Reset CPU No. 1 and restart the multiple CPU
QnU*18 6
error.)
system.
■Collateral information
• Common information: Module No. (CPU No.)
• Individual information:- 6
■Diagnostic Timing RUN:
• At power-on/At reset Off
[MULTI EXE. ERROR] ERR.:
In a multiple CPU system, the version of the Flicker 7
software package (PPC-DRV-01)*23 for the PC
CPU module is 1.06 or earlier. CPU Status:
Change the software package (PPC-DRV-01)*23 Stop
■Collateral information Q00/Q01*8
7010 • Common information: Module No. (CPU No.)
• Individual information:-
for the PC CPU module to the version 1.07 or later.
8
■Diagnostic Timing
• At power-on/At reset
[MULTI EXE. ERROR]
The Q172(H)CPU(N) or Q173(H)CPU(N) is
mounted on the multiple CPU high-speed main
base unit (Q3†DB). (This may result in a module
Replace the Q172(H)CPU(N) and
failure.)

12.1.9 Error code list (7000 to 10000)

12.1 Error Code List
Q173(H)CPU(N) with the Motion CPU compatible
■Collateral information
with the multiple CPU high-speed main base unit.
• Common information: Module No. (CPU No.)
• Individual information:-
■Diagnostic Timing
• At power-on/At reset Qn(H)*9
QnPH*9
[MULTI EXE. ERROR]
The Universal model QCPU (except Q02UCPU)
and Q172(H)CPU(N) are mounted on the same
base unit. (This may result in a module failure.) Check the QCPU and Motion CPU that can be
■Collateral information used in a multiple CPU system, and change the
• Common information: Module No. (CPU No.) system configuration.
• Individual information:-
■Diagnostic Timing
• At power-on/At reset

12-83
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
[MULTI EXE. ERROR]
Either of the following settings was made in a
multiple CPU system.
• Multiple CPU automatic refresh setting was
made for the inapplicable CPU module. • Correct the multiple CPU automatic refresh
• "I/O sharing when using multiple CPUs" setting setting. Q00/Q01*8
was made for the inapplicable CPU module. • Correct the "I/O sharing when using multiple QnU*18
■Collateral information CPUs" setting.
• Common information: Module No. (CPU No.)
• Individual information:-
■Diagnostic Timing
• At power-on/At reset
[MULTI EXE. ERROR]
The system configuration for using the Multiple
7011 CPU high speed transmission function is not met.
• The QnUCPU is not used for the CPU No.1.
RUN:
• The Multiple CPU high speed main base unit
Off
(Q3†DB) is not used. • Change the system configuration to meet the
ERR.:
• Points other than 0 is set to the send range for conditions for using the Multiple CPU high
Flicker
the CPU module incompatible with the multiple speed transmission function.
CPU high speed transmission function. • Set the send range of CPU, that does not QnU*20
CPU Status:
• Points other than 0 is set to the send range for correspond to multiple CPU compatible area, at
Stop
the CPU module incompatible with the multiple 0 point, when performing automatic refreshing in
CPU. multiple CPU compatible area.
■Collateral information
• Common information: Module No. (CPU No.)
• Individual information:-
■Diagnostic Timing
• At power-on/At reset
[MULTI EXE. ERROR]
The Q172(H)CPU(N) or Q173(H)CPU(N) is
mounted to the CPU slot or slots 0 to 2. (This may • Check the QCPU and Motion CPU that can be
result in a module failure.) used in a multiple CPU system, and change the
7013 ■Collateral information system configuration. QnU
• Common information: Module No. (CPU No.) • Remove the Motion CPU incompatible with the
• Individual information:- multiple CPU system.
■Diagnostic Timing
• At power-on/At reset
[MULTI CPU ERROR]
In a multiple CPU system, an error occurred in the
CPU module where "All station stop by stop error
RUN:
of CPU" was not selected in the operating mode
On
setting. Q00/Q01*8
Read the individual information of the error using ERR.:
(The CPU module where no error occurred was Qn(H)*8
7020 the programming tool. Check the error in the CPU On
used to detect an error.) QnPH
module, and remove the error.
■Collateral information QnU*18
CPU Status:
• Common information: Module No. (CPU No.)
Continue
• Individual information:-
■Diagnostic Timing
• Always
[CPU LAY ERROR]
An assignment error occurred in the CPU-
• Set the same value to the number of CPU
mountable slot (CPU slot, I/O slot 0, 1) in excess of RUN:
modules specified in the multiple CPU setting of
the number of CPU modules specified in the Off
the PLC parameter dialog box and the number
multiple CPU setting of the PLC parameter dialog ERR.:
of mounted CPU modules (including CPU Q00J/Q00/Q01*8
7030 box. Flicker
(empty)). QnU
■Collateral information
• Make the type specified in the I/O assignment
• Common information: Module No. (CPU No.) CPU Status:
setting of the PLC parameter dialog box
• Individual information:- Stop
consistent with the CPU module configuration.
■Diagnostic Timing
• At power-on/At reset

12-84
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
[CPU LAY ERROR]
An assignment error occurred within the range of
• Set the same value to the number of CPU
modules specified in the multiple CPU setting of
1
the number of CPUs specified in the multiple CPU
the PLC parameter dialog box and the number
setting of the PLC parameter dialog box.
of mounted CPU modules (including CPU Q00J/Q00/Q01*8
7031 ■Collateral information
2
(empty)). QnU
• Common information: Module No. (CPU No.)
• Make the type specified in the I/O assignment
• Individual information:-
setting of the PLC parameter dialog box
■Diagnostic Timing
• At power-on/At reset consistent with the CPU module configuration.

[CPU LAY ERROR]

The number of CPU modules mounted in a
3
multiple CPU system is wrong. Configure a system so that the number of
■Collateral information mountable modules of each CPU module does not Q00J/Q00/Q01*8
7032
12
• Common information: Module No. (CPU No.) exceed the maximum number of mountable QnU*18
• Individual information:- modules specified in the specification.
■Diagnostic Timing
• At power-on/At reset

6
[CPU LAY ERROR]
The CPU module has been mounted on the
RUN:
inapplicable slot.
Off Q00J/Q00/Q01*8
■Collateral information
7035 Mount the CPU module on the applicable slot. ERR.: QnPRH
• Common information: Module No. (Slot No.)
• Individual information:-
■Diagnostic Timing
Flicker QnU
6
CPU Status:
• At power-on/At reset
Stop
[CPU LAY ERROR]
The host CPU No. set by the multiple CPU setting
and the host CPU No. determined by the mounting • Mount the mounting slot of the CPU module
7
position of the CPU module are not the same. correctly.
7036 ■Collateral information • Correct the host CPU No. set by the multiple QnU*20
• Common information: Module No. (CPU No.)
• Individual information:-
CPU setting to the CPU No. determined by the
mounting position of the CPU module. 8
■Diagnostic Timing
• At power-on/At reset
[INCORRECT FILE]
Write the files shown in SD17 to SD22 (individual
The error of stored file (enabled parameter file) is
information) to the drive shown in SD16 (L)
detected.
(individual information). Turn off and then on or
■Collateral information
reset the CPU module.
• Common information:- QnU
8031 If the same error code is displayed again, the

12.1.9 Error code list (7000 to 10000)

12.1 Error Code List
• Individual information: File diagnostic LCPU
cause is a hardware failure of the CPU module.
information
(Please consult your local Mitsubishi
■Diagnostic Timing
• At power-on/At reset/STOP→RUN/At writing to representative, explaining a detailed description of
programmable controller the problem.)

[F**** ] RUN:
Annunciator (F) turned on. On
(The "****" portion of the error message indicates ERR.:
Read the individual information of the error using
an annunciator number.) On/Off*2
the programming tool to identify the numeric value QCPU
9000 ■Collateral information USER:
(annunciator number). Check the program LCPU
• Common information: Program error location On *24
corresponding to the value.
• Individual information: Annunciator number
■Diagnostic Timing CPU Status:
• When instruction executed Continue

12-85
 Error LED Status Corresponding
Error Contents and Cause Corrective Action
Code CPU Status CPU
[<CHK>ERR ***-***] RUN:
Error detected by the CHK instruction.
On
(The "***" portion of the error message indicates
ERR.:
the numbers of contact and coil that have been Read the individual information of the error using
Off Qn(H)
detected.) the programming tool to identify the numeric value
9010 USER: QnPH
■Collateral information (error number). Check the program corresponding
On*24 QnPRH
• Common information: Program error location to the value.
• Individual information: Failure No.
CPU Status:
■Diagnostic Timing
• When instruction executed Continue

[BOOT OK]
Storage of data onto ROM was completed RUN:
normally in automatic write to standard ROM. Off
Use the DIP switches to set the valid parameter
(BOOT LED also flickers.) ERR.: Qn(H)*8
drive to the standard ROM. Then, switch power on
9020 ■Collateral information Flicker QnPH
again, and perform boot operation from the
• Common information:- QnPRH
standard ROM.
• Individual information:- CPU Status:
■Diagnostic Timing Stop
• At power-on/At reset
[CONT. UNIT ERROR]
In the multiple CPU system, an error occurred in RUN:
the CPU module other than the Process CPU and Off
High Performance model QCPU. To check the details of the error, connect a ERR.:
Qn(H)*8
10000 ■Collateral information programming tool to the corresponding CPU Flicker
QnPH
• Common information:- module.
• Individual information:- CPU Status:
■Diagnostic Timing Continue
• Always
*2 For the Basic model QCPU, it can be turned on and off by the LED control function. (For the High Performance model
CPU, Process CPU, Redundant CPU, Universal model QCPU, and LCPU, it can only turned on.)
The manual of the CPU module used (function explanation, program fundamentals)
*8 This applies if the function version is B or later.
*9 This applies to the CPU modules when the first five digits of the serial number is "04012".
*18 This applies to the Universal model QCPU except for the Q00UJCPU.
*20 This applies to the Universal model QCPU except for the Q00UJCPU, Q00UCPU, Q01UCPU, and Q02UCPU.
*23 The product name is the Bus interface driver software package of MELSEC-Q series compatible PC CPU module
*24 The Basic model QCPU does not have the USER LED.

12-86
12.2 Canceling of Errors
1
Q series CPU module can perform the cancel operation for errors only when the errors allow
the CPU module to continue its operation.
To cancel the errors, follow the steps shown below. 2
1) Eliminate the cause of the error.
2) Store the error code to be canceled in the special register SD50. 3
3) Energize the special relay SM50 (OFF ON).
4) The error to be canceled is canceled.

After the CPU module is reset by the canceling of the error, the special relays, special
12
registers, and LEDs associated with the error are returned to the status under which the
error occurred.
If the same error occurs again after the cancellation of the error, it will be registered again in 6
the error history.

When multiple enunciators(F) detected are canceled, the first one with No. F only is
canceled.
6
Refer to the following manual for details of error canceling.
User's Manual (Function Explanation, Program Fundamentals) for the CPU module 7
used

8
(1) When the error is canceled with the error code to be canceled stored in the
SD50, the lower one digit of the code is neglected.
(Example)
If error codes 2100 and 2101 occur, and error code 2100 to cancel error code
2101.

12.2 Canceling of Errors

If error codes 2100 and 2111 occur, error code 2111 is not canceled even if
error code 2100 is canceled.
(2) Errors developed due to trouble in other than the CPU module are not
canceled even if the special relay (SM50) and special register (SD50) are
used to cancel the error.
(Example)
Since "SP. UNIT DOWN" is the error that occurred in the base unit (including
the extension cable), intelligent function module, etc. the error cause cannot
be removed even if the error is canceled by the special relay (SM50) and
special register (SD50).
Refer to the error code list and remove the error cause.

12-87
MEMO

12-88
A
8

APPENDICES 8

App-1
Appendix 1 OPERATION PROCESSING TIME

Appendix 1.1 Definition

(1) Processing time taken by the QCPU, LCPU is the total of the following processing times.
• Total of each instruction processing time
• END processing time (including I/O refresh time)
• Processing time for the function that increases the scan time
(2) Instruction processing time
This is the total of processing time of each instruction shown in Appendix 1.2, 1.3 and 1.4.
(3) END processing time, I/O refresh time, and processing time for the function that increases
the scan time
Refer to the following manual(s) for the END processing time, I/O refresh time, and
processing time for the function that increases the scan time.

(a) For QCPUs

• QnUCPU User's Manual (Functions Explanation, Program Fundamentals)
• Qn(H)/QnPH/QnPRHCPU User's Manual
(Functions Explanation, Program Fundamentals)
• MELSEC-L CPU Module User's Manual
(Functions Explanation, Program Fundamentals)

App-2
 Appendix 1.2 Operation Processing Time of Basic Model
QCPU 8
The processing time for the individual instructions are shown in the table on the following pages.
Operation processing times can vary substantially depending on the nature of the sources and
8
destinations of the instructions, and the values contained in the following tables should therefore
be taken as a set of general guidelines to processing time rather than as being strictly accurate.
8
(1) Sequence instructions
Processing Time (µs) 8
Instruction Condition (Device)
Q00JCPU Q00CPU Q01CPU

LD
LDI X0 0.20 0.16 0.10 A
AND
ANI
OR
D0.0 0.30 0.24 0.15 6
ORI

LDP
LDF X0 7
ANDP
0.30 0.24 0.15
ANDF
ORP D0.0 8
ORF

ANB
ORB
MPS –– 0.20 0.16 0.10

Appendix 1.2 Operation Processing Time of Basic Model QCPU

Appendix1 OPERATION PROCESSING TIME
MRD
MPP
When not executed
INV 0.20 0.16 0.10
When executed
MEP When not executed
0.30 0.24 0.15
MEF When executed

(OFF OFF)
When not executed
(ON ON)
EGP 0.20 0.16 0.10
(OFF ON)
When executed
(ON OFF)

(OFF OFF)
When not executed 17 9.5 9.4
(ON ON)
EGF
(OFF ON)
When executed 18 14 14
(ON OFF)

App-3
 Processing Time (µs)
Instruction Condition (Device)
Q00JCPU Q00CPU Q01CPU
When not (OFF OFF)
0.20 0.16 0.10
changed (ON ON)
Y
When (OFF ON)
0.20 0.16 0.10
changed (ON OFF)
When not (OFF OFF)
0.40 0.32 0.20
changed (ON ON)
D0.0
When (OFF ON)
0.40 0.32 0.20
changed (ON OFF)
When OFF 24 20 19
OUT
F When When displayed 260 210 200
ON Display completed 205 165 155
When not executed 1.1 0.88 0.55
After time up 1.1 0.88 0.55
T When
K 1.1 0.88 0.55
executed When added
D 1.2 0.96 0.60
When not executed 1.1 0.88 0.55
After time up 1.1 0.88 0.55
C When
K 1.1 0.88 0.55
executed When added
D 1.2 0.96 0.60
When not executed 1.1 0.88 0.55
After time up 1.1 0.88 0.55
OUTH T When
K 1.1 0.88 0.55
executed When added
D 1.2 0.96 0.60
When not executed 0.20 0.16 0.10
Y When When not changed (ON ON) 0.20 0.16 0.10
executed When changed (OFF ON) 0.20 0.16 0.10
When not executed 0.40 0.32 0.20
SET D0.0 When When not changed (ON ON) 0.40 0.32 0.20
executed When changed (OFF ON) 0.40 0.32 0.20
When not executed 0.50 0.44 0.25
F When When displayed 255 205 195
executed Display completed 195 160 150
When not executed 0.20 0.16 0.10
Y When When not changed (OFF OFF) 0.20 0.16 0.10
executed When changed (ON OFF) 0.20 0.16 0.10
When not executed 0.40 0.32 0.20
D0.0 When When not changed (ON ON) 0.40 0.32 0.20
executed When changed (OFF ON) 0.40 0.32 0.20
When not executed 0.20 0.16 0.10
SM
When executed 0.20 0.16 0.10
When not executed 0.48 0.44 0.25
RST
F When When displayed 75 69 65
executed Display completed 43 35 33
When not executed 0.80 0.64 0.40
T, C
When executed 1.0 0.80 0.50
When not executed 0.40 0.32 0.20
D
When executed 0.60 0.48 0.30
When not executed 0.50 0.40 0.25
Z
When executed 9.4 7.9 7.4
When not executed –– 0.32 0.20
R
When executed –– 0.48 0.30

App-4
 Processing Time (µs)
Instruction Condition (Device)
Q00JCPU Q00CPU Q01CPU
8
PLS 12 9.5 9.2
PLF 11 9.5 8.9

FF Y
When not executed
When executed
0.68
7.5
0.40
6.2
0.25
5.7
8
When not executed 0.50 0.40 0.25
DELTA DY0
When executed 26 21 21
When not executed 0.48 0.40 0.25
8
DELTAP DY0
When executed 58 45 43
SFT When not executed 0.50 0.34 0.25
SFTP When executed 12 8.7 8.3 8
M0 0.40 0.32 0.20
MC
D0.0 3.3 2.9 2.8
MCR –– 0.20 0.16 0.10 A
Error check performed 660 600 520
No error check performed
FEND
END
(• Battery check)
(• Fuse blown check)
660 600 520 6
(• I/O module verification)
NOP –– 0.20 0.16 0.10
NOPLF 7
–– 0.20 0.16 0.10
PAGE

8
(2) Basic instructions
The processing time when the instruction is not executed is calculated as follows:
Q00JCPU ··················································· 0.20 (No. of steps for each instruction + 1) µs
Q00CPU ····················································· 0.16 (No. of steps for each instruction + 1) µs

Appendix 1.2 Operation Processing Time of Basic Model QCPU

Appendix1 OPERATION PROCESSING TIME
Q01CPU ····················································· 0.10 (No. of steps for each instruction + 1) µs

Processing Time (µs)

Instruction Condition (Device)
Q00JCPU Q00CPU Q01CPU
In conductive status 0.80 0.64 0.40
LD =
In non-conductive status 0.80 0.64 0.40
When not executed 0.70 0.56 0.35
AND = In conductive status 0.80 0.64 0.40
When executed
In non-conductive status 0.80 0.64 0.40
When not executed 0.70 0.56 0.35
OR = In conductive status 0.80 0.64 0.40
When executed
In non-conductive status 0.80 0.64 0.40
In conductive status 0.80 0.64 0.40
LD < >
In non-conductive status 0.80 0.64 0.40
When not executed 0.70 0.56 0.35
AND < > In conductive status 0.80 0.64 0.40
When executed
In non-conductive status 0.80 0.64 0.40

App-5
 Processing Time (µs)
Instruction Condition (Device)
Q00JCPU Q00CPU Q01CPU
When not executed 0.70 0.56 0.35
OR < > In conductive status 0.80 0.64 0.40
When executed
In non-conductive status 0.80 0.64 0.40
In conductive status 0.80 0.64 0.40
LD >
In non-conductive status 0.80 0.64 0.40
When not executed 0.70 0.56 0.35
AND > In conductive status 0.80 0.64 0.40
When executed
In non-conductive status 0.80 0.64 0.40
When not executed 0.70 0.56 0.35
OR > In conductive status 0.80 0.64 0.40
When executed
In non-conductive status 0.80 0.64 0.40
In conductive status 0.80 0.64 0.40
LD < =
In non-conductive status 0.80 0.64 0.40
When not executed 0.70 0.56 0.35
AND < = In conductive status 0.80 0.64 0.40
When executed
In non-conductive status 0.80 0.64 0.40
When not executed 0.70 0.56 0.35
OR < = In conductive status 0.80 0.64 0.40
When executed
In non-conductive status 0.80 0.64 0.40
In conductive status 0.80 0.64 0.40
LD <
In non-conductive status 0.80 0.64 0.40
When not executed 0.70 0.56 0.35
AND < In conductive status 0.80 0.64 0.40
When executed
In non-conductive status 0.80 0.64 0.40
When not executed 0.70 0.56 0.35
OR < In conductive status 0.80 0.64 0.40
When executed
In non-conductive status 0.80 0.64 0.40
In conductive status 0.80 0.64 0.40
LD > =
In non-conductive status 0.80 0.64 0.40
When not executed 0.70 0.56 0.35
AND > = In conductive status 0.80 0.64 0.40
When executed
In non-conductive status 0.80 0.64 0.40
When not executed 0.70 0.56 0.35
OR > = In conductive status 0.80 0.64 0.40
When executed
In non-conductive status 0.80 0.64 0.40
In conductive status 1.0 0.80 0.50
LDD =
In non-conductive status 1.0 0.80 0.50
When not executed 0.80 0.64 0.40
ANDD = In conductive status 1.0 0.80 0.50
When executed
In non-conductive status 1.0 0.80 0.50
When not executed 0.80 0.64 0.40
ORD = In conductive status 1.0 0.80 0.50
When executed
In non-conductive status 1.0 0.80 0.50
In conductive status 1.0 0.80 0.50
LDD < >
In non-conductive status 1.0 0.80 0.50
When not executed 0.80 0.64 0.40
ANDD < > In conductive status 1.0 0.80 0.50
When executed
In non-conductive status 1.0 0.80 0.50

App-6
 Processing Time (µs)
Instruction Condition (Device)
Q00JCPU Q00CPU Q01CPU 8
When not executed 0.80 0.64 0.40
ORD < > In conductive status 1.0 0.80 0.50
When executed
In non-conductive status 1.0 0.80 0.50
8
In conductive status 1.0 0.80 0.50
LDD >
In non-conductive status 1.0 0.80 0.50
When not executed 0.80 0.64 0.40
8
ANDD > In conductive status 1.0 0.80 0.50
When executed
In non-conductive status 1.0 0.80 0.50
When not executed 0.80 0.64 0.40
8
ORD > In conductive status 1.0 0.80 0.50
When executed
In non-conductive status 1.0 0.80 0.50

LDD < =
In conductive status 1.0 0.80 0.50
A
In non-conductive status 1.0 0.80 0.50
When not executed 0.80 0.64 0.40
ANDD < =
When executed
In conductive status
In non-conductive status
1.0
1.0
0.80
0.80
0.50
0.50
6
When not executed 0.80 0.64 0.40
ORD < =
When executed
In conductive status
In non-conductive status
1.0
1.0
0.80
0.80
0.50
0.50
7
In conductive status 1.0 0.80 0.50
LDD <
In non-conductive status 1.0 0.80 0.50
When not executed 0.80 0.64 0.40
8
ANDD < In conductive status 1.0 0.80 0.50
When executed
In non-conductive status 1.0 0.80 0.50
When not executed 0.80 0.64 0.40

Appendix 1.2 Operation Processing Time of Basic Model QCPU

Appendix1 OPERATION PROCESSING TIME
ORD < In conductive status 1.0 0.80 0.50
When executed
In non-conductive status 1.0 0.80 0.50
In conductive status 1.0 0.80 0.50
LDD > =
In non-conductive status 1.0 0.80 0.50
When not executed 0.80 0.64 0.40
ANDD > = In conductive status 1.0 0.80 0.50
When executed
In non-conductive status 1.0 0.80 0.50
When not executed 0.80 0.64 0.40
ORD > = In conductive status 1.0 0.80 0.50
When executed
In non-conductive status 1.0 0.80 0.50

BKCMP = S1 S2 D n n=1 130 105 97

BKCMP = P S1 S2 D n n = 96 205 175 165

BKCMP<> S1 S2 D n n=1 130 105 98

BKCMP<>P S1 S2 D n n = 96 210 180 165

BKCMP> S1 S2 D n n=1 130 105 97

BKCMP>P S1 S2 D n n = 96 210 180 165

BKCMP>= S1 S2 D n n=1 130 105 98

BKCMP>=P S1 S2 D n n = 96 205 175 165

App-7
 Processing Time (µs)
Instruction Condition (Device)
Q00JCPU Q00CPU Q01CPU

BKCMP< S1 S2 D n n=1 130 105 98

BKCMP<P S1 S2 D n n = 96 210 180 165

BKCMP<= S1 S2 D n n=1 130 105 97

BKCMP<=P S1 S2 D n n = 96 205 175 165

+ S D
When executed 1.0 0.80 0.50
+P S D

+ S1 S2 D
When executed 1.2 0.96 0.60
+P S1 S2 D

- S D
When executed 1.0 0.80 0.50
-P S D

- S1 S2 D
When executed 1.2 0.96 0.60
- P S1 S2 D

D+ S D
When executed 1.3 1.04 0.65
D+P S D

D+ S1 S2 D
When executed 1.5 1.2 0.75
D+P S1 S2 D

D- S D
When executed 1.3 1.04 0.65
D-P S D

D - S1 S2 D
When executed 1.5 1.2 0.75
D - P S1 S2 D

* S1 S2 D
When executed 1.1 0.88 0.55
* P S1 S2 D

/ S1 S2 D
–– 19 16 15
/P S1 S2 D

D * S1 S2 D
–– 41 34 31
D * P S1 S2 D

D/ S1 S2 D
–– 28 23 21
D/P S1 S2 D

B+ S D
–– 34 28 26
B+P S D

B+ S1 S2 D
–– 47 39 37
B+P S1 S2 D

B- S D
–– 34 28 26
B-P S D

B - S1 S2 D
–– 48 40 38
B - P S1 S2 D

DB+ S D
–– 58 48 44
DB+P S D

DB+ S1 S2 D
–– 60 49 46
DB+P S1 S2 D

DB - S D
–– 59 48 45
DB - P S D

DB - S1 S2 D
–– 60 51 45
DB - P S1 S2 D

App-8
 Processing Time (µs)
Instruction Condition (Device)
Q00JCPU Q00CPU Q01CPU 8
B* S1 S2 D
–– 42 35 33
B * P S1 S2 D
8
B/ S1 S2 D
–– 48 40 37
B/P S1 S2 D

DB * S1 S2 D 8
–– 140 120 110
DB * P S1 S2 D

DB/ S1 S2 D
–– 83 69 65 8
DB/P S1 S2 D

BK + S1 S2 D n n=1 105 86 80

n = 96 185 155 140

A
BK + P S1 S2 D n

BK - S1 S2 D n n=1 105 86 80

BK - P S1 S2 D n n = 96 185 155 140 6

INC
–– 0.70 0.56 0.35
INCP
DINC 7
–– 0.90 0.72 0.45
DINCP
DEC
–– 0.70 0.56 0.35
DECP 8
DDEC
–– 0.90 0.72 0.45
DDECP
BCD
–– 20 16 15
BCDP

Appendix 1.2 Operation Processing Time of Basic Model QCPU

Appendix1 OPERATION PROCESSING TIME
DBCD
–– 26 21 20
DBCDP
BIN
–– 19 16 15
BINP
DBIN
–– 22 18 17
DBINP
DBL
–– 19 16 15
DBLP
WORD
–– 23 19 17
WORDP
GRY
–– 19 16 15
GRYP
DGRY
–– 23 19 17
DGRYP
GBIN
–– 52 42 40
GBINP
DGBIN
–– 110 88 84
DGBINP
NEG
–– 16 13 12
NEGP
DNEG
–– 19 17 15
DNEGP

App-9
 Processing Time (µs)
Instruction Condition (Device)
Q00JCPU Q00CPU Q01CPU

BKBCD S D n n=1 78 63 57

BKBCDP S D n n = 96 315 275 250

BKBIN S D n n=1 74 61 57

BKBINP S D n n = 96 285 255 230

MOV S = D0, D = D1 0.70 0.56 0.35

MOVP 155 130 120
S = D0, D = J1 \ W1

DMOV S = D0, D = D1 0.90 0.72 0.45

DMOVP 165 135 120
S = D0, D = J1 \ W1

$MOV 0 characters 46 38 35
$MOVP 32 characters 98 80 73
CML
–– 0.70 0.56 0.35
CMLP
DCML
–– 0.90 0.72 0.45
DCMLP

BMOV S D n n=1 27 21 20

BMOVP S D n n = 96 72 62 53

FMOV S D n n=1 23 19 17

FMOVP S D n n = 96 48 41 36

XCH
–– 7.6 6.3 5.7
XCHP

DXCH
–– 9.5 8.0 7.1
DXCHP

BXCH D1 D2 n n=1 62 51 48

BXCHP D1 D2 n n = 96 165 140 125

SWAP
–– 17 14 13
SWAPP
CJ –– 10 8.5 8.1
SCJ –– 10 8.5 8.1
JMP –– 11 8.5 8.1
GOEND –– 3.3 2.9 2.8
DI –– 13 12 11
EI –– 14 11 11
IMASK –– 41 34 35
IRET –– 205 170 155
n=1 55 46 43
X
RFS n = 96 79 64 59
RFSP n=1 54 45 41
Y
n = 96 73 61 56

App-10
 (3) Application instructions
The processing time when the instruction is not executed is calculated as follows:
Q00JCPU ··················································· 0.20 (No. of steps for each instruction + 1) µs
8
Q00CPU ····················································· 0.16 (No. of steps for each instruction + 1) µs
Q01CPU ····················································· 0.10 (No. of steps for each instruction + 1) µs
8

Processing Time (µs)

Instruction Condition (Device)
Q00JCPU Q00CPU Q01CPU
8
WAND S D
When executed 1.0 0.80 0.50
WANDP S D 8
WAND S1 S2 D
When executed 1.2 0.96 0.60
WANDP S1 S2
A
D

DAND S D
When executed 1.3 1.04 0.65
DANDP S D

DAND S1 S2 D
6
When executed 1.5 1.2 0.75
DANDP S1 S2 D

BKAND S1 S2 D n n=1 110 87 79 7

BKANDP S1 S2 D n n = 96 185 155 140

WOR S D
When executed 1.0 0.80 0.50 8
WORP S D

WOR S1 S2 D
When executed 1.2 0.96 0.60
WORP S1 S2 D

Appendix 1.2 Operation Processing Time of Basic Model QCPU

Appendix1 OPERATION PROCESSING TIME
DOR S D
When executed 1.3 1.04 0.65
DORP S D

DOR S1 S2 D
When executed 1.5 1.2 0.75
DORP S1 S2 D

BKOR S1 S2 D n n=1 110 87 81

BKORP S1 S2 D n n = 96 185 155 140

WXOR S D
When executed 1.0 0.80 0.50
WXORP S D

WXOR S1 S2 D
When executed 1.2 0.96 0.60
WXORP S1 S2 D

DXOR S D
When executed 1.3 1.04 0.65
DXORP S D

DXOR S1 S2 D
When executed 1.5 1.2 0.75
DXORP S1 S2 D

BKXOR S1 S2 D n n=1 110 87 81

BKXORP S1 S2 D n n = 96 185 155 140

App-11
 Processing Time (µs)
Instruction Condition (Device)
Q00JCPU Q00CPU Q01CPU

WXNR S D
When executed 1.0 0.80 0.50
WXNRP S D

WXNR S1 S2 D
When executed 1.2 0.96 0.60
WXNRP S1 S2 D

DXNR S D
When executed 1.3 1.04 0.65
DXNRP S D

DXNR S1 S2 D
When executed 1.5 1.2 0.75
DXNRP S1 S2 D

BKXNR S1 S2 D n n=1 110 87 82

BKXNRP S1 S2 D n n = 96 185 155 140

ROR D n n=1 13 11 9.7

RORP D n n = 15 13 11 9.7

RCR D n n=1 15 12 12

RCRP D n n = 15 15 13 12

ROL D n n=1 13 11 10

ROLP D n n = 15 13 11 10

RCL D n n=1 15 13 12

RCLP D n n = 15 16 13 12

DROR D n n=1 15 12 12

DRORP D n n = 31 15 13 12

DRCR D n n=1 17 14 14

DRCRP D n n = 31 18 16 15

DROL D n n=1 14 13 12

DROLP D n n = 31 14 13 12

DRCL D n n=1 18 15 14

DRCLP D n n = 31 20 17 16

SFR D n n=1 13 10 9.7

SFRP D n n = 15 13 11 9.5

SFL D n n=1 12 10 9.5

SFLP D n n = 15 12 9.8 9.5

BSFLR D n n=1 42 35 33

BSFLRP D n n = 96 69 58 54

BSFL D n n=1 41 34 32

BSFLP D n n = 96 63 53 50

DSFR D n n=1 19 16 15

DSFRP D n n = 96 71 61 53

DSFL D n n=1 19 16 15

DSFLP D n n = 96 70 60 52

App-12
 Processing Time (µs)
Instruction Condition (Device)
Q00JCPU Q00CPU Q01CPU 8
BSET D n n=1 27 22 20

BSETP D n n = 15 27 22 20
8
BRST D n n=1 27 22 21

BRSTP D n n = 15 27 22 21

TEST S1 S2 D
8
–– 35 30 27
TESTP S1 S2 D

DTEST S1 S2 D
–– 37 31 28
8
DTESTP S1 S2 D

n=1 49 41 38
BKRST D n
A
BKRSTP D n n = 96 64 54 50

All match 56 54 42
n=1
SER S1 S2 D n None match 56 54 42 6
SERP S1 S2 D n
All match 280 240 220
n = 96
None match 280 240 220

n=1
All match 71 67 53 7
DSER S1 S2 D n None match 71 67 54

DSERP S1 S2 D n
All match 495 415 375
n = 96
None match 500 415 375 8
SUM S =0 32 26 25
SUMP 27 22 21
S = FFFFH

DSUM S =0 54 44 42

Appendix 1.2 Operation Processing Time of Basic Model QCPU

Appendix1 OPERATION PROCESSING TIME
DSUMP 54 44 42
S = FFFFFFFFH

DECO S D n n=2 60 50 46

DECOP S D n n=8 80 65 61

M1 = ON 66 55 51
n=2
ENCO S D n M4 = ON 66 54 51

ENCOP S D n
M1 = ON 90 76 71
n=8
M256 = ON 76 74 71
SEG
–– 8.0 6.8 6.1
SEGP

DIS S D n n=1 47 39 36

DISP S D n n=4 53 43 40

UNI S D n n=1 54 44 41

UNIP S D n n=4 60 49 46

NDIS S1 D S2
–– 92 76 38
NDISP S1 D S2

NUNI S1 D S2
–– 47 39 36
NUNIP S1 D S2

App-13
 Processing Time (µs)
Instruction Condition (Device)
Q00JCPU Q00CPU Q01CPU

WTOB S D n n=1 56 46 42

WTOBP S D n n = 96 190 155 145

BTOW S D n n=1 56 46 42

BTOWP S D n n = 96 190 155 145

MAX S D n n=1 48 40 36

MAXP S D n n = 96 300 240 235

MIN S D n n=1 48 40 36

MINP S D n n = 96 300 240 235

DMAX S D n n=1 52 43 39

DMAXP S D n n = 96 600 490 460

DMIN S D n n=1 52 43 39

DMINP S D n n = 96 585 475 445

n=1 66 55 50
SORT S1 n S2 D1 D2
n = 96 105 86 80
n=1 98 57 52
DSORT S1 n S2 D1 D2
n = 96 115 96 88

WSUM S D n n=1 52 43 40

WSUMP S D n n = 96 175 140 135

DWSUM S D n n=1 61 51 46

DWSUMP S D n n = 96 515 420 395

FOR n n=0 11 8.9 8.1

NEXT –– 8.8 7.3 6.8
BREAK
–– 37 30 28
BREAKP
CALL Pn
–– 17 14 13
CALLP Pn

CALL Pn S1 to S5
–– 245 200 190
CALLP Pn S1 to S5
RET Return to original program 16 13 12
FCALL Pn
–– 29 24 22
FCALLP Pn

FCALL Pn S1 to S5
–– 250 205 190
FCALLP Pn S1 to S5

App-14
 Processing Time (µs)
Instruction Condition (Device)
Q00JCPU Q00CPU Q01CPU 8
COM –– 110 77 72
IX –– 65 54 51
IXEND –– 30 26 25
8
Number of contacts 1 145 120 110
IXDEV + IXSET
Number of contacts 14 770 630 585
FIFW Number of data points 0 36 32 28 8
FIFWP Number of data points 96 36 32 28
FIFR Number of data points 1 45 41 36
FIFRP Number of data points 96 93 82 70 8
FPOP Number of data points 1 40 37 32
FPOPP Number of data points 96 40 37 32
FINS Number of data points 0 53 44 38 A
FINSP Number of data points 96 100 89 76
FDEL Number of data points 1 60 50 43
FDELP Number of data points 96 110 95 82 6
FROM n1 n2 D n3 n3 = 1 125 105 93

FROMP n1 n2 D n3 *1 n3 = 1000 740 695 685

7
DFRO n1 n2 D n3 n3 = 1 130 110 100

DFROP n1 n2 D n3 *1 n3 = 500 745 695 675

8
TO n1 n2 S n3 n3 = 1 120 105 92

TOP n1 n2 S n3 *1 n3 = 1000 735 680 645

DTO n1 n2 S n3 n3 = 1 130 110 99

Appendix 1.2 Operation Processing Time of Basic Model QCPU

Appendix1 OPERATION PROCESSING TIME
DTOP n1 n2 S n3 *1 n3 = 500 740 680 640

*1 : The FROM/TO instruction differs in processing time according to the number of slots and the loaded
modules. (The CPU also differs in processing time according to the extension base type.)

App-15
 Processing Time (µs)
Instruction Condition (Device)
Q00JCPU Q00CPU Q01CPU
LIMIT
–– 34 28 26
LIMITP
DLIMIT
–– 41 34 30
DLIMITP
BAND
–– 33 28 25
BANDP
DBAND
–– 40 34 30
DBANDP
ZONE
–– 31 25 24
ZONEP
DZONE
–– 37 29 28
DZONEP
RSET
–– –– 18 16
RSETP
DATERD
–– 30 25 23
DATERDP
DATEWR
–– 69 57 54
DATEWRP
DATE+ No digit increase 47 39 36
DATE+P Digit increase 50 42 38
DATE - No digit increase 47 40 36
DATE - P Digit increase 50 42 38
SECOND
–– 28 24 22
SECONDP
HOUR
–– 38 32 29
HOURP
WDT
–– 18 15 14
WDTP
DUTY –– 41 36 32
ZRRDB
–– –– 24 22
ZRRDBP
ZRWRB
–– –– 27 24
ZRWRBP
ADRSET
–– 23 19 18
ADRSETP
ZPUSH
–– 38 33 30
ZPUSHP
ZPOP
–– 37 31 29
ZPOPP
ZCOM –– 105 82 80

(4) Processing time for QCPU instructions (QCPU instructions only)

Processing Time (µs)
Instruction Condition (Device)
Q00JCPU Q00CPU Q01CPU
UNIRD n=1 96 80 74
UNIRDP n = 16 440 370 340

App-16
 (5) Instructions executable by the product with the first 5 digits of the serial No. "04122" or higher

Instruction Condition (Device)

Processing Time (µs) 8
Q00JCPU Q00CPU Q01CPU
In conductive status 43.0 35.5 33.0
LDE = Single precision
In non-conductive status 46.0 38.0 35.5 8
When not executed 1.5 1.2 1.0
ANDE = Single precision In conductive status 35.5 29.5 26.5
When executed
In non-conductive status 42.0 35.0 32.5 8
When not executed 1.5 1.2 1.0
ORE = Single precision In conductive status 42.0 35.0 32.5
When executed
In non-conductive status 37.0 31.0 28.5 8
In conductive status 46.0 38.0 35.5
LDE < > Single precision
In non-conductive status 43.5 36.0 33.0
When not executed 1.5 1.2 1.0
A
ANDE < > Single precision In conductive status 38.5 31.5 29.0
When executed
In non-conductive status
When not executed
39.5
1.5
33.0
1.2
30.5
1.0
6
ORE < > Single precision In conductive status 45.0 37.5 35.0
When executed
In non-conductive status 34.5 29.0 26.5
7
In conductive status 46.0 37.5 35.5
LDE > Single precision
In non-conductive status 46.0 38.5 35.0
When not executed 1.5 1.2 1.0 8
ANDE > Single precision In conductive status 38.5 32.0 29.0
When executed
In non-conductive status 42.0 35.0 32.5
When not executed 1.5 1.2 1.0
ORE > Single precision In conductive status 45.0 37.5 34.5

Appendix 1.2 Operation Processing Time of Basic Model QCPU

Appendix1 OPERATION PROCESSING TIME
When executed
In non-conductive status 37.0 31.0 29.0
In conductive status 45.5 37.5 35.0
LDE < = Single precision
In non-conductive status 46.5 38.5 35.5
When not executed 1.5 1.2 1.0
ANDE < = Single precision In conductive status 38.5 31.5 29.0
When executed
In non-conductive status 42.5 35.5 32.5
When not executed 1.5 1.2 1.0
ORE < = Single precision In conductive status 45.0 37.5 34.5
When executed
In non-conductive status 37.5 31.5 28.5
In conductive status 45.5 37.5 35.0
LDE < Single precision
In non-conductive status 46.5 38.5 35.5
When not executed 1.5 1.2 1.0
ANDE < Single precision In conductive status 38.0 31.5 29.0
When executed
In non-conductive status 42.5 35.5 32.5
When not executed 1.5 1.2 1.0
ORE < Single precision In conductive status 45.0 37.5 34.5
When executed
In non-conductive status 37.5 31.5 29.0
In conductive status 45.5 38.0 35.5
LDE > = Single precision
In non-conductive status 46.5 38.0 35.0
When not executed 1.5 1.2 1.0
ANDE > = Single precision In conductive status 38.5 32.0 29.0
When executed
In non-conductive status 42.5 35.5 32.5

App-17
 Processing Time (µs)
Instruction Condition (Device)
Q00JCPU Q00CPU Q01CPU
When not executed 1.5 1.2 1.0
ORE > = Single precision In conductive status 45.0 38.5 34.5
When executed
In non-conductive status 37.5 31.0 28.5

E+ S D S = 0, D = 0 29.5 25.0 23.0

Single precision
E+P S D S = 2127, D = 2127 65.5 60.5 49.5

E+ S1 S2 D S1 = 0, S2 = 0 31.0 27.0 24.0

Single precision
E+P S1 S2 D S1 = 2127, S2 = 2127 66.5 56.0 51.0

E- S D S = 0, D = 0 29.5 25.0 23.0

Single precision
E -P S D S = 2127, D = 2127 48.5 41.0 37.5

E - S1 S2 D S1 = 0, S2 = 0 31.0 27.0 24.0

Single precision
E -P S1 S2 D S1 = 2127, S2 = 2127 50.5 42.5 38.5

E* S1 S2 D S1 = 0, S2 = 0 30.0 25.5 23.0

Single precision
E*P S1 S2 D S1 = 2127, S2 = 2127 65.5 55.0 49.5

E/ S1 S2 D S1 = 0, S2 = 1 30.0 26.0 23.0

Single precision
E/P S1 S2 D S1 = 2127, S2 = - 2126 69.5 57.5 53.0

INT S =0 21.5 18.5 16.0

Single precision
INTP 38.0 32.0 29.5
S = 32766.5

DINT S =0 23.0 19.5 17.5

Single precision
DINTP 42.0 35.5 32.0
S = 1234567890.3

FLT S =0 22.5 19.5 17.0

Single precision
FLTP 26.5 23.0 20.0
S = 7FFFH

DFLT S =0 23.0 20.0 17.5

Single precision
DFLTP 26.0 23.5 19.5
S = 7FFFFFFFH

ENEG S =0 20.5 17.0 15.5

ENEGP 31.5 26.0 24.0
S = E - 1.0
EMOV
–– 1.5 1.2 1.0
EMOVP
ESTR
–– 604.0 686.0 831.0
ESTRP
EVAL Decimal point format all 2-digit specification 138.0 148.0 196.0
EVALP Exponent format all 6-digit specification 164.0 177.0 214.0

App-18
 Processing Time (µs)
Instruction Condition (Device)
Q00JCPU Q00CPU Q01CPU 8
SIN
Single precision 204.0 173.0 157.0
SINP
COS
COSP
Single precision 187.0 158.0 144.0 8
TAN
Single precision 224.0 190.0 173.0
TANP
RAD
Single precision 51.0 43.0 39.0
8
RADP
DEG
Single precision 51.0 43.0 39.0
DEGP 8
SQR
Single precision 60.0 51.0 46.5
SQRP

EXP
Single precision
S = - 10 306.0 259.0 235.0
A
EXPP 306.0 259.0 235.0
S =1

73.0 61.5 56.0

LOG
LOGP
Single precision
S =1
6
S = 10 301.0 255.0 232.0

RND
–– 12.5 11.0 10.0
RNDP
7
SRND
–– 13.5 12.0 11.0
SRNDP

Appendix 1.2 Operation Processing Time of Basic Model QCPU

Appendix1 OPERATION PROCESSING TIME

App-19
Instruction Processing Time (µs)
Condition/Number of Points Processed
Name Q00JCPU Q00CPU Q01CPU
With auto refresh of CPU Refresh range: 2k words
–– 920 880
shared memory (0.5k words assigned equally to all CPUs)
COM *2
Without auto refresh of CPU
–– –– 150 135
shared memory
Read from CPU shared n3 = 1 –– 100 90
memory of host CPU n3 = 320 –– 440 420
FROM
Read from CPU shared n3 = 1 –– 110 105
memory of another CPU n3 = 320 –– 305 290
Write to CPU shared memory n3 = 1 –– 100 95
TO
of host CPU n3 = 320 –– 440 425
Write to CPU shared memory n4 = 1 –– 205 195
S.TO
of host CPU n4 = 320 –– 545 525

*2: If the processing overlaps those of the other CPUs in a multiple CPU system, the processing time increases
by a maximum of the following time.

For a system having only the main base unit

(Instruction processing time increase) = 4 0.54 (number of points
processed) (number of other CPUs) (µs)
For a system including extension base units
(Instruction processing time increase) = 4 1.30 (number of points
processed) (number of other CPUs) (µs)

(6) Table of the time to be added when file register, module access device or link direct device is
used

Device Specification Processing Time (µs)

Instruction Name data
Location Q00JCPU Q00CPU Q01CPU
Source –– 34 32
Bit
Destination –– 23 22
Source –– 13 12
File register (ZR) Word
Destination –– 9 8
Double Source –– 14 13
word Destination –– 10 9
Source 99 82 77
Bit
Destination 167 137 129
Module access device Source 74 61 58
Word
(Un\G , U3En\G0 to G511) Destination 72 60 56
Double Source 76 63 59
word Destination 92 75 71
Source 178 147 137
Bit
Destination 303 248 233
Source 154 126 118
Link direct device (Jn\ ) Word
Destination 153 125 117
Double Source 155 127 119
word Destination 163 133 125

App-20
 Appendix 1.3 Operation Processing Time of High Performance
Model QCPU/Process CPU/Redundant CPU 8

The processing time for the individual instructions are shown in the table on the following pages. 8
Operation processing time can vary substantially depending on the nature of the sources and
destinations of the instructions, and the values contained in the following tables should therefore
be taken as a set of general guidelines to processing times rather than as being strictly accurate. 8

(1) Sequence instructions 8

Processing Time (µs)
Instruction Condition (Device)
Qn QnH QnPH QnPRH
LD A
LDI
AND
–– 0.079 0.034 0.034 0.034
ANI
OR 6
ORI
LDP
LDF 7
ANDP
–– 0.158 0.068 0.068 0.068
ANDF
ORP
ORF
8
ANB
ORB
MPS –– 0.079 0.034 0.034 0.034
MRD

Appendix 1.3 Operation Processing Time of High Performance Model QCPU/Process CPU/Redundant CPU
Appendix1 OPERATION PROCESSING TIME
MPP
When not executed
INV 0.079 0.034 0.034 0.034
When executed
MEP When not executed
0.173 0.073 0.073 0.073
MEF When executed
(OFF OFF)
When not executed
EGP (ON ON)
0.158 0.068 0.068 0.068
EGF (OFF ON)
When executed
(ON OFF)

App-21
 Processing Time (µs)
Instruction Condition (Device)
Qn QnH QnPH QnPRH
(OFF OFF)
When not changed 0.158 0.068 0.068 0.068
(ON ON)
(OFF ON)
When changed 0.158 0.068 0.068 0.068
(ON OFF)
When OFF 2.8 1.2 1.2 1.2
F When When displayed 162 69.7 69.7 69.7
ON Display completed 126 54 54 54
OUT When not executed 0.63 0.27 0.27 0.27
After time up 0.63 0.27 0.27 0.27
T When
K 0.63 0.27 0.27 0.27
executed When added
D 0.63 0.27 0.27 0.27
When not executed 0.63 0.27 0.27 0.27
After time up 0.63 0.27 0.27 0.27
C When
K 0.63 0.27 0.27 0.27
executed When added
D 0.63 0.27 0.27 0.27
When not executed 0.63 0.27 0.27 0.27
After time up 0.63 0.27 0.27 0.27
OUTH T When
K 0.63 0.27 0.27 0.27
executed When added
D 0.63 0.27 0.27 0.27
When not executed 0.158 0.068 0.068 0.068
When not changed (ON ON) 0.158 0.068 0.068 0.068
When executed
When changed (OFF ON) 0.158 0.068 0.068 0.068
SET
When not executed 0.47 0.20 0.20 0.20
F When When displayed 161 69 69 69
executed Display completed 0.47 0.20 0.20 0.20
When not executed 0.158 0.068 0.068 0.068
When not changed (OFF OFF) 0.158 0.068 0.068 0.068
When executed
When changed (ON OFF) 0.158 0.068 0.068 0.068
When not executed 0.158 0.068 0.068 0.068
SM
When executed 0.158 0.068 0.068 0.068
When not executed 0.47 0.20 0.20 0.20
F When When displayed 90 38 38 38
executed Display completed 0.47 0.20 0.20 0.20
RST
When not executed 0.63 0.27 0.27 0.27
T, C
When executed 0.63 0.27 0.27 0.27
When not executed 0.24 0.10 0.10 0.10
D
When executed 0.24 0.10 0.10 0.10
When not executed 0.47 0.20 0.20 0.20
Z
When executed 4.3 1.9 1.9 1.9
When not executed 0.40 0.17 0.17 0.17
R
When executed 0.40 0.17 0.17 0.17
PLS
–– 1.0 0.44 0.44 0.44
PLF
When not executed 0.47 0.20 0.20 0.20
FF Y
When executed 0.47 0.20 0.20 0.20
DELTA When not executed 0.47 0.20 0.20 0.20
DY0
DELTAP When executed 5.9 2.6 2.6 2.6

App-22
 Processing Time (µs)
Instruction Condition (Device)
Qn QnH QnPH QnPRH 8
SFT When not executed 0.47 0.20 0.20 0.20
SFTP When executed 1.66 0.71 0.71 0.71
MC –– 0.24 0.10 0.10 0.10
8
MCR –– 0.079 0.034 0.034 0.034
Error check performed 380 150 150 500

FEND
No error check performed
(• Battery check)
8
END 380 150 150 500
(• Fuse blown check)
(• I/O module verification)
NOP –– 0.079 0.034 0.034 0.034 8
NOPLF
–– 0.079 0.034 0.034 0.034
PAGE
A

Appendix 1.3 Operation Processing Time of High Performance Model QCPU/Process CPU/Redundant CPU
Appendix1 OPERATION PROCESSING TIME

App-23
 (2) Basic instructions
The processing time when the instruction is not executed is calculated as follows:
Q02CPU ·····················································0.079 (No. of steps for each instruction + 1) µs
Q02HCPU, Q06HCPU, Q12HCPU, Q25HCPU, Q02PHCPU, Q06PHCPU, Q12PHCPU,
Q25PHCPU, Q12PRHCPU, Q25PRHCPU 0.034 (No. of steps for each instruction + 1) µs

Processing Time (µs)

Instruction Condition (Device)
Qn QnH QnPH QnPRH
In conductive status 0.24 0.10 0.10 0.10
LD =
In non-conductive status 0.24 0.10 0.10 0.10
When not executed 0.24 0.10 0.10 0.10
AND = When In conductive status 0.24 0.10 0.10 0.10
executed In non-conductive status 0.24 0.10 0.10 0.10
When not executed 0.24 0.10 0.10 0.10
OR = In conductive status 0.24 0.10 0.10 0.10
When executed
In non-conductive status 0.24 0.10 0.10 0.10
In conductive status 0.24 0.10 0.10 0.10
LD < >
In non-conductive status 0.24 0.10 0.10 0.10
When not executed 0.24 0.10 0.10 0.10
AND < > In conductive status 0.24 0.10 0.10 0.10
When executed
In non-conductive status 0.24 0.10 0.10 0.10
When not executed 0.24 0.10 0.10 0.10
OR < > In conductive status 0.24 0.10 0.10 0.10
When executed
In non-conductive status 0.24 0.10 0.10 0.10
In conductive status 0.24 0.10 0.10 0.10
LD >
In non-conductive status 0.24 0.10 0.10 0.10
When not executed 0.24 0.10 0.10 0.10
AND > In conductive status 0.24 0.10 0.10 0.10
When executed
In non-conductive status 0.24 0.10 0.10 0.10
When not executed 0.24 0.10 0.10 0.10
OR > In conductive status 0.24 0.10 0.10 0.10
When executed
In non-conductive status 0.24 0.10 0.10 0.10
In conductive status 0.24 0.10 0.10 0.10
LD < =
In non-conductive status 0.24 0.10 0.10 0.10
When not executed 0.24 0.10 0.10 0.10
AND < = In conductive status 0.24 0.10 0.10 0.10
When executed
In non-conductive status 0.24 0.10 0.10 0.10

App-24
 Processing Time (µs)
Instruction Condition (Device)
Qn QnH QnPH QnPRH 8
When not executed 0.24 0.10 0.10 0.10
OR < = In conductive status 0.24 0.10 0.10 0.10
When executed
In non-conductive status
In conductive status
0.24
0.24
0.10
0.10
0.10
0.10
0.10
0.10
8
LD <
In non-conductive status 0.24 0.10 0.10 0.10
When not executed 0.24 0.10 0.10 0.10
AND < In conductive status 0.24 0.10 0.10 0.10
8
When executed
In non-conductive status 0.24 0.10 0.10 0.10
When not executed 0.24 0.10 0.10 0.10
OR < In conductive status 0.24 0.10 0.10 0.10 8
When executed
In non-conductive status 0.24 0.10 0.10 0.10
In conductive status 0.24 0.10 0.10 0.10
LD > =
In non-conductive status 0.24 0.10 0.10 0.10 A
When not executed 0.24 0.10 0.10 0.10
AND > = In conductive status 0.24 0.10 0.10 0.10
When executed
In non-conductive status 0.24 0.10 0.10 0.10 6
When not executed 0.24 0.10 0.10 0.10
OR > = In conductive status 0.24 0.10 0.10 0.10
When executed
In non-conductive status 0.24 0.10 0.10 0.10
7
In conductive status 0.55 0.24 0.24 0.24
LDD =
In non-conductive status 0.39 0.17 0.17 0.17

ANDD =
When not executed
In conductive status
0.39
0.55
0.17
0.24
0.17
0.24
0.17
0.24
8
When executed
In non-conductive status 0.39 0.17 0.17 0.17
When not executed 0.39 0.17 0.17 0.17
ORD = In conductive status 0.55 0.24 0.24 0.24
When executed
In non-conductive status 0.55 0.24 0.24 0.24

Appendix 1.3 Operation Processing Time of High Performance Model QCPU/Process CPU/Redundant CPU
Appendix1 OPERATION PROCESSING TIME
In conductive status 0.55 0.24 0.24 0.24
LDD < >
In non-conductive status 0.55 0.24 0.24 0.24
When not executed 0.39 0.17 0.17 0.17
ANDD < > In conductive status 0.55 0.24 0.24 0.24
When executed
In non-conductive status 0.55 0.24 0.24 0.24
When not executed 0.39 0.17 0.17 0.17
ORD < > In conductive status 0.55 0.24 0.24 0.24
When executed
In non-conductive status 0.55 0.24 0.24 0.24
In conductive status 0.55 0.24 0.24 0.24
LDD >
In non-conductive status 0.55 0.24 0.24 0.24
When not executed 0.39 0.17 0.17 0.17
ANDD > In conductive status 0.55 0.24 0.24 0.24
When executed
In non-conductive status 0.55 0.24 0.24 0.24
When not executed 0.39 0.17 0.17 0.17
ORD > In conductive status 0.55 0.24 0.24 0.24
When executed
In non-conductive status 0.55 0.24 0.24 0.24
In conductive status 0.55 0.24 0.24 0.24
LDD < =
In non-conductive status 0.55 0.24 0.24 0.24
When not executed 0.39 0.17 0.17 0.17
ANDD < = In conductive status 0.55 0.24 0.24 0.24
When executed
In non-conductive status 0.55 0.24 0.24 0.24
When not executed 0.39 0.17 0.17 0.17
ORD < = In conductive status 0.55 0.24 0.24 0.24
When executed
In non-conductive status 0.55 0.24 0.24 0.24

App-25
 Processing Time (µs)
Instruction Condition (Device)
Qn QnH QnPH QnPRH
In conductive status 0.55 0.24 0.24 0.24
LDD <
In non-conductive status 0.55 0.24 0.24 0.24
When not executed 0.39 0.17 0.17 0.17
ANDD < In conductive status 0.55 0.24 0.24 0.24
When executed
In non-conductive status 0.55 0.24 0.24 0.24
When not executed 0.39 0.17 0.17 0.17
ORD < In conductive status 0.55 0.24 0.24 0.24
When executed
In non-conductive status 0.55 0.24 0.24 0.24
In conductive status 0.55 0.24 0.24 0.24
LDD > =
In non-conductive status 0.55 0.24 0.24 0.24
When not executed 0.39 0.17 0.17 0.17
ANDD > = In conductive status 0.55 0.24 0.24 0.24
When executed
In non-conductive status 0.55 0.24 0.24 0.24
When not executed 0.39 0.17 0.17 0.17
ORD > = In conductive status 0.55 0.24 0.24 0.24
When executed
In non-conductive status 0.55 0.24 0.24 0.24
93 40
In conductive status 6.4 6.4
Single 14.9 6.4
precision 92 40
In non-conductive status 6.4 6.4
14.9 6.4
*1
LDE =
93 40
In conductive status –– ––
Double 14.9 6.4
precision 92 40
In non-conductive status –– ––
14.9 6.4
When not executed 0.55 0.24 0.24 0.24
93 40
Single In conductive status 6.4 6.4
When 14.9 6.4
precision
executed 92 40
In non-conductive status 6.4 6.4
14.9 6.4
ANDE = *1
When not executed –– –– –– ––

93 40
Double In conductive status –– ––
When 14.9 6.4
precision
executed 92 40
In non-conductive status –– ––
14.9 6.4
When not executed 0.55 0.24 0.24 0.24
93 40
Single In conductive status 6.4 6.4
When 14.9 6.4
precision
executed 92 40
In non-conductive status 6.4 6.4
14.9 6.4
ORE = *1
When not executed 0.55 0.24 –– ––

93 40
Double In conductive status –– ––
When 14.9 6.4
precision
executed 92 40
In non-conductive status –– ––
14.9 6.4

*1 : The Qn/QnH changes in processing time depending on the serial No. of the CPU module.
Top : The first 5 digits of the serial No. are "05031" or lower
Bottom : The first 5 digits of the serial No. are "05032" or higher
For the condition to be satisfied when the instruction is not executed, there is no differentiation between the
top and bottom.

App-26
 Processing Time (µs)
Instruction Condition (Device)
Qn
92
QnH
40
QnPH QnPRH
8
In conductive status 6.4 6.4
Single 14.9 6.4
precision 92 40

LDE<> *1
In non-conductive status
14.9 6.4
6.4 6.4
8
92 40
In conductive status –– ––
Double 14.9 6.4
precision
In non-conductive status
92
14.9
40
6.4
–– –– 8
When not executed 0.55 0.24 0.24 0.24
92 40
Single
precision
When
In conductive status
14.9 6.4
6.4 6.4
8
executed 93 40
In non-conductive status 6.4 6.4
14.9 6.4
ANDE<> *1
When not executed 0.55
92
0.24
40
–– ––
A
Double In conductive status –– ––
When 14.9 6.4
precision
executed 92 40
In non-conductive status
14.9 6.4
–– ––
6
When not executed 0.55 0.24 0.24 0.24
93 40
Single In conductive status 6.4 6.4
precision
When
executed
14.9
92
6.4
40
7
In non-conductive status 6.4 6.4
14.9 6.4
ORE<> *1
When not executed 0.55 0.24 –– ––

Double In conductive status

93 40
–– ––
8
When 14.9 6.4
precision
executed 92 40
In non-conductive status –– ––
14.9 6.4
When not executed 92 40
6.4 6.4

Appendix 1.3 Operation Processing Time of High Performance Model QCPU/Process CPU/Redundant CPU
Appendix1 OPERATION PROCESSING TIME
Single 14.9 6.4
precision In conductive status 92 40
6.4 6.4
14.9 6.4
LDE> *1
92 40
–– ––
Double 14.9 6.4
In non-conductive status
precision 92 40
–– ––
14.9 6.4
When not executed 0.55 0.24 0.24 0.24
92 40
Single In conductive status 6.4 6.4
When 14.9 6.4
precision
executed 93 40
In non-conductive status 6.4 6.4
14.9 6.4
ANDE> *1
When not executed 0.55 0.24 –– ––
92 40
Double In conductive status –– ––
When 14.9 6.4
precision
executed 92 40
In non-conductive status –– ––
14.9 6.4
*1 : The Qn/QnH changes in processing time depending on the serial No. of the CPU module.
Top : The first 5 digits of the serial No. are "05031" or lower
Bottom : The first 5 digits of the serial No. are "05032" or higher
For the condition to be satisfied when the instruction is not executed, there is no differentiation between the
top and bottom.

App-27
 Processing Time (µs)
Instruction Condition (Device)
Qn QnH QnPH QnPRH
When not executed 0.55 0.24 0.24 0.24
93 40
Single In conductive status 6.4 6.4
When 14.9 6.4
precision
executed 92 40
In non-conductive status 6.4 6.4
14.9 6.4
ORE> *1
When not executed 0.55 0.24 –– ––
93 40
Double In conductive status –– ––
When 14.9 6.4
precision
executed 92 40
In non-conductive status –– ––
14.9 6.4
93 40
In conductive status 6.4 6.4
Single 14.9 6.4
precision 92 40
In non-conductive status 6.4 6.4
14.9 6.4
LDE<= *1
93 40
In conductive status –– ––
Double 14.9 6.4
precision 92 40
In non-conductive status –– ––
14.9 6.4
When not executed 0.55 0.24 0.24 0.24
92 40
Single In conductive status 6.4 6.4
When 14.9 6.4
precision
executed 92 40
In non-conductive status 6.4 6.4
14.9 6.4
ANDE<= *1
When not executed 0.55 0.24 –– ––
92 40
Double In conductive status –– ––
When 14.9 6.4
precision
executed 92 40
In non-conductive status –– ––
14.9 6.4
When not executed 0.55 0.24 0.24 0.24
92 40
Single In conductive status 6.4 6.4
When 14.9 6.4
precision
executed 92 40
In non-conductive status 6.4 6.4
14.9 6.4
ORE<= *1
When not executed 0.55 0.24 –– ––
92 40
Double In conductive status –– ––
When 14.9 6.4
precision
executed 92 40
In non-conductive status –– ––
14.9 6.4
92 40
In conductive status 6.4 6.4
Single 14.9 6.4
precision 92 40
In non-conductive status 6.4 6.4
14.9 6.4
LDE< *1
92 40
In conductive status –– ––
Double 14.9 6.4
precision 92 40
In non-conductive status –– ––
14.9 6.4
*1 : The Qn/QnH changes in processing time depending on the serial No. of the CPU module.
Top : The first 5 digits of the serial No. are "05031" or lower
Bottom : The first 5 digits of the serial No. are "05032" or higher
For the condition to be satisfied when the instruction is not executed, there is no differentiation between the
top and bottom.

App-28
 Processing Time (µs)
Instruction Condition (Device)
Qn QnH QnPH QnPRH 8
When not executed 0.55 0.24 0.24 0.24
92 40
Single In conductive status 6.4 6.4
precision
When 14.9 6.4
8
executed 92 40
In non-conductive status 6.4 6.4
14.9 6.4
ANDE< *1
When not executed 0.55 0.24 –– ––
8
92 40
Double In conductive status –– ––
When 14.9 6.4
precision
executed
In non-conductive status
92 40
–– –– 8
14.9 6.4
When not executed 0.55 0.24 0.24 0.24

Single In conductive status

93 40
6.4 6.4 A
When 14.9 6.4
precision
executed 92 40
In non-conductive status 6.4 6.4
ORE< *1
When not executed
14.9
0.55
6.4
0.24 –– ––
6
93 40
Double In conductive status –– ––
precision
When
executed
14.9
92
6.4
40
7
In non-conductive status –– ––
14.9 6.4
93 40
Single
In conductive status
14.9 6.4
6.4 6.4 8
precision 92 40
In non-conductive status 6.4 6.4
14.9 6.4
*1
LDE>=
93 40
In conductive status –– ––

Appendix 1.3 Operation Processing Time of High Performance Model QCPU/Process CPU/Redundant CPU
Appendix1 OPERATION PROCESSING TIME
Double 14.9 6.4
precision 92 40
In non-conductive status –– ––
14.9 6.4
When not executed 0.55 0.24 0.24 0.24
92 40
Single In conductive status 6.4 6.4
When 14.9 6.4
precision
executed 92 40
In non-conductive status 6.4 6.4
14.9 6.4
ANDE>= *1
When not executed 0.55 0.24 –– ––

92 40
Double In conductive status –– ––
When 14.9 6.4
precision
executed 92 40
In non-conductive status –– ––
14.9 6.4

*1 : The Qn/QnH changes in processing time depending on the serial No. of the CPU module.
Top : The first 5 digits of the serial No. are "05031" or lower
Bottom : The first 5 digits of the serial No. are "05032" or higher
For the condition to be satisfied when the instruction is not executed, there is no differentiation between the
top and bottom.

App-29
 Processing Time (µs)
Instruction Condition (Device)
Qn QnH QnPH QnPRH
When not executed 0.55 0.24 0.24 0.24
92 40
Single In conductive status 6.4 6.4
When 14.9 6.4
precision
executed 92 40
In non-conductive status 6.4 6.4
14.9 6.4
ORE>= *1
When not executed 0.55 0.24 –– ––

92 40
Double In conductive status –– ––
When 14.9 6.4
precision
executed 92 40
In non-conductive status –– ––
14.9 6.4
In conductive status 38 16 16 16
LD$ =
In non-conductive status 34 15 15 15
When not executed 0.56 0.23 0.23 0.23
AND$ = In conductive status 39 17 17 17
When executed
In non-conductive status 32 14 14 14
When not executed 0.56 0.24 0.24 0.24
OR$ = In conductive status 40 17 17 17
When executed
In non-conductive status 33 14 14 14
In conductive status 32 14 14 14
LD$ < >
In non-conductive status 40 17 17 17
When not executed 0.56 0.23 0.23 0.23
AND$ < > In conductive status 33 14 14 14
When executed
In non-conductive status 39 17 17 17
When not executed 0.56 0.24 0.24 0.24
OR$ < > In conductive status 32 14 14 14
When executed
In non-conductive status 39 17 17 17
In conductive status 32 14 14 14
LD$ >
In non-conductive status 40 17 17 17

*1 : The Qn/QnH changes in processing time depending on the serial No. of the CPU module.
Top : The first 5 digits of the serial No. are "05031" or lower
Bottom : The first 5 digits of the serial No. are "05032" or higher
For the condition to be satisfied when the instruction is not executed, there is no differentiation between the
top and bottom.

App-30
 Processing Time (µs)
Instruction Condition (Device)
Qn QnH QnPH QnPRH 8
When not executed 0.56 0.23 0.23 0.23
AND$ > In conductive status 33 14 14 14
When executed
In non-conductive status 39 17 17 17
8
When not executed 0.56 0.24 0.24 0.24
OR$ > In conductive status 32 14 14 14
When executed
In non-conductive status 39 17 17 17
8
In conductive status 40 17 17 17
LD$ < =
In non-conductive status 32 14 14 14
When not executed 0.56 0.23 0.23 0.23
8
AND$ < = In conductive status 39 17 17 17
When executed
In non-conductive status 32 14 14 14
When not executed 0.56 0.24 0.24 0.24
A
OR$ < = In conductive status 40 17 17 17
When executed
In non-conductive status 33 14 14 14

LD$ <
In conductive status
In non-conductive status
32
40
14
17
14
17
14
17
6
When not executed 0.56 0.23 0.23 0.23
AND$ <
When executed
In conductive status
In non-conductive status
32
39
14
16
14
16
14
16
7
When not executed 0.56 0.24 0.24 0.24
In conductive status 32 14 14 14
OR$ <
When executed
In non-conductive status 39 16 16 16
8
In conductive status 40 17 17 17
LD$ > =
In non-conductive status 32 14 14 14
When not executed 0.56 0.23 0.23 0.23

Appendix 1.3 Operation Processing Time of High Performance Model QCPU/Process CPU/Redundant CPU
Appendix1 OPERATION PROCESSING TIME
AND$ > = In conductive status 39 16 16 16
When executed
In non-conductive status 32 14 14 14
When not executed 0.56 0.24 0.24 0.24
OR$ > = In conductive status 39 17 17 17
When executed
In non-conductive status 32 14 14 14

BKCMP = S1 S2 D n n=1 48 21 21 21

BKCMP = P S1 S2 D n n = 96 142 61 61 61

BKCMP <> S1 S2 D n n=1 48 21 21 21

BKCMP <>P S1 S2 D n n = 96 150 65 65 65

BKCMP > S1 S2 D n n=1 48 21 21 21

BKCMP >P S1 S2 D n n = 96 142 61 61 61

BKCMP >= S1 S2 D n n=1 48 21 21 21

BKCMP >=P S1 S2 D n n = 96 150 65 65 65

BKCMP < S1 S2 D n n=1 48 21 21 21

BKCMP <P S1 S2 D n n = 96 158 68 68 68

BKCMP <= S1 S2 D n n=1 48 21 21 21

BKCMP <=P S1 S2 D n n = 96 150 65 65 65

App-31
 Processing Time (µs)
Instruction Condition (Device)
Qn QnH QnPH QnPRH

+ S D
When executed 0.39 0.17 0.17 0.17
+P S D

+ S1 S2 D
When executed 0.47 0.20 0.20 0.20
+P S1 S2 D

- S D
When executed 0.39 0.17 0.17 0.17
-P S D

- S1 S2 D
When executed 0.47 0.20 0.20 0.20
- P S1 S2 D

D+ S D
When executed 0.71 0.31 0.31 0.31
D+P S D

D+ S1 S2 D
When executed 0.79 0.34 0.34 0.34
D+P S1 S2 D

D- S D
When executed 0.71 0.30 0.30 0.30
D-P S D

D - S1 S2 D
When executed 0.79 0.34 0.34 0.34
D - P S1 S2 D

* S1 S2 D
When executed 0.47 0.20 0.20 0.20
* P S1 S2 D

/ S1 S2 D
–– 2.7 1.2 1.2 1.2
/P S1 S2 D

D * S1 S2 D
–– 7.9 3.4 3.4 3.4
D * P S1 S2 D

D/ S1 S2 D
–– 14 6.1 6.1 6.1
D/P S1 S2 D

B+ S D
–– 2.2 1.0 1.0 1.0
B+P S D

B+ S1 S2 D
–– 5.0 2.2 2.2 2.2
B+P S1 S2 D

B- S D
–– 2.0 0.9 0.9 0.9
B-P S D

B - S1 S2 D
–– 4.9 2.1 2.1 2.1
B - P S1 S2 D

DB+ S D
–– 12 5.0 5.0 5.0
DB+P S D

DB+ S1 S2 D
–– 12 5.3 5.3 5.3
DB+P S1 S2 D

DB - S D
–– 11 4.8 4.8 4.8
DB - P S D

DB - S1 S2 D
–– 12 5.2 5.2 5.2
DB - P S1 S2 D

B * S1 S2 D
–– 3.7 1.6 1.6 1.6
B * P S1 S2 D

App-32
 Processing Time (µs)
Instruction Condition (Device)
Qn QnH QnPH QnPRH 8
B/ S1 S2 D
–– 3.8 1.6 1.6 1.6
B/P S1 S2 D
8
DB * S1 S2 D
–– 24 10 10 10
DB * P S1 S2 D

DB/ S1 S2 D 8
–– 27 12 12 12
DB/P S1 S2 D

Single S = 0, D =0 1.8 0.78 0.78 0.78

8
precision 127 127 1.8 0.78 0.78 0.78
E+ S D S =2 , D =2

E+P S = 0, =0 203 87 –– ––
A
D
Double S D

precision 203 87
S = 2127, D = 2127 –– ––

Single S1 = 0, S2 =0 2.4 1.1 1.1 1.1

E+ S1 S2 D
precision
S1 = 2127, S2 = 2127 2.4 1.1 1.1 1.1
6
E+P S1 S2 D
Double S1 = 0, S2 =0 209 90 –– ––

precision
S1 = 2127, S2 = 2127 209 90 –– –– 7
Single S = 0, D =0 1.8 0.78 0.78 0.78
precision
E- S D S = 2127, D = 2127 1.8 0.78 0.78 0.78 8
E -P S D
Double S = 0, D =0 202 87 –– ––

precision 202 87
S = 2127, D = 2127 –– ––

Single S1 = 0, S2 =0 2.4 1.1 1.1 1.1

Appendix 1.3 Operation Processing Time of High Performance Model QCPU/Process CPU/Redundant CPU
Appendix1 OPERATION PROCESSING TIME
precision 2.4 1.1 1.1 1.1
E - S1 S2 D S1 = 2127, S2 = 2127

E -P S1 S2 D
Double S1 = 0, S2 =0 210 90 –– ––

precision 210 90
S1 = 2127, S2 = 2127 –– ––

Single S1 = 0, S2 =0 2.4 1.1 1.1 1.1

precision 2.4 1.1 1.1 1.1
E* S1 S2 D S1 = 2126, S2 = 2127

E*P S1 S2 D
Double S1 = 0, S2 =0 222 96 –– ––

precision 222 96
S1 = 2126, S2 = 2127 –– ––

Single S1 = 0, S2 =1 12 5.2 5.2 5.2

precision 12 5.2 5.2 5.2
E/ S1 S2 D S1 = 2127, S2 = - 2126

E/P S1 S2 D
Double S1 = 0, S2 =1 369 159 –– ––

precision 369 159

S1 = 2127, S2 = - 2126 –– ––

App-33
 Processing Time (µs)
Instruction Condition (Device)
Qn QnH QnPH QnPRH

$+ S D
–– 68 29 29 29
$+P S D

$+ S1 S2 D
–– 81 35 35 35
$+P S1 S2 D

INC
–– 0.32 0.14 0.14 0.14
INCP
DINC
–– 0.47 0.20 0.20 0.20
DINCP
DEC
–– 0.32 0.14 0.14 0.14
DECP
DDEC
–– 0.47 0.20 0.20 0.20
DDECP
BCD
–– 1.1 0.48 0.48 0.48
BCDP
DBCD
–– 3.2 1.4 1.4 1.4
DBCDP
BIN
–– 1.0 0.44 0.44 0.44
BINP
DBIN
–– 1.9 0.82 0.82 0.82
DBINP

Single S =0 3.2 1.4 1.4 1.4

precision 3.2 1.4 1.4 1.4
INT S = 32766.5
INTP 22 9.3 –– ––
Double S =0
precision 22 9.3 –– ––
S = 32766.5

Single S =0 2.5 1.1 1.1 1.1

precision 2.5 1.1 1.1 1.1
DINT S = 1234567890.3
DINTP 24 10 –– ––
Double S =0
precision 24 10 –– ––
S = 1234567890.3

Single S =0 2.1 0.92 0.92 0.92

precision 2.1 0.92 0.92 0.92
FLT S = 7FFFH
FLTP 22 9.6 –– ––
Double S =0
precision 22 9.6 –– ––
S = 7FFFH

Single S =0 2.1 0.88 0.88 0.88

precision 2.1 0.88 0.88 0.88
DFLT S = 7FFFFFFFH
DFLTP 26 11 –– ––
Double S =0
precision 26 11 –– ––
S = 7FFFFFFFH

App-34
 Processing Time (µs)
Instruction Condition (Device)
Qn QnH QnPH QnPRH 8
DBL
–– 4.5 1.9 1.9 1.9
DBLP
WORD
WORDP
–– 4.7 2.0 2.0 2.0 8
GRY
–– 4.7 2.0 2.0 2.0
GRYP
DGRY
–– 5.3 2.3 2.3 2.3
8
DGRYP
GBIN
–– 18 7.7 7.7 7.7
GBINP 8
DGBIN
–– 32 14 14 14
DGBINP
NEG
NEGP
–– 3.6 1.6 1.6 1.6 A
DNEG
–– 4.3 1.8 1.8 1.8
DNEGP
ENEG
–– 3.9 1.7 1.7 1.7
6
ENEGP

BKBCD S D n n=1 38 17 17 17

n = 96 99 43 43 43
7
BKBCDP S D n

BKBIN S D n n=1 38 17 17 17

BKBINP S D n n = 96 99 43 43 43 8
S = D0, D = D1 0.24 0.10 0.10 0.10

MOV –– –– –– ––
MOVP –– –– –– ––
S = D0, D = J1 \ W1

Appendix 1.3 Operation Processing Time of High Performance Model QCPU/Process CPU/Redundant CPU
Appendix1 OPERATION PROCESSING TIME
140*1 60*1 60*1 60*1

S = D0, D = D1 0.47 0.20 0.20 0.20

DMOV –– –– –– ––
DMOVP –– –– –– ––
S = D0, D = J1 \ W1
147*1 64*1 64*1 64*1
EMOV
–– 0.63 0.27 0.27 0.27
EMOVP
$MOV
–– 40 17 17 17
$MOVP
CML
–– 0.40 0.17 0.17 0.17
CMLP
DCML
–– 0.55 0.24 0.24 0.24
DCMLP

*1 : The upper row indicates the processing time when A38B/A1S38B and the extension base are used.
The center row indicates the processing time when A38HB/A1S38HB is used.
The lower row indicates the processing time when Q312B is used.

App-35
 Processing Time (µs)
Instruction Condition (Device)
Qn QnH QnPH QnPRH

BMOV S D n n=1 17 7.1 7.1 7.1

BMOVP S D n n = 96 32 14 14 14

FMOV S D n n=1 6.7 2.9 2.9 2.9

FMOVP S D n n = 96 14 6.1 6.1 6.1

XCH
XCHP
–– 1.3 0.54 0.54 0.54
DXCH
DXCHP

BXCH D1 D2 n n=1 31 13 13 13

BXCHP D1 D2 n n = 96 84 36 36 36

SWAP
–– 3.7 1.6 1.6 1.6
SWAPP
CJ –– 3.2 1.4 1.4 1.4
SCJ –– 3.2 1.4 1.4 1.4
JMP –– 3.2 1.4 1.4 1.4
GOEND –– 0.39 0.34 0.34 0.34
DI –– 0.95 0.41 0.41 0.41
EI –– 1.3 0.54 0.54 0.54
IMASK –– 11 4.6 4.6 4.6
IRET –– 1.6 0.68 0.68 0.68
RFS n=1 6.7 4.7 4.7 4.7
RFSP n = 96 19 13 13 13
UDCNT1 –– 15 6.5 6.5 ––

UDCNT2 –– 16 6.8 6.8 ––

TTMR –– 10 4.4 4.4 ––

STMR –– 20 7.1 7.1 ––

ROTC –– 26 11 11 ––

RAMP –– 18 7.7 7.7 ––

SPD –– 19 8.3 8.3 ––

PLSY –– 10 4.5 4.5 ––

PWM –– 9.1 3.9 3.9 ––

MTR –– 11 4.9 4.9 ––

App-36
 (3) Application instructions
The processing time when the instruction is not executed is calculated as follows:
Q02CPU ·······················································0.079 (No. of steps for each instruction + 1) µs
8
Q02HCPU, Q06HCPU, Q12HCPU, Q25HCPU, Q02PHCPU, Q06PHCPU, Q12PHCPU,
Q25PHCPU, Q12PRHCPU, Q25PRHCPU
······································································0.034 (No. of steps for each instruction + 1) µs 8
Processing Time ( µs)
Instruction Condition (Device)
Qn QnH QnPH QnPRH 8
WAND S D
When executed 0.39 0.17 0.17 0.17
WANDP S D
8
WAND S1 S2 D
When executed 0.47 0.20 0.20 0.20
WANDP S1 S2 D

DAND S D
A
When executed 0.71 0.31 0.31 0.31
DANDP S D

DAND S1 S2 D
When executed 0.79 0.34 0.34 0.34
6
DANDP S1 S2 D

BKAND S1 S2 D n n=1 36 16 16 16
7
BKANDP S1 S2 D n n = 96 74 32 32 32

WOR S D
When executed 0.40 0.17 0.17 0.17 8
WORP S D

WOR S1 S2 D
When executed 0.47 0.20 0.20 0.20
WORP S1 S2 D

Appendix 1.3 Operation Processing Time of High Performance Model QCPU/Process CPU/Redundant CPU
Appendix1 OPERATION PROCESSING TIME
DOR S D
When executed 0.71 0.31 0.31 0.31
DORP S D

DOR S1 S2 D
When executed 0.79 0.34 0.34 0.34
DORP S1 S2 D

BKOR S1 S2 D n n=1 36 16 16 16

BKORP S1 S2 D n n = 96 74 32 32 32

WXOR S D
When executed 0.39 0.17 0.17 0.17
WXORP S D

WXOR S1 S2 D
When executed 0.47 0.20 0.20 0.20
WXORP S1 S2 D

DXOR S D
When executed 0.71 0.31 0.31 0.31
DXORP S D

DXOR S1 S2 D
When executed 0.79 0.34 0.34 0.34
DXORP S1 S2 D

BKXOR S1 S2 D n n=1 36 16 16 16

BKXORP S1 S2 D n n = 96 74 32 32 32

App-37
 Processing Time (µs)
Instruction Condition (Device)
Qn QnH QnPH QnPRH

WXNR S D
When executed 0.40 0.17 0.17 0.17
WXNRP S D

WXNR S1 S2 D
When executed 0.47 0.20 0.20 0.20
WXNRP S1 S2 D

DNXR S D
When executed 0.71 0.31 0.31 0.31
DNXRP S D

DNXR S1 S2 D
When executed 0.79 0.34 0.34 0.34
DNXRP S1 S2 D

BKXNR S1 S2 D n n=1 36 16 16 16

BKXNRP S1 S2 D n n = 96 74 32 32 32

ROR D n n=1 2.0 0.85 0.85 0.85

RORP D n n = 15 2.0 0.85 0.85 0.85

RCR D n n=1 1.6 0.68 0.68 0.68

RCRP D n n = 15 1.6 0.68 0.68 0.68

ROL D n n=1 2.0 0.85 0.85 0.85

ROLP D n n = 15 2.0 0.85 0.85 0.85

RCL D n n=1 1.6 0.68 0.68 0.68

RCLP D n n = 15 1.6 0.68 0.68 0.68

DROR D n n=1 3.9 1.7 1.7 1.7

DRORP D n n = 31 4.0 1.7 1.7 1.7

DRCR D n n=1 4.3 1.8 1.8 1.8

DRCRP D n n = 31 4.3 1.9 1.9 1.9

DROL D n n=1 3.9 1.7 1.7 1.7

DROLP D n n = 31 4.0 1.7 1.7 1.7

DRCL D n n=1 4.3 1.8 1.8 1.8

DRCLP D n n = 31 4.3 1.9 1.9 1.9

SFR D n n=1 1.7 0.75 0.75 0.75

SFRP D n n = 15 2.0 0.85 0.85 0.85

SFL D n n=1 1.7 0.75 0.75 0.75

SFLP D n n = 15 2.0 0.85 0.85 0.85

BSFR D n n=1 20 8.6 8.6 8.6

BSFRP D n n = 96 24 10 10 10

BSFL D n n=1 20 8.5 8.5 8.5

BSFLP D n n = 96 23 10 10 10

DSFR D n n=1 1.3 0.58 0.58 0.58

DSFRP D n n = 96 25 11 11 11

DSFL D n n=1 1.3 0.58 0.58 0.58

DSFLP D n n = 96 26 11 11 11

App-38
 Processing Time (µs)
Instruction Condition (Device)
Qn QnH QnPH QnPRH 8
BSET D n n=1 7.6 3.3 3.3 3.3

BSETP D n n = 15 7.6 3.3 3.3 3.3

BRST D n n=1 7.6 3.3 3.3 3.3

8
BRSTP D n n = 15 7.6 3.3 3.3 3.3

TEST S1 S2 D 8
–– 8.2 3.5 3.5 3.5
TESTP S1 S2 D

DTEST S1 S2 D
–– 9.2 3.9 3.9 3.9 8
DTESTP S1 S2 D

BKRST S n n=1 18 7.8 7.8 7.8

BKRSTP S n n = 96 19 8.2 8.2 8.2 A

All match 22 9.6 9.6 9.6
n=1
SER S1 S2 D n None match 21 8.9 8.9 8.9

SERP S1 S2 D n
All match 115 49 49 49 6
n = 96
None match 133 57 57 57
All match 23 9.9 9.9 9.9
n=1
DSER S1 S2 D n None match 23 9.7 9.7 9.7 7
All match 142 61 61 61
DSERP S1 S2 D n n = 96
None match 132 57 57 57

SUM S =0
3.9 1.7 1.7 1.7
8
SUMP
S = FFFF

DSUM S =0 4.7 2.0 2.0 2.0

DSUMP 12 5.0 5.0 5.0
S = FFFFFFFFH

Appendix 1.3 Operation Processing Time of High Performance Model QCPU/Process CPU/Redundant CPU
Appendix1 OPERATION PROCESSING TIME
DECO S D n n=2 20 8.6 8.6 8.6

DECOP S D n n=8 27 12 12 12
M1 = ON 21 9.1 9.1 9.1
n=2
ENCO S D n M4 = ON 21 9.1 9.1 9.1
M1 = ON 28 12 12 12
ENCOP S D n n=8
M256 = ON 26 11 11 11
SEG
–– 1.3 0.54 0.54 0.54
SEGP

DIS S D n n=1 18 7.7 7.7 7.7

DISP S D n n=4 19 8.3 8.3 8.3

UNI S D n n=1 21 8.9 8.9 8.9

UNIP S D n n=4 23 9.7 9.7 9.7

NDIS S1 D S2
–– 41 18 18 18
NDISP S1 D S2

NUNI S1 D S2
–– 42 18 18 18
NUNIP S1 D S2

WTOB S D n n=1 47 20 20 20

WTOBP S D n n = 96 99 43 43 43

BTOW S D n n=1 45 19 19 19

BTOWP S D n n = 96 89 38 38 38

App-39
 Processing Time (µs)
Instruction Condition (Device)
Qn QnH QnPH QnPRH

MAX S D n n=1 17 7.1 7.1 7.1

MAXP S D n n = 96 136 59 59 59

MIN S D n n=1 17 7.1 7.1 7.1

MINP S D n n = 96 159 69 69 69

DMAX S D n n=1 27 12 12 12

DMAXP S D n n = 96 181 78 78 78

DMIN S D n n=1 27 12 12 12

DMINP S D n n = 96 112 48 48 48

n=1 16 7.1 7.1 7.1

SORT S1 n S2 D1 D2
n = 96 14 6.2 6.2 6.2
n=1 17 7.1 7.1 7.1
DSORT S1 n S2 D1 D2
n = 96 16 6.8 6.8 6.8

WSUM S D n n=1 16.4 7.1 7.1 7.1

WSUMP S D n n = 96 68.4 29.5 29.5 29.5

DWSUM S D n n=1 18.9 8.2 8.2 8.2

DWSUMP S D n n = 96 130.4 56.1 56.1 56.1

FOR n n=0 2.3 1.0 1.0 1.0

NEXT –– 3.3 1.4 1.4 1.4
BREAK
–– 11 4.6 4.6 4.6
BREAKP
CALL Pn Internal file pointer 2.1 0.88 0.88 0.88
CALLP Pn Common pointer 33 14 14 14

CALL Pn S1 to S5
–– 135 58 58 58
CALLP Pn S1 to S5
Return to original program 2.9 1.3 1.3 1.3
RET
Return to other program 20 8.5 8.5 8.5
FCALL Pn Internal file pointer 3.6 1.6 1.6 1.6
FCALLP Pn Common pointer 20 8.7 8.7 8.7

FCALL Pn S1 to S5
–– 134 57 57 57
FCALLP Pn S1 to S5
ECALL * Pn
ECALLP * Pn –– 77 33 33 33
*: Program name

ECALL * Pn S1 to S5
–– 162 70 70 70
ECALLP * Pn S1 to S5
*: Program name
EFCALL * Pn
EFCALLP * Pn –– 78 34 34 34
*: Program name

EFCALL * Pn S1 to S5
–– 200 86 86 86
EFCALLP * Pn S1 to S5
*: Program name

App-40
 Processing Time (µs)
Instruction Condition (Device)
Qn QnH QnPH QnPRH
8
COM –– 55 16 16 16
IX –– 12 5.2 5.2 5.2
IXEND –– 4.7 2.0 2.0 2.0
8
Number of contacts 1 48 21 21 21
IXDEV + IXSET
Number of contacts 14 93 40 40 40
FIFW Number of data points 0 11 4.5 4.5 4.5
8
FIFWP Number of data points 96 11 4.5 4.5 4.5
FIFR Number of data points 1 13 5.6 5.6 5.6
FIFRP Number of data points 96 32 14 14 14
FPOP Number of data points 1 16 7.0 7.0 7.0 8
FPOPP Number of data points 96 16 7.0 7.0 7.0
FINS Number of data points 0 20 8.4 8.4 8.4
FINSP Number of data points 96 36 15 15 15 A
FDEL Number of data points 1 19 7.5 7.5 7.5
FDELP Number of data points 96 39 15 15 15

n3 = 1
––
––
––
––
––
––
––
––
6
FROM n1 n2 D n3
47 22 22 22
FROMP n1 n2 D n3 –– –– –– ––
*1 n3 = 1000 –– –– –– –– 7
476 437 437 437
–– –– –– ––
n3 = 1 –– –– –– ––
DFRO n1 n2 D n3
51 24 24 24 8
DFROP n1 n2 D n3 –– –– –– ––
*1 n3 = 500 –– –– –– ––
478 437 437 437
–– –– –– ––

Appendix 1.3 Operation Processing Time of High Performance Model QCPU/Process CPU/Redundant CPU
Appendix1 OPERATION PROCESSING TIME
n3 = 1 –– –– –– ––
TO n1 n2 S n3
48 20 20 20
TOP n1 n2 S n3 –– –– –– ––
*1 n3 = 1000 –– –– –– ––
479 412 412 412
–– –– –– ––
n3 = 1 –– –– –– ––
DTO n1 n2 S n3
50 23 23 23
DTOP n1 n2 S n3 –– –– –– ––
*1 n3 = 500 –– –– –– ––
457 416 416 416
Variable 1 character 33 11 11 ––
SM701ON
PR Variable 32 character 48 18 18 ––
SM701OFF 21 7.8 7.8 ––
PRC –– 181 16 16 ––
When displayed –– –– –– ––
LED
Display completed –– –– –– ––

*1 : The upper row indicates the processing time when A38B/A1S38B and the extension base are used.
The center row indicates the processing time when A38HB/A1S38HB is used.
The bottom row indicates the processing times taken when the Q312B is used to execute the instruction for
the QJ71C24 in slot 0.
The FROM/TO instruction differs in processing time according to the number of slots and the loaded
modules.
(The QnCPU/QnHCPU also differs in processing time according to the extension base type.)

App-41
 Processing Time (µs)
Instruction Condition (Device)
Qn QnH QnPH QnPRH
When displayed –– –– –– ––
LEDC
Display completed –– –– –– ––

No display no display 0.40 0.17 0.17 0.17

LEDR
LED instruction execution no display 103 44 44 44
CHKST –– 5.8 2.5 2.5 2.5
1 contact no error 24 10 10 10
CHK 150 contact no error 1676 721 721 721
1 contact error 88 38 38 38
CHKCIR 10 steps 5.8 2.5 2.5 2.5
All internal devices –– –– –– ––

SLT File register 8k points –– –– –– ––

SLT execution completion –– –– –– ––

SLTR –– –– –– –– ––
Start –– –– –– ––
STRA
STRA execution completion –– –– –– ––
STRAR –– –– –– –– ––
PTRA –– –– –– –– ––
PTRAR –– –– –– –– ––

PTRAEXE When operating –– –– –– ––

PTRAEXEP Trace in progress –– –– –– ––

BINDA S =1 15 6.7 6.7 6.7

BINDAP 24 10 10 10
S = - 32768

DBINDA S =1 43 18 18 18
DBINDAP 86 37 37 37
S = - 2147483648

BINHA S =1 18 7.7 7.7 7.7

BINHAP 19 8.2 8.2 8.2
S = FFFFH

DBINHA S =1 23 10 10 10
DBINHAP 24 10 10 10
S = FFFFFFFFH

BCDDA S =1 23 9.8 9.8 9.8

BCDDAP 21 8.9 8.9 8.9
S = 9999

DBCDDA S =1 22 9.5 9.5 9.5

DBCDDAP 29 13 13 13
S = 99999999

DABIN S =1 57 25 25 25
DABINP 58 25 25 25
S = - 32768

DDABIN S =1 92 40 40 40
DDABINP 106 46 46 46
S = - 2147483648

HABIN S =1 13 5.8 5.8 5.8

HABINP 15 6.4 6.4 6.4
S = FFFFH

DHABIN S =1 22 9.5 9.5 9.5

DHABINP 25 11 11 11
S = FFFFFFFFH

App-42
 Processing Time (µs)
Instruction Condition (Device)
Qn QnH QnPH QnPRH 8
DABCD S =1 16 6.9 6.9 6.9
DABCDP 17 7.2 7.2 7.2
= 9999
8
S

DDABCD S =1 25 11 11 11
DDABCDP 29 13 13 13
S = 99999999
COMRD
–– 40 17 17 17
8
COMRDP
LEN 1 character 18 8.0 8.0 8.0
LENP 96 characters 86 37 37 37 8
STR
–– 53 23 23 23
STRP
DSTR
DSTRP
–– 123 53 53 53 A
VAL
–– 95 41 41 41
VALP
DVAL 6
–– 166 72 72 72
DVALP
ESTR
564 243 243 243
ESTRP
––
7
EVAL Decimal point format all 2-digit specification 100 43 43 43
EVALP Exponent format all 6-digit specification 127 55 55 55

ASC S D n n=1 64 28 28 28
8
ASCP S D n n = 96 289 125 125 125

HEX S D n n=1 60 26 26 26

Appendix 1.3 Operation Processing Time of High Performance Model QCPU/Process CPU/Redundant CPU
Appendix1 OPERATION PROCESSING TIME
HEXP S D n n = 96 343 148 148 148

RIGHT S D n n=1 49 21 21 21

RIGHTP S D n n = 96 131 56 56 56

LEFT S D n n=1 50 21 21 21

LEFTP S D n n = 96 131 56 56 56

MIDR
–– 53 23 23 23
MIDRP
MIDW
–– 128 55 55 55
MIDWP
No match 58 25 25 25
INSTR
Head 55 24 24 24
INSTRP Match
End 58 25 25 25

App-43
 Processing Time (µs)
Instruction Condition (Device)
Qn QnH QnPH QnPRH
EMOD
–– 527 227 227 227
EMODP
EREXP
–– 1656 713 713 713
EREXPP
SIN Single precision 115 50 50 50
SINP Double precision 1945 837 –– ––

COS Single precision 122 53 53 53

COSP Double precision 2618 1127 –– ––

TAN Single precision 123 53 53 53

TANP Double precision 2618 1127 –– ––

ASIN Single precision 111 48 48 48

ASINP Double precision 2491 1072 –– ––

ACOS Single precision 115 49 49 49

ACOSP Double precision 2367 1019 –– ––

ATAN Single precision 157 68 68 68

ATANP Double precision 3140 1352 –– ––

RAD Single precision 17 7.2 7.2 7.2

RADP Double precision 24 10 –– ––

DEG Single precision 17 7.2 7.2 7.2

DEGP Double precision 23 9.9 –– ––

SQR Single precision 28 12 12 12

SQRP Double precision 1812 780 –– ––

S = - 10
Single precision 129 56 56 56
EXP S =1
EXPP
S = - 10
Double precision 2386 1026 –– ––
S =1

S =1
Single precision 113 49 49 49
LOG S = 10
LOGP
S =1
Double precision 2146 924 –– ––
S = 10
RND
–– 3.9 1.7 1.7 1.7
RNDP
SRND
–– 3.5 1.5 1.5 1.5
SRNDP

App-44
 Processing Time (µs)
Instruction Condition (Device)
Qn QnH QnPH QnPRH 8
BSQR S =0 6.2 2.7 2.7 2.7
BSQRP 38 16 16 16
= 9999
8
S

BDSQR S =0 6.2 2.7 2.7 2.7

BDSQRP 38 16 16 16
S = 99999999
BSIN
–– 12 5.1 5.1 5.1
8
BSINP
BCOS
–– 12 5.2 5.2 5.2
BCOSP
8
BTAN
–– 12 5.2 5.2 5.2
BTANP
BASIN
BASINP
–– 20 8.7 8.7 8.7 A
BACOS
–– 21 9.0 9.0 9.0
BACOSP
BATAN
–– 22 9.6 9.6 9.6
6
BATANP
LIMIT
–– 10 4.3 4.3 4.3
LIMITP
7
DLIMIT
–– 11 4.7 4.7 4.7
DLIMITP
BAND
BANDP
–– 9.8 4.2 4.2 4.2 8
DBAND
–– 11 4.9 4.9 4.9
DBANDP
ZONE
–– 9.1 3.9 3.9 3.9
ZONEP

Appendix 1.3 Operation Processing Time of High Performance Model QCPU/Process CPU/Redundant CPU
Appendix1 OPERATION PROCESSING TIME
DZONE
–– 11 4.6 4.6 4.6
DZONEP
RSET
–– 6.8 2.9 2.9 2.9
RSETP
QDRSET
–– 205 88 88 88
QDRSETP
QCDSET
–– 147 63 63 63
QCDSETP
DATERD
–– 13 5.5 5.5 5.5
DATERDP
DATEWR
–– 15 6.4 6.4 6.4
DATEWRP

App-45
 Processing Time (µs)
Instruction Condition (Device)
Qn QnH QnPH QnPRH
DATE+ No digit increase 13 5.4 5.4 5.4
DATE+P Digit increase 13 5.4 5.4 5.4
DATE - No digit increase 12 5.2 5.2 5.2
DATE - P Digit increase 12 5.2 5.2 5.2
SECOND
–– 10 4.5 4.5 4.5
SECONDP
HOUR
–– 12 5.2 5.2 5.2
HOURP
1 character 3.0 1.3 1.3 1.3
MSG
32 characters 3.0 1.3 1.3 1.3
Initial time 20 8.6 8.6 8.6
PKEY
No reception 19 8.2 8.2 8.2
PSTOP
–– 79 34 34 34
PSTOPP
POFF
–– 79 34 34 34
POFFP
PSCAN
–– 75 32 32 32
PSCNAP
PLOW
–– 80 34 34 ––
PLOWP
WDT
–– 5.9 2.6 2.6 2.6
WDTP
DUTY –– 9.3 4.0 4.0 4.0
ZRRDB
–– 7.9 3.4 3.4 3.4
ZRRDBP
ZRWRB
–– 9.4 4.0 4.0 4.0
ZRWRBP
ADRSET
–– 4.9 2.1 2.1 2.1
ADRSETP
KEY –– 17 7.3 7.3 ––
ZPUSH
–– 11 4.7 4.7 4.7
ZPUSHP
ZPOP
–– 5.1 2.2 2.2 2.2
ZPOPP
EROMWR
–– –– –– –– ––
EROMWRP

App-46
 Processing Time (µs)
Instruction Condition (Device)
Qn QnH QnPH QnPRH 8
ZCOM –– 691 289 289 289
READ –– –– –– –– ––
SREAD –– –– –– –– ––
8
WRITE –– –– –– –– ––
SWRITE –– –– –– –– ––
SEND
RECV
––
––
––
––
––
––
––
––
––
––
8
REQ –– –– –– –– ––
ZNFR –– –– –– –– ––
ZNTO –– –– –– –– ––
8
MELSECNET/10 –– –– –– ––
ZNRD
MELSECNET (II) –– –– –– ––

MELSECNET/10 –– –– –– –– A
ZNWR
MELSECNET (II) –– –– –– ––
RFRP –– –– –– –– ––
RTOP –– –– –– –– –– 6

(4) Processing time for QCPU instructions (QCPU instructions only) 7

(a) Instructions available from function version A
Processing Time (µs)
Instruction Condition (Device)
Qn QnH QnPH QnPRH
8
UNIRD –– 79 34 34 34
Start 176 76 76 76
TRACE
STRA execution completion 6.3 2.7 2.7 2.7
19 8.2 8.2 8.2

Appendix 1.3 Operation Processing Time of High Performance Model QCPU/Process CPU/Redundant CPU
Appendix1 OPERATION PROCESSING TIME
TRACER ––

SP.FWRITE –– 84 36 36 36
SP.FREAD –– 82 35 35 35
PLOADP –– 58 25 25 ––

PUNLOADP –– 272 117 117 ––

PSWAPP –– 308 133 133 ––

1 point 45.5 20 20 20
When standard RAM is used
1000 points 215 91 91 91
RBMOV
1 point 49.5 22 22 22
When SRAM card is used
1000 points 540 305 305 305

App-47
 (b) Instructions available from function version B
Processing Time (µs)
Instruction Condition/Number of Points Processed
Qn QnH QnPH QnPRH
Refresh range: 2k words
(0.5k words 720 660 660 ––
With auto refresh of assigned equally to all CPUs)
CPU shared memory Refresh range: 4k words
COM *1
(1k words assigned equally to all 860 730 730 ––
CPUs)
Without auto refresh of
–– 43 20 20 20
CPU shared memory
Reading from CPU n3 = 1 59 29 29 ––
shared memory of
n3 = 1000 530 500 500 ––
another CPU
FROM *1 Main base unit 51 24 24 ––
Reading buffer memory n3 = 1
Extension base unit 54 27 27 ––
of intelligent function
Main base unit 540 480 480 ––
module*2 n3 = 1000
Extension base unit 1100 1050 1050 ––
n3 = 1 ("TO" instruction)
Writing to CPU shared 74 33 33 ––
S.TO n4 = 1 ("S.TO instruction")
memory of host CPU
n2 = 256 126 54 54 ––
Reading data of the
*3 –– 25 11 11 11
S (P).DATERD
expansion clock
Expansion clock data
*3 –– 38 17 17 17
S (P).DATE+
addition operation
Expansion clock data
*3 –– 38 17 17 17
S (P).DATE-
subtraction operation

*1 : If the processing overlaps those of the other CPUs in a multiple CPU system, the processing time
increases by a maximum of the following time.

For system having only the main base unit

(Instruction processing time increase) = 0.54 (number of points
processed) (number of other CPUs) (µs)
For system including extension base units
(Instruction processing time increase) = 1.30 (number of points
processed) (number of other CPUs) (µs)

*2 : In a multiple CPU system, the instruction processing time for the intelligent function module under control
of the host CPU is equal to that for the intelligent function module under control of another CPU.
*3 : Products with the first 5 digits of the serial No. "07032" or higher are applicable.
(5) Redundant system instructions (for redundant CPU)
Processing Time (µs)
Instruction Condition (Device)
Qn QnH QnPH QnPRH
SP.CONTSW –– –– –– –– 9.6

App-48
 (6) Table of the time to be added when file register, module access device or link direct device is
used
8
Device Specification Processing Time (µs)
Instruction data
Location Qn QnH QnPH QnPRH

Bit
Source
Destination
5.56
4.44
2.40
1.91
2.40
1.91
2.40
1.91
8
When standard Source 2.60 1.12 1.12 1.12
Word
RAM is used Destination 3.76 1.62 1.62 1.62

Double word
Source 2.83 1.22 1.22 1.22 8
Destination 4.00 1.72 1.72 1.72
File register (ZR)
Source 5.22 2.25 2.25 2.25
Bit
When SRAM Destination 4.09 1.76 1.76 1.76
card is used Source 2.25 0.97 0.97 0.97 8
Word
(Q2MEM-1MBS, Destination 3.42 1.47 1.47 1.47
Q2MEM-2MBS) Source 2.49 1.07 1.07 1.07
Double word
Destination 3.65 1.57 1.57 1.57 A
Source 35.56 15.31 15.31 15.31
Bit
Destination 65.08 28.01 28.01 28.01
Module access device Source 32.76 14.10 14.10 14.10
(Un\G , U3En\G0 to G4095)
Word
Destination 28.84 12.41 12.41 12.41 6
Source 32.99 14.20 14.20 14.20
Double word
Destination 29.07 12.51 12.51 12.51

Bit
Source 75.67 32.57 32.57 32.57 7
Destination 138.65 59.67 59.67 59.67
Source 72.73 31.30 31.30 31.30
Link direct device (Jn\ ) Word
Destination 137.32 59.10 59.10 59.10
Source 72.96 31.40 31.40 31.40 8
Double word
Destination 137.55 59.20 59.20 59.20

Appendix 1.3 Operation Processing Time of High Performance Model QCPU/Process CPU/Redundant CPU
Appendix1 OPERATION PROCESSING TIME

App-49
 Appendix 1.4 Operation Processing Time of Universal
Model QCPU

The processing time for the individual instructions are shown in the table on the following pages.
Operation processing times can vary substantially depending on the nature of the sources and
destinations of the instructions, and the values contained in the following tables should therefore
be taken as a set of general guidelines to processing time rather than as being strictly accurate.

Appendix 1.4.1 Subset instruction processing time

The following describes the subset instruction processing time.

1. The subset instruction processing time table shown in (1) applies when the device
used in an instruction satisfies either of the conditions (a) and (b).
2. Since the processing time of each instruction is not constant due to the cache
function in the Universal model QCPU, the minimum value and the maximum
value are described.
3. When using an F,T(ST),C device with an OUT/SET/RST instruction, add the
processing time for each instruction, with reference to the adding time in (3).
4. Since the processing time of each instruction is not constant due to the cache
function in the Universal model QCPU, the minimum value and the maximum
value are described.

(1) Subset instruction processing time table

(a) When using Q00UJCPU, Q00UCPU, Q01UCPU and Q02UCPU.
Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
Min. Max. Min. Max. Min. Max. Min. Max.
LD
LDI
AND
ANI
OR
ORI
When executed 0.120 0.080 0.060 0.040
LDP
LDF
ANDP
ANDF
ORP
Sequence ORF
instruction LDPI
When executed 0.360 0.240 0.180 0.120
LDFI
ANDPI
ANDFI
When executed 0.480 0.320 0.240 0.160
ORPI
ORFI
When not changed
OUT 0.120 0.080 0.060 0.040
When changed
When not executed
SET
When not changed 0.120 0.080 0.060 0.040
RST When executed
When changed

App-50
 Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
Min. Max. Min. Max. Min. Max. Min. Max.
8
In conductive status
LD= 0.360 0.240 0.180 0.120
In non-conductive status
When not executed 8
AND= In conductive status 0.360 0.240 0.180 0.120
When executed
In non-conductive status
When not executed 8
OR= In conductive status 0.360 0.240 0.180 0.120
When executed
In non-conductive status
In conductive status 8
LD<> 0.360 0.240 0.180 0.120
In non-conductive status
When not executed
AND<> In conductive status 0.360 0.240 0.180 0.120 A
When executed
In non-conductive status
When not executed
OR<> In conductive status 0.360 0.240 0.180 0.120 6
When executed
In non-conductive status
In conductive status
LD>
In non-conductive status
0.360 0.240 0.180 0.120
7
When not executed
AND> In conductive status 0.360 0.240 0.180 0.120
When executed
In non-conductive status 8
When not executed
OR> In conductive status 0.360 0.240 0.180 0.120
When executed
Basic In non-conductive status
instruction In conductive status

Appendix 1.4 Operation Processing Time of Universal Model QCPU

Appendix1 OPERATION PROCESSING TIME
LD<= 0.360 0.240 0.180 0.120
In non-conductive status
When not executed
AND<= In conductive status 0.360 0.240 0.180 0.120
When executed
In non-conductive status
When not executed
OR<= In conductive status 0.360 0.240 0.180 0.120
When executed
In non-conductive status
In conductive status
LD< 0.360 0.240 0.180 0.120
In non-conductive status
When not executed
AND< In conductive status 0.360 0.240 0.180 0.120
When executed
In non-conductive status
When not executed
OR< In conductive status 0.360 0.240 0.180 0.120
When executed
In non-conductive status
In conductive status
LD>= 0.360 0.240 0.180 0.120
In non-conductive status
When not executed
AND>= In conductive status 0.360 0.240 0.180 0.120
When executed
In non-conductive status
When not executed
OR>= In conductive status 0.360 0.240 0.180 0.120
When executed
In non-conductive status

App-51
 Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
Min. Max. Min. Max. Min. Max. Min. Max.
In conductive status
LDD= 0.360 0.240 0.180 0.120
In non-conductive status
When not executed
ANDD= In conductive status 0.360 0.240 0.180 0.120
When executed
In non-conductive status
When not executed
ORD= In conductive status 0.360 0.240 0.180 0.120
When executed
In non-conductive status
In conductive status
LDD<> 0.360 0.240 0.180 0.120
In non-conductive status
When not executed
ANDD<> In conductive status 0.360 0.240 0.180 0.120
When executed
In non-conductive status
When not executed
ORD<> In conductive status 0.360 0.240 0.180 0.120
When executed
In non-conductive status
In conductive status
LDD> 0.360 0.240 0.180 0.120
In non-conductive status
When not executed
ANDD> In conductive status 0.360 0.240 0.180 0.120
When executed
In non-conductive status
When not executed
ORD> In conductive status 0.360 0.240 0.180 0.120
When executed
Basic In non-conductive status
instruction In conductive status
LDD<= 0.360 0.240 0.180 0.120
In non-conductive status
When not executed
ANDD<= In conductive status 0.360 0.240 0.180 0.120
When executed
In non-conductive status
When not executed
ORD<= In conductive status 0.360 0.240 0.180 0.120
When executed
In non-conductive status
In conductive status
LDD< 0.360 0.240 0.180 0.120
In non-conductive status
When not executed
ANDD< In conductive status 0.360 0.240 0.180 0.120
When executed
In non-conductive status
When not executed
ORD< In conductive status 0.360 0.240 0.180 0.120
When executed
In non-conductive status
In conductive status
LDD>= 0.360 0.240 0.180 0.120
In non-conductive status
When not executed
ANDD>= In conductive status 0.360 0.240 0.180 0.120
When executed
In non-conductive status
When not executed
ORD>= In conductive status 0.360 0.240 0.180 0.120
When executed
In non-conductive status

App-52
 Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
Min. Max. Min. Max. Min. Max. Min. Max.
8
+ S D When executed 0.360 0.240 0.180 0.120

+ S1 S2 D When executed 0.480 0.320 0.240 0.160 8

- S D When executed 0.360 0.240 0.180 0.120

- S1 S2 D When executed 0.480 0.320 0.240 0.160

8
D+ S D When executed 0.360 0.240 0.180 0.120

D + S1 S2 When executed 0.480 0.320 0.240 0.160

8
D

D- S D When executed 0.360 0.240 0.180 0.120

D - S1 S2 D When executed 0.480 0.320 0.240 0.160

* S1 S2 D When executed 0.420 0.300 0.240 0.180

A
/ S1 S2 D When executed 0.520 0.400 0.340 0.280

D * S1 S2 D When executed 0.500 0.380 0.320 0.260 6

D/ S1 S2 D When executed 0.640 0.520 0.460 0.400

B+ S D When executed 3.100 12.300 3.100 12.300 3.100 12.300 3.300 8.300 7
B + S1 S2 D When executed 5.900 13.500 5.900 13.500 5.900 13.500 4.600 6.200

B- S D When executed 3.150 12.300 3.150 12.300 3.150 12.300 3.300 9.000
8
B - S1 S2 D When executed 5.950 13.600 5.950 13.600 5.950 13.600 4.600 8.200

B * S1 S2 D When executed 3.700 12.100 3.700 12.100 3.700 12.100 4.000 8.200
Basic
B/ S1 S2 D When executed 4.000 14.000 4.000 14.000 4.000 14.000 4.200 12.400
instruction

Appendix 1.4 Operation Processing Time of Universal Model QCPU

Appendix1 OPERATION PROCESSING TIME
Single S = 0, D =0 0.420 0.300 0.240 0.180
E+ S D
precision
S = 2127, D = 2127 0.420 0.300 0.240 0.180

Single S1 = 0, S2 =0 0.540 0.380 0.300 0.220

E + S1 S2 D
precision
S1 = 2127, S2 = 2127 0.540 0.380 0.300 0.220

Single S = 0, D =0 0.420 0.300 0.240 0.180

E- S D
precision
S = 2127, D = 2127 0.420 0.300 0.240 0.180

Single S1 = 0, S2 =0 0.540 0.380 0.300 0.220

E - S1 S2 D
precision
S1 = 2127, S2 = 2127 0.540 0.380 0.300 0.220

Single S1 = 0, S2 =0 0.420 0.300 0.240 0.180

E * S1 S2 D
precision
S1 = 2127, S2 = 2127 0.420 0.300 0.240 0.180

Single
E/ S1 S2 D
precision S1 = 2127, S2 = 2127 4.900 18.900 4.900 18.900 4.900 18.900 5.100 14.100

INC When executed 0.240 0.160 0.120 0.080

DINC When executed 0.240 0.160 0.120 0.080
DEC When executed 0.240 0.160 0.120 0.080
DDEC When executed 0.240 0.160 0.120 0.080
BCD When executed 0.320 0.240 0.200 0.160
DBCD When executed 0.400 0.320 0.280 0.240
BIN When executed 0.260 0.180 0.140 0.100
DBIN When executed 0.260 0.180 0.140 0.100

App-53
 Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
Min. Max. Min. Max. Min. Max. Min. Max.

Single S =0 0.300 0.220 0.180 0.140

FLT
precision 0.300 0.220 0.180 0.140
S = 7FFFH
Single S =0 0.300 0.220 0.180 0.140
DFLT
precision 0.300 0.220 0.180 0.140
S = 7FFFFFFFH
Single S =0 0.300 0.220 0.180 0.140
INT
precision 0.300 0.220 0.180 0.140
S = 32766.5
Single S =0 0.300 0.220 0.180 0.140
DINT
precision 0.300 0.220 0.180 0.140
S = 1234567890.3
MOV –– 0.240 0.160 0.120 0.080
DMOV –– 0.240 0.160 0.120 0.080
EMOV –– 0.240 0.160 0.120 0.080
CML –– 0.240 0.160 0.120 0.080
Basic DCML –– 0.240 0.160 0.120 0.080
instruction SM237= n=1 4.200 4.600 4.200 4.600 4.200 4.600 4.100 4.500
ON n=96 4.850 5.150 4.850 5.150 4.850 5.150 4.700 5.100
BMOV
SM237= n=1 6.800 11.300 6.800 11.300 6.800 11.300 6.300 8.900
OFF n=96 7.450 11.900 7.450 11.900 7.450 11.900 5.900 9.500
SM=237 n=1 4.100 4.600 4.100 4.600 4.100 4.600 4.100 4.600
=ON n=96 4.800 5.200 4.800 5.200 4.800 5.200 4.800 5.200
FMOV
SM237= n=1 4.600 8.250 4.600 8.250 4.600 8.250 4.600 7.900
OFF n=96 6.150 10.600 6.150 10.600 6.150 10.600 5.300 8.500
XCH –– 2.250 8.100 2.250 8.100 2.250 8.100 2.500 6.000
DXCH –– 2.400 8.200 2.400 8.200 2.400 8.200 2.800 7.900
SM237= n=1 2.700 2.800 2.700 2.800 2.700 2.800 2.350 2.450
ON n=96 6.500 6.800 6.500 6.800 6.500 6.800 5.950 6.000
DFMOV
SM237= n=1 4.000 8.150 4.000 8.150 4.000 8.150 3.000 6.950
OFF n=96 8.000 12.200 8.000 12.200 8.000 12.200 6.600 10.600
CJ –– 3.500 10.100 3.500 10.100 3.500 10.100 1.900 10.100
SCJ –– 3.500 10.100 3.500 10.100 3.500 10.100 1.900 10.100
JMP –– 3.500 10.100 3.500 10.100 3.500 10.100 1.900 10.100

WAND S D When executed 0.360 0.240 0.180 0.120

WAND S1 S2 D When executed 0.480 0.320 0.240 0.160

DAND S D When executed 0.360 0.240 0.180 0.120

DAND S1 S2 D When executed 0.480 0.320 0.240 0.160

WOR S D When executed 0.360 0.240 0.180 0.120

WOR S1 S2 D When executed 0.480 0.320 0.240 0.160

DOR S D When executed 0.360 0.240 0.180 0.120

Application DOR S1 S2 D When executed 0.480 0.320 0.240 0.160

instruction When executed 0.360 0.240 0.180 0.120
WXOR S D

WXOR S1 S2 D When executed 0.480 0.320 0.240 0.160

DXOR S D When executed 0.360 0.240 0.180 0.120

DXOR S1 S2 D When executed 0.480 0.320 0.240 0.160

WXNR S D When executed 0.360 0.240 0.180 0.120

WXNR S1 S2 D When executed 0.480 0.320 0.240 0.160

DXNR S D When executed 0.360 0.240 0.180 0.120

DXNR S1 S2 D When executed 0.480 0.320 0.240 0.160

App-54
 Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
Min. Max. Min. Max. Min. Max. Min. Max.
8
n=1 2.250 10.800 2.250 10.800 2.250 10.800 2.300 7.800
ROR D n
n = 15 2.250 10.800 2.350 10.800 2.350 10.800 2.400 7.800
n=1 2.250 10.800 2.250 10.800 2.250 10.800 2.300 3.900
8
RCR D n
n = 15 2.250 10.800 2.250 10.800 2.250 10.800 2.400 4.100
n=1 2.250 10.800 2.350 10.800 2.350 10.800 2.500 4.600
ROL D n
n = 15 2.250 10.800 2.350 10.800 2.350 10.800 2.400 4.600 8
n=1 2.250 11.500 2.300 11.500 2.300 11.500 2.400 7.500
RCL D n
n = 15 2.250 11.500 2.300 11.500 2.300 11.500 2.500 7.500
n=1 2.350 11.500 2.350 11.500 2.350 11.500 2.400 10.300 8
DROR D n
n = 31 2.350 11.500 2.350 11.500 2.350 11.500 2.500 10.300
n=1 2.350 13.300 2.350 13.300 2.350 13.300 2.500 12.700
DRCR D n
n = 31 2.350 14.900 2.350 14.900 2.350 14.900 2.500 12.700 A
n=1 2.350 10.800 2.350 10.800 2.350 10.800 2.500 11.800
DROL D n
n = 31 2.350 10.800 2.350 10.800 2.350 10.800 2.500 11.800
n=1 2.350 13.300 2.350 13.300 2.350 13.300 2.500 5.100 6
DRCL D n
Application n = 31 2.350 13.300 2.350 13.300 2.350 13.300 2.500 5.100
instruction n=1 2.350 9.900 2.350 9.900 2.350 9.900 2.400 6.100
SFR D n
n = 15 2.350 9.900 2.350 9.900 2.350 9.900 2.300 5.700 7
n=1 2.350 9.850 2.350 9.850 2.350 9.850 2.400 4.300
SFL D n
n = 15 2.350 9.850 2.350 9.850 2.350 9.850 2.400 4.300
n=1 3.250 15.500 3.250 15.500 3.250 15.500 3.300 12.000 8
DSFR D n
n = 96 32.600 45.000 32.600 45.000 32.600 45.000 32.600 42.200
n=1 3.200 15.500 3.200 15.500 3.200 15.500 3.300 8.200
DSFL D n
n = 96 32.600 45.100 32.600 45.100 32.600 45.100 32.600 37.700

3.100 8.950 3.100 8.950 3.100 8.950 3.400 6.700

Appendix 1.4 Operation Processing Time of Universal Model QCPU

Appendix1 OPERATION PROCESSING TIME
S =0
SUM
S = FFFFH 3.000 8.850 3.000 8.850 3.000 8.850 3.500 6.700

SEG When executed 2.100 7.700 2.100 7.700 2.100 7.700 2.100 5.900
FOR –– 1.500 7.500 1.500 7.500 1.500 7.500 1.200 6.300
Internal file pointer 4.800 5.400 4.800 5.400 4.800 5.400 2.700 4.800
CALL Pn
Common pointer 7.100 30.500 7.100 30.500 7.100 30.500 4.400 5.700

CALL Pn S1 to S5 –– 50.200 62.000 50.200 62.000 50.200 62.000 28.700 42.600

Remark
For the instructions for which a leading edge instruction ( P) is not described,
the processing time is the same as an ON execution instruction.
Example MOVP instruction, WANDP instruction etc.

App-55
 (b) When using Q03UD(E)HCPU, Q04UD(E)HCPU, Q06UD(E)HCPU,
Q10UD(E)HCPU,Q13UD(E)HCPU, Q20UD(E)HCPU, Q26UD(E)HCPU
Processing Time (µs)
Q10/Q13/Q20/
Category Instruction Condition (Device) Q03UD(E)CPU Q04/Q06UD(E)HCPU
Q26UD(E)HCPU
Min. Max. Min. Max. Min. Max.
LD
LDI
AND
ANI
OR
ORI
When executed 0.020 0.0095 0.0095
LDP
LDF
ANDP
ANDF
Sequence ORP
instruction ORF
LDPI
When executed 0.060 0.0285 0.0285
LDFI
ANDPI
ANDFI
When executed 0.080 0.038 0.038
ORPI
ORFI
When not changed
OUT 0.020 0.0095 0.0095
When changed
SET
When not executed 0.020 0.0095 0.0095
RST

App-56
 Processing Time (µs)
Q04/ Q10/Q13/Q20/
Category Instruction Condition (Device) Q03UD(E)CPU
Q06UD(E)HCPU Q26UD(E)HCPU 8
Min. Max. Min. Max. Min. Max.
In conductive status
LD=
In non-conductive status
0.060 0.0285 0.0285
8
When not executed
AND= In conductive status 0.060 0.0285 0.0285
When executed
In non-conductive status 8
When not executed
OR= In conductive status 0.060 0.0285 0.0285
When executed
In non-conductive status 8
In conductive status
LD<> 0.060 0.0285 0.0285
In non-conductive status
When not executed A
AND<> In conductive status 0.060 0.0285 0.0285
When executed
In non-conductive status
When not executed 6
OR<> In conductive status 0.060 0.0285 0.0285
When executed
In non-conductive status

LD>
In conductive status
0.060 0.0285 0.0285
7
In non-conductive status
When not executed
AND>
When executed
In conductive status 0.060 0.0285 0.0285 8
In non-conductive status
When not executed
OR> In conductive status 0.060 0.0285 0.0285
When executed
Basic In non-conductive status

Appendix 1.4 Operation Processing Time of Universal Model QCPU

Appendix1 OPERATION PROCESSING TIME
instruction In conductive status
LD<= 0.060 0.0285 0.0285
In non-conductive status
When not executed
AND<= In conductive status 0.060 0.0285 0.0285
When executed
In non-conductive status
When not executed
OR<= In conductive status 0.060 0.0285 0.0285
When executed
In non-conductive status
In conductive status
LD< 0.060 0.0285 0.0285
In non-conductive status
When not executed
AND< In conductive status 0.060 0.0285 0.0285
When executed
In non-conductive status
When not executed
OR< In conductive status 0.060 0.0285 0.0285
When executed
In non-conductive status
In conductive status
LD>= 0.060 0.0285 0.0285
In non-conductive status
When not executed
AND>= In conductive status 0.060 0.0285 0.0285
When executed
In non-conductive status
When not executed
OR>= In conductive status 0.060 0.0285 0.0285
When executed
In non-conductive status

App-57
 Processing Time (µs)
Q04/ Q10/Q13/Q20/
Category Instruction Condition (Device) Q03UD(E)CPU
Q06UD(E)HCPU Q26UD(E)HCPU
Min. Max. Min. Max. Min. Max.
In conductive status
LDD= 0.060 0.0285 0.0285
In non-conductive status
When not executed
ANDD= In conductive status 0.060 0.0285 0.0285
When executed
In non-conductive status
When not executed
ORD= In conductive status 0.060 0.0285 0.0285
When executed
In non-conductive status
In conductive status
LDD<> 0.060 0.0285 0.0285
In non-conductive status
When not executed
ANDD<> In conductive status 0.060 0.0285 0.0285
When executed
In non-conductive status
When not executed
ORD<> In conductive status 0.060 0.0285 0.0285
When executed
In non-conductive status
In conductive status
LDD> 0.060 0.0285 0.0285
In non-conductive status
When not executed
ANDD> In conductive status 0.060 0.0285 0.0285
When executed
In non-conductive status
When not executed
ORD> In conductive status 0.060 0.0285 0.0285
When executed
Basic In non-conductive status
instruction In conductive status
LDD<= 0.060 0.0285 0.0285
In non-conductive status
When not executed
ANDD<= In conductive status 0.060 0.0285 0.0285
When executed
In non-conductive status
When not executed
ORD<= In conductive status 0.060 0.0285 0.0285
When executed
In non-conductive status
In conductive status
LDD< 0.060 0.0285 0.0285
In non-conductive status
When not executed
ANDD< In conductive status 0.060 0.0285 0.0285
When executed
In non-conductive status
When not executed
ORD< In conductive status 0.060 0.0285 0.0285
When executed
In non-conductive status
In conductive status
LDD>= 0.060 0.0285 0.0285
In non-conductive status
When not executed
ANDD>= In conductive status 0.060 0.0285 0.0285
When executed
In non-conductive status
When not executed
ORD>= In conductive status 0.060 0.0285 0.0285
When executed
In non-conductive status

App-58
 Processing Time (µs)
Q10/Q13/Q20/
Category Instruction Condition (Device) Q03UD(E)CPU Q04/Q06UD(E)HCPU
Q26UD(E)HCPU 8
Min. Max. Min. Max. Min. Max.

+ S D When executed 0.060 0.0285 0.0285

+ S1 S2 D When executed 0.080 0.038 0.038

8
- S D When executed 0.060 0.0285 0.0285

- S1 S2 D When executed 0.080 0.038 0.038 8

D+ S D When executed 0.060 0.0285 0.0285

D + S1 S2 D When executed 0.080 0.038 0.038

8
D- S D When executed 0.060 0.0285 0.0285

D - S1 S2 D When executed 0.080 0.038 0.038

When executed 0.120 0.057 0.057

A
* S1 S2 D

/ S1 S2 D When executed 0.220 0.110 0.110

D * S1 S2 D When executed 0.200 0.095 0.095 6

D/ S1 S2 D When executed 0.340 0.170 0.170

B+ S D When executed 3.300 5.500 3.000 4.100 3.000 4.100

7
B+ S1 S2 D When executed 4.600 6.200 4.200 5.900 4.200 5.900

B- S D When executed 3.300 4.400 2.900 3.800 2.900 3.800

When executed 4.600 6.300 4.200 4.600 4.200 4.600

8
B - S1 S2 D

B * S1 S2 D When executed 4.000 4.800 3.400 4.800 3.400 4.800

Basic
B/ S1 S2 D When executed 4.200 5.700 3.700 5.200 3.700 5.200
instruction

Appendix 1.4 Operation Processing Time of Universal Model QCPU

Appendix1 OPERATION PROCESSING TIME
Single S = 0, D =0 0.120 0.057 0.057
E+ S D
precision
S = 2127, D = 2127 0.120 0.057 0.057

Single S1 = 0, S2 =0 0.140 0.0665 0.0665

E + S1 S2 D
precision
S1 = 2127, S2 = 2127 0.140 0.0665 0.0665

Single S = 0, D =0 0.120 0.057 0.057

E- S D
precision
S = 2127, D = 2127 0.120 0.057 0.057

Single S1 = 0, S2 =0 0.140 0.0665 0.0665

E - S1 S2 D
precision
S1 = 2127, S2 = 2127 0.140 0.0665 0.0665

Single S1 = 0, S2 =0 0.120 0.057 0.057

E * S1 S2 D
precision
S1 = 2127, S2 = 2127 0.120 0.057 0.057
Single
E/ S1 S2 D
precision S1 = 2127, S2 = 2127 4.500 5.600 3.900 4.900 0.285

INC When executed 0.040 0.019 0.019

DINC When executed 0.040 0.019 0.019
DEC When executed 0.040 0.019 0.019
DDEC When executed 0.040 0.019 0.019
BCD When executed 0.120 0.057 0.057
DBCD When executed 0.200 0.095 0.095
BIN When executed 0.060 0.0285 0.0285
DBIN When executed 0.060 0.0285 0.0285

App-59
 Processing Time (µs)
Q10/Q13/Q20/
Category Instruction Condition (Device) Q03UD(E)CPU Q04/Q06UD(E)HCPU
Q26UD(E)HCPU
Min. Max. Min. Max. Min. Max.

Single S =0 0.100 0.0475 0.0475

FLT
precision 0.100 0.0475 0.0475
S = 7FFFH
Single S =0 0.100 0.0475 0.0475
DFLT
precision 0.100 0.0475 0.0475
S = 7FFFFFFFH
Single S =0 0.100 0.0475 0.0475
INT
precision 0.100 0.0475 0.0475
S = 32766.5
Single S =0 0.100 0.0475 0.0475
DINT
precision 0.100 0.0475 0.0475
S = 1234567890.3
MOV –– 0.040 0.019 0.019
DMOV –– 0.040 0.019 0.019
EMOV –– 0.040 0.019 0.019
CML –– 0.040 0.019 0.019
DCML –– 0.040 0.019 0.019
6.300 8.200 5.400 7.000 5.400 7.000
*1 8.200 10.600 3.900 5.100 3.900 5.100
SM237=OFF
Basic n=1
*1 6.000 7.800 2.900 3.700 2.900 3.700
SM237=ON
instruction BMOV
7.100 8.800 5.900 7.600 5.900 7.600
SM237=OFF*1 9.300 11.900 4.400 5.700 4.400 5.700
n = 96
*1 7.100 9.100 3.400 4.300 3.400 4.300
SM237=ON
5.300 5.900 4.200 4.800 4.200 4.800
*1 7.000 8.000 3.400 3.800 3.400 3.800
SM237=OFF
n=1
*1 5.900 6.800 2.800 3.200 2.800 3.200
SM237=ON
FMOV
5.300 7.600 4.400 6.800 4.400 6.800
*1 7.400 12.200 3.600 5.800 3.600 5.800
SM237=OFF
n = 96
*1 6.300 11.000 3.000 5.200 3.000 5.200
SM237=ON
XCH –– 2.500 2.900 1.800 2.300 1.800 2.300
DXCH –– 2.800 3.700 2.100 2.900 2.100 2.900
SM237=OFF 2.600 3.750 2.250 3.150 2.250 3.150
n=1
SM237=ON 2.050 2.250 1.750 1.750 1.750 1.750
DFMOV*2
SM237=OFF 5.850 7.350 4.200 5.500 4.200 5.500
n=96
SM237=ON 5.300 6.000 3.650 4.150 3.650 4.150
CJ –– 1.800 2.800 1.400 2.400 1.400 2.400
SCJ –– 1.800 2.800 1.400 2.400 1.400 2.400
JMP –– 1.800 2.800 1.100 2.400 1.100 2.400
*1 : Can be used onliy for the Q03UDCPU, Q04UDHCPU and Q06UDHCPU whose first 5 digits of serial
number is “10012” or later.
*2 : Can be used onliy for the Q03UD(E)CPU, Q04UD(E)HCPU, Q06UD(E)HCPU, Q13UD(E)HCPU and
Q26UD(E)HCPU whose first 5 digits of serial number is “10012” or later.

App-60
 Processing Time (µs)
Q10/Q13/Q20/
Category Instruction Condition (Device) Q03UD(E)CPU Q04/Q06UD(E)HCPU
Q26UD(E)HCPU 8
Min. Max. Min. Max. Min. Max.

When executed 0.060 0.0285 0.0285

WAND S
8
D

WAND S1 S2 D When executed 0.080 0.038 0.038

DAND S D When executed 0.060 0.0285 0.0285

When executed 0.080 0.038 0.038

8
DAND S1 S2 D

WOR S D When executed 0.060 0.0285 0.0285

WOR S1 S2 D When executed 0.080 0.038 0.038 8

DOR S D When executed 0.060 0.0285 0.0285

Application DOR S1 S2 D When executed 0.080 0.038 0.038 A

instruction
WXOR S D When executed 0.060 0.0285 0.0285

WXOR S1 S2 D When executed 0.080 0.038 0.038

6
DXOR S D When executed 0.060 0.0285 0.0285

When executed 0.080 0.038 0.038

DXOR S1 S2
7
D

WXNR S D When executed 0.060 0.0285 0.0285

WXNR S1 S2 D When executed 0.080 0.038 0.038

When executed 0.060 0.0285 0.0285

8
DXNR S D

DXNR S1 S2 D When executed 0.080 0.038 0.038

Appendix 1.4 Operation Processing Time of Universal Model QCPU

Appendix1 OPERATION PROCESSING TIME

App-61
 Processing Time (µs)
Q10/Q13/Q20/
Category Instruction Condition (Device) Q03UD(E)CPU Q04/Q06UD(E)HCPU
Q26UD(E)HCPU
Min. Max. Min. Max. Min. Max.
n=1 2.300 3.100 1.700 2.500 1.700 2.500
ROR D n
n = 15 2.400 3.100 1.800 2.500 1.800 2.500
n=1 2.300 3.900 1.700 3.200 1.700 3.200
RCR D n
n = 15 2.400 4.100 1.700 3.200 1.700 3.200
n=1 2.400 3.300 1.800 3.200 1.800 3.200
ROL D n
n = 15 2.400 3.300 1.800 3.200 1.800 3.200
n=1 2.400 2.700 1.800 2.100 1.800 2.100
RCL D n
n = 15 2.400 2.800 1.800 2.200 1.800 2.200
n=1 2.400 3.400 1.900 2.700 1.900 2.700
DROR D n
n = 31 2.500 3.400 1.900 2.700 1.900 2.700
n=1 2.500 4.800 1.900 4.200 1.900 4.200
DRCR D n
n = 31 2.500 4.900 1.900 4.200 1.900 4.200
n=1 2.500 3.900 1.800 3.200 1.800 3.200
DROL D n
n = 31 2.500 3.900 1.800 3.300 1.800 3.300
n=1 2.500 4.800 1.900 3.800 1.900 3.800
DRCL D n
Application n = 31 2.500 4.600 1.900 3.800 1.900 3.800
instruction n=1 2.400 3.900 1.700 2.600 1.700 2.600
SFR D n
n = 15 2.300 3.900 1.800 2.600 1.800 2.600
n=1 2.400 4.300 1.800 2.700 1.800 2.700
SFL D n
n = 15 2.400 4.300 1.800 2.700 1.800 2.700
n=1 2.700 4.800 2.200 4.300 2.200 4.300
DSFR D n
n = 96 32.600 35.900 23.900 26.100 23.900 26.100
n=1 2.700 4.600 2.100 4.000 2.100 4.000
DSFL D n
n = 96 32.600 35.300 23.700 25.800 23.700 25.800

S =0 3.400 4.300 2.900 3.600 2.900 3.600

SUM
S = FFFFH 3.500 4.200 2.900 3.600 2.900 3.600

SEG When executed 2.100 2.800 1.500 2.100 1.500 2.100

FOR –– 1.200 2.400 0.870 2.100 0.870 2.100
Internal file pointer 2.600 4.000 2.300 3.600 2.300 3.600
CALL Pn
Common pointer 4.000 5.300 3.200 4.900 3.200 4.900

CALL Pn S1 to S5 –– 28.700 33.400 26.100 29.300 26.100 29.300

Remark
For the instructions for which a leading edge instruction ( P) is not described,
the processing time is the same as an ON execution instruction.
Example MOVP instruction, WANDP instruction etc.

App-62
 (2) Table of the time to be added when file register, module access device is used
(a) When using Q00UJCPU, Q00UCPU, Q01UCPU and Q02UCPU 8
Device Specification Processing Time (µs)
Device name data
Location Q00UJCPU Q00UCPU Q01UCPU Q02UCPU

Bit
Source 0.100 0.100 0.100 0.100 8
Destination 0.220 0.220 0.220 0.220
When standard Source 0.100 0.100 0.100 0.100
Word
RAM is used Destination 0.100 0.100 0.100 0.100
Source 0.200 0.200 0.200 0.200 8
Double word
Destination 0.200 0.200 0.200 0.200
Source –– –– –– 0.220
Bit
When SRAM Destination –– –– –– 0.420 8
File register card is used Source –– –– –– 0.220
Word
(R) (Q2MEM-1MBS, Destination –– –– –– 0.180
Q2MEM-2MBS) Source –– –– –– 0.440
Double word
Destination –– –– –– 0.380 A
Source –– –– –– 0.160
Bit
When SRAM Destination –– –– –– 0.320
card is used
Word
Source –– –– –– 0.160 6
(Q3MEM-4MBS, Destination –– –– –– 0.140
Q3MEM-8MBS) Source –– –– –– 0.320
Double word
0.300
Destination
Source
––
0.220
––
0.180
––
0.160 0.140
7
Bit
Destination 0.280 0.320 0.300 0.280
When standard Source 0.220 0.180 0.160 0.140
RAM is used
Word
Destination 0.220 0.180 0.160 0.140 8
Source 0.320 0.280 0.260 0.240
Double word
Destination 0.320 0.280 0.260 0.240
File register
Source –– –– –– 0.260
(ZR)/ Bit
When SRAM Destination –– –– –– 0.480
Extended
0.260

Appendix 1.4 Operation Processing Time of Universal Model QCPU

Appendix1 OPERATION PROCESSING TIME
card is used Source –– –– ––
data register Word
(Q2MEM-1MBS, Destination –– –– –– 0.220
(D)/Extended Q2MEM-2MBS) Source –– –– –– 0.480
link register Double word
Destination –– –– –– 0.420
(W))
Source –– –– –– 0.200
Bit
When SRAM Destination –– –– –– 0.380
card is used Source –– –– –– 0.200
Word
(Q3MEM-4MBS, Destination –– –– –– 0.180
Q3MEM-8MBS) Source –– –– –– 0.360
Double word
Destination –– –– –– 0.340
Source –– –– –– ––
Bit
Module access device Destination –– –– –– ––
(Multiple CPU high speed trans- Source –– –– –– ––
Word
mission area) Destination –– –– –– ––
(U3En\G10000) Source –– –– –– ––
Double word
Destination –– –– –– ––

App-63
 (b) When using Q03UD(E)CPU, Q04UD(E)HCPU, Q06UD(E)HCPU, Q10UD(E)HCPU,
Q13UDE(H)CPU,Q20UD(E)HCPU and Q26UD(E)HCPU
Processing Time (µs)
Device Specification
Device name data Q10/Q13/Q20/
Location Q03UD(E)CPU Q04/Q06UD(E)HCPU
Q26UD(E)HCPU
Source 0.100 0.048 0.048
Bit
Destination 0.100 0.038 0.038
When standard Source 0.100 0.048 0.048
Word
RAM is used Destination 0.100 0.038 0.038
Source 0.200 0.095 0.095
Double word
Destination 0.200 0.086 0.086
Source 0.220 0.200 0.200
Bit
When SRAM
Destination 0.180 0.162 0.162
File register card is used Source 0.220 0.200 0.200
Word
(R) (Q2MEM-1MBS, Destination 0.180 0.162 0.162
Q2MEM-2MBS) Source 0.440 0.399 0.399
Double word
Destination 0.380 0.361 0.361
Source 0.160 0.152 0.152
Bit
When SRAM
Destination 0.140 0.133 0.133
card is used Source 0.160 0.152 0.152
Word
(Q3MEM-4MBS, Destination 0.140 0.133 0.133
Q3MEM-8MBS) Source 0.320 0.304 0.304
Double word
Destination 0.300 0.295 0.295
Source 0.120 0.057 0.057
Bit
Destination 0.120 0.048 0.048
When standard Source 0.120 0.057 0.057
Word
RAM is used Destination 0.120 0.048 0.048
Source 0.220 0.105 0.105
Double word
Destination 0.220 0.095 0.095
File register
Source 0.240 0.209 0.209
(ZR)/ Bit
When SRAM
Destination 0.200 0.171 0.171
Extended
card is used Source 0.240 0.209 0.209
data register Word
(Q2MEM-1MBS, Destination 0.200 0.171 0.171
(D)/Extended Q2MEM-2MBS) Source 0.460 0.409 0.409
link register Double word
Destination 0.400 0.371 0.371
(W))
Source 0.180 0.162 0.162
Bit
When SRAM Destination 0.160 0.143 0.143
card is used Source 0.180 0.162 0.162
Word
(Q3MEM-4MBS, Destination 0.160 0.143 0.143
Q3MEM-8MBS) Source 0.340 0.314 0.314
Double word
Destination 0.320 0.304 0.304
Source 0.220 0.181 0.181
Bit
Module access device Destination 0.140 0.105 0.105
(Multiple CPU high speed trans- Source 0.220 0.181 0.181
Word
mission area) Destination 0.140 0.105 0.105
(U3En\G10000) Source 0.500 0.437 0.437
Double word
Destination 0.340 0.285 0.285

App-64
 (3) Table of the time to be added when F/T(ST)/C device is used in OUT/SET/RST instruction
(a) When using Q00UJCPU, Q00UCPU, Q01UCPU and Q02UCPU. 8
Instruction Processing Time (µs)
Device name Condition
name Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
When not executed 2.900 2.900 2.900 2.100 8
F When displayed 116.000 116.000 116.000 68.800
When executed
Display completed 116.000 116.000 116.000 61.600
OUT
When not executed 0.360 0.240 0.180 0.120 8
T(ST), C After time up 0.360 0.240 0.180 0.120
When executed
When added 0.360 0.240 0.180 0.120
When not executed 0.120 0.080 0.006 0.004 8
SET F When displayed 116.000 116.000 116.000 68.600
When executed
Display completed 116.000 116.000 116.000 65.700
When not executed 0.120 0.080 0.006 0.004 A
F When displayed 55.800 55.800 55.800 26.500
When executed
RST Display completed 29.200 29.200 29.200 21.600

T(ST), C
When not executed 0.360 0.240 0.180 0.120 6
When executed 0.360 0.240 0.180 0.120

7
(b) When using Q03UD(E)CPU, Q04UD(E)HCPU, Q06UD(E)HCPU, Q10UD(E)HCPU,
Q13UD(E)HCPU, Q20UD(E)HCPU and Q26UD(E)HCPU
Processing Time (µs) 8
Instruction
Device name Condition Q10/Q13/Q20/
name Q03UD(E)CPU Q04/Q06UD(E)HCPU
Q26UD(E)HCPU
When not executed 1.940 1.570 1.570
F When displayed 39.930 38.090 38.090

Appendix 1.4 Operation Processing Time of Universal Model QCPU

Appendix1 OPERATION PROCESSING TIME
When executed
OUT Display completed 39.750 37.980 37.980
When not executed 0.060 0.030 0.030
T(ST), C
When executed After time up 0.060 0.030 0.030
When not executed 0.000 0.000 0.000
SET F When displayed 42.900 40.600 40.600
When executed
Display completed 39.270 37.900 37.900
When not executed 0.000 0.000 0.000
F When displayed 45.260 36.600 36.600
When executed
RST Display completed 19.020 16.190 16.190
When not executed 0.060 0.030 0.030
T(ST), C
When executed 0.060 0.030 0.030

App-65
 Appendix 1.4.2 Processing time of instructions other than subset instruction
The following table shows the processing time of instructions other than subset instructions.

(1) Table of the processing time of instructions other than subset instructions
(a) When using Q00UJCPU, Q00UCPU, Q01UCPU and Q02UCPU
Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
Min. Max. Min. Max. Min. Max. Min. Max.
ANB
ORB
MPS –– 0.120 0.080 0.060 0.040
MRD
MPP
When not executed
INV 0.120 0.080 0.060 0.040
When executed
MEP When not executed
0.120 0.080 0.060 0.040
MEF When executed
EGP When not executed
0.120 0.080 0.060 0.040
EGF When executed
Sequence PLS –– 1.800 1.900 1.800 1.900 1.800 1.900 1.300 1.600
instruction
PLF –– 1.800 1.900 1.800 1.900 1.800 1.900 1.600 1.700
When not executed 0.240 0.160 0.120 0.080
FF
When executed 1.700 1.800 1.700 1.800 1.700 1.800 1.200 1.500
When not executed 0.240 0.160 0.120 0.080
DELTA
When executed 4.000 14.700 4.000 14.700 4.000 14.700 2.800 3.600
When not executed 0.240 0.160 0.120 0.800
SFT
When executed 1.800 12.600 1.800 12.600 1.800 12.600 1.600 6.600
MC –– 0.240 0.160 0.120 0.080
MCR –– 0.120 0.080 0.060 0.040
FEND Error check performed 250.000 250.000 250.000 250.000 250.000 250.000 175.000 252.000
END No error check performed 250.000 250.000 250.000 250.000 250.000 250.000 175.000 221.000

App-66
 Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
Min. Max. Min. Max. Min. Max. Min. Max.
8
NOP
Sequence
NOPLF –– 0.120 0.080 0.060 0.040
instruction
PAGE 8
Single In conductive status 4.400 20.900 4.400 20.900 4.400 20.900 4.700 10.100
LDE=
precision In non-conductive status 4.400 20.900 4.400 20.900 4.400 20.900 4.700 10.100

Single
When not executed 0.360 0.240 0.180 0.120 8
ANDE= When In conductive status 4.200 19.600 4.200 19.600 4.200 19.600 4.200 12.500
precision
executed In non-conductive status 4.200 19.600 4.200 19.600 4.200 19.600 4.400 11.900

Single
When not executed 0.360 0.240 0.180 0.120 8
ORE= When In conductive status 4.200 17.400 4.200 17.400 4.200 17.400 4.600 10.800
precision
executed In non-conductive status 4.200 17.400 4.200 17.400 4.200 17.400 4.500 9.800

LDE< >
Single In conductive status 4.400 20.900 4.400 20.900 4.400 20.900 4.700 7.700 A
precision In non-conductive status 4.400 20.900 4.400 20.900 4.400 20.900 4.600 8.200
When not executed 0.360 0.240 0.180 0.120
Single
ANDE< >
precision
When In conductive status 4.200 19.600 4.200 19.600 4.200 19.600 4.300 14.200 6
executed In non-conductive status 4.200 19.600 4.200 19.600 4.200 19.600 4.400 14.200
When not executed 0.360 0.240 0.180 0.120
Single
ORE< >
precision
When In conductive status 4.200 17.400 4.200 17.400 4.200 17.400 4.600 6.700 7
executed In non-conductive status 4.200 17.400 4.200 17.400 4.200 17.400 4.400 6.600

Single In conductive status 4.400 20.900 4.400 20.900 4.400 20.900 4.700 13.700
LDE>
precision In non-conductive status 4.400 20.900 4.400 20.900 4.400 20.900 4.600 13.700 8
When not executed 0.360 0.240 0.180 0.120
Single
Basic ANDE> When In conductive status 4.200 19.600 4.200 19.600 4.200 19.600 4.300 8.100
precision
instruction executed In non-conductive status 4.200 19.600 4.200 19.600 4.200 19.600 4.200 8.100
When not executed 0.360 0.240 0.180 0.120
Single

Appendix 1.4 Operation Processing Time of Universal Model QCPU

Appendix1 OPERATION PROCESSING TIME
ORE> When In conductive status 4.200 17.400 4.200 17.400 4.200 17.400 4.600 8.500
precision
executed In non-conductive status 4.200 17.400 4.200 17.400 4.200 17.400 4.400 8.100

Single In conductive status 4.400 20.900 4.400 20.900 4.400 20.900 4.700 11.100
LDE<=
precision In non-conductive status 4.400 20.900 4.400 20.900 4.400 20.900 4.700 9.600
When not executed 0.360 0.240 0.180 0.120
Single
ANDE<= When In conductive status 4.200 19.600 4.200 19.600 4.200 19.600 4.100 7.800
precision
executed In non-conductive status 4.200 19.600 4.200 19.600 4.200 19.600 4.400 8.200
When not executed 0.360 0.240 0.180 0.120
Single
ORE<= When In conductive status 4.200 17.400 4.200 17.400 4.200 17.400 4.500 10.300
precision
executed In non-conductive status 4.200 17.400 4.200 17.400 4.200 17.400 4.400 9.800

Single In conductive status 4.400 20.900 4.400 20.900 4.400 20.900 4.700 11.500
LDE<
precision In non-conductive status 4.400 20.900 4.400 20.900 4.400 20.900 4.700 10.900
When not executed 0.360 0.240 0.180 0.120
Single
ANDE< When In conductive status 4.200 19.600 4.200 19.600 4.200 19.600 4.300 9.200
precision
executed In non-conductive status 4.200 19.600 4.200 19.600 4.200 19.600 4.400 9.400
When not executed 0.360 0.240 0.180 0.120
Single
ORE< When In conductive status 4.200 17.400 4.200 17.400 4.200 17.400 4.600 10.400
precision
executed In non-conductive status 4.200 17.400 4.200 17.400 4.200 17.400 4.400 9.800

App-67
 Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
Min. Max. Min. Max. Min. Max. Min. Max.

Single In conductive status 4.400 20.900 4.400 20.900 4.400 20.900 4.700 12.200
LDE>=
precision In non-conductive status 4.400 20.900 4.400 20.900 4.400 20.900 4.700 11.800
When not executed 0.360 0.240 0.180 0.120
Single
ANDE>= When In conductive status 4.200 19.600 4.200 19.600 4.200 19.600 4.100 6.700
precision
executed In non-conductive status 4.200 19.600 4.200 19.600 4.200 19.600 4.400 7.000
When not executed 0.360 0.240 0.180 0.120
Single
ORE>= When In conductive status 4.200 17.400 4.200 17.400 4.200 17.400 4.600 14.000
precision
executed In non-conductive status 4.200 17.400 4.200 17.400 4.200 17.400 4.500 14.300

Double In conductive status 4.700 37.400 4.700 37.400 4.700 37.400 4.200 21.000
LDED=
precision In non-conductive status 4.700 37.400 4.700 37.400 4.700 37.400 5.100 21.900
When not executed 0.360 0.240 0.180 0.120
Double
ANDED= When In conductive status 4.500 34.700 4.500 34.700 4.500 34.700 3.800 17.800
precision
executed In non-conductive status 4.500 34.700 4.500 34.700 4.500 34.700 4.100 18.100
When not executed 0.360 0.240 0.180 0.120
Double
ORED= When In conductive status 4.700 33.200 4.700 33.200 4.700 33.200 4.100 23.800
precision
executed In non-conductive status 4.700 33.200 4.700 33.200 4.700 33.200 4.900 25.500

Double In conductive status 4.700 37.400 4.700 37.400 4.700 37.400 5.100 23.500
LDED<>
precision In non-conductive status 4.700 37.400 4.700 37.400 4.700 37.400 4.200 22.600
When not executed 0.360 0.240 0.180 0.120
Double
Basic ANDED<> When In conductive status 4.500 34.700 4.500 34.700 4.500 34.700 4.000 18.800
precision
instruction executed In non-conductive status 4.500 34.700 4.500 34.700 4.500 34.700 4.000 18.700
When not executed 0.360 0.240 0.180 0.120
Double
ORED<> When In conductive status 4.700 33.200 4.700 33.200 4.700 33.200 5.000 25.200
precision
executed In non-conductive status 4.700 33.200 4.700 33.200 4.700 33.200 4.100 23.400

Double In conductive status 4.700 37.400 4.700 37.400 4.700 37.400 5.100 25.100
LDED>
precision In non-conductive status 4.700 37.400 4.700 37.400 4.700 37.400 4.200 23.400
When not executed 0.360 0.240 0.180 0.120
Double
ANDED> When In conductive status 4.500 34.700 4.500 34.700 4.500 34.700 4.000 19.500
precision
executed In non-conductive status 4.500 34.700 4.500 34.700 4.500 34.700 4.100 19.700
When not executed 0.360 0.240 0.180 0.120
Double
ORED> When In conductive status 4.700 33.200 4.700 33.200 4.700 33.200 5.000 24.200
precision
executed In non-conductive status 4.700 33.200 4.700 33.200 4.700 33.200 4.900 25.800

Double In conductive status 4.700 37.400 4.700 37.400 4.700 37.400 4.200 22.500
LDED<=
precision In non-conductive status 4.700 37.400 4.700 37.400 4.700 37.400 4.200 13.500
When not executed 0.360 0.240 0.180 0.120
Double
ANDED<= When In conductive status 4.500 34.700 4.500 34.700 4.500 34.700 4.000 19.600
precision
executed In non-conductive status 4.500 34.700 4.500 34.700 4.500 34.700 4.100 19.700
When not executed 0.360 0.240 0.180 0.120
Double
ORED<= When In conductive status 4.700 33.200 4.700 33.200 4.700 33.200 5.000 26.300
precision
executed In non-conductive status 4.700 33.200 4.700 33.200 4.700 33.200 5.000 25.200

App-68
 Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
Min. Max. Min. Max. Min. Max. Min. Max.
8
Double In conductive status 4.700 37.400 4.700 37.400 4.700 37.400 5.100 25.000
LDED<
precision In non-conductive status 4.700 37.400 4.700 37.400 4.700 37.400 4.200 24.100
When not executed 0.360 0.240 0.180 0.120 8
Double
ANDED< When In conductive status 4.500 34.700 4.500 34.700 4.500 34.700 4.000 19.400
precision
executed In non-conductive status 4.500 34.700 4.500 34.700 4.500 34.700 4.100 19.700
When not executed 0.360 0.240 0.180 0.120 8
Double
ORED< When In conductive status 4.700 33.200 4.700 33.200 4.700 33.200 5.000 25.100
precision
executed In non-conductive status 4.700 33.200 4.700 33.200 4.700 33.200 5.000 25.100

Double In conductive status 4.700 37.400 4.700 37.400 4.700 37.400 4.200 13.100 8
LDED>=
precision In non-conductive status 4.700 37.400 4.700 37.400 4.700 37.400 4.300 13.100
When not executed 0.360 0.240 0.180 0.120
ANDED>=
Double
When In conductive status 4.500 34.700 4.500 34.700 4.500 34.700 3.900 19.500 A
precision
executed In non-conductive status 4.500 34.700 4.500 34.700 4.500 34.700 4.100 19.800
When not executed 0.360 0.240 0.180 0.120
ORED>=
Double
precision
When In conductive status 4.700 33.200 4.700 33.200 4.700 33.200 5.000 25.100 6
executed In non-conductive status 4.700 33.200 4.700 33.200 4.700 33.200 4.200 18.500
In conductive status 8.300 38.500 8.300 38.500 8.300 38.500 5.500 14.900
LD$=
In non-conductive status 8.300 38.500 8.300 38.500 8.300 38.500 5.500 15.600 7
When not executed 0.360 0.240 0.180 0.120
AND$= In conductive status 7.200 37.300 7.200 37.300 7.200 37.300 5.200 13.800
When executed
In non-conductive status 7.200 37.300 7.200 37.300 7.200 37.300 5.300 14.500 8
When not executed 0.360 0.240 0.180 0.120
Basic
OR$= In conductive status 7.500 36.600 7.500 36.600 7.500 36.600 5.500 14.900
instruction When executed
In non-conductive status 7.500 36.600 7.500 36.600 7.500 36.600 5.300 14.600
In conductive status 8.300 39.300 8.300 39.300 8.300 39.300 5.600 15.200

Appendix 1.4 Operation Processing Time of Universal Model QCPU

Appendix1 OPERATION PROCESSING TIME
LD$< >
In non-conductive status 8.300 39.300 8.300 39.300 8.300 39.300 5.600 15.400
When not executed 0.360 0.240 0.180 0.120
AND$< > In conductive status 8.000 38.200 8.000 38.200 8.000 38.200 4.300 21.500
When executed
In non-conductive status 8.000 38.200 8.000 38.200 8.000 38.200 4.500 23.400
When not executed 0.360 0.240 0.180 0.120
OR$< > In conductive status 8.300 37.300 8.300 37.300 8.300 37.300 5.400 17.700
When executed
In non-conductive status 8.300 37.300 8.300 37.300 8.300 37.300 5.300 19.400
In conductive status 8.300 41.600 8.300 41.600 8.300 41.600 6.400 19.200
LD$>
In non-conductive status 8.300 41.600 8.300 41.600 8.300 41.600 5.600 20.100
When not executed 0.360 0.240 0.180 0.120
AND$> In conductive status 8.000 38.100 8.000 38.100 8.000 38.100 4.500 15.400
When executed
In non-conductive status 8.000 38.100 8.000 38.100 8.000 38.100 4.600 15.300
When not executed 0.360 0.240 0.180 0.120
OR$> In conductive status 8.200 35.700 8.200 35.700 8.200 35.700 5.400 20.000
When executed
In non-conductive status 8.200 35.700 8.200 35.700 8.200 35.700 5.400 22.100
In conductive status 8.300 39.200 8.300 39.200 8.300 39.200 5.800 12.800
LD$<=
In non-conductive status 8.300 39.200 8.300 39.200 8.300 39.200 6.300 13.900
When not executed 0.360 0.240 0.180 0.120
AND$<= In conductive status 7.100 36.500 7.100 36.500 7.100 36.500 6.000 16.000
When executed
In non-conductive status 7.100 36.500 7.100 36.500 7.100 36.500 6.100 16.200

App-69
 Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
Min. Max. Min. Max. Min. Max. Min. Max.
When not executed 0.360 0.240 0.180 0.120
OR$<= When In conductive status 7.400 35.600 7.400 35.600 7.400 35.600 4.700 14.600
executed In non-conductive status 7.400 35.600 7.400 35.600 7.400 35.600 4.600 14.400
In conductive status 7.400 40.000 7.400 40.000 7.400 40.000 4.800 17.000
LD$<
In non-conductive status 7.400 40.000 7.400 40.000 7.400 40.000 5.500 18.000
When not executed 0.360 0.240 0.180 0.120
AND$< When In conductive status 8.000 37.300 8.000 37.300 8.000 37.300 5.900 13.400
executed In non-conductive status 8.000 37.300 8.000 37.300 8.000 37.300 6.200 14.500
When not executed 0.360 0.240 0.180 0.120
OR$< When In conductive status 8.300 35.600 8.300 35.600 8.300 35.600 6.200 18.700
executed In non-conductive status 8.300 35.600 8.300 35.600 8.300 35.600 5.400 19.700
In conductive status 7.400 38.300 7.400 38.300 7.400 38.300 4.800 10.000
LD$>=
In non-conductive status 7.400 38.300 7.400 38.300 7.400 38.300 5.500 11.200
When not executed 0.360 0.240 0.180 0.120
AND$>= When In conductive status 7.200 37.300 7.200 37.300 7.200 37.300 4.400 21.600
executed In non-conductive status 7.200 37.300 7.200 37.300 7.200 37.300 4.500 21.800
When not executed 0.360 0.240 0.180 0.120
OR$>= When In conductive status 8.200 36.400 8.200 36.400 8.200 36.400 5.400 15.400
executed In non-conductive status 8.200 36.400 8.200 36.400 8.200 36.400 5.300 15.300
n=1 15.300 36.100 15.300 36.100 15.300 36.100 8.200 22.600
BKCMP = S1 S2 D n
n = 96 64.500 85.500 64.500 85.500 64.500 85.500 57.400 72.500
Basic n=1 15.300 36.100 15.300 36.100 15.300 36.100 8.200 22.500
instruction BKCMP<> S1 S2 D n
n = 96 66.600 87.500 66.600 87.500 66.600 87.500 59.500 74.500
n=1 15.300 36.100 15.300 36.100 15.300 36.100 8.200 23.100
BKCMP> S1 S2 D n
n = 96 66.600 87.500 66.600 87.500 66.600 87.500 59.500 74.400
n=1 15.300 36.100 15.300 36.100 15.300 36.100 8.200 22.500
BKCMP<= S1 S2 D n
n = 96 64.500 85.500 64.500 85.500 64.500 85.500 57.400 72.400
n=1 15.300 36.100 15.300 36.100 15.300 36.100 8.300 23.000
BKCMP< S1 S2 D n
n = 96 66.600 87.500 66.600 87.500 66.600 87.500 59.500 74.500
n=1 15.300 36.100 15.300 36.100 15.300 36.100 8.200 22.500
BKCMP>= S1 S2 D n
n = 96 64.500 85.500 64.500 85.500 64.500 85.500 57.400 72.400
n=1 15.800 36.300 15.800 36.300 15.800 36.300 9.350 29.000
DBKCMP = S1 S2 D n
n = 96 64.900 85.700 64.900 85.700 64.900 85.700 60.700 78.400
n=1 15.700 36.300 15.700 36.300 15.700 36.300 9.350 28.900
DBKCMP<> S1 S2 D n
n = 96 67.000 87.700 67.000 87.700 67.000 87.700 62.500 80.300
n=1 15.800 36.300 15.800 36.300 15.800 36.300 9.350 29.000
DBKCMP> S1 S2 D n
n = 96 67.000 87.700 67.000 87.700 67.000 87.700 62.600 80.300
n=1 15.700 36.300 15.700 36.300 15.700 36.300 9.350 29.000
DBKCMP<= S1 S2 D n
n = 96 64.800 85.700 64.800 85.700 64.800 85.700 60.800 78.400
n=1 15.800 36.300 15.800 36.300 15.800 36.300 9.350 29.000
DBKCMP< S1 S2 D n
n = 96 67.000 87.700 67.000 87.700 67.000 87.700 62.700 80.400
n=1 15.700 36.300 15.700 36.300 15.700 36.300 9.300 29.000
DBKCMP>= S1 S2 D n
n = 96 64.800 85.700 64.800 85.700 64.800 85.700 60.700 78.400

App-70
 Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
Min. Max. Min. Max. Min. Max. Min. Max.
8
DB + S D When executed 5.750 13.300 5.750 13.300 5.750 13.300 4.900 7.500

DB + S1 S2 D When executed 5.650 13.200 5.650 13.200 5.650 13.200 5.200 11.000 8
DB - S D When executed 5.750 12.700 5.750 12.700 5.750 12.700 4.900 10.200

DB - S1 S2 D When executed 5.650 12.600 5.650 12.600 5.650 12.600 5.200 8.600
8
DB * S1 S2 D When executed 8.750 40.200 8.750 40.200 8.750 40.200 8.300 22.200

DB/ S1 S2 When executed 5.750 21.500 5.750 21.500 5.750 21.500 6.100 19.200
8
D

Double S = 0, D =0 4.500 26.700 4.500 26.700 4.500 26.700 4.800 16.800

ED + S D preci-
sion S = 21023, D = 21023 5.800 32.900 5.800 32.900 5.800 32.900 4.800 16.800

5.450 35.400 5.450 35.400 5.450 35.400 7.100 20.100

A
Double S1 = 0, S2 =0
ED + S1 S2 D preci-
sion S1 = 21023, S2 = 21023 6.750 41.400 6.750 41.400 6.750 41.400 7.100 20.100

Double S = 0, D =0 5.200 25.900 5.200 25.900 5.200 25.900 5.000 17.300 6

ED - S D preci-
sion S = 21023, D = 21023 6.000 27.700 6.000 27.700 6.000 27.700 5.000 17.300

Double S1 = 0, S2 =0 5.550 32.900 5.550 32.900 5.550 32.900 6.000 16.300 7

ED - S1 S2 D preci-
sion S1 = 21023, S2 = 21023 5.750 33.900 5.750 33.900 5.750 33.900 6.000 16.300

ED * S1 S2 D
Double
preci-
S1 = 0, S2 =0 5.550 34.400 5.550 34.400 5.550 34.400 10.500 22.300
8
sion S1 = 21023, S2 = 21023 5.950 39.100 5.950 39.100 5.950 39.100 10.500 22.300

Basic Double
instruction ED / S1 S2 D preci- S1 = 21023, S2 = 21023 8.050 44.200 8.050 44.200 8.050 44.200 7.500 27.200
sion

Appendix 1.4 Operation Processing Time of Universal Model QCPU

Appendix1 OPERATION PROCESSING TIME
n=1 13.500 28.500 13.500 28.500 13.500 28.500 12.100 19.700
BK + S1 S2 D n
n = 96 63.100 78.200 63.100 78.200 63.100 78.200 61.700 69.300
n=1 13.500 28.500 13.500 28.500 13.500 28.500 12.100 20.600
BK - S1 S2 D n
n = 96 63.100 78.200 63.100 78.200 63.100 78.200 61.700 70.200
n=1 10.100 24.200 10.100 24.200 10.100 24.200 7.050 19.200
DBK + S1 S2 D n
n = 96 59.800 73.900 59.800 73.900 59.800 73.900 59.400 68.900
n=1 10.100 24.200 10.100 24.200 10.100 24.200 7.050 19.900
DBK - S1 S2 D n
n = 96 59.800 73.900 59.800 73.900 59.800 73.900 59.400 69.600

$+ S D –– 15.400 64.300 15.400 64.300 15.400 64.300 14.400 34.000

$ + S1 S2 D –– 19.700 71.000 19.700 71.000 19.700 71.000 9.200 22.900

Double S =0 3.100 19.600 3.100 19.600 3.100 19.600 4.000 8.900

FLTD preci-
sion S = 7FFFH 3.350 19.900 3.350 19.900 3.350 19.900 3.400 9.000

Double S =0 3.200 20.400 3.200 20.400 3.200 20.400 4.100 10.800

DFLTD preci-
sion S = 7FFFFFFFH 3.450 20.500 3.450 20.500 3.450 20.500 3.600 10.800

Double S =0 3.200 22.900 3.200 22.900 3.200 22.900 3.500 9.300

INTD preci-
sion S = 32766.5 4.100 34.300 4.100 34.300 4.100 34.300 5.100 19.500

Double S =0 3.200 23.000 3.200 23.000 3.200 23.000 2.600 6.800

DINTD preci-
sion S = 1234567890.3 4.050 33.500 4.050 33.500 4.050 33.500 3.400 11.700

App-71
 Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
Min. Max. Min. Max. Min. Max. Min. Max.
DBL When executed 3.300 5.900 3.300 5.900 3.300 5.900 2.700 3.800
WORD When executed 3.000 7.250 3.000 7.250 3.000 7.250 2.900 7.000
GRY When executed 3.350 7.500 3.350 7.500 3.350 7.500 2.700 6.100
DGRY When executed 3.000 7.200 3.000 7.200 3.000 7.200 2.900 4.600
GBIN When executed 4.600 9.700 4.600 9.700 4.600 9.700 4.000 8.200
DGBIN When executed 5.550 10.700 5.550 10.700 5.550 10.700 5.500 8.000
NEG When executed 3.300 6.850 3.300 6.850 3.300 6.850 2.400 4.100
DNEG When executed 3.050 5.700 3.050 5.700 3.050 5.700 2.500 4.300
Floating point = 0 3.100 7.350 3.100 7.350 3.100 7.350 2.500 3.400
ENEG
Floating point = -1.0 3.350 11.700 3.350 11.700 3.350 11.700 2.700 4.500
Floating point = 0 3.000 21.200 3.000 21.200 3.000 21.200 2.200 3.500
EDNEG
Floating point = -1.0 3.100 22.900 3.100 22.900 3.100 22.900 2.400 3.500
n=1 8.700 27.600 8.700 27.600 8.700 27.600 9.700 22.000
BKBCD S D n
n = 96 84.200 104.000 84.200 104.000 84.200 104.000 74.200 86.500
n=1 8.450 28.100 8.450 28.100 8.450 28.100 8.900 16.300
BKBIN S D n
n = 96 56.100 75.800 56.100 75.800 56.100 75.800 58.500 65.100
ECON –– 3.100 21.300 3.100 21.300 3.100 21.300 4.300 6.800
EDCON –– 5.050 24.000 5.050 24.000 5.050 24.000 2.800 5.400
EDMOV –– 2.900 22.900 2.900 22.900 2.900 22.900 3.200 7.800
Character string to be
6.250 30.100 6.250 30.100 6.250 30.100 4.500 13.900
transferred = 0
$MOV
Character string to be
Basic 15.500 39.300 15.500 39.300 15.500 39.300 15.400 17.500
transferred = 32
instruction
n=1 8.400 20.900 8.400 20.900 8.400 20.900 8.700 15.200
BXCH D1 D2 n
n = 96 67.100 79.900 67.100 79.900 67.100 79.900 67.200 74.000
SWAP –– 3.300 3.550 3.300 3.550 3.300 3.550 2.400 2.700
GOEND –– 0.550 0.550 0.550 0.500
DI –– 2.800 8.400 2.800 8.400 2.800 8.400 1.800 2.200
EI –– 4.300 12.300 4.300 12.300 4.300 12.300 3.100 3.800
IMASK –– 12.900 40.600 12.900 40.600 12.900 40.600 9.800 25.000
IRET –– 1.000 1.000 1.000 1.000
n=1 7.500 26.500 7.500 26.500 7.500 26.500 4.300 16.100
RSF X n
n = 96 11.400 30.400 11.400 30.400 11.400 30.400 11.400 23.700
n=1 7.300 26.300 7.300 26.300 7.300 26.300 3.800 10.000
RSF Y n
n = 96 10.900 29.900 10.900 29.900 10.900 29.900 8.500 15.200
UDCNT1 –– 1.500 7.100 1.500 7.100 1.500 7.100 1.000 2.000
UDCNT2 –– 1.500 6.300 1.500 6.300 1.500 6.300 1.000 4.000
TTMR –– 5.300 20.900 5.300 20.900 5.300 20.900 3.900 6.100
STMR –– 8.900 49.800 8.900 49.800 8.900 49.800 7.200 30.000
ROTC –– 52.300 52.600 52.300 52.600 52.300 52.600 15.200 16.100
RAMP –– 7.400 30.900 7.400 30.900 7.400 30.900 5.900 18.300
SPD –– 1.500 6.300 1.500 6.300 1.500 6.300 1.000 2.800
PLSY –– 6.400 7.100 6.400 7.100 6.400 7.100 3.500 4.700
PWM –– 3.900 4.600 3.900 4.600 3.900 4.600 3.400 3.400
MTR –– 10.100 61.400 10.100 61.400 10.100 61.400 20.500 28.400

App-72
 Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
Min. Max. Min. Max. Min. Max. Min. Max.
8
n=1 13.600 28.500 13.600 28.500 13.600 28.500 12.100 20.100
BKAND S1 S2 D n
n = 96 63.200 78.200 63.200 78.200 63.200 78.200 57.400 63.200
n=1 13.500 28.500 13.500 28.500 13.500 28.500 7.700 13.200
8
BKOR S1 S2 D n
n = 96 63.100 78.200 63.100 78.200 63.100 78.200 57.400 62.800
n=1 13.600 28.300 13.600 28.300 13.600 28.300 7.800 13.200
BKXOR S1 S2 D n
n = 96 63.100 78.000 63.100 78.000 63.100 78.000 57.300 62.800
8
n=1 13.500 28.300 13.500 28.300 13.500 28.300 7.800 14.100
BKXNR S1 S2 D n
n = 96 63.100 78.000 63.100 78.000 63.100 78.000 57.400 62.900
n=1 5.050 21.100 5.050 21.100 5.050 21.100 3.700 6.300 8
BSFR D n
n = 96 9.000 34.800 9.000 34.800 9.000 34.800 10.200 12.800
n=1 4.800 19.100 4.800 19.100 4.800 19.100 4.500 8.900
BSFL D n
n = 96 8.550 34.300 8.550 34.300 8.550 34.300 10.100 14.300 A
n1 = 16 / n2 = 1 10.300 46.500 10.300 46.500 10.300 46.500 8.800 43.400
SFTBR D n1 n2
n1 = 16 / n2 = 15 10.300 46.400 10.300 46.400 10.300 46.400 8.750 43.400
n1 = 16 / n2 = 1 10.500 49.800 10.500 49.800 10.500 49.800 8.050 45.100 6
SFTBL D n1 n2
n1 = 16 / n2 = 15 10.500 49.800 10.500 49.800 10.500 49.800 8.050 45.100
n1 = 16 / n2 = 1 7.950 24.000 7.950 24.000 7.950 24.000 6.500 22.800
SFTWR D n1 n2
n1 = 16 / n2 = 15 7.950 24.100 7.950 24.100 7.950 24.100 6.500 22.800 7
n1 = 16 / n2 = 1 8.700 23.600 8.700 23.600 8.700 23.600 7.350 23.600
SFTWL D n1 n2
n1 = 16 / n2 = 15 8.650 23.700 8.650 23.700 8.650 23.700 7.300 23.700
n=1 4.550 4.750 4.550 4.750 4.550 4.750 3.000 3.400 8
BSET D n
n = 15 4.550 4.750 4.550 4.750 4.550 4.750 3.000 3.500
Application
n=1 4.600 4.750 4.600 4.750 4.600 4.750 3.000 3.400
instruction
BRST D n
n = 15 4.600 4.750 4.600 4.750 4.600 4.750 3.000 3.400
TEST When executed 7.250 13.200 7.250 13.200 7.250 13.200 4.400 6.900

Appendix 1.4 Operation Processing Time of Universal Model QCPU

Appendix1 OPERATION PROCESSING TIME
DTEST When executed 6.950 12.900 6.950 12.900 6.950 12.900 4.500 7.000
n=1 7.350 11.600 7.350 11.600 7.350 11.600 4.300 5.200
BKRST D n
n = 96 10.100 22.600 10.100 22.600 10.100 22.600 6.500 13.200
All match 6.650 6.800 6.650 6.800 6.650 6.800 5.000 5.300
n=1
None match 6.650 6.800 6.650 6.800 6.650 6.800 5.000 5.300
SER S1 S2 D n
n= All match 34.000 42.300 34.000 42.300 34.000 42.300 32.300 35.900
96 None match 34.000 42.300 34.000 42.300 34.000 42.300 32.400 35.900
All match 8.000 16.300 8.000 16.300 8.000 16.300 6.800 10.200
n=1
None match 8.000 16.300 8.000 16.300 8.000 16.300 6.800 10.200
DSER S1 S2 D n
n= All match 54.100 62.600 54.100 62.600 54.100 62.600 52.800 56.300
96 None match 54.100 62.600 54.100 62.600 54.100 62.600 52.800 56.300

S =0 4.100 4.200 4.100 4.200 4.100 4.200 3.700 4.100

DSUM S D
S = FFFFFFFFH 4.100 4.200 4.100 4.200 4.100 4.200 3.800 4.100

n=2 8.850 23.000 8.850 23.000 8.850 23.000 6.000 16.400

DECO S D n
n=8 13.600 36.600 13.600 36.600 13.600 36.600 8.100 15.200
M1 = ON 7.650 11.900 7.650 11.900 7.650 11.900 5.300 6.300
n=2
M4 = ON 7.500 11.700 7.500 11.700 7.500 11.700 5.200 6.200
ENCO S D n
M1 = ON 14.600 27.800 14.600 27.800 14.600 27.800 10.400 17.900
n=8
M256 = ON 10.600 23.700 10.600 23.700 10.600 23.700 5.700 13.300

App-73
 Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
Min. Max. Min. Max. Min. Max. Min. Max.
n=1 6.500 14.800 6.500 14.800 6.500 14.800 5.000 10.900
DIS S D n
n=4 6.900 15.200 6.900 15.200 6.900 15.200 5.400 11.300
n=1 6.800 15.100 6.800 15.100 6.800 15.100 5.500 8.900
UNI S D n
n=4 7.500 15.900 7.500 15.900 7.500 15.900 6.200 9.600
NDIS When executed 4.750 18.700 4.750 18.700 4.750 18.700 11.000 16.300
NUNI When executed 4.750 18.700 4.750 18.700 4.750 18.700 10.600 16.000
n=1 6.600 14.900 6.600 14.900 6.600 14.900 5.000 6.500
WTOB S D n
n = 96 37.700 46.100 37.700 46.100 37.700 46.100 36.000 38.400
n=1 7.350 15.600 7.350 15.600 7.350 15.600 5.100 6.100
BTOW S D n
n = 96 32.100 40.500 32.100 40.500 32.100 40.500 29.900 32.000
n=1 8.250 24.900 8.250 24.900 8.250 24.900 4.300 6.900
MAX S D n
n = 96 34.200 51.600 34.200 51.600 34.200 51.600 32.000 34.300
n=1 8.250 24.800 8.250 24.800 8.250 24.800 4.400 6.800
MIN S D n
n = 96 34.200 51.600 34.200 51.600 34.200 51.600 30.300 34.800
n=1 6.800 34.900 6.800 34.900 6.800 34.900 4.800 14.200
DMAX S D n
n = 96 60.300 89.200 60.300 89.200 60.300 89.200 56.400 68.000
n=1 7.600 35.700 7.600 35.700 7.600 35.700 4.800 9.300
DMIN S D n
n = 96 59.400 90.000 59.400 90.000 59.400 90.000 55.400 62.800
n=1 10.100 28.900 10.100 28.900 10.100 28.900 6.200 12.200
SORT S1 n S2 D1 D2
n = 96 52.100 92.400 52.100 92.400 52.100 92.400 6.200 13.100
n=1 9.300 29.000 9.300 29.000 9.300 29.000 6.200 10.500
DSORT S1 n S2 D1 D2
n = 96 43.600 89.600 43.600 89.600 43.600 89.600 6.100 10.500

Application n=1 6.700 15.000 6.700 15.000 6.700 15.000 4.800 6.200
WSUM S D n
instruction n = 96 28.900 37.100 28.900 37.100 28.900 37.100 26.900 28.700
n=1 8.600 26.800 8.600 26.800 8.600 26.800 5.500 7.000
DWSUM S D n
n = 96 56.200 74.700 56.200 74.700 56.200 74.700 53.000 56.300
n=1 5.850 19.800 5.850 19.800 5.850 19.800 4.300 17.300
MEAN S D n
n = 96 17.300 38.200 17.300 38.200 17.300 38.200 16.000 35.500
n=1 6.900 23.300 6.900 23.300 6.900 23.300 5.750 21.900
DMEAN S D n
n = 96 29.400 49.900 29.400 49.900 29.400 49.900 29.200 48.600
NEXT –– 1.000 1.100 1.000 1.100 1.000 1.100 0.980 1.400
BREAK –– 4.700 25.000 4.700 25.000 4.700 25.000 21.300 17.900
Return to original program 4.100 19.500 4.100 19.500 4.100 19.500 2.000 3.000
RET
Return to other program 4.700 16.700 4.700 16.700 4.700 16.700 2.300 4.900
Internal file pointer 5.400 5.400 5.400 5.400 5.400 5.400 3.300 5.300
FCALL Pn
Common pointer 7.600 30.500 7.600 30.500 7.600 30.500 4.900 6.600

FCALL Pn S1 to S5 –– 50.400 62.700 50.400 62.700 50.400 62.700 19.800 23.700

ECALL * Pn
–– 105.000 214.000 105.000 214.000 105.000 214.000 75.700 134.000
*: Program name

ECALL * Pn S1 to S5
–– 164.000 271.000 164.000 271.000 164.000 271.000 109.000 173.000
*: Program name
EFCALL * Pn
–– 105.000 214.000 105.000 214.000 105.000 214.000 76.200 134.000
*: Program name

EFCALL * Pn S1 to S5
–– 164.000 271.000 164.000 271.000 164.000 271.000 90.500 170.000
*: Program name
XCALL –– 5.100 6.700 5.100 6.700 5.100 6.700 3.800 6.400

App-74
 Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
Min. Max. Min. Max. Min. Max. Min. Max.
8
When selecting I/O refresh only 18.100 89.100 18.100 89.100 18.100 89.100 12.800 79.000
When selecting CC-Link refresh
only (Master station side)
33.300 132.000 33.300 132.000 33.300 132.000 24.900 119.000
8
When selecting CC-Link refresh
33.300 132.000 33.300 132.000 33.300 132.000 24.900 119.000
only (Local station side)
When selecting MELSECNET/H
78.600 231.000 78.600 231.000 78.600 231.000 54.000 212.000
8
refresh only (Control station side)
When selecting MELSECNET/H
78.600 231.000 78.600 231.000 78.600 231.000 54.000 212.000
refresh only (Normal station side)
8
When selecting intelli auto
18.100 89.000 18.100 89.000 18.100 89.000 12.800 79.000
COM refresh only
CCOM When selecting I/O outside the
group only (Input only)
15.700 71.600 15.700 71.600 15.700 71.600 8.600 76.500 A
When selecting I/O outside the
40.200 152.000 40.200 152.000 40.200 152.000 26.300 135.000
group only (Output only)
When selecting I/O outside the
45.800 153.000 45.800 153.000 45.800 153.000 26.100 135.000
6
group only (Both I/O)
When selecting refresh of multi-
ple CPU high speed transmission –– –– –– –– –– –– –– –– 7
area only
When selecting communication
18.200 89.000 18.200 89.000 18.200 89.000 7.250 54.300
with peripheral device
Number of data points = 0 6.100 14.200 6.100 14.200 6.100 14.200 3.700 10.100
8
FIFW
Number of data points = 96 6.100 14.200 6.100 14.200 6.100 14.200 3.800 5.200

Application Number of data points = 0 7.500 15.600 7.500 15.600 7.500 15.600 4.400 5.800
FIFR
instruction Number of data points = 96 37.000 45.000 37.000 45.000 37.000 45.000 33.500 35.200

Appendix 1.4 Operation Processing Time of Universal Model QCPU

Appendix1 OPERATION PROCESSING TIME
Number of data points = 0 7.600 15.600 7.600 15.600 7.600 15.600 4.400 10.800
FPOP
Number of data points = 96 7.600 15.600 7.600 15.600 7.600 15.600 4.400 10.800
Number of data points = 0 6.900 15.000 6.900 15.000 6.900 15.000 5.000 10.700
FINS
Number of data points = 96 36.600 44.700 36.600 44.700 36.600 44.700 4.400 10.900
Number of data points = 0 8.000 16.100 8.000 16.100 8.000 16.100 4.900 11.300
FDEL
Number of data points = 96 37.300 45.500 37.300 45.500 37.300 45.500 34.200 35.900
n3 = 1 17.400 74.700 17.400 74.700 17.400 74.700 12.100 71.300
FROM n1 n2 D n3
n3 = 1000 406.000 498.500 406.000 498.500 406.000 498.500 402.600 495.100

n3 = 1 19.600 85.600 19.600 85.600 19.600 85.600 14.600 81.800

DFRO n1 n2 D n3
n3 = 500 406.000 498.500 406.000 498.500 406.000 498.500 402.600 495.100

n3 = 1 16.400 69.600 16.400 69.600 16.400 69.600 11.700 63.400

TO n1 n2 S n3
n3 = 1000 381.300 471.200 381.300 471.200 381.300 471.200 375.900 464.300

n3 = 1 18.600 85.100 18.600 85.100 18.600 85.100 14.200 78.500

DTO n1 n2 S n3
n3 = 500 381.300 471.200 381.300 471.200 381.300 471.200 375.900 464.300

No display no display 1.500 7.100 1.500 7.100 1.500 7.100 5.100 5.100
LEDR LED instruction execution no
38.900 109.000 38.900 109.000 38.900 109.000 35.700 89.200
display

S =1 5.600 13.900 5.600 13.900 5.600 13.900 4.900 6.500

BINDA S D
S = -32768 7.800 16.200 7.800 16.200 7.800 16.200 7.200 8.700

S =1 6.200 14.500 6.200 14.500 6.200 14.500 5.700 7.100

DBINDA S D
S = -2147483648 11.000 19.200 11.000 19.200 11.000 19.200 10.400 12.200

App-75
 Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
Min. Max. Min. Max. Min. Max. Min. Max.

S =1 5.050 13.400 5.050 13.400 5.050 13.400 4.400 5.900

BINHA S D
S = FFFFH 5.050 13.400 5.050 13.400 5.050 13.400 4.400 5.800

S =1 5.600 13.900 5.600 13.900 5.600 13.900 5.200 6.700

DBINHA S D
S = FFFFFFFFH 5.600 13.900 5.600 13.900 5.600 13.900 5.100 6.500

S =1 4.850 13.200 4.850 13.200 4.850 13.200 4.300 5.800

BCDDA S D
S = 9999 5.300 13.600 5.300 13.600 5.300 13.600 4.700 6.100

S =1 5.300 13.600 5.300 13.600 5.300 13.600 4.800 6.300

DBCDDA S D
S = 99999999 6.200 14.500 6.200 14.500 6.200 14.500 5.600 7.100

S =1 7.000 18.500 7.000 18.500 7.000 18.500 6.500 9.000

DABIN S D
S = -32768 6.950 18.500 6.950 18.500 6.950 18.500 6.300 8.900

S =1 9.450 21.000 9.450 21.000 9.450 21.000 9.400 12.000

DDABIN S D
S = -2147483648 9.450 21.000 9.450 21.000 9.450 21.000 9.100 11.600

Application S =1 5.650 17.100 5.650 17.100 5.650 17.100 4.900 7.500

instruction HABIN S D
S = FFFFH 5.750 17.300 5.750 17.300 5.750 17.300 5.100 8.100

S =1 6.800 18.200 6.800 18.200 6.800 18.200 6.000 8.500

DHABIN S D
S = FFFFFFFFH 7.100 18.600 7.100 18.600 7.100 18.600 6.300 8.900

S =1 5.650 17.200 5.650 17.200 5.650 17.200 5.000 7.500

DABCD S D
S = 9999 5.700 17.200 5.700 17.200 5.700 17.200 5.000 7.500

S =1 6.850 18.300 6.850 18.300 6.850 18.300 6.200 8.800

DDABCD S D
S = 99999999 6.850 18.300 6.850 18.300 6.850 18.300 6.200 8.800

COMRD –– 185.000 188.000 185.000 188.000 185.000 188.000 97.300 97.400

1 character 4.700 16.200 4.700 16.200 4.700 16.200 4.100 6.600
LEN
96 characters 20.600 32.900 20.600 32.900 20.600 32.900 19.800 22.400
STR –– 9.800 36.500 9.800 36.500 9.800 36.500 6.900 14.400
DSTR –– 12.100 40.400 12.100 40.400 12.100 40.400 10.200 20.800
VAL –– 12.200 40.900 12.200 40.900 12.200 40.900 9.800 23.900
DVAL –– 19.400 45.600 19.400 45.600 19.400 45.600 14.000 33.100
ESTR –– 29.700 87.800 29.700 87.800 29.700 87.800 22.100 52.400

App-76
 Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
Min. Max. Min. Max. Min. Max. Min. Max.
8
Decimal point format
23.900 70.400 23.900 70.400 23.900 70.400 23.300 36.500
all 2-digit specification
EVAL
Exponent format
23.700 70.300 23.700 70.300 23.700 70.300 23.300 36.400
8
all 6-digit specification
n=1 10.200 41.800 10.200 41.800 10.200 41.800 5.600 19.700
ASC S n
8
D
n = 96 31.900 66.600 31.900 66.600 31.900 66.600 30.200 44.700
n=1 8.600 43.400 8.600 43.400 8.600 43.400 7.500 23.100
HEX S D n
n = 96 77.100 115.000 77.100 115.000 77.100 115.000 37.500 53.300

RIGHT S D n
n=1 10.900 29.600 10.900 29.600 10.900 29.600 7.600 11.400 8
n = 96 41.400 60.300 41.400 60.300 41.400 60.300 36.300 46.000
n=1 10.600 29.300 10.600 29.300 10.600 29.300 6.500 16.100
LEFT S n
A
D
n = 96 41.300 60.200 41.300 60.200 41.300 60.200 36.200 46.200
MIDR –– 11.700 30.600 11.700 30.600 11.700 30.600 9.500 19.100
MIDW –– 12.400 24.000 12.400 24.000 12.400 24.000 10.300 18.200
No match 22.000 38.200 22.000 38.200 22.000 38.200 19.300 29.000 6
INSTR Head 13.300 29.600 13.300 29.600 13.300 29.600 10.300 20.000
Match
End 21.900 38.100 21.900 38.100 21.900 38.100 51.100 60.800
EMOD –– 11.600 24.000 11.600 24.000 11.600 24.000 10.300 15.300 7
EREXP –– 19.700 28.000 19.700 28.000 19.700 28.000 19.300 22.300

S = 128 / D = 40 /
47.000 102.000 47.000 102.000 47.000 102.000 44.300 96.700
n=1 8
STRINS S D n
S = 128 / D = 40 /
70.100 134.000 70.100 134.000 70.100 134.000 58.800 112.000
n = 48

Application S = 128 / D = 40 /
46.400 93.600 46.400 93.600 46.400 93.600 39.000 78.100

Appendix 1.4 Operation Processing Time of Universal Model QCPU

Appendix1 OPERATION PROCESSING TIME
instruction
n=1
STRDEL S D n
S = 128 / D = 40 /
44.500 70.600 44.500 70.600 44.500 70.600 36.000 69.200
n = 48
SIN Single precision 6.400 13.900 6.400 13.900 6.400 13.900 4.500 9.900
COS Single precision 6.100 13.500 6.100 13.500 6.100 13.500 4.300 8.200
TAN Single precision 8.300 15.000 8.300 15.000 8.300 15.000 5.100 7.200
ASIN Single precision 7.300 15.600 7.300 15.600 7.300 15.600 6.100 13.700
ACOS Single precision 8.100 16.500 8.100 16.500 8.100 16.500 6.800 11.100
ATAN Single precision 5.350 12.000 5.350 12.000 5.350 12.000 4.000 6.900
SIND Double precision 13.400 51.300 13.400 51.300 13.400 51.300 9.600 26.000
COSD Double precision 14.700 51.700 14.700 51.700 14.700 51.700 10.000 26.900
TAND Double precision 17.400 54.400 17.400 54.400 17.400 54.400 11.400 25.300
ASIND Double precision 22.600 60.300 22.600 60.300 22.600 60.300 12.100 30.800
ACOSD Double precision 19.700 60.000 19.700 60.000 19.700 60.000 11.700 28.000
ATAND Double precision 15.000 51.800 15.000 51.800 15.000 51.800 9.700 22.000
RAD Single precision 3.200 10.300 3.200 10.300 3.200 10.300 2.500 4.800
RADD Double precision 5.200 43.100 5.200 43.100 5.200 43.100 4.100 16.400
DEG Single precision 3.200 11.500 3.200 11.500 3.200 11.500 2.500 4.700
DEGD Double precision 5.150 43.800 5.150 43.800 5.150 43.800 5.000 18.100
SQR Single precision 3.900 12.300 3.900 12.300 3.900 12.300 3.500 9.300
SQRD Double precision 7.000 45.700 7.000 45.700 7.000 45.700 5.700 25.400

Single S = -10 6.350 13.800 6.350 13.800 6.350 13.800 4.000 13.000
EXP S D
precision 6.350 13.800 6.350 13.800 6.350 13.800 4.000 13.000
S =1

App-77
 Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
Min. Max. Min. Max. Min. Max. Min. Max.

Double S = -10 15.800 52.700 15.800 52.700 15.800 52.700 8.800 27.600
EXPD S D
precision 15.400 52.500 15.400 52.500 15.400 52.500 8.500 27.300
S =1

Single S =1 5.800 14.900 5.800 14.900 5.800 14.900 4.100 8.100

LOG S D
precision 7.450 16.500 7.450 16.500 7.450 16.500 6.200 10.300
S = 10

Double S =1 11.000 48.900 11.000 48.900 11.000 48.900 9.500 28.300

LOGD S D
precision 12.600 51.300 12.600 51.300 12.600 51.300 11.100 29.900
S = 10
RND –– 1.950 5.450 1.950 5.450 1.950 5.450 1.200 2.300
SRND –– 2.750 4.550 2.750 4.550 2.750 4.550 1.400 2.400

S =0 2.500 6.800 2.500 6.800 2.500 6.800 1.800 3.300

BSQR S D
S = 9999 6.400 15.500 6.400 15.500 6.400 15.500 5.100 8.800

S =0 2.600 6.050 2.600 6.050 2.600 6.050 1.900 3.700

BDSQR S D
S = 99999999 8.450 17.600 8.450 17.600 8.450 17.600 7.500 10.900

BSIN –– 11.500 32.800 11.500 32.800 11.500 32.800 8.700 20.200

Application BCOS –– 10.400 32.500 10.400 32.500 10.400 32.500 7.800 14.400
instruction
BTAN –– 12.100 33.700 12.100 33.700 12.100 33.700 9.000 17.000
BASIN –– 13.300 32.800 13.300 32.800 13.300 32.800 12.200 15.100
BACOS –– 13.400 33.700 13.400 33.700 13.400 33.700 13.100 14.900
BATAN –– 12.600 31.400 12.600 31.400 12.600 31.400 11.400 15.700

Single S1 = 12.3 E + 5
POW S1 S2 D 12.200 22.100 12.200 22.100 12.200 22.100 8.950 19.500
precision S2 = 3.45 E + 0

Double S1 = 12.3 E + 5
POWD S1 S2 D 27.300 61.000 27.300 61.000 27.300 61.000 19.400 55.200
precision S2 = 3.45 E + 0
LOG10 Single precision 8.200 16.500 8.200 16.500 8.200 16.500 5.950 14.800
LOG10D Double precision 15.100 48.000 15.100 48.000 15.100 48.000 12.400 46.500
LIMIT –– 5.350 5.500 5.350 5.500 5.350 5.500 5.200 5.400
DLIMIT –– 6.000 6.150 6.000 6.150 6.000 6.150 5.700 5.900
BAND –– 5.450 12.400 5.450 12.400 5.450 12.400 5.400 6.300
DBAND –– 6.050 11.900 6.050 11.900 6.050 11.900 5.800 6.900
ZONE –– 6.250 10.700 6.250 10.700 6.250 10.700 5.200 11.100
DZONE –– 6.000 11.900 6.000 11.900 6.000 11.900 5.700 10.800

App-78
 Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU 8
Min. Max. Min. Max. Min. Max. Min. Max.
Point No.1

< S1 < 14.900 50.100 14.900 50.100 14.900 50.100 14.700 48.000
8
SM750 Point No.2
= ON Point No.9

< S1 <
Point No.10
15.800 50.900 15.800 50.900 15.800 50.900 19.600 50.400
8
SCL S1 S2 D
Point No.1

< S1 < 13.900 53.100 13.900 53.100 13.900 53.100 13.700 51.000
SM750 Point No.2 8
= OFF Point No.9

< S1 < 16.600 56.600 16.600 56.600 16.600 56.600 20.400 56.200
Point No.10 A
Point No.1

< S1 < 13.400 52.400 13.400 52.400 13.400 52.400 12.800 50.300
SM750 Point No.2 6
= ON Point No.9

< S1 < 14.200 54.100 14.200 54.100 14.200 54.100 17.300 53.500

DSCL S1 S2 D
Point No.10
7
Point No.1

< S1 < 12.300 53.200 12.300 53.200 12.300 53.200 11.500 51.100
Point No.2
SM750
= OFF Point No.9
8
< S1 < 15.000 57.600 15.000 57.600 15.000 57.600 18.100 57.100
Application Point No.10
instruction Point No.1
14.200 53.300 14.200 53.300 14.200 53.300 13.200 51.200

Appendix 1.4 Operation Processing Time of Universal Model QCPU

Appendix1 OPERATION PROCESSING TIME
< S1 <
SM750 Point No.2
= ON Point No.9

< S1 < 14.900 55.000 14.900 55.000 14.900 55.000 18.000 54.500
Point No.10
SCL2 S1 S2 D
Point No.1

< S1 < 15.000 53.500 15.000 53.500 15.000 53.500 14.000 51.300
SM750 Point No.2
= OFF Point No.9

< S1 < 16.300 56.400 16.300 56.400 16.300 56.400 19.300 55.800
Point No.10
Point No.1

< S1 < 13.400 52.700 13.400 52.700 13.400 52.700 13.100 50.500
SM750 Point No.2
= ON Point No.9

< S1 < 14.200 54.300 14.200 54.300 14.200 54.300 18.100 53.700
Point No.10
DSCL2 S1 S2 D
Point No.1

< S1 < 12.300 53.200 12.300 53.200 12.300 53.200 12.100 51.000
SM750 Point No.2
= OFF Point No.9

< S1 < 15.000 57.600 15.000 57.600 15.000 57.600 18.900 57.100
Point No.10

App-79
 Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
Min. Max. Min. Max. Min. Max. Min. Max.
Standard RAM 6.800 26.900 6.800 26.900 6.800 26.900 3.000 16.400
RSET
SRAM card –– –– –– –– –– –– 3.000 16.400
SRAM card to standard RAM –– –– –– –– –– –– 230.000 327.000
QDRSET
Standard RAM to SRAM card –– –– –– –– –– –– 997.000 1066.000
SRAM card to standard ROM –– –– –– –– –– –– 525.000 690.000
QCDSET
Standard ROM to SRAM card –– –– –– –– –– –– 490.000 655.000
DATERD –– 5.600 27.800 5.600 27.800 5.600 27.800 5.100 14.700
DATEWR –– 7.800 42.100 7.800 42.100 7.800 42.100 7.100 23.000
No digit increase 14.200 41.200 14.200 41.200 14.200 41.200 6.500 13.100
DATE +
Digit increase 14.200 41.200 14.200 41.200 14.200 41.200 5.700 21.200
No digit increase 15.100 41.200 15.100 41.200 15.100 41.200 6.500 11.500
DATE -
Digit increase 15.100 41.200 15.100 41.200 15.100 41.200 5.700 17.200
SECOND –– 5.800 20.500 5.800 20.500 5.800 20.500 2.600 5.900
HOUR –– 6.200 22.500 6.200 22.500 6.200 22.500 3.000 5.300
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.400 23.400
status
of specified
In nonconductive
date 8.200 25.500 8.200 25.500 6.500 25.500 8.200 25.500
status
LDDT =
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.200
status
of current
In nonconductive
date 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.200
status
When not executed 0.480 0.320 0.240 0.160
Application
In conductive
instruction Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.200 23.400
status
of specified
In nonconductive
date 8.200 25.500 8.200 25.500 6.500 25.500 7.200 23.400
ANDDT= status
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.200
status
of current
In nonconductive
date 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.200
status
When not executed 0.480 0.320 0.240 0.160
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.400 23.300
status
of specified
In nonconductive
date 8.200 25.500 8.200 25.500 6.500 25.500 7.400 23.300
ORDT= status
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.000
status
of current
In nonconductive
date 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.000
status
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.400 23.400
status
of specified
In nonconductive
date 8.200 25.500 8.200 25.500 6.500 25.500 7.400 23.400
status
LDDT <>
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.200
status
of current
In nonconductive
date 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.200
status

App-80
 Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU 8
Min. Max. Min. Max. Min. Max. Min. Max.
When not executed 0.480 0.320 0.240 0.160

Comparison
In conductive
8.200 25.500 8.200 25.500 6.500 25.500 7.200 23.400 8
status
of specified
In nonconductive
date 8.200 25.500 8.200 25.500 6.500 25.500 7.200 23.400
ANDDT<> status
In conductive
8
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.200
status
of current
In nonconductive
date
status
6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.200
8
When not executed 0.480 0.320 0.240 0.160
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.400 23.300
of specified
status A
In nonconductive
date 8.200 25.500 8.200 25.500 6.500 25.500 7.400 23.300
ORDT<> status

Comparison
In conductive
status
6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.000 6
of current
In nonconductive
date 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.000
status
In conductive 7
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.400 23.400
status
of specified
In nonconductive
date
LDDT>
status
8.200 25.500 8.200 25.500 6.500 25.500 7.400 23.400
8
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.200
status
of current
In nonconductive
date 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.200
Application status

Appendix 1.4 Operation Processing Time of Universal Model QCPU

Appendix1 OPERATION PROCESSING TIME
instruction When not executed 0.480 0.320 0.240 0.160

In conductive
Comparison 8.200 25.500 8.200 25.500 8.200 25.500 7.200 23.400
status
of specified
In nonconductive
date 8.200 25.500 8.200 25.500 8.200 25.500 7.200 23.400
ANDDT> status
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.200
status
of current
In nonconductive
date 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.200
status
When not executed 0.480 0.320 0.240 0.160
In conductive
Comparison 8.200 25.500 8.200 25.500 8.200 25.500 7.400 23.300
status
of specified
In nonconductive
date 8.200 25.500 8.200 25.500 8.200 25.500 7.400 23.300
ORDT> status
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.000
status
of current
In nonconductive
date 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.000
status
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.400 23.400
status
of specified
In nonconductive
date 8.200 25.500 8.200 25.500 6.500 25.500 7.400 23.400
status
LDDT<=
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.200
status
of current
In nonconductive
date 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.200
status

App-81
 Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
Min. Max. Min. Max. Min. Max. Min. Max.
When not executed 0.480 0.320 0.240 0.160
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.200 23.400
status
of specified
In nonconductive
date 8.200 25.500 8.200 25.500 6.500 25.500 7.200 23.400
ANDDT<= status
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.200
status
of current
In nonconductive
date 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.200
status
When not executed 0.480 0.320 0.240 0.160
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.400 23.300
status
of specified
In nonconductive
date 8.200 25.500 8.200 25.500 6.500 25.500 7.400 23.300
ORDT<= status
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.000
status
of current
In nonconductive
date 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.000
status
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.400 23.400
status
of specified
In nonconductive
date 8.200 25.500 8.200 25.500 6.500 25.500 7.400 23.400
status
LDDT<
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.200
status
of current
In nonconductive
date 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.200
Application status
instruction When not executed 0.480 0.320 0.240 0.160
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.200 23.400
status
of specified
In nonconductive
date 8.200 25.500 8.200 25.500 6.500 25.500 7.200 23.400
ANDDT< status
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.200
status
of current
In nonconductive
date 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.200
status
When not executed 0.480 0.320 0.240 0.160
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.400 23.300
status
of specified
In nonconductive
date 8.200 25.500 8.200 25.500 6.500 25.500 7.400 23.300
ORDT< status
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.000
status
of current
In nonconductive
date 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.000
status
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.400 23.400
status
of specified
In nonconductive
date 8.200 25.500 8.200 25.500 6.500 25.500 7.400 23.400
status
LDDT>=
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.200
status
of current
In nonconductive
date 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.200
status

App-82
 Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU 8
Min. Max. Min. Max. Min. Max. Min. Max.
When not executed 0.480 0.320 0.240 0.160

Comparison
In conductive
8.200 25.500 8.200 25.500 6.500 25.500 7.200 23.400 8
status
of specified
In nonconductive
date 8.200 25.500 8.200 25.500 6.500 25.500 7.200 23.400
ANDDT>= status
In conductive
8
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.200
status
of current
In nonconductive
date
status
6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.200
8
When not executed 0.480 0.320 0.240 0.160
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.400 23.300
of specified
status A
In nonconductive
date 8.200 25.500 8.200 25.500 6.500 25.500 7.400 23.300
ORDT>= status

Comparison
In conductive
status
6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.000 6
of current
In nonconductive
date 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.000
status
In conductive 7
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.300 23.300
status
of specified
In nonconductive
date 8.200 25.500 8.200 25.500 6.500 25.500 7.300 23.300
LDTM=
status 8
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.100
status
of current
In nonconductive
date 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.100
Application status

Appendix 1.4 Operation Processing Time of Universal Model QCPU

Appendix1 OPERATION PROCESSING TIME
instruction When not executed 0.480 0.320 0.240 0.160
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.000 23.000
status
of specified
In nonconductive
clock 8.200 25.500 8.200 25.500 6.500 25.500 7.000 23.000
ANDTM= status
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.600 21.900
status
of current
In nonconductive
clock 6.500 23.100 6.500 23.100 6.500 23.100 5.600 21.900
status
When not executed 0.480 0.320 0.240 0.160
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.300 23.200
status
of specified
In nonconductive
clock 8.200 25.500 8.200 25.500 6.500 25.500 7.300 23.200
ORTM= status
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.000
status
of current
In nonconductive
clock 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.000
status
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.300 23.300
status
of specified
In nonconductive
clock 8.200 25.500 8.200 25.500 6.500 25.500 7.300 23.300
status
LDTM<>
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.100
status
of current
In nonconductive
clock 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.100
status

App-83
 Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
Min. Max. Min. Max. Min. Max. Min. Max.
When not executed 0.480 0.320 0.240 0.160
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.000 23.000
status
of specified
In nonconductive
clock 8.200 25.500 8.200 25.500 6.500 25.500 7.000 23.000
ANDTM<> status
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.600 21.900
status
of current
In nonconductive
clock 6.500 23.100 6.500 23.100 6.500 23.100 5.600 21.900
status
When not executed 0.480 0.320 0.240 0.160
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.300 23.200
status
of specified
In nonconductive
clock 8.200 25.500 8.200 25.500 6.500 25.500 7.300 23.200
ORTM<> status
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.000
status
of current
In nonconductive
clock 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.000
status
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.300 23.300
status
of specified
In nonconductive
clock 8.200 25.500 8.200 25.500 6.500 25.500 7.300 23.300
status
LDTM>
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.100
status
of current
In nonconductive
clock 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.100
Application status
instruction When not executed 0.480 0.320 0.240 0.160
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.000 23.000
status
of specified
In nonconductive
clock 8.200 25.500 8.200 25.500 6.500 25.500 7.000 23.000
ANDTM> status
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.600 21.900
status
of current
In nonconductive
clock 6.500 23.100 6.500 23.100 6.500 23.100 5.600 21.900
status
When not executed 0.480 0.320 0.240 0.160
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.300 23.200
status
of specified
In nonconductive
clock 8.200 25.500 8.200 25.500 6.500 25.500 7.300 23.200
ORTM> status
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.000
status
of current
In nonconductive
clock 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.000
status
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.300 23.300
status
of specified
In nonconductive
clock 8.200 25.500 8.200 25.500 6.500 25.500 7.300 23.300
status
LDTM<=
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.100
status
of current
In nonconductive
clock 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.100
status

App-84
 Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU 8
Min. Max. Min. Max. Min. Max. Min. Max.
When not executed 0.480 0.320 0.240 0.160

Comparison
In conductive
8.200 25.500 8.200 25.500 6.500 25.500 7.000 23.000 8
status
of specified
In nonconductive
clock 8.200 25.500 8.200 25.500 6.500 25.500 7.000 23.000
ANDTM<= status
In conductive
8
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.600 21.900
status
of current
In nonconductive
clock
status
6.500 23.100 6.500 23.100 6.500 23.100 5.600 21.900
8
When not executed 0.480 0.320 0.240 0.160
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.300 23.200
of specified
status A
In nonconductive
clock 8.200 25.500 8.200 25.500 6.500 25.500 7.300 23.200
ORTM<= status

Comparison
In conductive
status
6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.000 6
of current
In nonconductive
clock 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.000
status
In conductive 7
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.300 23.300
status
of specified
In nonconductive
clock 8.200 25.500 8.200 25.500 6.500 25.500 7.300 23.300
LDTM<
status 8
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.100
status
of current
In nonconductive
clock 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.100
Application status

Appendix 1.4 Operation Processing Time of Universal Model QCPU

Appendix1 OPERATION PROCESSING TIME
instruction When not executed 0.480 0.320 0.240 0.160
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.000 23.000
status
of specified
In nonconductive
clock 8.200 25.500 8.200 25.500 6.500 25.500 7.000 23.000
ANDTM< status
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.600 21.900
status
of current
In nonconductive
clock 6.500 23.100 6.500 23.100 6.500 23.100 5.600 21.900
status
When not executed 0.480 0.320 0.240 0.160
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.300 23.200
status
of specified
In nonconductive
clock 8.200 25.500 8.200 25.500 6.500 25.500 7.300 23.200
ORTM< status
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.000
status
of current
In nonconductive
clock 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.000
status
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.300 23.300
status
of specified
In nonconductive
clock 8.200 25.500 8.200 25.500 6.500 25.500 7.300 23.300
status
LDTM>=
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.100
status
of current
In nonconductive
clock 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.100
status

App-85
 Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
Min. Max. Min. Max. Min. Max. Min. Max.
When not executed 0.480 0.320 0.240 0.160
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.000 23.000
status
of specified
In nonconductive
clock 8.200 25.500 8.200 25.500 6.500 25.500 7.000 23.000
ANDTM>= status
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.600 21.900
status
of current
In nonconductive
clock 6.500 23.100 6.500 23.100 6.500 23.100 5.600 21.900
status
When not executed 0.480 0.320 0.240 0.160
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.000 23.000
status
of specified
In nonconductive
clock 8.200 25.500 8.200 25.500 6.500 25.500 7.000 23.000
ORTM>= status
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.100
status
of current
In nonconductive
clock 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.100
status
Application
instruction S.DATERD –– 9.250 51.000 9.250 51.000 9.250 51.000 7.500 23.400
No digit increase 16.800 75.400 16.800 75.400 16.800 75.400 9.100 23.400
S.DATE +
Digit increase 16.800 75.400 16.800 75.400 16.800 75.400 8.900 22.200
No digit increase 17.600 75.300 17.600 75.300 17.600 75.300 9.000 22.200
S.DATE -
Digit increase 16.900 75.300 16.900 75.300 16.900 75.300 9.800 22.100
PSTOP –– 82.200 199.000 82.200 199.000 82.200 199.000 61.400 84.500
POFF –– 82.600 198.000 82.600 198.000 82.600 198.000 121.000 246.000
PSCAN –– 83.600 200.000 83.600 200.000 83.600 200.000 126.000 232.000
WDT –– 2.900 12.000 2.900 12.000 2.900 12.000 1.300 3.000
DUTY –– 7.700 27.500 7.700 27.500 7.700 27.500 4.900 24.300
TIMCHK –– 5.350 24.500 5.350 24.500 5.350 24.500 7.400 23.300
File register of standard RAM 4.100 4.200 4.100 4.200 4.100 4.200 2.400 2.600
ZRRDB
File register of SRAM card –– –– –– –– –– –– 2.500 2.800
File register of standard RAM 5.400 5.500 5.400 5.500 5.400 5.500 3.100 3.300
ZRWRB
File register of SRAM card –– –– –– –– –– –– 3.300 3.600
ADRSET –– 2.400 6.650 2.400 6.650 2.400 6.650 4.200 4.900
ZPUSH –– 9.200 20.500 9.200 20.500 9.200 20.500 6.900 14.000
ZPOP –– 9.000 15.500 9.000 15.500 9.000 15.500 7.500 12.500

App-86
 Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU 8
Min. Max. Min. Max. Min. Max. Min. Max.
When mounting CC-Link
module
(Master station side)
29.400 91.700 29.400 91.700 29.400 91.700 20.600 55.000
8
When mounting CC-Link
module 29.500 91.600 29.500 91.600 29.500 91.600 20.600 66.100
(Local station side) 8
When mounting
MELSECNET/H,
S.ZCOM
CC-Link IEcontroller 79.900 214.000 79.900 214.000 79.900 214.000 102.000 180.000 8
network module(Control
station side)
When mounting
MELSECNET/H,
A
CC-Link IEcontroller 79.900 214.000 79.900 214.000 79.900 214.000 29.800 102.000
network module(Normal
station side) 6
Application S.RTREAD –– 9.200 57.700 9.200 57.700 9.200 57.700 6.700 33.500
instruction S.RTWRITE –– 10.900 67.100 10.900 67.100 10.900 67.100 8.300 26.000

UNIRD n1 D n2
n2 = 1 6.000 33.100 6.000 33.100 6.000 33.100 4.000 29.100
7
n2 = 16 16.500 43.600 16.500 43.600 16.500 43.600 12.500 37.600
TYPERD 48.50 141.30 43.50 139.90 43.40 139.80 32.40 134.20
TRACE
TRACER
Start
––
174.000
5.100
174.000
15.500
174.000
5.100
174.000
15.500
174.000
5.100
174.000
15.500
96.600
3.800
103.000
13.600
8
1 point –– –– 12.200 34.900 12.200 34.900 9.400 31.300
When standard
1000
RAM is used –– –– 121.500 145.100 121.500 145.100 118.500 141.300
points
RBNOV S D n
1 point –– –– –– –– –– –– 9.400 31.400

Appendix 1.4 Operation Processing Time of Universal Model QCPU

Appendix1 OPERATION PROCESSING TIME
When SRAM
1000
card is used –– –– –– –– –– –– 178.500 201.300
points
SP.FWRITE –– –– –– –– –– –– –– 9.200 12.100
SP.FREAD –– –– –– –– –– –– –– 489.000 544.000
SP.DEVST –– –– –– –– –– –– –– 87.000 144.000
S.DEVLD –– –– –– –– –– –– –– 127.000 140.000

App-87
 Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
Min. Max. Min. Max. Min. Max. Min. Max.
Writing to host n4 = 1 64.600 78.100 64.600 78.100 64.600 78.100 64.600 78.100

S.TO n1 n2 n3 n4 D CPU shared

n4 = 320 115.000 126.000 115.000 126.000 115.000 126.000 154.000 126.000
memory
Writing to host n3 = 1 12.700 62.200 12.700 62.200 12.700 62.200 8.300 58.200

TO n1 n2 S n3 CPU shared
n3 = 320 63.500 112.300 63.500 112.300 63.500 112.300 56.200 107.800
memory
Writing to host n3 = 1 13.500 62.300 13.500 62.300 13.500 62.300 8.600 58.300

DTO n1 n2 S n3 CPU shared

n3 = 320 112.900 160.800 112.900 160.800 112.900 160.800 106.800 157.300
memory
Multiple Reading from n3 = 1 12.100 58.700 12.100 58.700 12.100 58.700 8.400 52.600
CPU host CPU shared
dedicated n3 = 320 56.000 101.700 56.000 101.700 56.000 101.700 51.700 96.600
memory
instruction FROM n1 n2 D n3
Reading from n3 = 1 24.400 82.900 24.400 82.900 24.400 82.900 16.600 37.000
other CPU n3 = 320 152.000 243.000 152.000 243.000 152.000 243.000 153.000 185.000
shared memory n3 = 1000 418.000 518.000 418.000 518.000 418.000 518.000 432.000 485.000
Reading from n3 = 1 12.100 58.700 12.100 58.700 12.100 58.700 8.800 53.400
host CPU shared
n3 = 320 97.400 143.700 97.400 143.700 97.400 143.700 94.900 139.600
memory
DFRO n1 n2 D n3 n3 = 1 24.800 94.200 24.800 94.200 24.800 94.200 16.600 47.300
Reading from
other CPU n3 = 320 276.000 367.000 276.000 367.000 276.000 367.000 278.000 339.000
shared memory n3 = 1000 799.000 892.000 799.000 892.000 799.000 892.000 841.000 892.000

Remark
For the instructions for which a rise execution instruction ( P) is not specified,
the processing time is the same as an ON execution instruction.
Example WORDP instruction and TOP instruction

App-88
 (b) When using Q03UD(E)JCPU, Q04UD(E)HCPU, Q06UD(E)HCPU,
Q10UD(E)HCPU, Q13UD(E)HCPU, Q20UD(E)HCPU and Q26UD(E)HCPU
Processing Time (µs)
8
Q10/Q13/Q20/
Category Instruction Condition (Device) Q03UD(E)CPU Q04/Q06UD(E)HCPU
Q26UD(E)HCPU
Min. Max. Min. Max. Min. Max. 8
ANB
ORB
MPS
MRD
–– 0.020 0.0095 0.0095
8
MPP
When not executed
INV
When executed
0.020 0.0095 0.0095 8
MEP When not executed
0.020 0.0095 0.0095
MEF When executed
EGP When not executed
A
0.020 0.0095 0.0095
EGF When executed
PLS –– 1.300 1.600 0.890 1.100 0.890 1.100

Sequence PLF –– 1.500 1.600 0.940 1.200 0.940 1.200 6

instruction When not executed 0.040 0.0185 0.0185
FF
When executed 1.200 1.500 0.790 0.910 0.790 0.910
When not executed 0.040 0.0185 0.0185 7
DELTA
When executed 2.800 3.600 2.400 3.200 2.400 3.200
When not executed 0.040 0.0185 0.0185
SFT
When executed 1.600 3.300 1.100 2.700 1.100 2.700 8
MC –– 0.040 0.0185 0.0185
MCR –– 0.040 0.0185 0.0185
FEND Error check performed 108.000 130.000 75.800 89.300 75.800 89.300
END No error check performed 107.000 124.000 75.800 89.800 75.800 89.800

Appendix 1.4 Operation Processing Time of Universal Model QCPU

Appendix1 OPERATION PROCESSING TIME
NOP
NOPLF –– 0.020 0.0095 0.0095
PAGE

App-89
 Processing Time (µs)
Q04/ Q10/Q13/Q20/
Category Instruction Condition (Device) Q03UD(E)CPU
Q06UD(E)HCPU Q26UD(E)HCPU
Min. Max. Min. Max. Min. Max.
Single In conductive status 3.700 4.700 3.300 4.300 3.300 4.300
LDE=
precision In non-conductive status
3.800 5.000 3.400 4.500 3.400 4.500
When not executed
Single
ANDE= When In conductive status 0.060 0.0285 0.0285
precision
executed In non-conductive status 3.300 5.800 3.000 5.100 3.000 5.100
When not executed 3.500 5.600 3.000 5.200 3.000 5.200
Single
ORE= When In conductive status 0.060 0.0285
precision
executed In non-conductive status 3.600 4.500 3.200 4.200 0.0285
Single In conductive status 3.500 4.800 3.200 4.300
LDE< >
precision In non-conductive status 4.000 4.700 3.600 4.200
0.0285
When not executed 3.900 4.500 3.500 4.000
Single
ANDE< > When In conductive status 0.060 0.0285
precision
executed In non-conductive status 3.300 5.100 3.000 4.800 0.0285
When not executed 3.500 5.000 3.100 4.600
Single
ORE< > When In conductive status 0.060 0.0285
precision
executed In non-conductive status 3.600 6.000 3.300 5.500 0.0285
Single In conductive status 3.500 5.800 3.100 5.300
LDE>
precision In non-conductive status 3.800 5.000 3.300 4.600
0.0285
When not executed 3.700 4.900 3.300 4.400
Single
Basic ANDE> When In conductive status 0.060 0.0285
precision
instruction executed In non-conductive status 3.500 4.700 3.100 4.200 0.0285
When not executed 3.600 4.500 3.100 4.000
Single
ORE> When In conductive status 0.060 0.0285
precision
executed In non-conductive status 3.600 5.100 3.300 4.600 0.0285
Single In conductive status 3.500 4.800 3.200 4.500
LDE<=
precision In non-conductive status 3.800 5.600 3.400 5.200
0.0285
When not executed 3.800 5.600 3.400 5.100
Single
ANDE<= When In conductive status 0.060 0.0285
precision
executed In non-conductive status 3.200 4.600 2.800 4.200 0.0285
When not executed 3.500 5.000 3.100 4.500
Single
ORE<= When In conductive status 0.060 0.0285
precision
executed In non-conductive status 3.700 5.800 3.400 5.400 0.0285
Single In conductive status 3.800 5.700 3.300 5.300
LDE<
precision In non-conductive status 4.000 5.400 3.500 4.900
0.0285
When not executed 4.000 5.200 3.500 4.900
Single
ANDE< When In conductive status 0.060 0.0285
precision
executed In non-conductive status 3.400 4.600 3.000 4.200 0.0285
When not executed 3.500 4.900 3.100 4.400
Single
ORE< When In conductive status 0.060 0.0285
precision 0.0285
executed In non-conductive status 3.600 5.200 3.300 4.900

App-90
 Processing Time (µs)
Q04/ Q10/Q13/Q20/
Category Instruction Condition (Device) Q03UD(E)CPU
Q06UD(E)HCPU Q26UD(E)HCPU 8
Min. Max. Min. Max. Min. Max.

Single In conductive status 3.800 6.000 3.300 5.500

LDE>=
precision In non-conductive status 3.800 5.900 3.400 5.400
0.0285
8
When not executed 0.060 0.0285
Single
ANDE>= When In conductive status 3.200 4.800 2.900 4.600 0.0285
precision
executed In non-conductive status 3.500 5.400 3.100 5.100 8
When not executed 0.060 0.0285
Single
ORE>= When In conductive status 3.600 5.200 3.300 4.700 0.0285
precision
executed In non-conductive status 3.500 5.200 3.200 4.700 8
Double In conductive status 4.100 7.700 3.500 7.200 3.500 7.200
LDED=
precision In non-conductive status
When not executed
4.300 8.100 3.800 7.400 3.800 7.400
A
Double
ANDED= When In conductive status 0.060 0.0285 0.0285
precision
executed In non-conductive status 3.600 7.600 3.200 7.000 3.200 7.000
When not executed 3.900 7.700 3.400 7.400 3.400 7.400 6
Double
ORED= When In conductive status 0.060 0.0285 0.0285
precision
executed In non-conductive status 3.800 8.800 3.400 8.300 3.400 8.300

LDED<>
Double In conductive status 4.000 9.300 3.700 8.800 3.700 8.800 7
precision In non-conductive status 4.400 8.200 3.900 7.700 3.900 7.700
When not executed
4.100 7.900 3.500 7.500 3.500 7.500
Basic ANDED<>
Double
precision
When In conductive status 8
instruction executed In non-conductive status 0.060 0.0285 0.0285
When not executed 3.800 7.600 3.300 7.200 3.300 7.200
Double
ORED<> When In conductive status 3.800 7.700 3.400 7.300 3.400 7.300
precision
executed In non-conductive status 0.060 0.0285 0.0285

Appendix 1.4 Operation Processing Time of Universal Model QCPU

Appendix1 OPERATION PROCESSING TIME
Double In conductive status 4.100 9.300 3.700 8.900 3.700 8.900
LDED>
precision In non-conductive status 3.800 8.900 3.400 8.400 3.400 8.400
When not executed 4.300 8.100 3.800 7.500 3.800 7.500
Double
ANDED> When In conductive status
precision 4.100 7.800 3.500 7.200 3.500 7.200
executed In non-conductive status
When not executed 0.060 0.0285 0.0285
Double
ORED> When In conductive status 3.800 7.700 3.300 7.300 3.300 7.300
precision
executed In non-conductive status 4.000 7.900 3.500 7.500 3.500 7.500
Double In conductive status 0.060 0.0285 0.0285
LDED<=
precision In non-conductive status 4.100 9.300 3.700 8.800 3.700 8.800
When not executed 4.100 9.300 3.700 8.800 3.700 8.800
Double
ANDED<= When In conductive status 4.000 8.000 3.500 7.400 3.500 7.400
precision
executed In non-conductive status
4.100 9.400 3.600 8.800 3.600 8.800
When not executed
Double
ORED<= When In conductive status 0.060 0.0285 0.0285
precision
executed In non-conductive status 3.800 7.700 3.300 7.200 3.300 7.200

App-91
 Processing Time (µs)
Q04/ Q10/Q13/Q20/
Category Instruction Condition (Device) Q03UD(E)CPU
Q06UD(E)HCPU Q26UD(E)HCPU
Min. Max. Min. Max. Min. Max.

Double In conductive status 4.300 8.300 3.800 7.600 3.800 7.600

LDED<
precision In non-conductive status
3.700 7.900 3.500 7.400 3.500 7.400
When not executed
Double
ANDED< When In conductive status 0.060 0.0285 0.0285
precision
executed In non-conductive status 3.800 7.800 3.300 7.300 3.300 7.300
When not executed 3.900 7.900 3.400 3.900 3.400 3.900
Double
ORED< When In conductive status 0.060 0.0285 0.0285
precision
executed In non-conductive status 4.100 9.600 3.700 9.200 3.700 9.200
Double In conductive status 4.000 9.600 3.700 9.200 3.700 9.200
LDED>=
precision In non-conductive status 4.100 9.600 3.600 9.000 3.600 9.000
When not executed
Double 4.100 9.600 3.600 8.900 3.600 8.900
ANDED>= When In conductive status
precision
executed In non-conductive status 0.060 0.0285 0.0285
When not executed 3.800 7.900 3.400 7.400 3.400 7.400
Double
ORED>= When In conductive status 3.900 8.100 3.400 7.500 3.400 7.500
precision
executed In non-conductive status 0.060 0.0285 0.0285
In conductive status 4.100 9.600 3.700 9.200 3.700 9.200
LD$=
In non-conductive status 4.000 7.200 3.600 6.600 3.600 6.600
When not executed 5.300 8.900 4.700 8.100 4.700 8.100
AND$= In conductive status 4.700 9.000 4.200 8.200 4.200 8.200
When executed
In non-conductive status 0.060 0.0285 0.0285
When not executed 4.400 6.800 3.900 6.400 3.900 6.400
Basic
OR$= In conductive status 4.500 6.700 4.000 6.300 4.000 6.300
instruction When executed
In non-conductive status 0.060 0.0285 0.0285
In conductive status 5.100 8.200 4.200 7.600 4.200 7.600
LD$< >
In non-conductive status 5.000 8.100 4.000 7.200 4.000 7.200
When not executed 4.800 8.100 4.300 7.500 4.300 7.500
AND$< > In conductive status 4.700 8.400 4.200 7.800 4.200 7.800
When executed
In non-conductive status 0.060 0.0285 0.0285
When not executed 4.300 5.500 4.100 5.100 4.100 5.100
OR$< > In conductive status 4.500 5.900 4.400 5.400 4.400 5.400
When executed
In non-conductive status 0.060 0.0285 0.0285
In conductive status 5.200 7.300 4.100 6.700 4.100 6.700
LD$>
In non-conductive status 5.100 7.200 4.100 6.700 4.100 6.700
When not executed 4.800 7.200 4.300 6.700 4.300 6.700
AND$> In conductive status 4.800 7.700 4.200 7.100 4.200 7.100
When executed
In non-conductive status 0.060 0.0285 0.0285
When not executed 4.500 7.100 4.000 6.700 4.000 6.700
OR$> In conductive status 4.600 7.600 4.300 7.000 4.300 7.000
When executed
In non-conductive status 0.060 0.0285 0.0285
In conductive status 5.100 6.800 4.300 6.200 4.300 6.200
LD$<=
In non-conductive status 5.200 7.200 4.300 6.600 4.300 6.600
When not executed 5.000 6.300 4.400 5.700 4.400 5.700
AND$<= In conductive status 4.800 6.400 4.200 5.800 4.200 5.800
When executed
In non-conductive status 0.060 0.0285 0.0285

App-92
 Processing Time (µs)
Q04/ Q10/Q13/Q20/
Category Instruction Condition (Device) Q03UD(E)CPU
Q06UD(E)HCPU Q26UD(E)HCPU 8
Min. Max. Min. Max. Min. Max.
When not executed 0.060 0.0285 0.0285
OR$<= When In conductive status 4.700 7.700 4.400 7.200 4.400 7.200 8
executed In non-conductive status 4.600 7.600 4.400 7.100 4.400 7.100
In conductive status 4.800 8.100 4.500 7.500 4.500 7.500
LD$<
In non-conductive status 5.000 8.300 4.500 7.900 4.500 7.900 8
When not executed 0.060 0.0285 0.0285
AND$< When In conductive status 4.500 7.100 4.000 6.600 4.000 6.600
executed In non-conductive status 4.900 7.500 4.400 7.100 4.400 7.100 8
When not executed 0.060 0.0285 0.0285
OR$< When In conductive status 5.100 7.800 4.100 7.200 4.100 7.200
executed In non-conductive status 5.000 8.100 4.100 7.600 4.100 7.600 A
In conductive status 4.800 6.700 4.500 6.200 4.500 6.200
LD$>=
In non-conductive status 5.000 6.700 4.400 6.300 4.400 6.300
When not executed 0.060 0.0285 0.0285 6
AND$>= When In conductive status 4.400 6.800 4.100 6.300 4.100 6.300
executed In non-conductive status 4.500 7.000 4.200 6.600 4.200 6.600
When not executed 0.060 0.0285 0.0285 7
OR$>= When In conductive status 5.400 6.600 4.100 5.800 4.100 5.800
executed In non-conductive status 5.300 6.300 4.100 5.700 4.100 5.700
n=1 8.200 10.700 7.500 10.000 7.500 10.000 8
BKCMP = S1 S2 D n
n = 96 57.400 61.800 46.400 48.700 46.400 48.700
Basic
n=1 8.200 10.700 7.500 10.000 7.500 10.000
instruction BKCMP<> S1 S2 D n
n = 96 59.500 63.300 45.600 50.400 45.600 50.400
n=1 8.200 10.800 7.500 10.100 7.500 10.100

Appendix 1.4 Operation Processing Time of Universal Model QCPU

Appendix1 OPERATION PROCESSING TIME
BKCMP> S1 S2 D n
n = 96 59.500 63.400 47.700 50.500 47.700 50.500
n=1 8.200 10.600 7.500 10.000 7.500 10.000
BKCMP<= S1 S2 D n
n = 96 57.400 61.700 46.400 49.000 46.400 49.000
n=1 8.300 10.600 7.500 10.000 7.500 10.000
BKCMP< S1 S2 D n
n = 96 59.500 63.600 47.600 50.500 47.600 50.500
n=1 8.200 10.900 7.500 10.000 7.500 10.000
BKCMP>= S1 S2 D n
n = 96 57.400 62.000 46.400 48.900 46.400 48.900
n=1 9.250 14.000 8.600 13.000 8.600 13.000
DBKCMP = S1 S2 D n
n = 96 60.700 67.500 47.900 52.800 47.900 52.800
n=1 9.250 14.000 8.600 13.000 8.600 13.000
DBKCMP<> S1 S2 D n
n = 96 60.700 67.500 47.900 52.800 47.900 52.800
n=1 9.250 14.000 8.600 13.000 8.600 13.000
DBKCMP> S1 S2 D n
n = 96 60.700 67.500 47.900 52.800 47.900 52.800
n=1 9.250 14.000 8.600 13.000 8.600 13.000
DBKCMP<= S1 S2 D n
n = 96 60.700 67.500 47.900 52.800 47.900 52.800
n=1 9.250 14.000 8.600 13.000 8.600 13.000
DBKCMP< S1 S2 D n
n = 96 60.700 67.500 47.900 52.800 47.900 52.800
n=1 9.250 14.000 8.600 13.000 8.600 13.000
DBKCMP>= S1 S2 D n
n = 96 60.700 67.500 47.900 52.800 47.900 52.800

App-93
 Processing Time (µs)
Q04/ Q10/Q13/Q20/
Category Instruction Condition (Device) Q03UD(E)CPU
Q06UD(E)HCPU Q26UD(E)HCPU
Min. Max. Min. Max. Min. Max.

DB + S D When executed 4.900 7.000 4.600 6.400 4.600 6.400

DB + S1 S2 D When executed 5.200 7.300 4.800 6.700 4.800 6.700

DB - S D When executed 4.900 6.600 4.700 6.000 4.700 6.000

DB - S1 S2 D When executed 5.200 7.500 4.800 6.600 4.800 6.600

DB * S1 S2 D When executed 8.300 12.100 8.100 11.600 8.100 11.600

DB/ S1 S2 D When executed 6.100 9.100 5.800 8.800 5.800 8.800

Double S = 0, D =0 4.800 8.000 4.300 7.200 4.300 7.200

ED + S D preci-
sion S = 21023, D = 21023 4.800 8.000 4.300 7.200 4.300 7.200

Double S1 = 0, S2 =0 5.500 9.800 4.800 9.200 4.800 9.200

ED + S1 S2 D preci-
sion S1 = 21023, S2 = 21023 5.500 9.800 4.800 9.200 4.800 9.200

Double S = 0, D =0 5.000 8.200 4.400 7.500 4.400 7.500

ED - S D preci-
sion S = 21023, D = 21023 5.000 8.200 4.400 7.500 4.400 7.500

Double S1 = 0, S2 =0 4.400 8.100 3.800 7.500 3.800 7.500

ED - S1 S2 D preci-
sion S1 = 21023, S2 = 21023 4.400 8.100 3.800 7.500 3.800 7.500

Double S1 = 0, S2 =0 5.800 9.500 5.100 8.800 5.100 8.800

ED * S1 S2 D preci-
sion S1 = 21023, S2 = 21023 5.800 9.500 5.100 8.800 5.100 8.800
Basic Double
instruction ED / S1 S2 D preci- S1 = 21023, S2 = 21023 6.600 10.600 5.900 10.000 5.900 10.000
sion
n=1 9.100 11.200 8.500 10.600 8.500 10.600
BK + S1 S2 D n
n = 96 60.700 62.900 44.600 47.000 44.600 47.000
n=1 9.700 12.000 8.900 11.300 8.900 11.300
BK - S1 S2 D n
n = 96 61.300 63.600 45.600 47.900 45.600 47.900
n=1 7.000 10.700 6.450 9.950 6.450 9.950
DBK + S1 S2 D n
n = 96 59.400 63.100 43.700 47.500 43.700 47.500
n=1 7.000 10.700 6.450 9.950 6.450 9.950
DBK - S1 S2 D n
n = 96 59.400 63.100 43.700 47.500 43.700 47.500

$+ S D –– 8.800 14.600 8.100 13.900 8.100 13.900

$ + S1 S2 D –– 7.300 11.100 6.500 10.300 6.500 10.300

Double S =0 2.300 5.000 1.800 4.700 1.800 4.700

FLTD preci-
sion S = 7FFFH 2.500 5.200 2.200 4.800 2.200 4.800

Double S =0 2.400 5.200 2.000 4.900 2.000 4.900

DFLTD preci-
sion S = 7FFFFFFFH 2.700 5.400 2.300 5.100 2.300 5.100

Double S =0 2.700 4.100 2.200 4.100 2.200 4.100

INTD preci-
sion S = 32766.5 3.700 5.900 3.200 5.600 3.200 5.600

Double S =0 2.600 3.900 2.200 3.400 2.200 3.400

DINTD preci-
sion S = 1234567890.3 3.400 5.600 3.000 5.100 3.000 5.100

App-94
 Processing Time (µs)
Q04/ Q10/Q13/Q20/
Category Instruction Condition (Device) Q03UD(E)CPU
Q06UD(E)HCPU Q26UD(E)HCPU 8
Min. Max. Min. Max. Min. Max.
DBL When executed 2.700 3.400 2.300 2.700 2.300 2.700
WORD When executed 2.900 4.300 2.600 3.600 2.600 3.600 8
GRY When executed 2.700 3.900 2.300 3.400 2.300 3.400
DGRY When executed 2.900 3.500 2.500 3.000 2.500 3.000
GBIN When executed 4.000 4.800 3.800 4.300 3.800 4.300 8
DGBIN When executed 5.500 6.100 5.000 5.900 5.000 5.900
NEG When executed 2.400 3.900 2.000 3.300 2.000 3.300
DNEG When executed 2.500 3.700 2.500 3.300 2.500 3.300 8
Floating point = 0 2.500 3.300 2.300 2.800 2.300 2.800
ENEG
Floating point = -1.0 2.700 4.500 2.500 3.900 2.500 3.900
Floating point = 0 2.200 3.500 1.800 3.100 1.800 3.100 A
EDNEG
Floating point = -1.0 2.400 3.500 1.900 3.000 1.900 3.000
n=1 6.600 8.900 5.900 8.200 5.900 8.200
BKBCD S D n
n = 96 71.300 74.100 61.000 63.400 61.000 63.400 6
n=1 6.500 9.800 5.600 9.300 5.600 9.300
BKBIN S D n
n = 96 56.300 59.500 49.200 52.500 49.200 52.500
ECON –– 2.600 5.400 2.100 4.500 2.100 4.500 7
EDCON –– 2.800 5.400 2.500 5.400 2.500 5.400
EDMOV –– 2.300 5.500 1.700 5.000 1.700 5.000
Character string to be
4.000 6.300 3.400 5.600 3.400 5.600
8
transferred = 0
$MOV
Character string to be
Basic 14.600 16.500 11.400 13.300 11.400 13.300
transferred = 32
instruction
n=1 6.200 7.900 5.500 7.300 5.500 7.300

Appendix 1.4 Operation Processing Time of Universal Model QCPU

Appendix1 OPERATION PROCESSING TIME
BXCH D1 D2 n
n = 96 67.000 68.800 47.300 49.300 47.300 49.300
SWAP –– 2.400 2.700 1.900 2.200 1.900 2.200
GOEND –– 0.500 0.500 0.500
DI –– 1.800 2.200 1.500 1.800 1.500 1.800
EI –– 3.100 3.800 3.000 3.300 3.000 3.300
IMASK –– 9.800 13.300 7.200 10.500 7.200 10.500
IRET –– 1.000 1.000 1.000
n=1 4.200 5.900 3.700 5.600 3.700 5.600
RSF X n
n = 96 11.400 13.800 10.700 12.400 10.700 12.400
n=1 3.800 4.800 3.400 4.800 3.400 4.800
RSF Y n
n = 96 8.500 9.500 8.100 8.900 8.100 8.900
UDCNT1 –– 0.900 1.500 0.500 0.983 0.500 0.983
UDCNT2 –– 0.900 1.700 0.600 1.300 0.600 1.300
TTMR –– 3.900 6.100 3.400 5.400 3.400 5.400
STMR –– 6.800 13.500 5.800 12.500 5.800 12.500
ROTC –– 9.000 10.500 8.000 9.400 8.000 9.400
RAMP –– 5.900 8.800 5.200 8.400 5.200 8.400
SPD –– 0.900 1.900 0.500 1.400 0.500 1.400
PLSY –– 1.900 2.200 1.500 1.800 1.500 1.800
PWM –– 1.200 1.600 0.900 1.200 0.900 1.200
MTR –– 10.400 19.800 9.400 10.000 9.400 10.000

App-95
 Processing Time (µs)
Q04/ Q10/Q13/Q20/
Category Instruction Condition (Device) Q03UD(E)CPU
Q06UD(E)HCPU Q26UD(E)HCPU
Min. Max. Min. Max. Min. Max.
n=1 9.000 11.700 8.300 11.000 8.300 11.000
BKAND S1 S2 D n
n = 96 57.400 63.100 43.800 47.300 43.800 47.300
n=1 7.700 10.000 7.700 9.500 7.700 9.500
BKOR S1 S2 D n
n = 96 57.400 61.900 44.300 45.800 44.300 45.800
n=1 7.800 10.100 7.300 9.200 7.300 9.200
BKXOR S1 S2 D n
n = 96 57.300 61.500 43.800 45.800 43.800 45.800
n=1 7.800 9.600 7.600 8.900 7.600 8.900
BKXNR S1 S2 D n
n = 96 57.400 61.400 43.900 45.300 43.900 45.300
n=1 3.700 5.400 3.200 4.800 3.200 4.800
BSFR D n
n = 96 6.900 9.000 5.800 7.700 5.800 7.700
n=1 4.100 5.900 3.400 5.100 3.400 5.100
BSFL D n
n = 96 7.100 9.100 6.000 7.900 6.000 7.900
n1 = 16 / n2 = 1 7.950 17.500 7.600 16.900 7.600 16.900
SFTBR D n1 n2
n1 = 16 / n2 = 15 7.950 17.500 7.550 16.900 7.550 16.900
n1 = 16 / n2 = 1 7.950 17.900 7.500 17.400 7.500 17.400
SFTBL D n1 n2
n1 = 16 / n2 = 15 7.900 17.800 7.500 17.300 7.500 17.300
n1 = 16 / n2 = 1 5.950 10.600 4.600 8.700 4.600 8.700
SFTWR D n1 n2
n1 = 16 / n2 = 15 5.900 10.600 4.600 8.700 4.600 8.700
n1 = 16 / n2 = 1 5.950 10.700 4.550 8.700 4.550 8.700
SFTWL D n1 n2
n1 = 16 / n2 = 15 5.950 10.700 4.600 8.800 4.600 8.800
n=1 3.000 3.400 2.500 2.800 2.500 2.800
BSET D n
n = 15 3.000 3.500 2.500 2.800 2.500 2.800
Application
n=1 3.000 3.400 2.600 2.800 2.600 2.800
instruction
BRST D n
n = 15 3.000 3.400 2.500 2.800 2.500 2.800
TEST When executed 4.400 5.300 3.700 4.700 3.700 4.700
DTEST When executed 4.500 5.400 3.900 4.800 3.900 4.800
n=1 4.300 4.600 3.700 4.100 3.700 4.100
BKRST D n
n = 96 6.000 6.800 5.100 6.000 5.100 6.000
All match 4.900 5.300 4.200 4.600 4.200 4.600
n=1
None match 5.000 5.300 4.200 4.600 4.200 4.600
SER S1 S2 D n
n= All match 32.300 32.900 25.900 26.300 25.900 26.300
96 None match 32.400 32.900 25.900 26.300 25.900 26.300
All match 6.100 6.500 5.400 5.700 5.400 5.700
n=1
None match 6.200 6.600 5.500 5.900 5.500 5.900
DSER S1 S2 D n
n= All match 52.800 54.200 41.200 41.800 41.200 41.800
96 None match 52.800 54.200 41.200 41.800 41.200 41.800

S =0 3.700 4.100 3.300 3.600 3.300 3.600

DSUM S D
S = FFFFFFFFH 3.800 4.100 3.200 3.700 3.200 3.700

n=2 6.000 7.500 5.300 6.900 5.300 6.900

DECO S D n
n=8 8.100 9.300 6.800 7.800 6.800 7.800
M1 = ON 5.300 5.700 4.700 5.100 4.700 5.100
n=2
M4 = ON 5.200 5.700 4.600 5.000 4.600 5.000
ENCO S D n
M1 = ON 10.400 11.400 9.000 10.000 9.000 10.000
n=8
M256 = ON 5.700 6.800 5.100 6.100 5.100 6.100

App-96
 Processing Time (µs)
Q04/ Q10/Q13/Q20/
Category Instruction Condition (Device) Q03UD(E)CPU
Q06UD(E)HCPU Q26UD(E)HCPU 8
Min. Max. Min. Max. Min. Max.
n=1 4.400 5.300 3.800 4.600 3.800 4.600
DIS S D n
n=4 4.800 5.700 4.000 5.000 4.000 5.000 8
n=1 5.000 5.300 3.500 4.800 3.500 4.800
UNI S D n
n=4 5.600 6.000 4.000 5.100 4.000 5.100
NDIS When executed 11.000 13.100 11.000 13.200 11.000 13.200 8
NUNI When executed 10.600 12.700 7.300 13.200 7.300 13.200
n=1 5.000 6.500 4.400 5.800 4.400 5.800
WTOB S D n
n = 96 36.000 38.400 28.200 29.300 28.200 29.300 8
n=1 5.100 6.100 4.600 5.500 4.600 5.500
BTOW S D n
n = 96 29.900 32.000 22.800 23.800 22.800 23.800
n=1 4.300 6.900 4.000 6.100 4.000 6.100 A
MAX S D n
n = 96 31.200 33.500 24.700 27.000 24.700 27.000
n=1 4.400 6.800 4.000 6.000 4.000 6.000
MIN S D n
n = 96 30.300 34.800 26.500 28.300 26.500 28.300 6
n=1 4.800 9.100 4.800 8.100 4.800 8.100
DMAX S D n
n = 96 56.400 62.200 47.100 49.600 47.100 49.600
n=1 4.800 6.800 4.300 5.900 4.300 5.900 7
DMIN S D n
n = 96 55.400 60.200 45.400 47.400 45.400 47.400
n=1 6.200 9.300 5.600 8.800 5.600 8.800
SORT S1 n S2 D1 D2
n = 96 6.200 9.400 5.600 8.600 5.600 8.600 8
n=1 6.200 9.300 5.600 8.200 5.600 8.200
DSORT S1 n S2 D1 D2
n = 96 6.100 9.100 5.600 8.400 5.600 8.400
n=1 4.800 6.200 4.200 5.500 4.200 5.500
Application
WSUM S D n
instruction n = 96 26.900 28.700 21.300 22.300 21.300 22.300

Appendix 1.4 Operation Processing Time of Universal Model QCPU

Appendix1 OPERATION PROCESSING TIME
n=1 5.500 7.000 4.800 6.100 4.800 6.100
DWSUM S D n
n = 96 53.000 56.300 42.700 44.000 42.700 44.000
n=1 4.300 8.650 3.900 7.800 3.900 7.800
MEAN S D n
n = 96 16.000 21.400 12.900 18.000 12.900 18.000
n=1 5.700 10.600 5.300 9.950 5.300 9.950
DMEAN S D n
n = 96 29.200 35.200 23.000 28.800 23.000 28.800
NEXT –– 0.940 1.400 0.770 1.200 0.770 1.200
BREAK –– 10.400 5.500 9.100 5.000 9.100 5.000
Return to original program 2.000 3.000 1.600 2.600 1.600 2.600
RET
Return to other program 2.300 3.700 2.000 3.100 2.000 3.100
Internal file pointer 3.100 4.400 2.700 3.600 2.700 3.600
FCALL Pn
Common pointer 4.000 5.700 3.600 5.100 3.600 5.100

FCALL Pn S1 to S5 –– 19.300 21.500 16.500 18.600 16.500 18.600

ECALL * Pn
–– 70.300 82.300 65.900 77.600 65.900 77.600
*: Program name

ECALL * Pn S1 to S5
–– 101.000 114.000 91.800 105.000 91.800 105.000
*: Program name
EFCALL * Pn
–– 70.700 82.800 66.200 78.100 66.200 78.100
*: Program name

EFCALL * Pn S1 to S5
–– 86.500 107.000 78.800 91.600 78.800 91.600
*: Program name
XCALL –– 3.800 5.700 3.700 5.200 3.700 5.200

App-97
 Processing Time (µs)
Q04/ Q10/Q13/Q20/
Category Instruction Condition (Device) Q03UD(E)CPU
Q06UD(E)HCPU Q26UD(E)HCPU
Min. Max. Min. Max. Min. Max.
When selecting I/O refresh only 12.800 29.100 12.400 28.600 12.400 28.600
When selecting CC-Link refresh
16.000 39.500 15.500 39.100 15.500 39.100
only (Master station side)
When selecting CC-Link refresh
16.100 39.500 15.500 39.100 15.500 39.100
only (Local station side)
When selecting MELSECNET/H
34.700 70.400 34.400 69.800 34.400 69.800
refresh only (Control station side)
When selecting MELSECNET/H
34.700 70.400 34.400 69.800 34.400 69.800
refresh only (Normal station side)
When selecting intelli auto
12.800 33.200 12.800 33.200 12.800 33.200
COM refresh only
CCOM When selecting I/O outside the
7.900 21.100 7.700 20.700 7.700 20.700
group only (Input only)
When selecting I/O outside the
16.900 44.800 16.500 44.200 16.500 44.200
group only (Output only)
When selecting I/O outside the
22.600 52.600 22.400 52.600 22.400 52.600
group only (Both I/O)
When selecting refresh of multi-
ple CPU high speed transmission 13.000 33.800 12.700 33.200 12.700 33.200
area only
When selecting communication
7.250 18.800 7.100 18.500 7.100 18.500
with peripheral device
Number of data points = 0 3.700 5.300 3.200 4.600 3.200 4.600
FIFW
Number of data points = 96 3.800 4.400 3.300 3.800 3.300 3.800

Application Number of data points = 0 4.300 5.000 3.800 4.400 3.800 4.400
FIFR
instruction Number of data points = 96 33.500 35.500 24.800 25.700 24.800 25.700
Number of data points = 0 4.300 5.900 3.800 5.300 3.800 5.300
FPOP
Number of data points = 96 4.300 5.900 3.700 5.400 3.700 5.400
Number of data points = 0 4.800 5.900 3.700 5.300 3.700 5.300
FINS
Number of data points = 96 4.300 5.900 3.700 5.300 3.700 5.300
Number of data points = 0 4.900 6.500 4.200 5.800 4.200 5.800
FDEL
Number of data points = 96 34.200 35.900 25.400 25.900 25.400 25.900
n3 = 1 10.800 24.100 10.700 23.600 10.700 23.600
FROM n1 n2 D n3
n3 = 1000 392.600 413.300 390.900 410.200 390.900 410.200
n3 = 1 13.600 27.700 12.600 26.700 12.600 26.700
DFRO n1 n2 D n3
n3 = 500 392.600 413.300 390.900 410.200 390.900 410.200
n3 = 1 10.200 21.900 9.600 21.300 9.600 21.300
TO n1 n2 S n3
n3 = 1000 373.700 394.100 372.500 390.800 372.500 390.800
n3 = 1 13.000 26.700 12.000 25.700 12.000 25.700
DTO n1 n2 S n3
n3 = 500 373.700 394.100 372.500 390.800 372.500 390.800
No display no display 2.400 2.600 1.900 2.000 1.900 2.000
LEDR LED instruction execution no
28.100 39.400 24.400 35.800 24.400 35.800
display

S =1 4.900 6.500 4.300 5.600 4.300 5.600

BINDA S D
S = -32768 7.200 8.700 6.500 8.000 6.500 8.000

S =1 5.700 7.100 4.900 6.300 4.900 6.300

DBINDA S D
S = -2147483648 10.400 12.000 9.600 11.000 9.600 11.000

App-98
 Processing Time (µs)
Q04/ Q10/Q13/Q20/
Category Instruction Condition (Device) Q03UD(E)CPU
Q06UD(E)HCPU Q26UD(E)HCPU 8
Min. Max. Min. Max. Min. Max.

4.400 5.900 3.800 5.200 3.800 5.200

BINHA S D
S =1
8
S = FFFFH 4.400 5.800 3.700 5.200 3.700 5.200

=1 5.200 6.700 4.600 6.000 4.600 6.000

8
S
DBINHA S D
S = FFFFFFFFH 5.100 6.500 4.600 6.000 4.600 6.000

S =1 4.300 5.800 3.600 5.000 3.600 5.000

BCDDA S D
S = 9999 4.700 6.100 4.100 5.400 4.100 5.400
8
S =1 4.800 6.300 4.000 5.500 4.000 5.500
DBCDDA S
A
D
S = 99999999 5.600 7.100 4.900 6.300 4.900 6.300

S =1 6.500 8.500 5.800 7.800 5.800 7.800

DABIN S D
S = -32768 6.300 8.300 5.600 7.700 5.600 7.700 6
S =1 9.400 11.500 8.500 10.500 8.500 10.500
DDABIN S D
S = -2147483648 9.100 11.200 8.100 10.200 8.100 10.200
7
Application S =1 4.900 7.100 4.400 6.400 4.400 6.400
instruction HABIN S D
= FFFFH 5.100 7.300 4.600 6.500 4.600 6.500
S
8
S =1 6.000 8.100 5.300 7.300 5.300 7.300
DHABIN S D
S = FFFFFFFFH 6.300 8.500 5.600 7.700 5.600 7.700

S =1 5.000 7.100 4.400 6.300 4.400 6.300

DABCD S D

Appendix 1.4 Operation Processing Time of Universal Model QCPU

Appendix1 OPERATION PROCESSING TIME
S = 9999 5.000 7.100 4.300 6.300 4.300 6.300

S =1 6.200 8.300 5.500 7.400 5.500 7.400

DDABCD S D
S = 99999999 6.200 8.300 5.500 7.500 5.500 7.500

COMRD –– 51.600 52.400 50.900 51.200 50.900 51.200

1 character 4.100 6.200 3.600 5.500 3.600 5.500
LEN
96 characters 19.800 22.200 16.800 18.700 16.800 18.700
STR –– 6.900 11.100 6.600 10.400 6.600 10.400
DSTR –– 10.200 12.500 9.600 11.500 9.600 11.500
VAL –– 9.800 14.200 8.900 13.000 8.900 13.000
DVAL –– 14.000 18.700 12.700 16.800 12.700 16.800
ESTR –– 18.700 24.100 17.900 23.100 17.900 23.100

App-99
 Processing Time (µs)
Q04/ Q10/Q13/Q20/
Category Instruction Condition (Device) Q03UD(E)CPU
Q06UD(E)HCPU Q26UD(E)HCPU
Min. Max. Min. Max. Min. Max.
Decimal point format
23.300 30.400 22.800 29.000 22.800 29.000
all 2-digit specification
EVAL
Exponent format
23.300 30.500 22.500 29.000 22.500 29.000
all 6-digit specification
n=1 5.600 9.000 5.400 8.300 5.400 8.300
ASC S D n
n = 96 28.700 32.100 25.200 28.400 25.200 28.400
n=1 6.000 9.700 5.400 9.000 5.400 9.000
HEX S D n
n = 96 35.600 39.800 31.300 35.000 31.300 35.000
n=1 7.600 9.400 7.300 6.600 7.300 6.600
RIGHT S D n
n = 96 36.300 40.000 29.200 31.600 29.200 31.600
n=1 6.500 8.900 5.900 8.200 5.900 8.200
LEFT S D n
n = 96 36.200 39.700 29.200 31.500 29.200 31.500
MIDR –– 9.500 12.100 8.100 10.300 8.100 10.300
MIDW –– 10.300 12.000 8.800 10.200 8.800 10.200
No match 19.300 21.800 16.600 18.400 16.600 18.400
INSTR Head 10.300 12.800 9.100 10.900 9.100 10.900
Match
End 51.100 54.200 42.700 44.900 42.700 44.900
EMOD –– 10.300 11.800 9.600 11.000 9.600 11.000
EREXP –– 19.300 21.000 18.800 20.100 18.800 20.100

S = 128 / D = 40 /
41.100 54.200 35.300 47.600 35.300 47.600
n=1
STRINS S D n
S = 128 / D = 40 /
56.700 81.400 48.600 61.700 48.600 61.700
Application n = 48
instruction
S = 128 / D = 40 /
39.000 49.500 34.800 44.600 34.800 44.600
n=1
STRDEL S D n
S = 128 / D = 40 /
36.000 45.200 29.200 38.100 29.200 38.100
n = 48
SIN Single precision 4.500 6.200 4.100 5.700 4.100 5.700
COS Single precision 4.300 6.000 4.000 5.600 4.000 5.600
TAN Single precision 5.100 7.200 5.100 6.700 5.100 6.700
ASIN Single precision 6.100 8.900 5.900 8.500 5.900 8.500
ACOS Single precision 6.800 9.300 6.700 8.900 6.700 8.900
ATAN Single precision 4.000 6.500 3.900 6.000 3.900 6.000
SIND Double precision 8.800 14.300 8.500 13.800 8.500 13.800
COSD Double precision 9.300 15.100 8.800 14.600 8.800 14.600
TAND Double precision 11.200 16.900 10.800 16.500 10.800 16.500
ASIND Double precision 12.000 17.100 11.600 16.600 11.600 16.600
ACOSD Double precision 11.700 16.500 11.200 16.200 11.200 16.200
ATAND Double precision 9.500 14.200 9.100 13.800 9.100 13.800
RAD Single precision 2.500 4.800 2.100 4.300 2.100 4.300
RADD Double precision 4.000 9.600 3.600 9.200 3.600 9.200
DEG Single precision 2.500 4.700 2.200 4.400 2.200 4.400
DEGD Double precision 4.300 9.000 3.800 9.000 3.800 9.000
SQR Single precision 3.000 4.600 2.600 4.300 2.600 4.300
SQRD Double precision 5.600 11.500 5.200 11.000 5.200 11.000

App-100
 Processing Time (µs)
Q04/ Q10/Q13/Q20/
Category Instruction Condition (Device) Q03UD(E)CPU
Q06UD(E)HCPU Q26UD(E)HCPU 8
Min. Max. Min. Max. Min. Max.

4.000 6.100 3.800 5.500 3.800 5.500

EXP S D
Single
precision
S = -10
8
S =1 4.000 6.100 3.800 5.600 3.800 5.600

Double = -10 8.700 13.900 8.200 13.500 8.200 13.500

8
S
EXPD S D
precision 8.400 13.600 8.000 13.200 8.000 13.200
S =1

Single S =1 4.100 6.900 3.800 6.400 3.800 6.400

LOG S D
precision
S = 10 5.600 8.200 5.200 7.700 5.200 7.700 8
Double S =1 8.100 13.000 7.700 12.500 7.700 12.500
LOGD S
A
D
precision 9.700 14.800 9.200 14.300 9.200 14.300
S = 10
RND –– 1.200 2.300 0.800 1.800 0.800 1.800
SRND –– 1.400 2.400 1.100 2.000 1.100 2.000

S =0 1.800 3.300 1.600 2.800 1.600 2.800

6
BSQR S D
S = 9999 5.100 8.800 5.100 8.000 5.100 8.000

S =0 1.900 3.400 1.500 3.000 1.500 3.000 7

BDSQR S D
S = 99999999 7.500 10.200 7.500 9.900 7.500 9.900
Application
instruction BSIN –– 8.600 15.100 8.100 14.500 8.100 14.500
8
BCOS –– 7.800 14.400 7.800 13.700 7.800 13.700
BTAN –– 9.000 13.800 9.000 13.300 9.000 13.300
BASIN –– 10.600 13.400 10.100 12.800 10.100 12.800
BACOS –– 11.600 14.400 11.100 14.100 11.100 14.100

Appendix 1.4 Operation Processing Time of Universal Model QCPU

Appendix1 OPERATION PROCESSING TIME
BATAN –– 9.800 11.700 9.100 10.900 9.100 10.900

Single S1 = 12.3 E + 5
POW S1 S2 D
precision S2 = 3.45 E + 0
8.750 11.400 8.400 10.900 8.400 10.900
Double S1 = 12.3 E + 5
POWD S1 S2 D
precision S2 = 3.45 E + 0
LOG10 Single precision
18.600 27.200 18.200 26.500 18.200 26.500
LOG10D Double precision
LIMIT –– 5.900 8.550 5.700 8.050 5.700 8.050
DLIMIT –– 11.500 19.400 11.100 18.600 11.100 18.600
BAND –– 2.800 3.100 2.400 2.700 2.400 2.700
DBAND –– 3.200 3.500 2.800 3.000 2.800 3.000
ZONE –– 3.000 4.300 2.700 3.800 2.700 3.800
DZONE –– 3.600 5.100 3.300 4.600 3.300 4.600

App-101
 Processing Time (µs)
Q04/ Q10/Q13/Q20/
Category Instruction Condition (Device) Q03UD(E)CPU
Q06UD(E)HCPU Q26UD(E)HCPU
Min. Max. Min. Max. Min. Max.
Point No.1

< S1 < 13.200 23.600 12.300 22.500 12.300 22.500

SM750 Point No.2
= ON Point No.9

< S1 < 13.300 23.600 12.600 22.700 12.600 22.700

Point No.10
SCL S1 S2 D
Point No.1

< S1 < 12.000 23.100 11.400 22.200 11.400 22.200

SM750 Point No.2
= OFF Point No.9

< S1 < 14.100 25.300 12.800 23.900 12.800 23.900

Point No.10
Point No.1

< S1 < 12.800 23.800 11.900 23.000 11.900 23.000

SM750 Point No.2
= ON Point No.9

< S1 < 12.900 23.900 12.100 23.000 12.100 23.000

Point No.10
DSCL S1 S2 D
Point No.1

< S1 < 11.500 22.400 10.900 21.500 10.900 21.500

SM750 Point No.2
= OFF Point No.9

< S1 < 13.800 24.900 12.700 23.600 12.700 23.600

Application Point No.10
instruction Point No.1

< S1 < 12.700 24.200 11.900 23.300 11.900 23.300

SM750 Point No.2
= ON Point No.9

< S1 < 12.900 24.600 12.100 23.300 12.100 23.300

Point No.10
SCL2 S1 S2 D
Point No.1

< S1 < 12.300 23.400 11.500 22.600 11.500 22.600

SM750 Point No.2
= OFF Point No.9

< S1 < 13.700 25.000 12.600 23.900 12.600 23.900

Point No.10
Point No.1

< S1 < 12.600 23.800 11.800 22.900 11.800 22.900

SM750 Point No.2
= ON Point No.9

< S1 < 13.000 23.900 12.200 22.800 12.200 22.800

Point No.10
DSCL2 S1 S2 D
Point No.1

< S1 < 11.500 22.400 11.000 21.400 11.000 21.400

SM750 Point No.2
= OFF Point No.9

< S1 < 13.900 24.900 12.800 23.600 12.800 23.600

Point No.10

App-102
 Processing Time (µs)

Category Instruction Condition (Device) Q03UD(E)CPU

Q04/ Q10/Q13/Q20/ 8
Q06UD(E)HCPU Q26UD(E)HCPU
Min. Max. Min. Max. Min. Max.

RSET
Standard RAM 3.000 6.300 2.700 5.900 2.700 5.900
8
SRAM card 3.000 6.400 2.600 5.800 2.600 5.800
SRAM card to standard RAM 120.000 134.000 115.000 134.000 115.000 134.000
QDRSET
Standard RAM to SRAM card
SRAM card to standard ROM
533.000
306.000
560.000
346.000
520.000
305.000
553.000
346.000
520.000
305.000
553.000
346.000
8
QCDSET
Standard ROM to SRAM card 311.000 342.000 300.000 334.000 300.000 334.000
DATERD
DATEWR
––
––
3.200
4.900
5.000
9.700
2.500
4.100
4.200
8.900
2.500
4.100
4.200
8.900
8
No digit increase 5.100 8.000 4.700 6.600 4.700 6.600
DATE +
Digit increase 5.700 8.000 4.600 6.500 4.600 6.500
No digit increase 5.800 8.500 4.600 7.000 4.600 7.000
A
DATE -
Digit increase 5.700 7.400 4.600 6.500 4.600 6.500
SECOND –– 2.600 3.900 2.200 3.400 2.200 3.400
HOUR –– 2.900 4.800 2.400 4.300 2.400 4.300 6
In conductive
Comparison 7.400 11.400 6.800 10.900 6.800 10.900
status
of specified
date
In nonconductive
7.400 11.600 6.800 10.900 6.800 10.900
7
status
LDDT =
In conductive
Comparison 5.900 10.000 5.500 9.700 5.500 9.700
of current
status
8
In nonconductive
date 5.900 10.100 5.500 9.700 5.500 9.700
status
When not executed 0.008 0.038 0.038
Application
In conductive
instruction Comparison 7.200 11.400 6.500 10.700 6.500 10.700
status

Appendix 1.4 Operation Processing Time of Universal Model QCPU

Appendix1 OPERATION PROCESSING TIME
of specified
In nonconductive
date 7.200 11.400 6.500 10.700 6.500 10.700
ANDDT= status
In conductive
Comparison 5.700 9.900 5.300 9.300 5.300 9.300
status
of current
In nonconductive
date 5.700 9.900 5.300 9.300 5.300 9.300
status
When not executed 0.008 0.038 0.038
In conductive
Comparison 7.400 11.500 6.700 10.800 6.700 10.800
status
of specified
In nonconductive
date 7.400 11.500 6.700 10.800 6.700 10.800
ORDT= status
In conductive
Comparison 5.900 10.000 5.400 9.600 5.400 9.600
status
of current
In nonconductive
date 5.900 10.000 5.400 9.600 5.400 9.600
status
In conductive
Comparison 7.400 11.400 6.800 10.900 6.800 10.900
status
of specified
In nonconductive
date 7.400 11.600 6.800 10.900 6.800 10.900
status
LDDT <>
In conductive
Comparison 5.900 10.000 5.500 9.700 5.500 9.700
status
of current
In nonconductive
date 5.900 10.100 5.500 9.700 5.500 9.700
status

App-103
 Processing Time (µs)
Q04/ Q10/Q13/Q20/
Category Instruction Condition (Device) Q03UD(E)CPU
Q06UD(E)HCPU Q26UD(E)HCPU
Min. Max. Min. Max. Min. Max.
When not executed 0.008 0.038 0.038
In conductive
Comparison 7.200 11.400 6.500 10.700 6.500 10.700
status
of specified
In nonconductive
date 7.200 11.400 6.500 10.700 6.500 10.700
ANDDT<> status
In conductive
Comparison 5.700 9.900 5.300 9.300 5.300 9.300
status
of current
In nonconductive
date 5.700 9.900 5.300 9.300 5.300 9.300
status
When not executed 0.008 0.038 0.038
In conductive
Comparison 7.400 11.500 6.700 10.800 6.700 10.800
status
of specified
In nonconductive
date 7.400 11.500 6.700 10.800 6.700 10.800
ORDT<> status
In conductive
Comparison 5.900 10.000 5.400 9.600 5.400 9.600
status
of current
In nonconductive
date 5.900 10.000 5.400 9.600 5.400 9.600
status
In conductive
Comparison 7.400 11.400 6.800 10.900 6.800 10.900
status
of specified
In nonconductive
date 7.400 11.600 6.800 10.900 6.800 10.900
Application status
LDDT>
instruction In conductive
Comparison 5.900 10.000 5.500 9.700 5.500 9.700
status
of current
In nonconductive
date 5.900 10.100 5.500 9.700 5.500 9.700
status
When not executed 0.008 0.038 0.038
In conductive
Comparison 7.200 11.400 6.500 10.700 6.500 10.700
status
of specified
In nonconductive
date 7.200 11.400 6.500 10.700 6.500 10.700
ANDDT> status
In conductive
Comparison 5.700 9.900 5.300 9.300 5.300 9.300
status
of current
In nonconductive
date 5.700 9.900 5.300 9.300 5.300 9.300
status
When not executed 0.008 0.038 0.038
In conductive
Comparison 7.400 11.500 6.700 10.800 6.700 10.800
status
of specified
In nonconductive
date 7.400 11.500 6.700 10.800 6.700 10.800
ORDT> status
In conductive
Comparison 5.900 10.000 5.400 9.600 5.400 9.600
status
of current
In nonconductive
date 5.900 10.000 5.400 9.600 5.400 9.600
status

App-104
 Processing Time (µs)
Q04/ Q10/Q13/Q20/
Category Instruction Condition (Device) Q03UD(E)CPU
Q06UD(E)HCPU Q26UD(E)HCPU 8
Min. Max. Min. Max. Min. Max.
In conductive
Comparison
of specified
status
7.400 11.400 6.800 10.900 6.800 10.900
8
In nonconductive
date 7.400 11.600 6.800 10.900 6.800 10.900
status
LDDT<=
Comparison
In conductive
5.900 10.000 5.500 9.700 5.500 9.700 8
status
of current
In nonconductive
date 5.900 10.100 5.500 9.700 5.500 9.700
status
When not executed 0.008 0.038 0.038
8
In conductive
Comparison 7.200 11.400 6.500 10.700 6.500 10.700
status
of specified
In nonconductive A
date 7.200 11.400 6.500 10.700 6.500 10.700
ANDDT<= status
In conductive
5.700 9.900 5.300 9.300 5.300 9.300
Comparison
of current
status 6
In nonconductive
date 5.700 9.900 5.300 9.300 5.300 9.300
status
When not executed 0.008 0.038 0.038
7
In conductive
Comparison 7.400 11.500 6.700 10.800 6.700 10.800
status
of specified
In nonconductive
ORDT<=
date
status
7.400 11.500 6.700 10.800 6.700 10.800 8
In conductive
Comparison 5.900 10.000 5.400 9.600 5.400 9.600
status
of current
In nonconductive
date 5.900 10.000 5.400 9.600 5.400 9.600
Application status

Appendix 1.4 Operation Processing Time of Universal Model QCPU

Appendix1 OPERATION PROCESSING TIME
instruction In conductive
Comparison 7.400 11.400 6.800 10.900 6.800 10.900
status
of specified
In nonconductive
date 7.400 11.600 6.800 10.900 6.800 10.900
status
LDDT<
In conductive
Comparison 5.900 10.000 5.500 9.700 5.500 9.700
status
of current
In nonconductive
date 5.900 10.100 5.500 9.700 5.500 9.700
status
When not executed 0.008 0.038 0.038
In conductive
Comparison 7.200 11.400 6.500 10.700 6.500 10.700
status
of specified
In nonconductive
date 7.200 11.400 6.500 10.700 6.500 10.700
ANDDT< status
In conductive
Comparison 5.700 9.900 5.300 9.300 5.300 9.300
status
of current
In nonconductive
date 5.700 9.900 5.300 9.300 5.300 9.300
status
When not executed 0.008 0.038 0.038
In conductive
Comparison 7.400 11.500 6.700 10.800 6.700 10.800
status
of specified
In nonconductive
date 7.400 11.500 6.700 10.800 6.700 10.800
ORDT< status
In conductive
Comparison 5.900 10.000 5.400 9.600 5.400 9.600
status
of current
In nonconductive
date 5.900 10.000 5.400 9.600 5.400 9.600
status

App-105
 Processing Time (µs)
Q04/ Q10/Q13/Q20/
Category Instruction Condition (Device) Q03UD(E)CPU
Q06UD(E)HCPU Q26UD(E)HCPU
Min. Max. Min. Max. Min. Max.
In conductive
Comparison 7.400 11.400 6.800 10.900 6.800 10.900
status
of specified
In nonconductive
date 7.400 11.600 6.800 10.900 6.800 10.900
status
LDDT>=
In conductive
Comparison 5.900 10.000 5.500 9.700 5.500 9.700
status
of current
In nonconductive
date 5.900 10.100 5.500 9.700 5.500 9.700
status
When not executed 0.008 0.038 0.038
In conductive
Comparison 7.200 11.400 6.500 10.700 6.500 10.700
status
of specified
In nonconductive
date 7.200 11.400 6.500 10.700 6.500 10.700
ANDDT>= status
In conductive
Comparison 5.700 9.900 5.300 9.300 5.300 9.300
status
of current
In nonconductive
date 5.700 9.900 5.300 9.300 5.300 9.300
status
When not executed 0.008 0.038 0.038
In conductive
Comparison 7.400 11.500 6.700 10.800 6.700 10.800
status
of specified
In nonconductive
date 7.400 11.500 6.700 10.800 6.700 10.800
ORDT>= status
In conductive
Comparison 5.900 10.000 5.400 9.600 5.400 9.600
status
of current
In nonconductive
Application date 5.900 10.000 5.400 9.600 5.400 9.600
status
instruction
In conductive
Comparison 7.300 11.500 6.700 10.800 6.700 10.800
status
of specified
In nonconductive
ciock 7.300 11.500 6.700 10.800 6.700 10.800
status
LDTM=
In conductive
Comparison 5.800 9.900 5.400 9.500 5.400 9.500
status
of current
In nonconductive
ciock 5.800 9.900 5.400 9.500 5.400 9.500
status
When not executed 0.008 0.038 0.038
In conductive
Comparison 7.000 11.500 6.300 10.800 6.300 10.800
status
of specified
In nonconductive
ciock 7.000 11.500 6.300 10.800 6.300 10.800
ANDTM= status
In conductive
Comparison 5.500 9.900 5.100 9.500 5.100 9.500
status
of current
In nonconductive
ciock 5.500 9.900 5.100 9.500 5.100 9.500
status
When not executed 0.008 0.038 0.038
In conductive
Comparison 7.300 11.500 6.600 10.800 6.600 10.800
status
of specified
In nonconductive
ORTM= ciock 7.300 11.500 6.600 10.800 6.600 10.800
status
Comparison
In conductive
of current 5.900 9.900 5.300 9.500 5.300 9.500
status
ciock

App-106
 Processing Time (µs)
Q04/ Q10/Q13/Q20/
Category Instruction Condition (Device) Q03UD(E)CPU
Q06UD(E)HCPU Q26UD(E)HCPU 8
Min. Max. Min. Max. Min. Max.
In conductive
Comparison
of specified
status
7.300 11.500 6.700 10.800 6.700 10.800
8
In nonconductive
ciock 7.300 11.500 6.700 10.800 6.700 10.800
status
LDTM<>
Comparison
In conductive
5.800 9.900 5.400 9.500 5.400 9.500 8
status
of current
In nonconductive
ciock 5.800 9.900 5.400 9.500 5.400 9.500
status
When not executed 0.008 0.038 0.038
8
In conductive
Comparison 7.000 11.500 6.300 10.800 6.300 10.800
status
of specified
In nonconductive A
ciock 7.000 11.500 6.300 10.800 6.300 10.800
ANDTM<> status
In conductive
5.500 9.900 5.100 9.500 5.100 9.500
Comparison
of current
status 6
In nonconductive
ciock 5.500 9.900 5.100 9.500 5.100 9.500
status
When not executed 0.008 0.038 0.038
7
In conductive
Comparison 7.300 11.500 6.600 10.800 6.600 10.800
status
of specified
In nonconductive
ORTM<>
ciock
status
7.300 11.500 6.600 10.800 6.600 10.800 8
In conductive
Comparison 5.900 9.900 5.300 9.500 5.300 9.500
status
of current
In nonconductive
ciock 5.900 9.900 5.300 9.500 5.300 9.500
Application status

Appendix 1.4 Operation Processing Time of Universal Model QCPU

Appendix1 OPERATION PROCESSING TIME
instruction In conductive
Comparison 7.300 11.500 6.700 10.800 6.700 10.800
status
of specified
In nonconductive
ciock 7.300 11.500 6.700 10.800 6.700 10.800
status
LDTM>
In conductive
Comparison 5.800 9.900 5.400 9.500 5.400 9.500
status
of current
In nonconductive
ciock 5.800 9.900 5.400 9.500 5.400 9.500
status
When not executed 0.008 0.038 0.038
In conductive
Comparison 7.000 11.500 6.300 10.800 6.300 10.800
status
of specified
In nonconductive
ciock 7.000 11.500 6.300 10.800 6.300 10.800
ANDTM> status
In conductive
Comparison 5.500 9.900 5.100 9.500 5.100 9.500
status
of current
In nonconductive
ciock 5.500 9.900 5.100 9.500 5.100 9.500
status
When not executed 0.008 0.038 0.038
In conductive
Comparison 7.300 11.500 6.600 10.800 6.600 10.800
status
of specified
In nonconductive
ciock 7.300 11.500 6.600 10.800 6.600 10.800
ORTM> status
In conductive
Comparison 5.900 9.900 5.300 9.500 5.300 9.500
status
of current
In nonconductive
ciock 5.900 9.900 5.300 9.500 5.300 9.500
status

App-107
 Processing Time (µs)
Q04/ Q10/Q13/Q20/
Category Instruction Condition (Device) Q03UD(E)CPU
Q06UD(E)HCPU Q26UD(E)HCPU
Min. Max. Min. Max. Min. Max.
In conductive
Comparison 7.300 11.500 6.700 10.800 6.700 10.800
status
of specified
In nonconductive
ciock 7.300 11.500 6.700 10.800 6.700 10.800
status
LDTM<=
In conductive
Comparison 5.800 9.900 5.400 9.500 5.400 9.500
status
of current
In nonconductive
ciock 5.800 9.900 5.400 9.500 5.400 9.500
status
When not executed 0.008 0.038 0.038
In conductive
Comparison 7.000 11.500 6.300 10.800 6.300 10.800
status
of specified
In nonconductive
ciock 7.000 11.500 6.300 10.800 6.300 10.800
ANDTM<= status
In conductive
Comparison 5.500 9.900 5.100 9.500 5.100 9.500
status
of current
In nonconductive
ciock 5.500 9.900 5.100 9.500 5.100 9.500
status
When not executed 0.008 0.038 0.038
In conductive
Comparison 7.300 11.500 6.600 10.800 6.600 10.800
status
of specified
In nonconductive
ciock 7.300 11.500 6.600 10.800 6.600 10.800
ORTM<= status
In conductive
Comparison 5.900 9.900 5.300 9.500 5.300 9.500
status
of current
In nonconductive
ciock 5.900 9.900 5.300 9.500 5.300 9.500
Application status
instruction In conductive
Comparison 7.300 11.500 6.700 10.800 6.700 10.800
status
of specified
In nonconductive
ciock 7.300 11.500 6.700 10.800 6.700 10.800
status
LDTM<
In conductive
Comparison 5.800 9.900 5.400 9.500 5.400 9.500
status
of current
In nonconductive
ciock 5.800 9.900 5.400 9.500 5.400 9.500
status
When not executed 0.480 0.320 0.240
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500
status
of specified
In nonconductive
ciock 8.200 25.500 8.200 25.500 6.500 25.500
ANDTM< status
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100
status
of current
In nonconductive
ciock 6.500 23.100 6.500 23.100 6.500 23.100
status
When not executed 0.480 0.320 0.240
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500
status
of specified
In nonconductive
ciock 8.200 25.500 8.200 25.500 6.500 25.500
ORTM< status
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100
status
of current
In nonconductive
ciock 6.500 23.100 6.500 23.100 6.500 23.100
status

App-108
 Processing Time (µs)
Q04/ Q10/Q13/Q20/
Category Instruction Condition (Device) Q03UD(E)CPU
Q06UD(E)HCPU Q26UD(E)HCPU 8
Min. Max. Min. Max. Min. Max.
In conductive
Comparison
of specified
status
7.300 11.500 6.700 10.800 6.700 10.800
8
In nonconductive
ciock 7.300 11.500 6.700 10.800 6.700 10.800
status
LDTM<
Comparison
In conductive
5.800 9.900 5.400 9.500 5.400 9.500 8
status
of current
In nonconductive
ciock 5.800 9.900 5.400 9.500 5.400 9.500
status
When not executed 0.480 0.320 0.240
8
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500
status
of specified
In nonconductive A
ciock 8.200 25.500 8.200 25.500 6.500 25.500
ANDTM< status
In conductive
6.500 23.100 6.500 23.100 6.500 23.100
Comparison
of current
status 6
In nonconductive
ciock 6.500 23.100 6.500 23.100 6.500 23.100
status
When not executed 0.480 0.320 0.240
7
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500
status
of specified
In nonconductive
ORTM<
ciock
status
8.200 25.500 8.200 25.500 6.500 25.500 8
Application
In conductive
instruction Comparison 6.500 23.100 6.500 23.100 6.500 23.100
status
of current
In nonconductive
ciock 6.500 23.100 6.500 23.100 6.500 23.100
status

Appendix 1.4 Operation Processing Time of Universal Model QCPU

Appendix1 OPERATION PROCESSING TIME
S.DATERD –– 9.250 51.000 9.250 51.000 9.250 51.000
No digit increase 16.800 75.400 16.800 75.400 16.800 75.400
S.DATE +
Digit increase 16.800 75.400 16.800 75.400 16.800 75.400
No digit increase 17.600 75.300 17.600 75.300 17.600 75.300
S.DATE -
Digit increase 16.900 75.300 16.900 75.300 16.900 75.300
PSTOP –– 82.200 199.000 82.200 199.000 82.200 199.000
POFF –– 82.600 198.000 82.600 198.000 82.600 198.000
PSCAN –– 83.600 200.000 83.600 200.000 83.600 200.000
WDT –– 2.900 12.000 2.900 12.000 2.900 12.000
DUTY –– 7.700 27.500 7.700 27.500 7.700 27.500
TIMCHK –– 5.350 24.500 5.350 24.500 5.350 24.500
File register of standard RAM 4.100 4.200 4.100 4.200 4.100 4.200
ZRRDB
File register of SRAM card –– –– –– –– –– ––
File register of standard RAM 5.400 5.500 5.400 5.500 5.400 5.500
ZRWRB
File register of SRAM card –– –– –– –– –– ––
ADRSET –– 2.400 6.650 2.400 6.650 2.400 6.650
ZPUSH –– 9.200 20.500 9.200 20.500 9.200 20.500
ZPOP –– 9.000 15.500 9.000 15.500 9.000 15.500

App-109
 Processing Time (µs)
Q04/ Q10/Q13/Q20/
Category Instruction Condition (Device) Q03UD(E)CPU
Q06UD(E)HCPU Q26UD(E)HCPU
Min. Max. Min. Max. Min. Max.
When mounting CC-Link
module 19.600 26.500 19.300 26.000 19.300 26.000
(Master station side)
When mounting CC-Link
module 19.600 26.500 19.100 26.200 19.100 26.200
(Local station side)
When mounting
MELSECNET/H,
S.ZCOM
CC-Link IEcontroller 53.500 73.500 53.000 72.700 53.000 72.700
network module(Control
station side)
When mounting
MELSECNET/H,
CC-Link IEcontroller 29.800 41.200 29.800 40.600 29.800 40.600
network module(Normal
station side)

Application S.RTREAD –– 5.900 11.000 5.400 10.500 5.400 10.500

instruction S.RTWRITE –– 6.700 11.100 6.000 10.400 6.000 10.400
n2 = 1 4.000 8.400 3.700 8.000 3.700 8.000
UNIRD n1 D n2
n2 = 16 12.500 17.000 12.200 16.600 12.200 16.600
TYPERD 29.800 53.000 29.500 52.300 29.500 52.300
TRACE Start 46.600 48.300 43.800 44.700 43.800 44.700
TRACER –– 3.300 6.800 2.600 6.000 2.600 6.000
1 point 11.300 16.800 9.200 15.100 9.200 15.100
When standard
1000
RAM is used 120.700 127.100 61.000 68.600 61.000 68.600
points
RBNOV S D n
1 point 11.200 16.700 9.400 15..600 9.400 15.600
When SRAM
1000
card is used 180.700 187.100 165.000 172.600 165.000 172.600
points
SP.FWRITE –– 6.700 11.100 6.000 10.400 6.000 10.400
SP.FREAD –– 5.900 11.000 5.400 10.500 5.400 10.500
SP.DEVST –– 4.500 36.500 4.000 34.500 4.000 34.500
S.DEVLD –– 11.000 17.800 10.000 17.000 10.000 17.000

App-110
 Processing Time (µs)
Q04/ Q10/Q13/Q20/
Category Instruction Condition (Device) Q03UD(E)CPU
Q06UD(E)HCPU Q26UD(E)HCPU 8
Min. Max. Min. Max. Min. Max.
Writing to host n4 = 1 34.700 34.900 33.500 34.400 33.500 34.400

S.TO n1 n2 n3 n4 D CPU shared

n4 = 320 85.900 87.600 75.200 75.500 75.200 75.500
8
memory
Writing to host n3 = 1 4.700 23.800 5.200 23.300 5.200 23.300

TO n1 n2 S n3 CPU shared
memory
n3 = 320 57.500 76.200 47.100 64.500 47.100 64.500 8
Writing to host n3 = 1 5.300 23.800 5.800 23.300 5.800 23.300
CPU shared
DTO n1 n2 n3
8
S
n3 = 320 111.300 128.400 91.500 108.500 91.500 108.500
memory
Multiple Reading from n3 = 1 5.000 23.800 4.300 23.300 4.300 23.300
CPU host CPU shared
dedicated
instruction
memory
n3 = 320 51.400 65.600 44.400 60.700 44.400 60.700
A
FROM n1 n2 D n3 n3 = 1 11.600 17.700 10.600 13.900 10.600 13.900
Reading from
other CPU n3 = 320 142.000 160.000 142.000 149.000 142.000 149.000
shared memory n3 = 1000 431.000 463.000 422.000 448.000 422.000 448.000 6
Reading from n3 = 1 5.200 23.800 5.600 23.300 5.600 23.300
host CPU shared
n3 = 320 96.400 113.200 83.600 100.800 83.600 100.800
memory
DFRO n1 n2 D n3
Reading from n3 = 1 12.900 20.800 12.200 17.100 12.200 17.100
7
other CPU n3 = 320 277.000 299.000 274.000 291.000 274.000 291.000
shared memory n3 = 1000 838.000 860.000 835.000 857.000 835.000 857.000
n=1 34.700 34.900 33.500 34.400 33.500 34.400
8
D.DDWR n S1 S2 D1 D2 n=16 85.900 87.600 75.200 75.500 75.200 75.500

Writes devices to n=96 5.600 10.200 3.300 9.900 3.300 9.900

Multiple another CPU. n=1 36.700 42.400 34.300 39.200 34.300 39.200
CPU high- n=16 5.000 12.100 3.100 10.500 3.100 10.500

Appendix 1.4 Operation Processing Time of Universal Model QCPU

Appendix1 OPERATION PROCESSING TIME
DP.DDWR n S1 S2 D1 D2
speed
n=96 59.100 66.800 55.300 65.100 55.300 65.100
transmis-
n=1 3.300 12.700 2.400 9.600 2.400 9.600
sion dedi-
cated D.DDRD n S1 S2 D1 D2 n=16 50.900 64.400 45.200 48.200 45.200 48.200
Reads devices n=96 11.600 17.700 10.600 13.900 10.600 13.900
instruction
from another
CPU. n=1 142.000 160.000 142.000 149.000 142.000 149.000

DP.DDRD n S1 S2 D1 D2 n=16 431.000 463.000 422.000 448.000 422.000 448.000

n=96 6.700 12.600 2.800 9.900 2.800 9.900

Remark
the instructions for which a rise execution instruction ( P) is not specified, the
processing time is the same as an ON execution instruction.
Example WORDP instruction and TOP instruction

App-111
 (2) Table of the time to be added when file register, module access device or link direct device is used
(a) When using Q00UJCPU, Q00UCPUI, Q01UCPU and Q02UCPU
Device Specification Processing Time (µs)
Device name data
Location Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
Source 0.100 0.100 0.100 0.100
Bit
Destination 0.100 0.100 0.100 0.100
When standard Source 0.100 0.100 0.100 0.100
Word
RAM is used Destination 0.100 0.100 0.100 0.100
Source 0.100 0.100 0.100 0.200
Double word
Destination 0.100 0.100 0.100 0.200
Source –– –– –– 0.220
Bit
When SRAM Destination –– –– –– 0.180
card is used Source –– –– –– 0.220
File register (R) Word
(Q2MEM-1MBS, Destination –– –– –– 0.180
Q2MEM-2MBS) Source –– –– –– 0.440
Double word
Destination –– –– –– 0.380
Source –– –– –– 0.160
Bit
When SRAM Destination –– –– –– 0.140
card is used Source –– –– –– 0.160
Word
(Q3MEM-4MBS, Destination –– –– –– 0.140
Q3MEM-8MBS) Source –– –– –– 0.320
Double word
Destination –– –– –– 0.300
Source 0.120 0.120 0.120 0.120
Bit
Destination 0.120 0.120 0.120 0.120
When standard Source 0.120 0.120 0.120 0.120
Word
RAM is used Destination 0.120 0.120 0.120 0.120
Source 0.120 0.120 0.120 0.220
Double word
Destination 0.120 0.120 0.120 0.220
Source –– –– –– 0.240
Bit
When SRAM Destination –– –– –– 0.200
card is used Source –– –– –– 0.240
File register (ZR) Word
(Q2MEM-1MBS, Destination –– –– –– 0.200
Q2MEM-2MBS) Source –– –– –– 0.460
Double word
Destination –– –– –– 0.400
Source –– –– –– 0.180
Bit
When SRAM Destination –– –– –– 0.160
card is used Source –– –– –– 0.180
Word
(Q3MEM-4MBS, Destination –– –– –– 0.160
Q3MEM-8MBS) Source –– –– –– 0.340
Double word
Destination –– –– –– 0.320
Source –– –– –– 12.000
Bit
Destination –– –– –– 17.300
Module access device Source –– –– –– 9.700
Word
(Un\G , U3En\G0 to G4095) Destination –– –– –– 33.000
Source –– –– –– 24.200
Double word
Destination –– –– –– 34.800
Source –– –– –– 32.900
Bit
Destination –– –– –– 67.300
Link direct device Source –– –– –– 37.200
Word
(Jn\ ) Destination –– –– –– 37.000
Source –– –– –– 39.500
Double word
Destination –– –– –– 41.900

App-112
 (b) When using Q03UD(E)CPU, Q04UD(E)HCPU, Q06UD(E)HCPU, Q10UD(E)HCPU,
Q13UD(E)HCPU, Q20UD(E)HCPU and Q26UD(E)HCPU
8
Processing Time (µs)
Device Specification
Device name data Q04/ Q10/Q13/Q20/
Location Q03UD(E)CPU
Q06UD(E)HCPU Q26UD(E)HCPU
Source 0.100 0.048 0.048
8
Bit
Destination 0.100 0.038 0.038
When standard Source 0.100 0.048 0.048
Word
RAM is used Destination 0.100 0.038 0.038 8
Source 0.200 0.095 0.095
Double word
Destination 0.200 0.086 0.086

When SRAM
Bit
Source
Destination
0.220
0.180
0.200
0.162
0.200
0.162
8
card is used Source 0.220 0.200 0.200
File register (R) Word
(Q2MEM-1MBS, Destination 0.180 0.162 0.162
Q2MEM-2MBS)
Double word
Source 0.440 0.399 0.399 A
Destination 0.380 0.361 0.361
Source 0.160 0.152 0.152
Bit
When SRAM
card is used
Destination
Source
0.140
0.160
0.133
0.152
0.133
0.152
6
Word
(Q3MEM-4MBS, Destination 0.140 0.133 0.133
Q3MEM-8MBS) Source 0.320 0.304 0.304
Double word
Destination 0.300 0.295 0.295 7
Source 0.120 0.057 0.057
Bit
Destination 0.120 0.048 0.048
When standard
RAM is used
Word
Source
Destination
0.120
0.120
0.057
0.048
0.057
0.048
8
Source 0.220 0.105 0.105
Double word
Destination 0.220 0.095 0.095
Source 0.240 0.209 0.209
File rExtended Bit
When SRAM Destination 0.200 0.171 0.171

Appendix 1.4 Operation Processing Time of Universal Model QCPU

Appendix1 OPERATION PROCESSING TIME
data register (D)/
card is used Source 0.240 0.209 0.209
Extended link Word
(Q2MEM-1MBS, Destination 0.200 0.171 0.171
register (W))
Q2MEM-2MBS) Source 0.460 0.409 0.409
egister (ZR) Double word
Destination 0.400 0.371 0.371
Source 0.180 0.162 0.162
Bit
When SRAM Destination 0.160 0.143 0.143
card is used Source 0.180 0.162 0.162
Word
(Q3MEM-4MBS, Destination 0.160 0.143 0.143
Q3MEM-8MBS) Source 0.340 0.314 0.314
Double word
Destination 0.320 0.304 0.304
Source 11.700 11.200 11.200
Bit
Destination 15.400 15.300 15.300
Module access device Source 9.460 9.410 9.410
Word
(Un\G , U3En\G0 to G4095) Destination 19.000 19.000 19.000
Source 11.000 10.900 10.900
Double word
Destination 18.800 18.700 18.700
Source 32.700 31.300 31.300
Bit
Destination 52.300 29.900 29.900
Link direct device Source 28.500 17.300 17.300
Word
(Jn\ ) Destination 27.500 14.700 14.700
Source 30.300 18.100 18.100
Double word
Destination 30.600 15.700 15.700

App-113
 Appendix 1.5 Operation Processing Time of LCPU
The processing time for the individual instructions are shown in the table on the following pages.
Operation processing times can vary substantially depending on the nature of the sources and
destinations of the instructions, and the values contained in the following tables should therefore
be taken as a set of general guidelines to processing time rather than as being strictly accurate.

Appendix 1.5.1 Subset instruction processing time

The following describes the subset instruction processing time.

1. The subset instruction processing time table shown in (1) applies when the device
used in an instruction satisfies either of the conditions.
(See section 3.5.1 for the device conditions for subset instruction processing.)
2. When using the file register or a module access device (U3En\G10000 or higher),
add the processing time for each instruction, with reference to the adding time in (2).
3. When using an F,T(ST),C device with an OUT/SET/RST instruction, add the
processing time for each instruction, with reference to the adding time in (3).
4. Since the processing time of each instruction is not constant due to the cache
function in the LCPU, the minimum value and the maximum value are described.

(1) Subset instruction processing time table

(a) When using L02CPU, L26CPU-BT.
Processing Time (µs)
Category Instruction Condition (Device) L02CPU L26CPU-BT
Min. Max. Min. Max.
LD
LDI
AND
ANI
OR
ORI
When executed 0.040 0.0095
LDP
LDF
ANDP
ANDF
ORP
ORF
LDPI
Sequence When executed 0.120 0.0285
LDFI
instruction
ANDPI
ANDFI
When executed 0.160 0.038
ORPI
ORFI
When not changed
OUT 0.040 0.0095
When changed
When not changed
OUT H 0.040 0.0095
When changed
When not executed
SET
When not changed 0.040 0.0095
RST When executed
When changed

App-114
 Processing Time (µs)
Category Instruction Condition (Device) L02CPU L26CPU-BT
Min. Max. Min. Max.
8
In conductive status
LD= 0.120 0.0285
In non-conductive status
When not executed
8
AND= In conductive status 0.120 0.0285
When executed
In non-conductive status
When not executed
8
OR= In conductive status 0.120 0.0285
When executed
In non-conductive status
In conductive status
8
LD<> 0.120 0.0285
In non-conductive status
When not executed
AND<> In conductive status 0.120 0.0285
A
When executed
In non-conductive status
When not executed
OR<> In conductive status 0.120 0.0285 6
When executed
In non-conductive status
In conductive status
LD>
In non-conductive status
0.120 0.0285 7
When not executed
AND> In conductive status 0.120 0.0285
When executed
In non-conductive status 8
When not executed
OR> In conductive status 0.120 0.0285
When executed
Basic In non-conductive status
instruction In conductive status

Appendix 1.5 Operation Processing Time of LCPU

Appendix1 OPERATION PROCESSING TIME
LD<= 0.120 0.0285
In non-conductive status
When not executed
AND<= In conductive status 0.120 0.0285
When executed
In non-conductive status
When not executed
OR<= In conductive status 0.120 0.0285
When executed
In non-conductive status
In conductive status
LD< 0.120 0.0285
In non-conductive status
When not executed
AND< In conductive status 0.120 0.0285
When executed
In non-conductive status
When not executed
OR< In conductive status 0.120 0.0285
When executed
In non-conductive status
In conductive status
LD>= 0.120 0.0285
In non-conductive status
When not executed
AND>= In conductive status 0.120 0.0285
When executed
In non-conductive status
When not executed
OR>= In conductive status 0.120 0.0285
When executed
In non-conductive status

App-115
 Processing Time (µs)
Category Instruction Condition (Device) L02CPU L26CPU-BT
Min. Max. Min. Max.
In conductive status
LDD= 0.120 0.0285
In non-conductive status
When not executed
ANDD= In conductive status 0.120 0.0285
When executed
In non-conductive status
When not executed
ORD= In conductive status 0.120 0.0285
When executed
In non-conductive status
In conductive status
LDD<> 0.120 0.0285
In non-conductive status
When not executed
ANDD<> In conductive status 0.120 0.0285
When executed
In non-conductive status
When not executed
ORD<> In conductive status 0.120 0.0285
When executed
In non-conductive status
In conductive status
LDD> 0.120 0.0285
In non-conductive status
When not executed
ANDD> In conductive status 0.120 0.0285
When executed
In non-conductive status
When not executed
ORD> In conductive status 0.120 0.0285
When executed
Basic In non-conductive status
instruction In conductive status
LDD<= 0.120 0.0285
In non-conductive status
When not executed
ANDD<= In conductive status 0.120 0.0285
When executed
In non-conductive status
When not executed
ORD<= In conductive status 0.120 0.0285
When executed
In non-conductive status
In conductive status
LDD< 0.120 0.0285
In non-conductive status
When not executed
ANDD< In conductive status 0.120 0.0285
When executed
In non-conductive status
When not executed
ORD< In conductive status 0.120 0.0285
When executed
In non-conductive status
In conductive status
LDD>= 0.120 0.0285
In non-conductive status
When not executed
ANDD>= In conductive status 0.120 0.0285
When executed
In non-conductive status
When not executed
ORD>= In conductive status 0.120 0.0285
When executed
In non-conductive status

App-116
 Processing Time (µs)
Category Instruction Condition (Device) L02CPU L26CPU-BT
Min. Max. Min. Max.
8
+ S D When executed 0.120 0.0285

+ S1 S2 D When executed 0.160 0.038 8

- S D When executed 0.120 0.0285

- S1 S2 D When executed 0.160 0.038

8
D+ S D When executed 0.120 0.0285

When executed 0.160 0.038

D + S1 S2 D
8
D- S D When executed 0.120 0.0285

D - S1 S2 D When executed 0.160 0.038

When executed 0.180 0.057

A
* S1 S2 D

/ S1 S2 D When executed 0.280 0.105

D * S1 S2 D When executed 0.260 0.095

6
D/ S1 S2 D When executed 0.400 0.162

B+ S D When executed 3.100 6.800 2.900 4.100 7

B + S1 S2 D When executed 4.800 8.900 4.200 5.900

B- S D When executed 3.100 6.800 2.900 4.100 8

B - S1 S2 D When executed 4.800 8.900 4.200 4.600

B * S1 S2 D When executed 3.900 7.400 3.400 4.800

Basic
B/ S1 S2 D When executed 3.900 8.500 3.700 5.200

Appendix 1.5 Operation Processing Time of LCPU

Appendix1 OPERATION PROCESSING TIME
instruction

Single S = 0, D =0 0.180 0.057

E+ S D
precision
S = 2127, D = 2127 0.180 0.057

Single S1 = 0, S2 =0 0.220 0.0665

E + S1 S2 D
precision
S1 = 2127, S2 = 2127 0.220 0.0665

Single S = 0, D =0 0.180 0.057

E- S D
precision
S = 2127, D = 2127 0.180 0.057

Single S1 = 0, S2 =0 0.220 0.0665

E - S1 S2 D
precision
S1 = 2127, S2 = 2127 0.220 0.0665

Single S1 = 0, S2 =0 0.180 0.057

E * S1 S2 D
precision
S1 = 2127, S2 = 2127 0.180 0.057

Single
E/ S1 S2 D
precision S1 = 2127, S2 = 2127 3.900 8.500 0.285

INC When executed 0.080 0.019

DINC When executed 0.080 0.019
DEC When executed 0.080 0.019
DDEC When executed 0.080 0.019
BCD When executed 0.160 0.057
DBCD When executed 0.240 0.095
BIN When executed 0.100 0.0285
DBIN When executed 0.100 0.0285

App-117
 Processing Time (µs)
Category Instruction Condition (Device) L02CPU L26CPU-BT
Min. Max. Min. Max.

Single S =0 0.100 0.0475

FLT
precision 0.140 0.0475
S = 7FFFH
Single S =0 0.140 0.0475
DFLT
precision 0.140 0.0475
S = 7FFFFFFFH
Single S =0 0.140 0.0475
INT
precision 0.140 0.0475
S = 32766.5
Single S =0 0.140 0.0475
DINT
precision 0.140 0.0475
S = 1234567890.3
MOV – 0.080 0.019
DMOV – 0.080 0.019
EMOV – 0.080 0.019
CML – 0.080 0.019
Basic DCML – 0.080 0.019
instruction SM237= n=1 3.600 4.100 2.900 3.200
ON n=96 4.500 4.700 3.400 3.700
BMOV
SM237= n=1 5.000 7.400 4.200 5.500
OFF n=96 6.000 7.900 4.700 6.000
SM237= n=1 5.900 6.800 2.800 3.200
ON n=96 6.300 11.000 3.000 5.200
FMOV
SM237= n=1 7.000 8.000 3.400 3.800
OFF n=96 5.200 6.900 3.600 5.800
XCH – 2.100 4.100 1.800 2.300
DXCH – 2.200 4.200 2.100 2.900
SM237= n=1 2.000 3.200 1.750 1.750
ON n=96 5.600 6.100 3.650 4.150
DFMOV
SM237= n=1 2.900 4.600 2.250 3.150
OFF n=96 6.100 8.200 4.200 5.500
CJ –– 2.100 2.900 1.100 2.400
SCJ –– 2.100 2.900 1.100 2.400
JMP –– 2.100 2.900 1.100 2.400

WAND S D When executed 0.120 0.0285

WAND S1 S2 D When executed 0.160 0.038

DAND S D When executed 0.120 0.0285

DAND S1 S2 D When executed 0.160 0.038

WOR S D When executed 0.120 0.0285

WOR S1 S2 D When executed 0.160 0.038

DOR S D When executed 0.120 0.0285

Application DOR S1 S2 D When executed 0.160 0.038

instruction When executed 0.120 0.0285
WXOR S D

WXOR S1 S2 D When executed 0.160 0.038

DXOR S D When executed 0.120 0.0285

DXOR S1 S2 D When executed 0.160 0.038

WXNR S D When executed 0.120 0.0285

WXNR S1 S2 D When executed 0.160 0.038

DXNR S D When executed 0.120 0.0285

DXNR S1 S2 D When executed 0.160 0.038

App-118
 Processing Time (µs)
Category Instruction Condition (Device) L02CPU L26CPU-BT
Min. Max. Min. Max.
8
n=1 2.200 4.900 1.700 2.500
ROR D n
n = 15 2.200 4.900 1.700 2.500
n=1 2.100 4.800 1.700 3.200
8
RCR D n
n = 15 2.100 4.800 1.700 3.200
n=1 2.100 4.800 1.800 3.200
ROL D n
n = 15 2.100 4.800 1.800 3.200
8
n=1 2.100 5.200 1.800 2.200
RCL D n
n = 15 2.100 5.200 1.800 2.200
n=1 2.200 5.200 1.900 2.700
8
DROR D n
n = 31 2.200 5.200 1.900 2.700
n=1 2.200 5.900 1.900 4.200
DRCR D n
n = 31 2.200 5.900 1.900 4.200
A
n=1 2.200 4.900 1.800 3.300
DROL D n
n = 31 2.200 4.900 1.800 3.300
n=1 2.200 5.900 1.900 3.800 6
DRCL D n
Application n = 31 2.200 5.900 1.900 3.800
instruction n=1 2.200 4.600 1.700 2.600
SFR D n
n = 15 2.200 4.600 1.700 2.600 7
n=1 2.200 4.600 1.800 2.700
SFL D n
n = 15 2.200 4.600 1.800 2.700
n=1 2.200 6.100 2.200 4.300 8
DSFR D n
n = 96 33.400 38.100 23.900 26.100
n=1 2.200 6.100 2.100 4.000
DSFL D n
n = 96 33.500 38.000 23.700 25.800
=0 3.000 4.800 2.900 3.600

Appendix 1.5 Operation Processing Time of LCPU

Appendix1 OPERATION PROCESSING TIME
S
SUM
S = FFFFH 3.000 4.900 2.900 3.600
SEG When executed 1.700 3.600 1.500 2.100
FOR – 1.300 3.200 0.870 2.100
Internal file pointer 2.600 4.000 2.300 3.600
CALL Pn
Common pointer 4.600 13.500 3.200 4.900

CALL Pn S1 to S5 – 31.200 36.000 26.100 29.300

Remark
For the instructions for which a leading edge instruction ( P) is not described,
the processing time is the same as an ON execution instruction.
Example MOVP instruction, WANDP instruction etc.

App-119
 (2) Table of the time to be added when file register is used

(a) When using L02CPU, L26CPU-BT.

Device Specification Processing Time (µs)
Device name data
Location L02CPU L26CPU-BT
Source 0.100 0.048
Bit
Destination 0.220 0.038
When standard Source 0.100 0.048
File register (R) Word
RAM is used Destination 0.100 0.038
Source 0.200 0.095
Double word
Destination 0.200 0.086
Source 0.140 0.057
Bit
Destination 0.280 0.048
File register (ZR),
When standard Source 0.140 0.057
Extended data register (D), Word
RAM is used Destination 0.140 0.048
Extended link register (W)
Source 0.240 0.105
Double word
Destination 0.240 0.095

(3) Table of the time to be added when F/T(ST)/C device is used in OUT/SET/RST instruction

(a) When using L02CPU, L26CPU-BT.

Processing Time (µs)
Instruction name Device name Condition
L02CPU L26CPU-BT
When not executed 2.000 1.570
F When displayed 53.100 38.090
When executed
Display completed 53.000 37.980
OUT
When not executed 0.120 0.030
T(ST), C After time up 0.120 0.030
When executed
When added 0.120 0.030
When not executed 0.040 0.010
SET F When displayed 52.000 40.600
When executed
Display completed 43.600 37.900
When not executed 0.040 0.010
F When displayed 45.700 36.600
When executed
RST Display completed 19.000 16.190
When not executed 0.120 0.030
T(ST), C
When executed 0.120 0.030

App-120
Appendix 1.5.2 Processing time of instructions other than subset instruction
8
The following table shows the processing time of instructions other than subset instructions.

(1) Table of the processing time of instructions other than subset instructions
(a) When using L02CPU, L26CPU-BT
8
Processing Time (µs)
Category Instruction Condition (Device) L02CPU L26CPU-BT 8
Min. Max. Min. Max.
ANB
ORB
MPS – 0.040 0.0095
8
MRD
MPP

INV
When not executed
0.040 0.0095
A
When executed
MEP When not executed
MEF When executed
0.040 0.0095
6
EGP When not executed
0.040 0.0095
EGF When executed
PLS – 1.600 1.700 0.890 1.200 7
PLF – 1.600 1.700 0.890 1.200
Sequence
When not executed 0.080 0.0185
FF
instruction
When executed 1.500 1.500 0.790 0.910 8
When not executed 0.080 0.0185
DELTA
When executed 2.700 6.800 2.400 3.200
When not executed 0.080 0.0185
SFT
When executed 1.700 4.300 1.100 2.700

Appendix 1.5 Operation Processing Time of LCPU

Appendix1 OPERATION PROCESSING TIME
MC – 0.080 0.0185
MCR – 0.040 0.0185
FEND Error check performed 170.000 210.000 130.000 170.000
END No error check performed 170.000 210.000 130.000 170.000
STOP – – –
NOP
NOPLF – 0.040 0.0095
PAGE

App-121
 Processing Time (µs)
Category Instruction Condition (Device) L02CPU L26CPU-BT
Min. Max. Min. Max.
Single In conductive status 3.900 10.000 0.0285
LDE=
precision In non-conductive status 3.900 10.000
0.0285
When not executed 0.120
Single
ANDE= When In conductive status 3.400 9.300 0.0285
precision
executed In non-conductive status 3.400 9.300 0.0285
When not executed 0.120 0.0285
Single
ORE= When In conductive status 3.500 8.500 0.0285
precision
executed In non-conductive status 3.500 8.500 0.0285
Single In conductive status 3.900 10.000 0.0285
LDE< >
precision In non-conductive status 3.900 10.000 0.0285
When not executed 0.120 0.0285
Single
ANDE< > When In conductive status 3.400 9.300 0.0285
precision
executed In non-conductive status 3.400 9.300 0.0285
When not executed 0.120 0.0285
Single
ORE< > When In conductive status 3.500 8.500 0.0285
precision
executed In non-conductive status 3.500 8.500 0.0285
Single In conductive status 3.900 10.000 0.0285
LDE>
precision In non-conductive status 3.900 10.000 0.0285
When not executed 0.120 0.0285
Single
Basic ANDE> When In conductive status 3.400 9.300 0.0285
precision
instruction executed In non-conductive status 3.400 9.300 0.0285
When not executed 0.120 0.0285
Single
ORE> When In conductive status 3.500 8.500 0.0285
precision
executed In non-conductive status 3.500 8.500 0.0285
Single In conductive status 3.900 10.000 0.0285
LDE<=
precision In non-conductive status 3.900 10.000 0.0285
When not executed 0.120 0.0285
Single
ANDE<= When In conductive status 3.400 9.300 0.0285
precision
executed In non-conductive status 3.400 9.300 0.0285
When not executed 0.120 0.0285
Single
ORE<= When In conductive status 3.500 8.500 0.0285
precision
executed In non-conductive status 3.500 8.500 0.0285
Single In conductive status 3.900 10.000 0.0285
LDE<
precision In non-conductive status 3.900 10.000 0.0285
When not executed 0.120 0.0285
Single
ANDE< When In conductive status 3.400 9.300 0.0285
precision
executed In non-conductive status 3.400 9.300 0.0285
When not executed 0.120 0.0285
Single
ORE< When In conductive status 3.500 8.500 0.0285
precision
executed In non-conductive status 3.500 8.500 0.0285

App-122
 Processing Time (µs)
Category Instruction Condition (Device) L02CPU L26CPU-BT
Min. Max. Min. Max.
8
Single In conductive status 3.900 10.000 0.0285
LDE>=
precision In non-conductive status 3.900 10.000 0.0285
When not executed 0.120 0.0285
8
Single
ANDE>= When In conductive status 3.400 9.300 0.0285
precision
executed In non-conductive status 3.400 9.300 0.0285
When not executed 0.120 0.0285
8
Single
ORE>= When In conductive status 3.500 8.500 0.0285
precision
executed In non-conductive status 3.500 8.500 0.0285
Double In conductive status 4.800 16.000 3.500 9.000
8
LDED=
precision In non-conductive status 4.800 16.000 3.500 9.000
When not executed 0.120 0.0285
ANDED=
Double
When In conductive status 4.400 15.100 3.200 7.500
A
precision
executed In non-conductive status 4.400 15.100 3.200 7.500
When not executed 0.120 0.0285
ORED=
Double
When In conductive status 4.500 14.900 3.400 9.200 6
precision
executed In non-conductive status 4.500 14.900 3.400 9.200
Double In conductive status 4.800 16.000 3.500 9.000
LDED<>
precision In non-conductive status 4.800 16.000 3.500 9.000 7
When not executed 0.120 0.0285
Double
Basic ANDED<> When In conductive status 4.400 15.100 3.200 7.500
instruction
precision
executed In non-conductive status 4.400 15.100 3.200 7.500 8
When not executed 0.120 0.0285
Double
ORED<> When In conductive status 4.500 14.900 3.400 9.200
precision
executed In non-conductive status 4.500 14.900 3.400 9.200
Double In conductive status 4.800 16.000 3.500 9.000

Appendix 1.5 Operation Processing Time of LCPU

Appendix1 OPERATION PROCESSING TIME
LDED>
precision In non-conductive status 4.800 16.000 3.500 9.000
When not executed 0.120 0.0285
Double
ANDED> When In conductive status 4.400 15.100 3.200 7.500
precision
executed In non-conductive status 4.400 15.100 3.200 7.500
When not executed 0.120 0.0285
Double
ORED> When In conductive status 4.500 14.900 3.400 9.200
precision
executed In non-conductive status 4.500 14.900 3.400 9.200
Double In conductive status 4.800 16.000 3.500 9.000
LDED<=
precision In non-conductive status 4.800 16.000 3.500 9.000
When not executed 0.120 0.0285
Double
ANDED<= When In conductive status 4.400 15.100 3.200 7.500
precision
executed In non-conductive status 4.400 15.100 3.200 7.500
When not executed 0.120 0.0285
Double
ORED<= When In conductive status 4.500 14.900 3.400 9.200
precision
executed In non-conductive status 4.500 14.900 3.400 9.200

App-123
 Processing Time (µs)
Category Instruction Condition (Device) L02CPU L26CPU-BT
Min. Max. Min. Max.
Double In conductive status 4.800 16.000 3.500 9.000
LDED<
precision In non-conductive status 4.800 16.000 3.500 9.000
When not executed 0.120 0.0285
Double
ANDED< When In conductive status 4.400 15.100 3.200 7.500
precision
executed In non-conductive status 4.400 15.100 3.200 7.500
When not executed 0.120 0.0285
Double
ORED< When In conductive status 4.500 14.900 3.400 9.200
precision
executed In non-conductive status 4.500 14.900 3.400 9.200
Double In conductive status 4.800 16.000 3.500 9.000
LDED>=
precision In non-conductive status 4.800 16.000 3.500 9.000
When not executed 0.120 0.0285
Double
ANDED>= When In conductive status 4.400 15.100 3.200 7.500
precision
executed In non-conductive status 4.400 15.100 3.200 7.500
When not executed 0.120 0.0285
Double
ORED>= When In conductive status 4.500 14.900 3.400 9.200
precision
executed In non-conductive status 4.500 14.900 3.400 9.200
In conductive status 5.600 17.100 4.200 8.200
LD$=
In non-conductive status 5.600 17.100 4.200 8.200
When not executed 0.120 0.0285
AND$= In conductive status 5.300 16.400 3.900 7.300
When executed
In non-conductive status 5.300 16.400 3.900 7.300
When not executed 0.120 0.0285
Basic
OR$= In conductive status 5.200 15.700 4.000 7.600
instruction When executed
In non-conductive status 5.200 15.700 4.000 7.600
In conductive status 5.600 17.100 4.200 8.200
LD$< >
In non-conductive status 5.600 17.100 4.200 8.200
When not executed 0.120 0.0285
AND$< > In conductive status 5.300 16.400 3.900 7.300
When executed
In non-conductive status 5.300 16.400 3.900 7.300
When not executed 0.120 0.0285
OR$< > In conductive status 5.200 15.700 4.000 7.600
When executed
In non-conductive status 5.200 15.700 4.000 7.600
In conductive status 5.600 17.100 4.200 8.200
LD$>
In non-conductive status 5.600 17.100 4.200 8.200
When not executed 0.120 0.0285
AND$> In conductive status 5.300 16.400 3.900 7.300
When executed
In non-conductive status 5.300 16.400 3.900 7.300
When not executed 0.120 0.0285
OR$> In conductive status 5.200 15.700 4.000 7.600