UNIT V SYNCHRONOUS AND AYNCHRONOUS SEQUENTIAL CIRCUITS

Synchronous Sequential Circuits: General Model – Classification – Design – Use of

Algorithmic State Machine – Analysis of Synchronous Sequential Circuits
Asynchronous Sequential Circuits: Design of fundamental mode and pulse mode
circuits – Incompletely specified State Machines – Problems in Asynchronous Circuits –
Design of Hazard Free Switching circuits. Design of Combinational and Sequential
circuits using VERILOG
 5.1 General Model
The Mealy model: the outputs are functions of both the present state and inputs
● The outputs may change if the inputs change during the clock pulse
period.
♦ The outputs may have momentary false values unless the inputs are
synchronized with the clocks.
 The Moore model: the outputs are functions of the present state only
● The outputs are synchronous with the clocks.

Mealy Moore

Present I/P Next output Present I/P Next output

state state state state
A B X A B y A B X A B y
0 0 0 0 0 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 1 0 1 0
0 1 0 0 0 1 0 1 0 0 1 0
0 1 1 1 1 0 0 1 1 1 0 0
1 0 0 0 0 1 1 0 0 1 0 0
1 0 1 1 0 0 1 0 1 1 1 0
1 1 0 0 0 1 1 1 0 1 1 1
1 1 1 1 0 0 1 1 1 0 0 1

In Mealy: For the same state, the output changes with the input.
In Moore: For the same state, the output does not change with the input
 Moore State Diagram

0 0
1
00/0 01/0

1 1

11/1 10/0
1
0 0
State Reduction and Assignment

 State Reduction Reductions on the number of flip-flops and the number of gates.
● A reduction in the number of states may result in a reduction in the number of flip-
flops.
● An example state diagram showing in Fig
 State: a a b c d e f f g f g a
Input: 0 1 0 1 0 1 1 0 1 0 0
Output: 0 0 0 0 0 1 1 0 1 0 0

● Only the input-output sequences are important.

● Two circuits are equivalent
♦ Have identical outputs for all input sequences;
♦ The number of states is not important.

 Equivalent states
● Two states are said to be equivalent
♦ For each member of the set of inputs, they give exactly the same output and
send the circuit to the same state or to an equivalent state.
♦ One of them can be removed.
STATE TABLE:
Present Next state Output
state X=0 X=1 X=0 X=1
a a b 0 0
b c d 0 0
c a d 0 0
d e f 0 1
e a f 0 1
f g f 0 1
g a f 0 1

 Reducing the state table

● e = g (remove g);
● d = f (remove f);

REDUCING STATE TABLE:

Present Next state Output

state X=0 X=1 X=0 X=1
a a b 0 0
b c d 0 0
c a d 0 0
d e f 0 1
e a f 0 1
f e f 0 1

THE REDUCED FINITE STATE MACHINE

REDUCED STATE TABLE:

Present Next state Output

state X=0 X=1 X=0 X=1
a a b 0 0
b c d 0 0
c a d 0 0
d e d 0 1
e a d 0 1

STATE: a a b c d e d d e d e a
INPUT: 0 1 0 1 0 1 1 0 1 0 0
OUTPUT: 0 0 0 0 0 1 1 0 1 0 0
 ● The checking of each pair of states for possible equivalence can be done systematically
using Implication Table.
● The unused states are treated as don't-care condition  fewer combinational gates.

REDUCED STATE TABLE:

Present Next state Output

state X=0 X=1 X=0 X=1
a a b 0 0
b c d 0 0
c a d 0 0
d e d 0 1
e a d 0 1

Implication Table
 The state-reduction procedure for completely specified state tables is based on the
algorithm that two states in a state table can be combined into one if they can be shown to
be equivalent. There are occasions when a pair of states do not have the same next states,
but, nonetheless, go to equivalent next states. Consider the following state table:

Present Next state Output

state X=0 X=1 X=0 X=1
a c b 0 1
b d a 0 1
c a d 1 0
d b d 1 0
• (a, b) imply (c, d) and (c, d) imply (a, b). Both pairs of states are equivalent; i.e., a and b are
equivalent as well as c and d.
 The checking of each pair of states for possible equivalence in a table with a large number
of states can be done systematically by means of an implication table. This a chart that
consists of squares, one for every possible pair of states, that provide spaces for listing any
possible implied states. Consider the following state table:

Present Next state Output

state X=0 X=1 X=0 X=1
a d b 0 0
b e a 0 0
c g f 0 1
d a d 1 0
e a d0 1 0
f c b 0 0
g a e 1 0

 The implication table is:

b  d,e
x x
x x x
x x x
c,d x c,e x x x x
a,b
x x x d,e d,e x
a b c d e f

 On the left side along the vertical are listed all the states defined in the state table except
the last, and across the bottom horizontally are listed all the states except the last.
 The states that are not equivalent are marked with a ‘x’ in the corresponding square,
whereas their equivalence is recorded with a ‘√’.
 Some of the squares have entries of implied states that must be further investigated to
determine whether they are equivalent or not.
 The step-by-step procedure of filling in the squares is as follows:
 1. Place a cross in any square corresponding to a pair of states whose outputs are not
equal for every input.
2. Enter in the remaining squares the pairs of states that are implied by the pair of
states representing the squares. We do that by starting from the top square in the left
column and going down and then proceeding with the next column to the right.
3. Make successive passes through the table to determine whether any additional
squares should be marked with a ‘x’. A square in the table is crossed out if it
contains at least one implied pair that is not equivalent.
4. Finally, all the squares that have no crosses are recorded with check marks. The
equivalent states are: (a, b), (d, e), (d, g), (e, g).

We now combine pairs of states into larger groups of equivalent states. The last three pairs can be
combined into a set of three equivalent states (d, e,g) because each one of the states in the group is
equivalent to the other two. The final partition of these states consists of the equivalent states
found from the implication table, together with all the remaining states in the state table that are
not equivalent to any other state:
(a, b) (c) (d, e, g) (f)
The reduced state table is:

Present Next state Output

state X=0 X=1 X=0 X=1
a d a 0 0
c d f 0 1
d a d 1 0
f c a 0 0

State Assignment
 State Assignment
 To minimize the cost of the combinational circuits.
● Three possible binary state assignments. (m states need n-bits, where 2n > m)
THREE POSSIBLE BINARY STATE ASSIGNMENTS:

State Assignment 1, Assignment 2, Assignment 3,

Binary Gray code One-Hot
a 000 000 000
b 001 001 00010
c 010 011 00100
d 011 010 01000
e 100 110 10000

● Any binary number assignment is satisfactory as long as each state is assigned a unique
number.
● Use binary assignment 1.
 REDUCED STATE TABLE WITH BINARY ASSIGNMENT1:

Present Next state Output

state X=0 X=1 X=0 X=1
000 000 00 0 0
001 010 011 0 0
010 000 011 0 0
011 100 011 0 1
100 000 011 0 1

 Design Procedure for sequential circuit

● The word description of the circuit behavior to get a state diagram;
● State reduction if necessary;
● Assign binary values to the states;
● Obtain the binary-coded state table;
● Choose the type of flip-flops;
● Derive the simplified flip-flop input equations and output equations;
● Draw the logic diagram;

 Example:
Detect 3 or more consecutive 1’s

0 1
S0 / 0 S1 / 0
0

0 1
0

S3 / 1 S2 / 0
1 1

STATE A B
 S0 0 0
S1 0 0
S2 1 0
S3 1 1

STATE TABLE:

PRESENT STATE INPUT NEXT STATE OUTPUT

A B x A B y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 0
0 1 1 1 0 0
1 0 0 0 0 0
1 0 1 1 1 0
1 1 0 0 0 1
1 1 1 1 1 1

Synthesis using D Flip-Flops

A(t+1) = DA (A, B, x)
= ∑ (3, 5, 7)
B(t+1) = DB (A, B, x)
= ∑ (1, 5, 7)
y (A, B, x) = ∑ (6, 7)

K MAP SIMPLIFICATION

B B
0 0 1 0 0 1 0 0
A 0 1 1 0 A 0 1 1 0
x x

0 0 0 0
0 0 1 1
A
DA (A, B, x) = ∑ (3, 5, 7)
=Ax+Bx
DB (A, B, x) = ∑ (1, 5, 7)
= A x + B’ x
y (A, B, x) = ∑ (6, 7)
=AB

D Q A
x

Q
y

D Q B

CLK Q
Sequential circuit design
• Now let’s reverse the process: In sequential circuit design, we turn some description into a
working circuit.
– We first make a state table or diagram to express the computation.
– Then we can turn that table or diagram into a sequential circuit.

Sequence recognizers
• A sequence recognizer is a special kind of sequential circuit that looks for a special bit
pattern in some input.
• The recognizer circuit has only one input, X.
– One bit of input is supplied on every clock cycle. For example, it would take 20
cycles to scan a 20-bit input.
– This is an easy way to permit arbitrarily long input sequences.
• There is one output, Z, which is 1 when the desired pattern is found.
• Our example will detect the bit pattern “1001”:
Inputs: 1 1 1 0 0 1 1 0 1 0 0 1 0 0 1 1 0 …
Outputs: 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 …
Here, one input and one output bit appear every clock cycle.
• This requires a sequential circuit because the circuit has to “remember” the inputs from
previous clock cycles, in order to determine whether or not a match was found.
A basic state diagram
• What state do we need for the sequence recognizer?
– We have to “remember” inputs from previous clock cycles.
– For example, if the previous three inputs were 100 and the current input is 1, then
the output should be 1.
– In general, we will have to remember occurrences of parts of the desired pattern—
in this case, 1, 10, and 100.
• We’ll start with a basic state diagram (edges are labeled input/output):

1/0 0/0 0/0

A B C D

State Meaning
A None of the desired pattern (1001) has been input yet.
B We’ve already seen the first bit (1) of the desired pattern.
C We’ve already seen the first two bits (10) of the desired pattern.
D We’ve already seen the first three bits (100) of the desired pattern.
Overlapping occurrences of the pattern
• What happens if we’re in state D (the last three inputs were 100), and the current input is 1?
– The output should be a 1, because we’ve found the desired pattern.
– But this last 1 could also be the start of another occurrence of the pattern! For
example, 1001001 contains two occurrences of 1001.
– To detect overlapping occurrences of the pattern, the next state should be B.
1/0 0/0 0/0
A B C D

1/1

State Meaning
A None of the desired pattern (1001) has been input yet.
B We’ve already seen the first bit (1) of the desired pattern.
C We’ve already seen the first two bits (10) of the desired pattern.
D We’ve already seen the first three bits (100) of the desired pattern.
Filling in the other arrows
• Remember that we need two outgoing arrows for each node, to account for the possibilities
of X=0 and X=1.
• The remaining arrows we need are shown in blue. They also allow for the correct detection
of overlapping occurrences of 1001.
0/0
1/0

1/0 0/0 0/0

A B C D
1/0

0/0 1/1

State Meaning
A None of the desired pattern (1001) has been input yet.
B We’ve already seen the first bit (1) of the desired pattern.
C We’ve already seen the first two bits (10) of the desired pattern.
D We’ve already seen the first three bits (100) of the desired pattern.
Finally, making the state table
0/0
1/0

1/0 0/0 0/0

A B C D
1/0

0/0 1/1
Remember how the state diagram arrows correspond to rows of the state table:

Present Input Next Output

State State
A 0 A 0
A 1 B 0
B 0 C 0
B 1 B 0
C 0 D 0
C 1 B 0
D 0 A 0
D 1 B 1

Sequential circuit design procedure

Step 1: Make a state table based on the problem statement. The table should show the
present states, inputs, next states and outputs. (It may be easier to find a state diagram first, and
then convert that to a table.)
Step 2: Assign binary codes to the states in the state table, if you haven’t already. If you have n
states, your binary codes will have at least log2 n digits, and your circuit will have at least log2
n flip-flops.
Step 3: For each flip-flop and each row of your state table, find the flip-flop input values that are
needed to generate the next state from the present state. You can use flip-flop excitation tables
here.
Step 4: Find simplified equations for the flip-flop inputs and the outputs.
Step 5: Build the circuit!

Step 2: Assigning binary codes to states

• We have four states ABCD, so we need at least two flip-flops Q1Q0.
• The easiest thing to do is represent state A with Q1Q0 = 00, B with 01, C with 10, and D
with 11.
• The state assignment can have a big impact on circuit complexity, but we won’t worry
about that too much in this class.
 Present Next
Present Input Next Output Input Output
State State State State
A 0 A 0 Q1 Q0 X Q1 Q0 Z
A 1 B 0 0 0 0 0 0 0
B 0 C 0 0 0 1 0 1 0
B 1 B 0  0 1 0 1 0 0
C 0 D 0 0 1 1 0 1 0
C 1 B 0 1 0 0 1 1 0
D 0 A 0 1 0 1 0 1 0
D 1 B 1 1 1 0 0 0 0
1 1 1 0 1 1

Step 3: Finding flip-flop input values

• Next we have to figure out how to actually make the flip-flops change from their present
state into the desired next state.
• This depends on what kind of flip-flops you use!
• We’ll use two JKs. For each flip-flip Qi, look at its present and next states, and determine
what the inputs Ji and Ki should be in order to make that state change

Present Next
Input Flip Flop Inputs Output
State State
Q1 Q0 X Q1 Q0 J1 K1 J0 K0 Z
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 1 0 0
0 1 1 0 1 0
1 0 0 1 1 0
1 0 1 0 1 0
1 1 0 0 0 0
1 1 1 0 1 1
Finding JK flip-flop input values
• For JK flip-flops, this is a little tricky. Recall the characteristic table:

J K Q(t+1) Operation
0 0 Q(t) No Change
0 1 0 Reset
1 0 1 set
1 1 Q’(t) Complement

• If the present state of a JK flip-flop is 0 and we want the next state to be 1, then we have
two choices for the JK inputs:
– We can use JK=10, to explicitly set the flip-flop’s next state to 1.
– We can also use JK=11, to complement the current state 0.
• So to change from 0 to 1, we must set J=1, but K could be either 0 or 1.
• Similarly, the other possible state transitions can all be done in two different ways as well.

JK excitation table
An excitation table shows what flip-flop inputs are required in order to make a desired state
change

Q(t) Q(t+1) J K Operation

0 0 0 X No Change/Reset
0 1 1 X Set/Complement
1 0 X 1 Reset/Complement
1 1 X 0 No change/Set

• This is the same information that’s given in the characteristic table, but presented
“backwards.”
J K Q(t+1) Operation
0 0 Q(t) No Change
0 1 0 Reset
1 0 1 Set
1 1 Q’(t) Complement
 • We can now use the JK excitation table on the right to find the correct values
for each flip-flop’s inputs, based on its present and next states.
Present Next
Input Flip Flop Inputs Output
State State
Q1 Q0 X Q1 Q0 J1 K1 J0 K0 Z
0 0 0 0 0 0 X 0 X 0
0 0 1 0 1 0 X 1 X 0
0 1 0 1 0 1 X X 1 0
0 1 1 0 1 0 X X 0 0
1 0 0 1 1 X 0 1 X 0
1 0 1 0 1 X 1 1 X 0
1 1 0 0 0 X 1 X 1 0
1 1 1 0 1 X 1 X 0 1

Step 4: Find equations for the FF inputs and output

• Now you can make K-maps and find equations for each of the four flip-flop
inputs, as well as for the output Z.
• These equations are in terms of the present state and the inputs.
• The advantage of using JK flip-flops is that there are many don’t care
conditions, which can result in simpler MSP equations.

Present Next
Input Flip Flop Inputs Output
State State
Q1 Q0 X Q1 Q0 J1 K1 J0 K0 Z
0 0 0 0 0 0 X 0 X 0
0 0 1 0 1 0 X 1 X 0
0 1 0 1 0 1 X X 1 0
0 1 1 0 1 0 1 1 0 0
1 0 0 1 1 X 0 1 X 0
1 0 1 0 1 X 1 1 X 0
1 1 0 1 1 X 1 X 1 0
1 1 1 0 1 X 1 X 0 1

J1 = X’ Q0
K 1 = X + Q0
J0 = X + Q1
K0 = X’
Z = Q1Q0X
Step 5: Build the circuit
Lastly, we use these simplified equations to build the completed circuit.
Timing diagram
• Here is one example timing diagram for our sequence detector.
– The flip-flops Q1Q0 start in the initial state, 00.
– On the first three positive clock edges, X is 1, 0, and 0. These inputs cause Q1Q0 to
change, so after the third edge Q1Q0 = 11.
– Then when X=1, Z becomes 1 also, meaning that 1001 was found.
• The output Z does not have to change at positive clock edges. Instead, it may change
whenever X changes, since Z = Q1Q0X.

1 2 3 4
CLK
Q1
Q0
X
Z

Building the same circuit with D flip-flops

• What if you want to build the circuit using D flip-flops instead?
• We already have the state table and state assignments, so we can just start from Step 3,
finding the flip-flop input values.
• D flip-flops have only one input, so our table only needs two columns for D1 and D0.
Present Flip Flop
Input Next State Output
State inputs
Q1 Q0 X Q1 Q0 D1 D0 Z
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0
0 1 0 1 0 1 0 0
0 1 1 0 1 0 1 0
1 0 0 1 1 1 1 0
1 0 1 0 1 0 1 0
1 1 0 0 0 0 0 0
1 1 1 0 1 0 1 1
•
You can do K-maps again, to find:
D1 = Q1 Q0’ X’ + Q1’ Q0 X’
D0 = X + Q1 Q0’
Z = Q1 Q0 X

Present Flip Flop

Input Next State Output
State inputs
Q1 Q0 X Q1 Q0 D1 D0 Z
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0
0 1 0 1 0 1 0 0
0 1 1 0 1 0 1 0
1 0 0 1 1 1 1 0
1 0 1 0 1 0 1 0
1 1 0 0 0 0 0 0
1 1 1 0 1 0 1 1

D1 = Q1 Q0’ X’ + Q1’ Q0 X’
D0 = X + Q1 Q0’
The analysis of asynchronous sequential circuits
proceeds in much the same way as that of clocked

Synchronous and Asynchronous circuits

Sequential circuits are divided into two main types:
• Synchronous
• Asynchronous.

Their classification depends on the timing of their signals.

Synchronous sequential circuits change their states and output values at discrete instants of time,
which are specified by the rising
and falling edge of a free-running clock signal. The clock signal is generally some form of square
wave as shown in Figure below.
 Figure. Clock Signal
From the diagram you can see that the clock period is the time between successive
transitions in the same direction, that is, between two rising or two falling edges. State transitions
in synchronous sequential circuits are made to take place at times when the clock is making a
transition from 0 to 1 (rising edge) or from 1 to 0 (falling edge). Between successive clock pulses
there is no change in the information stored in memory.
The reciprocal of the clock period is referred to as the clock frequency. The clock width is
defined as the time during which the value of the clock signal is equal to 1. The ratio of the clock
width and clock period is referred to as the duty cycle. A clock signal is said to be active high if
the state changes occur at the clock's rising edge or during the clock width. Otherwise, the clock is
said to be active low. Synchronous sequential circuits are also known as clocked sequential
circuits.
The memory elements used in synchronous sequential circuits are usually flip-flops. These
circuits are binary cells capable of storing one bit of information. A flip-flop circuit has two
outputs, one for the normal value and one for the complement value of the bit stored in it. Binary
information can enter a flip-flop in a variety of ways, a fact which give rise to the different types of
flip-flops. For information on the different types of basic flip-flop circuits and their logical
properties, see the previous tutorial on flip-flops.
Asynchronous sequential circuits:Here the transition from one state to another is initiated
by the change in the primary inputs; there is no external synchronisation. The memory commonly
used in asynchronous sequential circuits are time-delayed devices, usually implemented by
feedback among logic gates. Thus, asynchronous sequential circuits may be regarded as
combinational circuits with feedback. Because of the feedback among logic gates, asynchronous
sequential circuits may, at times, become unstable due to transient conditions. The instability
problem imposes many difficulties on the designer. Hence, they are not as commonly used as
synchronous systems.
Design of Sequential Circuits
The design of a synchronous sequential circuit starts from a set of specifications and
culminates in a logic diagram or a list of Boolean functions from which a logic diagram can be
obtained. In contrast to a combinational logic, which is fully specified by a truth table, a sequential
circuit requires a state table for its specification. The first step in the design of sequential circuits is
to obtain a state table or an equivalence representation, such as a state diagram.
A synchronous sequential circuit is made up of flip-flops and combinational gates. The
design of the circuit consists of choosing the flip-flops and then finding the combinational
structure which, together with the flip-flops, produces a circuit that fulfils the required
specifications. The number of flip-flops is determined from the number of states needed in the
circuit.
The recommended steps for the design of sequential circuits are set out below.
Example:
Design a synchronous sequential circuit whose state diagram is shown. The type of flip-flop to be
use is J-K.

From the state diagram, we can generate the state table. Note that there is no output section for this
circuit. Two flip-flops are needed to represent the four states and are designated Q0Q1. The input
variable is labelled x.

State table.
Present State Next State
Q0 Q1 x=0 x=1
0 0 0 0 0 1
0 1 1 0 0 1
1 0 1 0 1 1
1 1 1 1 0 0

We shall now derive the excitation table and the combinational structure. The table is now
arranged in a different form, where the present state and input variables are arranged in the form of
a truth table. Remember, the excitable for the JK flip-flop was derive in
Excitation table for JK flip-flop

Output Transitions Flip Flop Inputs

Qn Qn+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

Excitation table of the circuit

Present State Next State Input Flip Flop Inputs

Q0 Q1 Q0 Q1 X J0 K0 J1 K1
0 0 0 0 0 0 X 0 X
0 0 0 1 1 0 X 1 X
0 1 1 0 0 1 X X 1
0 1 0 1 1 0 X X 0
1 0 1 0 0 X 0 0 X
1 0 1 1 1 X 0 1 X
1 1 1 1 0 X 0 X 0
1 1 0 0 1 X 1 X 1

In the first row, we have a transition for flip-flop Q0 from 0 in the present state to 0 in the next
state. In Table 10 we find that a transition of states from 0 to 0 requires that input J = 0 and input K
= X. So 0 and X are copied in the first row under J0 and K0 respectively. Since the first row also
shows a transition for the flip-flop Q1 from 0 in the present state to 0 in the next state, 0 and X are
copied in the first row under J1 and K1. This process is continued for each row of the table and for
each flip-flop, with the input conditions as specified in Table 10.
The simplified Boolean functions for the combinational circuit can now be derived. The input
variables are Q0, Q1, and x; the output are the variables J0, K0, J1 and K1. The information from
the truth table is plotted on the Karnaugh maps

Karnaugh Maps

The flip-flop input functions are derived:

J0 = Q1*x' K0 = Q1*x
J1 = x K1 = Q0'*x' + Q0*x = Q0x

The logic diagram is drawn

Analysis of Sequential Circuits

The behaviour of a sequential circuit is determined from the inputs, the outputs and the
states of its flip-flops. Both the output and the next state are a function of the inputs and the present
state.
The suggested analysis procedure of a sequential circuit is
 We start with the logic schematic from which we can derive excitation equations for each
flip-flop input. Then, to obtain next-state equations, we insert the excitation equations into the
characteristic equations. The output equations can be derived from the schematic, and once we
have our output and next-state equations, we can generate the next-state and output tables as well
as state diagrams. When we reach this stage, we use either the table or the state diagram to develop
a timing diagram which can be verified through simulation.
Example
Derive the next state, the output table and the state diagram for the sequential circuit shown

SOLUTION:
Excitation equations:
D0 = Cnt Q0 = Cnt'*Q0 + Cnt*Q0'
D0 = Cnt'*Q1 + Cnt*Q1'*Q0 + Cnt*Q1*Q0'
Next-state equations:
Q0(next) = D0 = Cnt'*Q0 + Cnt*Q0'
Q1(next) = D0 = Cnt'*Q1 + Cnt*Q1'*Q0 + Cnt*Q1*Q0'
In addition, however, we have computed the output equation.
Output equation: Y = Q1Q0
As this equation shows, the output Y will equal to 1 when the counter is in state Q1Q0 = 11, and it
will stay 1 as long as the counter stays in that state.
Next-state and output table:
Present State Next State Output
Q1 Q0 Cnt=0 Cnt=1 Z
0 0 0 0 0 1 0
0 1 0 1 1 0 0
1 0 1 0 1 1 0
1 1 1 1 0 0 1

State diagram:

Timing diagram:
Note that the counter will reach the state Q1Q0 = 11 only in the third clock cycle, so the output Y
will equal 1 after Q0 changes to 1. Since counting is disabled in the third clock cycle, the counter
will stay in the state Q1Q0 = 11 and Y will stay asserted in all succeeding clock cycles until
counting is enabled again.

Design a sequential circuit whose state tables are specified, using D flip-flops.

State table of a sequential circuit.

Present State Next State Output
Q0 Q1 x=0 x=1 x=0 x=1
0 0 0 0 0 1 0 0
0 1 0 0 1 0 0 0
1 0 1 1 1 0 0 0
1 1 0 0 0 1 0 1

Excitation table for a D flip-flop.

Flip Flop
Output Transitions
Inputs
Qn Qn+1 D
0 0 0
0 1 1
1 0 0
1 1 1

Next step is to derive the excitation table for the design circuit, which is. The output of the circuit
is labelled Z.
 Present State Next State Input Flip Flop Inputs Output
Q0 Q1 Q0 Q1 X D0 D1 Z
0 0 0 0 0 0 0 0
0 0 0 1 1 0 1 0
0 1 0 0 0 0 0 0
0 1 1 0 0 0 0 0
1 0 1 1 0 1 1 0
1 0 1 0 1 1 0 0
1 1 0 0 0 0 0 0
1 1 0 1 1 0 1 1

Excitation table

Now plot the flip-flop inputs and output functions on the Karnaugh map to derive the Boolean
expressions, which is shown

Karnaugh maps

The simplified Boolean expressions are:

D0 = Q0*Q1' + Q0'*Q1*x
D1 = Q0'*Q1'*x + Q0*Q1*x + Q0*Q1'*x'
Z = Q0*Q1*x
Finally, draw the logic diagram.

Hazards
In digital logic, a hazard in a system is an undesirable effect caused by either a deficiency
in the system or external influences. Logic hazards are manifestations of a problem in which
changes in the input variables do not change the output correctly due to some form of delay caused
by logic elements (NOT, AND, OR gates, etc.) This results in the logic not performing its function
properly. The three different most common kinds of hazards are usually referred to as static,
dynamic and function hazards.

Hazard is an unwanted transient i.e, spike or glitch that occurs due to unequal path or unequal
propagation delays.

Hazards are a temporary problem, as the logic circuit will eventually settle to the desired
function. However, despite the logic arriving at the correct output, it is imperative that hazards be
eliminated as they can have an effect on other connected systems.

Static Hazards
A static hazard is the situation where, when one input variable changes, the output changes
momentarily when it shouldn't. This particular type of hazard is usually due to a NOT gate within
the logic. The hazard can be dealt with in two ways:
• Insert another (additional) delay to the circuit. This then eliminates the static hazard.
 • Eliminate the hazard by inserting more logic to counteract the effects (Note this makes
assumptions that the logic will fail)

Static hazard is a condition which results in a single momentary incorrect output due to change
in a single input variable when the output is expected to remain in the same state.
The first case is the most used of the two options. This is because it does not make assumptions
about the logic, instead the method adds redundancy to overcome the hazard.
To solve the hazard we shall use our previous example and apply a theory that David A. Huffman
discovered. The insertion of a redundant loop can eliminate a static hazard.
Static-0 hazard
When the output is to remain at the value 0 and a momentary 1 output is possible during the
transition between the two input states, then the hazard is called a static-0 hazard
Static-1 hazard
If the two input states both produce a 1 output in the steady state and a momentary 0 output is
possible during the transition between the two input states, then the hazard is called a Static-1
hazard

In the next example, it will also be evident that there will not be a situation where a static '0'
occurs. A static '0' hazard is one which briefly goes to '1' when it should remain at '0'. A static '1'
hazard is the reverse of this situation, i.e. the output should remain at '1' yet under some condition
it briefly changes state to '0' (something we shall see in the following example)..

Example of a static hazard

Let us consider an imperfect circuit that suffers from a delay in the physical logic elements i.e.
AND gates etc. The simple circuit performs the function:
f = X1 * X2 + X1' * X3
and the logic diagram can be shown as follows:

If we first look at the starting diagram, it is clear that if no delays were to occur, then the circuit
would function normally. However since this isn't a perfect circuit, and an error occurs when the
input changes from 111 to 011. i.e. when X1 changes state. Now we know roughly how the hazard
is occurring, for a clearer picture and the solution on how to solve this problem, we look to the
Karnaugh Map:

This Karnaugh Map shows the circuit. The two gates are shown by solid rings, and the hazard can
be seen under the dashed ring. The theory proved by Huffman tells us that by adding a redundant
loop 'X2X3' this will eliminate the hazard. So the resulting logic is of the form shown in the next
figure.
So our original function is now: f = X1 * X2 + X1' * X3 + X2 * X3
Now we can see that even with imperfect logic elements, our example will not show signs of
hazards when X1 changes state. This theory can be applied to any logic system. Computer
programs deal with most of this work now, but for simple examples it is quicker to do the
debugging by hand. When there are many input variables (say 6 or more) it will become quite
difficult to 'see' the errors on a Karnaugh map.
Elimination of static hazard
By covering the adjacent cells with a redundant grouping that overlaps both groupings.

Dynamic hazard
A transient change occurring 3 or more times at an output terminal of a logic network when the
output is supposed to change only once during a transition between two input states differing in
the value of one variable.

Elimination of a Dynamic hazard

Dynamic hazard can be eliminated by covering every pair of 1 cells and every pair of 0 cells in
the K-map by atleast one sub cube.
Essential hazard
Essential hazard is a type of hazard that exists only in asynchronous sequential circuits with
two or more feedbacks. An essential hazard is caused by unequal delays along two or more
paths that originate from the same input. An excessive delay through an inverter circuit in
comparison to the delay associated with the feedback path may cause essential hazard.
Elimination of Essential hazard
Essential hazard can be eliminated by adding redundant gates as in static hazards. They can be
eliminated by adjusting the amount of delay in the affected path. For this, each feedback loop
must be designed with extra care to ensure that the delay in the feedback path is long enough
compared to the delay of other signals that originate from the input terminals.