A project Report
on
Automatic Washing Machine
( Using Verilog Code on Vivado )
Submitted by
Piyush Sahu (201300025)
Abhishek Chaudhary (201300004)
Supervisor
Mr. Devendra Kumar
( Assistant Professor )
Department of Electronics and Communication Engineering
GLA University, Mathura, Uttar Pradesh (281406)
Date of Submission is 03 Dec 2022
DECLARATION
I Piyush Sahu, BTech 2nd year, 201300025 and Abhishek Chaudhary, 2nd year
201300004 hereby declare that the work presented in this project report entitled
“Automatic Washing machine (using Verilog HDL” Is an authentic record of our
own work carried under supervision of Mr. Devendra Kumar (Assistant
Professor).
Piyush Sahu (201300025) Signature:
Abhishek Chaudhary(201300004) Signature:
CERTIFICATE
This is to certify that the above statement made by the students are correct to the
best of my knowledge and belief.
Date:
Place: Mathura
Mr. Devendra Kumar
Assistant Professor
Signature:
Page no. 2
CONTENTS
Table of contents Page No.
Certificate and Declaration 2
Introduction 4
Project Description and work Done 5-8
Verilog Code 9
Simulation Results / RTL Schematic 10-11
Power Estimation 12-13
Conclusion 14
References 15
Page no. 3
INTRODUCTION
In recent years, with the development of science and technology, world is
switching towards automation. Automation is not limited to consumer related
products only, it ranges from household products like automatic washing
machine, oven to defence systems like automatic guided missile system. The
requirement to design such electronic systems also produces a revolutionary
change, a new class of development tools relate to electronic systems are
spreading quickly. Hardware Description language ( HDL) is a method to
Description of digital circuit. HDL describes a certain function of digital circuit
usually has one or more files composition. According to certain rules (or
grammar) HDL describes documents after the compilation, and uses the
electronic system design automation (EDA) tools to comprehensive, just can be
transformed into practical circuit. In recent years, with the rapid development of
EDA and large scale programmable of logic device, HDL can hierarchical
description and simulation of any electronic component’s characteristics, so that
the circuit designers and developers could describe the feature of the circuit
freely, which can build the bridge of communication and exchange data between
chip designers and producers.
The project will demonstrate the capabilities and scope of Verilog HDL by
implementing the control system of Automatic Washing Machine. A concept of
FSM( Finite State Machine) is used for making the model. For implementation
purpose Xilinx Vivado software. The control system generates control signal to
control overall functionalities of the system.
Page no. 4
The design of automatic washing machine
Designing of an automatic machine system can be easily done using the concept
of FSM using Verilog HDL. It becomes one of the basic needs of public. It helps
people to save their time and using it for some necessary work. Because of easy
to implant in one’s house, we can see it in most of the houses. It has various other
advantages, like operation of each step automatically instead of manually.
Analysis over its power and area consumption is a never-ending process. People
are working tirelessly to achieve the above-mentioned objectives.
The principle of automatic washing machine
The inside bucket of fully-automatic washing machine has many small holes,
through them the bucket of water between the inside and outside is interlinked,
electromagnetic valve executes the water in and out. When the water in the
control system will fill the electromagnetic valve opens, so feed the water into
outer barrel. When drainage, the control system will let the drain
electromagnetic valve opens, so the water by outer barrel row to drain. When
dehydration, the control system will close clutch and by turning on washing
motor driving internal vats to dry. High, middle, and low water level control
switch is used to detect the high, middle, and low water level. Start button is
used to activate washing machine to work, stop button is used to achieve
manually stop water, drainage, dehydration, and alarm. Drainage button is to
achieve manually drainage.
State Diagram
It is used to describe how our code will work. It describes the state it will follow
to achieve the mechanism of automatic washing machine.
State is basically a various input/output condition through which system goes.
A system can have many states depending upon the number of inputs and
algorithm involved. When these states are finite in number, we termed it as
finite state machine(FSM).
Page no. 5
Fig 1: state diagram1
Page no. 6
FLOWCHART
The below given flowchart describes how the system will work from check_door
to spin with other intermediate states.
Fig 2: state diagram2 with input conditions
Fig3: Flowchart of automatic washing machine
Page no. 7
Ports Description and The Various States
Table 1: State Description
S.No. State code State Description
1 3’b000 check_door
2 3’b001 fill_water
3 3’b010 add_detergent
4 3’b011 cycle
5 3’b100 drain_water
6 3’b101 spin
Table 2: Input signal
S.No. Input signal Signal Description
1 clk provides clock to circuit
2 reset it will reset the system irrespective of state and input
3 door_close check for door close
4 start it will check the start of system
5 filled checks for water filled in the bucket
6 detergent_added checks for detergent added
7 cycle_timeout current process ended
8 drained indicating that water is drained out
9 spin_timeout Drying of clothes done
Table 3: output Signal Description
S.No. Output signal Signal discription
1 door_lock Indicates that machine has started
2 fill_valve _on Indicates that water is filling in bucket
3 detergent_wash It indicates that detergent wash is done
4 drain_valve_on Water is drained out
5 water_wash Washed from water
6 motor_on Motor is on
7 done It shows that washing of clothes done
Page no. 8
Glimpse Of Verilog Code
Of
Automatic Washing Machine
module automatic_washing_machine( list of ports);
input //list of input ports
output //list of output ports
parameters:
parameters:
parameters:
parameters:
parameters:
parameters:
always@( posedge clk )
begin
if(reset)
statement
else
statement
always@(posedge clk)//always block2
begin
case( state)
check_door:
fill_water:
detergent_added:
cycle:
drained_water:
spin:
endcase
end
endmodule
Page no. 9
Description of above code
The code describes the way system is executing the process.
First, we have given the name of module as automatic_washing_machine inside
it all the input and output ports are listed as clk, reset, door_close, start, filled,
detergent_added, cycle_timeout, drained, spin_timeout, door_lock, motor_on,
fill_valve_on, drain_valve_on, done, detergent_wash, water_wash.
Inside the always block it checks whether reset is high or low if it is high, it always
directs the system to initial state of check door else current_state is next_state.
The states are as check_door which checks whether the door is open or closed if
found closed it will fill the water and indicates on indicator that it gets filled. The
next state is add_detergent, if detergent is added then go for detergent wash later
this foam water is drained out it will go for fresh water wash state. After draining
of the water it goes to next state known as spin state which means drying of
clothes. When all the process are executed, it shows that process is completed by
raising the done equal to one.
Simulation Results
Fig4: simulation of automatic washing machine
Page no. 10
RTL Schematic
RTL means register transfer level. It is the model of the actual circuit written in
the hardware descriptive language like VHDL or Verilog. In essence, the HDL
code describes how data is transferred as it passes through register to register in
the transistor-based circuit. Simply it converts the texted code into circuits.
The below image shows the RTL schematic of automatic washing machine.
Fig 5: RTL Schematic of automatic washing machine
Page no. 11
Power Estimation
In a twenty first century power consumption becomes an important factor.
Therefore, systems are designed considering the power as one of the important
factors.
Power dissipated by any circuit is of two types:
Static power dissipation (power consumed when circuit is not in operational
mode), while the second one is dynamic power dissipation( the power dissipated
by circuit when it performs some operations.
Hence, total power dissipation must be as small as possible.
The power dissipation of a circuit depends on the type of inverter used to design
the circuit, temperature of the working environment etc.
Power analysis for automatic washing machine considering input voltage and
difference in temperature has been shown.
Page no. 12
when temperature is change to 10-degree Celsius
Page no. 13
CONCLUSIONS
Automatic washing machine code has been successfully implemented using the
concept of FSM in Verilog HDL. All the functionalities have been checked.
Total power consumed ( Static and Dynamic power dissipation have been
analysed.
PIN diagram of the circuit obtained by implementing above discussed properties
have been included and shown as
PIN diagram of circuit
Page no. 14
REFERENCES
1. Wangguan etc. Verilog HDL and digital circuit design [M].beijing
mechanical industry press, 2005.9
2. XiaYu wen. Veri log digital system design guide [M].beijing: aerospace
university press, 2003. 2-10 Thomas & Moorby, The Hardware Verilog
DescriptionLanguage [M]. Beijing tsinghua university press, 2001. 23-36.
3. WangJiGang, GuGuoChang. Structures and patterns in communication
system software application research (J].journal of computer application
pract, (II) : 43-45.
4. YangJimin YangJiBing, digital system design and VerilogHDL
[M].beijing: electronic industry press, 2003,23(11 ):43-45.
5. YuanJunQuan, SunMinQi, CaoRui. VerilogHDL digital system design and
its application [M].concrete: xi
Page no. 15
