MVSILICON BP1064L2 DATASHEET

BP1064L2 Datasheet
High Performance 32-bit Bluetooth Audio Processor

Versions:

Date Version Description

2020/1 V0.5 Preliminary English version

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Content
1. Overview..........................................................................................................................................................................1
2. Functional Block Diagram.............................................................................................................................................3
3. DSP processing block diagram................................................................................................................................... 4
4. Pin Definition...................................................................................................................................................................5
5. GPIO Pin Description.................................................................................................................................................... 5
6. Electrical Characteristics.............................................................................................................................................. 9
6.1. Working condition for BP1064L2............................................................................................................... 9
6.2. Digital IO Electrical Characteristics........................................................................................................... 9
6.3. Audio Performance.....................................................................................................................................10
7. Operational Frequency and Power Consumption..................................................................................................12
7.1. Clock source and Operational frequency............................................................................................... 12
7.2. Power Consumption under Typical Mode.............................................................................................. 12
8. Package.........................................................................................................................................................................13
9. Storage and Soldering................................................................................................................................................ 14
10. Declaration..................................................................................................................................................................15
11. Technical Support......................................................................................................................................................16

Figures
Figure 1 . Functional Block Diagram of BP1064L2.............................................................................................. 3
Figure 2 . Audio DSP signal processing block diagram.......................................................................................4
Figure 3 . Pin Definition............................................................................................................................................. 5
Figure 4 . Package and Size.................................................................................................................................. 13

Tables
Table 1 . Pin definition............................................................................................................................................... 5
Table 2 . GPIO State and Electric level (POR)..................................................................................................... 7
Table 3 . Working Condition of BP1064L2.............................................................................................................9
Table 4 . Digital IO DC Characteristics...................................................................................................................9
Table 5 . Digital IO Driving and Pull-Up/Down Capability................................................................................... 9
Table 6 . Wakeup IO Driving and Pull-Up/Down Capability..............................................................................10
Table 7 . Audio DAC performance@44.1KHz.....................................................................................................10
Table 8 . Audio ADC performance @LINEIN1/3 channel，44.1KHz..............................................................10
Table 9 . Audio ADC performance @LINEIN4/5 channel，44.1KHz..............................................................11
Table 10 . Audio ADC performance @microphone channel, 44.1KHz...........................................................11
Table 11 . Power consumption.............................................................................................................................. 12

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1. Overview

Core and Memory Bluetooth

 High performance 32-bit RISC core,  Dual mode Bluetooth V5.0, compatible with
@ max. 288MHz, supports DSP instruction, Bluetooth V4.2 and V2.1+EDR
with floating-point unit(FPU) integrated  Support Piconet and Scatternet networking
 FFT/IFFT accelerator supports operations of protocols
up to 1024 complex numbers or 2048 real  Maximum transmit power is 10dBm, support
numbers class1, class2 and class3
 320KB on-chip SRAM, 32KB I-Cache and  Receiving sensitivity (Typical)
32KB D-Cache  DH1：-88dBm
 Internal 16M bits FLASH code and data  2DH5：-88dBm
storage  3DH5：-82dBm
 EFUSE configuration register  BLE：-92dBm
 2-wire SDP(Serial Debug Port), break-point  Support
and code tracking debug A2DP/AVRCP/HFP/HSP/OPP/HID/SPP/PBAP/
 40 interrupt vectors GATT/SM profiles
 4-level interrupt priority  Support PLC(Package Loss Concealment)
Audio Power, Clock and Reset
 Four audio ADC, SNR≥94dB,
 DC 3.3~5V power supply @ LDOIN
9 sampling rate: 8KHz / 11.025KHz / 12KHz /
 Internal LDOs: 5V to 3.3V and 3.3V to 1.2V
16KHz / 22.05KHz / 24KHz / 32KHz / 44.1KHz
 RC 12MHz and two PLL clocks
/ 48KHz
 Support 24MHz crystal
 Support up to 4 digital microphones or 2
 Internal POR(Power on Reset), LVD(Low-
analog microphone with AGC
Voltage-Detection) and Watchdog
 ADC line-in supports single-end or differential
 Multiple low-power options: CPU clock
input
frequency reduction, system clock frequency
 Three audio DAC, SNR≥105dB,
reduction, sleep, deep sleep
9 sampling rate: 8KHz / 11.025KHz / 12KHz /
 Low power RTC mode, supporting IO wake up
16KHz / 22.05KHz / 24KHz / 32KHz / 44.1KHz
and alarm signal output
/ 48KHz
 Directly drive earphone of 16Ω or 32Ω with Timer, PWM and PWC
power of 40mW  2 basic timers (TIM1, TIM2)
 Two duplex I2S( or IIS), sampling rate  4 general timers (TIM3, TIM4, TIM5, TIM6),
8K~192KHz, max. 32bits with PWM and PWC function
 One half-duplex S/PDIF supporting HDMI Peripherals
audio and ARC
 Max. 38 GPIOs

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 All GPIOs support external interrupt and Encode: MP2/MP3, IMA-ADPCM

wakeup  Sound effects:
 GPIOs configurable: pull-up, pull-down, Hi- Echo, Reverb, 3D, Virtual bass, Auto-tune/pitch
impedance , pull-down current source, etc shifter/Voice changer, EQ, DRC, AEC, Noise
 USB 2.0 Full-speed OTG controller and PHY, 6 suppression, Frequency-shifting, Screaming
endpoints detection and suppression
 One SPI master(SPIM) @ max.60M  SDK includes abound of examples and
 One SPI slave(SPIS) @ max.60M middleware
 One SDIO @ max.30M  Free Eclipse-based IDE and GCC compiler
 Two duplex UART @ max.3Mbps, the UART0  Support FreeRTOS
with flow control  All C programming, easy for porting
 One I2C master/slave controller @ max.400K Firmware Programming and Protection
 12-bit SAR-ADC @ max. 450K sampling rate,
 Multiple flash programming supported:
sampling from 15 external IOs or 2 internal
debugger, specific burner/programmer, or
voltages
Flash Burner Lite
 One IR interface, supports NEC or SONY
 Firmware upgradable with Dual-bank
mode
 32-bit customized key for firmware encryption
 True random number generator
 On-chip 64-bit unique ID
DMA
ESD
 8-channel DMA, all memory direct addressing,
addresses can be assigned to any peripherals  HBM 2KV ESD capability
except OTG, IR and I2C Package and Operational Temperature
 Unique automatic transmit-and-capture
 LQFP64-7x7mm
mechanism for memory and IO matching, or
 Working temperature: -40℃ ~ 85℃
DMA-GPIO, can simulate various
communication and controlling timing Application Fields

SDK Firmware Stack and IDE  Bluetooth audio speaker

 Bluetooth Karaoke equipment
 Audio algorithm list:  Bluetooth Headphone
Decode: MP2, MP3, WMA, APE, FLAC, AAC,  Bluetooth Car audio
MP4, M4A, WAV(IMA-ADPCM & PCM), AIF,  Multiple microphone system for intelligent voice
AIFC application with Bluetooth

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2. Functional Block Diagram

Figure 1. Functional Block Diagram of BP1064L2

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3. DSP processing block diagram

Figure 2. Audio DSP signal processing block diagram

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4. Pin Definition

Figure 3. Pin Definition

5. GPIO Pin Description

Table 1. Pin definition

Pin# Pin Name Type Other multiplexing function(s)
1 AVDD33 PWR Analog power output, external filter capacitor is required
2 LDOIN PWR Power input for whole chip
3 LDO12O PWR 1.2V core power, external filter capacitor is required
4 DVSS GND Digital groud

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Pin# Pin Name Type Other multiplexing function(s)

IO port belonging to low power domain, external signal can wake the
5 WAKEUP_C0 I/O
chip from Powerdown mode, or output RTC alarm signal
Power supply for low power domain (including RTC, backup registers,
6 VBAT PWR
and WAKEUP IO)
7 32K_XI I 32.768K RTC crystal XI
8 32K_XO O 32.768K RTC crystal XO
9 POWERKEY I Configurable power key, also be used as an ADC channel (AD11)
10 GPIO_B4 I/O I2C_SDA
11 GPIO_B5 I/O I2C_SCL
SPIS_MOSI / UART0_RXD / UART0_TXD / MCLK0_OUT /
12 GPIO_A0 I/O
MCLK0_IN / TIM3_PWM
SPIS_CLK / UART0_TXD / UART0_RXD / I2S0_LRCLK /
13 GPIO_A1 I/O
I2S1_LRCLK / TIM4_PWM
LDO33DO/ Digital 3.3V power output and RF 3.3V power input, external filter
14 PWR
RF3V3_IF capacitor is required
15 RFIO AI RF antenna port
16 RFVSS GND RF ground
17 RF3V3_TR PWR RF power 3.3V input
18 RFVDD12 PWR RF power 1.2V output, external filter capacitor is required
19 24M_XI I 24M crystal XI
20 24M_XO O 24M crystal XO
21 GPIO_A5 I/O LCD0 / SPIM_MOSI / UART0_RXD / I2C_SDA
22 GPIO_A6 I/O LCD1 / SPIM_CLK / UART0_TXD / I2C_SCL
23 GPIO_A7 I/O LCD2 / SPIM_MISO / UART0_CTS / MCLK1_OUT / MCLK1_IN
24 GPIO_A8 I/O LCD3 / UART0_RTS / I2S1_LRCLK / TIM3_PWM
25 GPIO_A9 I/O LCD4 / UART1_RXD / I2S1_BCLK / TIM4_PWM
26 GPIO_A10 I/O LCD5 / UART1_TXD / I2S1_DO / I2S1_DI / TIM5_PWM
27 GPIO_A11 I/O LCD6 / UART1_CTS / I2S1_DI / I2S1_DO / TIM6_PWM
28 GPIO_A12 I/O LCD7 / UART1_RTS
29 GPIO_A13 I/O LCD8
30 GPIO_A14 I/O LCD9
31 DVSS GND Digital ground
32 GPIO_A15 I/O LCD10 / SD_DAT
33 GPIO_A16 I/O LCD11 / SD_CLK
34 GPIO_A17 I/O LCD12 / SD_CMD
35 GPIO_A18 I/O USB_DM / UART1_RXD
36 GPIO_A19 I/O USB_DP / UART1_TXD
AD0 / SD_DAT / SPIM_MOSI / SPIS_MOSI / I2S0_LRCLK /
37 GPIO_A20 I/O
I2S1_LRCLK
38 GPIO_A21 I/O AD1 / SD_CLK / SPIM_CLK / SPIS_CLK / I2S0_BCLK / I2S1_BCLK
AD2 / SD_CMD / SPIM_MISO / SPIS_MISO / UART1_RTS / I2S0_DO
39 GPIO_A22 I/O
/ I2S0_DI / TIM3_PWM
LCD13 / AD0 / SPIS_CS / UART1_CTS / I2S0_DI / I2S0_DO /
40 GPIO_A23 I/O
TIM4_PWM
LCD14 / AD1 / UART1_RXD / I2C_SDA / MCLK0_OUT / MCLK0_IN /
41 GPIO_A24 I/O
TIM5_PWM
42 GPIO_A25 I/O LCD15 / AD2 / UART1_TXD / I2C_SCL / TIM6_PWM
43 GPIO_A26 I/O AD3
44 GPIO_A27 I/O AD4 / MCLK1_OUT / MCLK1_IN / TIM3_PWM
45 GPIO_A28 I/O AD5 / SPDIF_AI_0 / I2S1_LRCLK / SPDIF_DI / SPDIF_DO /

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Pin# Pin Name Type Other multiplexing function(s)

TIM4_PWM
AD6 / SPDIF_AI_1 / I2S1_BCLK / SPDIF_DI / SPDIF_DO / CLKOUT /
46 GPIO_A29 I/O
IR
AD7 / SPDIF_AI_2 / I2S1_DO / I2S1_DI / I2C_SDA / SPDIF_DI /
47 GPIO_A30 I/O
SPDIF_DO / DMIC1_DAT
AD8 / SPDIF_AI_3 / I2S1_DI / I2S1_DO / I2C_SCL / SPDIF_DI /
48 GPIO_A31 I/O
SPDIF_DO / DMIC1_CLK
49 GPIO_B6 I/O EFUSE VDD / CLK_OUT / IR
50 GPIO_B7 I/O CLK_OUT / IR
51 GPIO_B0 I/O LINEIN4_R / AD9 / TIM5_PWM / SW_CLK
52 GPIO_B1 I/O LINEIN4_L / AD10 / TIM6_PWM / SW_D
53 RESETN I Chip independent reset pin, low level effective
(note, the reset signal is not valid for low power domain)
54 GPIO_B2 I/O LINEIN5_R / DMIC0_DAT
55 GPIO_B3 I/O LINEIN5_L / DMIC0_CLK
56 LINEIN1R AI Analog audio LINEIN-1 right-channel input
57 LINEIN1L AI Analog audio LINEIN-1 left-channel input
LINEIN3R /
58 AI Analog audio LINEIN-3 right-channel input or MIC2 input
MIC2
LINEIN3L /
59 AI Analog audio LINEIN-3 left-channel input or MIC1 input
MIC1
60 VMID AO Bias voltage for audio module internal use
61 AVSS GND Analog ground
62 DAC_R AO Audio right-channel output
63 DAC_L AO Audio left-channel output
64 DAC_X AO Audio x-channel output
Note:
1) Pad types:
I: digital input; O: digital output; AI: analog input; AO: analog output; I/O: bi-directional input/output;
PWR: Power; GND: Ground
2) All GPIOs are grouped into A, B. Group A has 29 signals and Group B has 8.
3) BP1064L2 is a CMOS device and all unconnected GPIO pins are supposed to be set to pull-up or pull-
down in order to avoid the unnecessary power consumption cause by the electric charge accumulation.
4) GPIOs response differently with the different type of resets:
a) If Power-on-Reset (POR) is active, GPIOs will be reset as input and be set to high-impedance as
indicated in table 2.
b) If Watchdog reset or software SYSTEM RESET is active, GPIOs, based on the register
configuration, can either keep the previous status(multiplexing, input/output or pull-up/down setting)
before the reset or be set as the same as described in a) or table 2.
Table 2. GPIO State and Electric level (POR)
Pin(s) Type Electric level
GPIO_A[1:0] Floating High Impedance
GPIO_A[31:5] Floating High Impedance
GPIO_B[7:0] Floating High Impedance

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5) When the POWERKEY is not used, please keep the POWERKEY pin unconnected. Do not short to the
ground or LDOIN.
6) MCLK0 or MCLK1 is used for connected to other audio peripherals as audio clock, which can be
configured as input (IN) or output (OUT).
7) Low power domain working power supply (LDOIN or VBAT) Contains 3 parts: RTC, WAKEUP IO, and
backup registers. All functions are reset to the initial state only when the chip has an power-on reset.
The initial state of WAKEUP_C0 is floating with high resistance.

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6. Electrical Characteristics

6.1. Working condition for BP1064L2

Table 3. Working Condition of BP1064L2

Parameter Pin Min Typ Max Unit
Ambient temperature -40 85 ℃
Power supply for chip LDOIN 3.3 5.25 V
Power supply for analog modules AVDD 3.3 V
Internal LDO for digital power supply LDO33DO 3.3 V
Core working voltage LDO12O 1.2 V
Low power RTC operating voltage VBAT 2.5 3.0 3.6 V

6.2. Digital IO Electrical Characteristics

Table 4. Digital IO DC Characteristics

Symbol Meaning Min. Typ. Max. Unit Testing Condition
VIH Input High 2.2 3.6 V VDD33=3.3V
VIL Input Low -0.3 1.0 V VDD33=3.3V
IL Input leakage current -10 10 uA
VOH Output High 3.0 V @IOH=8mA
VOL Output Low 0.3 V @IOL=8mA

Table 5. Digital IO Driving and Pull-Up/Down Capability

Name IOs Normal Enhanced Unit Testing Condition
Driving GPIO_A[10:5] / 8 24 mA VDD33=3.3V, typical
Capability GPIO_A[17:15] /
GPIO_A24 /
GPIO_A[31:30]
GPIO_A[1:0] / 4 8 mA VDD33=3.3V, typical
GPIO_A[23:18] /
GPIO_A[29:28] /
GPIO_B[3:0] /
GPIO_B[6]
GPIO_B[5:4] 19 34 mA VDD33=3.3V, typical
Pull-up All GPIOs 20 70 uA VDD33=3.3V, typical
Pull-down All GPIOs 20 - uA VDD33=3.3V, typical
Pull-down GPIO_A[10:5] / 1.3 2.6 / mA VDD33=3.3V, typical
current GPIO_A[17:15] / 1.3+2.6
source GPIO_A24 /
GPIO_A[31:30] /
GPIO_B[5:4]

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GPIO_A[1:0] / 2.6 mA VDD33=3.3V, typical

GPIO_A[23:18] /
GPIO_A[29:28] / -
GPIO_B[3:0] /
GPIO_B[6]

Table 6. Wakeup IO Driving and Pull-Up/Down Capability

Output driving Pull-Up Pull-Down Drop-down
IOs Testing Condition
(mA) (Ω) (Ω) current source
WAKEUP_C0 4mA 20K/50K 20K/50K 3.4mA VBAT = 3V, typical

6.3. Audio Performance

Table 7. Audio DAC [email protected]

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 24 Bits
Full Scale Output
AVDD=3.3V 1.067 Vrms
Signal Level
Sampling frequency 8 48 KHz
A-Weighted, 1KHz
Dynamic Range 105 dB
-60dBFS input signal
A-Weighted, 1KHz
Signal to Noise Ratio 105 dB
0dBFS, input signal
Total Harmonic A-Weighted ,1KHz
-86 dB
Distortion + Noise -6dBFS, input signal
Gain Error 0.008 dB
Group Delay 20 samples 2.65 ms
Phase deviation 0.18 degree
Channel Separation -106 dB

Table 8. Audio ADC performance @LINEIN1/3 channel，44.1KHz

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 16 bits
Full Scale input Signal
AVDD=3.3V 0.85 Vrms
Level
Sampling frequency 8 48 KHz
PGA Gain Range -18 12 dB
Input Resistance PGA gain=0dB 36 KΩ
No Filter
94 dB
1KHz input signal
Dynamic Range
A-Weighted
96 dB
1KHz input signal
No Filter, 850mVrms
94 dB
1KHz input signal
Signal to Noise Ratio
A-Weighted, 850mVrms
96 dB
1KHz input signal

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Total Harmonic 700mVrms

-86 dB
Distortion + Noise 1KHz input signal
Gain Error 0.033 dB
Group Delay 20 samples 850 us
Channel Separation -100 dB

Table 9. Audio ADC performance @LINEIN4/5 channel，44.1KHz

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 16 bits
Full Scale input Signal
AVDD=3.3V 0.85 Vrms
Level
Sampling frequency 8 48 KHz
PGA Gain Range -19 42 dB
Input Resistance 50 KΩ
No Filter @ Fin=1KHz 93 dB
Dynamic Range
A-Weighted @ Fin=1KHz 95 dB
No Filter @ 850mVrms,
93 dB
Fin=1KHz
Signal to Noise Ratio
A-Weighted @ 850mVrms,
95 dB
Fin=1KHz
Total Harmonic
@ 700mVrms, Fin=1KHz -82 dB
Distortion + Noise
Gain Error 0.033 dB
Group Delay 20 samples 850 us
Channel Separation -100 dB

Table 10. Audio ADC performance @microphone channel, 44.1KHz

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 16 bits
Full Scale input Signal
AVDD=3.3V 0.85 Vrms
Level
Sampling frequency 8 48 KHz
Without GainBoost -20 20 dB
PGA Gain Range
With GainBoost -20 47 dB
Input Resistance PGA gain=20dB with Gainboost 1.5 KΩ
No Filter 94 dB
Dynamic Range
A-Weighted 96 dB
No Filter 94 dB
Signal to Noise Ratio
A-Weighted 96 dB
PGA Gain=0, -2dBFS
-80 dB
Total Harmonic Without GainBoost
Distortion + Noise PGA Gain=0, -2dBFS
-86 dB
With GainBoost
Gain Error 0.03 dB
Group Delay 850 us
Channel Separation -97 dB

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7. Operational Frequency and Power Consumption

7.1. Clock source and Operational frequency

T.B.D

7.2. Power Consumption under Typical Mode

Table 11. Power consumption

Typical Mode Typical Current Condition
Bluetooth A2DP T.B.D.
Bluetooth HFP T.B.D.
Bluetooth sniff T.B.D.
Powerdown T.B.D.

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8. Package

Figure 4. Package and Size

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9. Storage and Soldering

Storage temperature: -65℃ ~ 150℃.

BP1064L2 is a moisture sensitive component. The moisture sensitivity classification is Class 3.
It’ s important that the parts are handled under precaution and a proper manner.
The handling, baking and out-of-pack storage conditions of the moisture sensitive components are
described in IPC/JEDC S-STD-033A.
The Technologies recommends utilizing the standard precautions listed below.
1. Calculated shelf life in Sealed Bag: 12 months at <40℃ and <90% relative humidity(RH)
2. Peak Package Body Temperature: 250℃
3. After bag is opened, devices that will be subjected to reflow solder of other high temperature process
must be:
a. Mounted within 168 hours of factory condition ≤30℃ / 60% RH
b. Stored at <10% RH if not used
4. Devices require baking, before mounting if:
a. Humidity indicator card is >10% when read at 23±5℃ immediately after moisture barrier bag is
opened
b. Items 3a or 3b is not met
5. If baking is required, please refer to J-STD-033 standard for low temperature (40℃) baking requirement
in Tape/Reel form.

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10. Declaration

All information and data contained in this document are without any commitment, are not to be considered
as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue
of this document invalidates previous issues. Product availability and delivery are exclusively subject to our
respective order confirmation form; the same applies to orders based on delivered development samples
delivered. By this publication, Shanghai Mountain View Silicon Co., Ltd.(“MVSILICON”) does not assume
responsibility for patent infringements or other rights of third parties that may result from its use.

No part of this publication may be reproduced, photocopied, stored in a retrieval system, or translated in any
form or by any means, electronic, mechanical, manual, optical, or otherwise, without the prior written
permission of Shanghai Mountain View Silicon Co., Ltd.

Shanghai Mountain View Silicon Co., Ltd. assumes no responsibility for any errors contained herein.

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11. Technical Support

Shanghai Mountain View Silicon Co., Ltd. (上海山景集成电路股份有限公司)

Website: http://www.mvsilicon.com
Email: [email protected]

Shanghai Headquarter:
Suite 4C, Building 3, 1238 Zhangjiang Road, Pudong New District, Shanghai, China
ZIP: 201203
Tel: 86-21-68549851/68549853/68549857/50938107
Fax: 86-21-58992765

Shenzhen Sales and FAE Branch:

Suite 6A, Olympic Tower, 2 Shangbao Road, Futian District, Shenzhen, Guangdong, China
ZIP: 518034
Tel: 86-755-83522952
Fax: 86-755-83522957

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