AMITY UNIVERSITY

RAJASTHAN
Laboratory Manual
B. Tech (ECE), Year – III, Semester -V
Digital Circuit &System-II Lab – BEC 521

Department of Electronics & Communication

Engineering
Amity School of Engineering & technology
 Experiment-1

AIM: To implement VHDL code for all the basic gates and test their simulation with
signal.

APPARATUS REQUIRED: Xilinx 13.3 synthesize tool

CODES:

1.XOR gate

Code for XOR gate

library IEEE; use

IEEE.STD_LOGIC_1164.ALL;

entity ssr1 is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC; y:

out STD_LOGIC); end ssr1;

architecture Behavioral of ssr1 is

begin y<=a xor b; end

Behavioral;

2. AND gate
Code for AND gate library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity andgate is Port

( a : in STD_LOGIC;

b : in STD_LOGIC; y

: out STD_LOGIC); end

andgate;

architecture Behavioral of andgate is

begin y<=a

AND b; end

Behavioral;
3. OR gate
Code for OR gate library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity orgate is
Port ( a : in STD_LOGIC;

b : in STD_LOGIC; y : out

STD_LOGIC); end orgate;

architecture Behavioral of orgate is

begin y<=a or b;

end Behavioral;
4. NAND gate

Code for NAND gate library

IEEE; use

IEEE.STD_LOGIC_1164.ALL;

entity nandgate is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC; y

: out STD_LOGIC); end

nandgate;

architecture Behavioral of nandgate is

begin y<=a

nand b;

end Behavioral;
5. NOR gate

Code for NOR gate library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity norgate is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC; y

: out STD_LOGIC); end

norgate;

architecture Behavioral of norgate is

begin y<=a

nor b; end

Behavioral;
6. XNOR gate

Code for XNOR gate library

IEEE; use

IEEE.STD_LOGIC_1164.ALL;

entity xnorgate is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC; y

: out STD_LOGIC); end

xnorgate;

architecture Behavioral of xnorgate is

begin y<=a xnor b; end Behavioral;

7. NOT gate

Code for NOT gate library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity notgate is

Port ( a : in STD_LOGIC;

y : out STD_LOGIC); end

notgate;

architecture Behavioral of notgate is

begin y<=not a;

end behavio
Experiment:-
AIM: To implement VHDL code for half adder using different types of programming
modeling and test simulation with signal.

APPARATUS REQUIRED: Xilinx 13.3 synthesize tool

Code using data flow modelling:

library IEEE; use

IEEE.STD_LOGIC_1164.ALL;

entity ssr is
Port ( a : in STD_LOGIC;

b : in STD_LOGIC; s
: out STD_LOGIC;

c : out STD_LOGIC); end

ssr;

architecture Behavioral of ssr is

begin s<=a

xor b; c<=a
and b;

end Behavioral;
Code using structural modelling
library IEEE; use

IEEE.STD_LOGIC_1164.ALL;

entity HA2 is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC; s

: out STD_LOGIC;

c : out STD_LOGIC); end

HA2;

architecture Behavioral of HA2 is

component XOR1 port (u,v: in STD_LOGIC;

w :out STD_LOGIC); end component; component

AND1 port(x,y:in STD_LOGIC; z:out

STD_LOGIC); end component;

begin

XOR1 port map(a,b,s)

AND1 port map(a,b,c)

end Behavioral;
 Experiment-3
AIM: To implement VHDL code of half subtractor using different types of
programming modeling and test simulation with signal.

APPARATUS REQUIRED: Xilinx software, simulation tool

Half Substractor using Data flow modelling:

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

entity ssr is
Port ( a : in STD_LOGIC;

b : out STD_LOGIC; c:
in STD_LOGIC; d : out

STD_LOGIC); end ssr;

architecture Behavioral of ssr is

begin b<= a xor c; d<= (not a)

and c; end Behavioral;
Half Substractor using behavioral modelling:
library IEEE; use

IEEE.STD_LOGIC_1164.ALL;

entity halfsubstractor1 is Port ( a : in

STD_LOGIC; c : in STD_LOGIC;

b : out STD_LOGIC; d : out

STD_LOGIC); end halfsubstractor1;

architecture Behavioral of halfsubstractor1 is

begin process (a,c) begin if (a='0') then d<=c;

b<=c;

else d<=not
c; b<= '0';

end if; end

process;

end Behavioral;
 Experiment - 4
Aim : To implement VHDL code for Full adder using different types of programming
modeling and test their simulation with signal.

Apparatus : Xilinx software. Behavioral

Modeling

library IEEE; use

IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL;

entity fab is
Port ( a : in std_logic; b : in
std_logic; cin : in std_logic;

s : out std_logic; cout : out

std_logic); end fab; architecture

Behavioral of fab is begin

process(a,b,cin) begin if(a='0' and

b='0' and cin='0')then s<='0';

cout<='0'; elsif( a='0' and b='0' and

cin='1')then s<='1'; cout<='0';

elsif( a='0' and b='1' and cin='0')then
s<='1'; cout<='0'; elsif( a='0' and

b='1' and cin='1')then s<='0';

cout<='1'; elsif( a='1' and b='0' and

cin='0')then s<='1'; cout<='0';

elsif( a='1' and b='0' and cin='1')then

s<='0'; cout<='1'; elsif( a='1' and

b='1' and cin='0')then s<='0';

cout='1'; else s<='1'; cout<='1';

end if; end process; end Behavioral;

Out put:

Structural Modeling
library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL;

entity HA is
Port ( A,B : in STD_LOGIC;
S,C : out STD_LOGIC);
end HA;

architecture dataflow of HA is

begin
S <= A XOR B; C
<= A AND B;
end dataflow;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ORGATE is
Port ( X,Y : in STD_LOGIC;
Z : out STD_LOGIC);
end ORGATE;
architecture dataflow of ORGATE is
begin Z <= X OR Y; end dataflow;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL;

entity FAdder is
Port ( FA, FB, FC : in STD_LOGIC;
FS, FCA : out STD_LOGIC); end
FAdder;

architecture structural of FAdder is

component HA is
Port ( A,B : in STD_LOGIC;
S,C : out STD_LOGIC);
end component; component
ORGATE is
Port ( X,Y: in STD_LOGIC;
Z: out STD_LOGIC); end
component; SIGNAL
S0,S1,S2:STD_LOGIC;
begin
U1:HA PORT MAP(A=>FA,B=>FB,S=>S0,C=>S1); U2:HA
PORT MAP(A=>S0,B=>FC,S=>FS,C=>S2); U3:ORGATE
PORT MAP(X=>S2,Y=>S1,Z=>FCA);
end structural;
 Experiment – 5

AIM : To implement VHDL code for Binary to Grey converter and test their
simulations with signal.

APPARATUS REQUIRED : Xilinx software.

CODE FOR BINARY TO GREY CONVERTER :
library IEEE; use
IEEE.STD_LOGIC_1164.ALL;

entity ssrB-A is
Port ( b0 : in STD_LOGIC;
b1 : in STD_LOGIC; b2 : in

STD_LOGIC; b3 : in
STD_LOGIC; g0 : out

STD_LOGIC; g1 : out
STD_LOGIC; g2 : out

STD_LOGIC; g3 : out
STD_LOGIC); end ssrB-A;

architecture Behavioral of ssrB-A is

begin g3<=b3; g2<=b3 xor b2;
g1<=b2 xor b1; g0<=b1 xor b0; end

Behavioral;

Experiment – 6
AIM: To implement VHDL code for 1-bit comparator using different types of
programming modeling and test simulation with signal.
APPARATUS REQUIRED: Xilinx software.

DATA FLOW MODELING:

library IEEE; use

IEEE.STD_LOGIC_1164.ALL;

entity ssr1bit is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC; g : out

STD_LOGIC; e : out
STD_LOGIC; l : out

STD_LOGIC); end ssr1bit ;

architecture Behavioral of ssr1bit is

begin g<=a and (not b); e<=a xnor

b; l<=(not a) and b; end Behavioral;

When-else: library IEEE; use

IEEE.STD_LOGIC_1164.ALL;

entity ssr1bit is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC; g : out

STD_LOGIC; e : out
STD_LOGIC; l : out

STD_LOGIC); end ssr1bit;

architecture Behavioral of ssr1bit is

begin g<='1' when (a>b) else '0';

e<='1' when (a=b) else '0'; l<='1'

when (a<b) else '0'; end Behavioral;

Experiment - 7
Aim : To implement VHDL code for 2-bit comparator using different types of
programming modeling and test simulation with signal.
Apparatus Required : Xilinx software.
Code for 2-bit comparator :

Data flow modeling :

library IEEE; use

IEEE.STD_LOGIC_1164.ALL;

entity ssr is

Port ( a1 : in STD_LOGIC; a0 : in STD_LOGIC;

b1 : in STD_LOGIC; b0 : in STD_LOGIC;
g : out STD_LOGIC; e : out STD_LOGIC; l:

out STD_LOGIC); end ssr; architecture Behavioral of ssr

is begin g<=(a1 and (not b1)) or ((a1 xnor b1) and (a0 and

(not b0))); e<=(a1 xnor b1) and (a0 xnor b0); l<=((not a1)

and b1) or ((a1 xnor b1) and ((not a0) and b0)); end

Behavioral;

STRUCTURAL MODELING :
library IEEE; use

IEEE.STD_LOGIC_1164.ALL;

entity ssr is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC; g:

out STD_LOGIC; e : out

STD_LOGIC; l : out

STD_LOGIC); end ssr;

architecture Behavioral of ssr is

component not1 port(c:in

STD_LOGIC; d:out

STD_LOGIC); end component;

component and1 port(f:in

STD_LOGIC; h:in

STD_LOGIC;

i:out STD_LOGIC);
end component;

component xnor1

port(j:in STD_LOGIC;

k:in STD_LOGIC;

m:out STD_LOGIC);

end component; signal s1,s2

: STD_LOGIC; begin nt1 :

not1 port map(b,s1); nd1 :

and1 port map(a,s1,g); xnr :

xnor1 port map(a,b,e); nt2 :

not1 port map(a,s2); nd2 :

and1 port map(b,s2,l); end

Behavioral;
 Experiment – 8
Aim : To implement VHDL code for 4:1 multiplexer and test their simulations with
signal.

Apparatus : Xilinx software.

Code for 4:1 multiplexer :

Data flow modeling :
library IEEE; use

IEEE.STD_LOGIC_1164.ALL;

entity mp is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC; c : in

STD_LOGIC; d : in

STD_LOGIC; s1 : in

STD_LOGIC; s0 : in

STD_LOGIC; y : out

STD_LOGIC); end mp;

architecture Behavioral of mp is

begin

y<=(a and (not s1) and (not s0)) or (b and (not s1) and s0) or (c and s1 and (not s0))
or (d and s1 and s0); end Behavioral;
 Experiment - 9
Aim : To implement VHDL code for Full Subtractor using different types of
modeling and test their simulation with signal.

Apparatus : Xilinx software.

DATA FLOW MODELLING :

library IEEE; use

IEEE.STD_LOGIC_1164.ALL;

entity sai is

Port ( a : in STD_LOGIC; bi : in

STD_LOGIC; c : in STD_LOGIC; d:
out STD_LOGIC; bo : out STD_LOGIC);

end sai; architecture Behavioral of sai is begin d

<= a xor (bi xor c); bo <= (bi and c) or ((not a) and

c) or ((not a) and bi); end Behavioral;

Behavioral Modelling : library

IEEE; use

IEEE.STD_LOGIC_1164.ALL;

entity sai is Port ( a : in

STD_LOGIC; bi : in

STD_LOGIC; c : in

STD_LOGIC; d : out

STD_LOGIC; bo : out

STD_LOGIC); end sai;

architecture Behavioral of sai is

begin process(a,bi,c) begin

if(a='0' and bi='0') then d<=c;

bo<=c; elsif(a='0' and bi='1')

then d<= not c; bo<= '1';

elsif(a='1' and bi='0') then d<=

not c; bo<= '0'; else d<=c;

bo<=c; end if; end process; end

Behavioral;

Structural Modelling :
library IEEE; use

IEEE.STD_LOGIC_1164.ALL;

entity rama is

Port ( a : in STD_LOGIC;

bi : in STD_LOGIC; c : in

STD_LOGIC; d : out

STD_LOGIC; bo : out

STD_LOGIC); end rama;

architecture Behavioral of rama is

component hs1 port(w,x : in

STD_LOGIC; y,z : out

STD_LOGIC); end component;

component or1 port(o,r : in

STD_LOGIC;

g : out STD_LOGIC); end

component; signal

s1,s2,s3:STD_LOGIC; begin

f1:hs1 port map(a,bi,s1,s2);

f2:hs1 port map(s1,c,d,s3);

f3:or1 port map(s3,s2,bo);

end Behavioral;
 Experiment - 10
Aim : To implement VHDL code for SR flip flop and test simulation with
signal.
APPARATUS REQUIRED: Xilinx software.

library IEEE; use

IEEE.STD_LOGIC_1164.ALL;

entity SR is
Port ( S : in STD_LOGIC;
R : in STD_LOGIC;
CLK : in STD_LOGIC;
Q : out STD_LOGIC); end SR;

architecture Behavioral of SR is
signal p : std_logic;

begin process(S,R,CLK) begin

if(CLK'event and CLK = '1') then

if (S = '0' and R = '0') then

P<=P; elsif(S = '0' and R = '1')

then p<='0'; elsif(S='1' and

R='0') then p<='1'; elsif(S='1'

and R ='1') then P<='Z'; end if;

Q<=p;
end if; end

process; end
Behavioral;
 Experiment - 11
Aim: To implement VHDL code for JK flip flop and test simulation with
signal.
APPARATUS REQUIRED: Xilink software.
library IEEE; use

IEEE.STD_LOGIC_1164.ALL;

entity ssr is
Port (j: in STD_LOGIC;

k: in STD_LOGIC; clk: in
STD_LOGIC; q: out

STD_LOGIC); end ssr;

architecture Behavioural of ssr is

signal p: std_logic;

begin process (j,k,clk) begin

if(clk'event and clk = '1') then if (j

='0' and k = '0') then p<=p;

elsif (j='0' and k = '1') then

p<='0'; elsif (j ='1' and k=

'0') then p<= '1'; else p<=

not p; end if; end if; q<=p;

end process;

end Behavioural;
 EXPERIMENT -12

AIM: To implement VHDL code for 2*2 binary multiplier and test their
simulation with signal.
APPARATUS REQUIRED: Xilink software, simulation tool

Using STRUCTURAL MODELLING

library IEEE; use

IEEE.STD_LOGIC_1164.ALL;

entity ssr is
Port ( A1,A0,B1,B0 : in STD_LOGIC;
P0,P1,P2,P3 : out STD_LOGIC); end

ssr; architecture behavioural of ssr is

component andgate1

port( u,v : in std_logic;

W: out std_logic);

end component;
component ssrHA1
port (a,b : in std_logic;
s,c : out std_logic);

end component; signal

S1,S2,S3,S4: STD_LOGIC; begin

G1: andgate1 port map(A0,B0,P0);

G2: andgate1 port map(A1,B0,S1);
G3: andgate1 port map(A0,B1,S2);
G4: andgate1 port map(A1,B1,S3);
G5: ssrHA1 port map(S1,S2,P1,S4); G6:
ssrHA1 port map(S3,S4,P2,P3); end

behavioural;
HALF ADDER CODE
library IEEE; use
IEEE.STD_LOGIC_1164.ALL;

entity ssrHA1 is

Port ( a ,b : in STD_LOGIC ;
s ,c : out STD_LOGIC);

end vibhanshuHA1; architecture

behavioural of ssrHA1 is begin

process (a,b)

begin

if (a='0') then
s <= b;

c <= '0';
 else

s <= NOT b;
c <= b; end if;

end process;

end behavioural;

AND GATE CODE

library IEEE; use
IEEE.STD_LOGIC_1164.ALL; entity

ssrandgate1 is Port ( u : in
STD_LOGIC; v : in STD_LOGIC;

w : out STD_LOGIC); end andgate1;

architecture Behavioral of ssrandgate1 is

begin w <= u and v; end Behavioral;