UNIT-I Introduction to PIC Microcontroller

UNIT I
INTRODUCTION TO PIC MICROCONTROLLER
Introduction to PIC Microcontroller–PIC 16C6x and PIC16C7x Architecture–
PIC16cxx–- Pipelining -Program Memory considerations – Register File
Structure - Instruction Set - Addressing modes –Simple Operations.

INTRODUCTION TO PIC MICRO CONTROLLERS

1. INTRODUCTION
The term PIC stands for Peripheral Interface Controller .It is the brain
child of Microchip Technology, USA . Originally this was developed as a
supporting device for PDP computers to control its peripheral devices, and
therefore named as PIC, Peripheral Interface Controller. These 8-bit micro
controllers have become very important now -a -days in industrial automation
and embedded applications etc.
One of the earlier versions of PIC Microcontrollers is PIC16C6x/7x. The
7x family has an enhancement of Analog to Digital converter capability. These
cs are available with a range of capabilities packaged in both dual in-line (DIP)
packages and surface-mount packages. These are available in 28 pin DIP, 40
pin DIP, 44 pin surface mount package…etc. Some of PIC controllers contain
the letter A in their number. The presence of A indicates the brown-out reset
feature, which causes a reset of the PIC when the Power Supply voltage drops
below 4.0v.
Overview and Features
The PIC 16F8XX Microcontrollers are basically RISC microcontrollers with
very small instruction set of only 35 instructions and a two-stage pipeline
concept fetch and execution of instructions. As a result, all instructions
execute in a single cycle except for program branches.
It has two types of internal memories .One is program memory and the other
is data memory. Program memory is provided by 8K words (or 8K*14 bits) of
FLASH Memory, and data memory has two sources. One type of data memory
is a 368-byte RAM (random access memory) and the other is256-byte EEPROM
(Electrically erasable programmable ROM). Power consumption is less than 2
mA in 5V operating condition.
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Low-end Architectures
Microchip PIC microcontrollers are available in various types. When PIC −
MicroCU first became available from General Instruments in early 1980’s, the
microcontroller consisted of a very simple processor executing 12-bit wide
instructions with basic I/O functions and limited program memory. These
devices are known as low-end architectures.
Example: PIC 12C5XX, PIC 16C5XX, PIC 16C505
Mid-range Architectures
Mid-range Architectures are built by upgrading low-end architecture with more
number of peripherals, more numbers of register and more data memory. Some
of the mid-range devices are PIC 16C6X PIC16C7X, PIC16F87X. C and F
indicates the types of program memory.
Type C = EPROM F = Flash and RC = Mask ROM

SALIENT FEATURES
 Speed :
When operated at its maximum clock rate at its 200Mhz , i.e, PIC
executes most of its instructions in 0.2 s or five instructions per microsecond.
i.e 1 instruction cycle = 4 clock cycles.
 Instruction set Simplicity :
The instruction set is so simple that it consists of only just 35 instructions (as
opposed to 111 instructions for 8051).
 Power on Reset:
PIC will be Reset whenever the power is on,. A watch dog timer resets the
PIC if the chip malfunctions or deviates from its normal operation at any time.
 Brown out Reset:
PIC will be Reset whenever voltage drops under 4.0 volts.
 Programmable timer options:
Three timers can characterize inputs, control outputs and provide
internal timing for the program execution.
 Powerful output pin control:
A single instruction can select and drive a single output pin high or low
in its 0.2 s instruction execution time. The PIC can drive a load of up to
25A.
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 I/O port expansion:

With the help of built in serial peripheral interface the number of I/O
ports can be expanded. EPROM/DIP/ROM options are provided.

 High performance RISC CPU

 Operating speed: DC – 20 MHz clock input DC – 200 ns instruction cycle
 Eight level deep hardware stack
 Direct, indirect and relative addressing modes
 Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)
 Three Timers Timer0,Timer 1 and Timer 2.
 Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable
operation
 Programmable code-protection
 Power saving SLEEP mode
 10-bit multi-channel Analog-to-Digital converter
 Selectable oscillator options
 One USART /SCI port with 9-bit address detection.
 Low-power, high-speed CMOS EPROM/ROM technology
 Fully static design
 Wide operating voltage range: 2.5V to 6.0V
 Commercial, Industrial and Extended temperature ranges
 Low-power consumption: <2mA @5V, 4MHz, 15 A typical @ 3V, 32 kHz, <1
A typical standby current

Harvard Architecture

The high performance of the PIC16CXX family can be attributed to a number of

architectural features commonly found in RISC microprocessors. To begin with,
the PIC 16CXX uses a Harvard architecture, in which, program and data are
accessed from separate memories using separate buses. This improves
bandwidth over traditional Von Neumann architecture where program and data
may be fetched from the same memory using the same bus.As the PIC
16c6x/7x family of micro-controllers uses Harvard Architecture it enables the
devices exceptionally fast execution speed for a given clock rate. In the Harvard
 UNIT-I Introduction to PIC Microcontroller

Architecture separate buses are used for Data and Instruction as shown in the
diagram.

Instructions are fetched from program memory using buses that are distinct
from the buses used for accessing variables in data memory, I/O ports etc.
Every instruction is coded as a single 14-bit word and fetched over a 14-bit
wide bus.

Separating program and data buses further allows instructions to be sized

differently than 8-bit wide data words. Instruction op-codes are 14-bits wide
making it possible to have all single word instructions. A 14-bit wide program
memory access bus fetches a 14-bit instruction in a single cycle

1.1 ARCHITECTURE OF PIC 16C67 (8 – bit microcontroller)

The PIC16FXX is a family of low-cost, high-performance, CMOS, fully-

static, 8-bit microcontrollers.
All PIC microcontrollers employ an advanced RISC architecture. The
PIC16FXX microcontroller family has enhanced core features, eight-level deep
stack, and multiple internal and external interrupt sources. The two-stage
instruction pipeline allows all instructions to execute in a single cycle, except
for program branches (which require two cycles). A total of 35 instructions
(reduced instruction set) are available. Also, a large register set helps to
achieve a very high performance.
The PIC 16FXX uses Harvard architecture, in which, program and data
are accessed from separate memories using separate buses. This improves
bandwidth over traditional Von Neumann architecture where program and data
 UNIT-I Introduction to PIC Microcontroller

may be fetched from the same memory using the same bus. Separating
program and data buses further allows instructions to be sized differently than
8-bit wide data words. Instruction opcodes are 14-bits wide making it possible
to have all single word instructions. A 14-bit wide program memory access bus
fetches a 14-bit instruction in a single cycle. A two-stage pipeline overlaps fetch
and execution of instructions. Consequently, all instructions execute in a
single cycle (200 ns@ 20MHz) except for program branches.
The PIC 16C6X devices have a 13-bit program counter capable of addressing
an 8Kx14 program memory space. The PIC 16FF876/877 devices have 8Kx 14
words of Flash program memory.

Figure 1.1 Block diagram of PIC 16C67 Microcontroller

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Figure 1.1 Block diagram of PIC 16C77 Microcontroller

The above architecture is divided into three parts, such as fetching, decoding
and executing.
Clock generation:
The clock input(from OSC1) is internally divided by four to generate four clocks
namely Q1, Q2, Q3 and Q4. Internally, the program counter is incremented
every Q1, the instruction is fetched from the program memory and latched into
the instruction register in Q4. The instruction is decoded and executed during
the following Q1 through Q4.
Fetching and Decoding:
Program counter (PC) is used to point the next instruction to be fetched.
Fetched instruction from the program memory will be stored in the instruction
register and it will be decoded in the instruction decoding unit.
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i) Program Counter (PC – 13 bit):

The low byte comes from the PCL register, which is readable and writable
register. The upper bits are not readable but are indirectly writable through
PCLATH register. On any reset, the upper bits of the PC will be cleared.
ii) Stack pointer(SP – 13 bit):
The Stack Pointer is not part of either program or data space. The Program
counter is pushed on to the stack when a CALL instruction is executed or an
interrupt or branch instruction to store the return address. The stack is
Popped in the event of return instruction execution (retrieving return address
from stack).
Execution:
iii) Arithmetic & logic Unit (ALU): (8-bit)
The ALU is a general purpose arithmetic unit. It performs arithmetic and
boolean operation between the data in the working register and any register
file. The ALU is 8 bits wide and capable of addition, subtraction, shift and
logical operations.
In two operand instructions, typically one operand is the working register (W
register) the other operand is a file register or an immediate constant. In a
single operand instructions, the operand is either the W register or a file
register.
iv) Working Register (W- 8 bit):
The W register is an 8 bit working register used for ALU operations. It is used
by many instructions as the source of an operand. It also serves as the
destination for the result of instruction execution (similar to accumulator). It is
not an addressable register.
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v) Status Register (8 bit):

This is an 8-bit register which denotes the status of ALU after any arithmetic
operation and also RESET status and the bank select bits for the data
memory.

C: Carry/borrow bit
DC: Digit carry/borrow bit
Z: Zero bit
NOT_PD : Reset Status bit (Power-down mode bit)
NOT_TO : Reset Status bit (time- out bit)
RPO: Register bank Select
• The bits 7 and 6 of Status Register are unused by 16C6x/7x. The ‘C’ bit is
set when two 8-bit operands are added together and a 9-bit result occurs.
This 9-bit is placed in the carry bit.
• The DC or Digit carry bit indicates that a carry from the lower 4 bits
occurred during an 8-bit addition.
Example: 0011 1000
0011 1000
0111 0000
• Here DC=1 as a result of the carry from the bit 3 to the bit 4 position.
• The Z or zero bits is affected by the execution of arithmetic or logic
instructions.
• The reset status bits NOT_TO and NOT_PD are used in conjunction with
PIC’s sleep mode. The micro controller can put itself to sleep mode to save
power during intervals when it has nothing to do. It can be reset by any of
three kinds. Upon reset the CPU can check these two reset status bits to
determine which kind of event resettled it and then respond accordingly.
• The Register bank select bit RPO is used to select either bank or bank. When
RPO=0, select Bank 0, RPO=1, select Bank 1
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vi) File Select Register (FSR – 8 bit):

It is the pointer used for indirect addressing. It is a special purpose register
that serves as an address pointer to any address throughout the entire
register file.
vii) Indirect File:
It is not a physical register addressing but this INDF will cause indirect
addressing. Any instructions using the INDF register actually access the
register pointed to by the FSR.
viii) Parallel I/O Ports
Most of the PIC16cx/7x family controllers have 33 I/O lines and five I/O ports
They are PORT A, PORT B, PORT C , PORT D and PORT E.
viii) PORTS:
PORT A:
Port A is a 6-bit wide bi-directional port. Its data direction register is TRISA
setting TRISA bit to 1 will make the corresponding PORT A Pin an input.
Clearing a TRIS a bit will make the corresponding pin as an output.
PORT B:
Port B is an 8-bit wide, bi-directional port. Four of the PORT B pins RB7 – RB4
have an interrupt-on- change feature. Only the pins configured as inputs can
cause this interrupt to occur.
PORT C:
Port C is an 8-bit wide, bidirectional port. Bits of the TRISC Register determine
the function of its pins. Similar to other ports, a logic one 1 in the TRISC
Register configures the appropriate port pin as an input.
PORT D:
Port D is an 8-bit wide bi-directional port. In addition to I/O port, Port D also
works as 8-bit parallel slave port or microprocessor port. When control bit
PSPMODE (TRISE:4) is set.
PORT E:
It is a 3-bit bi-directional port. Port E bits are multiplexed with analog inputs of
ADC and they serve as control signals (RD , WR, CS) for parallel slave port
mode of operation.
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ix) Timers:
It has 3 timer modules such as Timer 0 (8 – bit overflow counter), Timer 1 (16 –
bit Timer/counter), Timer 2 (8 – bit timer). Each module can generate an
interrupt to indicate that an event has occurred (i.e timer overflow)
x) Watch Dog Timer (WDT):
A Watch dog timer is a simple timer circuit that performs a specific operation
after a certain period of time if something goes wrong. Suppose we have written
a program which is compiled successfully and when we simulate if every time
seems to work fine. Then we program the PIC. However after a long period of
time the program gets stuck somewhere. What needs it this case is some kind
of reset if the program is gets stuck. This is a purpose of a watchdog timer
circuit. When the WDT is enable counter starts at 00 and increment by 1 until
it reaches FF. When it goes from FF to 00 the PIC will be reset, irrespective of
what it is doing. The only way we can stop the WDT, from resetting the WDT
back to 00 throughout the program which is done by the processor. Which
indicates that the processor functioning is going on. Watch dog timer is thus

increase the system reliability.

xi) Capture – Compare – PWM (CCP):
• Capture mode captures the 16-bit value of TMR1 into the CCPRxH:CCPRxL
register pair. The capture event can be programmed for either the falling
edge, rising edge, fourth rising edge, or sixteenth rising edge of the CCPx
pin.
• Compare mode compares the TMR1H:TMR1L register pair to the
CCPRxH:CCPRxL register pair. When a match occurs, an interrupt can be
generated and the output pin CCPx can be forced to a given state (High or
Low) and Timer1 can be reset. This depends on control bits
CCPxM3:CCPxM0.
• PWM mode compares the TMR2 register to a 10-bit duty cycle register
(CCPRxH:CCPRx) as well as to an 8-bit period register (PR2). When the
TMR2 register=Duty Cycle register, the CCPx pin will be forced low. When
TMR2=PR2, TMR2 is cleared to 00h, an interrupt can be generated, and the
CCPx pin (if an output) will be forced high.
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1.3 PIPELINING:
Overlapped movement of instruction to the processor is called pipelining.
The CPU executes each instruction during the cycle following its fetch,
pipelining instruction fetches and instruction executions to achieve the
execution of one instruction every cycle. This is illustrated in Figure 1.3.1. It
can be seen that while each instruction requires two cycles (a fetch cycle
followed by an execute cycle), the execution of nth unit is overlapped with the
fetch of (n+1)th instruction. In every cycle new instructions are fetched
The normal process is broken whenever an instruction includes a
branch operation, CALL instruction, GOTO Address as illustrated on Figure
1.3.2.
 In this example, instruction is fetched during the second cycle, goto New
Address, whose job it is to change the normal flow of instruction fetches
from one address to the next address.
 During the third cycle, the CPU carries out the sequential fetch from
address n+2.
 At the end of that third cycle, the CPU executes the goto New Address
instruction by changing the program counter to New Address instead of
simply incrementing it to n+3.
 On the fourth cycle while it is fetching the instruction at New Address , it
ignores the instruction automatically fetched from address n+2. While
this (n+2)th instruction is located in the program immediately after the
(n+1)th goto New Address instruction, it is never executed immediately
after the execution of that (n+1)th goto New Address instruction.
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Fig 1.3.1. Pipelining of instruction fetch successive addressing

Figure 1.3.2 Extra cycle for a jump/goto Instruction

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1.4 MEMORY ORGANIZATION :

The memory module of the PIC controller has three memory blocks.
a) Program memory
b) Data memory and
c) Stack
a) Program Memory:
The PIC 16F8XX has 4k x14 program memory space (0000H-0FFFH).It
has a 13 bit Program counter(PC) to access any address (213=4k). This PIC
family uses 13-bit program counter allowing the controllers to an 8k-program
memory without changing the CPU structure.

Figure 1.4.1 Program memory access for PIC parts having 2K of program
memory.
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Figure 1.4.2 Program memory access for PIC parts having 4K of program
memory.
An independent 8-level stack is used for the program counter. As the program
counter is 13bit, the stack is organized as 8x13bit registers. When an interrupt
occurs, the program counter is pushed onto the stack. When the interrupt is
being serviced, other interrupts remain disabled. Hence, other 7 registers of
the stack can be used for subroutine calls within an interrupt service routine
or within the mainline program. The Program memory and Stack memory shown in
below.
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Figure 1.4.3. Program memory allocation and STACK memory Map

Two addresses in the program memory address space are treated in a special
way by the CPU. When the CPU starts up from its reset state, its program
counter is automatically cleared to zero. This is illustrated in Figure 1.4.1. with
the content of address H'000’ being a go to Mainline instruction. The second
special address H'004' , is automatically loaded into the program counter when
an interrupt occurs. A goto IntService instruction can be assigned to this
address, to cause the CPU to jump to the beginning of the interrupt service
routine, located elsewhere in the memory space. When we deal with tables,
they are assigned to addresses in the range H’005 – H’0FF’ because for most of
the applications this space is sufficient. The main line program begins after the
tables.
On reset, the program counter is cleared and the program starts at 00H. Here a
'goto' instruction is required that takes the processor to the mainline program.
When a peripheral interrupt enable is received, the processor goes to 004H. A
suitable branching to the interrupt service routine (ISR) is written at 004H.
 The mainline program begins execution when the PIC comes out of reset. It
continues running until one of the PIC’s interrupt sources requests service.
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 At that point the execution of the mainline code is temporarily suspended.

 The CPU begins the execution of the interrupt service routine by
automatically loading the program counter with H'004'.
 At the completion of the interrupt service routine, the CPU returns to where
it left off in the mainline program

after PIC reset

PC = 4500 ------------- NEW PC = xxxx --------------
4501 ------------- xxx1 --------------
4502 ------------- -
4503 CALL xxxx -
(PIC interrupt sources xxx8 -Return address
required service) popped from stack

4504 -------- ( 4504 will be

pushed onto stack)

 As shown in Figure 1.4.4, bits 10…0 of the call instruction are loaded into
the program counter. At the same time, bits 4 and 3 of a special register
called PCLATH (“program counter latch”) are loaded into bits 12 and 11 of
the program counter.
 As long as the program memory is less than 2048(i.e.,2K) words, bits 4
and 3 of PCLATH can be left initialized to H'00', and then the 11 address
bits in the call instruction will identify the starting address of any
subroutine located up to address H'7FF'.
 For the programs larger than this, it is necessary to ensure that bit 3 of

PCLATH is set or cleared appropriately each time a subroutine is called.

The goto instruction, which also has an 11-bit address field, requires an

identical treatment.
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Figure 1.4.4 Addressing used by subroutine calls

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1.5 DATA MEMORY

The data memory of PIC 16F8XX is partitioned

into multiple banks which contain the general
purpose registers and the Special function
Registers.(SFRs).The bits RP1 and RP0 bits of
the status register are used to select these
banks. Each bank extends upto 7FH(128
Bytes).The lower bytes of the each bank are
reserved for the Special Function
Registers.Above the SFRs are general purpose
registers implemented as static RAM.

Figure 1.5 Data Memory Map

1.6 REGISTER FILE STRUCTURE

The term register file is used to denote the location that an
instruction can access via an address. The register file consists of 2
components:
a) General Purpose Register File
b) Special Purpose Register File

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a) General Purpose Register File:

The general purpose register file is another name for the
microcontroller’s RAM . Data can be written to each 8-bit location updated
and retrieved any number of times. It can be accessed either directly or
indirectly through the File Select Register.
b) Special Purpose Register File :
The special function registers are used by the CPU and Peripheral
modules for controlling the desired operation of the device, it consists of
input, output ports and control registers used to configure each 8-bit port
either as input or output. It contains registers that provide the data input
and data output to a chip resources like Timers, Serial Ports and Analog
to Digital converter and also the registers that contains control bits for
selecting the mode of operation and also enabling or disabling its
operation.

Figure 1.6 Register file structure

1.7 CPU REGISTERS

The CPU registers are used in the execution of the instruction of
the PIC microcontroller. The PIC PIC16C6X Microcontroller has the
following registers.

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1. Working Register-W (Similar to Accumulator)

2. Status Register
3. FSR – File Select Register (Indirect Data memory address pointer)
4. INDF – INDirect File register
5. Program Counter
1. Working Register:
Working Register is used by many instructions as the source of an
operand. It also serves as the destination for the result of instruction
execution and it is similar to accumulator in other cs and ps.
2.Status Register:
This is an 8-bit register which denotes the status of ALU after any
arithmetic operation and also RESET status and the bank select bits for
the data memory.

C: Carry/borrow bit
DC: Digit carry/borrow bit
Z: Zero bit
NOT_PD : Reset Status bit (Power-down mode bit)
NOT_TO : Reset Status bit (tme- out bit)
RPO: Register bank Select
The bits 7 and 6 of Status Register are unused by 16c6x/7x. The ‘C’
bit is set when two 8-bit operands are added together and a 9-bit result
occurs. This 9-bit is placed in the carry bit.
The DC or Digit carry bit indicates that a carry from the lower 4 bits
occurred during an 8-bit addition.
Example: 0011 1000
0011 1000
0111 0000
Here DC=1 as a result of the carry from the bit 3 to the bit 4
position.

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The Z or zero bits is affected by the execution of arithmetic or logic

instructions.
The reset status bits NOT_TO and NOT_PD are used in conjunction
with PIC’s sleep mode. The micro controller can put itself to sleep mode to
save power during intervals when it has nothing to do. It can be reset by
any of three kinds. Upon reset the CPU can check these two reset status
bits to determine which kind of event resettled it and then respond
accordingly.
The Register bank select bit RPO is used to select either bank or
bank.When RPO=0, select Bank 0, RPO=1, select Bank 1.
Example: bcf STATUS, RPO ; Select bank 0
bsf STATUS, RPO ; Select bank 1.
3.FSR – (File Select Register):
It is the pointer used for indirect addressing. In the indirect
addressing mode the 8-bit register file address is first written into FSR. It
is a special purpose register that serves as an address pointer to any
address through out the entire register file.
4.INDF – (Indirect File):
It is not a physical register addressing but this INDF will cause
indirect addressing. Any instruction using the INDF register actually
access the register pointed to by the FSR.
5 .PCL and PCLATH Register:

The final feature of the CPU registers is the role of PCL and PCLATH.
 PCL is actually the lower 8 bits of the 13-bit program counter. It
can be read, just like any other register.
 PCLATH is not the upper 5 bits of the PC. PCLATH can be read from
or written to without affecting the PC. The upper 3 bits of PCLATH

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remain zero(and there is no purpose). It is only when PCL is written

to that PCLATH is automatically written into the program counter at
the same time.
6. PROGRAM COUNTER:

 The program counter is supported by an eight level stack. When an

interrupt occurs, the program counter is automatically pushed onto
the stack, so further interrupts remain disabled while any interrupt
source is being serviced, only one of the eight stack location is needed
to deal with the interrupt return address.
 The other seven levels can be divided between nested subroutine
within the interrupt service routine and nested subroutines within the
mainline program
1.8 ADDRESSING MODES.
The PIC microcontrollers support only TWO addressing modes .They are
(i) Direct Addressing Mode
(ii) Indirect Addressing mode
Direct Addressing Mode :
In direct addressing mode 7 bits (0-6) of the instruction identify the
register file address and the 8 th bit of the register file address must come
from a separate register bank select bit(RP0). Figure 1.8.1 shows direct
addressing being used to access register file address 14 or 94 depending
on the value of RP0.

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Figure 1.8.1 Direct Addressing

The above figure 1.8.1 explains the method of accessing register file
address 13H by direct addressing method.
Indirect Addressing Mode
In the indirect addressing mode the 8-bit register file address is first
written into a Special Function Register(SFR) which acts as a pointer to
any address location in the register file. A subsequent direct access of
INDF will actually access the register file using the content of FSR as a
pointer to the desired location of the operand. To use indirect addressing,

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the desired 8-bit address must first be written into FSR using direct
addressing. To make the possible value of the register bank select bit,
RP0, the FSR register is accessed at either address 04 or 84.
0000 0100 H = 04
1000 0100 H = 84
It can be seen that differ only in the bit controlled by RP0 during direct
addressing. Consequently a write to either 04 or 84 will write into the FSR
register.

Figure 1.8.2. Indirect Addressing mode

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1.9 INSTRUCTION SET

While writing the instructions the following guidelines are followed.
a) Write the instructions mnemonics in lower case (example: xorwf)
b) Write special Register names, RAM variable names and bit names in
upper case (example: STATUS, RPO….)
c) Write instruction and subroutine labels in mixed case (example:
Mainline, LoopTime..)
The instruction set of PIC is divided into three basic categories.
They are
(a) Byte oriented Instructions
(b) Bit oriented Instructions
(c) Literal and Control Instructions
Byte Oriented Instructions
In a byte oriented Instructions f represents a file register and d
represents destination register. The destination specifies where the result
of operation is to be placed. If D= 0 the result is placed in W
register(Accumulator) and if d = 1 , the result is placed in the file register
specified in the instruction.
addwf f, d ; add w and f
clrf f ; clear f
movwf f ,d ; move f
nop ; no operation
subwf f ,d ; subtract w from f

Bit Oriented Instruction

In bit oriented instructions, b represents a bit field designator which
selects the number of the bit affected by the operation and f represents
the number of the file in which the bit is located.

bcf f , b ; bit clear f

bsf f, b ; bit set f
btfsc f,b ; bit test f ,skip if set

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Literal and Control Instrucrtions

In literal and control instructions K represents an 8 or 11 bit constant or
literal value.
addlw k ; add literal and w
andlw k ; and literal with w
call k ; call subroutine
movlw k ; move literal to w
sublw k ; subtract w from literal
Based on the type of operation PIC supports various Instructions. They
are explained below.

CLASSIFICATION OF INSTRUCTIONS
All the instructions of the PIC microcontroller are classified into nearly 9
groups. They are given below with examples.
(i).Arithmetic Operations :
addlw k ; add literal value k to w
addwf f, d ; The contents of the W register are added with
the register f.
subwf f ,d ; the contents of W register are subtracted from
register f
(ii).Logical Instructions :
andlw k ; The contents of W register are ANDED with the 8-bit
literal k. The result is stored in the W register.
iorlw k ; Inclusive OR the literal value into W register
xorwf f,d ; The contents of W register are XORed with register f
and the result is stored in W or f.
comf f, d ; Complement f .
(iii).Increment/Decrement Instructions
incf f ,d ; Increment contents of f register by 1
decf f , d ; Decrement f by 1
(iv).Data Transfer instructions :
movf f,d ; Move f to W i.e The contents of register f is moved
to a destination depending on d

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movlw k ; Move literal k to W

movwf f ; Move W to f
(v) Clear Instructions
clrf ; Clear file f
clr w ; Clear the contents of W register and zero bit is set
clrwdt ; Clear Watch dog timer
bcf ; Clear bit b of register f.
(vi)Rotate Instructions
rlf ; Rotate Left f through carry
rrf ; Rotate Right f through carry
(vii). Branch Instructions : There are two types of Branch
instructions.(i)Conditional Branch and (ii) Un conditional Branch
instructions.
(i) Conditional Branch Instructions
btfsc f , b ; Bit Test skip if clear
btfss f , b ; Bit test f , skip if set
If bit B in register f is zero ,then the next instruction is executed,
otherwise next instruction is discarded and a NOP is executed.
decfsz f,d ; Decrement f ,skip if zero.
incfsz f,d ; Increment f ,skip if zero

(ii) Unconditional Instructions

call k ; Call the subroutine k unconditionally
goto k ; Unconditional k branch
return ; Return from subroutine
reetlw k ; Return with literal in W register.
(viii Miscellaneous
bsf f,b ; Set bit b of register f
sleep ; Go into stand by mode
nop ; No operation i.e Do nothing , wait one clock
cycle.

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The various instructions used in PIC are presented in the Table below.
Single-bit manipulation Operation
bcf PORTB, 0 ;Clear bit 0 of PORTB
bsf STATUS, C ;Set the carry bit
Clear/move
Clrw ;Clear the working register, W
clrf TEMP1 ;Clear temporary variable TEMP1
movlw 5 ;Load 5 into W
movlw 10 ;Load D ‘10’ or H ‘10’ into W
;depending upon default representation
movwf TEMP1 ;Move W into TEMP1
movwf TEMP1, F ;Incorrect syntax
movf TEMP1, W ;Move TEMP1 into W
swapf TEMP1, F ;Swap 4-bit nibbles of TEMP1
swapf TEMP1, W ;Move TEMP1 to W, swapping nibbles
;and leave TEMP1 unchanged
Increment/decrement/compleme
nt
incf TEMP1, F ;Increment TEMP1
incf TEMP1, W ;W < - TEMP1 + 1; TEMP1 unchanged
decf TEMP1, F ;Decrement TEMP1
comf TEMP1, F ;Change 0s to 1s and 1s to 0s
Multiple-bit manipulation
andlw B’00000111’ ;Force upper 5 bits of W to zero
andwf TEMP1, F ;TEMP1 < - TEMP1 and W
andwf TEMP1, W ;W < - TEMP1 AND W
iorlw B’00000111’ ;Force lower 3 bits of W to one
iorwf TEMP1, F ;TEMP1 < - TEMP1 or W
xorlw B’00000111’ ;Complement lower 3 bits of W
xorwf TEMP1, W ;W < - TEMP1 XOR W
Addition/Subtraction
addlw 5 ;Add 5 to W

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addwf ;TEMP1 < - TEMP1 + W

TEMP1, F ;W < - 5 – W (not W < - W – 5!)
sublw 5 ;TEMP1 < - TEMP1 – W
subwf TEMP1, F
Rotate
rlf TEMP1, F ;Nine-bit left rotate through C
;(C < - TEMP1, 7; TEMP1, I+1 < - TEMP1, I
; TEMP1, 0 < - C)
rrf TEMP1, W ; Leave TEMP1 unchanged
;copy to W and rotate W right through C
Conditional branch
btfsc TEMP1, 0 ;Skip the next instruction if bit 0 of
;TEMP1 equals zero
btfss STATUS, C ;Skip if C = 1
decfsz TEMP1 , F ;Decrement TEMP1; skip if zero
incfsz TEMP1, W ;Leave TEMP1 unchanged; skip if
;TEMP1 = H’FF’; W< - TEMP1 + 1
Goto/call/return/return from
interrupt
goto There ;Next instruction to be executed is
; labeled “There”
call Task1 ;Pushed return address; next instruction
;to be executed is labeled “Task1”
return ;Pop return address off of stack
retlw 5 ;Pop return address; W < -5
retfie ;Pop return address; reenable interrupts
Miscellaneous
Clrwdt ;If watchdog timer is enabled, this;
instruction will reset it (before it,;resets the
sleep CPU)
;Stop clock; reduce power; wait,;for
nop watchdog timer or external signal;to begin

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program execution again ;

Do nothing; wait one clock cycles

1.10 SIMPLE OPERATIONS

Either –or Sequence

Assume that an instruction that affects the Z bit has just been executed.
Then depending on the result one instruction sequence or another is to be
executed, continuing on after either case.

Decrement a 16- bit counter

Assume that the upper byte of the counter is called COUNTH and the
lower byte is called COUNTL

Note how the movf instruction is first used to test COUNTL for zero

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without changing it, and even without having to move it into W

Test a 16 – bit variable for zero

Using same COUNTH,COUNTL variable as previously , the following

sequence will either branch to an instruction labeled both zero if the
variable equals zero or to an instruction labeled carryon otherwise

The Ports of PIC controller are made either inpur or output ports by using
the TRISx register ,which is a SFR.To make the Port an output,0 must be
written to the TRISx register and to use the pPort as input ,a 1 must be
put in to the TRISx register. Fors example to make the PortB as input
port , the bits of TRISB are made 1(High).
The following example explains the I/O port programming.
Example 1: MOVLW 0x0
MOVWF TRISB ; make the Port B an output port.
L1 : MOVLW 0x55 ; WREG = 55
MOVWF PORTB ; Move 55 into portB.
CALL DELAY
MOVLW 0X AA
MOVWF PORTB ; Move AA into portB
CALL DELAY
GO TO L1
This program alternately loads Port B with 55 and AA.

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Example 2: In this example Port B and PORT C are used to transfer the
data continuously.
MOVLW B ‘00000000’ ; WREG = 00000000(Binary)
MOVWF TRISB ; Port B an out port
MOVLW B ‘11111111’ ;WREG = 11111111 (Binary)
MOVWF TRISC ; Port C input Port
L2 MOVF PORTC , W ;Move data from Port C to WREG.
Addlw 5 ; Add literal 5 to it.
MOVWF PORTB ; send it to Port B
GOTO L2 ; Continue the loop.

Example 3 : CLRF TRISB ; Clear TrisB( Port B is made outport)

SETF TRISC ; Set TRISC, (Port C is made Input port)
L2 : MOVF PORT C ,W ; Get data from Port C.
ADDLW 5 ; Add literal 5
MOVWF PORT B ; Send it to Port B
BRA L2 ; Branch to Loop L2

So , it is clear that unless the TRIS bits are activated by putting a 1 ,the
data will not be transferred to WREG from the port pins of PORT C

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APPENDIX : A Pin Digram OF PIC Micro Controller

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APPENDIX : B PIC16C6X Family

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APPENDIX : C PIC16C7X Family

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APPENDIX : D Architecture of PIC16C6X Family

PIC16C61

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PIC16C62/62A/R62/64/64A/R64 BLOCK DIAGRAM

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PIC16C63/R63/65/65A/R65 BLOCK DIAGRAM

PIC16C66/67 BLOCK DIAGRAM

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APPENDIX : E Architecture of PIC16C7X Family

PIC16C72 BLOCK DIAGRAM

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PIC16C73/73A/76 BLOCK DIAGRAM

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PIC16C74/74A/77 BLOCK DIAGRAM

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