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6th Sem - DSDV QP (A & B Section) - Paper 1

This document outlines the details of an internal test being administered by the Department of Electronics and Communication Engineering at ATME College of Engineering. The test covers the subject of Digital System Design Using Verilog. It will take place on May 30, 2017 from 3:00 PM to 4:00 PM for sixth semester students in sections A and B. The test contains two parts - Part A consists of 2 out of 3 questions worth 10 marks each, and Part B consists of 1 out of 2 questions worth 5 marks. The questions cover topics like arithmetic/logical/shift/memory instructions, developing a Verilog model of a dual port SRAM, field programmable gate arrays and CPLDs, differences between hard and soft errors,

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254 views1 page

6th Sem - DSDV QP (A & B Section) - Paper 1

This document outlines the details of an internal test being administered by the Department of Electronics and Communication Engineering at ATME College of Engineering. The test covers the subject of Digital System Design Using Verilog. It will take place on May 30, 2017 from 3:00 PM to 4:00 PM for sixth semester students in sections A and B. The test contains two parts - Part A consists of 2 out of 3 questions worth 10 marks each, and Part B consists of 1 out of 2 questions worth 5 marks. The questions cover topics like arithmetic/logical/shift/memory instructions, developing a Verilog model of a dual port SRAM, field programmable gate arrays and CPLDs, differences between hard and soft errors,

Uploaded by

chaitragowda213_4732
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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ATME COLLEGE OF ENGINEERING

DEPT OF ELECTRONICS AND COMMUNICATIONENGINEERING

THIRD INTERNAL TEST


SUB CODE : 10EC666 TIME: 3:00 PM- 4:00 PM
SUBJECT : Digital System Design Using Verilog DATE: 30-05-2017
SEM : Sixth Semester (A & B Section) MAX. MARKS:25

PART-A
.Answer any two Questions (TEN MARKS)
01 Explain arithmetic, logical, shift and memory instructions.
.
02 Develop a Verilog model of a dual port 4K x 16 bit flow through SSRAM. One port allows data to be
. written and read, while other port only allows data to be read.
03 Explain field programmable gate arrays and CPLD.
.
PART B
Answer any one Question (FIVE MARKS)
04 Differentiate between hard and soft errors.
.
05 Explain jump instructions.
.

THIRD INTERNAL TEST

ATME COLLEGE OF ENGINEERING


DEPT OF ELECTRONICS AND COMMUNICATIONENGINEERING

SUB CODE : 10EC666 TIME: 3:00 PM- 4:00 PM


SUBJECT : Digital System Design Using Verilog DATE: 30-05-2017
SEM : Sixth Semester (A & B Section) MAX. MARKS:25

PART-A
.Answer any two Questions (TEN MARKS)
01 Explain arithmetic, logical, shift and memory instructions.
.
02 Develop a Verilog model of a dual port 4K x 16 bit flow through SSRAM. One port allows data to be
. written and read, while other port only allows data to be read.
03 Explain field programmable gate arrays and CPLD.
.
PART B
Answer any one Question (FIVE MARKS)
04 Differentiate between hard and soft errors.
.
05 Explain jump instructions.
.

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