Digital Systems Design (DSD)

(for ECE 2021)

 Course Introduction

 Course description
 Module objectives
 Specific course learning outcomes
 Text/Reference Books
 Homework and exercises
 Final Exam
 Evaluation and grading policy
 Syllabus
 Lab

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 1. Course description

 An introduction to digital electronics, integrated circuits, numbering

systems, Boolean algebra, gates, flip-flops, multiplexers, sequential
circuits, combinational circuits, and computer architecture;
 Introduction to hardware description language and programmable logic
devices;
 Laboratory activities to include the design, construction, analysis, and
measurement of basic digital circuits;

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 2. Module objectives

 Binary number systems, number representations, and codes

 Boolean algebra and Boolean functions
 Logic gates and circuits
 Logic simplification using Boolean algebra and Karnaugh maps
 Combinational logic design and building blocks
 Synchronous sequential logic design and state machines
 Latches, flip-flops, registers and counters
 Programmable logic
 Memory basic

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 3. Specific course learning outcomes

 Understand, describe, and use different numerical systems such as

binary, decimal, hexadecimal, binary-coded decimal systems in
designing logic and arithmetic circuits
 Convert numbers from/to binary, decimal, and hexadecimal
 Interpret and use logic primitives, components, and libraries of a
hardware description language to implement a digital circuit
 Design logic circuits that use binary numbers
 Understand the principles of combining logic gates in different
integrated circuits (IC)

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 3. Specific course learning outcomes (cont.)

 Describe, derive, and simplify combinational logic expression using

tools and theorems in order to design and troubleshoot a
correspondent logic circuit
 Design and build combinational circuits using gates and inverters
 Design and build sequential circuits using gates, inverters and flip-
flops
 Analyze circuits that use more integrated devices such as
multiplexors, decoders, shift registers, counters, addressable
memories and FIFOs (first in, first out)

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 4. Text/Reference Books

Text Books
 Ronald J. Tocci, et al., “Digital Systems: Principles and
Applications,” 10th Edition, Pearson Education International, 2007,
ISBN: 0-13-172579-3.
 M. Morris R. Mano and Michael D. Ciletti, “Digital Design,” 4th
Edition, Pearson, 2006.
 Victor P. Nelson, “Digital Logic Circuit Analysis and Design,” 1st
Edition, Pearson, 1995, ISBN-10: 0134638948.
 Alan B. Marcovitz, “Introduction to Logic Design,” 3rd Edition,
McGraw-Hill, 2010, ISBN 978–0–07–319164–5.

Reference Books
 John F. Wakerly, “Digital Design: Principles and Practices,” 4th
Edition, Pearson, 2005, ISBN-10: 0131863894.
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 5. Homework and exercises

 Every lecture has an assignment. The submission deadline will be

given at the end of the lecture. All works presented must meet
professional standards regarding materials and format.
 The homework grade is 10% in the total grade of the course.
 No late homework will be accepted.

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 6. Team project

 Each group of 2-3 students will do a small project of digital

circuit design for practical applications. Different groups should
have different team projects.
 The topic will be proposed by each group under an agreement
of the instructor.
 The project grade (or the 15-min quick test) is 10% in the
total grade of the course.

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 7. Final Exam

 The final exam occupies 100% in the total grade of the course.
 It is a closed-book exam however students can use a cheat-sheet
with the size of A4.
 It is very important to note that students cannot be allowed to
increase the area of the A4-size paper.

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 8. Evaluation and grading policy (1)

Allocation of Marks
Home works 10%
Team project (the 15-min quick test) 10%
Final exam 100%
Extra points (bonus points in the 10%
class)/COVID-19
Total 120%

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 8. Evaluation and grading policy (2)

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 9. Syllabus in general

Lecture 1: Introductory Concepts

 1-1 Numerical Representations
 1-2 Digital and Analog Systems
 1-3 Digital Number Systems
 1-4 Representing Binary Quantities
 1-5 Digital Circuits/Logic Circuits
 1-6 Parallel and Serial Transmission
 1-7 Memory
 1-8 Digital Computers

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 9. Syllabus in general (cont.)

Lecture 2: Number Systems and Codes

 2-1 Binary-to-Decimal Conversions
 2-2 Decimal-to-Binary Conversions
 2-3 Hexadecimal Number System
 2-4 BCD Code
 2-5 The Gray Code
 2-6 Putting It All Together
 2-7 The Byte, Nibble, and Word
 2-8 Alphanumeric Codes
 2-9 Parity Method for Error Detection
 2-10 Applications
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 9. Syllabus in general (cont.)

Lecture 3: Describing Logic Circuits

 3-1 Boolean Constants and Variables
 3-2 Truth Tables
 3-3 OR Operation with OR Gates
 3-4 AND Operation with AND Gates
 3-5 NOT Operation
 3-6 Describing Logic Circuits Algebraically
 3-7 Evaluating Logic-Circuit Outputs
 3-8 Implementing Circuits from Boolean Expressions
 3-9 NOR Gates and NAND Gates
 3-10 Boolean Theorems

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 9. Syllabus in general (cont.)

Lecture 3: Describing Logic Circuits (cont.)

 3-11 DeMorgan’s Theorems
 3-12 Universality of NAND Gates and NOR Gate
 3-13 Alternate Logic-Gate Representations
 3-14 Which Gate Representation to Use
 3-15 IEEE/ANSI Standard Logic Symbols
 3-16 Summary of Methods to Describe Logic Circuit
 3-17 Description Languages Versus Programming Languages
 3-18 Implementing Logic Circuits with PLDs
 3-19 HDL Format and Syntax
 3-20 Intermediate Signals

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 9. Syllabus in general (cont.)

Lecture 4: Combinational Logic Circuits and CMOS Structures of

Logic Gates
 4-1 Sum-of-Products Form
 4-2 Simplifying Logic Circuits
 4-3 Algebraic Simplification
 4-4 Designing Combinational Logic Circuits
 4-5 Karnaugh Map Method
 4-6 Exclusive-OR and Exclusive-NOR Circuits
 4-7 Parity Generator and Checker
 4-8 Enable/Disable Circuits

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 9. Syllabus in general (cont.)

Lecture 4: Combinational Logic Circuits and CMOS Structures of

Logic Gates (cont.)
 4-9 Basic Characteristics of Digital ICs
 4-10 Troubleshooting Digital Systems
 4-11 Internal Digital IC Faults
 4-12 External Faults
 4-13 Troubleshooting Case Study
 4-14 Programmable Logic Devices
 4-15 Representing Data in HDL
 4-16 Truth Tables Using HDL
 4-17 Decision Control Structures in HDL

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 9. Syllabus in general (cont.)

Lecture 5: Flip-Flops and Related Devices

 5-1 NAND Gate Latch
 5-2 NOR Gate Latch
 5-3 Troubleshooting Case Study
 5-4 Digital Pulses
 5-5 Clock Signals and Clocked Flip-Flops
 5-6 Clocked S-R Flip-Flop
 5-7 Clocked J-K Flip-Flop
 5-8 Clocked D Flip-Flop
 5-9 D Latch (Transparent Latch)

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 9. Syllabus in general (cont.)

Lecture 5: Flip-Flops and Related Devices (cont.)

 5-10 Asynchronous Inputs
 5-11 IEEE/ANSI Symbols
 5-12 Flip-Flop Timing Considerations
 5-13 Potential Timing Problem in FF Circuits
 5-14 Flip-Flop Applications
 5-15 Flip-Flop Synchronization
 5-16 Detecting an Input Sequence
 5-17 Data Storage and Transfer
 5-18 Serial Data Transfer: Shift Registers
 5-19 Frequency Division and Counting

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 9. Syllabus in general (cont.)

Lecture 5: Flip-Flops and Related Devices (cont.)

 5-20 Microcomputer Application
 5-21 Schmitt-Trigger Devices
 5-22 One-Shot (Monostable Multivibrator)
 5-23 Clock Generator Circuits
 5-24 Troubleshooting Flip-Flop Circuits
 5-25 Sequential Circuits Using HDL
 5-26 Edge-Triggered Devices
 5-27 HDL Circuits with Multiple Components

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 9. Syllabus in general (cont.)

Lecture 6: Digital Arithmetic: Operations and Circuits

 6-1 Binary Addition
 6-2 Representing Signed Numbers
 6-3 Addition in the 2’s-Complement System
 6-4 Subtraction in the 2’s-Complement System
 6-5 Multiplication of Binary Numbers
 6-6 Binary Division
 6-7 BCD Addition
 6-8 Hexadecimal Arithmetic
 6-9 Arithmetic Circuits

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 9. Syllabus in general (cont.)

Lecture 6: Digital Arithmetic: Operations and Circuits (cont.)

 6-10 Parallel Binary Adder
 6-11 Design of a Full Adder
 6-12 Complete Parallel Adder with Registers
 6-13 Carry Propagation
 6-14 Integrated-Circuit Parallel Adder
 6-15 2’s-Complement System
 6-16 ALU Integrated Circuits
 6-17 Troubleshooting Case Study
 6-18 Using TTL Library Functions with HDL
 6-19 Logical Operations on Bit Arrays
 6-20 HDL Adders
 6-21 Expanding the Bit Capacity of a Circuit
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 9. Syllabus in general (cont.)

Lecture 7: Counters and Registers and Introduction to Hardware

Description Language (Verilog HDL + VHDL)
 7-1 Asynchronous (Ripple) Counters
 7-2 Propagation Delay in Ripple Counters
 7-3 Synchronous (Parallel) Counters
 7-4 Counters with MOD Numbers <2N
 7-5 Synchronous Down and Up/Down Counters
 7-6 Presettable Counters
 7-7 IC Synchronous Counters
 7-8 Decoding a Counter
 7-9 Analyzing Synchronous Counters
 7-10 Synchronous Counter Design

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 9. Syllabus in general (cont.)

Lecture 7: Counters and Registers and Introduction to Hardware

Description Language (Verilog HDL + VHDL) (cont.)
 7-11 Basic Counters Using HDLs
 7-12 Full-Featured Counters in HDL
 7-13 Wiring HDL Modules Together
 7-14 State Machines
 7-15 Integrated-Circuit Registers
 7-16 Parallel In/Parallel Out—The 74ALS174/74HC174
 7-17 Serial In/Serial Out—The 74ALS166/74HC166
 7-18 Parallel In/Serial Out—The 74ALS165/74HC165
 7-19 Serial In/Parallel Out—The 74ALS164/74HC164

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 9. Syllabus in general (cont.)

Lecture 7: Counters and Registers and Introduction to Hardware

Description Language (Verilog HDL + VHDL) (cont.)
 7-20 Shift-Register Counters
 7-21 Troubleshooting
 7-22 HDL Registers
 7-23 HDL Ring Counters
 7-24 HDL One-Shots

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 10. Labs

The course has 4 experiments.

Lab 1
 Two-way staircase switching circuit
 Battery level monitoring circuit
Lab 2
 Data transmission with parity-bit generator at the transmitter and
parity checking at the receiver
Lab 3
 Serial transfer of information from X register into Y register
 J-K flip-flops wired as a three-bit binary counter (MOD-8)
Lab 4
 An n-bit adder/subtractor description in VHDL

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VGU
VIETNAMESE-GERMAN UNIVERSITY

Bui Minh Duong

Lecturer in Electrical Power System
ECE program, Faculty of Engineering
Email: [email protected]
Mobile phone: 0918163356