sxopen )ightemitingdodes i es spay, (©) Tau ryt ipiny e (@ plasmadispay. © CRT ian 2, Digital computers use. leme ea rigoal ene Bia complement shacton, Them (© Vey spe process, (©) liminaonof erect sbscto, (© casyhandling of nepaive mines, (@)Simpifeason of ce 3. Personal omputercaotbe sed fowhich nt of follow used forwhich ne of he following? (©) Gamepiying. (0) "Weaterfeesing, © Offceasomaion. —(@) Homeeompatng ‘ees ue ere a 44. A personal computer as typically (@) 510 10 kilobytes of main memory. (©) 10t0 100 kilobytes of main memory. (© 10010256 kilobytes of main memory. (@ 256 kilobytes to 1 megabyte of main memory. TURSCLES ERE, wm ‘5. A group of personal computers are configured to work together ing up the execution ofa single program in ® @) %. Consider the following applications 1, Windwinnel simulation, 2. Real-time video viewing Acomputeris used for (neither I nor 2. © Lonly. (© bon and? @ 2enly, finscrns. exe, 20m 7. Thetecnigue foresing oe et of aresses ise anetworand Femappin hose adderes toa feret st dese that ae Seems local etwoicon he interes called (Gy network adress eslaton (b) address resolution. (©) erwork address maping (@) viral LAN 8 Whatiype ofaeworkis the Inemet? (0) Ceulcswithed newote (0) Message vtcea ner (©) Packedswiched network (@) Celbewiched ster rurscans exe, 9. Whichof he following stomens is conetinrespectof TCP and protocols? (0) FePisconecin-orented, whereas UP scomectoness @ TePisconecinies, wheres: UDP scomectonariznte (©) Both are connentonles, {Both are coneston-rente. 10: Btectve address is ealoulated by adding or subtracting Gipicemen valve fursc.ns. ere, 20m lursc.nes. ae, 208 ‘Answers: 1. (eB) 2. @, 3. (0) A. (B), 5 (8), 6. (0). 7. (@, 8. (€), 9. (), 10. (4), 11. (), 12. (©), 1B. (), 4. (WAS) 1G DAATEO) POERCS (immediate address, (©) absolute address. () relative address. (base address. TUnseies, Re, 201 4 ‘Consider the following: 1. Inputdevice 2. Arithmetic and logic unit 3. Control unit, 4, Auxiliary memory 5. Main memory 6. Activehub ‘Which ofthese form part of CPU? (@) 1,4and 6. (@) 2,3and6. (© 24ands. @ 23and5. {UPSC.LES E8200) 12, "The following micro-operatons are part of interrupt eyele of contro unit: 1. MAR @ save-address PC routine-address 2. MBR «= (PC) 3. Memory « (MBR) ‘Which one ofthe fllowing is the comect order of ther occurrence? (@) 1,2and3, @) 2,3and 1. ©) 21and3. @ Bt and 2. Girsc-nes, exe, 210; 207, 13, Whichof te following sre included inthe architecure of computer? 1. Addressing modes, design of CPU 2, Instetion set data formats 3. Secondary memory, operating system ‘Sethe correct answer using he codes given below: Chl: na. and 3, 1 oon ofa PSC ES Ey 14, Which of the following are included in the architect computer? 1. Addressing modes, CPU. 2, Instruction set, data formats. 3. Secondary memory, operating system. Selectthe correct answer from the codes given below: (@ Land? (>) Tand3 (@ 2and3 (@) 3omly. (UPSC.LES.ETE, 209) 15. The addressing mode that permits relocation, without any change ‘whatsoever in the code, is (@). indirect addressing. (©) indexed addressing. () base register addressing. (@)_PCrelativeaddressing. (UPSC.LES. ETE, 2016) 16, Ina microprocessor when a CPU is interrupted, it (@)_ stops execution of instructions. (@)_ acknowledges interrupt and branches of subroutine, (©) acknowledges interrupt and continues, (@) acknowledges interrupt and waits forthe next instruction from the interrupting device. (UPS.c. 128, BE, 280% 2015) 17, Thecontentof which ofthe following determines the state ofthe CPU atthe end ofthe execute cycle (when the interuptis recognized)? 1. Program counter, 2. Processor register. 3. Certain status conitions, Select the correct answer using the cades given below: Codes: (@ Land2. () 2and3. (©) Land3, (@) 1,2and3: (UPSC.LES, EE, 2001 ws\ ‘cin Ant i Integrate Cour in Eaton and Communication Engnering 38. Consider hypothetical processor with largest instruction length being 32-is and 16 registers RyRy. Proce suport ol following instructions: ae vt % ADD Ri,Rj | SUB Ri, Rj : AND Ri, Rj NOTRi MOV Ri, Rj i LOAD "Address Loads into register Ry | STORE Address Stores the content of Ry | JUMP Address | m ‘Address ‘What is the maximnam number of addres pins on this processor? OD OB © 9 @ 30 (wrseLes. ET, 200) ‘Which ofthe following fare comect statements)? 1, Busisa group of wires carrying information, 2. Busis needed to achieve reasonable speed of operation. 3. Busean cary data for address. 4. Abuscanbe shared by more than one device. Selectthe correct answer fom the codes given below : | @) Lonly. (@) Land 2 only. (©) 2,3and4only. @h 1. Band, [UPS LES. Ee, 209) , 20. (@) main frames, (©) supercomputers ‘Assngle bus structures primarily found in () mini and micro-computers, (@ High performance machines. TUPSCLES.ETE, 200) dentfication of highest priority interrupt can be achieved in a ‘minimum ime by which ofthe following schemes? i) Hardwired pojing. a () Priority encier circuit PORICS Onreceivng an interup from an VO device, the CPU. (@)_ halts fora pedetemined time, (©) branches off tothe inteupt service routine after completion of the curentinstuction branches off othe interrupt service routine immediately. hands over contol of address bus and data bus tothe interrupting device. UPS AEs. Ene, 2) Consider the following: 1. Compilers 2. Design 3, Evaluation 4, Inston setarcitetre ‘Which of thes ar include nthe present definition of computer achiecure to desin fll computer system? @ 1,283. @) 1,3and4 (© 2.3and4. (@ 1,2,3and4, iurscixs, ex, anm Which ofthe following are the problems wit using Millions insrutions per second (MIPS) as a measure for comparing compute performance? 1 Ttdoesnotake into sccounthe capable ofthe insuuctions 21 MIPS ean vary inversely with performance, 3 MIPS varies between programs on the sume computer (@) Land 2only. (&) 2and3 only (© 1and3 only. @ 1,2and3, furse.tes. ere, {in wrtng the miroprogram, there are two situations in which a Padof te mier instution can be kept lank whenit © @ 25, ‘Kaswers: 18. (0) 19. (0,20. (b) 2 (0), 22s (0), 23. (0:24: (0,28. (0), 26. (0,27. (@, 28. (0), 29. (6) 30... 1 contac unit 2 cause tbe we. econo ofa make. se Bandon ‘and 3. {© Land 3 only. @ oc urs. Exe. sexsor consists of 15 registers. The number bs multiplexer and in| the destination decoder ‘A bus organized proc “of seleetionlinesineach arorespctively (@ 2and4. 0) ‘Thetncoect match when n> Dis {0 SIsb Mel ofcomputer (8) SIMD Mel of computer © MISD Mote of compute MIMD Mosel + meontol units and 1 ALU ofeompater (urs. ts. 200 Incase te cals poston dependent. be most sible desig wmweis, dist mode {© elsverode ind 2. (@) 4and4. (A) 4 and 8 4 and 2.) Ae Gpsc-tes. ERE 2mn iif 1 control unit and 1 ALU: {Seno unit an « ALUe neonel units andn ALU @ (@) indirect mode. (@) indexed mode, TUPSCLES. £7,202 3. Which addressing mode helps to access table data in memory efficiently? (Indirect mode (@) Imamediate mode. (©) Auto-decrementor Auto-inerement mode. (@ Index mode. [UPSCLES ETE, 206 Data transfer between the main memory and the CPU register takes place through two registers, namely, usppse 30. ‘and ecu Wescizsers sn A processorhas 32-bit architecture. Each instructions I wordlong, G2bits.Ithas 64 registers. supports 50 instructions, which have 2 registers operands + 1 immediate operand. Assuming that the ‘immediate operands an unsigned integer, whatsits maxima value? (@ 16383 (b) 32767 (©) 65536 (@) 1024 (UPSC.LES ETE, 216, a Consider the following: 1. Operation code. 2. Source operand reference. 3. Resultoperandreference. 4. Nextinstruction reference. ‘Which ofthe above are typical elements of machine instructions? (@) 1,2and3 only. ©) 1,2and4 only. (©) Sand 4only. @ 1,2,3and4. (UPSC.LES ETE 20 33, Considerthe following features: 1. Negative operands cannot be used. ‘When immediate operand chs ois ae anges, the program should be 3. Te rogram sditcultoread |. The size of operand is restricted by word length o é = stricted by word length of the isadvantages of immediate addressing include (©) Vend2” () 2andé ( Dends Gd) Lands [UPSC.LRS ETE, ‘A pulse train can be delayed by @ er layed by a finite number of clock periods (9) aseriain serial-out shift register. 2 (@),32.(€), 33. 0), 340) ee() aserial-in parael-out shit register, (© aparallelin serial-out shift register (@ aporallel-in parallel-out shift register, 35. Which of the following counters ean be used t frequency of a microprocessor by 52 (@ 3bitcounter. (0) Sbiteounter, (©) mod 3 counter, (@ mod counter, TUPSC.Es. exe, 200 36. The following register holds the instruct ion before it goes tothe TATE E.ce, 2010) (0 divide the clock (@) Control register ©) Accumulator. (©) Address register, cuit (@) Datarogister. TWPSC. Les, ere, 203) ‘Which one ofthe following pais is not correctly matched? (8) Horizontal micro-instruction : CISC-instrctions (©) Maltiptier control F 2'scomplement (©) Multiplier control unit Encoding by fonction (@) Vertical micro instruction: RISC-instructions (URSC.LES, ETE, 206) ar. ‘38. Consider the following statements: Intel Pentium-1V processoris designed to give 1, DVD authoring and MPEG 4 video 2, 3.D gaming and digital imagi 43. Superior performance for analog music, ‘Which ofthe statements given above are corect? (Only 1 and 2. (@) Only 2and 3. (©) Only 1 and 3. @ 1,2and3. TURSC.LES. EE, 206) -39,_ Select the signal which is not a pat ofthe modem port on PC? ETectrimees - ‘microprocessor? (@) Camry flag. (©) Overflow flag. (©) Avriliary carry fag. (@) Parity fag. TUPSC.LES, EE, 200) 41, Which of the following capabilites are available in a Universal ShiftRegister? 1. Shiftleft 2. Shiftright 43, Parallelload 4, Serialadd ‘Select the correct answer from the codes given below: (@ 2and4only. () 1,2and3. © 1,2and4. @ 13and4, TUPSC.LES. Ra, 200) 42, Which one of the following can be used to change data from spatial code to temporal code? (@ Shiftregisters © ADeconverters ©) Counters. (@)_ Combinational circuits, (UPS.C. LES. RE, 198) (Consider the following statements regarding registers and latches: 1. Registers are made of edge triggered FFs whereas latches are ‘made from level-triggered FFs. 2. Registers are temporary storage devices whereas latches are not. 3,_‘Alatchemploy crs coupled feedback connection. 4 “Arepster oes binary word whereas latch does m0 Whichofthesbove satemens are cone? @ Lon.) Tand3. (6) 2and3, (@) and. [uPsc.12s. te, 20 200 Computer Fundamentals and Microprocesors | ‘Shift repster with associated waveform is shown in the following figure, Which ofthese is/are correct? cik neo cock ineur x i x || I x i Teaaalgasal () X;alone. (XX and Xy TUPSC.LES. ETE, ¥97 45. The method used to transfer data from VO units to memory by suspending the memory-CPU data transfer for one memory cyele iscalled (@), UO spooling. (QM Line conditioning. (@) X; alone, (©) Xyalone, ) Cycle stealing. 1) Demand paging, the . 1. longercontrol word than vertical microinstruction 2. high degree of parallelism 3. slowerexecution than vertical microinstruction ‘Which ofthese statements ilar corect? @ alone. (b) alone. () Land? (6 2and3. TORS LES. ETE, 2001 47, Which ofthe followings nota characteristic of transparent DMA mode of VO operation? (@ Theexternal logic steals cycles from the CPU. (©) The normal ate of executions stowed down. (© Only one word can be transferred ata time. (@ Datais transfered toffrom memory directly. TURSCLES. EE, 2001 48. Which one ofthe following isnota characteristic of RISC processor design? (@) Oneinstruction pereycle. (©) Registerto-egister operations only. (©) Simple address modes. (©. Register-o-memory operations only. TUPSC.LES. EE, 200) 49._ A particular parallel program computation requires 100 seconds ‘when executed on a single processor. If 40 percent of this, computatonis inherently sequential then what aethe theoretically bestelapsed times for this program running with Zand 4 processor, respectively? (@ 20and 10 seconds. (© 50 and 25 seconds. (b) 30and 15 seconds.SEEDER tugrant Gn Buns nd Conmieaon Engering ‘50. "The advantage of cycle stealing in DMA is that A. Teincreases the maximum VO transfer rate. 2. Tkreduces the interference by the DMA controller in the CPU's ‘memory access. 3. This beneficially employed for VO device with shorter bursts of data transfer, ‘Which ofthe above statements are correct? (® 1nd? only. (©) Land 3only. © 2and3 only. @ Ltmen” ‘51. Consider the following statements: ae: Theadvantage of yl stealing inDMA is that 1. itneeasesthemaimum UO taser 2, sede their y the DMA contlrinhe CPU's ‘memory access 3. itis beneficially employed for VO devices with shorter busts of data transfer, ‘Which ofthe statements given above are corect? (and 2. @) Land3. © 2and3, @ 12and3, TUPSC-LES, esr 2042007) '52, For which of the following devices, is DMA the mos suitable? (@) Keyboard. ©) Mouse © Joystick. (@) Hard disk (UPSC.LES, EE, 206) 53, Inamicrocomputer, why ae waitsates used? (@) Tomake the processor wait during a DMA operation. (@) Tomake the processor wait during an interupt processing. (©) Tomake the processor wait during a power shutdown, (@_Toimterface slow peripherals tothe processor. (UPS.C-LES. Eom, 2007 Sn processor sts. Cae. Select thecomect answer using he codes given below (@ L2and3only.—() 2.3anddonly. © U3andéonly. — @) 1, 2and bony TUPse LES ET 208) 15, What is the purpose of DMA fuiliy in microprocessor based sysem? (@) To increase the speed of data transfer between the uP and WO devices. (©) Toincresethe sped of datatransferbeween the uP andthe memory. (© Toineresse the sped of data transfer between the memory and the VO deve. (© Toimprove the reliability ofthe system, {Urse.te5.e:78, 20 56, In microprocessor bated systems DMA facility is required to increas the speed of dta transfer between he (@ microprocessor andthe VO devices. {b) microprocessor andthe memory {© memory andthe WO devices. {memory andthe reliability system, orscigs. exe, 2nm 57, Theabiliytoalthe CPU temporary and use thisinerval of ime to send information on buses is caled (@ cyclestealing. © secerngn ine cin rectmemory sees. ©, pane © Gees iesc ies ETE, 58, A ‘DMA’ transfer implies (@) direct transfer of data between memory and accumulator. Amawers! 50. (©), 5 (©), 52. (@), 53. (2), $4. (©), 55. (©), 56. (0), 57. (2), SB. (0), $9. (0), 60 (0), 6 (0), 62.00), 39, 60. ou. tronics. 6. (@) direct transfer of data between memory and VO devices out the use of HP. ; (©) transfer of data exclusively within HP registers: fast tansfer fata between uP ana /O devices ata ane et Ops eso UPS TES: EEE, 200 ‘The speed gained by ann’ segment pipeline executing 'm” tasks i inem=D —s @ Steed © Grm-D nem atm o © Gnd uPsc.1ES. ETE, 201) ‘Which ofthe following instrution processing activity ofthe CPU canbepipelined? 1. Instruction encoding 3. Operand storing (@) 1 and? only (© 1and3 only. 2. Operandioading (b) 2and3 only. @ 1,2and3. TUPSC.LES. BIE 2011) Ina microprocessor, the service routine fora certain interrupt starts froma fixed locaton of memory which cannot be externally set, but the interrupt can be delayed or rejected. Such an interrupts (@)_non-maskable and non-vectored. (&)_ maskable and non-veetored (©) no-maskable and vectored. (@)_ maskable and vectored. {GATE R.CE, 200% UPS LES. EE, 2013) ‘The type of device used to interface a parallel data format with extemal equipment’ serial format is (&), UART. (a3) serial-in, parallel-out, CECT (are used for the DMA controler to acquire the data and ‘address bus from the microprocessor. (©) ate used by the 1O device to invoke an error routine if @ problem occurs during DMA transfer. (@ areused by the DMA controller to signal the microprocessor about the end of the current data transfer. TUPSC.LES. ETE, 2013) 1. The method used for resolving data dependency conflict by the compilertsls (@)delayedtoad (©) operand forwarding. (©) prefetch argetinstuction, @ loop butter wrsc.tes.Ere, 2m The correct instruction execution sequence is (@) Execute, Decode and Fetch. (@) Fetch, Execute and Decode. (©) Execute, Fetch and Decode (@) Fetch, Decode and Execute, TUPSc.1es. ETE, These commesionofinemapinesorexabline Priority is known as nie pias (0 aly lng pi © ling ity. (6) parallel priority (serial ine priocity. ¥ WRSCLES Ere, me ‘The aigq Hip is an 8-itserial-input-paalle-output shift restr, Me lock is 1 Mie The i binary number into the chip is Saale ee 63. (8), 64. (@), 65. (€), 66. (2), 67.0) a@ yO Qu. © ays.) 16ys, wesc ies. ene, 20n 668. Which one ofthe following statements is correct? a (©) RAMisanonolalememary whereas ROM ia ola (b) RAMisa volatile mes s RAMIsa ole memory whereas ROMs nen-tol (©) Both RAM and ROM are volatile memories but in ROM. datas not lost when power is switched off, (@ Both RAM and ROM are non-volatile memories but in RAM datas lost when power is switched of WUrse Les. Er square ofa4bit number, What must beth siz ofthe (@) 16 address lines and 16 data lines, ee (©) 4.address ines and 8 data lines (©) 8address lines and 8 data lines. (@)_ 4 address lines and 16 data lines. (U.PS.c.LES. ETE, 2004) 70. Atypical cel fora dynamic RAM canbe implemented by usin ‘how many MOS transistors? . deve (@) Six. 0) Five. le © One, Tr, jursecues. E7200 ‘TL, The minimum number of MOS transistors required to make a dynamic RAM cells @1 2 @3>- m4 (GATE Bee, 198 72, A dynamic RAM consists of (@) Gwansistors. (B). 2transistors and 2 capacitors. (b) asadynamic memory. (©) torealizea sequential logic. (@) realize acombinational logic. lear ECE, 99) 74, Each cell ofastatic Random Access Memory contains (@) 6 MOS transistors. (b) 4 MOS transistors and 2 capacitors. (© 2MOS transistors and 4 capacitors. (@)_1MOS transistor and I capacitor. 175, Inthe DRAM cell in the figure the V, of the NMOSFET is 1 V. For the following three combinations of WL gir ye, and BL voltages (el) [GATE RCE, 1961 WORD LINE (Wt) @ 4Vvavav GATE ECE, 20) 16, Ina DRAM, (@) periodic refreshing is not required ()_ information is stored ina capacitor. (© informations stored in latch. (@ both read and write operations can be performed simultaneously. {ate E.ce, 2017 ‘71. Consider the following statements: 1, MOSFET ROMs have much larger capacities than those ofthe BIT ROMs. 2. BIT ROMSs are faster than the MOSFET ROMS. 3. BJTRAM memories ean be static or dynamic, “Ansvwers: 68. (0), B,(), 70 (©), 7h (@) 7 (0), 73. (8), 74 (8), 75. (), 76. (0), 77. (0), 78. (4), 79. (a, 80, BL. (©) 82 (8), 85.(,0) ec (rOics Computer Findomentals and Microfrecesors ‘Which of the statements given above islare correct? @ Tony.) Land2. (© Zand3, @, te 78. Which one ofthe following has the shortest access time? |, Zand 3. 1,205) (@ NMOS EPROM. (@) NMOS RAM (© CMOS RAM. (@) Bipolar sat RA a0 combinational circuit described 79. AsingleROMisused to design i anee eee at number of tiesinerin te ROM? (@)_ Number of input variables inthe truth able, (b) Number of output variables in the truth table. (©) Number of input plus output variables inthe truth table, (@). Number of ines in the truth table, (UP5.C.1ES. BE 2006) 80. Which one of the following statements is correct? (@) Static | hazard may oceurina2-evel AND-OR gate network, (Static hazard may oceur ina2-level AND-OR gate network, (©) Dynamic hazard may occur in a 2-level OR-AND gate network. (@)_ Essential hazards may oocur in a combinational logic circuit. 81. The difference between PLA and ROM is (@)_ PLA is sequential, ROM is combinational. () PLA is combinational, ROM is sequential. (©). PLAeconomizes on the number of min-terms to implement Boolean functions. (@) PLA has fixed AND array, ROM has fixed OR array. TUPSC LES. ETE, 2011] 82. Consider the following statements for a DRAM: 1. Bitis stored as acharge. 2s made of MOS transistors. ced of DRAM is faster eAGeINy (©) 3 and only. @ 1,2,3and4. (UPSC.LES. 83. Which one ofthe following statements is correct? (@) PROM contains a programmable *AND” array and a fixed ‘OR’ array. (©) PLA contains a fixed ‘AND" array and a programmable ‘OR’ array. (© PROM contains a fixed “AND" array and a programmable ‘OR’ array. (© PLA contains programmable “AND” array and a programmable ‘NOR’ array. (UPS.C. LES. RE, 204; 208; 2010) 84. Choose the correct statement from the following (@_ PROMcontainsa programmable AND array and a fixed OR ray. (©) PLAcontainsa fited AND atray anda programmable OR aay. (© PROM contains fixed AND array anda programmable OR. amy. (@ PLA contains a programmable AND array and a programmable OR array. (ate ce, 193, ‘Which one ofthe following statements is correct? (@) PROM contains a programmable ‘AND" array and a fixed ‘OR’ ary. (©) PLA contains a fixed ‘AND" array and a programmable ‘OR’ aay. (©) PROM contains a fixed ‘AND? array and programmable “OR’ array. Bee ae (@ PLA contains a programmable “AND” atray and a programmable ‘OR’ array. cunscina cee ante =(0) 1500-167 ‘What is the total memory range and memory map, if for a 16 bit (@) 0100-027 (@) FROO-P9FF.GATEECE 2m address bus; Ag = 1, Ag=Oand Ayy-A ae connected to 23-8 (© FOOO-FAFF. of 1024 bytes connected toa 16 bit secaeringtie? Ay indAyactnededtoenetedodet 93, Thee ae four chips east OS mans 1,23 and¢ @ 16k 800K") 2k so00NOFFF H ena (© 16k, 8000 H-BFFFH (4) 2k, 8000 H-8 FFF H respectively azo mapped (0 ruse testo 87, UCSe AyghyAsisused ast chip electing 4K RAM rau ‘in an 8085 system, then its memory range will be a (@) 3000-3 eH cs ©) 700017 FER (©) S000 5 FFE Hand e000 -6 FR H (@) 6000 H- 6 FFF H and 7000 H-7 FFF H AGATE BCE, 1999) = 88 An 8085 microprocessor based system uses a 4K 8 BL RAM = ‘whose starting addres is ADO H, The addess of the last byt in this RAMs (@) OFFF H (6) 1000H (©) BOFF H (#) BAOOH (GATE ECE, 201 hots ‘ate 89. Inthe circuit shownin the figure, Aisa parll-in, prale-out 4 zl Ditregiser, which oadsat the rising edge ofthe clock C. The input lines are connected to 4 bitbus, W. ls output acts a the inpatto 1 16x4ROM whose outputs floating when the enable input Eis (0. partial table ofthe contents ofthe ROM iss follows Adiess | 0] 2[4]6[8 [|u| aa_{o11i] 1111] 0100] 1010] 1011 |1000 0010 | 1000 | SrFFH up (©), 180011-IFFFH, 2800H-2FFFH, 3800H1-3FFFH, 4800H- 1 4 4EFFH eC ICS 2c Ves toaremé, 23 (@) OCOOH-OFFFH, 1COOH-1FFFH, 2COOH-2FFFH, 3COOH- SBFFH 92. If WLis the Word Line and BL the Bit Line, an SRAM cellis \ ‘ The clcko theres is shown andthe dton he W but at | tine s0110.The Gatton the bs at tine is a @) 1111) 1011 = 1000 @) oo10 @ haf nea, 2 0. Sat memory aes anges NOT represented hp Land \ ‘hip#!2inde gue Agios ins fipuewethe ste nes | tnd CS means Chip eet Pere foa) D> A xD > eam somes ajo | Jnaworst 86:6), 87. ($8. (0,88), 0. (0, 9. (@, 92.0) :Computer Fundamenals and Microprocesors i we x Yoo “a 96. A ROMs used to store the table fr mukiplication of to &-it 4 t ‘unsigned integers. The sie ofthe ROM requiredis” | ona PO ee (@) 256% «8 (© 4kx16 @) 64x! " 4 seer @) otewd ©) AXIE (SHAS J 97. A semiconductor RAM has 12 it addres register and an 8 bi ae eam afinise ene ® (@) 256bits (b) 4,096bits si (©) 32,768 bits @ 10,48,576 bits we s ionowiss bz, 200 a ae a 98, A32kB RAM is formed by 16 numbers of a particular type of Shai ee oe ase hate east? (a) 32kbits (b) 1GKbits (c) Skbits (a) 4Kbits @ IGATER.CE, 2016) [UPS.C. LES. ETE 2017) 90, The mamber of NAND gt ei fr 90 diensina qRheuingt sexe OM angler (a) 16 (b) 48 © 4 (a) 104 93. A2x2ROM anys wi Se ae . A2x array is built with the help of diodes as shown inthe 100, The principle of locality of reference justifies the use of Gatto Vga arsenictwterie ed“ Dg BMA nes and Band, ar signals tat ae ouput of he ease amps ©) ile coche mmo eontomedaniaconeyoniapotethlimsaningte ©) Wrmimemey OO. PASTE ara s0 fea 101. Ifa RAM has 34 bits in its MAR and 16 bits in its MDR, then its % & capacity will be cm eos w ion © SMB tome a8 Ts ns ~ 102. The use of cache in a computer system increases the { aublemenon ss rte apn . © gull mons gt e nic ar: mory abcess, a0 C { Se i aelanebbes CTTT y Ey 2. Cache memory is fast but costly memory. = 5 Peormance face ding progam excewonis measured Bo By 4, Cache size is very large. Wf oe Dos ‘nid besten gensboremecome? wee (tant, @ 2a) © Sands) mds BITS STORED IN THE ROM ARRAY WASTER 104, Wie ack epacomentlsthmis pen edn cache Ding eatopenton tesceoetvrdinegorhighanite “Spare Desiioe es ee ae eet ea ora than svn cet dap sve ato bs - Oe sponding to Dj, (where i= 0 or 1 and j= 0 or 1) stored in the 395, In which untis the performance of cache memory measured ? nM 2 (@) He, (b)_Bits/s te Pile fel (9 aecnsen. (‘Hm ofJofjekidehd Sescusena.sen aate nce, 2m 106. ‘The access ime of a word ina4 MB main memory is 100s. The ‘acess time of a word ina 32 KB data cache memory is 10ns. The ‘94, Fora particular type of memory, the access time and the cycle time a ‘ae respectively 200 ns and 200 ns. The maximum rate at which average data cache hit ratio is 0.95. The effective memory access the data can be accessed, is me (@) 25% 10% ) 5x 10% @ 95ns (b) MSns (©) 2ns @ 95ns © 02x10% @ 10% TUPSC.LES EE, 1991 [UPS.C. LES. ETE, 1999] 107. Given a 32-bit processor with 16MB main memory, 32 kB 4-way 98. Four memory chips of 16 x 4 size have their address buses set-associative on-chip cache and a block size (or line size) of 16 cotmecnd ie Tassel booze ‘words. Whats the total numberof tag bitin the memory address © xa @) 16x16 (@ 32%8 (@) 256x1 format? s [UPSC.15. BT, 201; 20151 @ 9 On Ouse Om os [UPSCLES. ETE, 2008 Answers: (a), 94. ( = rr EMErS: 93. (0), 94. (), 95.) 96 (), 97.) 98 (), 99. (10D (0, 10.) 12), 103 (0, 104.) 105 (6, 106), 107 ()108. Given that main memory acces times 1,200ns and Cache access time is 100 ns; the average memory acces time isnot to exceed 120ns. The hit to for the Cache must beat east ©) 90%.) 98. ©) BOG. (@) 75%. twrseies Ere m0 109. “The access time ofa cache memory is 100 ns and that of main ‘memory is 1s. 808 ofthe memory request are for read snd cers are for write. Hirai for ead only accesses is 09. A write {through procedureis used. The average acces time ofthe sytem. forboth read and write requests is (© 2000s. () 3600s.) 72008. (@) 1100.08. TURSCLES. BIE. 21 110. A computer system has a4 K word cache organized in block-et associative manner wih blocks per set, 64 words per lock. The ‘numbers ofits in the SET and WORD field ofthe maia memory adres formula are respectively (@ 1Sand4 () Gand4 (©) Tand2 (6) 4and6 (ors 1S ERE, 2 IL. A computer system has aCache with acces time 10ns, ahitrtio ‘of 80% and average memory access tine s 201s. Then whats the access ime for physical memory? (@ 50ns @) 40ns (30m (d) 2006 urseues 88,200 112, A cache line has 128 bytes The main memory has latency 643s and bandwidth 1 GB/s. The ime required to fetch the entirecache Tineis (@ 3a (©) 64s © 96ns @) I92ns WUPSC LES ETE, 207) E k address bus of Jntel 8085 is 16 bts and hBhee the memory ig qt 1114, Ifthe memory chp size is 256> 1 bis then the numberof chips ‘required to make up 1k (1024) bytes of memory is @2 4 © OSs (UPSC. LES RTE, 195) 15, A microprocessor has 24 addres ines and 32 data lines. Ifituses 10bits of opcode, the size ofits Memory Bufer Registris (@) Whis () Wbits © 32bis (GH 1bdits (UPS. LES. ET, 202) 116. A three-bit shift register is shown in the given figure al sal a sr rs a ‘To have he coment "00" aa, he numberof lock pulses ied would be o 3 6 @s @) 16 urs us 22,19 sider tht evel of he memory biearchy has a it rat of 117 Come to ae 0 come tha inte fovel, and memory requests hat mie inte vl 100 ns 0 ete. The average access time of the levels complete Tee sfoDas © Ome) 28m 4 {UPSC.LES. ETE, 2018) OG ALL AID. (@), 1B ©, HA), 115.00), 116 AT 0s. (109. (0), 110 (2) 111) 6. (0,107. 126. Answers 55, (b), 124. @) 125-00 An Integrated Course in lectroni and Communication Engineering ro processor aes Ds Con Of 118 Te ied enn oS ode Ea spas 29s so ess He (S13), EOD es tye ene ns @ET# BED we 0 0108 asinine see vires 01000108) Et aa 00000101 CHO 108 £2) sia tes at lcations 0000 0108 CH) t0 0000 O10F Gy G eotitc pag terseras oy ening core defines employ? 1, iene of ny ea Mr rein ig feted may terete eon ©) Care orl residing mem. (3 Nowe otte sve caeeeteee a corny thie ne fe 1 KB, 2 KB a 4 KB. The an Te me What arte tsb so ts hp ease tom ana aie espe (3 Soe tebtsand anon spetvey ©) Sete tos and obi respect (Sb: tei and 128 be expe Worsetrs exam 21, WikehoCoefliovng ete memory pina: tat? a Ae tne a ne. 2 Blocks andlock esti, SG tie nd anh Souerheconet ee oh codes ven blow: ton. Tandon (Danton @ tenes pon CAG}: a08 fosiies ‘ ony sk when addressed from a sixteen bit bus with twasMISBs used to enable the decoder? @ 2K) 4K @ 16K @ 6K TUPS.CLES. EE 300 123, An VO processor controls the flow of information between (@) cache memory and UO deviee. (@)_-mainmemory and VO device. (© wolO devices, (@) cacheand main memory, Turse. ues. er8, 10 Among memory types, the abbreviation MPDRAM stands for (4) Malo Dynanie Random Acces Moony {®) Malipoin:Dynamic Random Acco Money, {© Malipoin Disk Random Acces Menser (© Muliport Dimensional Random Access Memory. 125. A memory sys ha ace mer System has a total of § memory chips each with {Daderesstines and daaines The sie of he mses =) ©) 6k byes, © akoyes 124, ©) 32k bytes 4k bytes, a Uns. Ertan care 126 ie Semiconductor random access memory of «compe wor, ach of bis, Itean perfor rootaste eit ny bitsare therein the Address Reise 8 OR @ @ turse, 16) 24 3 [urs ues. em, 2H127. 128, 19. 130. asl. 132, 134, 13s, ‘Answers: 127, 14 ‘The speed mismatch betweer is alleviated by using a buffer between memory and Known as (@)_ volatile ROM, (©) cachememory, (©) non-volatile ROM, (@) EPROM, Uses ‘The semiconductor RAM of aligital com, hoe of 1itsand a capacity o 63S wenden 80ns. Ifthe CPU is much faster than the my er ime ot @) 40.96 ps o gens © stm @) 048 ms ‘Which of the following statements are correct? see 1, DRAM offer reduced powercamserrsy, 2 Anassosiatve mem icheape ten 3. Thefastst and mos fee cachcmnpason siderable mimony. 4 The adress gencrated bya segmented program i el physical address. = — a reanization uses content (@ Vand 3. (6) Land. (©) 2and3. (@) 2and4, Ursus ere, 218) ‘Techniques that automatically move program and data blocks into the physical main memory when they are required for execution secalled (2) main memory techniques, (©) virtual memory techniques, (©) cache memory techniques ogjate mappingtechniques. (UP.c. Es. ARE, 215) 2. Power consumption per bit of static RAM is less than that of dynamic RAM. 3. Dynamic RAM is less expensive than the static RAM. Which of the following statements are correct? (@) 1,2and3. (b) Land 2only. (©) 2and3 only (@) Land 3 only. TUPSC ues. ee, 2016) ‘A.computer employs RAM chips of 256 bytes and ROM chips of 1024 bytes. If the computer system needs 1 kB of RAM and 1kB of ROM, then how many address lines are required to access the memory? @ 10 wn OR w 1B TUPSC.UES. ETE, 2016) ‘The software that transfers the object program from secondary ‘memory to the main memory is called (@) assembler. (b) loader. (© linker. (@) task builder UPS, LS TI, 199) ‘A Read/Write memory chip has a capacity of 64k bytes. Assuming Separate data and address Jines and availabilty of chip enable signal, what is the minimum number of pins required inthe IC chip? @) 28 ©) 26 © m4 (@) 221uPsc.ues, ere, 2002 ‘A memory system of size 16 kbytes is required to be designed ‘sing memory chips which have 12 address lines and 4 data lines (0,443. (0), 144, (0), 145. (2), 146. (d) 136, 137, 138, 139, 140, TrONICS ai, 142, 13, at, 14s, M6, (©), 128. (a), 129, (2), 130. (0), 131. (4), 132. (b), 133. (b), 134. (0), 138. (€), 136. (©), 137. (6), 138. (a), 139. Computer Fundamentals and Microprocessors ees cach. What isthe number of such chips required to design the ‘memory system? O24 @8 @ 16 [UPSC-LES. ETE, 207; GATE RCE, 196) A memory system of size 32 kbytes is required to be designed Using memory chips which have 12 addres lines and 4 data lines ‘cach. What is the number of such chips required to design the ‘memory system’? OF M8 O68 WR (ursc. Es. ee, 208) ‘Whatdoes the minimizing ofthe memory requirement ofa program mean? @)_ Maximizing numberof macro eels. (©) Minimizing eumber of macro cells. (©) Minimizing depth of recursion, (@)_ Both @) and (above. furse.tes. ene, 2007 ‘A Program nt that permits repeated operation of aparicular sequence of inst (@). subroutine. (©) mode. ‘Which one of the following is correct? Amicorogam @)_ is usually writen in high level language. (©) isaprogram for microcomputers. (©) isaprogram written in assembly language. (@)_isasequencing program forthe contol unitof any processor. TUPSC LES EE Which one ofthe following is correct? E by anes ofan (©) any programa verysmallsize. curse. tes. ea00n ‘The microprograms provided by a manufacture tobe used on his rmicroprogrammed computer ate generaly called (software. (©) nerware. (©) firmware. (@) hardware. [UPSC- LES. EE 201; 2014 Inan assembler, which one ofthe following i required for variable names in symbol table? (@) Addresses. (©) Values. (©) Registers. (@ Storage TUPSc. ts Ere, 200) ‘The computer program which converts statements writen in high level language to object code is known as (@) assembler. (©) compiler. (© disassember. (operating system, TUESC LES. EE, 2003) Division by zero in a program gives rise to which one of the following? (@)_ Syntax error (©) Run-time error. (©) Logical eror. (@) Semantic error. TUPSC.LES. eE,20m, ‘Wrapping of data functions togetherin a clase is known as. (@)_ overloading. (b)_dataabstraction. (©) polymorphism, (@) encapsulation. TUPSC Les. E2010 Which of the following has a major role in implementation of function calls nC? 1H Os(@)_Processor's rey 5s epsers, ().Datasegment © Theheap. (@)_ System stack. TUPSCUES, R20) 147. The datatype defined by users (9) bwiltindaintype. (Q)_abwraetdatatype. {© homogencousdatatype(@) tel datatype furse 148. The creation of the variable will automatically ereate a spe ‘aiableassocated whit eal as @) buffer variable. (b) text variable. (© allocated vaabls,—(@) ating variable Tens MES. 2041 Locality of reference concept wil fl in which ofthe Following ety ‘Where there are (@)_ many conditional jamps. (6) many unconditionally jumps. (©)_ many operands. (@) None ofthe above. 1180, If he mantissa inthe floating point representation ofa number is 237 bitslong, then what isthe accuracy of the digital computer? (@) 37 decimal places. () 23:ecimal places. (@)_Wedecimal places. [WPS LES RE 208) 151. A certain wel-known computer family represents the exponents ‘ofits floating-point numbers as “Excess-64" integers. Which one of the following numbers is represented by the exponent eetstetseatieo? “ ~o14 2 ‘ @e 0) = -644 $2, lectronits.A cadéfiy 152, Consier the following statements in respect ofthe expression A+XYZ(& A 1. Result ofexpression may depend upon order of evaluation of ‘operands of the operator “+” 2. Result of expression would never depend upon order of evaluation of operands ofthe operator “+” 3. XYZisnota valid name of function ‘Which of thestatements given above is/are coreet? @ Lonly. () 2only. (© tand3. () 1,2and3. {UPS.C.ues. ex, 200 4153, Itis awkward to employ signed-magnitude system in computer atithmetc, because 1, signand magnitude have tobe handled separately. 2. ithas two representation for 0. Which ofthe above statements sare conect? (@) Joniy. (©) 2only, (© Both Y and 2, (@) Neither 1 nor2, TUN. Les. a, 154, Which are the characteristics of verical merinsrutions? 1. Considerable encoding of control information 2. Limited ability t express parallel micro operation 3. Long format Select the correct answer using the codes given below: (@ Land 2only. (6) 2and3 only (© Vand 3 only. () 1,2and TAT. (), 148. 3), 180. (0), 151 (0,152. (a), 162. (c), 163.6) —_—— TWPSC-LES. Bee, ae) 153.0), 154.) 155, @@), A Inert our in Etnies nd ammunition Bagibeing jon nA = 20a =-7iNPASCAL erat sequal to oe 2 OU ws PSC. es example ofa valid array declaration in PASCAL ig 156 Ane ABC: ARRAY 5] OF REAL @) VaR C ARRAY IN. M; o10} OF REAL {VAR P; ARRAY [8] OF INTEGER (G) VAR x: ARRAY (2.8) OF INTEGER PSC hyp A PASCAL functions defined a cal (Var At: Bang begin Y:230: 50° A+(B-Al, {this funetion was called 10; the value of R would be os 0929 OB wx (UPSC.185.222, 9 158. Which of the following conditional IF statements of Pascale correct? 1, IP condition 1 THEN statement 1 ELSE IF condition 2 THEN statement ELSE statement 3 IL, IF condition 1 THEN IF condition 2 siatement ELSE statement? Select ihe coect answer using the codes given below: (@ Tana. (©) Mand. © Yanamt (@ Landi (ursc.nes ex. 159, The different clases of formal parameters used in PASCAL (@)_ value and variable parameters. (©) procedure and funetion parameters. (©) value, variable, procedure and function parametes- (@) variable, procedure and function parameters. TUPSC.LES. ETE 160, The C expression ++i equivalent to writing © F5142 0) izi+1 © izisi @ inititi qursc.1Es ETE AGI. InC language f—=9 is equivalent to @ I-92 & f2f-9 © 29-1 @ Fg . qursc.ues. 8 Which one of the following correctly defines a C-mie® # computing the square? B pielies sara) xx. (6) eaafne gr (0 lefines sar (x) (x) * (x)) (@) # defines cs ies Sar (x) (x) * x) turseues. 163. Which ofthe foto i integers in @) int *B (29) ©) int *P wing comecty declares a pointer 156. 4), 187, @), 158. @),© imeP) (20) © im*@p20p TUPSC.LEs. er, 20 here each one will take expressions in avoids 164, Given three integer variables a,b, ¢ wh positive value. Which one of te following overflow? @ atb-c 0) bra~c ©) beta (W) chasboene TUrsc.nes, mr, 2009 Pa gat oft same ype ing peo socal 165. 1tis given that two pointer variables and p > B results in @ 11100000 (6) 00000111 [UPSC.LES ETE, 2014) ‘Ansmers: 164. (c) 165 (0), 166. (a), 167. (0), 168. (0), 169. (2), 170. (0), 171 (@) 172. (e), 173. (a), 174. (0), 17S. (0), 176. (8), 177-(@) 178.0) ¥79. (€), 180. (b), 181. (a) 1 How isthe subroutine invoked? 2. How are parameters passed? 3. How are values returned? 44. How many parameters are passed? Selectthe correct answer using the codes given below: (@) Land 3 only. (@) 2and 4 only. (©) 1,2and3 only. @ 1,2,3and4, TUPSCLES Ee, 206) 179,, Witnreference oC programming language, which ofthe following, statements are corect? 1. Anidentifiermay start with an underscore. 2. Anidentfer may end with an underscore. 3, IFisavaididentfier 44 The number of significant characters in an identifier is implementation dependent. Select the corect answer from the codes given below: (@ Land? only () Zand 3 only. © 1,2,3and4, (@ Band 4 only. TUPSC LES. ETE, 2009 180, Which one of the following operators of high evel language is, sedto eliminate the run-time cost of redundant adress calculations? (@)_ Arithmetic. () Assignment (© Logical. (@. Relational. (UPSC-UES. ET 20) 181. Which ofthe following ivare NOT the functions of assembly- language directions? 5 1. Define system parameters.i : 2. Assign specific symbol ie symbolic memory location, 3. Control the outpat of the assembly process. (®) Land 2 only. (&) 2and3 only. © and 3 only, (@) 1,2and3, TUPsc urs exe, 182, ‘teen conten of progmnming age retento mie (a) memory feation. (©) identifier () value (@)_ Noneot these. TUS LS Es 208) 183. If the value of x in decimal number is 3,954, the value of yin ‘decimal number compated bythe given flow chartis 2 © a @ 3954 (ups. Les. e200) 184, What will be values ofA and B respectively, when printed forthe Electronics @ 20 o (@) 10and 20. (6) Sands. © 2and 10. (@) Wands. TUPSC uns, Br, 200) 4185, Consider the following C structure and declaration: 1, Structdste { 2. intday: 3. intron 4. intyears sh Struct date * pd; Which ofthe following s the comet method to referto the year ‘member? (@) (pa) “year () (pa) * year. (@) pam year. © (*pd) > year. [UPSC.LES. ET, 2000) 182. (a), 183. A, 18S (2, 186. (0, 187 (), 188.) 189. (6), 190. (4) lowing decaration of C: , J above detain ICP winger toe cant Whe oo unton uring spate anaay ore 0 Petey of pone On ein ner NEE 186, Consider the fol int) Qh (UPSCUES. ETE, 200) consider the following Pascal program fragment: wari j:imeget, procedure ¥(p. integer): begin pepe 187. i ¥ Guihs 1 both parameters to Y are passed by reference, what ae the values off and at the end of the program fragment? ©) 3 @ i=3,j=2 (Ursc1es ere, 200) 188. Consider the following C program: finelude < stdio > ‘main () catem ! © 2 @) 3 (UPSC.LES. ETE, 205) 189. Consider the following information ‘Anatray A [Lis sid tbe pondered if Ali-pl s Ali] s [i+ pl Foreach such that p <1 m-p. Forexample, the ary 14263 75 is2-ordered. Ina 2-ordered anay of 2N elements, whats te ‘maximum number of positions that an element canbe fom i position ifthe array were ordered? @! 2 @M @N rss. EE 190, x=tiy:=0; wile yk do tesin =x; yeyel nt Forthabove Pascal program fagmentinvolving iegesx)804 Ambion ofthe allowing ia Top ivan ete a Seams ofeachexecutonet elogpand athe compen @ © OF De +1. @ ros. Cee ETE. 2004)191. Consider the following °C’ program: rain() igs i ri(s riC) pi) ) pri() { staticintk; printed" 44%); ) ‘Which one ofthe following is correct. ich oe of he folowing in respect of the program (@ Weprints 012. (© prints 111 (@_ Teprints3 consceutive but unpredictable numbers. TURSC.LES PH, 208 (©) Meprints 123. 192, Consider the following C statements: 1 xslt 2. seine max = 40; 3. xekix=t 4. For (i= O:i<= hi +4) (primtcivedny ) Which of the C statements given above are not correct? (@ Land only. (b) 1,2and3 only. (©) 2and3 only. (@) and 4 only. TURSCLES. En, 200 193. Whatis the output ofthe following program? ore @ 33 30 @3 @ 03 (WPS Les. BE. 2008 194, Consider the assembler directives ORG 8000 T:DW OFAOFH Which one ofthe following is coreet? (@). The contents ofthe locations 8000 and 8001 get erased, () The contents of the locations 8000 and 8001 remain ‘unchanged. (©. Theleast significant byte OF will be stored at location 8000 and the most significant byte FA will be stored at location 8001 (@) ‘The leas significant byte OF willbe stored at location 890! and the most significant byte FA will be stored at location 8000. TUPSC.LES. EE 2009) 195. Analgordum s made up of2 modes M, nd My I order of Mi sf) and that of Ms), then the order ofthe slg @) fm) x s(n) ©) s@) aA a © min (fin). 8) @)_ max «n 0) ee, 196. Which of the following data structure is used by a compiler 10 manage information about variables and ther atibutes? G@) Abstract syntax tree, (0) Linked list (©) Parable. Symbol table 0) Pamebie. @, {UPS.C.LES. B-T-E 2010) SRO LS ETD PO DE HOGG. We, 20 60,201 Om OREO AME) 208. (a) 197. 198, 199, 200. 201. “Tectronics. 203. 204. 208, Computer “Which of the following operations are performedon linear queaes? 1, Testing linear queue for underflow. 2. Baqueve operation. 3. Dequeue operation. 4, Testing aTinear queue fr overflow. Select the correct answer using the codes given below (@) 1,2and3, (b) 2,3and4. Ndanid naan ide # UPSC.LES. ETE. 2001) ‘Which ofthe following is nota linear data steture? (a) Array. (6). Linked list (©) Stack, (@) Tree. 'A data structure in which insertions and deletions are possible at eitherend, isealleda (@) queue. (b) deque (UPSC.1ES. ETE, 2002) (@) enque. TUPSC.LES, EME, 2001 {In a 500 % 500 matrix, 95% ofthe elements are zeros and these clements are randomly distributed. Which is an appropriate data structure tostore ths efficiently? (©) stack. (@) Anarray. () Atwee. © Allis. @ Astack. TUPSCIES. ETE, 208) ‘Which one of the following is the most suitable definition of ARRAY ? {@)_ltisacollection of items which share a common name. (0) Itisacollection of items which share a common name and ‘occupy consecutive memory locations. (©) this collection of items ofthe same type and storage class ‘which share common name and occupy consecutive memory Tocations. is @ 1 (4) Cannot be determined from the given data. [WESC LES. EE,2000) Which one ofthe following is not correct about recursion? (@)_ Depth of stack is proportional to the depth of recursion. ()_ Some of the recursive function can not be writen as non- (©) For some of functions, writing reeursive version is easier than non-recursive vet (@)_ Recursive functions have terminating condition which limits the depth of recursion. [UPS.C.LES. ETE, 2006) Consider the following statements: 1. Internal sorting is used ifthe numberof items to be sorted is very large. 2. External sorting is used ifthe number of items to be sorted very large. 3, Extemal sorting needs auxiliary storage. 4, Invernal sorting needs auxiliary storage. ‘White above stementsare come? (@) Land 2. () 2and3. (©) Sand, Sorting i useful for 1. report generation. 2, making searching easier and efficient. 3. responding to queries easily. 4, minimizing the storage needed.1 \ (@) 1, 2and 3 only () 1.3anasony. (© 2,3and 4 only. on (@ 1,2,3.and only. iurse ues er, 200 206. Given below are some applications. Choosing from the options, pick hone hatalloctesa suitable dts strc ripening sep : 1. Representation ofa sparse mati. 2. Fast access to any item from ast of dat, 3: Conver ini expressions to postin expression, Storing the tems of along polynomial with arbitrary number ofterms. () Links ay listed list, and stack (©). Stack, array and stack listed list. (©) Amray array, tree and stack, (Linked tst, array and stack Hist eS. ETE, 2011) 207. Which one of the following algorithms design techniques is used inguick sor algorithm’? (@) Dynamic programming. () Backtacking. (© Divideandconquer. (@) Greedy. TURSCLES. EE 2009) 208. Which ofthe following algorithm design techniques is used in the {uicksortalgorithm? (@)_ Dynamic programm (©) Divide and conquer. () Backtracking (@) Greedy method. (UPS. LES ETE, 2014) 209. There are four diferent algorithms Aj, A. Ay and A, to solve a given problem withthe complexity order log (n), log (log (2), ‘log (n) and nog (n respectively. Which isthe best algorithm? OA OA OA @ Ay rors. ung ere, 00) ONIC. TUPSCLkS. Ene, 2 211. Ina circularly single linked list organisation insertion of atecord involves the modification of (@) nopoimer. ©) pointer. (©) 2poimers. (@) 3 pointers. TOPS. ues. en, 201) 212, The expression for the infix equivalent ofthe prefix form of 4+-*T ABCDIEFF + GH will be @) APC D+ ERIG+H © AP*C-D+BFG+H © A®*C-D+ERIG+H) (@) AP *C-D+ EUEIG +H) 213. The prefix form the expression X + Y—Zis WPS. Le. 2, 909 (@) -+XYZ () +-X¥Z. © xYZ-+ (@) xYZ+- TOPS. US. Era, 200) 214, Consider the following statements: 1 Infix, Prefix and Postfix notations fr expressing the sumof A, and B are A +B, +AB and AB + respectively. 2. AVL tre isa binary wee in which the difference in heights ‘between the left and the sight subtrees not more than one for every node. 3, Stack data structure is used to save and retrieve information in reverse order, 4. Queue dita structure is known as LIFO. 6 Integrated Conse in Electrons and Communication Engincerine 215, 216. 217. 218. 220, 2. 222, How many di msgivenabove ae corect? aes (b) 2,3 and 4. @ U2anas, TUPSC.LES 4,299 Which ofthe: (@ 1,2and3. ( Land. convertinfixnotationto prefix notations “Theda structure needed 10 (@). eraph. (a) quene, (0) stack Oe Os EE any ity Floyd's shortest path algorithm is “The complexity Floyd's shortest pal ge a ©) OWN) (O(N) (0): U9 00 - 60 OO CE Ifthe given binary tee is traversed in post-order then the order of nodes visited as @ JGEDBKHIFCA () DBJGEAKHFIC (©) DIGEBKHIFCA (@ ABDEGICFHKI [UPSC.LES. EE, Yom A single edge is added toa ree without inereasing the number of nodes. The number of eycles in the graph is equal 0 (@ zero. (b) one. (@) two. (4) indeterminate. TWPSC.LES. EE, 39m ery” urse-u Exe, 200 ‘Whatisthe depth of complete binary tree with nodes? () logg(n+ 1) 1. (©) login = 1) +1. ©) logy(n) +1 @ logy(n)-1. (UrSe uss. ex, 08 Conse the folowing statements on binary tee: 1. Are with nodes has (nl) edges, 2. Alabelled and rooted binary tree can be uniquely constructed a, Himpstoeran poder eae ei (Ganee ae re, Of nodes in a binary tree of height ‘4A complete binary tee with m internal nodes has (n+ 1) leaves, Which of the statements given above are correct? ® 2am () 1,2and3 only. 3 (@) Zand 4 only, i (UPS@1es. ee, 20 inct binary trees can be constructed with three nodes? PL OR yal ggg ne (UPse.Les, Exe 200) inTig ” TM8eafnodes. The number of nods of dese? @ logan) nay On @ (Urs. tes, 622,201 5 206. (0, 2076), 208 6) 208,240), 2480), 212. (0,213.0), 214 BIB 221. (c) 222. (6), 223. 0) rv 246. (€), 247.) 218, (), 219: (8), 220.00Wha maximum smb of den levels, if the root level is zero? eps aay ie a as @ 2 B16 Wa |@ won ‘oamageatinar sch seinasendingenien eee (Gq) postorertaversl only.) none ean (© pre-order traversal only. sa (G) Uotcre treated pene aca : Wore ns ents Inabinry tthe number ofinemal asd sof dpe isan the numberof intemal nodes of degree 2x6. The sume: of ‘nodes in the binary tree is S Tenant tle @7 © 8 9 @ 10 cori eterna ‘iemuberofedtsa tropa gaphotdegee Danvers irewalte @ ND 21. @) ND2 © N+D @ NP WWPSC.LeS. Exe, 2010) tna completely connected graph having “n’ vertices, the total numberof edges is equal to 28. nea=1) ©) 2m © wt © [UPSCLEs. ETE, 197) ‘An array multiplier is used to find the product of a3 bt number ‘vith a4 bit number. How many 4 bits address are required to perform nitiplication? @ 1 © 2 wn 29. ©3 @ 4 TUPSC.LES ETE, 2013) “Wrapping of data and functions together ina class is known as joading. (@) dataabstraction. 230, 237. -ETCCLCORIGS.. (©) Quick sort. (@) Selection sont WUPSC LES. ET, 208) (@) Bubble ort (©) Inserionsor. 282, Theaveragesuocesfl search time for sequential search items @ on @ 2 © 1) @ logaet (Urse. Les ema ‘Avweighted complete graph with n vertices has weights 2 and edges (V, Vp. The weight ofa minimum spanning tree is oF a © 2-2 @ nl WSC. LES. EE, 20171 Blocks searchis used to locatea recordin an ordered file consisting ‘of N records. The optimum size ofthe block is @ WN © W ON @ NB [urs ues. en, 1971 » $ 234, 235. ‘The numberof distinct permutations of 1,2,3, obtainable by ‘stacks equal to the numberof distinct binary tees Wit (@®) mnodes. (b) 2nnodes. (©) Ins I nodes (@) Anodes. TUPSC.LES. EE 98) 236, Thee processors with their respective process IDs given by Py. and P, having estimated completion time of 8 ms, 4 ms and 2 ms, respectively, enter a ready queue together inthe order Py, Pa and P,, What isthe average turn time in the Round Robin ‘Scheduling Algorithm with time 2 ms? Answers:, 224, (b), 225. (b), 226, (a), 227 (0), 228. (d), 229. (230. (2), 231. (8), 232, (a), 233. (€), 234. (8), 238. (8), 236. (0) 237-6 238.8 239. (#), 240. (€), 241, (4), 242, (€), 243. (0) 240, 241. 242, Computer Fundamentals and Micoprcesors {S587 (@ 10ms. (b) 1Sms ©) 20ms, @ .25ms TUPSC. MES. TH 2008) ‘Consider the following set of processes: Pros] P| Ps | Ps | Pe | Ps Bursttime [10ms | 29ms | 3ms | Tms | 12ms First Come First Serve (FCPS), non-preemptive Shortest Job First (SIF) and Round Robin (RR) (quantum = 10ms), Scheduling ‘Algorithms for this process st would imply which ofthe following features? 1. The SIF policy result in less than half ofthe average waiting, time obtained with FCFS scheduling. 2, The RR algorithm gives an intermediate value for the average wating 3. Deterministic modelling takes a particular predetermined ‘workload, ad designs the performance ofeach algorithm for that workload. Select the correct answer using the code given below: (@) 1,2and3. (b) Land? only. (©) Vand 3 only. (@ 2and3 only. (UPSE ESE, 218) ‘Consider the following processes which arrived in the order Py, P, and Py. Process [Burst time A 24 ms Pa 3ms ams acarde Ray. (@) sequential logic circuit that counts number of pul (sequential logic circuit that adds two numbers. (6) combinational logic circuit that adds two numbers. (@) combinational circuit that multiplies two numbers. TURSC. LES. ET, 2006) ‘Which one of the following is loaded inthe main memory by the bootstrap loader? (system data. (©) user program, (©) BIOS. (@ partof DOs. TUPSC-LES. ET, 200) ‘Which ofthe following are required fora multimedia PC? 1. CD-ROM drive, speaker and sound card. 2, Modem and network card 3, Hardware needed to display videos and animation. 4, Software needed to display videos and animation. Select the correct answer using the codes given below: (@ 1,2and3. () 1,2,3and4, (© U2and (@ 13nd. ‘ TUPSC.18S. EX, 200 ‘Why docs an increas of the RAM of a computer typically improve performance ? {@) Virtual memory increase. (b) Larger RAMS are faster. (©) Fewerpage faults oceur. (@) Fewer segmentation faults occu. “Anexample ofa spooled devices (@) agraphical display deviee. Bee: (©) line printer used to print the output ofa numberof jobs. lursc.1es. er, 20mSE (©) a secondary stora, se device in a virtual memory system. (@) sterinalasedtocaeriputdsintonreeey ee Sta peria maple programa em anulanenaty a ingle poets eee (9) ulti) mutcig © mls © mllqoceng openting ucminsconne 1 Neonlre acne 2. rap endl, ‘Whichoftesbove tenons an cone © L2amdsenge gy Teden deny © Sunder asuna Consider the following statements regarding database normal forms: 1. Any relation with two attributes if BCNF? 2. Lossless, dependency preserving decomposition into BCNF is always possible 3. Lossless, dependency. preserving decomposition into 3NFis always possible, 4. BCNFis stricter than 3NF, Which ofthe above statements ar corect? (@) 1,2and3. () 1,3and4. © Uden, @ 23anda, (wrse. uns. er, 2017) nsider the following schedules for transactiongT,, T, end Ty BI ‘The conect schedule of serialization willbe @ 197,97 ©) 197,97, © Toho @ Tmt 1UPSc.tes. e722 248, A disedriveas rotational speed of 3,600 rpm, an average seek time of 10 ms, 64 sectors per track and 512 bytes of data per sector. What is the average time to access the entre data of a 16 Kbytes file stored sequentially onthe disk? (@) 18.85 ms ©) 10ms © 27.15 ms (@) 9ms wrscreserse, 2s .249,_ A disc drive hasan average seek time of 10 ms, 32 sectors on each track and 512 bytes per sector Ihe average time to read 8 kbytes Read (Y) Read (Y) write Waite 0) Waite Read (X) Write 00 Ar Integrated Coure in letoncs and Communication Engineering 250. 251. 252. 253. 254, Acattenas 256, 251. 258, oh oo (@ 3,600%pm. 400 Sons On disk is 30 ms. It rotates at the rate of ime of a sake 1d Each tack has a capacity of 300 words, 0 rotations pe secon Tewcestine seams (@) ms (@ 47ms (b) SOms_ ©) TUPSCLES. Ee, Se ais tn 24 cing ss em Si cee 3 (@) 68.80 x 10% bytes/s. — (b) coe Om [UPSC.LES. Ee, 207 it page table is held in registers. IF Inthe demand paging memory. a page table i jttakes 1,000 ms to service a page fault nd ifthe memory access time is 10 ms, whats the effective access ime fora page feultrate of 0017 (@) 199ms (&) 109ns (©) 9.99ms (d) 0.99 ms TUPSC.LES. E22, 29 ‘A magnetic drum of 8 inch diameter has 100 tracks and storage density of 200 btsfinch, What sits storage capacity? (@ 8.402 bits (&) 202,400 bits. (©) 502,400 bits (@ 1,004,800 bits. TWPSC.LES. ET, 209) A virtual memory system has an address space of 8k words, 2 ‘memory space of 4k words and page and block sizes of Ik words, ‘The number of page faults using LRU policy, for following page 20 eens 1 and of 8085 chip mast be (@)_equaltothe desired clock frequency (b) twice the desired clock frequency. (©) fourtimes the desired clock frequency. (@) eighties the desired clock frequency UPS. ez, Which ofthe following counters canbe used to divide the cock frequeney of microprocessor by 3? (@) Sbitcountr. (b) Sbitcounter. © mod Scounter. (mod S counter. TUPSEuEs. exe,200 Jn 8085 if the clock frequency is § Mit, the tne reed © xcoutean instruction of 18 Ttaes is @ 30us & 36us (© 40ns (@ 6Ons : (ursc.uss.ere, 208 A logic operation that wil selectively clear bitin register Ain pose sions where there areI'sindhe bis of eit Bie @ Acasa © ACRE © Ac AB @ Ac AB TWPsc. ues. 218,200) tion word to indicate, if an ind IE We use 3 bits in the instiue ot eonimuously stored dts 20m, what the roan speed 9.35. 10:65. cola ree aasahet (urse.1es.Er8, 1 ‘Aers 244), 245. (246 (0 2A.) 288.) 289.0280.) 254.) 29) 253,284 28 256, (8), 257 (0), 258 (0s 259.0) sig261. 262. 261. Answers: 260. (6), 261. (b), 262. (c). 263. (€), 264. (0), 268. ( . An ‘Assembler’ fora microprocessor is In 8085 microprocessor the value of the mos significant bitof the feat following the execution of a seat flowing te any athe or Boolean @ theeany-satueMas —) thea © tesignstawsag —() ese smueig TOS. LS RT, 198 09 Which one of the following flags isn ching na ok 8 flags is not used for branching in a (a), Camry fag. (©) Auritiaryea © Overflow flag. pr Diy cay ld (@) Party fag ‘ue es, An instruction used to set the carry flag in a comy : classified as on dashes Gq) diatranstr © logic. () arithmetic. (program contol (GATE BCE, 198) ed for ‘assembly of processors in a production li () creation of new programmes using different modules, translation ofa program from assembly language to machine language. translation of higher level language into English text. GATE RCE, 198) [A microprocessor based system can perform many different functions, because {@)_itsoperationis controlled by software. @) itisdigital system, (6) ituses aRAM. (@)_itcan be controlled by input and output devices. TURSC LES. EE 210) outgt data lines of microprocessors and memories are usually @ data bus at the same time, (©) the data lines can be multiplexed for both input and output. (@) itincreases the speed ofthe data transfers over the data bus TUPSC LES. BRE 2010 E2010 . Inregisterindex addressing mode the effective addressis given by (@) theindex register value. (©) the sumof the index register value and the operand. (©) theoperand (@) thedifference ofthe index register value and the operand GATE HC, 1998) Consider the following registers: 1. Accumulator and B register. 2. Band Cregisters. 3. Dand Eregisters. 4, Hand L registers ‘Which of these 8-bit registers of 8085 uP can be paired together to make a l6-bitregister? @ 1.3and4 (b) 2,3and4 © Vand2 @ 1.2and3 TUPSC. LES ETE, 200) ‘Consider the following statements: 1. In8085 microprocessor, the pairs of general purpose «= fers forte operaonsre ACD an 2. It nimopersor hedte fis known (ADs =A 9. 80t3 microprocessor ALE es Saunas ban \nichot he stemen glen above coe? @ nama Zand Son. © Tend ony. and only. z (8) Fane pS UES. EAE, 2071 xddress multiplexed ed to operate multiplexed 215. (), 276, (@), 277. (0), 278. (@) 270. m. mm. 273. 274, 276. a. 278, . Consider the following re Computer Fundamentals and Miroprocesers 136003 |/AONSS 1, Accumulotorand register 2. Band Cregisters 3. DandEregisters 4, Hand Lrregisters ‘Which of these bit registers of 8085 1P canbe paired together to make a 16-bitregister? (@) I,3and4. () 2,3and4. (©) Vand2. (@ 1,2and3. (urs. AS ETE, 2002; E20 “The 8085 has two registers known as primary data pointers. These areregisters G@) BandC (6) Dandé (¢) HandL @) Cand D (PSC. LES TE, 200) Following isa 16-bit register for 8085 microprocessor: (@)_Stackpointer. (@) Accumulator. (©) Register. (@ Register. UPC. AES, Fe 2021 Inan assemble, which one ofthe followings required for variable names in symbol table? (a) Addeesses. (6) Registers. () Values. (@) Storage, THPSc-nEs, Bae 3000) Which one ofthe following register of 8085 microprocessors not apartof programming model? (@) Instruction register. (©). Status register. (&) Memory address register. (@) Temporary data register Torsctes. ET 3006) In an 8085 microprocessor, the shift registers which store the result of an addition and the overflow bit ate, respectively (@) Band () AandF (©) Hand F (@ AandC (care ECE, 20151 petromcs Aceadciny 93 There can be maximum of 256 input devices and 256,butput devices “4, ‘Arithmetic and logic operations canbe dreetly performed with the VO data Select the correct answer using the codes given below: @ 1,2and4. ©) 13and4, (© 2and3. (@ Vand [UPSC.UES. EE, 205) ‘Ina microprocessor system with memory mapped VO. (@)_ devices have 8-bitaddresses. ()_ devices are accessed using IN and OUT instructions {@)_ there can bea maximum of 256 input devices and 256 output devices. (@) arithmetic and logic operations can be directly performed ‘withthe VO data, [UPSC.LES ETE, 20151 ‘An VO processor controls the flow of information between (@) cache memory and W/O deviees. (@) main memory and VO devices. (©) twoVO devices. (@) cache and main memories. Ina microprocessor, WAIT states are used t0 (@)_ make the processor WAIT during a DMA operation. (©) make the processor WAIT during an interrupt processing. ()_ make the processor WAIT during a power shunt down. (@)inerface SLOW peripheral tothe processor. [UPS 1ES, ETE, 2051 ‘266. (a), 267. (b), 268. (b), 269. (b), 270. (¢), 271. (a), 272. (€),273: (), 274 (O),y | ' | An Integrted Course in Electronics and Comsnunication Engineering 279. Ina microcomputer, WAIT sates are used to (@)__make the processor wait during a DMA operation, (©) maketh processor wait during an imerrupt processing. (©)__make the processor wait during a power shutdown, (@) interface slow peripherals tothe processor, came ne 280. ‘The statement label in a subroutine : (2) may be the sameas in the main program, (©) isalways the same asin the main program, (cannot be the same a in the main program, (@ cannot be used, WS. 18S. e208) 281. ‘The contens of accumulator in an 8085 microprocessor ae altered after the execation ofthe nstnction? (@) CMPC. (0) CPI3A. (© ANISC. (@ ORAA. TWRSecues hn, 208) 282, Inan8085 microprocessor, which one ofthe following instructions ‘changes the content of the accurmlator? @ MOV B,M () POHL (©) RNZ (@) SBIBEH (oaTe nee, 208) 283, Forthe 8085 assembly language program given below, the content ‘ofthe accumulator after the execution ofthe program is 30H MM AH so02H MoV BA so0sH sre sooth CMe S00sH RAR 3008H RAB @ OH O 4H © OM @) ETH (are 2c, 20 Flsetrorics 285. Consider the following instructions of $085 pP: 1. MOV M, A, 2 ADDC 3. MVIA, FF 4. CMP M Which ofthese cause change in the status of flag (5)? (@) 1and2. (©) 1,2and3, (© Sanda, (@) Zand, TOPS. uns. E200) 286. Consider the following: 1 Sign Fag, 2. Zero Flag, 3. Cary Flag, 4. Party Flag. Which ofthe above lags of 8085 get affected by the instruction ‘SUB B? (®) 1and2. (&) 1and3. (©) 3and4. (4) 1,2,3 and4, TUPS.C.LRS, Ey 20) 287, Each instruction in an assembly program has the following fields 1. Label field. 22. Mnemonic field 3. Operand field 4. Common field ‘The comect sequenceforder of thes fields is: @ 12.34 ©) 1,243 © 2134 (@) 21,4,3 WSC as. aa, my 200) 288, The first machine cycle of an instructions always (a) amemoryreadcycle. (b) afetcheycle. @ anVOreadeycle. (@) amemory witecyce, One Turkestan ‘Answers: 279. (8), 280. (3) 281. (0), 282 (8), 283. (©), 284.0), 285. (0), 286. (8), 287, (a, 294, (a), 295. (d), 296 (0), 297. (b) the numberof machine cycles”, and te types of machine a4 ia it for PUSH B? cycles carted (n=? fech and memory wre (hy. m= 3, fetch and 2 memory write, (©) m= 3, fetch memory write and ead (@) madfetchand2 memory Tae essa ier hefollovng statement : Fn can ost nen of acme seem 2 erat pening F eeremamatne. 4 sealouptdtae Tinker sateen ven aioe recone? ) 3and4. (8) Landd, (©) Land 2. () 2and3. (0) Dane OO a 4085 as 87H nd 79 ten 2 a CARRY and ZERO fg il be se100 (3 Gane gw eet 0-ZERO Hast () EARRY fag ibe ZERO M00, wn ZERO Map il ot (8 Somcanian Zeno mpc 292.1085 mioprocesor als 7 Hand 79H, tags wb ty sezee,accoandey = ( sr0za0.Ac=t andy. mel, i twrae.urs ere, 293, One 85, whch of he following machine cycles re eed ine CALL ncn? 1 nsncion Fach 2 Mano ead 2.00 4, Memory Write 3. Memory Read 4. Memory Write Selectthe correct answer using the code given below: @) 2only (©) Land 4 only. (© 23and4, @ 1.2.3 and4 TUPSC Les EE 2001 298. Consider the following instructions of 8085 microprocessor: 1 Mov a,c 2 STA addtess 3. ORLbyte ‘The conect sequence inthe decreasing order of thei respective ier saereqennts (@) 3,2and 1, (©) 1,3.nd2. @ U2an 4 © 23am TPS. es, exe, : nain programs conditions uconin he subroutine canbe 296, Ifthe CALL instevetion o 085 inthe then RETURN: (@) conditions (©) conditional or unconditional, (© canbe determined by LDA instruction (@) unconditional. WUPSC, Les, Ee, 20 297. In $085 ifthe clock frequency is 5 MEiz, the time ce . is Metz, the time requ xeeute an instucton of 18 Tstateig ne TONERS © 30us ©) 36us dons (a) 6ons Wrsc. tes. Ere, 2061 268. (0,289. (6), 290. (@), 291, (a), 292. (@, 293-10298. 299. 301. 302, 306, 307, ‘Ansiners: 298 0) 290, a), 300. (301 (0, 302, ©), 303.) 304, (0), 308. (), 306 (a), 307. (6),308. (6,309. @), 310. OS ieeemlyda wis, timerequiredto execute an instructions hus thon te a esiorscaasrante is therbenonk ofan eng ct EL kes eee a oe required to execute instruction XTHI, over hia miceproccenn, ecstatic (© 433nsee. © 867 psec hap ele et ae ofthe aceumulator (©) ANI FOR. (@) ANI OFH. TWPSeLes. e200) ‘Which ofthe following instructions copies abyteof data into the ‘coumulator fom the memory adess given inthe instruction? @ LDA address () LDAX B. (© LHLD adktess. (@) STA address (UPSCLES, Exe, 2010 For the 8085 assembly language program given below, the content, fof te accumulator afte the execution ofthe program is 3000 MVIA, 45H 3002 MOV B, A 3003, sTc 3004 cmc 3005 RAR 3006 XRAB 3007 HLT © 5H © 7H @ ETB WUPScUEs. EE, 2011 x RST inka, (@) 0030H. () 0005 H. (@) 00281. (G) (UPSCLES. ETE 20 For peo fetch operation i 8085 microprocessor RD =0, ALE high in T, BD =0, ALE high i 7, BD =0, ALE high in BD =0, ALE high in Ty fursdigs exe. 5. An 8085 microprocessor executes the following instructions: “The numbers are represented in signed 2's complement form as P=I1101101 and Q= 11100110 If Q is subtracted from P, the value obtained in signed 2's ‘complement form is, (@ 100000111 (b) 09000111 © 1001 (@ o1i1s1001 [UPSC.UES. EE 2021 ‘Which one ofthe following instructions uses implied addressing mode? @ CMA @ sBB [UPS HES. Bo 2081 tack of the execution ssof the next (@) IMP @) ADC A tegister of microprocessor which keeps t ‘of program and which contains the memory addres instruction to be executed is called (®) index register, (b)_-memory address register. (©) program counter. (@) instruction register. TURSC. LES. ETE, 201% 2016) 313. (0), 314. (©), 315. (a), 316.) cS" 310. au. 312, 314. 315. 316. Micoprocesors ES6TH holds the address ofthe iri 2h unter’ agin (@) Accumulator (b). Program counter © Stra ‘pte th ap ck a eee ttt ees tere oes oy ngamcomet sine bn ‘Which one of the following Keeps track of instruction execution sequence? {@) Accumulator. () Program counter. (©) Stack pointer. (@ Instruction register. TUPSC. LES. BT, 1996 A tegster of microprocessor which keep track ofthe execution of ‘program and contains the memory address ofthe next instruction tobeexecutediscalled (@) index register. (©) program counter. (6) memory address register. (@) instevction register. TUPSC. LES. T2015, “The program counter (PC) in microprocessor (@) counts the number of programs being executed by the microprocessor. (6) counts the number of instruction being executed by the microprocessor. (6). countsthenumber of nterupts handled by the microprocessor. (@)_ keeps the address ofthe next instruction tobe fetched. TUPSC.LES. ETE 2013) following pairto the contents of the DE register Pal. ‘The program counter is an instruction pointer. ‘Whenever an instruction uses the HL pointer, the addressingis called indirect addressing. HEL register paris also called data pointer. (@ Land 2 only. (@) 1,2and3, (© 23and4. (@ 2and only. TUPSE LES ETE, 2013) “The stack pointer willbe affected by instructions: 1. PUSH PSW 2. CALL ADDR 3. XTHL, 4. RSTn (@ 1,2,3and4. (b) Land3 only. (© 1,2and4 only. (@ 2,3and4 only. TUPSC.LES. ETE, 20131 Consider the folowing statements regarding RESET instruction ‘0f 8085 microprocessor: 1. PC contents become 00004. 2. Allinterrptsare enabled. 3. RESET OUT pinisat logic 0. ‘Which ofthe above statementsisfare correct? (@ only. (b) 2only. (©) Land2. (@) 2and3. i (UPSC.1ES. ETE, 2014 Ina microprocessor when a CPU is interrupted, it @)_ Sop cerun onc, ) acknowledges interrupt and branches of subroutine, (©) acknowledges interrupt and continues (@)_ acknowledges interrupt and waits for the next instruction from the interrupting device. a(Sera ‘from the interrupting device, (GATE F.C, 1995) 318, Anadddressing mode in which the location ofthe data icontained : sorters Li: DECCX Ursc. Les. ee, 2016) ©) 012s © 366s (@ 4.19 TWPS.C.LBS. Et, 2017) 320. Which one ofthe following parsis not correctly matched? (2) Horizontal micro-instuetion: CISC instruction (b) Multiplier contrat: 2's complement (©) Multiplier contol unit: Encoding by function (@_Venical micro-instruetion:IUSC instructions [UPS LES ene, 20m 321, What are the commands tothe assembler itself, called? (@) Macros (©) Macro instructions, (@) Pseudo intritions. |. Eleegtronics I I jimpinsructonsexcued | tanning and evinginpu-oupu da, | (©) sting al imgoran CPU eis cones whenever an inemiptistobesenced | (€ ering propa insrcosferineopervice rotting, | (GATE EC, 1989), | | t 323, The total number of memory accesses involved (inclusive ofthe ‘op-code fetch) when an 8085 processor executes the instruction LDA 2008 His @i 2 ©3 wa (GATE EE, 196) ‘324, In an 8085 microprocessor, the instruction CMP B has been executed while the content of the accumulators less than that of register B, Asa result Carry flag will be set but Zero flag wil be reset, \ (0) Cary flag will be reset but Zero flag will be set. (©). Both Carry flag and Zero flag will be rest (@_ Both Carry flag and Zero flag will be set. GaTER.ce, 205) 325, ‘The contents of Register (B) and Accumulator (A) of 8085 microprocessor are 49H and 3AH respectively, The contents of A andthe status of cary flag (CY) and sign flag (S) after executing ‘SUB B instructions are SERS G52 Sma as Brg per TS BE eT A Ileraed Course in Eectrnis ond Communication Engine sah, The number of memory eles required to exer the fllovng Sinaeions (DUDA 3000 GDLXID, POPE ea 4 for (1) and 3 for (U), jand 2 for (ID. (b) 4 for ©) Pho Dane ford), (8) 3for Cand for, © 3fora “Ae 5 instons given below sider te sequence of 08 ar TH 9258, MOV A, M, CHA MOV Jane ofthe lowing is peiom We oe of locaton 9238are moved tthe accumula, (> Comet of oeaton 9258 are compared With the one oe accurate. (o Gimeno locaton 9258 re complemented and soredia jeation 258 (Contato lesion $892 ar complemented and soda ieaton 589. (cer wea ti rs and store the sds to lil the numbers OAH by OBH a er nthe scala The mumbersare avalible nega and Crespectvely. A part ofthe 8085 program for this purpseis given below: MVIA, 00H Loop: HLTEND ‘The sequence of instruction to complete the program would be (@ JNZLOOP, — ADD B, DCRC (©) ADB, JNZLOOP, — DCRC © DcRC, JNZLOOP, ADD B INZ LOOP Acadenty= é LXI SP, OOFFA LXIH, O107H MVIA, 208 SUBM The content of accumulator wi 109 is (@) 20H hen the program counter reaches ©) OH © OOH @) FF (Gate Ee, 208) 330. Initially content of accumulator a ontent of memory lly area tor are OOH and content of Tin addition folowing. ORI 40H ADD M ‘What willbe the resutin the. isexecuted? (@ 40H code exists from 0109 H onwards, Accumulator after the last instruction ©) 20H ©) CoH) 42H (Gave ce, 208 the following instructions: SOA me instructions 381, An8085 executes 27104 LXUH, 2713H DAD H 2714H PCHL ae@ PC=271H (@) PC= 2008 @ pes eto @ PC=6140H HL=2715H (care RCE, 4, An 9085 astembly language program i given bean, heen thatthe cary flags intially unset, Thecontentof he ecg after the execution ofthe program is, iets MVIAO7H RIC MOV B,A RLC RLC ADD B RRC (@ 8CH ©) 4H © BH w IsH 333, Inan 8085 system, a PUSH. TGATH Ec, 2011) nan 8085 system, a PUSH operation requires more elockeycles thana POP oeton, Whicrone tte folovingoplon ic corect reason for this? {@)_ ForPOP. the data receivers remain in the same direction as for instruction fetch (memory t processor), wheres for PUSH their direction has tobe reversed Memory write operations are slower than memory read ‘operations in an $085 based system. ‘The stack pointer needs tobe predecremented before writing registers in a PUSH, whereas POP operation uses the audress already in the stack pointer. (Orders of registers has to be interchanged for a PUSH on, whereas POP uses their natural order. toate eee, 2016) o © 'RLC is executed! carry fag, respectively willbe (@). 4EandO (b) 4Eand1 (c) 4Fand0 (@) 4Fand 1° GATE RCE 2016) 4335, The MODEM is used with a personal computer todo which of the following? (@)_ Convert from serial to parallel and vice versa. (©). Convert signals between TTL and RS 232 standard and vice versa, Convert from digital to analog signals and vice versa. ‘Toconvert the computer toa long distance communication link. [UPSC.LES. EE 2012) 4336. Which one ofthe following is used a the interface chip for data transmission between 8086 and a 16-bit ADC ? (@ 8259 (b) 8255 (©) 8253 @ 8251 [UPSC.LES RTE, 20081 © o 4337. The interface chip used for data transmission between 8085 and I6bit ADCis a) ©) 8255. @) 299 251) 8253 ©) 8255, OS an 388, The merac chip used for data tansmissionbeoween 808648 164i ADC is @ 8259 (b) 8255 ©) 8253 (@) 8251 [UPSCLES ETE, 978) 339, Whatis the purpose ofa start bitin RS232 serial com protocol? {@) Tosynchronise receiver for receiving every BYE. (©) Tosynchronise receiver for receiving sequence of Pte Answers: 332, (¢), 333. €), 334. (@), 335: (©) 37.0) etree seston Computer Fundamentals and Microprocessors; ‘MBAS (©) Acts asa pay bit (@) ‘Tosynchronise receiver for receiving the lastbyte TUPSCLES ETE, “The purpose of asta bit in RS232 serial communication protocol is (@)_tosynchronize receiver for receiving every byte o ze receiver for receiving a sequence of byte. © @ asaparity tosynchronize receiver for receiving the last byte. TUPSC. LES. BITE, 20%, 2010) ‘When compared with an RS232C serial port, the USB (Universal Serial Bus) 341, @ ©) © @ supports a lower range of peripherals. supports a faster transfer rate does not suppor, ‘Hot plug-ability’ controller in PC can not detect the presence or absence of USB devices. TUPSC.LES. BIE, 2010) “The 8254 Programmable Interval Timers et to work in MODE 5, The following would best describe its function: (@) Sofware triggered strobe. (6) Hardwate triggered strobe. (©) Square wave generator. (@ Interrupton terminal count, (UPS.C-1ES. E.R. 20121 ‘To configure port A and port B as output pots, port C not being used in the $155 programmable interface, the contol word should 342, 343. have the value (@ 03H) OH (©) 02H (a) 6OH Tursc-res. ETE, 20101 ‘344, With espect to the default R7 routine in 8259 PIC, which ofthe following statements are corect? ‘with lowest priority (@ 1,2and3. (©) Vand 3 only. () Land 2 only. (@) 2and3 only. [OPSE LES. ETE, 2015) Inmode O, interrupt on terminal count of 8253, ifthe gate pin is made low while counter is decrementing, which one of the following operations will follow? (4) Counter stops and cleared to “0” and starts deerementing ‘when gate pin is made high. () Counter stops and thereafter itinerements il gate pi high. ‘Countertops, the current contents are held andthe decrement ‘operation resumes only after gate pin is made high. ‘Counter stops, the current contents are held for one clock ‘cycle andthe decrement operation resumes. (UPSC.LES ETE, 2015) Ms. a © @ Consider te following statements: sie a259A Programmable tempt Conor can Tr manage eight inept 2. ectran teopeqestnywhetlnthe memory ma 5 hved bor 16 btinewal betwen nemo vec cto 4 telnaind wit operational command wos ‘Which of he sbove stents ae cect? @ L2andSeniy (@) 2anddonly. (©) 3and4 only. @ = 1,2,3and4, turse us ena 347. What are the conditions which are necessary for using a parallel port? "336. (), 337. ©, 338. (0) 339. (2), 340. (2), 341. (6), 342. (0), 343. (@), 344, DROME, secsif i jaar izing by placing appropriate bits atthe contol register. ling on interrupe whenever a status flag sets a the status register, 23. Interrupting servicing (device driver) programming. Selectthe comest answer using the code given below: (@ Land? only. () Land 3 only \ (© 1,2and3, (@) Zand 3 only . i (urs res. 20 348. An asynchronous link between two computers uses the star sop Scheme, with one start bit and one stop bit, anda transmission rate 0f 48.8 kbit/s, Whatisthe effective transmission rate as seen by thetwo computers? (@) 480 bytes | (©) 4880 bytev5 () 488 oyteus @) 4800bytes's : (USC Les xr 207 349, Consider a memory chip with 1024 bytes storage connected t0& 8085 chip address lines (or any microprocessor with 16 address I lines) as below, What isthe range of memory address? Ans Ate Are i is — Elee | 350, An S-bit microprocessor has 16-bit address bus Ay-Ays. The processor has a1 KB memory chip as shown, The address range Beacatips ws | aE [ear Ht 4 cs. 4 gE a (@) FOOFH to FOE (© F000 H to FFF H (©) FIO0H to PAF H (©) F700 Hito FAFF H (GATE Ec, 999 351. The decoding circuit shownin figure hasbeen used to generate the active low chip select signal fora microprocessor peripheral. (The address lines are designated as Ay to A, for UO addresses) ‘The peripheral will comespond to VO addresses in the range zs Lo * [ew ecucr ee Gouin Bectronics and Communication Engineering @ ore eee os OS oman esti tt eg Sromgesto sen tee aay aa and te Conta EBT ¢ ae sa chip would get selected is 382, An 8255 chips () FBH-FCH. (@) FOH-FTH.(careE.ce, 307 1353. Inthe circuit shown, the device connected to YS can have adress (@) FSH FBH, (© FSH -FFH intherange coat ee, a 354. A microprocessor wih I6tit address busi sed in iar men selon cnfgation (Aes busines eet ‘ea chipset of memory ei wh 4 meray hip The Imaimumaddesate enor pete Ook OW ibk © Bk 4k (eaten, 2m 355, nan 085 miroprocetrsytem wih memory mapped VO, ("WO deveshave laden? (©) WO devise accesed xing TW and OUT into (© there canbe maximum of 236 input deve ond 56 on seven (@) arithmetic and logic operations can be direct! formed wiht 0 da tener 356. Fora microprocessor system using VO-mapped UO, which ofthe following statement(s)is NOT true? (®) Memory space available is greater, (©) Notall data transfer instructions are available. (© WO and memory address spaces ae distin (©) WOaddtess spaceis greater, Gare ece, 198) 387. The 8255 felon FOBFAmmable Peripheral Interface is used a deseibed aa ‘A Then interfaced to a microprocessor through chee Spaetson i nated by a signal rom he 825, tA, Ton Port C causes data tobe strobed intoComputer Fundamentals and Microprocessors Z| OP ons ava biden ia A OFS, on A handsbeking signals, '# Port supported by appropriate Hergromias meet pond nei pen of te 8255 for) an cy (@) Mode 0 for (1) and Mode 1 for (1 (8 Move for) and Mote ory (©) Mode 2 for (I) and Mode 0 for(i, (@) Mode 1 for (1) and Mode 2for (i). care nce, jae Forte 985 leeqroceac, the neraing se 8-bit digital data (DI, ~DI,) from an extemal device estore te the figure. The ination orcomectdataterctos en 358. = = ‘clea “a 3 [REUTS) Dl-Dty Diy-Do, | OagAgus) nt FE Te jocm eos) TxSa Gy os, in = &: & (@) MVIA, FH () IN FSH (© OUT FSH (@) LDA FSF (GATE ECE, 2018) ROM with an ayve low Chip Sletinpat RS) ist efx ‘ ° 209. shosktdey rod int2 = S fi " address bit ‘Which one of the following logic expressions will generate the correct CS signal for this ROM? Ast Aut An Ant An“) () Ays* Ayg* Ais + Ay) © Aiy-Rig-(An +A *Ais An) @ AystAuet An Ae cexre nce, 2018 36, READY signal in 8085 is useful when the CPU communicates with {@)_aslow peripheral device. (b) a fast peripheral device. (© aDMAconteollerchip. (4) a PPIchip. UPSc.1Rs, EEA 2001 1361. Consider the following statements: ‘The 8085 microprocessor will not enter into cycle whenever 1. INTR interrupts recognized. 2, RST x: isrecognized. 3. DAD r, instrction is executed Wihichof the statements given aboveisfare comet |, (0) only.) Zonly., (2) Land 2, 0) 8 aaa is both level and edge bus idle machine ‘362. Which one of the following interrupts sensitive? ark @) Ri () TRAP @) 2 @ RST7S (b) RSTSS (TRAP, (TT nest 363, 1n 8085 microprocessor, after the execution of RST instruction, the program contol shifts 0 “Answer: 358(@ 359, (a), 360. (a, 361 (€), 362. (©), 363. ©), 364. (6), 368. (), 366. (), 367 (a), 368. (2), 369. (@), 370. (0), 364 368, 366, 367. 368, 370. am. 32. (@) 0030, (6) 0005 H. (©) 0028 H. (A) 0024 H. [PSCLES: EE, 2012) CConsier the following 8085 interrupts: 1. TRAP 2. INTR 4, RST 7S 5. RSTO ‘The sofware imerrupts are (@) Land only. (©) Band 5 only. 3, RSTO (o) dand only. asad. , TUPS.C.LES. E-LE, 2012) “TRAP raninemtin 08S Wichonecf hollowing state ist aboutte TRAP? Gy tittecluggered, — @) Risnegtveedge tigger (O, Mispostiveedgetigsered. {@) is both postive and negative edge iggered- me : art PSC. LES, B-T-E, 2013) ‘Whatisaninterruptin which he extemal device supplies its adress as well a the interrupt quest known a8 (@) Vectored interrupt, (b) Maskable interrupt. (©) Non-maskable interrupt (8) None ofthe above. | [PSC LES. RE, 208) ‘An interuptin which the external device supplies its address as ‘well as the interrupt request, is known as (@ vectoredinterrupt(b)_maskable interrupt (©) polled intemupt (@) noni interrupt TUPSE-LES. ETE 1978) nan 8085 pP system, the RST instruction will cause an interrupt (@)_ only ifan interrupt service routine is not being executed. (only ifa bitin the interrupt maskis made 0. (6) only if interrupts have been enabled by an Elinstruction. @, (Gare RCE, 197) ‘none of the above. cro rie sgrvi in ntergupt mf fixed ich cabot Be CRtergaly 1, ucllan itigrrupt (@)_none-maskable and non-vectored. (@)_ maskable and non-vectored. (©) non-maskable and vectored. (@)_maskableand vectored. “The number of hardware interrupts (which require an external signal to interrupt) present in an 8085 microprocessor are (GATE ECE, 200) @ 13 GATE ECE, 200] In the 8085 microprocessor, the RST 6 instruction transfers the program execution tothe following location: (@ 30H © 24H © 48H @1 4 © 5 @ 6H GATE R.CE, 2000) Consider the following program: ‘ORG 7000 LXIH, 7000 H MOVE AL ADD H IMEND, RSTO PCHL ALT ‘Which one of the following statements is correct? (@)_ The program will halt the processor. (©) The program willbe repeated infinitely. (©). The program will branch to 0007 H after JM END. (@) ‘The program will branch to 0000 H after JM END. TUPSC.LES. EE, 20) BEGIN: END: 1 @),372.(0)