CY7C64215
CY7C64215
Features
■ Powerful Harvard Architecture Processor ■ Additional System Resources
2
❐ M8C Processor Speeds to 24 MHz ❐ I C Slave, Master, and Multi-Master to 400 kHz
❐ Two 8x8 Multiply, 32-Bit Accumulate ❐ Watchdog and Sleep Timers
❐ 3.15 to 5.25V Operating Voltage ❐ User-Configurable Low Voltage Detection
❐ USB 2.0 USB-IF Certified. TID# 40000110 ❐ Integrated Supervisory Circuit
❐ Commercial Operating Temperature Range: 0°C to +70°C ❐ On-Chip Precision Voltage Reference
❐ Industrial Operating Temperature Range: –40°C to +85°C
■ Complete Development Tools
■ Advanced Peripherals (enCoRe™ III Blocks) ❐ Free Development Software (PSoC Designer™)
❐ 6 Analog enCoRe III Blocks provide: ❐ Full Featured, In-Circuit Emulator and Programmer
• Up to 14-Bit Incremental and Delta Sigma ADCs ❐ Full Speed Emulation
❐ Programmable Threshold Comparator ❐ Complex Breakpoint Structure
❐ Four Digital enCoRe III Blocks Provide: ❐ 128K Bytes Trace Memory
• 8-Bit and 16-Bit PWMs, Timers, and Counters
• I2C Master Block Diagram
• SPI Master or Slave
• Full Duplex UART
• CYFISNP and CYFISPI Modules to Talk to Cypress CYFI
Radio
■ Complex Peripherals by Combining Blocks
■ Full Speed USB (12 Mbps)
❐ Four Unidirectional Endpoints
❐ One Bidirectional Control Endpoint enCoRe III Core
❐ Dedicated 256 Byte Buffer
❐ No External Crystal Required
❐ Operational at 3.15V to 3.5V or 4.35V to 5.25V
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 38-08036 Rev. *E Revised February 1, 2010
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Contents
Features ............................................................................. 1 Pin Information ................................................................. 8
Block Diagram .................................................................. 1 56-Pin Part Pinout ....................................................... 8
Contents ............................................................................ 2 28-Pin Part Pinout ....................................................... 9
Applications ...................................................................... 3 Register Reference ......................................................... 10
enCoRe III Functional Overview ...................................... 3 Register Mapping Tables .......................................... 10
enCoRe III Core .......................................................... 3 Register Map Bank 0 Table: User Space .................. 11
The Digital System ...................................................... 3 Register Map Bank 1 Table: Configuration Space .... 12
The Analog System ..................................................... 4 Electrical Specifications ................................................ 13
Additional System Resources ..................................... 4 Absolute Maximum Ratings .......................................... 14
enCoRe III Device Characteristics .............................. 4 Operating Temperature .................................................. 14
Getting Started .................................................................. 5 DC Electrical Characteristics ..................................... 15
Development Kits ........................................................ 5 AC Electrical Characteristics ..................................... 22
Technical Training Modules ........................................ 5 Packaging Information ................................................... 28
Consultants ................................................................. 5 Package Diagrams .................................................... 28
Technical Support ....................................................... 5 Thermal Impedance .................................................. 30
Application Notes ........................................................ 5 Solder Reflow Peak Temperature ............................. 30
Development Tools .......................................................... 5 Package Handling ........................................................... 30
PSoC Designer Software Subsystems ........................ 5 Ordering Information ...................................................... 31
Hardware Tools ........................................................... 6 Document History Page ................................................. 32
Designing with User Modules ......................................... 6 Sales, Solutions, and Legal Information ...................... 33
Document Conventions ................................................... 7 Worldwide Sales and Design Support ....................... 33
Acronyms Used ........................................................... 7 Products .................................................................... 33
Units of Measure ......................................................... 7 PSoC® Solutions ...................................................... 33
Numeric Naming .......................................................... 7
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Applications The 24 MHz IMO is doubled to 48 MHz for use by the digital
system, if needed. The 48 MHz clock is required to clock the USB
■ PC HID devices block and must be enabled for communication. A low power 32
❐ Mouse (Optomechanical, Optical, Trackball) kHz ILO (internal low speed oscillator) is provided for the Sleep
❐ Keyboards
Timer and WDT. The clocks, together with programmable clock
dividers (System Resource), provide flexibility to integrate
❐ Joysticks
almost any timing requirement into enCoRe III. In USB systems,
■ Gaming the IMO self-tunes to ±0.25% accuracy for USB communication.
❐ Game Pads
The extended temperature range for the Industrial operating
❐ Console Keyboards
range (–40°C to +85°C) requires the use of an external clock
■ General Purpose oscillator, which is only available on the 56-pin QFN package.
❐ Barcode Scanners
enCoRe III GPIOs provide connection to the CPU, digital and
❐ POS Terminal
analog resources of the device. Each pin’s drive mode may be
❐ Consumer Electronics
selected from eight options, enabling great flexibility in external
❐ Toys interfacing. Every pin also has capability to generate a system
❐ Remote Controls interrupt on high level, low level, and change from last read.
❐ USB to Serial
The Digital System
enCoRe III Functional Overview The Digital System is composed of four digital enCoRe III blocks.
The enCoRe III is based on flexible PSoC architecture and is a Each block is an 8-bit resource that is used alone or combined
full featured, full speed (12 Mbps) USB part. Configurable with other blocks to form 8, 16, 24, and 32-bit peripherals, which
analog, digital, and interconnect circuitry enable a high level of are called user module references.
integration in a host of consumer, and communication applica- Figure 1. Digital System Block Diagram
tions.
Port 7 Port 5 Port 3 Port 1
This architecture enables the user to create customized Port 4 Port 2 Port 0
peripheral configurations that match the requirements of each
individual application. Additionally, a fast CPU, Flash program
memory, SRAM data memory, and configurable I/O are included Digital Clocks To System Bus To Analog
in both 28-pin SSOP and 56-pin QFN packages. From Core System
enCoRe III architecture, as illustrated in the “Block Diagram” on
page 1, is comprised of four main areas: enCoRe III Core, Digital
DIGITAL SYSTEM
System, Analog System, and System Resources including a full
Digital enCoRe III Block Array
speed USB port. Configurable global busing enables all the
device resources to combine into a complete custom system.
8 Row 0 4 8
Configuration
The enCoRe III CY7C64215 can have up to seven I/O ports that
Configuration
Row Output
Row Input
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P2[6]
Sigma ADCs.
P2[3]
■ Digital clock dividers provide three customizable clock
P2[4]
frequencies for use in applications. The clocks are routed to
P2[1]
P2[2]
both the digital and analog systems.
P2[0] ■ The I2C module provides 100 and 400 kHz communication over
two wires. Slave, master, and multi-master modes are all
supported.
■ Low Voltage Detection (LVD) interrupts can signal the appli-
cation of falling voltage levels, while the advanced POR (Power
On Reset) circuit eliminates the need for a system supervisor.
Analog
Analog
Analog
Block
Blocks
Blocks
Digital
Digital
Digital
Inputs
SRAM
ACB00 ACB01
Rows
Flash
Size
Size
Array Part
I/O
Number
ASC10 ASD11
CY7C64215 up to 1 4 22 2 2 6 1K 16K
ASD20 ASC21 28 Pin 22
CY7C64215 up to 1 4 48 2 2 6 1K 16K
56 Pin 50
Analog Reference
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Debugger The user module library contains the following digital and analog
The PSoC Designer Debugger subsystem provides hardware module designs:
in-circuit emulation, enabling the designer to test the program in ■ Analog Blocks
a physical system while providing an internal view of the enCoRe ❐ Incremental ADC (ADCINC)
III device. Debugger commands enable the designer to read and
❐ Delta Sigma ADC (DelSig)
program and read and write data memory, read and write I/O
❐ Programmable Threshold Comparator (CMPPRG)
registers, read and write CPU registers, set and clear break-
points, and provide program run, halt, and step control. The ■ Digital Blocks
debugger also enables the designer to create a trace buffer of ❐ Counters: 8-bit and 16-bit (Counter8 and Counter 16)
registers and memory locations of interest. ❐ PWMs: 8-bit and 16-bit (PWM8 and PWM16)
Online Help System ❐ Timers: 8-bit and 16-bit (Timer8 and Timer 16)
2 2
❐ I C Master (I CM)
The online help system displays online, context-sensitive help
❐ SPI Master (SPIM)
for the user. Designed for procedural and quick reference, each
❐ SPI Slave (SPIS)
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online ❐ Full Duplex UART (UART)
Support Forum to aid the designer in getting started. ❐ RF (CYFISNP and CYFISPI)
■ System Resources
Hardware Tools
❐ Protocols:
In-Circuit Emulator • USBFS
A low cost, high functionality ICE Cube is available for devel- • I2C Bootheader (Boothdr I2C)
opment support. This hardware has the capability to program • USB Bootheader (BoothdrUSBFS)
single devices. • USBUART
The emulator consists of a base unit that connects to the PC by ❐ Digital System Resources
way of a USB port. The base unit is universal which operates with • E2PROM
all enCoRe III devices. • LCD
• LED
Designing with User Modules • 7-segment LED (LED7SEG)
The development process for the enCoRe III device differs from • Shadow Registers (SHADOWREG)
that of a traditional fixed-function microprocessor. The configu- • Sleep Timer
rable analog and digital hardware blocks give the enCoRe III
Each user module establishes the basic register settings that
architecture a unique flexibility that pays dividends in managing
implement the selected function. It also provides parameters that
specification change during development and by lowering
enable you to tailor its precise configuration to your particular
inventory costs. These configurable resources, called enCoRe
application. For example, a Pulse Width Modulator User Module
III Blocks, have the ability to implement a wide variety of
configures one or more digital PSoC blocks, one for each 8 bits
user-selectable functions. Each block has several registers that
of resolution. The user module parameters permit the designer
determine its function and connectivity to other blocks, multi-
to establish the pulse width and duty cycle. User modules also
plexers, buses and to the I/O pins. Iterative development cycles
provide tested software to cut development time. The user
permit you to adapt the hardware and software. This substan-
module application programming interface (API) provides
tially lowers the risk of having to select a different part to meet
high-level functions to control and respond to hardware events
the final design requirements.
at run-time. The API also provides optional interrupt service
To speed the development process, the PSoC Designer routines that is adapted as needed.
Integrated Development Environment (IDE) provides a library of
The API functions are documented in user module data sheets
pre-built, pre-tested hardware peripheral functions, called “User
that are viewed directly in the PSoC Designer IDE. These data
Modules.” User modules make selecting and implementing
sheets explain the internal operation of the user module and
peripheral devices simple, and come in analog, digital, and
provide performance specifications. Each data sheet describes
mixed signal varieties.
the use of each user module parameter and documents the
setting of each register controlled by the user module.
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The development process starts when you open a new project Acronym Description
and bring up the Device Editor/Chip Layout View, a graphical
user interface (GUI) for configuring the hardware. You pick the CT continuous time
user modules you need for your project and map them onto the ECO external crystal oscillator
PSoC blocks with point-and-click simplicity. Next, you build
EEPROM electrically erasable programmable read-only
signal chains by interconnecting user modules to each other and
memory
the I/O pins. At this stage, you also configure the clock source
connections and enter parameter values directly or by selecting FSR full scale range
values from drop-down menus. When you are ready to test the GPIO general purpose I/O
hardware configuration or move on to developing code for the
project, you perform the “Generate Application” step. This GUI graphical user interface
causes PSoC Designer to generate source code that automati- HBM human body model
cally configures the device to your specification and provides the
LSb least-significant bit
high-level user module API functions.
LVD low voltage detect
The next step is to write your main program, and any
sub-routines using PSoC Designer’s Application Editor MSb most-significant bit
subsystem. The Application Editor includes a Project Manager PC program counter
that enables you to open the project source code files (including
all generated code files) from a hierarchal view. The source code PLL phase-locked loop
editor provides syntax coloring and advanced edit features for POR power on reset
both C and assembly language. File search capabilities include
PPOR precision power on reset
simple string searches and recursive “grep-style” patterns. A
single mouse click invokes the Build Manager. It employs a PSoC® Programmable System-on-Chip™
professional-strength “makefile” system to automatically analyze PWM pulse width modulator
all file dependencies and run the compiler and assembler as
necessary. Project level options control optimization strategies SC switched capacitor
used by the compiler and linker. Syntax errors are displayed in a SRAM static random access memory
console window. Double clicking the error message takes you
ICE in-circuit emulator
directly to the offending line of source code. When all is correct,
the linker builds a HEX file image suitable for programming. ILO internal low speed oscillator
The last step in the development process takes place inside the IMO internal main oscillator
PSoC Designer’s Debugger subsystem. The Debugger I/O input/output
downloads the HEX image to the In-Circuit Emulator (ICE CUBE)
where it runs at full speed. Debugger capabilities rival those of IPOR imprecise power on reset
systems costing many times more. In addition to traditional
single-step, run-to-breakpoint and watch-variable features, the Units of Measure
Debugger provides a large trace buffer and enables you define
A units of measure table is located in the Electrical Specifications
complex breakpoint events that include monitoring address and
section. Table 5 on page 13 lists all the abbreviations used to
data bus values, memory locations, and external signals.
measure the enCoRe III devices.
Document Conventions Numeric Naming
Acronyms Used Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
The following table lists the acronyms that are used in this ‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’
document. prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (For example, 01010100b’ or
Acronym Description ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimal.
AC alternating current
ADC analog-to-digital converter
API application programming interface
CPU central processing unit
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Pin Information
56-Pin Part Pinout
The CY7C64215 enCoRe III device is available in a 56-pin package which is listed and illustrated in the following table. Every port pin
(labeled “P”) is capable of Digital I/O. However, Vss and Vdd are not capable of Digital I/O.
P0[3], A, IO, M
P0[5], A, IO, M
1 I/O I, M P2[3] Direct Switched Capacitor Block Input.
P0[1], A, I, M
P0[7], A, I, M
P0[6], A, I, M
P0[4], A, I, M
P0[2], A, I, M
P0[0], A, I, M
2 I/O I, M P2[1] Direct Switched Capacitor Block Input.
P2[5], M
P2[7], M
P2[6], M
P2[4], M
3 I/O M P4[7]
Vdd
Vss
4 I/O M P4[5]
5 I/O M P4[3]
6 I/O M P4[1]
56
54
53
52
45
44
55
50
47
46
51
48
43
49
7 I/O M P3[7] A , I , M , P2[3] 1 42 P2[2] , A , I , M
8 I/O M P3[5] A , I , M , P2[1] 2 41 P2[0] , A , I , M
9 I/O M P3[3] M , P4[7] 3 40 P4[6] , M
M , P4[5] 4 39 P4[4] , M
10 I/O M P3[1]
M , P4[3] 5 38 P4[2] , M
11 I/O M P5[7] M , P4[1] 6 37 P4[0] , M
12 I/O M P5[5] M , P3[7] 7 QFN-MLF 36 P3[6] , M
13 I/O M P5[3] M , P3[5] 8 35 P3[4] , M
( Top View)
14 I/O M P5[1] M , P3[3] 9 34 P3[2] , M
15 I/O M P1[7] I2C Serial Clock (SCL). M , P3[1] 10 33 P3[0] , M
16 I/O M P1[5] I2C Serial Data (SDA). M , P5[7] 11 32 P5[6] , M
17 I/O M P1[3] M , P5[5] 12 31 P5[4] , M
18 I/O M P1[1] I2C Serial Clock (SCL), ISSP-SCLK. M , P5[3] 13 30 P5[2] , M
M , P5[1] 14 29 P5[0] , M
19 Power Vss Ground Connection.
15
16
17
18
19
20
21
22
23
24
25
26
27
28
20 USB D+
21 USB D-
Vdd
Vss
D+
D-
P1[3]
P1[1]
P1[7]
P1[5]
P7[7]
P7[0]
P1[0]
P1[2]
P1[4]
P1[6]
22 Power Vdd Supply Voltage.
M,
M, I2C SCL,
M, I2C SCL,
M, I2C SDA,
M, I2C SDA,
M,
M,
M,
23 I/O P7[7]
24 I/O P7[0]
25 I/O M P1[0] I2C Serial Data (SDA), ISSP-SDATA.
26 I/O M P1[2]
27 I/O M P1[4] Optional External Clock Input EXTCLK.
28 I/O M P1[6]
29 I/O M P5[0] Pin Type
Name Description
30 I/O M P5[2] No. Digital Analog
31 I/O M P5[4] 44 I/O M P2[6] External Voltage Reference (VREF) Input.
32 I/O M P5[6] 45 I/O I, M P0[0] Analog Column Mux Input.
33 I/O M P3[0] 46 I/O I, M P0[2] Analog Column Mux Input and Column Output.
34 I/O M P3[2] 47 I/O I, M P0[4] Analog Column Mux Input and Column Output.
35 I/O M P3[4] 48 I/O I, M P0[6] Analog Column Mux Input.
36 I/O M P3[6] 49 Power Vdd Supply Voltage.
37 I/O M P4[0] 50 Power Vss Ground Connection.
38 I/O M P4[2] 51 I/O I, M P0[7] Analog Column Mux Input.
39 I/O M P4[4] 52 I/O I/O, M P0[5] Analog Column Mux Input and Column Output
40 I/O M P4[6] 53 I/O I/O, M P0[3] Analog Column Mux Input and Column Output.
41 I/O I, M P2[0] Direct Switched Capacitor Block Input. 54 I/O I, M P0[1] Analog Column Mux Input.
42 I/O I, M P2[2] Direct Switched Capacitor Block Input. 55 I/O M P2[7]
43 I/O M P2[4] External Analog Ground (AGND) Input. 56 I/O M P2[5]
Note
1. The center pad on the QFN-MLF package should be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground,
it should be electrically floated and not connected to any other signal.
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Electrical Specifications
This section presents the DC and AC electrical specifications of the CY7C64215 enCoRe III. For the most up to date electrical
specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/go/usb.
Specifications are valid for –40°C < TA < 85°C and TJ < 100°C, except where noted. Specifications for devices running at greater than
12 MHz are valid for –40°C < TA < 70°C and TJ < 82°C.
Figure 5. Voltage versus CPU Frequency
5.25
4.75
Vdd Voltage (V)
4.35
[2]
Valid Operating Region
3.50
3.15
CPU Frequency
The following table lists the units of measure that are used in this section.
Note
2. This is a valid operating region for the CPU, but USB hardware is non-functional in the voltage range from 3.50V – 4.35V.
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Operating Temperature
Table 7. Operating Temperature
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DC Electrical Characteristics
DC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and –40°C < TA < 85°C, or 3.15V to 3.5V and –40°C < TA < 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 8. DC Chip-Level Specifications
Note
3. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This should be compared with devices that have similar
functions enabled.
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Note
3. AGND tolerance includes the offsets of the local buffer in the enCoRe III block. Bandgap voltage is 1.3V ± 0.02V.
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Notes
4. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply.
5. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply.
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DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and –40°C < TA < 85°C, or 3.15V to 3.5V and –40°C < TA < 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Notes
6. The 50,000 cycle Flash endurance per block will only be guaranteed if the Flash is operating within one voltage range. Voltage ranges are 3.0V to 3.6V and 4.75V
to 5.25V.
7. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2
blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block
ever sees more than 50,000 cycles).
For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing.
Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.
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AC Electrical Characteristics
AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and –40°C < TA < 85°C, or 3.15V to 3.5V and –40°C < TA < 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 18. AC Chip-Level Specifications
F24M
Notes
7. 4.75V < Vdd < 5.25V.
8. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
9. 3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation
at 3.3V.
10. See the individual user module data sheets for information on maximum frequencies for user modules.
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90%
GPIO
Pin
Output
Voltage
10%
TRiseF TFallF
TRiseS TFallS
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Note
11. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
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AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and –40°C < TA < 85°C, or 3.15V to 3.5V and –40°C < TA < 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 25. AC Programming Specifications
Parameter Description Min Typ Max Unit Notes
TRSCLK Rise Time of SCLK 1 – 20 ns
TFSCLK Fall Time of SCLK 1 – 20 ns
TSSCLK Data Set up Time to Falling Edge of SCLK 40 – – ns
THSCLK Data Hold Time from Falling Edge of SCLK 40 – – ns
FSCLK Frequency of SCLK 0 – 8 MHz
TERASEB Flash Erase Time (Block) – 10 – ms
TWRITE Flash Block Write Time – 40 – ms
TDSCLK Data Out Delay from Falling Edge of SCLK – – 45 ns Vdd > 3.6
TDSCLK3 Data Out Delay from Falling Edge of SCLK – – 50 ns 3.15 < Vdd < 3.5
TERASEALL Flash Erase Time (Bulk) – 40 – ms Erase all blocks and
protection fields at once.
TPROGRAM_HOT Flash Block Erase + Flash Block Write Time – – 100 ms 0°C ≤ TJ ≤ 100°C
TPROGRAM_COLD Flash Block Erase + Flash Block Write Time – – 200 ms -40°C ≤ TJ ≤ 0°C
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AC I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and –40°C < TA < 85°C, or 3.15V to 3.5V and –40°C < TA < 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 26. AC Characteristics of the I2C SDA and SCL Pins for Vdd
Standard-Mode Fast-Mode
Parameter Description Unit Notes
Min Max Min Max
FSCLI2C SCL Clock Frequency 0 100 0 400 kHz
THDSTAI2C Hold Time (repeated) START Condition. After 4.0 – 0.6 – μs
this period, the first clock pulse is generated.
TLOWI2C LOW Period of the SCL Clock 4.7 – 1.3 – μs
THIGHI2C HIGH Period of the SCL Clock 4.0 – 0.6 – μs
TSUSTAI2C Setup Time for a Repeated START Condition 4.7 – 0.6 – μs
THDDATI2C Data Hold Time 0 – 0 – μs
TSUDATI2C Data Setup Time 250 – 100[12] – ns
TSUSTOI2C Setup Time for STOP Condition 4.0 – 0.6 – μs
TBUFI2C Bus Free Time Between a STOP and START 4.7 – 1.3 – μs
Condition
TSPI2C Pulse Width of spikes are suppressed by the – – 0 50 ns
input filter.
SDA
TLOWI2C TSPI2C
TSUDATI2C THDSTAI2C TBUFI2C
SCL
TSUSTAI2C TSUSTOI2C
S THDSTAI2C THDDATI2C THIGHI2C Sr P S
Note
12. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement TSUDATI2C ≥ 250 ns must then be met. This automatically is the
case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line trmax + TSUDATI2C = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
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Packaging Information
This section illustrates the package specification for the CY7C64215 enCoRe III, along with the thermal impedance for the package.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at
http://www.cypress.com/design/MR10161.
Package Diagrams
Figure 9. 56-Pin (8x8 mm) QFN-MLF (PUNCH)
001-12921 *A
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CY7C64215
001-53450 *A
51-85079 *D
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Thermal Impedance
Package Handling
Some IC packages require baking before they are soldered onto a PCB to remove moisture that may have been absorbed after leaving
the factory. A label on the packaging has details about actual bake temperature and the minimum bake time to remove this moisture.
The maximum bake time is the aggregate time that the devices are exposed to the bake temperature. Exceeding this exposure time
may degrade device reliability.
Notes
13. TJ = TA + POWER x θJA
14. To achieve the thermal impedance specified for the QFN package, the center thermal pad should be soldered to the PCB ground plane.
15. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5°C with Sn-Pb or 245 ± 5°C with Sn-Ag-Cu paste.
Refer to the solder manufacturer specifications.
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Ordering Information
Package Ordering Code Flash Size SRAM (Bytes) Temperature Range
56-Pin QFN-MLF (Punch) CY7C64215-56LFXC 16K 1K 0°C to 70°C
56-Pin QFN-MLF (Punch) CY7C64215-56LFXCT 16K 1K 0°C to 70°C
(Tape and Reel)
28-Pin SSOP CY7C64215-28PVXC 16K 1K 0°C to 70°C
28-Pin SSOP CY7C64215-28PVXCT 16K 1K 0°C to 70°C
(Tape and Reel)
56-Pin QFN (Sawn) Commercial CY7C64215-56LTXC 16K 1K 0°C to 70°C
56-Pin QFN (Sawn) Commercial CY7C64215-56LTXCT 16K 1K 0°C to 70°C
(Tape and Reel)
56-Pin QFN (Sawn) Industrial CY7C64215-56LTXI 16K 1K –40°C to 85°C
56-Pin QFN (Sawn) Industrial CY7C64215-56LTXIT 16K 1K –40°C to 85°C
(Tape and Reel)
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Products
Automotive cypress.com/go/automotive PSoC® Solutions
Clocks & Buffers cypress.com/go/clocks psoc.cypress.com/solutions
Interface cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5
Lighting & Power Control cypress.com/go/powerpsoc
cypress.com/go/plc
Memory cypress.com/go/memory
Optical & Image Sensing cypress.com/go/image
PSoC cypress.com/go/psoc
Touch Sensing cypress.com/go/touch
USB Controllers cypress.com/go/USB
Wireless/RF cypress.com/go/wireless
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a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
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