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CY7C64215

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100 views33 pages

CY7C64215

Uploaded by

rocky liu
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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CY7C64215

enCoRe™ III Full Speed USB Controller

Features
■ Powerful Harvard Architecture Processor ■ Additional System Resources
2
❐ M8C Processor Speeds to 24 MHz ❐ I C Slave, Master, and Multi-Master to 400 kHz
❐ Two 8x8 Multiply, 32-Bit Accumulate ❐ Watchdog and Sleep Timers
❐ 3.15 to 5.25V Operating Voltage ❐ User-Configurable Low Voltage Detection
❐ USB 2.0 USB-IF Certified. TID# 40000110 ❐ Integrated Supervisory Circuit
❐ Commercial Operating Temperature Range: 0°C to +70°C ❐ On-Chip Precision Voltage Reference
❐ Industrial Operating Temperature Range: –40°C to +85°C
■ Complete Development Tools
■ Advanced Peripherals (enCoRe™ III Blocks) ❐ Free Development Software (PSoC Designer™)
❐ 6 Analog enCoRe III Blocks provide: ❐ Full Featured, In-Circuit Emulator and Programmer
• Up to 14-Bit Incremental and Delta Sigma ADCs ❐ Full Speed Emulation
❐ Programmable Threshold Comparator ❐ Complex Breakpoint Structure
❐ Four Digital enCoRe III Blocks Provide: ❐ 128K Bytes Trace Memory
• 8-Bit and 16-Bit PWMs, Timers, and Counters
• I2C Master Block Diagram
• SPI Master or Slave
• Full Duplex UART
• CYFISNP and CYFISPI Modules to Talk to Cypress CYFI
Radio
■ Complex Peripherals by Combining Blocks
■ Full Speed USB (12 Mbps)
❐ Four Unidirectional Endpoints
❐ One Bidirectional Control Endpoint enCoRe III Core
❐ Dedicated 256 Byte Buffer
❐ No External Crystal Required
❐ Operational at 3.15V to 3.5V or 4.35V to 5.25V

■ Flexible On-Chip Memory


❐ 16K Flash Program Storage 50,000 Erase/Write Cycles
❐ 1K SRAM Data Storage
❐ In-System Serial Programming (ISSP)
❐ Partial Flash Updates
❐ Flexible Protection Modes
❐ EEPROM Emulation in Flash

■ Programmable Pin Configurations


❐ 25 mA Sink on all GPIO
❐ Pull Up, Pull Down, High Z, Strong, or Open Drain Drive
Modes on all GPIO
❐ Configurable Interrupt on all GPIO

■ Precision, Programmable Clocking


❐ Internal ±4% 24 and 48 MHz Oscillator with Support for
External Clock Oscillator
❐ Internal Oscillator for Watchdog and Sleep
❐ .25% Accuracy for USB with no External Components

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 38-08036 Rev. *E Revised February 1, 2010

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Contents
Features ............................................................................. 1 Pin Information ................................................................. 8
Block Diagram .................................................................. 1 56-Pin Part Pinout ....................................................... 8
Contents ............................................................................ 2 28-Pin Part Pinout ....................................................... 9
Applications ...................................................................... 3 Register Reference ......................................................... 10
enCoRe III Functional Overview ...................................... 3 Register Mapping Tables .......................................... 10
enCoRe III Core .......................................................... 3 Register Map Bank 0 Table: User Space .................. 11
The Digital System ...................................................... 3 Register Map Bank 1 Table: Configuration Space .... 12
The Analog System ..................................................... 4 Electrical Specifications ................................................ 13
Additional System Resources ..................................... 4 Absolute Maximum Ratings .......................................... 14
enCoRe III Device Characteristics .............................. 4 Operating Temperature .................................................. 14
Getting Started .................................................................. 5 DC Electrical Characteristics ..................................... 15
Development Kits ........................................................ 5 AC Electrical Characteristics ..................................... 22
Technical Training Modules ........................................ 5 Packaging Information ................................................... 28
Consultants ................................................................. 5 Package Diagrams .................................................... 28
Technical Support ....................................................... 5 Thermal Impedance .................................................. 30
Application Notes ........................................................ 5 Solder Reflow Peak Temperature ............................. 30
Development Tools .......................................................... 5 Package Handling ........................................................... 30
PSoC Designer Software Subsystems ........................ 5 Ordering Information ...................................................... 31
Hardware Tools ........................................................... 6 Document History Page ................................................. 32
Designing with User Modules ......................................... 6 Sales, Solutions, and Legal Information ...................... 33
Document Conventions ................................................... 7 Worldwide Sales and Design Support ....................... 33
Acronyms Used ........................................................... 7 Products .................................................................... 33
Units of Measure ......................................................... 7 PSoC® Solutions ...................................................... 33
Numeric Naming .......................................................... 7

Document Number: 38-08036 Rev. *E Page 2 of 33

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Applications The 24 MHz IMO is doubled to 48 MHz for use by the digital
system, if needed. The 48 MHz clock is required to clock the USB
■ PC HID devices block and must be enabled for communication. A low power 32
❐ Mouse (Optomechanical, Optical, Trackball) kHz ILO (internal low speed oscillator) is provided for the Sleep
❐ Keyboards
Timer and WDT. The clocks, together with programmable clock
dividers (System Resource), provide flexibility to integrate
❐ Joysticks
almost any timing requirement into enCoRe III. In USB systems,
■ Gaming the IMO self-tunes to ±0.25% accuracy for USB communication.
❐ Game Pads
The extended temperature range for the Industrial operating
❐ Console Keyboards
range (–40°C to +85°C) requires the use of an external clock
■ General Purpose oscillator, which is only available on the 56-pin QFN package.
❐ Barcode Scanners
enCoRe III GPIOs provide connection to the CPU, digital and
❐ POS Terminal
analog resources of the device. Each pin’s drive mode may be
❐ Consumer Electronics
selected from eight options, enabling great flexibility in external
❐ Toys interfacing. Every pin also has capability to generate a system
❐ Remote Controls interrupt on high level, low level, and change from last read.
❐ USB to Serial
The Digital System
enCoRe III Functional Overview The Digital System is composed of four digital enCoRe III blocks.
The enCoRe III is based on flexible PSoC architecture and is a Each block is an 8-bit resource that is used alone or combined
full featured, full speed (12 Mbps) USB part. Configurable with other blocks to form 8, 16, 24, and 32-bit peripherals, which
analog, digital, and interconnect circuitry enable a high level of are called user module references.
integration in a host of consumer, and communication applica- Figure 1. Digital System Block Diagram
tions.
Port 7 Port 5 Port 3 Port 1
This architecture enables the user to create customized Port 4 Port 2 Port 0
peripheral configurations that match the requirements of each
individual application. Additionally, a fast CPU, Flash program
memory, SRAM data memory, and configurable I/O are included Digital Clocks To System Bus To Analog
in both 28-pin SSOP and 56-pin QFN packages. From Core System
enCoRe III architecture, as illustrated in the “Block Diagram” on
page 1, is comprised of four main areas: enCoRe III Core, Digital
DIGITAL SYSTEM
System, Analog System, and System Resources including a full
Digital enCoRe III Block Array
speed USB port. Configurable global busing enables all the
device resources to combine into a complete custom system.
8 Row 0 4 8
Configuration

The enCoRe III CY7C64215 can have up to seven I/O ports that

Configuration
Row Output
Row Input

connect to the global digital and analog interconnects, providing 8


DBB00 DBB01 DCB02 DCB03
8
access to 4 digital blocks and 6 analog blocks.
4

enCoRe III Core


The enCoRe III Core is a powerful engine that supports a rich
feature set. The core includes a CPU, memory, clocks, and GIE[7:0] GlobalDigital GOE[7:0]
configurable GPIO (General Purpose I/O). GIO[7:0] Interconnect GOO[7:0]

The M8C CPU core is a powerful processor with speeds up to


24 MHz, providing a four MIPS 8-bit Harvard architecture micro-
processor. The CPU uses an interrupt controller with up to 20
vectors, to simplify programming of real-time embedded events. The following digital configurations can be built from the blocks:
Program execution is timed and protected using the included
■ PWMs, Timers, and Counters (8-bit and 16-bit)
Sleep and Watch Dog Timers (WDT).
Memory encompasses 16K of Flash for program storage, 1K of ■ UART 8-bit with selectable parity
SRAM for data storage, and up to 2K of EEPROM emulated ■ SPI master and slave
using the Flash. Program Flash uses four protection levels on
blocks of 64 bytes, enabling customized software IP protection. ■ I2C Master
enCoRe III incorporates flexible internal clock generators, ■ RF Interface: Interface to Cypress CYFI Radio
including a 24 MHz IMO (internal main oscillator) accurate to 8%
over temperature and voltage as well as an option for an external The digital blocks are connected to any GPIO through a series
clock oscillator. USB operation requires the OSC LOCK bit of the of global buses that can route any signal to any pin. The buses
USB_CR0 register to be set to obtain IMO accuracy to .25%. also enable signal multiplexing and performing logic operations.
This configurability frees your designs from the constraints of a
fixed peripheral controller.

Document Number: 38-08036 Rev. *E Page 3 of 33

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The Analog System The Analog Multiplexer System


The Analog System is composed of six configurable blocks, The Analog Mux Bus can connect to every GPIO pin in ports 0–5.
comprised of an opamp circuit enabling the creation of complex Pins which are connected to the bus individually or in any combi-
analog signal flows. Analog peripherals are very flexible and are nation. The bus also connects to the analog system for analysis
customized to support specific application requirements. with comparators and analog-to-digital converters. It is split into
enCoRe III analog function supports the Analog-to-digital two sections for simultaneous dual-channel processing. An
converters (with 6 to 14-bit resolution, selectable as Incremental, additional 8:1 analog input multiplexer provides a second path to
and Delta Sigma) and programmable threshold comparator). bring Port 0 pins to the analog array.
Analog blocks are arranged in two columns of three, with each Additional System Resources
column comprising one CT (Continuous Time - AC B00 or AC
B01) and two SC (Switched Capacitor - ASC10 and ASD20 or System Resources provide additional capability useful to
ASD11 and ASC21) blocks, as shown in Figure 2. complete systems. Additional resources include a multiplier,
decimator, low voltage detection, and power-on reset. Brief
Figure 2. Analog System Block Diagram statements describing the merits of each resource follow.
All IO
(Except Port 7) ■ Full Speed USB (12 Mbps) with five configurable endpoints and
256 bytes of RAM. No external components required except
P0[7] P0[6] two series resistors. Industrial temperature operating range for
USB requires an external clock oscillator.
P0[5] P0[4]
■ Two multiply accumulates (MACs) provide fast 8-bit multipliers
with 32-bit accumulate, to assist in both general math and
P0[3] P0[2]
digital filters.
P0[1] P0[0]
■ The decimator provides a custom hardware filter for digital
signal processing applications including the creation of Delta
AGNDIn RefIn
Mux Bus
Analog

P2[6]
Sigma ADCs.
P2[3]
■ Digital clock dividers provide three customizable clock
P2[4]
frequencies for use in applications. The clocks are routed to
P2[1]
P2[2]
both the digital and analog systems.
P2[0] ■ The I2C module provides 100 and 400 kHz communication over
two wires. Slave, master, and multi-master modes are all
supported.
■ Low Voltage Detection (LVD) interrupts can signal the appli-
cation of falling voltage levels, while the advanced POR (Power
On Reset) circuit eliminates the need for a system supervisor.

enCoRe III Device Characteristics


ACI0[1:0] ACI1[1:0] enCoRe III devices have four digital blocks and six analog
Array Input blocks. The following table lists the resources available for
Configuration specific enCoRe III devices.

Table 1. enCoRe III Device Characteristics


Columns
Outputs
Analog

Analog

Analog

Analog

Block
Blocks

Blocks
Digital

Digital

Digital

Inputs

SRAM

ACB00 ACB01
Rows

Flash
Size

Size
Array Part
I/O

Number
ASC10 ASD11

CY7C64215 up to 1 4 22 2 2 6 1K 16K
ASD20 ASC21 28 Pin 22
CY7C64215 up to 1 4 48 2 2 6 1K 16K
56 Pin 50

Analog Reference

Interface to RefHi Reference AGNDIn


Digital System Ref Lo Generators Ref In
AGND Bandgap

M8C Interface (Address Bus, Data Bus, Etc.)

Document Number: 38-08036 Rev. *E Page 4 of 33

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Getting Started Development Tools


The quickest path to understanding the enCoRe III silicon is by PSoC Designer is a Microsoft® Windows® based, integrated
reading this data sheet and using the PSoC Designer Integrated development environment for enCoRe III. The PSoC Designer
Development Environment (IDE). This data sheet is an overview IDE and application runs on Windows XP or Vista.
of the enCoRe V integrated circuit and presents specific pin, PSoC Designer helps the customer to select an operating config-
register, and electrical specifications. For in-depth information, uration for the enCoRe III, write application code that uses the
along with detailed programming information, reference the enCoRe III, and debug the application. This system provides
PSoC Programmable System-on-Chip Technical Reference design database management by project, an integrated
Manual, which can be found on http://www.cypress.com/psoc. debugger with In-Circuit Emulator, in-system programming
For up-to-date Ordering, Packaging, and Electrical Specification support, and the CYASM macro assembler for the CPUs. PSoC
information, reference the latest enCoRe V device data sheets Designer also supports a high-level C language compiler
on the web at http://www.cypress.com/go/usb. developed specifically for the devices in the family.

Development Kits PSoC Designer Software Subsystems


Development Kits are available online from Cypress at Device Editor
www.cypress.com/shop and through a growing number of
regional and global distributors, which include Arrow, Avnet, The Device Editor subsystem enables the user to select different
Digi-Key, Farnell, Future Electronics, and Newark. Under onboard analog and digital components called user modules
Product Categories, click USB (Universal Serial Bus) to view a using the enCoRe III blocks. Examples of user modules are
current list of available items. ADCs, SPIM, UART, and PWMs.
The device editor also supports easy development of multiple
Technical Training Modules configurations and dynamic reconfiguration. Dynamic configu-
Free technical training (on demand, webinars, and workshops) ration enables changing configurations at run time.
is available online at www.cypress.com/training. The training PSoC Designer sets up power on initialization tables for selected
covers a wide variety of topics and skill levels to assist you in enCoRe III block configurations and creates source code for an
your designs. application framework. The framework contains software to
operate the selected components and, if the project uses more
Consultants than one operating configuration, contains routines to switch
between different sets of enCoRe III block configurations at run
Certified USB consultants offer everything from technical assis- time. PSoC Designer can print out a configuration sheet for a
tance to completed PSoC designs. To contact or become a PSoC given project configuration for use during application
Consultant go to www.cypress.com/cypros. programming in conjunction with the Device Data Sheet. Once
the framework is generated, the user can add appli-
Technical Support
cation-specific code to flesh out the framework. It is also possible
For assistance with technical issues, search KnowledgeBase to change the selected components and regenerate the
articles and forums at www.cypress.com/support. If you cannot framework.
find an answer to your question, call technical support at
1-800-541-4736. Application Editor
In the Application Editor you can edit your C language and
Application Notes Assembly language source code. You can also assemble,
Application notes are an excellent introduction to the wide variety compile, link, and build.
of possible PSoC designs. They are located here:
www.cypress.com/psoc. Select Application Notes under the Assembler. The macro assembler enables the assembly code
Documentation tab. to merge seamlessly with C code. The link libraries automatically
use absolute addressing or is compiled in relative mode, and
linked with other software modules to get absolute addressing.
C Language Compiler. A C language compiler is available that
supports the enCoRe III family of devices. Even if you have never
worked in the C language before, the product quickly enables
you to create complete C programs for the enCoRe III devices.
The embedded, optimizing C compiler provides all the features
of C tailored to the enCoRe III architecture. It comes complete
with embedded libraries providing port and bus operations,
standard keypad and display support, and extended math
functionality.

Document Number: 38-08036 Rev. *E Page 5 of 33

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Debugger The user module library contains the following digital and analog
The PSoC Designer Debugger subsystem provides hardware module designs:
in-circuit emulation, enabling the designer to test the program in ■ Analog Blocks
a physical system while providing an internal view of the enCoRe ❐ Incremental ADC (ADCINC)
III device. Debugger commands enable the designer to read and
❐ Delta Sigma ADC (DelSig)
program and read and write data memory, read and write I/O
❐ Programmable Threshold Comparator (CMPPRG)
registers, read and write CPU registers, set and clear break-
points, and provide program run, halt, and step control. The ■ Digital Blocks
debugger also enables the designer to create a trace buffer of ❐ Counters: 8-bit and 16-bit (Counter8 and Counter 16)
registers and memory locations of interest. ❐ PWMs: 8-bit and 16-bit (PWM8 and PWM16)

Online Help System ❐ Timers: 8-bit and 16-bit (Timer8 and Timer 16)
2 2
❐ I C Master (I CM)
The online help system displays online, context-sensitive help
❐ SPI Master (SPIM)
for the user. Designed for procedural and quick reference, each
❐ SPI Slave (SPIS)
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online ❐ Full Duplex UART (UART)
Support Forum to aid the designer in getting started. ❐ RF (CYFISNP and CYFISPI)

■ System Resources
Hardware Tools
❐ Protocols:
In-Circuit Emulator • USBFS
A low cost, high functionality ICE Cube is available for devel- • I2C Bootheader (Boothdr I2C)
opment support. This hardware has the capability to program • USB Bootheader (BoothdrUSBFS)
single devices. • USBUART
The emulator consists of a base unit that connects to the PC by ❐ Digital System Resources
way of a USB port. The base unit is universal which operates with • E2PROM
all enCoRe III devices. • LCD
• LED
Designing with User Modules • 7-segment LED (LED7SEG)
The development process for the enCoRe III device differs from • Shadow Registers (SHADOWREG)
that of a traditional fixed-function microprocessor. The configu- • Sleep Timer
rable analog and digital hardware blocks give the enCoRe III
Each user module establishes the basic register settings that
architecture a unique flexibility that pays dividends in managing
implement the selected function. It also provides parameters that
specification change during development and by lowering
enable you to tailor its precise configuration to your particular
inventory costs. These configurable resources, called enCoRe
application. For example, a Pulse Width Modulator User Module
III Blocks, have the ability to implement a wide variety of
configures one or more digital PSoC blocks, one for each 8 bits
user-selectable functions. Each block has several registers that
of resolution. The user module parameters permit the designer
determine its function and connectivity to other blocks, multi-
to establish the pulse width and duty cycle. User modules also
plexers, buses and to the I/O pins. Iterative development cycles
provide tested software to cut development time. The user
permit you to adapt the hardware and software. This substan-
module application programming interface (API) provides
tially lowers the risk of having to select a different part to meet
high-level functions to control and respond to hardware events
the final design requirements.
at run-time. The API also provides optional interrupt service
To speed the development process, the PSoC Designer routines that is adapted as needed.
Integrated Development Environment (IDE) provides a library of
The API functions are documented in user module data sheets
pre-built, pre-tested hardware peripheral functions, called “User
that are viewed directly in the PSoC Designer IDE. These data
Modules.” User modules make selecting and implementing
sheets explain the internal operation of the user module and
peripheral devices simple, and come in analog, digital, and
provide performance specifications. Each data sheet describes
mixed signal varieties.
the use of each user module parameter and documents the
setting of each register controlled by the user module.

Document Number: 38-08036 Rev. *E Page 6 of 33

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The development process starts when you open a new project Acronym Description
and bring up the Device Editor/Chip Layout View, a graphical
user interface (GUI) for configuring the hardware. You pick the CT continuous time
user modules you need for your project and map them onto the ECO external crystal oscillator
PSoC blocks with point-and-click simplicity. Next, you build
EEPROM electrically erasable programmable read-only
signal chains by interconnecting user modules to each other and
memory
the I/O pins. At this stage, you also configure the clock source
connections and enter parameter values directly or by selecting FSR full scale range
values from drop-down menus. When you are ready to test the GPIO general purpose I/O
hardware configuration or move on to developing code for the
project, you perform the “Generate Application” step. This GUI graphical user interface
causes PSoC Designer to generate source code that automati- HBM human body model
cally configures the device to your specification and provides the
LSb least-significant bit
high-level user module API functions.
LVD low voltage detect
The next step is to write your main program, and any
sub-routines using PSoC Designer’s Application Editor MSb most-significant bit
subsystem. The Application Editor includes a Project Manager PC program counter
that enables you to open the project source code files (including
all generated code files) from a hierarchal view. The source code PLL phase-locked loop
editor provides syntax coloring and advanced edit features for POR power on reset
both C and assembly language. File search capabilities include
PPOR precision power on reset
simple string searches and recursive “grep-style” patterns. A
single mouse click invokes the Build Manager. It employs a PSoC® Programmable System-on-Chip™
professional-strength “makefile” system to automatically analyze PWM pulse width modulator
all file dependencies and run the compiler and assembler as
necessary. Project level options control optimization strategies SC switched capacitor
used by the compiler and linker. Syntax errors are displayed in a SRAM static random access memory
console window. Double clicking the error message takes you
ICE in-circuit emulator
directly to the offending line of source code. When all is correct,
the linker builds a HEX file image suitable for programming. ILO internal low speed oscillator
The last step in the development process takes place inside the IMO internal main oscillator
PSoC Designer’s Debugger subsystem. The Debugger I/O input/output
downloads the HEX image to the In-Circuit Emulator (ICE CUBE)
where it runs at full speed. Debugger capabilities rival those of IPOR imprecise power on reset
systems costing many times more. In addition to traditional
single-step, run-to-breakpoint and watch-variable features, the Units of Measure
Debugger provides a large trace buffer and enables you define
A units of measure table is located in the Electrical Specifications
complex breakpoint events that include monitoring address and
section. Table 5 on page 13 lists all the abbreviations used to
data bus values, memory locations, and external signals.
measure the enCoRe III devices.
Document Conventions Numeric Naming
Acronyms Used Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
The following table lists the acronyms that are used in this ‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’
document. prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (For example, 01010100b’ or
Acronym Description ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimal.
AC alternating current
ADC analog-to-digital converter
API application programming interface
CPU central processing unit

Document Number: 38-08036 Rev. *E Page 7 of 33

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Pin Information
56-Pin Part Pinout
The CY7C64215 enCoRe III device is available in a 56-pin package which is listed and illustrated in the following table. Every port pin
(labeled “P”) is capable of Digital I/O. However, Vss and Vdd are not capable of Digital I/O.

Table 2. 56-Pin Part Pinout (QFN-MLF SAWN)[1]


Pin Type Figure 3. CY7C64215 56-Pin enCoRe III Device
Name Description
No. Digital Analog

P0[3], A, IO, M
P0[5], A, IO, M
1 I/O I, M P2[3] Direct Switched Capacitor Block Input.

P0[1], A, I, M

P0[7], A, I, M

P0[6], A, I, M
P0[4], A, I, M
P0[2], A, I, M
P0[0], A, I, M
2 I/O I, M P2[1] Direct Switched Capacitor Block Input.

P2[5], M
P2[7], M

P2[6], M
P2[4], M
3 I/O M P4[7]

Vdd
Vss
4 I/O M P4[5]
5 I/O M P4[3]
6 I/O M P4[1]

56

54
53
52

45
44
55

50

47
46
51

48

43
49
7 I/O M P3[7] A , I , M , P2[3] 1 42 P2[2] , A , I , M
8 I/O M P3[5] A , I , M , P2[1] 2 41 P2[0] , A , I , M
9 I/O M P3[3] M , P4[7] 3 40 P4[6] , M
M , P4[5] 4 39 P4[4] , M
10 I/O M P3[1]
M , P4[3] 5 38 P4[2] , M
11 I/O M P5[7] M , P4[1] 6 37 P4[0] , M
12 I/O M P5[5] M , P3[7] 7 QFN-MLF 36 P3[6] , M
13 I/O M P5[3] M , P3[5] 8 35 P3[4] , M
( Top View)
14 I/O M P5[1] M , P3[3] 9 34 P3[2] , M
15 I/O M P1[7] I2C Serial Clock (SCL). M , P3[1] 10 33 P3[0] , M
16 I/O M P1[5] I2C Serial Data (SDA). M , P5[7] 11 32 P5[6] , M
17 I/O M P1[3] M , P5[5] 12 31 P5[4] , M
18 I/O M P1[1] I2C Serial Clock (SCL), ISSP-SCLK. M , P5[3] 13 30 P5[2] , M
M , P5[1] 14 29 P5[0] , M
19 Power Vss Ground Connection.
15
16
17
18
19
20
21
22
23
24
25
26
27
28
20 USB D+
21 USB D-
Vdd
Vss
D+
D-
P1[3]
P1[1]
P1[7]
P1[5]

P7[7]
P7[0]
P1[0]
P1[2]
P1[4]
P1[6]
22 Power Vdd Supply Voltage.
M,
M, I2C SCL,
M, I2C SCL,
M, I2C SDA,

M, I2C SDA,
M,
M,
M,
23 I/O P7[7]
24 I/O P7[0]
25 I/O M P1[0] I2C Serial Data (SDA), ISSP-SDATA.
26 I/O M P1[2]
27 I/O M P1[4] Optional External Clock Input EXTCLK.
28 I/O M P1[6]
29 I/O M P5[0] Pin Type
Name Description
30 I/O M P5[2] No. Digital Analog
31 I/O M P5[4] 44 I/O M P2[6] External Voltage Reference (VREF) Input.
32 I/O M P5[6] 45 I/O I, M P0[0] Analog Column Mux Input.
33 I/O M P3[0] 46 I/O I, M P0[2] Analog Column Mux Input and Column Output.
34 I/O M P3[2] 47 I/O I, M P0[4] Analog Column Mux Input and Column Output.
35 I/O M P3[4] 48 I/O I, M P0[6] Analog Column Mux Input.
36 I/O M P3[6] 49 Power Vdd Supply Voltage.
37 I/O M P4[0] 50 Power Vss Ground Connection.
38 I/O M P4[2] 51 I/O I, M P0[7] Analog Column Mux Input.
39 I/O M P4[4] 52 I/O I/O, M P0[5] Analog Column Mux Input and Column Output
40 I/O M P4[6] 53 I/O I/O, M P0[3] Analog Column Mux Input and Column Output.
41 I/O I, M P2[0] Direct Switched Capacitor Block Input. 54 I/O I, M P0[1] Analog Column Mux Input.
42 I/O I, M P2[2] Direct Switched Capacitor Block Input. 55 I/O M P2[7]
43 I/O M P2[4] External Analog Ground (AGND) Input. 56 I/O M P2[5]

LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.

Note
1. The center pad on the QFN-MLF package should be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground,
it should be electrically floated and not connected to any other signal.

Document Number: 38-08036 Rev. *E Page 8 of 33

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CY7C64215

28-Pin Part Pinout


The CY7C64215 enCoRe III device is available in a 28-pin package which is listed and illustrated in the following table. Every port pin
(labeled with a “P”) is capable of Digital I/O. However, Vss and Vdd are not capable of Digital I/O.

Table 3. 28-Pin Part Pinout (SSOP)


Pin Type Figure 4. CY7C64215 28-Pin enCoRe III Device
Name Description
No. Digital Analog
1 Power GND Ground Connection.
2 I/O I, M P0[7] Analog Column Mux Input. Vss 1 28 Vdd
3 I/O I/O,M P0[5] Analog Column Mux Input and Column Output. AI,P0[7] 2 27 P0[6],AI
4 I/O I/O,M P0[3] Analog Column Mux Input and Column Output. AIO,P0[5] 3 26 P0[4],AI
5 I/O I,M P0[1] Analog Column Mux Input. AIO,P0[3] 4 25 P0[2],AI
6 I/O M P2[5] AI,P0[1] 5 24 P0[0],AI
7 I/O M P2[3] Direct Switched Capacitor Block Input. P2[5] 6 23 P2[4]
8 I/O M P2[1] Direct Switched Capacitor Block Input. AI,P2[3] 7 22 P2[2],AI
SSOP
9 I/O M P1[7] I2C Serial Clock (SCL). AI,P2[1] 8 21 P2[0],AI
10 I/O M P1[5] I2C Serial Data (SDA). I2CSCL,P1[7] 9 20 P1[6]
11 I/O M P1[3] I2CSDA,P1[5] 10 19 P1[4]
12 I/O M P1[1] I2C Serial Clock (SCL), ISSP-SCLK. P1[3] 11 18 P1[2]
13 Power GND Ground Connection. I2CSCL, P1[1] 12 17 P1[0],I2CSDA
14 USB D+ Vss 13 16 Vdd
15 USB D- D+ 14 15 D-
16 Power Vdd Supply Voltage.
17 I/O M P1[0] I2C Serial Data (SDA), ISSP-SDATA.
18 I/O M P1[2]
19 I/O M P1[4]
20 I/O M P1[6]
21 I/O M P2[0] Direct Switched Capacitor Block Input.
22 I/O M P2[2] Direct Switched Capacitor Block Input.
23 I/O M P2[4] External Analog Ground (AGND) Input.
24 I/O M P0[0] Analog Column Mux Input.
25 I/O M P0[2] Analog Column Mux Input and Column Output.
26 I/O M P0[4] Analog Column Mux Input and Column Output.
27 I/O M P0[6] Analog Column Mux Input.
28 Power Vdd Supply Voltage.

LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.

Document Number: 38-08036 Rev. *E Page 9 of 33

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CY7C64215

Register Reference Register Mapping Tables


The enCoRe III device has a total register address space of 512
The register conventions specific to this section are listed in the bytes. The register space is referred to as I/O space and is
following table. divided into two banks. The XOI bit in the Flag register (CPU_F)
determines which bank the user is currently in. When the XOI bit
Table 4. Register Conventions is set the user is in Bank 1.
Convention Description Note In the following register mapping tables, blank fields are
R Read register or bit(s) Reserved and should not be accessed.

W Write register or bit(s)


L Logical register or bit(s)
C Clearable register or bit(s)
# Access is bit specific

Document Number: 38-08036 Rev. *E Page 10 of 33

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Register Map Bank 0 Table: User Space


Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access
PRT0DR 00 RW PMA0_DR 40 RW ASC10CR0 80 RW C0
PRT0IE 01 RW PMA1_DR 41 RW ASC10CR1 81 RW C1
PRT0GS 02 RW PMA2_DR 42 RW ASC10CR2 82 RW C2
PRT0DM2 03 RW PMA3_DR 43 RW ASC10CR3 83 RW C3
PRT1DR 04 RW PMA4_DR 44 RW ASD11CR0 84 RW C4
PRT1IE 05 RW PMA5_DR 45 RW ASD11CR1 85 RW C5
PRT1GS 06 RW PMA6_DR 46 RW ASD11CR2 86 RW C6
PRT1DM2 07 RW PMA7_DR 47 RW ASD11CR3 87 RW C7
PRT2DR 08 RW USB_SOF0 48 R 88 C8
PRT2IE 09 RW USB_SOF1 49 R 89 C9
PRT2GS 0A RW USB_CR0 4A RW 8A CA
PRT2DM2 0B RW USBIO_CR0 4B # 8B CB
PRT3DR 0C RW USBIO_CR1 4C RW 8C CC
PRT3IE 0D RW 4D 8D CD
PRT3GS 0E RW EP1_CNT1 4E # 8E CE
PRT3DM2 0F RW EP1_CNT 4F RW 8F CF
PRT4DR 10 RW EP2_CNT1 50 # ASD20CR0 90 RW CUR_PP D0 RW
PRT4IE 11 RW EP2_CNT 51 RW ASD20CR1 91 RW STK_PP D1 RW
PRT4GS 12 RW EP3_CNT1 52 # ASD20CR2 92 RW D2
PRT4DM2 13 RW EP3_CNT 53 RW ASD20CR3 93 RW IDX_PP D3 RW
PRT5DR 14 RW EP4_CNT1 54 # ASC21CR0 94 RW MVR_PP D4 RW
PRT5IE 15 RW EP4_CNT 55 RW ASC21CR1 95 RW MVW_PP D5 RW
PRT5GS 16 RW EP0_CR 56 # ASC21CR2 96 RW I2C_CFG D6 RW
PRT5DM2 17 RW EP0_CNT 57 # ASC21CR3 97 RW I2C_SCR D7 #
18 EP0_DR0 58 RW 98 I2C_DR D8 RW
19 EP0_DR1 59 RW 99 I2C_MSCR D9 #
1A EP0_DR2 5A RW 9A INT_CLR0 DA RW
1B EP0_DR3 5B RW 9B INT_CLR1 DB RW
PRT7DR 1C RW EP0_DR4 5C RW 9C INT_CLR2 DC RW
PRT7IE 1D RW EP0_DR5 5D RW 9D INT_CLR3 DD RW
PRT7GS 1E RW EP0_DR6 5E RW 9E INT_MSK3 DE RW
PRT7DM2 1F RW EP0_DR7 5F RW 9F INT_MSK2 DF RW
DBB00DR0 20 # AMX_IN 60 RW A0 INT_MSK0 E0 RW
DBB00DR1 21 W AMUXCFG 61 RW A1 INT_MSK1 E1 RW
DBB00DR2 22 RW 62 A2 INT_VC E2 RC
DBB00CR0 23 # ARF_CR 63 RW A3 RES_WDT E3 W
DBB01DR0 24 # CMP_CR0 64 # A4 DEC_DH E4 RC
DBB01DR1 25 W ASY_CR 65 # A5 DEC_DL E5 RC
DBB01DR2 26 RW CMP_CR1 66 RW A6 DEC_CR0 E6 RW
DBB01CR0 27 # 67 A7 DEC_CR1 E7 RW
DCB02DR0 28 # 68 MUL1_X A8 W MUL0_X E8 W
DCB02DR1 29 W 69 MUL1_Y A9 W MUL0_Y E9 W
DCB02DR2 2A RW 6A MUL1_DH AA R MUL0_DH EA R
DCB02CR0 2B # 6B MUL1_DL AB R MUL0_DL EB R
DCB03DR0 2C # TMP_DR0 6C RW ACC1_DR1 AC RW ACC0_DR1 EC RW
DCB03DR1 2D W TMP_DR1 6D RW ACC1_DR0 AD RW ACC0_DR0 ED RW
DCB03DR2 2E RW TMP_DR2 6E RW ACC1_DR3 AE RW ACC0_DR3 EE RW
DCB03CR0 2F # TMP_DR3 6F RW ACC1_DR2 AF RW ACC0_DR2 EF RW
30 ACB00CR3 70 RW RDI0RI B0 RW F0
31 ACB00CR0 71 RW RDI0SYN B1 RW F1
32 ACB00CR1 72 RW RDI0IS B2 RW F2
33 ACB00CR2 73 RW RDI0LT0 B3 RW F3
34 ACB01CR3 74 RW RDI0LT1 B4 RW F4
35 ACB01CR0 75 RW RDI0RO0 B5 RW F5
36 ACB01CR1 76 RW RDI0RO1 B6 RW F6
37 ACB01CR2 77 RW B7 CPU_F F7 RL
38 78 B8 F8
39 79 B9 F9
3A 7A BA FA
3B 7B BB FB
3C 7C BC FC
3D 7D BD DAC_D FD RW
3E 7E BE CPU_SCR1 FE #
3F 7F BF CPU_SCR0 FF #
Blank fields are Reserved and should not be accessed. # Access is bit specific.

Document Number: 38-08036 Rev. *E Page 11 of 33

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Register Map Bank 1 Table: Configuration Space


Addr Addr Addr Addr
Name Access Name Access Name Access Name Access
(1,Hex) (1,Hex) (1,Hex) (1,Hex)
PRT0DM0 00 RW PMA0_WA 40 RW ASC10CR0 80 RW USBIO_CR2 C0 RW
PRT0DM1 01 RW PMA1_WA 41 RW ASC10CR1 81 RW USB_CR1 C1 #
PRT0IC0 02 RW PMA2_WA 42 RW ASC10CR2 82 RW
PRT0IC1 03 RW PMA3_WA 43 RW ASC10CR3 83 RW
PRT1DM0 04 RW PMA4_WA 44 RW ASD11CR0 84 RW EP1_CR0 C4 #
PRT1DM1 05 RW PMA5_WA 45 RW ASD11CR1 85 RW EP2_CR0 C5 #
PRT1IC0 06 RW PMA6_WA 46 RW ASD11CR2 86 RW EP3_CR0 C6 #
PRT1IC1 07 RW PMA7_WA 47 RW ASD11CR3 87 RW EP4_CR0 C7 #
PRT2DM0 08 RW 48 88 C8
PRT2DM1 09 RW 49 89 C9
PRT2IC0 0A RW 4A 8A CA
PRT2IC1 0B RW 4B 8B CB
PRT3DM0 0C RW 4C 8C CC
PRT3DM1 0D RW 4D 8D CD
PRT3IC0 0E RW 4E 8E CE
PRT3IC1 0F RW 4F 8F CF
PRT4DM0 10 RW PMA0_RA 50 RW 90 GDI_O_IN D0 RW
PRT4DM1 11 RW PMA1_RA 51 RW ASD20CR1 91 RW GDI_E_IN D1 RW
PRT4IC0 12 RW PMA2_RA 52 RW ASD20CR2 92 RW GDI_O_OU D2 RW
PRT4IC1 13 RW PMA3_RA 53 RW ASD20CR3 93 RW GDI_E_OU D3 RW
PRT5DM0 14 RW PMA4_RA 54 RW ASC21CR0 94 RW D4
PRT5DM1 15 RW PMA5_RA 55 RW ASC21CR1 95 RW D5
PRT5IC0 16 RW PMA6_RA 56 RW ASC21CR2 96 RW D6
PRT5IC1 17 RW PMA7_RA 57 RW ASC21CR3 97 RW D7
18 58 98 MUX_CR0 D8 RW
19 59 99 MUX_CR1 D9 RW
1A 5A 9A MUX_CR2 DA RW
1B 5B 9B MUX_CR3 DB RW
PRT7DM0 1C RW 5C 9C DC
PRT7DM1 1D RW 5D 9D OSC_GO_EN DD RW
PRT7IC0 1E RW 5E 9E OSC_CR4 DE RW
PRT7IC1 1F RW 5F 9F OSC_CR3 DF RW
DBB00FN 20 RW CLK_CR0 60 RW A0 OSC_CR0 E0 RW
DBB00IN 21 RW CLK_CR1 61 RW A1 OSC_CR1 E1 RW
DBB00OU 22 RW ABF_CR0 62 RW A2 OSC_CR2 E2 RW
23 AMD_CR0 63 RW A3 VLT_CR E3 RW
DBB01FN 24 RW CMP_GO_EN 64 RW A4 VLT_CMP E4 R
DBB01IN 25 RW 65 RW A5 E5
DBB01OU 26 RW AMD_CR1 66 RW A6 E6
27 ALT_CR0 67 RW A7 E7
DCB02FN 28 RW 68 A8 IMO_TR E8 W
DCB02IN 29 RW 69 A9 ILO_TR E9 W
DCB02OU 2A RW 6A AA BDG_TR EA RW
2B 6B AB ECO_TR EB W
DCB03FN 2C RW TMP_DR0 6C RW AC MUX_CR4 EC RW
DCB03IN 2D RW TMP_DR1 6D RW AD MUX_CR5 ED RW
DCB03OU 2E RW TMP_DR2 6E RW AE EE
2F TMP_DR3 6F RW AF EF
30 ACB00CR3 70 RW RDI0RI B0 RW F0
31 ACB00CR0 71 RW RDI0SYN B1 RW F1
32 ACB00CR1 72 RW RDI0IS B2 RW F2
33 ACB00CR2 73 RW RDI0LT0 B3 RW F3
34 ACB01CR3 74 RW RDI0LT1 B4 RW F4
35 ACB01CR0 75 RW RDI0RO0 B5 RW F5
36 ACB01CR1 76 RW RDI0RO1 B6 RW F6
37 ACB01CR2 77 RW B7 CPU_F F7 RL
38 78 B8 F8
39 79 B9 F9
3A 7A BA FA
3B 7B BB FB
3C 7C BC FC
3D 7D BD DAC_CR FD RW
3E 7E BE CPU_SCR1 FE #
3F 7F BF CPU_SCR0 FF #
Blank fields are Reserved and should not be accessed. # Access is bit specific.

Document Number: 38-08036 Rev. *E Page 12 of 33

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Electrical Specifications
This section presents the DC and AC electrical specifications of the CY7C64215 enCoRe III. For the most up to date electrical
specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/go/usb.
Specifications are valid for –40°C < TA < 85°C and TJ < 100°C, except where noted. Specifications for devices running at greater than
12 MHz are valid for –40°C < TA < 70°C and TJ < 82°C.
Figure 5. Voltage versus CPU Frequency

5.25

Valid Operating Region

4.75
Vdd Voltage (V)

4.35
[2]
Valid Operating Region

3.50

Valid Operating Region

3.15

93 kHz 12 MHz 24 MHz

CPU Frequency

The following table lists the units of measure that are used in this section.

Table 5. Units of Measure


Symbol Unit of Measure Symbol Unit of Measure
°C degree Celsius μW microwatts
dB decibels mA milliampere
fF femto farad ms millisecond
Hz hertz mV millivolts
KB 1024 bytes nA nanoampere
Kbit 1024 bits ns nanosecond
kHz kilohertz nV nanovolts
kΩ kilohm Ω ohm
MHz megahertz pA picoampere
MΩ megaohm pF picofarad
μA microampere pp peak-to-peak
μF microfarad ppm parts per million
μH microhenry ps picosecond
μs microsecond sps samples per second
μV microvolts s sigma: one standard deviation
μVrms microvolts root-mean-square V volts

Note
2. This is a valid operating region for the CPU, but USB hardware is non-functional in the voltage range from 3.50V – 4.35V.

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Absolute Maximum Ratings


Table 6. Absolute Maximum Ratings

Parameter Description Min Typ Max Unit Notes


TSTG Storage Temperature –55 – +100 °C Higher storage temperatures
reduces data retention time.
TA Ambient Temperature with Power Applied 0 – +70 °C
Vdd Supply Voltage on Vdd Relative to Vss –0.5 – +6.0 V
VIO DC Input Voltage Vss – 0.5 – Vdd + 0.5 V
VIO2 DC Voltage Applied to Tri-state Vss – 0.5 – Vdd + 0.5 V
IMIO Maximum Current into any Port Pin –25 – +50 mA
IMAIO Maximum Current into any Port Pin –50 – +50 mA
Configured as Analog Driver
ESD Electro Static Discharge Voltage 2000 – – V Human Body Model ESD.
LU Latch Up Current – – 200 mA

Operating Temperature
Table 7. Operating Temperature

Parameter Description Min Typ Max Unit Notes


TAC Commercial Ambient Temperature 0 – +70 °C
TAI Industrial Ambient Temperature –40 – +85 °C USB operation requires the
use of an external clock
oscillator and the 56-pin
QFN package.
TJ Junction Temperature –40 – +100 °C The temperature rise from
ambient to junction is
package specific. See
“Thermal Impedance” on
page 30. The user must limit
the power consumption to
comply with this
requirement.

Document Number: 38-08036 Rev. *E Page 14 of 33

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DC Electrical Characteristics
DC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and –40°C < TA < 85°C, or 3.15V to 3.5V and –40°C < TA < 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 8. DC Chip-Level Specifications

Parameter Description Min Typ Max Unit Notes


Vdd Supply Voltage 3.0 – 5.25 V See DC POR and LVD specifications,
Table 16 on page 20. USB hardware is not
functional when Vdd is between 3.5V to
4.35V.
IDD5 Supply Current, IMO = 24 MHz (5V) – 14 27 mA Conditions are Vdd = 5.0V, TA = 25°C,
CPU = 3 MHz, SYSCLK doubler disabled,
VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 =
93.75 kHz, analog power = off.
IDD3 Supply Current, IMO = 24 MHz (3.3V) – 8 14 mA Conditions are Vdd = 3.3V, TA = 25°C,
CPU = 3 MHz, SYSCLK doubler disabled,
VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 =
0.367 kHz, analog power = off.
ISB Sleep (Mode) Current with POR, LVD, Sleep – 3 6.5 μA Conditions are with internal slow speed
Timer, and WDT.[3] oscillator, Vdd = 3.3V, 0°C < TA < 55°C,
analog power = off.
ISBH Sleep (Mode) Current with POR, LVD, Sleep – 4 25 μA Conditions are with internal slow speed
Timer, and WDT at high temperature.[3] oscillator, Vdd = 3.3V, 55°C < TA < 70°C,
analog power = off.
DC General Purpose I/O Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and –40°C < TA < 85°C, or 3.15V to 3.5V and –40°C < TA < 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 9. DC GPIO Specifications
Parameter Description Min Typ Max Unit Notes
RPU Pull Up Resistor 4 5.6 8 kΩ
RPD Pull down Resistor 4 5.6 8 kΩ
VOH High Output Level Vdd – 1.0 – – V IOH = 10 mA, Vdd = 4.75 to 5.25V (8 total
loads, 4 on even port pins (for example,
P0[2], P1[4]), 4 on odd port pins (for
example, P0[3], P1[5])). 80 mA maximum
combined IOH budget.
VOL Low Output Level – – 0.75 V IOL = 25 mA, Vdd = 4.75 to 5.25V (8 total
loads, 4 on even port pins (for example,
P0[2], P1[4]), 4 on odd port pins (for
example, P0[3], P1[5])). 150 mA
maximum combined IOL budget.
IOH High Level Source Current 10 – – mA
IOL Low Level Sink Current 25 – – mA
VIL Input Low Level – – 0.8 V Vdd = 3.15 to 5.25.
VIH Input High Level 2.1 – V Vdd = 3.15 to 5.25.

Note
3. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This should be compared with devices that have similar
functions enabled.

Document Number: 38-08036 Rev. *E Page 15 of 33

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Table 9. DC GPIO Specifications (continued)


VH Input Hysteresis – 60 – mV
IIL Input Leakage (Absolute Value) – 1 – nA Gross tested to 1 μA.
CIN Capacitive Load on Pins as Input – 3.5 10 pF Package and pin dependent. Temp =
25°C.
COUT Capacitive Load on Pins as Output – 3.5 10 pF Package and pin dependent. Temp =
25°C.

DC Full Speed USB Specifications


The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges when the IMO is
selected as system clock: 4.75V to 5.25V and 0°C < TA < 70°C, or 3.15V to 3.5V and 0°C < TA < 70°C, respectively.
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges when an external
clock is selected as the system clock: 4.75V to 5.25V and –40°C < TA < 85°C, or 3.15V to 3.5V and –40°C < TA < 85°C.
Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only.
Table 10. DC Full Speed (12 Mbps) USB Specifications
Parameter Description Min Typ Max Unit Notes
USB Interface
VDI Differential Input Sensitivity 0.2 – – V | (D+) – (D–) |
VCM Differential Input Common Mode Range 0.8 – 2.5 V
VSE Single Ended Receiver Threshold 0.8 – 2.0 V
CIN Transceiver Capacitance – – 20 pF
IIO High Z State Data Line Leakage –10 – 10 μA 0V < VIN < 3.3V.
REXT External USB Series Resistor 23 – 25 Ω In series with each USB pin.
VUOH Static Output High, Driven 2.8 – 3.6 V 15 kΩ ± 5% to ground. Internal pull up
enabled.
VUOHI Static Output High, Idle 2.7 – 3.6 V 15 kΩ ± 5% to ground. Internal pull up
enabled.
VUOL Static Output Low – – 0.3 V 15 kΩ ± 5% to ground. Internal pull up
enabled.
ZO USB Driver Output Impedance 28 – 44 Ω Including REXT resistor.
VCRS D+/D– Crossover Voltage 1.3 – 2.0 V

Document Number: 38-08036 Rev. *E Page 16 of 33

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DC Analog Output Buffer Specifications


The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and –40°C < TA < 85°C, or 3.15V to 3.5V and –40°C < TA < 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 11. 5V DC Analog Output Buffer Specifications

Parameter Description Min Typ Max Unit Notes


VOSOB Input Offset Voltage (Absolute Value) – 3 12 mV
TCVOSOB Average Input Offset Voltage Drift – +6 – μV/°C
VCMOB Common-Mode Input Voltage Range 0.5 – Vdd - 1.0 V
ROUTOB Output Resistance
Power = Low – 0.6 – W
Power = High – 0.6 – W
VOHIGHOB High Output Voltage Swing
(Load = 32 ohms to Vdd/2)
Power = Low 0.5xVdd + 1.1 – – V
Power = High 0.5xVdd + 1.1 – – V
VOLOWOB Low Output Voltage Swing
(Load = 32 ohms to Vdd/2)
Power = Low – – 0.5 x Vdd – V
Power = High – – 1.3 V
0.5 x Vdd –
1.3
ISOB Supply Current Including Bias Cell (No
Load) – 1.1 5.1 mA
Power = Low – 2.6 8.8 mA
Power = High
PSRROB Supply Voltage Rejection Ratio 53 64 – dB (0.5 x Vdd – 1.3) < VOUT < (Vdd
– 2.3).

Table 12. 3.3V DC Analog Output Buffer Specifications

Parameter Description Min Typ Max Unit Notes


VOSOB Input Offset Voltage (Absolute Value) – 3 12 mV
TCVOSOB Average Input Offset Voltage Drift – +6 – μV/°C
VCMOB Common-Mode Input Voltage Range 0.5 - Vdd - 1.0 V
ROUTOB Output Resistance
Power = Low – 1 – W
Power = High – 1 – W
VOHIGHOB High Output Voltage Swing
(Load = 1K ohms to Vdd/2)
Power = Low 0.5 x Vdd + 1.0 – – V
Power = High 0.5 x Vdd + 1.0 – – V
VOLOWOB Low Output Voltage Swing
(Load = 1K ohms to Vdd/2)
Power = Low – – 0.5 x Vdd – 1.0 V
Power = High – – 0.5 x Vdd – 1.0 V
ISOB Supply Current Including Bias Cell
(No Load) 0.8 2.0 mA
Power = Low – 2.0 4.3 mA
Power = High
PSRROB Supply Voltage Rejection Ratio 34 64 – dB (0.5 x Vdd – 1.0) < VOUT < (0.5 x
Vdd + 0.9).

Document Number: 38-08036 Rev. *E Page 17 of 33

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DC Analog Reference Specifications


The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and –40°C < TA < 85°C, or 3.15V to 3.5V and –40°C < TA < 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 13. 5V DC Analog Reference Specifications
Parameter Description Min Typ Max Unit
BG Bandgap Voltage Reference 1.28 1.30 1.32 V
– AGND = Vdd/2[3] Vdd/2 – 0.04 Vdd/2 – 0.01 Vdd/2 + 0.007 V
– AGND = 2 x BandGap[3] 2 x BG – 0.048 2 x BG – 0.030 2 x BG + 0.024 V
– AGND = P2[4] (P2[4] = Vdd/2)[3] P2[4] – 0.011 P2[4] P2[4] + 0.011 V
[3]
– AGND = BandGap BG – 0.009 BG + 0.008 BG + 0.016 V
– AGND = 1.6 x BandGap[3] 1.6 x BG – 0.022 1.6 x BG – 0.010 1.6 x BG + 0.018 V
– AGND Block to Block Variation –0.034 0.000 0.034 V
(AGND = Vdd/2)[3]
– RefHi = Vdd/2 + BandGap Vdd/2 + BG – 0.10 Vdd/2 + BG Vdd/2 + BG + 0.10 V
– RefHi = 3 x BandGap 3 x BG – 0.06 3 x BG 3 x BG + 0.06 V
– RefHi = 2 x BandGap + P2[6] (P2[6] = 2 x BG + P2[6] – 2 x BG + P2[6] – 0.018 2 x BG + P2[6] + 0.077 V
1.3V) 0.113
– RefHi = P2[4] + BandGap (P2[4] = P2[4] + BG – 0.130 P2[4] + BG – 0.016 P2[4] + BG + 0.098 V
Vdd/2)
– RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[4] + P2[6] – 0.133 P2[4] + P2[6] – 0.016 P2[4] + P2[6]+ 0.100 V
P2[6] = 1.3V)
– RefHi = 3.2 x BandGap 3.2 x BG – 0.112 3.2 x BG 3.2 x BG + 0.076 V
– RefLo = Vdd/2 – BandGap Vdd/2 – BG – 0.04 Vdd/2 – BG + 0.024 Vdd/2 – BG + 0.04 V
– RefLo = BandGap BG – 0.06 BG BG + 0.06 V
– RefLo = 2 x BandGap – P2[6] (P2[6] = 2 x BG – P2[6] – 2 x BG – P2[6] + 0.025 2 x BG – P2[6] + 0.134 V
1.3V) 0.084
– RefLo = P2[4] – BandGap (P2[4] = P2[4] – BG – 0.056 P2[4] – BG + 0.026 P2[4] – BG + 0.107 V
Vdd/2)
– RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[4] – P2[6] – 0.057 P2[4] – P2[6] + 0.026 P2[4] – P2[6] + 0.110 V
P2[6] = 1.3V)

Document Number: 38-08036 Rev. *E Page 18 of 33

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Table 14. 3.3V DC Analog Reference Specifications


Parameter Description Min Typ Max Unit
BG Bandgap Voltage Reference 1.28 1.30 1.32 V
– AGND = Vdd/2[3] Vdd/2 – 0.03 Vdd/2 – 0.01 Vdd/2 + 0.005 V
– AGND = 2 x BandGap[3] Not Allowed
– AGND = P2[4] (P2[4] = Vdd/2) P2[4] – 0.008 P2[4] + 0.001 P2[4] + 0.009 V
– AGND = BandGap[3] BG – 0.009 BG + 0.005 BG + 0.015 V
– AGND = 1.6 x BandGap[3] 1.6 x BG – 0.027 1.6 x BG – 0.010 1.6 x BG + 0.018 V
– AGND Column to Column Variation –0.034 0.000 0.034 V
(AGND = Vdd/2)[3]
– RefHi = Vdd/2 + BandGap Not Allowed
– RefHi = 3 x BandGap Not Allowed
– RefHi = 2 x BandGap + P2[6] Not Allowed
(P2[6] = 0.5V)
– RefHi = P2[4] + BandGap Not Allowed
(P2[4] = Vdd/2)
– RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[4] + P2[6] – 0.075 P2[4] + P2[6] – 0.009 P2[4] + P2[6] + 0.057 V
P2[6] = 0.5V)
– RefHi = 3.2 x BandGap Not Allowed
– RefLo = Vdd/2 – BandGap Not Allowed
– RefLo = BandGap Not Allowed
– RefLo = 2 x BandGap - P2[6] Not Allowed
(P2[6] = 0.5V)
– RefLo = P2[4] – BandGap Not Allowed
(P2[4] = Vdd/2)
– RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[4] – P2[6] – 0.048 P2[4] – P2[6] + 0.022 P2[4] – P2[6] + 0.092 V
P2[6] = 0.5V)

DC Analog enCoRe III Block Specifications


The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and –40°C < TA < 85°C, or 3.15V to 3.5V and –40°C < TA < 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 15. DC Analog enCoRe III Block Specifications

Parameter Description Min Typ Max Unit Notes


RCT Resistor Unit Value (Continuous Time) – 12.2 – kΩ
CSC Capacitor Unit Value (Switched – 80 – fF
Capacitor)

Note
3. AGND tolerance includes the offsets of the local buffer in the enCoRe III block. Bandgap voltage is 1.3V ± 0.02V.

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DC POR and LVD Specifications


The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and –40°C < TA < 85°C, or 3.15V to 3.5V and –40°C < TA < 85°C, respectively. Typical parameters apply to 5V or 3.3V at 25°C and
are for design guidance only.
Note The bits PORLEV and VM in the following table refer to bits in the VLT_CR register. See the PSoC Mixed-Signal Array Technical
Reference Manual for more information on the VLT_CR register.

Table 16. DC POR and LVD Specifications


Parameter Description Min Typ Max Unit Notes
Vdd Value for PPOR Trip (positive ramp)
VPPOR0R PORLEV[1:0] = 00b 2.91 V
VPPOR1R PORLEV[1:0] = 01b – 4.39 – V
VPPOR2R PORLEV[1:0] = 10b 4.55 V
Vdd Value for PPOR Trip (negative ramp)
VPPOR0 PORLEV[1:0] = 00b 2.82 V
VPPOR1 PORLEV[1:0] = 01b – 4.39 – V
VPPOR2 PORLEV[1:0] = 10b 4.55 V
PPOR Hysteresis
VPH0 PORLEV[1:0] = 00b – 92 – mV
VPH1 PORLEV[1:0] = 01b – 0 – mV
VPH2 PORLEV[1:0] = 10b – 0 – mV
Vdd Value for LVD Trip
VLVD0 VM[2:0] = 000b 2.86 2.92 2.98[4] V
VLVD1 VM[2:0] = 001b 2.96 3.02 3.08 V
VLVD2 VM[2:0] = 010b 3.07 3.13 3.20 V
VLVD3 VM[2:0] = 011b 3.92 4.00 4.08 V
VLVD4 VM[2:0] = 100b 4.39 4.48 4.57 V
VLVD5 VM[2:0] = 101b 4.55 4.64 4.74[5] V
VLVD6 VM[2:0] = 110b 4.63 4.73 4.82 V
VLVD7 VM[2:0] = 111b 4.72 4.81 4.91 V

Notes
4. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply.
5. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply.

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DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and –40°C < TA < 85°C, or 3.15V to 3.5V and –40°C < TA < 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.

Table 17. DC Programming Specifications


Parameter Description Min Typ Max Unit Notes
IDDP Supply Current During Programming or Verify – 15 30 mA
VILP Input Low Voltage During Programming or – – 0.8 V
Verify
VIHP Input High Voltage During Programming or 2.1 – – V
Verify
IILP Input Current when Applying Vilp to P1[0] or – – 0.2 mA Driving internal pull down resistor.
P1[1] During Programming or Verify
IIHP Input Current when Applying Vihp to P1[0] or – – 1.5 mA Driving internal pull down resistor.
P1[1] During Programming or Verify
VOLV Output Low Voltage During Programming or – – Vss + 0.75 V
Verify
VOHV Output High Voltage During Programming or Vdd – 1.0 – Vdd V
Verify
FlashENPB Flash Endurance (per block) 50,000[6] – – – Erase/write cycles per block.
FlashENT Flash Endurance (total)[7] 1,800,000 – – – Erase/write cycles.
FlashDR Flash Data Retention 10 – – Years

Notes
6. The 50,000 cycle Flash endurance per block will only be guaranteed if the Flash is operating within one voltage range. Voltage ranges are 3.0V to 3.6V and 4.75V
to 5.25V.
7. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2
blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block
ever sees more than 50,000 cycles).
For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing.
Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.

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AC Electrical Characteristics
AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and –40°C < TA < 85°C, or 3.15V to 3.5V and –40°C < TA < 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 18. AC Chip-Level Specifications

Parameter Description Min Typ Max Unit Notes


[7, 8]
FIMO245V Internal Main Oscillator Frequency for 23.04 24 24.96 MHz Trimmed for 5V operation using
24 MHz (5V) factory trim values.
FIMO243V Internal Main Oscillator Frequency for 22.08 24 25.92[7,9] MHz Trimmed for 3.3V operation using
24 MHz (3.3V) factory trim values.
FIMOUSB Internal Main Oscillator Frequency with 23.94 24 24.06[8] MHz USB operation for system clock
USB Frequency Locking Enabled and source from the IMO is limited to
USB Traffic Present 0°C < TA < 70°C.
FCPU1 CPU Frequency (5V Nominal) 0.93 24 24.96[7,8] MHz
FCPU2 CPU Frequency (3.3V Nominal) 0.93 12 12.96[8, 9] MHz
FBLK5 Digital PSoC Block Frequency 0 48 49.92[7, 8, 10] MHz Refer to the AC Digital Block
(5V Nominal) Specifications.
FBLK3 Digital PSoC Block Frequency ( 0 24 25.92[8, 10] MHz
3.3V Nominal)
F32K1 Internal Low Speed Oscillator Frequency 15 32 64 kHz
F32K_U Internal Low Speed Oscillator Untrimmed 5 – – kHz
Frequency
DCILO Internal Low Speed Oscillator Duty Cycle 20 50 80 %
Jitter32k 32 kHz Period Jitter – 100 ns
Step24M 24 MHz Trim Step Size – 50 – kHz
Fout48M 48 MHz Output Frequency 46.08 48.0 49.92[7, 9] MHz Trimmed. Utilizing factory trim values.
Jitter24M1 24 MHz Period Jitter (IMO) Peak-to-Peak – 300 ps
FMAX Maximum Frequency of Signal on Row – – 12.96 MHz
Input or Row Output
SRPOWER_UP Power Supply Slew Rate – – 250 V/ms
TPOWERUP Time from End of POR to CPU Executing – 16 100 ms
Code
Figure 6. 24 MHz Period Jitter (IMO) Timing Diagram
Jitter24M1

F24M

Notes
7. 4.75V < Vdd < 5.25V.
8. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
9. 3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation
at 3.3V.
10. See the individual user module data sheets for information on maximum frequencies for user modules.

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AC General Purpose I/O Specifications


The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and –40°C < TA < 85°C, or 3.15V to 3.5V and –40°C < TA < 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 19. AC GPIO Specifications
Parameter Description Min Typ Max Unit Notes
FGPIO GPIO Operating Frequency 0 – 12 MHz Normal Strong Mode
TRiseF Rise Time, Normal Strong Mode, Cload = 50 pF 3 – 18 ns Vdd = 4.5 to 5.25V, 10%–90%
TFallF Fall Time, Normal Strong Mode, Cload = 50 pF 2 – 18 ns Vdd = 4.5 to 5.25V, 10%–90%
TRiseS Rise Time, Slow Strong Mode, Cload = 50 pF 10 27 – ns Vdd = 3 to 5.25V, 10%–90%
TFallS Fall Time, Slow Strong Mode, Cload = 50 pF 10 22 – ns Vdd = 3 to 5.25V, 10%–90%

Figure 7. GPIO Timing Diagram

90%

GPIO
Pin
Output
Voltage

10%

TRiseF TFallF
TRiseS TFallS

AC Full Speed USB Specifications


The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and –40°C < TA < 85°C, or 3.15V to 3.5V and –40°C < TA < 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 20. AC Full Speed (12 Mbps) USB Specifications
Parameter Description Min Typ Max Unit Notes
TRFS Transition Rise Time 4 – 20 ns For 50 pF load.
TFSS Transition Fall Time 4 – 20 ns For 50 pF load.
TRFMFS Rise/Fall Time Matching: (TR/TF) 90 – 111 % For 50 pF load.
TDRATEFS Full Speed Data Rate 12 – 0.25% 12 12 + 0.25% Mbps

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AC Digital Block Specifications


The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and –40°C < TA < 85°C, or 3.15V to 3.5V and –40°C < TA < 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 21. AC Digital Block Specifications
Function Description Min Typ Max Unit Notes
Timer Capture Pulse Width 50[11] – – ns
Maximum Frequency, No Capture – – 49.92 MHz 4.75V < Vdd < 5.25V.
Maximum Frequency, With Capture – – 25.92 MHz
Counter Enable Pulse Width 50[11] – – ns
Maximum Frequency, No Enable Input – – 49.92 MHz 4.75V < Vdd < 5.25V.
Maximum Frequency, Enable Input – – 25.92 MHz
Dead Band Kill Pulse Width:
Asynchronous Restart Mode 20 – – ns
Synchronous Restart Mode 50[11] – – ns
Disable Mode 50[12] – – ns
Maximum Frequency – – 49.92 MHz 4.75V < Vdd < 5.25V.
CRCPRS Maximum Input Clock Frequency – – 49.92 MHz 4.75V < Vdd < 5.25V.
(PRS
Mode)
CRCPRS Maximum Input Clock Frequency – – 24.6 MHz
(CRC
Mode)
SPIM Maximum Input Clock Frequency – – 8.2 MHz Maximum data rate at 4.1 MHz due to 2
x over clocking.
SPIS Maximum Input Clock Frequency – – 4.1 MHz
Width of SS_ Negated Between Trans- 50[11] – – ns
missions
Transmitter Maximum Input Clock Frequency – – 24.6 MHz Maximum data rate at 3.08 MHz due to 8
x over clocking.
Receiver Maximum Input Clock Frequency – – 24.6 MHz Maximum data rate at 3.08 MHz due to 8
x over clocking.

AC External Clock Specifications


The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and –40°C < TA < 85°C, or 3.15V to 3.5V and –40°C < TA < 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.

Table 22. AC External Clock Specifications


Parameter Description Min Typ Max Unit Notes
FOSCEXT Frequency for USB Applications 23.94 24 24.06 MHz USB operation in the extended Industrial
temperature range (–40°C < TA < 85°C)
requires that the system clock is sourced
from an external clock oscillator.
– Duty Cycle 47 50 53 %
– Powerup to IMO Switch 150 – – μs

Note
11. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).

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AC Analog Output Buffer Specifications


The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and –40°C < TA < 85°C, or 3.15V to 3.5V and –40°C < TA < 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 23. 5V AC Analog Output Buffer Specifications

Parameter Description Min Typ Max Unit Notes


TROB Rising Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low – – 2.5 μs
Power = High – – 2.5 μs
TSOB Falling Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low – – 2.2 μs
Power = High – – 2.2 μs
SRROB Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load
Power = Low 0.65 – – V/μs
Power = High 0.65 – – V/μs
SRFOB Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load
Power = Low 0.65 – – V/μs
Power = High 0.65 – – V/μs
BWOBSS Small Signal Bandwidth, 20mVpp, 3-dB BW, 100 pF Load
Power = Low 0.8 – – MHz
Power = High 0.8 – – MHz
BWOBLS Large Signal Bandwidth, 1Vpp, 3-dB BW, 100 pF Load
Power = Low 300 – – kHz
Power = High 300 – – kHz

Table 24. 3.3V AC Analog Output Buffer Specifications

Parameter Description Min Typ Max Unit Notes


TROB Rising Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low – – 3.8 μs
Power = High – – 3.8 μs
TSOB Falling Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low – – 2.6 μs
Power = High – – 2.6 μs
SRROB Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load
Power = Low 0.5 – – V/μs
Power = High 0.5 – – V/μs
SRFOB Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load
Power = Low 0.5 – – V/μs
Power = High 0.5 – – V/μs
BWOBSS Small Signal Bandwidth, 20mVpp, 3dB BW, 100 pF Load
Power = Low 0.7 – – MHz
Power = High 0.7 – – MHz
BWOBLS Large Signal Bandwidth, 1Vpp, 3dB BW, 100 pF Load
Power = Low 200 – – kHz
Power = High 200 – – kHz

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AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and –40°C < TA < 85°C, or 3.15V to 3.5V and –40°C < TA < 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 25. AC Programming Specifications
Parameter Description Min Typ Max Unit Notes
TRSCLK Rise Time of SCLK 1 – 20 ns
TFSCLK Fall Time of SCLK 1 – 20 ns
TSSCLK Data Set up Time to Falling Edge of SCLK 40 – – ns
THSCLK Data Hold Time from Falling Edge of SCLK 40 – – ns
FSCLK Frequency of SCLK 0 – 8 MHz
TERASEB Flash Erase Time (Block) – 10 – ms
TWRITE Flash Block Write Time – 40 – ms
TDSCLK Data Out Delay from Falling Edge of SCLK – – 45 ns Vdd > 3.6
TDSCLK3 Data Out Delay from Falling Edge of SCLK – – 50 ns 3.15 < Vdd < 3.5
TERASEALL Flash Erase Time (Bulk) – 40 – ms Erase all blocks and
protection fields at once.
TPROGRAM_HOT Flash Block Erase + Flash Block Write Time – – 100 ms 0°C ≤ TJ ≤ 100°C
TPROGRAM_COLD Flash Block Erase + Flash Block Write Time – – 200 ms -40°C ≤ TJ ≤ 0°C

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AC I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and –40°C < TA < 85°C, or 3.15V to 3.5V and –40°C < TA < 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 26. AC Characteristics of the I2C SDA and SCL Pins for Vdd

Standard-Mode Fast-Mode
Parameter Description Unit Notes
Min Max Min Max
FSCLI2C SCL Clock Frequency 0 100 0 400 kHz
THDSTAI2C Hold Time (repeated) START Condition. After 4.0 – 0.6 – μs
this period, the first clock pulse is generated.
TLOWI2C LOW Period of the SCL Clock 4.7 – 1.3 – μs
THIGHI2C HIGH Period of the SCL Clock 4.0 – 0.6 – μs
TSUSTAI2C Setup Time for a Repeated START Condition 4.7 – 0.6 – μs
THDDATI2C Data Hold Time 0 – 0 – μs
TSUDATI2C Data Setup Time 250 – 100[12] – ns
TSUSTOI2C Setup Time for STOP Condition 4.0 – 0.6 – μs
TBUFI2C Bus Free Time Between a STOP and START 4.7 – 1.3 – μs
Condition
TSPI2C Pulse Width of spikes are suppressed by the – – 0 50 ns
input filter.

Figure 8. Definition for Timing for Fast-/Standard-Mode on the I2C Bus

SDA
TLOWI2C TSPI2C
TSUDATI2C THDSTAI2C TBUFI2C

SCL

TSUSTAI2C TSUSTOI2C
S THDSTAI2C THDDATI2C THIGHI2C Sr P S

Note
12. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement TSUDATI2C ≥ 250 ns must then be met. This automatically is the
case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line trmax + TSUDATI2C = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.

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Packaging Information
This section illustrates the package specification for the CY7C64215 enCoRe III, along with the thermal impedance for the package.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at
http://www.cypress.com/design/MR10161.

Package Diagrams
Figure 9. 56-Pin (8x8 mm) QFN-MLF (PUNCH)

001-12921 *A

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Figure 10. 56-Pin QFN (8 X 8 X 0.9 MM) (SAWN)

001-53450 *A

Figure 11. 28-Pin (210-Mil) SSOP

51-85079 *D

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Thermal Impedance

Table 27. Thermal Impedance for the Package

Package Typical θJA [13]


56 Pin QFN[14] 20 oC/W
28 Pin SSOP 96 oC/W

Solder Reflow Peak Temperature


Following is the minimum solder reflow peak temperature to achieve good solderability.

Table 28. Solder Reflow Peak Temperature

Package Minimum Peak Temperature[15] Maximum Peak Temperature


56 Pin QFN 240°C 260°C
28 Pin SSOP 240°C 260°C

Package Handling

Some IC packages require baking before they are soldered onto a PCB to remove moisture that may have been absorbed after leaving
the factory. A label on the packaging has details about actual bake temperature and the minimum bake time to remove this moisture.
The maximum bake time is the aggregate time that the devices are exposed to the bake temperature. Exceeding this exposure time
may degrade device reliability.

Parameter Description Min Typ Max Unit


TBAKETEMP Bake Temperature 125 See Package Label °C
TBAKETIME Bake Time See Package Label 72 Hours

Notes
13. TJ = TA + POWER x θJA
14. To achieve the thermal impedance specified for the QFN package, the center thermal pad should be soldered to the PCB ground plane.
15. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5°C with Sn-Pb or 245 ± 5°C with Sn-Ag-Cu paste.
Refer to the solder manufacturer specifications.

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Ordering Information
Package Ordering Code Flash Size SRAM (Bytes) Temperature Range
56-Pin QFN-MLF (Punch) CY7C64215-56LFXC 16K 1K 0°C to 70°C
56-Pin QFN-MLF (Punch) CY7C64215-56LFXCT 16K 1K 0°C to 70°C
(Tape and Reel)
28-Pin SSOP CY7C64215-28PVXC 16K 1K 0°C to 70°C
28-Pin SSOP CY7C64215-28PVXCT 16K 1K 0°C to 70°C
(Tape and Reel)
56-Pin QFN (Sawn) Commercial CY7C64215-56LTXC 16K 1K 0°C to 70°C
56-Pin QFN (Sawn) Commercial CY7C64215-56LTXCT 16K 1K 0°C to 70°C
(Tape and Reel)
56-Pin QFN (Sawn) Industrial CY7C64215-56LTXI 16K 1K –40°C to 85°C
56-Pin QFN (Sawn) Industrial CY7C64215-56LTXIT 16K 1K –40°C to 85°C
(Tape and Reel)

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Document History Page


Description Title: CY7C64215, enCoRe™ III Full Speed USB Controller
Document Number: 38-08036
Submission Orig. of
Rev. ECN No. Description of Change
Date Change
** 131325 See ECN XGR New data sheet.
*A 385256 See ECN BHA Changed from Advance Information to Preliminary.
Added standard data sheet items.
Changed Part number from CY7C642xx to CY7C64215.
*B 2547630 08/04/08 AZIEL/PYRS Operational voltage range for USB specified under "Full Speed USB (12Mbps)".
CMP_GO_EN1 register removed as it has no functionality on Radon.
Figure "CPU Frequency" adjusted to show invalid operating region for USB with
footnote describing reason.
DC electrical characteristic, Vdd. Note added describing where USB hardware
is non-functional.
*C 2620679 12/12/08 CMCC/PYRS Added Package Handling information.
Deleted note regarding link to amkor.com for MLF package dimensions.
*D 2717887 06/11/2009 DPT Added 56 -Pin Sawn QFN (8 X 8 mm) package diagram and added
CY7C64215-56LTXC part information in the Ordering Information table.
*E 2852393 01/15/2010 BHA/XUT ■ Added Table of Contents.
■ Added external clock oscillator option and Industrial Temperature information
to the Features, Pin Information, Electrical Specifications, Operating Temper-
ature, DC Electrical Characteristics, AC Electrical Characteristics, and
Ordering Information sections.
■ Updated DC GPIO, AC Chip, and AC Programming Specifications follows:
❐ Replaced TRAMP (time) with SRPOWER_UP (slew rate) specification.
❐ Added IOH, IOL, DCILO, F32K_U, TPOWERUP, TERASEALL,
TPROGRAM_HOT, and TPROGRAM_COLD specifications.
❐ Updated Vdd ranges on Figure 5 and Table 8.
❐ Added notes for VM and VDI on Table 10.
❐ Removed TR/TF from Table 20.
■ Update Ordering Information for: CY7C64215-56LFXCT,
CY7C64215-28PVXCT, CY7C64215-56LTXIT Tape and Reel.
■ Updated 28-Pin SSOP and 56-Pin QFN PUNCH and SAWN package
diagrams.
■ Updated copyright and Sales, Solutions, and Legal Information URLs.

Document Number: 38-08036 Rev. *E Page 32 of 33

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CY7C64215

Sales, Solutions, and Legal Information


Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.

Products
Automotive cypress.com/go/automotive PSoC® Solutions
Clocks & Buffers cypress.com/go/clocks psoc.cypress.com/solutions
Interface cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5
Lighting & Power Control cypress.com/go/powerpsoc
cypress.com/go/plc
Memory cypress.com/go/memory
Optical & Image Sensing cypress.com/go/image
PSoC cypress.com/go/psoc
Touch Sensing cypress.com/go/touch
USB Controllers cypress.com/go/USB
Wireless/RF cypress.com/go/wireless

© Cypress Semiconductor Corporation, 2007-2009, 2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the
use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products
for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 38-08036 Rev. *E Revised February 1, 2010 Page 33 of 33


PSoC Designer™ and enCoRe™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corporation.
Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided
that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors.
All products and company names mentioned in this document may be the trademarks of their respective holders.

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