ECE365 Exam Mar2012
ECE365 Exam Mar2012
INSTRUCTIONS TP CANDIDATES
1. This question paper consists of TWO (2) parts : PART A (25 Questions)
PART B (3 Questions)
Do not bring any material into the examination room unless permission is given by the
invigilator.
Please check to make sure that this examination pack consists of:
PARTA
3) Control unit in a microprocessor determines the Operation of a CPU either it reads from
or writes into memory or I/O.
8) Microcomputer Systems can be built with a processor and input/output device without a
bus System and memory.
12 A microprocessor with 24-bit address bus and 8-bit data bus can address up to
512MB.
21) Index Register X and Y in HCS12/HC11 are also used in several arithmetic Operations.
22) Stack Pointer (SP) is a 16-bit register holds the address of the next instruction to be
executed.
24) Table Q24 shows the prefixes for number bases in HCS12/HC11 :
Table Q24
Base Prefix Example
Binary B 10101111B
Hexadecimal H 2587H
25) Program Counter (PC) increases the value of address that it holds automatically.
(25 marks)
PARTB
QUESTION 1
c) A microprocessor Chip has 16-bit address bus and 32-bit data bus. Calculate:
i) The minimum and maximum signed data that can be transferred between
microprocessor and memory or I/O. Show your answer in both hexadecimal and
decimal numbers.
ii) The capacity of the memory can be interfaced with the microprocessor chip.
State your answer in bytes.
iii) The starting and final addresses of the memory that can be interfaced with the
microprocessor. Express your answer in hexadecimal numbers only.
iv) Given a 2K x 32 SRAM, design the interfacing circuit by using 3-to-8 decoder as
shown in Figure Q1c, where the starting address of SRAM is 2000H. and show
all your calculations. Determine the final address of SRAM. Use the MREQ RD
i
A (MSB) O0 3—
B ° 1 ")
<J
C (LSB)
r* El
L
—c Ü o6 1
E3 o 7 <J
")
3-to-8 Decoder
Figure Q1c
(16 marks)
QUESTION 2
a) Draw a diagram of HCS12 CPU registers and list two (2) features of HCS12.
(5 marks)
b) Identify the addressing modes and constant offset ränge of the following Instructions:
i) INY
ii) LDX #4000
iii) LDAA 0,Y
iv) LDAB -200.X
v) STAA 7.SP+
(5 marks)
(5 marks)
d) HCS12/HC11 supports the addition of data greater than 16-bit. Figure Q2d is a
flowchart of 64-bit multiprecision addition by using looping instructions. The two (2)
values of addition are stored in $800 and $810, and the final result is stored at $900.
Start your program at the address of $800.
Notes:
Figure Q2d
(10 marks)
QUESTION 3
a) A System has four (4) common cathode seven-segment LEDs display which connected
to Port A, Port B, Port P and Port T of HCS12/HC11. This System will display 'HELP'
on the seven-segment LEDs display.
i) Draw a complete circuit of the System.
ii) Determine the corresponding value of 'HELP' at all ports.
iii) Write a complete program.
(12marks)
b) Figure Q3b depicts the circuit connection between eight (8) LEDs with HCS12/HC11.
BO
B1
HCS12/ B2
HC11 B3
B4
B5
B6
B7
J1
Figure Q3b
i) The HCS12/HC11 uses the E-clock signal as a timing reference. If the crystal
oscillator of the HCS12/HC11 is 48MHz, compute the E-clock in Hertz (Hz) and
seconds (s).
ii) Write a füll program to make all LEDs blinking. The delay between turning on
and off is 500ms. Refer to Table Q3b for your Instructions.
(6 marks)
Table Q3b
Mnemonic Instruction cycle
Addressing EXT IDX IDX1 IDX2 INH REL
modes
Dec 4 3 4 5 1 -
Bne - - - - - 3
Dbne - - - - - 3
Beq - - - - - 3
dbeq - - - - - 3
Notes:
EXT : Extended addressing modes
IDX : 5-bit constant offset indexed addressing modes
IDX1 : 9-bit constant offset indexed addressing modes
IDX2 : 16-bit constant offset indexed addressing modes
INH : Inherent mode
REL : Relative mode
c) Figure Q3c shows the connection between DIP switch, LEDs and HCS12/HC11.
Followings are the Instruction sequence for the circuit. Analyze the Output of the
program.
ORG$1000;HC11
BCLR DDRH,$03
BSET DDRB,$F0
BSET DDRJ,$02
BCLR PTJ,$02
AGAIN: LDAA PTH
STAA $2000
BRSET $2000,$03,RESULT1
BACK1: BRCLR $2000,$03,RESULT2
BACK2: BRSET $2000,$01,RESULT3
BACK3: BRSET $2000,$02,RESULT4
BRA AGAIN
RESULT1: LDAA #%11110000
STAA PORTB
BRA BACK1
RESULT2: LDAA#0
STAA PORTB
BRA BACK2
RESULT3: LDAA #%00110000
STAA PORTB
BRA BACK3
RESULT4: LDAA #% 11000000
STAA PORTB
BRA AGAIN
END
Figure Q3c
(7 Marks)