Scribd
Upload
26 views

RISC V ISS SystemC Interface Propsal

This document proposes a SystemC module wrapper for a C++ based RISC-V Instruction Set Simulator. The wrapper module includes ports for clock, reset, and data I/O. It uses upcalls to notify the environment of interrupts during execution and blocking methods for data transport. On each clock cycle, it checks for reset, interrupts, and passes the next instruction to the ISS object.

Uploaded by

jeries shehadeh
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
26 views

RISC V ISS SystemC Interface Propsal

This document proposes a SystemC module wrapper for a C++ based RISC-V Instruction Set Simulator. The wrapper module includes ports for clock, reset, and data I/O. It uses upcalls to notify the environment of interrupts during execution and blocking methods for data transport. On each clock cycle, it checks for reset, interrupts, and passes the next instruction to the ISS object.

Uploaded by

jeries shehadeh
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 3

ORION VLSI Technologies

IP – Architectural Team
RISC V ISS SysctemC Interface (Wrapper) Proposal
Shehadeh, J under Team Lead Hroub(CTO), A and Nasir,N (CEO)

Proposal

Below is a SystemC module wrapper for a C++ based RISC-V Instruction Set Simulator. The
module includes ports for clock, reset, and an output port. Inside the module there is a
RISCVSIM object which is instantiated in the constructor.

Upcalls/Interrupts are implemented in the module to allow environment notification of certain


events during execution time: when the ISS encounters an interrupt it can use those upcalls to
notify the wrapper.

Blocking method is also implemented to allow sending and receiving data using a blocking
mechanism. This shall be helpful for out TLM module.

The simulation Thread waits for the positive edge of the clock and checks if reset is asserted then
if yes it loads the program and run the simulation. It also checks if an interrupt has occurred by
calling the interrupt_occured function, if yes it puts the value true on the interrupt output to be
handled by another module in the systemC environment. The simulation thread also retrieves
data from the ISS by calling get_data() function of the ISS object and writing it to the "data_bus"
port. Then it read the data from "data_bus" port and set it to the ISS object by calling set_data()
function of the ISS object. In this way the data is exchanged between the ISS and the systemc
environment (Note that this step may be unnecessary if we are only interested in the final output)

The step() function is responsible for the cycle accurate simulation. It is called eached cycle to
pass the next instruction with the updated line number.

Note that this code is in a dirty stage as it’s running time can be cut shorter

Note that this module is not time accurate as it will issue a new instruction on every clock cycle.

Confidential – Orion VLSI Technologies


Code

#include "systemc.h"
#include simulator library header

SC_MODULE(ISS_WRAPPER) {
sc_in<bool> clk;
sc_in<bool> reset;
sc_out<bool> done; //for status check
sc_out<bool> interrupt; //for interrupts (manual)
sc_inout_rv<32> data_bus; // inout port for data bus

Spike_ISS *iss;

void iss_thread() {
while (true) {
if (reset.read() == true) {
iss->load_program("program.bin");
iss->run();
done.write(true);
}

if (iss->interrupt_occured()) {
interrupt.write(true);
} else {
interrupt.write(false);
}

data_bus.write(iss->get_data()); // blocking transport


wait();
iss->set_data(data_bus.read()); // blocking transport
}
}

//constructors and destructors


SC_CTOR(ISS_WRAPPER) {
iss = new ISS();

SC_THREAD(iss_thread);
sensitive << clk.pos();
}

~ISS_WRAPPER() {
delete iss;
}
};

Confidential – Orion VLSI Technologies


Step() Function Implementation

#include <iostream>
#include <fstream>
#include <string>

//returns specified instruction (line number passed as parameter)


Iss_thread step(int i, String s){
//initialize local counter
int ins = 0;

//goes through instruction till it reaches specified line


std::ifstream instructionFile("s.txt");
while(std::getline(instructionFile)){
//returns line (instruction) if it reached specified line
if(ins == i){
return sted::getline(s);
}else{
ins++; //if not increment local counter
}
}
return "outOfReach";
}

References & Citations


 IEEE Computer Society. (2012). IEEE Standard for Standard SystemC® Language
Reference Manual. IEEE STD 1666
 Formaggio L, Fummi F, Pravadelli G. (2004). A timing-accurate HW/SW co-simulation
of an ISS with SystemC. Universita` di Verona. Italy
 Chapter 4. Wrapping the ISS. (n.d.). Www.embecosm.com. Retrieved January 20, 2023,
from https://www.embecosm.com/appnotes/ean1/html/ch04.html
 SystemC: sc_dt Namespace Reference. (n.d.). Eda-Playground.readthedocs.io. Retrieved
January 20, 2023, from https://eda-playground.readthedocs.io/en/latest/_static/systemc-
2.3.1/sysc/a00394.html

Confidential – Orion VLSI Technologies

You might also like