Unit-1

1.Draw the register organization of 8086 Microprocessor and explain it.

8086 Microprocessor
Architecture Execution Unit (EU)

EU decodes and
executes instructions.

A decoder in the EU
control system
translates instructions.

16-bit ALU for

performing arithmetic
and logic operation

Four general purpose

registers(AX, BX, CX, DX);

Pointer registers (Stack

Pointer, Base Pointer);

and
Some of the 16 bit registers can be
Index registers (Source used as two 8 bit registers as :
Index, Destination Index)
each of 16-bits AX can be used as AH and AL
BX can be used as BH and BL
CX can be used as CH and CL 53
DX can be used as DH and DL
Accumulator Register (AX)
Consists of two 8-bit registers AL and AH, which can be combined together and used as a 16-bit register AX.
AL in this case contains the low order byte of the word, and AH contains the high-order byte.
The I/O instructions use the AX or AL for inputting / outputting 16 or 8 bit data to or from an I/O port.
Multiplication and Division instructions also use the AX or AL.
Base Register (BX)
Consists of two 8-bit registers BL and BH, which can be combined together and used as a 16-bit register BX.
BL in this case contains the low-order byte of the word, and BH contains the high-order byte.
This is the only general purpose register whose contents can be used for addressing the 8086 memory.
All memory references utilizing this register content for addressing use DS as the default segment register.
Counter Register (CX)
Consists of two 8-bit registers CL and CH, which can be combined together and used as a 16-bit register CX.
When combined, CL register contains the low order byte of the word, and CH contains the high-order byte.
Instructions such as SHIFT, ROTATE and LOOP use the contents of CX as a counter.

Stack Pointer (SP) and Base Pointer (BP)

SP and BP are used to access data in the stack segment.
SP is used as an offset from the current SS during execution of instructions that involve the stack segment in the
external memory.
SP contents are automatically updated (incremented/ decremented) due to execution of a POP or PUSH
instruction.
BP contains an offset address in the current SS, which is used by instructions utilizing the based addressing
mode.
Source Index (SI) and Destination Index (DI)
Used in indexed addressing.
Instructions that process data strings use the SI and DI registers together with DS and ES respectively in order
to distinguish between the source and destination addresses.
Four 16-bit segment registers: Code Segment (CS), Data Segment (DS),Stack Segment (SS),Extra Segment (ES)
2. Explain the minimum mode pins of 8086 Microprocessor in detail. Or
Draw the read and write cycle timing diagrams of 8086 in minimum mode.
The 8086 microprocessor can work in two modes of operations : Minimum mode and Maximum mode
In the minimum mode of operation the microprocessor do not associate with any co-processors and can not
be used for multiprocessor systems.
8086 Microprocessor
Pins and Signals Minimum mode signals

(Data Transmit/ Receive) Output signal from the

processor to control the direction of data flow
through the data transceivers

(Data Enable) Output signal from the processor

used as out put enable for the transceivers

ALE (Address Latch Enable) Used to demultiplex the

address and data lines using external latches

Used to differentiate memory access and I/O

access. For memory reference instructions, it is
high. For IN and OUT instructions, it is low.

Write control signal; asserted low Whenever

processor writes data to memory or I/O port

(Interrupt Acknowledge) When the interrupt

request is accepted by the processor, the output is
low on this line.
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8086 Microprocessor
Pins and Signals Minimum mode signals

HOLD Input signal to the processor form the bus masters

as a request to grant the control of the bus.

Usually used by the DMA controller to get the

control of the bus.

HLDA (Hold Acknowledge) Acknowledge signal by the

processor to the bus master requesting the control
of the bus through HOLD.

The acknowledge is asserted high, when the

processor accepts HOLD.

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 Timing diagram :
• The working of min mode
can be easily understood
by timing diagrams.
• All processors bus cycle is
of at least 4 T-
states(T1,T2,T3,T4) .The
address is given by
processor in the T1 state.
It is available on the bus
for one T-state.
• In T2, the bus is tristated
for changing the direction
of the bus( in the case of
a data read cycle.)
• The data transfer takes
place between T3 and T4.
• If the addressed device is
slower, then the wait
state is inserted between
T3 and T4.

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• At T1 state ALE =1 ,this indicates that a valid address

is latched on the address bus and also M / IO’= 1,
which indicates the memory operation is in progress.
• In T2, the address is removed from the local bus and
is sent to the addressed device. Then the bus is
tristated.
• When RD’ = 0 , the valid data is present on the data
bus.
• During T2 DEN’ =0, which enables transreceivers and
DT/R’ = 0 ,which indicates that the data is received.
• During T3, data is put on the data bus and the
processor reads it.
• The output device makes the READY line high. This
means the output device has performed the data
transfer process. When the processor makes the read
signal to 1, then the output device will again tristate
its bus drivers.

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3. Explain the concept of physical address calculation of 8086 microprocessor.

8086 Microprocessor
Addressing Modes : Memory Access

Offset Value (16 bits)

Segment Register (16 bits) 0000

Adder

Physical Address (20 Bits)

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8086 Microprocessor
Addressing Modes : Memory Access

20 Address lines  8086 can address up to

220 = 1M bytes of memory

However, the largest register is only 16 bits

Physical Address will have to be calculated

Physical Address : Actual address of a byte in
memory. i.e. the value which goes out onto the
address bus.

Memory Address represented in the form –

Seg : Offset (Eg - 89AB:F012)

Each time the processor wants to access

memory, it takes the contents of a segment
register, shifts it one hexadecimal place to the
16 bytes of
left (same as multiplying by 1610), then add the contiguous memory
required offset to form the 20- bit address

89AB : F012  89AB  89AB0 (Paragraph to byte  89AB x 10 = 89AB0)

F012  0F012 (Offset is already in byte unit)
+ -------
98AC2 (The absolute address)
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4. Draw the internal architecture of 8086 microprocessor and explain its

operation.
 Architecture

Execution Unit (EU)

EU executes instructions that have already been fetched by the BIU.
BIU and EU functions separately.
Bus Interface Unit (BIU)
BIU fetches instructions, reads data from memory and I/O ports, writes data to memory and I/ O ports.
Instruction queue
A group of First-In-First-Out (FIFO) in which up to 6 bytes of instruction code are pre fetched from
the memory ahead of time.
This is done in order to speed up the execution by overlapping instruction fetch with execution.
This mechanism is known as pipelining.
EU decodes and executes instructions.
A decoder in the EU control system translates instructions.
16-bit ALU for performing arithmetic and logic operation
Four general purpose registers(AX, BX, CX, DX);
Pointer registers (Stack Pointer, Base Pointer); and Index registers (Source Index, Destination Index) each of
16-bits
Some of the 16 bit registers can be used as two 8 bit registers as :
AX can be used as AH and AL
BX can be used as BH and BL
CX can be used as CH and CL
DX can be used as DH and DL
Sl.No. Type Register width Name of register

1 General purpose register 16 bit AX, BX, CX, DX

8 bit AL, AH, BL, BH, CL, CH, DL, DH
2 Pointer register 16 bit SP, BP
3 Index register 16 bit SI, DI
4 Instruction Pointer 16 bit IP
5 Segment register 16 bit CS, DS, SS, ES
6 Flag (PSW) 16 bit Flag register
8086 Microprocessor
Architecture Registers and Special Functions

Register Name of the Register Special Function

AX 16-bit Accumulator Stores the 16-bit results of arithmetic and logic

operations

AL 8-bit Accumulator Stores the 8-bit results of arithmetic and logic

operations

BX Base register Used to hold base value in base addressing mode

to access memory data

CX Count Register Used to hold the count value in SHIFT, ROTATE

and LOOP instructions

DX Data Register Used to hold data for multiplication and division

operations

SP Stack Pointer Used to hold the offset address of top stack

memory

BP Base Pointer Used to hold the base value in base addressing

using SS register to access data from stack
memory

SI Source Index Used to hold index value of source operand (data)

for string instructions

DI Data Index Used to hold the index value of destination

operand (data) for string operations 63

5. Explain the concept of segmented memory. What are the advantages?

8086’s 1-megabyte memory is divided into segments of up to 64K bytes each.
The 8086 can directly address four segments (256 K bytes within the 1 M byte of memory) at a particular
time.
Programs obtain access to code and data in the segments by changing the segment register content to point to
the desired segments
Segmentation is the process in which the main memory of the computer is logically divided into different
segments and each segment has its own base address.
• It is basically used to enhance the speed of execution of the computer system, so that the processor is
able to fetch and execute the data from the memory easily and fast.
Note that the 8086 does not work the whole 1MB memory at any given time. However, it works only with four
64KB segments within the whole 1MB memory.