5 4 3 2 1

COMPAL CONFIDENTIAL Merion 14 AR

MODEL NAME :EDC40 Whiskey lake-U U42
D
PCB NO : LA-G871P 2019-03-05 D

BOM P/N : 431ADY31L0x REV : 1.0 (A00)

@ : Nopop Component
EMI@ : EMI Component
@EMI@ : EMI Nopop Component
ESD@ : ESDComponent
@ESD@ : ESD Nopop Component
C

RF@ : RF Component C

@RF@ : RF Nopop Component

CONN@ : Connector Component
CXDP@ : XDP Component
DS3@ : Deep sleep support
NDS3@ : non Deep sleep support
750@ : NUVOTON NPCT750 TPM Component
B ST33@ : ST ST33HTPH TPM Component B

RTD3@ : RTD3 support

@RTD3@ : RTD3 Nopop Component
NRTD3@ : non RTD3 support
MB PCB
Part Number

DAA000HW010
Description

PCB 2EE LA-G871P REV1 MB AR 1

VPRO@ : vPro Component
NVPRO@ : Non-vPro Component
Layout Dell logo
JUMP@ : Jump solder and short
A
@JUMP@ : Jump no solder A

i7@ : Only i7 config support 4*4 antenna DELL CONFIDENTIAL/PROPRIETARY

Power CKT : Merion 14_WHL_PWR_X02_1228a Compal Electronics, Inc.
GPIO map : 20181221a Rev1.5
https://Dr-Bios.com
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
COPYRIGHT 2018
ALL RIGHT RESERVED TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Cover Sheet
REV:A00 NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PWB:7YM2P PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P 1.0

Date: Tuesday, March 05, 2019 Sheet 1 of 109

5 4 3 2 1
 5 4 3 2 1

Merion14 AR Block Diagram Reverse Type

Memory BUS (DDR4) DDR4-SO-DIMM X2

BANK 0, 1, 2, 3
DDR4 2400MHz for WHL-U
D
Up to 2x16GB Modules P23~24 D

2-Lane eDP1.3 EDP LCD Touch

EDP CONN I2C[0] P38
P38
USB2.0[6]
Camera
P38 Trough eDP Cable
PCIE[5][6][7][8]
HDMI 1.4 HDMI SLGC55544BVTR
USB2.0[2] USB2.0[2]_PS
CONN P40 DDI[1] USB POWER SHARE
INTEL P71
AR-SP USB USB3.0 Conn
DDI[2]
TBT P42-43 USB3.0[2]
PS(Ext Port 1) Right side
Left side TypeC P71
P45
USB2.0[3]
WHL-U 42 MCP USB3.0 Conn Left side
USB2.0 USB3.0[3] (Ext Port 2) P72
PD Solut i on
SMBus TPS65982DD SMBus
USB2.0[1] from PCH P44,50 I2C

C C

PAGE 6~19
PCIE[9] SATA[1]/PCIE[12] PCIE[10]

CNVi
Card reader M.2,3042 Key B
RTS5242 P70 Micro SIM M.2,2230 Key E
P52 WWAN/LTE/HCA WLAN+BT/CNVi
PCIex2 for 2nd SSD and
Optane P52 P52

SD4.0 USB2.0[7] USB2.0[10]

P70

A(
c
t
i
v
e)
S
t
e
e
r
i
n
g
A
n
t
e
n
n
a
USB/PCIE MUX

M
B
HD3SS3212 I2C[3] LED/B
P54 P9

SPI
Bettery LED
PCIE[11] USB3.0[4]
SATA[2]/PCIE[16][15][14][13]
Pop option
GD25B256DYIG Breath LED
P64
vPro use P8 INT.Speaker
B P56 B
256Mb 4K sector WSON8
LID SWITCH
GD25B64CYIGR P64
HD Audio I/F HDA Codec Universal Jack
Non-vPro use P8 ALC3254 P56 P56
64Mb 4K sector WSON8 USH CONN
P66
GD25B127DSIGR Dig. MIC
P38
TDA8034HN
ESPI

Smart Card Non-vPro use P8 M.2 2280 CPU&PCH XDP Port

USB2.0[8] 128Mb 4K sector SOP8 SSD Conn P68 Trough eDP Cable P79
USH TPM1.2
BCM58202 TPM2.0
SPI ST-ST33HTPH2032AHC1 AUTOMATIC POWER
RFID/NFC P66 SWITCH(APS) P79
BC link
Fingerprint SPI KB/TP CONN
CONN SMSC KBC P63 DC/DC Interface
P78
USH board MEC5105
P58-59
PWM
FP-USB2.0 FAN CONN POWER ON/OFF SW
Fingerprint P63 P77
MOCV P66

A A

DELL CONFIDENTIAL/PROPRIETARY

https://Dr-Bios.com
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Block Diagram
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 2 of 109
5 4 3 2 1
 5 4 3 2 1

POWER STATES USB3.0 SSIC PCIE SATA DESTINATION USB PORT# DESTINATION
Signal SLP SLP SLP SLP ALWAYS M SUS RUN CLOCKS USB3.0-1 PCIE-1 N/A 1 Type C
S3# S4# S5# A# PLANE PLANE PLANE PLANE
State
USB3.0-2 PCIE-2 JUSB1-->Right 2 JUSB1-->Right
S0 (Full ON) / M0 HIGH HIGH HIGH HIGH ON ON ON ON ON USB3.0-3 PCIE-3 JUSB2-->Lef t 3 JUSB2-->Left
D
S3 (Suspend to RAM) / M3 LOW HIGH HIGH HIGH ON ON ON OFF OFF
USB3.0-4 PCIE-4 M.2 3042(LTE) 4 N/A D

USB3.0-5 PCIE-5 5 N/A

S4 (Suspend to DISK) / M3 LOW LOW HIGH HIGH ON ON OFF OFF OFF
USB3.0-6 PCIE-6 6 Camera
Alpine Ridge - SP
S5 (SOFT OFF) / M3 LOW LOW LOW HIGH ON ON OFF OFF OFF PCIE-7 7 M2 3042(WWAN)

S3 (Suspend to RAM) / M-OFF LOW HIGH HIGH LOW ON OFF ON OFF OFF
PCIE-8 8 USH
PCIE-9 Card Reader 9 Reserve for FPR in PB
S4 (Suspend to DISK) / M-OFF LOW LOW HIGH LOW ON OFF OFF OFF OFF
PCIE-10 M.2 2230(WLAN) 10 M.2 2230(BT)
S5 (SOFT OFF) / M-OFF LOW LOW LOW LOW ON OFF OFF OFF OFF PCIE-11 SATA-0
M.2 3042(LTE)
PCIE-12 SATA-1
PCIE-13
C C

PCIE-14 M.2 2280 SSD

(PCIex4 or SATA)
PCIE-15 SATA-1*
PCIE-16 SATA-2

PM TABLE

+5V_ALW
+3.3V_ALW +5V_RUN
+3.3V_ALW_DSW +1.2V_MEM +3.3V_RUN
B power B
plane +3.3V_ALW_PCH +2.5V_MEM +0.6V_DDR_VTT
+RTC_CELL +1.0V_VCCSTG +1.8V_RUN
+1.8V_PRIM
+5V_ALW2
+3.3V_ALW2
State
+3.3V_RTC_LDO
+1.0V_PRIM

S0 ON ON ON

S5 S4/AC ON OFF OFF

S5 S4/AC doesn't exist OFF OFF OFF

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Port assignment
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 3 of 109
5 4 3 2 1
 5 4 3 2 1

CPU PWR
SIO_SLP_S4# VCCSTG_EN
TPS22961 PCH PWR
+1.2V_MEM (UZ27) +VCCPLL_OC
Peripheral Device PWR
SY8210A
(PU200) TYPE-C Power
0.6V_DDR_VTT_ON VCCSTG_EN
TPS22961
Barrel Type-C +0.6V_DDR_VTT (UZ19) +1.0V_VCCSTG
ADAPTER ADAPTER
RUN_ON
TPS22961
D
(UZ21) +1.0V_VCCST D

PCH_PRIM_EN
SY8286R
(PU301) +1.0V_PRIM

RUN_ON
CHARGER SY8057BQ
ISL9538 +13.5VB +5V_ALW (PU401) +1.0VS_VCCIO
ALW ON
(PU700) SYV828C
(PU102) SY8057CQ PCH_PRIM_EN

(PU402) +1.0V_PRIM_CORE
+5V_ALW2 Merion 14 Touch PWR is +5V
RUN_ON 3.3V_TS_EN
EM5209 PJV1701
(UZ47) +5V_RUN (QV8) +TS_PWR

BATTERY AUD_PWR_EN
EM5209
(@UZ5) +5V_RUN_AUDIO

USB_PWR_SHR_VBUS_EN
SY8288B +3.3V_RTC_LDO SLGC55544C
(PU100) (UI3) +5V_USB_CHG_PWR
C C
ALW ON
USB_PWR_EN1#
+3.3V_ALW2 SY6288
(UI1) +USB_EX2_PWR

+3.3V_ALW

PCH_PRIM_EN RUN_ON
RT8097A AOZ1336
(PU501) +1.8V_PRIM (UZ8) +1.8V_RUN
FDMF3035
ISL95808 FDMF3035 (PU610) AO6405
(PU614) (PU612) FDMF3035 (QV1) WLAN_PWR_EN
EM5209
(PU613) +3.3V_WLAN
(UZ47)
IMVP_VR_ON

IMVP_VR_ON

IMVP_VR_ON

EN_INVPWR

PCH_PRIM_EN

B +3.3V_ALW_PCH B
EM5209
(UZ3)
RUN_ON AUD_PWR_EN
+VCC_SA +VCC_GT +VCC_CORE +BL_PWR_SRC EM5209
+3.3V_RUN (@UZ5) +3.3V_RUN_AUDIO

3.3V_WWAN_EN
EM5209 3.3V_CAM_EN#
(UZ4) +3.3V_WWAN PJV1701
(QZ1) +3.3V_CAM

EN_LCDPW R
G527ATP1U
TYPE-C (UV24) +LCDVDD
+5V_ALW
TPS65982DD
(UT5) +20V_TBTA_VBUS_1(5V~20V) SIO_SLP_S4#
AP7361C
+20V_TBTA_VBUS_1(5V~20V) (PU503) +2.5V_MEM
for DDR4

A
+5V_ALW A

AP2204 AP2112K
(UT8) (UT7) +3.3V_VDD_PIC
+5V_TBT_VBUS
DELL CONFIDENTIAL/PROPRIETARY
Reserved Compal Electronics, Inc.

https://Dr-Bios.com
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Power rails
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 4 of 109
5 4 3 2 1
 5 4 3 2 1

+1.0V_PRIM
Timing Diagram for S5 to S0 mode VCCPRIM_1P0
VCCPRIM_CORE
PCH PWRBTN#
SIO_PWRBTN# 8
DCPDSW_1P0
VCCMPHYAON_1P0 PCH_RSMRST#
VCCAPLL_1P0
VCCCLK1~6
RSMRST#
SIO_SLP_SUS#
7
VCCMPHYGT_1P0
VCCSRAM_1P0
SLP_SUS# 5
SIO_SLP_S5#
+1.0V_MPHYGT VCCAMPHYPLL_1P0 SLP_S5#
VCCAPLLEBB
SIO_SLP_S4#
9
SLP_S4# 10
SIO_SLP_S3#
+3.3V_ALW +3.3V_ALW_DSW SLP_S3#
3 VCCDSW_3P3
SLP_A#
SIO_SLP_A#

D
CPU
+3.3V_SPI 5 +3.3V_ALW_PCH SIO_SLP_LAN#
11 D

+VCC_CORE VCCHDA SLP_LAN#

VCCST_PWRGD VCCSPI
12 VCCST_PWRGD VCC VCCPRIM_3P3
VCCPGPPA~E
SLP_WLAN#/GPD9
SIO_SLP_WLAN#
+1.0VS_VCCIO VCCRTCPRIM RESET_OUT#
H_CPUPWRGD
VCCIO
6 +1.8V_PRIM SYS_PWROK
16
15 PROCPWRGD +VCC_GT VCCPGPPG
VCCATS PCH_PWROK
PCH_PWROK

PCH_PLTRST#
VCCGT
+RTC_CELL 14
+1.2V_MEM
17 PLTRST#
VDDQ
VCCRTC
VCCST_PWRGD
VCCST_PWRGD
12
0.6V_DDR_VTT_ON
VDDQC
VCCPLL_OC +1.0V_PRIM 6 +1.0V_PRIM_CORE
VCCPRIM_CORE
12 DDR_VTT_CNTL +1.0V_VCCST 11 SIO_SLP_S4# PROCPWRGD
H_CPUPWRGD
15
VCCST TPS22961 PCH_PLTRST#
VCCSTG
VCCPLL 17 PLTRST#
+VCC_SA
VCCSA

PCH_DPWROK
4 DSW_PWROK

+3.3V_ALW
ENVDD_PCH
+LCDVDD G524B1T11 EDP_VDDEN

+PWR_SRC
+1.0V_PRIM_CORE SIO_SLP_SUS# +3.3V_ALW
6 TPS62134
SIO_SLP_LAN#
+3.3V_ALW 11 +3.3V_LAN EM5209VF SLP_LAN#

C
6 +1.8V_PRIM
RT8097
+5V_RUN
C
@PCH_3.3V_TS_EN

+5V_TSP LP2301ALT1G GPP_B21

+PWR_SRC
6 3.3V_TS_EN (EC)
+3.3V_RUN
+1.0V_PRIM SY8286
3.3V_CAM_EN#
+3.3V_CAM LP2301ALT1G GPD7

Power Button

EC 5105 1BAT 2AC

11 SIO_SLP_WLAN#
11 ADAPTER
+PWR_SRC
+5V_ALW ALWON
+5V_ALW2
RUN_ON
EC 5105 SYV828
+5V_ALW
+5V_RUN 1BAT
EM5209VF
+PWR_SRC
+3.3V_ALW +3.3V_RTC_LDO
BATTERY SY8288
+3.3V_ALW2 2AC
EM5209VF +3.3V_RUN +3.3V_HDD_M2 +3.3V_ALW
+1.8V_PRIM
SIO_SLP_WLAN#
B
EM5209VF +1.8V_RUN B

PCH_RSMRST#
+PWR_SRC 7 +3.3V_ALW
SLP_WLAN#_GATE
+3.3V_ALW
NMOS
TLV62130 +1.0VS_VCCIO PCH_DPWROK 5
4 EM5209VF
PCH_PRIM_EN +3.3V_ALW_PCH 5
11 +3.3V_WLAN EM5209VF
OR
Gate
AUX_EN_WOWL 11 +3.3V_ALW
16
RESET_OUT#

3.3V_WWAN_EN
EM5209VF +3.3V_WWAN

5 SIO_SLP_SUS#

10 SIO_SLP_S4#

SIO_SLP_S5#
9
SIO_SLP_LAN#

11 SIO_SLP_S3# +PWR_SRC
SIO_SLP_A# EN_INVPWR
AO6405 +BL_PWR_SRC 18
+PWR_SRC
12
+VCC_SA IMVP_VR_ON 10 +PWR_SRC
13 +VCC_CORE ISL95857 SIO_SLP_S4#
+VCC_GT +1.2V_MEM VDDQ
SY8210 VTT
DDR
+0.6V_DDR_VTT

PCH_PWROK
0.6V_DDR_VTT_ON
12
A
14 A

https://Dr-Bios.com
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Power Sequence
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Re v
1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date : Tuesday, March 05, 2019 Sheet 5 of 109
5 4 3 2 1
 5 4 3 2 1

For 2LANE EDP

+3.3V_RUN

2 1 CPU_DP1_CTRL_CLK
RC503 2.2K_0402_5% CPU@
2 1 CPU_DP1_CTRL_DATA UC1A
D D
RC178 2.2K_0402_5% AL5 AG4
2 1 CPU_DP2_CTRL_CLK <42> CPU_DP1_N0 AL6 DDI1_TXN_0 EDP_TXN_0 AG3 EDP_TXN0 <38>
RC176 2.2K_0402_5% <42> CPU_DP1_P0 AJ5 DDI1_TXP_0 EDP_TXP_0 AG2 EDP_TXP0 <38>
2 1 CPU_DP2_CTRL_DATA <42> CPU_DP1_N1 AJ6 DDI1_TXN_1 EDP_TXN_1 AG1 EDP_TXN1 <38>
RC502 2.2K_0402_5% <42> CPU_DP1_P1 AF6 DDI1_TXP_1 EDP_TXP_1 AJ4 EDP_TXP1 <38>
<42> CPU_DP1_N2 AF5 DDI1_TXN_2 EDP EDP_TXN_2 AJ3
<42> CPU_DP1_P2 AE5 DDI1_TXP_2 EDP_TXP_2 AJ2
<42> CPU_DP1_N3 AE6 DDI1_TXN_3 EDP_TXN_3 AJ1
<42> CPU_DP1_P3 DDI1_TXP_3 DDI EDP_TXP_3
AR AC4
<42> CPU_DP2_N0 AC3 DDI2_TXN_0 AH4
<42> CPU_DP2_P0 AC1 DDI2_TXP_0 EDP_AUX_N AH3 EDP_AUXN <38>
<42> CPU_DP2_N1 AC2 DDI2_TXN_1 EDP_AUX_P EDP_AUXP <38>
<42> CPU_DP2_P1 AE4 DDI2_TXP_1 AM7
<42> CPU_DP2_N2 AE3 DDI2_TXN_2 DISP_UTILS
<42> CPU_DP2_P2 AE1 DDI2_TXP_2 AC7 CPU_DP1_AUXN
<42> CPU_DP2_N3 AE2 DDI2_TXN_3 DDI1_AUX_N AC6 CPU_DP1_AUXP CPU_DP1_AUXN <42>
<42> CPU_DP2_P3 DDI2_TXP_3 DDI1_AUX_P AD4 CPU_DP2_AUXN CPU_DP1_AUXP <42> EDP_HPD 2 1
DDI2_AUX_N AD3 CPU_DP2_AUXP CPU_DP2_AUXN <42>
100K_0402_5% RC2
DDI2_AUX_P AG7 CPU_DP3_AUXN 1 CPU_DP2_AUXP <42>
DISPLAY SIDEBANDS DDI3_AUX_N AG6 CPU_DP3_AUXP 1 PAD~D @ T1
1 2 24.9_0402_1% EDP_COMP AM6 DDI3_AUX_P PAD~D @ T2
+1.0VS_VCCIO RC8
DISP_RCOMP
CPU_DP1_CTRL_CLK CC8 CN6 CPU_DP1_HPD
<42> CPU_DP1_CTRL_CLK CPU_DP1_CTRL_DATA CC9 GPP_E18/DPPB_CTRLCLK/CNV_BT_HOST_WAKE# GPP_E13/DDPB_HPD0/DISP_MISC0 CM6 CPU_DP2_HPD CPU_DP1_HPD <42>
COMPENSATION PU FOR eDP <42> CPU_DP1_CTRL_DATA GPP_E19/DPPB_CTRLDATA GPP_E14/DDPC_HPD1/DISP_MISC1 CP7 CPU_DP2_HPD <42>
All VREF traces should CAD Note: CPU_DP2_CTRL_CLK GPP_E15/DPPD_HPD2/DISP_MISC2
CH4 CP6
have 10 mil trace width Trace width=5 mils CPU_DP2_CTRL_DATA CH3 GPP_E20/DPPC_CTRLCLK GPP_E16/DPPE_HPD3/DISP_MISC3 CM7 EDP_HPD
GPP_E21/DPPC_CTRLDATA GPP_E17/EDP_HPD/DISP_MISC4 EDP_HPD <38>
Isolation Spacing=25mil,
CP4 CK11
Max length=100 mils. CN4 GPP_E22/DPPD_CTRLCLK EDP_BKLTEN CG11 PANEL_BKLEN <38>
GPP_E23/DPPD_CTRLDATA EDP_VDDEN CH11 ENVDD_PCH <38>
CR26 EDP_BKLTCTL EDP_BIA_PWM <38>
GPP_H17 CP26 GPP_H16/DDPF_CTRLCLK
GPP_H17/DDPF_CTRLDATA

+3.3V_ALW_PCH WHL-U42_BGA1528
C C
1 of 20
1 2 GPP_H17
@ RC101 20K_0402_5%

+3.3V_ALW_PCH
+3.3V_ALW_PCH

2
2
RC95
@ RC753 100K_0402_5%
This strap should sample HIGH. 10K_0402_5%
There should NOT be any on-board device

1
CPU@ driving it to opposite direction during strap sampling. TBT_RTD3_WAKE#

1
UC1I RTD3_CIO_PWR_EN

CNV_PRX_DTX_N0 CPU_C10_GATE#

2
CR30 CNVio CN27
<52> CNV_PRX_DTX_N0 CNV_PRX_DTX_P0 CP30 CNV_WR_D0N GPP_H18/CPU_C10_GATE# CPU_C10_GATE# <17,87>
<52> CNV_PRX_DTX_P0 @ RC454
CNV_WR_D0P CM27
CNV_PRX_DTX_N1 GPP_H19/TIMESYNC_0 20K_0402_5%
CM30
<52> CNV_PRX_DTX_N1 CNV_PRX_DTX_P1 CN30 CNV_WR_D1N CF25 GPP_H21
<52> CNV_PRX_DTX_P1 CNV_WR_D1P GPP_H21/XTAL_FREQ_SELECT

1
CNV_PTX_DRX_N0 CN32 CN26 RTD3_CIO_PWR_EN
<52> CNV_PTX_DRX_N0 CNV_PTX_DRX_P0 CM32 CNV_WT_D0N GPP_H22 CM26 GPP_H23 RTD3_CIO_PWR_EN <42>
<52> CNV_PTX_DRX_P0 CNV_WT_D0P GPP_H23 CK17
CNV_PTX_DRX_N1 CP33 GPP_F10
<52> CNV_PTX_DRX_N1 CNV_PTX_DRX_P1 CN33 CNV_WT_D1N BV35 TBT_RTD3_WAKE#
<52> CNV_PTX_DRX_P1 CNV_WT_D1P GPD7 CN20 TBT_RTD3_WAKE# <42>
+3.3V_ALW_PCH
CLK_CNV_PRX_DTX_N CN31 GPP_F3 +3.3V_ALW_PCH
<52> CLK_CNV_PRX_DTX_N CLK_CNV_PRX_DTX_P CP31 CNV_WR_CLKN CG25 TBT_FORCE_PWR
B
2 1 PCH_TBT_PERST# <52> CLK_CNV_PRX_DTX_P CLK_CNV_PTX_DRX_N CP34 CNV_WR_CLKP GPP_D4/IMGCLKOUT0/BK4/SBK4 CH25 TBT_FORCE_PWR <42> B
<52> CLK_CNV_PTX_DRX_N CLK_CNV_PTX_DRX_P CN34 CNV_WT_CLKN GPP_H20/IMGCLKOUT_1
RTD3@ RC557 10K_0402_5%

2
<52> CLK_CNV_PTX_DRX_P CNV_WT_CLKP CR20 MEM_CONFIG0 1
GPP_F12/EMMC_DATA0 PAD~D @T408
150_0402_1% 1 2 RC448 CNV_WT_RCOMP CP32 CM20 MEM_CONFIG1 1 @T409
RC443
CR32 CNV_WT_RCOMP_0 GPP_F13/EMMC_DATA1 CN19 MEM_CONFIG2 1 PAD~D 4.7K_0402_5%
CNV_COEX3 CNV_WT_RCOMP_1 GPP_F14/EMMC_DATA2 MEM_CONFIG3 PAD~D @T410
<52> CNV_COEX3 CP20 EMMC CM19 1 @T411
2 1 PCH_TBT_PERST# GPP_F0/CNV_PA_BLANKING GPP_F15/EMMC_DATA3 CN18 MEM_CONFIG4 1 PAD~D

1
GPP_F16/EMMC_DATA4 PAD~D @T412 GPP_H21
@ RC754 10K_0402_5% CK19 CR18
CG17 GPP_F1 GPP_F17/EMMC_DATA5 CP18
GPP_F2 GPP_F18/EMMC_DATA6 CM18 LOW: 38.4/19.2MHZ (DEFAULT)

2
PCH_TBT_PERST# CR14 GPP_F19/EMMC_DATA7
HIGH: 24MHZ
<42> PCH_TBT_PERST# SBIOS_TX CP14 GPP_C8/UART0_RXD @ RC444
<79> SBIOS_TX TYPEC_CON_SEL1 CN14 GPP_C9/UART0_TXD CM16 20K_0402_5%
TYPEC_CON_SEL2 CM14 GPP_C10/UART0_RTS# GPP_F20/EMMC_RCLK CP16
GPP_C11/UART0_CTS# GPP_F21/EMMC_CLK CR16 Jony_01/16 : CK15 - Keep 200 ohm

1
CNV_COEX2 CJ17 GPP_F11/EMMC_CMD CN16 575962_WHL-U_DDR4_RVP_Sch_Rev0p5.pdf
<52> CNV_COEX2 CNV_COEX1 CH17 GPP_F8/CNV_MFUART2_RXD GPP_F22/EMMC_RESET#

Reserve
<52> CNV_COEX1 GPP_F9/CNV_MFUART2_TXD CK15 EMMC_RCOMP 1 2
CF17 EMMC_RCOMP RC10 200_0402_1%
GPP_F23/A4WP_PRESENT
+3.3V_ALW_PCH
+3.3V_ALW_PCH +3.3V_ALW_PCH WHL-U42_BGA1528
0 = Master Attached Flash Sharing

2
9 of 20 (MAFS) enabled. (Default)
2

@ RC537 1 = Slave Attached Flash Sharing

4.7K_0402_5% (SAFS) enabled.
@ RC744 @ RC743
10K_0402_5% 10K_0402_5%

1
GPP_H23
1

2
TYPEC_CON_SEL1 TYPEC_CON_SEL2
@ RC446
1

20K_0402_5%

@ RC745 @ RC63

1
10K_0402_5% 10K_0402_5%
2

A A

Vendor JAE FOXCON TBD TBD

TYPEC_CON_SEL1 LOW LOW HIGH HIGH

DELL CONFIDENTIAL/PROPRIETARY
TYPEC_CON_SEL2 LOW HIGH LOW HIGH
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title

https://Dr-Bios.com
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT CPU(1/14)DDI,EDP,CSI2,EMMC
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 6 of 109
5 4 3 2 1
 5 4 3 2 1

DDR4, Ballout for side by side(Non-Interleave)

<23> DDR_A_DQS#[0..7] <24> DDR_B_DQS#[0..7]

D D
<23> DDR_A_D[0..63] <24> DDR_B_D[0..63]

<23> DDR_A_DQS[0..7] <24> DDR_B_DQS[0..7]

<23> DDR_A_MA[0..16] <24> DDR_B_MA[0..16]

CPU@
UC1B CPU@
UC1C
DDR_A_D0 A26 Interleave / Non-Interleaved

DDR_A_D1 D26 DDR0_DQ_0/DDR0_DQ_0 LPDDR3 / DDR4

V32 DDR_A_CLK#0 DDR_A_D16 J22
lnterleave /
Non-lnterleaved
LPDDR3 / DDR4
AF28 DDR_B_CLK#0
DDR_A_D2 DDR0_DQ_1/DDR0_DQ_1 DDR0_CKN_0/DDR0_CKN_0 DDR_A_CLK0 DDR_A_CLK#0 <23> DDR_A_D17 DDR1_DQ_0/DDR0_DQ_16 DDR1_CKN_0/DDR1_CKN_0 DDR_B_CLK0 DDR_B_CLK#0 <24>
D28 V31 H25 AF29
DDR_A_D3 DDR0_DQ_2/DDR0_DQ_2 DDR0_CKP_0/DDR0_CKP_0 DDR_A_CLK#1 DDR_A_CLK0 <23> DDR_A_D18 DDR1_DQ_1/DDR0_DQ_17 DDR1_CKP_0/DDR1_CKP_0 DDR_B_CLK#1 DDR_B_CLK0 <24>
C28 T32 G22 AE28
DDR_A_D4 DDR0_DQ_3/DDR0_DQ_3 DDR0_CKN_1/DDR0_CKN_1 DDR_A_CLK1 DDR_A_CLK#1 <23> DDR_A_D19 DDR1_DQ_2/DDR0_DQ_18 DDR1_CKN_1/DDR1_CKN_1 DDR_B_CLK1 DDR_B_CLK#1 <24>
B26 T31 H22 AE29
DDR_A_D5 DDR0_DQ_4/DDR0_DQ_4 DDR0_CKP_1/DDR0_CKP_1 DDR_A_CLK1 <23> DDR_A_D20 DDR1_DQ_3/DDR0_DQ_19 DDR1_CKP_1/DDR1_CKP_1 DDR_B_CLK1 <24>
C26 F25
DDR_A_D6 B28 DDR0_DQ_5/DDR0_DQ_5 U36 DDR_A_CKE0 DDR_A_D21 J25 DDR1_DQ_4/DDR0_DQ_20 T28 DDR_B_CKE0
DDR_A_D7 DDR0_DQ_6/DDR0_DQ_6 DDR0_CKE_0/DDR0_CKE_0 DDR_A_CKE1 DDR_A_CKE0 <23> DDR_A_D22 DDR1_DQ_5/DDR0_DQ_21 DDR1_CKE_0/DDR1_CKE_0 DDR_B_CKE1 DDR_B_CKE0 <24>
A28 U37 G25 T29
DDR_A_CKE1 <23>
1 DDR_B_CKE1
DDR_A_D8 DDR0_DQ_7/DDR0_DQ_7 DDR0_CKE_1/DDR0_CKE_1 DDR_A_CKE2 1 DDR_A_D23 DDR1_DQ_6/DDR0_DQ_22 DDR1_CKE_1/DDR1_CKE_1 <24>
B30 U34 F22 V28
DDR_A_D9 DDR0_DQ_8/DDR0_DQ_8 DDR0_CKE_2/NC DDR_A_CKE3 1 PAD~D @ T351 DDR_A_D24 DDR1_DQ_7/DDR0_DQ_23 DDR1_CKE_2/NC PAD~D @ T353
D30 U35 D22 V29 1
DDR_A_D10 DDR0_DQ_9/DDR0_DQ_9 DDR0_CKE_3/NC PAD~D @ T350 DDR_A_D25 DDR1_DQ_8/DDR0_DQ_24 DDR1_CKE_3/NC PAD~D @ T354
B33 C22
DDR_A_D11 D32 DDR0_DQ_10/DDR0_DQ_10 AE32 DDR_A_CS#0 DDR_A_D26 C24 DDR1_DQ_9/DDR0_DQ_25 AL37 DDR_B_CS#0
DDR_A_D12 DDR0_DQ_11/DDR0_DQ_11 DDR0_CS#_0/DDR0_CS#_0 DDR_A_CS#1 DDR_A_CS#0 <23> DDR_A_D27 DDR1_DQ_10/DDR0_DQ_26 DDR1_CS#_0/DDR1_CS#_0 DDR_B_CS#1 DDR_B_CS#0 <24>
A30 AF32 D24 AL35
DDR_A_D13 DDR0_DQ_12/DDR0_DQ_12 DDR0_CS#_1/DDR0_CS#_1 DDR_A_ODT0 DDR_A_CS#1 <23> DDR_A_D28 DDR1_DQ_11/DDR0_DQ_27 DDR1_CS#_1/DDR1_CS#_1 DDR_B_ODT0 DDR_B_CS#1 <24>
C30 AE31 A22 AL36
DDR_A_D14 DDR0_DQ_13/DDR0_DQ_13 DDR0_ODT_0/DDR0_ODT_0 DDR_A_ODT1 DDR_A_ODT0 <23> DDR_A_D29 DDR1_DQ_12/DDR0_DQ_28 DDR1_ODT_0/DDR1_ODT_0 DDR_B_ODT1 DDR_B_ODT0 <24>
B32 AF31 B22 AL34
DDR_A_D15 DDR0_DQ_14/DDR0_DQ_14 NC/DDR0_ODT_1 DDR_A_ODT1 <23> DDR_A_D30 DDR1_DQ_13/DDR0_DQ_29 NC/DDR1_ODT_1 DDR_B_ODT1 <24>
C32 A24 AG36
DDR_A_D32 DDR0_DQ_15/DDR0_DQ_15 DDR_A_D31 DDR1_DQ_14/DDR0_DQ_30 DDR1_CAB_9/DDR1_MA_0 DDR_B_MA0 <24>
H37 AC37 B24 AG35
DDR_A_D33 DDR0_DQ_16/DDR0_DQ_32 DDR0_CAB_9/DDR0_MA_0 DDR_A_MA0 <23> DDR_A_D48 DDR1_DQ_15/DDR0_DQ_31 DDR1_CAB_8/DDR1_MA_1 DDR_B_MA1 <24>
H34 AC36 G31 AF34
DDR_A_D34 DDR0_DQ_17/DDR0_DQ_33 DDR0_CAB_8/DDR0_MA_1 DDR_A_MA1 <23> DDR_A_D49 DDR1_DQ_16/DDR0_DQ_48 DDR1_CAB_5/DDR1_MA_2 DDR_B_MA2 <24>
K34 AC34 G32 AG37
DDR_A_D35 DDR0_DQ_18/DDR0_DQ_34 DDR0_CAB_5/DDR0_MA_2 DDR_A_MA2 <23> DDR_A_D50 DDR1_DQ_17/DDR0_DQ_49 NC/DDR1_MA_3 DDR_B_MA3 <24>
K35 AC35 H29 AE35
DDR_A_D36 DDR0_DQ_19/DDR0_DQ_35 NC/DDR0_MA_3 DDR_A_MA3 <23> DDR_A_D51 DDR1_DQ_18/DDR0_DQ_50 NC/DDR1_MA_4 DDR_B_MA4 <24>
H36 AA35 H28 AF35
DDR_A_D37 DDR0_DQ_20/DDR0_DQ_36 NC/DDR0_MA_4 DDR_A_MA4 <23> DDR_A_D52 DDR1_DQ_19/DDR0_DQ_51 DDR1_CAA_0/DDR1_MA_5 DDR_B_MA5 <24>
H35 AB35 G28 AE37
DDR_A_D38 DDR0_DQ_21/DDR0_DQ_37 DDR0_CAA_0/DDR0_MA_5 DDR_A_MA5 <23> DDR_A_D53 DDR1_DQ_20/DDR0_DQ_52 DDR1_CAA_2/DDR1_MA_6 DDR_B_MA6 <24>
K36 AA37 G29 AC29
DDR_A_D39 DDR0_DQ_22/DDR0_DQ_38 DDR0_CAA_2/DDR0_MA_6 DDR_A_MA6 <23> DDR_A_D54 DDR1_DQ_21/DDR0_DQ_53 DDR1_CAA_4/DDR1_MA_7 DDR_B_MA7 <24>
K37 AA36 H31 AE36
DDR_A_D40 DDR0_DQ_23/DDR0_DQ_39 DDR0_CAA_4/DDR0_MA_7 DDR_A_MA7 <23> DDR_A_D55 DDR1_DQ_22/DDR0_DQ_54 DDR1_CAA_3/DDR1_MA_8 DDR_B_MA8 <24>
N36 AB34 H32 AB29
DDR_A_D41 DDR0_DQ_24/DDR0_DQ_40 DDR0_CAA_3/DDR0_MA_8 DDR_A_MA8 <23> DDR_A_D56 DDR1_DQ_23/DDR0_DQ_55 DDR1_CAA_1/DDR1_MA_9 DDR_B_MA9 <24>
N34 W36 L31 AG34
DDR_A_D42 DDR0_DQ_25/DDR0_DQ_41 DDR0_CAA_1/DDR0_MA_9 DDR_A_MA9 <23> DDR_A_D57 DDR1_DQ_24/DDR0_DQ_56 DDR1_CAB_7/DDR1_MA_10 DDR_B_MA10 <24>
R37 Y31 L32 AC28
C DDR_A_D43 DDR0_DQ_26/DDR0_DQ_42 DDR0_CAB_7/DDR0_MA_10 DDR_A_MA10 <23> DDR_A_D58 DDR1_DQ_25/DDR0_DQ_57 DDR1_CAA_7/DDR1_MA_11 DDR_B_MA11 <24> C
R34 W34 N29 AB28
DDR_A_D44 DDR0_DQ_27/DDR0_DQ_43 DDR0_CAA_7/DDR0_MA_11 DDR_A_MA11 <23> DDR_A_D59 DDR1_DQ_26/DDR0_DQ_58 DDR1_CAA_6/DDR1_MA_12 DDR_B_MA12 <24>
N37 AA34 N28 AK35
DDR_A_D45 DDR0_DQ_28/DDR0_DQ_44 DDR0_CAA_6/DDR0_MA_12 DDR_A_MA12 <23> DDR_A_D60 DDR1_DQ_27/DDR0_DQ_59 DDR1_CAB_0/DDR1_MA_13 DDR_B_MA13 <24>
N35 AC32 L28
DDR_A_D46 DDR0_DQ_29/DDR0_DQ_45 DDR0_CAB_0/DDR0_MA_13 DDR_A_MA13 <23> DDR_A_D61 DDR1_DQ_28/DDR0_DQ_60
R36 L29 AJ35
DDR_A_D47 DDR0_DQ_30/DDR0_DQ_46 DDR_A_D62 DDR1_DQ_29/DDR0_DQ_61 DDR1_CAB_2/DDR1_MA_14 DDR_B_MA14 <24>
R35 AC31 N31 AK34
DDR_B_D0 DDR0_DQ_31/DDR0_DQ_47 DDR0_CAB_2/DDR0_MA_14 DDR_A_MA14 <23> DDR_A_D63 DDR1_DQ_30/DDR0_DQ_62 DDR1_CAB_1/DDR1_MA_15 DDR_B_MA15 <24>
AN35 AB32 N32 AJ34
DDR_B_D1 DDR0_DQ_32/DDR1_DQ_0 DDR0_CAB_1/DDR0_MA_15 DDR_A_MA15 <23> DDR_B_D16 DDR1_DQ_31/DDR0_DQ_63 DDR1_CAB_3/DDR1_MA_16 DDR_B_MA16 <24>
AN34 Y32 AJ29
DDR_B_D2 DDR0_DQ_33/DDR1_DQ_1 DDR0_CAB_3/DDR0_MA_16 DDR_A_MA16 <23> DDR_B_D17 DDR1_DQ_32/DDR1_DQ_16
AR35 AJ30 AJ37
DDR_B_D3 DDR0_DQ_34/DDR1_DQ_2 DDR_B_D18 DDR1_DQ_33/DDR1_DQ_17 DDR1_CAB_4/DDR1_BA_0 DDR_B_BA0 <24>
AR34 W32 AM32 AJ36
DDR_B_D4 DDR0_DQ_35/DDR1_DQ_3 DDR0_CAB_4/DDR0_BA_0 DDR_A_BA0 <23> DDR_B_D19 DDR1_DQ_34/DDR1_DQ_18 DDR1_CAB_6/DDR1_BA_1 DDR_B_BA1 <24>
AN37 AB31 AM31 W29
DDR_B_D5 DDR0_DQ_36/DDR1_DQ_4 DDR0_CAB_6/DDR0_BA_1 DDR_A_BA1 <23> DDR_B_D20 DDR1_DQ_35/DDR1_DQ_19 DDR1_CAA_5/DDR1_BG_0 DDR_B_BG0 <24>
AN36 V34 AM30
DDR_B_D6 DDR0_DQ_37/DDR1_DQ_5 DDR0_CAA_5/DDR0_BG_0 DDR_A_BG0 <23> DDR_B_D21 DDR1_DQ_36/DDR1_DQ_20
AR36 AM29 Y28
DDR_B_D7 DDR0_DQ_38/DDR1_DQ_6 DDR_B_D22 DDR1_DQ_37/DDR1_DQ_21 DDR1_CAA_9/DDR1_BG_1 DDR_B_BG1 <24>
AR37 V35 AJ31 W28
DDR_B_D8 DDR0_DQ_39/DDR1_DQ_7 DDR0_CAA_8/DDR0_ACT# DDR_A_ACT# <23> DDR_B_D23 DDR1_DQ_38/DDR1_DQ_22 DDR1_CAA_8/DDR1_ACT# DDR_B_ACT# <24>
AU35 W35 AJ32
DDR_B_D9 DDR0_DQ_40/DDR1_DQ_8 DDR0_CAA_9/DDR0_BG_1 DDR_A_BG1 <23> DDR_B_D24 DDR1_DQ_39/DDR1_DQ_23 lnterleave / Non-lnterleaved
AU34 AR31 H24
DDR_B_D10 DDR0_DQ_41/DDR1_DQ_9 Interleave / Non-Interleaved DDR_B_D25 DDR1_DQ_40/DDR1_DQ_24 DDR1_DQSN_0/DDR0_DQSN_2 DDR_A_DQS#2 <23>
AW35 C27 AR32 G24
DDR_B_D11 DDR0_DQ_42/DDR1_DQ_10 DDR0_DQSN_0/DDR0_DQSN_0 DDR_A_DQS#0 <23> DDR_B_D26 DDR1_DQ_41/DDR1_DQ_25 DDR1_DQSP_0/DDR0_DQSP_2 DDR_A_DQS2 <23>
AW34 D27 AV30 C23
DDR_B_D12 DDR0_DQ_43/DDR1_DQ_11 DDR0_DQSP_0/DDR0_DQSP_0 DDR_A_DQS0 <23> DDR_B_D27 DDR1_DQ_42/DDR1_DQ_26 DDR1_DQSN_1/DDR0_DQSN_3 DDR_A_DQS#3 <23>
AU37 D31 AV29 D23
DDR_B_D13 DDR0_DQ_44/DDR1_DQ_12 DDR0_DQSN_1/DDR0_DQSN_1 DDR_A_DQS#1 <23> DDR_B_D28 DDR1_DQ_43/DDR1_DQ_27 DDR1_DQSP_1/DDR0_DQSP_3 DDR_A_DQS3 <23>
AU36 C31 AR30 G30
DDR_B_D14 DDR0_DQ_45/DDR1_DQ_13 DDR0_DQSP_1/DDR0_DQSP_1 DDR_A_DQS1 <23> DDR_B_D29 DDR1_DQ_44/DDR1_DQ_28 DDR1_DQSN_2/DDR0_DQSN_6 DDR_A_DQS#6 <23>
AW36 J35 AR29 H30
DDR_B_D15 DDR0_DQ_46/DDR1_DQ_14 DDR0_DQSN_2/DDR0_DQSN_4 DDR_A_DQS#4 <23> DDR_B_D30 DDR1_DQ_45/DDR1_DQ_29 DDR1_DQSP_2/DDR0_DQSP_6 DDR_A_DQS6 <23>
AW37 J34 AV32 L30
DDR_B_D32 DDR0_DQ_47/DDR1_DQ_15 DDR0_DQSP_2/DDR0_DQSP_4 DDR_A_DQS4 <23> DDR_B_D31 DDR1_DQ_46/DDR1_DQ_30 DDR1_DQSN_3/DDR0_DQSN_7 DDR_A_DQS#7 <23>
BA35 P34 AV31 N30
DDR_B_D33 DDR0_DQ_48/DDR1_DQ_32 DDR0_DQSN_3/DDR0_DQSN_5 DDR_A_DQS#5 <23> DDR_B_D48 DDR1_DQ_47/DDR1_DQ_31 DDR1_DQSP_3/DDR0_DQSP_7 DDR_A_DQS7 <23>
BA34 P35 BA32 AL31
DDR_B_D34 DDR0_DQ_49/DDR1_DQ_33 DDR0_DQSP_3/DDR0_DQSP_5 DDR_A_DQS5 <23> DDR_B_D49 DDR1_DQ_48/DDR1_DQ_48 DDR1_DQSN_4/DDR1_DQSN_2 DDR_B_DQS#2 <24>
BC35 AP35 BA31 AL30
DDR_B_D35 DDR0_DQ_50/DDR1_DQ_34 DDR0_DQSN_4/DDR1_DQSN_0 DDR_B_DQS#0 <24> DDR_B_D50 DDR1_DQ_49/DDR1_DQ_49 DDR1_DQSP_4/DDR1_DQSP_2 DDR_B_DQS2 <24>
BC34 AP34 BD31 AU31
DDR_B_D36 DDR0_DQ_51/DDR1_DQ_35 DDR0_DQSP_4/DDR1_DQSP_0 DDR_B_DQS0 <24> DDR_B_D51 DDR1_DQ_50/DDR1_DQ_50 DDR1_DQSN_5/DDR1_DQSN_3 DDR_B_DQS#3 <24>
BA37 AV34 BD32 AU30
DDR_B_D37 DDR0_DQ_52/DDR1_DQ_36 DDR0_DQSN_5/DDR1_DQSN_1 DDR_B_DQS#1 <24> DDR_B_D52 DDR1_DQ_51/DDR1_DQ_51 DDR1_DQSP_5/DDR1_DQSP_3 DDR_B_DQS3 <24>
BA36 AV35 BA30 BC31
DDR_B_D38 DDR0_DQ_53/DDR1_DQ_37 DDR0_DQSP_5/DDR1_DQSP_1 DDR_B_DQS1 <24> DDR_B_D53 DDR1_DQ_52/DDR1_DQ_52 DDR1_DQSN_6/DDR1_DQSN_6 DDR_B_DQS#6 <24>
BC36 BB35 BA29 BC30
DDR_B_D39 DDR0_DQ_54/DDR1_DQ_38 DDR0_DQSN_6/DDR1_DQSN_4 DDR_B_DQS#4 <24> DDR_B_D54 DDR1_DQ_53/DDR1_DQ_53 DDR1_DQSP_6/DDR1_DQSP_6 DDR_B_DQS6 <24>
BC37 BB34 BD29 BH31
DDR_B_D40 DDR0_DQ_55/DDR1_DQ_39 DDR0_DQSP_6/DDR1_DQSP_4 DDR_B_DQS4 <24> DDR_B_D55 DDR1_DQ_54/DDR1_DQ_54 DDR1_DQSN_7/DDR1_DQSN_7 DDR_B_DQS#7 <24>
BE35 BF34 BD30 BH30
DDR_B_D41 DDR0_DQ_56/DDR1_DQ_40 DDR0_DQSN_7/DDR1_DQSN_5 DDR_B_DQS#5 <24> DDR_B_D56 DDR1_DQ_55/DDR1_DQ_55 DDR1_DQSP_7/DDR1_DQSP_7 DDR_B_DQS7 <24>
BE34 BF35 BG31
DDR_B_D42 DDR0_DQ_57/DDR1_DQ_41 DDR0_DQSP_7/DDR1_DQSP_5 DDR_B_DQS5 <24> DDR_B_D57 DDR1_DQ_56/DDR1_DQ_56 DDR_B_ALERT#
BG35 BG32 Y29
DDR_B_D43 DDR0_DQ_58/DDR1_DQ_42 LPDDR3 / DDR4 DDR_B_D58 DDR1_DQ_57/DDR1_DQ_57 NC/DDR1_ALERT# DDR_B_PARITY DDR_B_ALERT# <24>DDR1_PAR,DDR1_ALERT#
BG34 W37 BK32 AE34
DDR_B_D44 DDR0_DQ_59/DDR1_DQ_43 NC/DDR0_ALERT# DDR_A_ALERT# <23>DDR0_PAR,DDR0_ALERT# DDR_B_D59 DDR1_DQ_58/DDR1_DQ_58 NC/DDR1_PAR DDR_DRAMRST# DDR_B_PARITY <24> for DDR4
BE37 W31 BK31 BU31
DDR_B_D45 DDR0_DQ_60/DDR1_DQ_44 NC/DDR0_PAR DDR_A_PARITY <23>for DDR4 DDR_B_D60 DDR1_DQ_59/DDR1_DQ_59 DRAM_RESET# DDR_DRAMRST# <23>
BE36 BG29
DDR_B_D46 BG36 DDR0_DQ_61/DDR1_DQ_45 F36 DDR_B_D61 BG30 DDR1_DQ_60/DDR1_DQ_60 BN28 SM_RCOMP0
DDR_B_D47 DDR0_DQ_62/DDR1_DQ_46 DDR_VREF_CA +DDR_VREF_CA DDR_B_D62 DDR1_DQ_61/DDR1_DQ_61 DDR_RCOMP_0 SM_RCOMP1
BG37 D35 BK30 BN27
DDR0_DQ_63/DDR1_DQ_47 DDR0_VREF_DQ_0 D37 DDR_B_D63 BK29 DDR1_DQ_62/DDR1_DQ_62 DDR_RCOMP_1 BN29 SM_RCOMP2
DDR0_VREF_DQ_1 E36 DDR1_DQ_63/DDR1_DQ_63 DDR_RCOMP_2
DDR1_VREF_DQ +DDR_VREF_B_DQ
C35
DDR_VTT_CTL DDR_VTT_CTRL <23>
W HL-U42_BGA1528
B W HL-U42_BGA1528 B
3 of 20
2 of 20

Hank3/5:575962_WHL_DDR4_RVP_RN_TDK_Rev0p7.pdf page12,keep setting

DDR4 COMPENSATION SIGNALS

SM_RCOMP0 RC5 1 2 121_0402_1%
SM_RCOMP1 RC504 1 2 80.6_0402_1%
SM_RCOMP2 RC7 1 2 100_0402_1%

A A
CAD Note:
Trace width=12~15 mil, Spacing=20 mils
Max trace length= 500 mil

DELL CONFIDENTIAL/PROPRIETARY

https://Dr-Bios.com
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT CPU(2/14)DDR4
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 7 of 109
5 4 3 2 1
 5 4 3 2 1

Merion Limit height

QC2 change to SB000014O00 H=0.6mm(MAX)
SPI_MOSI= SPI_IO0
SPI_MISO= SPI_IO1 CPU@
PCH EDS R0.7 p.235~236 UC1E +3.3V_RUN
PCH_SPI_CLK MEM_SMBCLK DDR_XDP_WAN_SMBCLK <23,24,79>
CH37 CK14

1
PCH_SPI_D1 CF37 SPI0_CLK GPP_C0/SMBCLK CH15 MEM_SMBDATA QC2
CXDP@ RC505 1 2 1K_0402_1% PCH_SPI_D0 CF36 SPI0_MISO GPP_C1/SMBDATA CJ15 GPP_C2 2 S1
<79> PCH_SPI_DO_XDP PCH_SPI_D2 SPI0_MOSI GPP_C2/SMBALERT# MEM_SMBCLK
CXDP@ RC11 1 2 1K_0402_1% CF34 G1
D1 6
<79> PCH_SPI_DO2_XDP PCH_SPI_D3 CG34 SPI0_IO2 SPI - FLASH CH14 SML0_SMBCLK 4
PCH_SPI_CS#0 CG36 SPI0_IO3 SMBUS , SMLINK GPP_C3/SML0CLK CF15 SML0_SMBDATA Merion no RJ45 LAN port 5 S2 DDR_XDP_WAN_SMBDAT <23,24,79>
PCH_SPI_CS#1 CG35 SPI0_CS0# GPP_C4/SML0DATA CG15 GPP_C5 G2
1219 Change D2
PCH_SPI_CS#2 CH34 SPI0_CS1# GPP_C5/SML0ALERT# PJX138K_SOT563-6
<66> PCH_SPI_CS#2

3
SPI0_CS2# CN15 SML1_SMBCLK
GPP_C6/SML1CLK SML1_SMBDATA SML1_SMBCLK <58> MEM_SMBDATA
CM15
D GPP_C7/SML1DATA GPP_B23 SML1_SMBDATA <58> D
1031 change CF20 CC34
CG22 GPP_D1/SPI1_CLK/BK1/SBK1 GPP_B23/SML1ALERT#/PCHHOT#
RTC_DET# CF22 GPP_D2/SPI1_MISO_IO1/BK2/SBK2
<83> RTC_DET# GPP_D3/SPI1_MOSI_IO0/BK3/SBK3 ESPI_IO0_R
CG23 CA29 RC366 1 2 15_0402_5%
GPP_D21/SPI1_IO2 SPI - TOUCH GPP_A1/LAD0/ESPI_IO0 ESPI_IO1_R ESPI_IO0 <58,79>
CH23 BY29 RC367 1 2 15_0402_5%
GPP_D22/SPI1_IO3 GPP_A2/LAD1/ESPI_IO1 ESPI_IO2_R ESPI_IO1 <58,79>
CG20 BY27 RC368 1 2 15_0402_5% ESPI_IO2 <58,79>
<70> MEDIACARD_IRQ# GPP_D0/SPI1_CS0#/BK0/SBK0 GPP_A3/LAD2/ESPI_IO2 BV27 ESPI_IO3_R RC369 1 2 15_0402_5%
GPP_A4/LAD3/ESPI_IO3 ESPI_IO3 <58,79>
CA28
GPP_A5/LFRAME#/ESPI_CS# CA27 ESPI_CS# <58,79> RVP 15 ohm
LPC , ESPI GPP_A14/SUS_STAT#/ESPI_RESET# ESPI_RESET# <58,79> 575962_WHL-U_DDR4_RVP_Sch_Rev0p5.pdf
CH7
<52> PCH_CL_CLK1 CH8 CL_CLK
<52> PCH_CL_DATA1 CL_DATA C LINK ESPI_CLK
CH9 BV32 RC19 1 2 33_0402_5% EMI@
<52> PCH_CL_RST1# CL_RST# GPP_A9/CLKOUT_LPC0/ESPI_CLK BV30 ESPI_CLK_5105 <58,79>
BV29 GPP_A10/CLKOUT_LPC1 BY30 GPP_A8
ESPI_ALERT# BV28 GPP_A0/RCIN#/TIME_SYNC1 GPP_A8/CLKRUN#
<58> ESPI_ALERT# GPP_A6/SERIRQ
+1.8V_PRIM
+3.3V_RUN
W HL-U42_BGA1528

ESPI_ALERT# 5 of 20 DDR_XDP_WAN_SMBDAT 1 2
RC244 1 2 10K_0402_1%
RC318 2.2K_0402_5%
DDR_XDP_WAN_SMBCLK 1 2
RC319 2.2K_0402_5%
+3.3V_ALW _PCH +3.3V_ALW _PCH GPP_A8 1 2
RF Request @ RC849 8.2K_0402_5%

1
ESPI_CLK_5105 1 2
RC94 RC61 @RF@ CC316 33P_0402_50V8J
100K_0402_5% 100K_0402_5%
+3.3V_ALW_PCH

2
PCH_SPI_D0 PCH_SPI_D2
SML0_SMBCLK 1 2

1
@RF@ CC318 33P_0402_50V8J MEM_SMBCLK 1 2
@ RC518 @ RC519 RC12 1K_0402_5%
4.7K_0402_5% 4.7K_0402_5% SML1_SMBCLK 1 2 MEM_SMBDATA 1 2
@RF@ CC319 33P_0402_50V8J RC14 1K_0402_5%
SML1_SMBCLK 1 2

2
PLACE RC61 AND RC519 CLOS MEM_SMBCLK 1 2 RC15 1K_0402_5%
TO THE SPI SIGNAL TO AVOID STUB @RF@ CC320 33P_0402_50V8J SML1_SMBDATA 1 2
WEAK INTERNAL PU WEAK INTERNAL PU RC507 1K_0402_5%
SML0_SMBCLK 1 2
C BOOT HALT CONSENT STRAP @ RC347 499_0402_1%
C
SML0_SMBDATA 1 2
HIGH Disabled HIGH Disabled Place close CPU side @ RC348 499_0402_1%
LOW Enabled LOW Enabled RTC_DET# 1 2
2 1 ESPI_RESET# RC866 10K_0201_5%
@ RC833 100K_0402_5%
1031 change
2 1 PCH_SPI_CLK
RC96 100K_0402_5% +3.3V_ALW _PCH
566439_CNL_PCH_UY_EDS_Vol_1_Rev_1.1.pdf

1
For signal deglitch, refer to 575412_WHL_U_PDG rev0p8 RC62 External pull-up is required. Recommend 100K if pulled
100K_0402_5% up to 3.3V or 75K if pulled up to 1.8V. This strap should sample HIGH.
There should NOT be any on-board device driving it to opposite direction
during strap sampling.

2
PCH_SPI_D3

1
@ RC515
4.7K_0402_5%

2
PLACE RC62 AND RC515 CLOS
TO THE SPI SIGNAL TO AVOID STUB
WEAK INTERNAL PU
A0 PERSONALITY STRAP
HIGH Disabled
LOW Enabled

+3.3V_ALW_PCH
Follow RVP pull up change to 4.7K
GPP_C2
Pop option at P.102 1 2
Pop option at P.102 RC266 4.7K_0402_5%

B
SOFTWARE TAA TLS CONFIDENTIALITY
B

VPRO PDG P.296 R1 50 ohm

PCH_SPI_D1_R1 1 2 PCH_SPI_D1_0_R
<66> PCH_SPI_D1_R1 HIGH ENABLE
VPRO@ RC734 49.9_0201_1%
PCH_SPI_D0_R1 1 2 PCH_SPI_D0_0_R LOW(DEFAULT) DISABLE
<66> PCH_SPI_D0_R1 VPRO PDG P.296 R2 5 ohm
VPRO@ RC570 49.9_0201_1%
PCH_SPI_CLK_R1 1 2 PCH_SPI_CLK_0_R NVPRO PDG P.298 R2 10 ohm JSPI1 CONN@
<66> PCH_SPI_CLK_R1 VPRO@ RC571 49.9_0201_1% 1 2 PCH_SPI_CS#1_R1 1
PCH_SPI_D3_R1 1 2 PCH_SPI_D3_0_R NVPRO@ RC24 0_0201_5% PCH_SPI_CS#1 2 1 +3.3V_ALW_PCH
VPRO@ RC572 49.9_0201_1% 1 2 PCH_SPI_D0_R1 3 2
VPRO@ RC25 4.99_0201_1% PCH_SPI_D0 4 3
NVPRO follow PDG P.298 R1 33 ohm 1 2 PCH_SPI_D1_R1 5 4
PCH_SPI_D1_R1 1 2 PCH_SPI_D1_1_R VPRO@ RC26 4.99_0201_1% PCH_SPI_D1 6 5 GPP_C5 RC277 1 2 4.7K_0402_5%
NVPRO@ RC573 33_0201_1% 1 2 PCH_SPI_CLK_R1 7 6
PCH_SPI_D0_R1 PCH_SPI_D0_1_R 7 GPP_C5 @ RC397 1 2 20K_0402_5%
1 2 VPRO@ RC27 4.99_0201_1% PCH_SPI_CLK 8
NVPRO@ RC574 33_0201_1% 1 2 PCH_SPI_CS#0_R1 9 8
PCH_SPI_CLK_R1 1 2 PCH_SPI_CLK_1_R @ RC28 0_0201_5% PCH_SPI_CS#0 10 9
NVPRO@ RC575 33_0201_1% 1 2 PCH_SPI_D2_R1 11 10 EC interface
PCH_SPI_D3_R1 1 2 PCH_SPI_D3_1_R VPRO@ RC29 4.99_0201_1% PCH_SPI_D2 12 11
NVPRO@ RC576 33_0201_1% 1 2 PCH_SPI_D3_R1 13 12 HIGH ESPI
VPRO@ RC30 4.99_0201_1% PCH_SPI_D3 14 13 LOW (DEFAULT) LPC
PDG SPI0 2 resistor 50ohm, SPI0 3 resistor 33ohm 15 14
CLOSEED TO ROM +3.3V_SPI 15
Pop option at P.102 Please place close for future replace to RP +3.3V_ALW _PCH
16
17 16
<63> PROM_BIOS_R 18 17
19 18 +3.3V_ALW_PCH
For vPro +3.3V_SPI 1 2 20 19
20
256Mb WSON8 Flash ROM CC9
@ RC31 0_0201_5% 21
22 GND1
For Non-vPro 1 2 1 2 GND2 GPP_B23 1 2
64Mb WSON8 Flash ROM 0.1U_0201_10V6K DC4 ACES_50506-02041-P01
RC317 150K_0402_5%
PCH_SPI_CLK_1_R PCH_SPI_CLK_0_R RB521CM-30T2R_SOD923-2
PCH_SPI_CS#0_R1 @ RC32 1
VPRO@ UC5
PCH_SPI_CS#0_R2 for DCI-OOB
2 0_0201_5% 1 8
PCH_SPI_D1_0_R 2 CS# VCC 7 PCH_SPI_D3_0_R EXI BOOT STALL BYPASS
33_0402_5%

33_0402_5%

3 SO(IO1) IO3
1

PCH_SPI_D2_R1 1 2 PCH_SPI_D2_0_R 6 PCH_SPI_CLK_0_R

@EMI@

@EMI@

HIGH ENABLED
RC33 49.9_0201_1% 4 IO2 SCLK 5 PCH_SPI_D0_0_R
LOW(DEFAULT) DIABLED
RC289

RC299

VPRO@ VSS SI(IO0) 9

ThemalPad WEAK INTERNAL PD
GD25B256DYIG_W SON8_8X6
2

2
33P_0402_50V8J

33P_0402_50V8J

A A
@EMI@

@EMI@
1

1
CC1452

CC1453

+3.3V_SPI
NVPRO@
2

CC10
For Non-vPro 1 2
128Mb SOP8 Flash ROM 0.1U_0201_10V6K
NVPRO@ NVPRO@ UC6
PCH_SPI_CS#1_R1 RC302 1 2 0_0201_5% PCH_SPI_CS#1_R2
PCH_SPI_D1_1_R
1
2 CS# VCC
8
7 PCH_SPI_D3_1_R
DELL CONFIDENTIAL/PROPRIETARY
PCH_SPI_D2_R1 PCH_SPI_D2_1_R 3 DO(IO1) IO PCH_SPI_CLK_1_R

https://Dr-Bios.com
1 2 6
RC35 33_0201_1% 4 IO2 CLK 5 PCH_SPI_D0_1_R Compal Electronics, Inc.
NVPRO@ GND DI(IO0) Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
GD25B127DSIGR_SO8 TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
CPU(3/14)SPI,ESPI,SMB,LPC
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 8 of 109
5 4 3 2 1
 5 4 3 2 1

CPU@
UC1F
+3.3V_ALW_PCH
PRIM_CORE_OPT_DIS CC27
GPP_A7 CC32 GPP_B15/GSPI0_CS0# CN22 IR_CAM_DET#
ONE_DIMM# GPP_A7/PIRQA#/GSPI0_CS1# GPP_D9/ISH_SPI_CS#/GSPI2_CS0# DGPU_HOLD_RST# 1 IR_CAM_DET# <38>
CE28 CR22
CE27 GPP_B16/GSPI0_CLK GPP_D10/ISH_SPI_CLK/GSPI2_CLK CM22 TBT_DET# PAD~D @T420
NRB_BIT CE29 GPP_B17/GSPI0_MISO ISH GPP_D11/ISH_SPI_MISO/GSPI2_MISO CP22 GPP_D12
GPP_B18/GSPI0_MOSI GPP_D12/ISH_SPI_MOSI/GSPI2_MOSI

2
@
CA31 CK22 ISH_I2C0_ACC_SDA 1 RC400
GPP_B19/GSPI1_CS0# GPP_D5/ISH_I2C0_SDA ISH_I2C0_ACC_SCL 1 PAD~D @T415
T12 @ PAD~D 1 PME# CA32 CH20 10K_0402_5%
TPM_PIRQ# GPP_A11/PME#/GSPI1_CS1#/SD_VDD2_PWR_EN# GPP_D6/ISH_I2C0_SCL PAD~D @T416
CC29
<66> TPM_PIRQ# PCH_3.3V_TS_EN CC30 GPP_B20/GSPI1_CLK CH22 ISH_I2C1_ALS_SDA
<38> PCH_3.3V_TS_EN ISH_I2C1_ALS_SDA <38>

1
GPP_B22 CA30 GPP_B21/GSPI1_MISO GPP_D7/ISH_I2C1_SDA CJ22 ISH_I2C1_ALS_SCL
RC710,RC711 change to 33ohm from 75ohm, GPP_B22/GSPI1_MOSI GPP_D8/ISH_I2C1_SCL ISH_I2C1_ALS_SCL <38>
follow Intel MOW WW32 CNV_BRI_PRX_DTX CK20 TBT_DET#
D <52> CNV_BRI_PRX_DTX 2 33_0402_5%CNV_RGI_PTX_DRX GPP_F5/CNV_BRI_RSP ISH_I2C2_SDA D
<52> CNV_RGI_PTX_DRX_R RC710 1 CG19 CJ27
2 33_0402_5%CNV_BRI_PTX_DRX GPP_F6/CNV_RGI_DT GPP_H10/I2C5_SDA/ISH_I2C2_SDA ISH_I2C2_SCL ISH_I2C2_SDA <52>
<52> CNV_BRI_PTX_DRX_R RC711 1 CJ20 CJ29
CNV_RGI_PRX_DTX CH19 GPP_F4/CNV_BRI_DT GPP_H11/I2C5_SCL/ISH_I2C2_SCL ISH_I2C2_SCL <52>
<52> CNV_RGI_PRX_DTX GPP_F7/CNV_RGI_RSP CM24 SML0B_SMBDATA
RC710,RC711 placed closer to PCH. GPP_D13/ISH_UART0_RXD
Reserve

1
CN23 SML0B_SMBCLK
3MM_CAM_DET# CR12 GPP_D14/ISH_UART0_TXD CM23 WWAN_FULL_PWR_EN
<38> 3MM_CAM_DET# P_SENSOR_PWR_SAVE# GPP_C20/UART2_RXD GPP_D15/ISH_UART0_RTS#/GSPI2_CS1# WWAN_FULL_PWR_EN <52> 10K_0402_5%
CP12 CR24
<38> P_SENSOR_PWR_SAVE# SMART_SPK_DET1# CN12 GPP_C21/UART2_TXD GPP_D16/ISH_UART0_CTS#/SML0BALERT# RC401
<56> SMART_SPK_DET1# TS_INT# CM12 GPP_C22/UART2_RTS# CG12 SIO_EXT_WAKE#
<38> TS_INT# SIO_EXT_WAKE# <58>

2
GPP_C23/UART2_CTS# GPP_C12/UART1_RXD/ISH_UART1_RXD CH12 TBT_DET#
CM11 I2C , UART GPP_C13/UART1_TXD/ISH_UART1_TXD CF12 LCD_CBL_DET#
TS <38> TS_I2C_SDA CN11 GPP_C16/I2C0_SDA GPP_C14/UART1_RTS#/ISH_UART1_RTS# CG14 PCH_HDD_EN 1 LCD_CBL_DET# <38>
<38> TS_I2C_SCL GPP_C17/I2C0_SCL GPP_C15/UART1_CTS#/ISH_UART1_CTS# PAD~D @T421
HIGH NON AR
CK12 BW35 ISH_ACC1 1
TP <63> I2C1_SDA_TP GPP_C18/I2C1_SDA GPP_A18/ISH_GP0 ISH_ACC2 PAD~D @T395
CJ12 BW34 1
<63> I2C1_SCK_TP GPP_C19/I2C1_SCL GPP_A19/ISH_GP1 CA37 ISH_TABLE_MODE# 1 PAD~D @T396
LOW AR
1 I2C2_SDA_ALS CF27 GPP_A20/ISH_GP2 CA36 ISH_ALS_INT# PAD~D @T397
T388 @ PAD~D I2C2_SCL_ALS GPP_H4/I2C2_SDA GPP_A21/ISH_GP3 ISH_NB_MODE ISH_ALS_INT# <38>
1 CF29 CA35 1
T389 @ PAD~D GPP_H5/I2C2_SCL GPP_A22/ISH_GP4 ISH_LID_CL#_NB PAD~D @T375
CA34 1
I2C3_ANT_SDA GPP_A23/ISH_GP5 ISH_LID_CL#_TAB PAD~D @T376
CH27 BW37 1
I2C3_ANT_SCL CH28 GPP_H6/I2C3_SDA GPP_A12/ISH_GP6/BM_BUSY#/SX_EXIT_HOLDOFF# PAD~D @T377
GPP_H7/I2C3_SCL
CJ30 NB_MODE for NB13/Bandon
GPP_H8/I2C4_SDA
CJ31
GPP_H9/I2C4_SCL LID_CL#_NB for NB13/Bandon
WHL-U42_BGA1528 LID_CL#_TAB for NB13/Bandon RF Request
PU OPTION TO AVOID RSP SIGNALS
566439_CNL_PCH_LP__EDS_Rev1p2 ISH_ALS_INT# for Merion
+1.8V_PRIM FROM FLOATING IN CASE INTERNAL PUS NOT ENABLED IN A0 P.119 Primary Well Group H (Per-pad 1.8 V or 3.3 V) 6 of 20 SML0B_SMBCLK 1 2
Please setting 3.3V @RF@ CC1476 33P_0402_50V8J

20K_0402_5% 2 1 @ RC724 CNV_BRI_PRX_DTX add I2C3 TP for for sensor IC(Reserved)

20K_0402_5% 2 1 @ RC733 CNV_RGI_PRX_DTX add I2C3_ANT TP for ACTIVE STEERING ANT for MERION Place close CPU side
C C

+3.3V_RUN
Active Steering Antenna circuit +3.3V_ALW_PCH

PRIM_CORE_OPT_DIS 1 2
1031 change,RC435 reserve for FUSE location CONN@ @ RC854 10K_0402_5%
JASA1 SIO_EXT_WAKE# 1 2
RC435 1 2 0_0603_5% +3.3V_RUN_R 4 6 RC748 10K_0402_5%
+3.3V_RUN I2C3_ANT_SCL @ RC549 1 I2C3_ANT_SCL_R 4 G2
2 0_0201_5% 3 5
I2C3_ANT_SDA @ RC548 1 2 0_0201_5% I2C3_ANT_SDA_R 2 3 G1
100K_0402_5% 2 1 @ RC747 PCH_3.3V_TS_EN 1 2 SML0B_SMBCLK 1 2
1 @ RC829 1K_0402_5%
10K_0402_5% 2 1 @ RC841 GPP_A7 CVILU_CI1804M1HRG-NH SML0B_SMBDATA 1 2
RF Request @ RC830 1K_0402_5%
GPP_D12 1 2
2.2K_0201_5% 2 1 RC512 I2C3_ANT_SDA RC847 100K_0402_5%
+3.3V_RUN_R
2.2K_0201_5% 2 1 RC513 I2C3_ANT_SCL Link CI1804M1HRG-NH done 0212
+3.3V_RUN
I2C3_ANT for ACTIVE STEERING ANT for MERION

100P_0201_50V8J
@RF@ CC1466
1
LCD_CBL_DET# 1 2
RC749 100K_0402_5%
2 IR_CAM_DET# 2 1
Follow RVP,PDG pull up change to 20K RC345 100K_0402_5%

+1.8V_PRIM

place as close as JASA1

2

+3.3V_RUN
20K_0402_5%
RC842

ISH_I2C2_SDA 1 2
1

B RC363 1K_0402_5% B
CNV_RGI_PTX_DRX_R ISH_I2C2_SCL 1 2
Reserved for wake on voice RC362 1K_0402_5%
1
4.7K_0402_5%

@
+3.3V_ALW_PCH
RC832
2

5
@ UC9
PRIM_CORE_OPT_DIS 1 MC74VHC1G32DFT2G_SC70-5~D

P
+3.3V_ALW_PCH INB 4
SIO_SLP_S0# O VR_LPM_R# <87>
2
<11,17,66,79,87> SIO_SLP_S0# INA
G
M.2 CNVI MODES
1 2 NRB_BIT 0 = Integrated CNVi enable.
3

RC831 4.7K_0402_5% 1 = Integrated CNVi disable. (Disable CNVi for bring up)
WEAK INTERNAL PU

NO REBOOT STRAP 1 2
1218 add RC867 reserve for BITS392123
HIGH No REBOOT @ RC867 0_0201_5%
1 2
LOW(DEFAULT) REBOOT ENABLE @ RC660 0_0201_5%
Weak IPD

+3.3V_ALW_PCH
ONE_DIMM#
A A
1

1
10K_0402_5%

2.2K_0402_5%
RC53

@RC46
2

GPP_B22 DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

https://Dr-Bios.com
BOOT BIOS Dest i nat i on(Bi t 6
) Title
DIMM Detect PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
HIGH LPC
HIGH 1 DIMM
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
CPU(4/14)GSPI,I2C,UART,ISH
LOW(DEFAULT) SPI Size Document Number R ev
LOW 2 DIMM NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 9 of 109
5 4 3 2 1
 5 4 3 2 1

For Merion AR (follow WHL 180416a port map)

CPU@
UC1H
CB5
BW9 PCIE1_RXN/USB31_1_RXN CB6
D <42> PCIE_PRX_DTX_N5 BW8 PCIE5_RXN/USB31_5_RXN PCIE1_RXP/USB31_1_RXP CA4 D
<42> PCIE_PRX_DTX_P5 BW4 PCIE5_RXP/USB31_5_RXP PCIE / USB3.1 / SATA PCIE1_TXN/USB31_1_TXN CA3
<42> PCIE_PTX_DRX_N5 BW3 PCIE5_TXN/USB31_5_TXN PCIE1_TXP/USB31_1_TXP
<42> PCIE_PTX_DRX_P5 PCIE5_TXP/USB31_5_TXP BY8
BU6 PCIE2_RXN/USB31_2_RXN/SSIC_1_RXN BY9 USB3_PRX_DTX_N2 <71>
<42> PCIE_PRX_DTX_N6 BU5 PCIE6_RXN/USB31_6_RXN PCIE2_RXP/USB31_2_RXP/SSIC_1_RXP CA2 USB3_PRX_DTX_P2 <71>
<42> PCIE_PRX_DTX_P6 BU4 PCIE6_RXP/USB31_6_RXP PCIE2_TXN/USB31_2_TXN/SSIC_1_TXN CA1 USB3_PTX_DRX_N2 <71> -----> Ext USB3 Port 1 charge
<42> PCIE_PTX_DRX_N6 BU3 PCIE6_TXN/USB31_6_TXN PCIE2_TXP/USB31_2_TXP/SSIC_1_TXP USB3_PTX_DRX_P2 <71>
<42> PCIE_PTX_DRX_P6 PCIE6_TXP/USB31_6_TXP BY7
AR(PCIE5~8) ---> BT7 PCIE3_RXN/USB31_3_RXN BY6 USB3_PRX_DTX_N3 <72>
<42> PCIE_PRX_DTX_N7 BT6 PCIE7_RXN PCIE3_RXP/USB31_3_RXP BY4 USB3_PRX_DTX_P3 <72>
<42> PCIE_PRX_DTX_P7 BU2 PCIE7_RXP PCIE3_TXN/USB31_3_TXN BY3 USB3_PTX_DRX_N3 <72> -----> Ext USB3 Port 2
<42> PCIE_PTX_DRX_N7 BU1 PCIE7_TXN PCIE3_TXP/USB31_3_TXP USB3_PTX_DRX_P3 <72>
<42> PCIE_PTX_DRX_P7 PCIE7_TXP BW6
BU9 PCIE4_RXN/USB31_4_RXN BW5 USB3_PRX_DTX_N4 <54>
<42> PCIE_PRX_DTX_N8 BU8 PCIE8_RXN PCIE4_RXP/USB31_4_RXP BW2 USB3_PRX_DTX_P4 <54>
<42> PCIE_PRX_DTX_P8 BT4 PCIE8_RXP PCIE4_TXN/USB31_4_TXN BW1 USB3_PTX_DRX_N4 <54> -----> M.2 3042(LTE)
<42> PCIE_PTX_DRX_N8 BT3 PCIE8_TXN PCIE4_TXP/USB31_4_TXP USB3_PTX_DRX_P4 <54>
<42> PCIE_PTX_DRX_P8 PCIE8_TXP CE3
BP5 USB2_1N CE4 USB20_N1 <44>
<70>
<70>
PCIE_PRX_DTX_N9
PCIE_PRX_DTX_P9
BP6 PCIE9_RXN USB2_1P USB20_P1 <44> -----> Type C (PD)
BR2 PCIE9_RXP USB2.0 CE1
Card Reader RTS5242-----> <70> PCIE_PTX_DRX_N9 BR1 PCIE9_TXN USB2_2N CE2 USB20_N2 <71>
<70> PCIE_PTX_DRX_P9 PCIE9_TXP USB2_2P USB20_P2 <71> -----> Ext USB2 Port 1
BN6 CG3
<52> PCIE_PRX_DTX_N10 BN5 PCIE10_RXN USB2_3N CG4 USB20_N3 <72>
<52> PCIE_PRX_DTX_P10 BR4 PCIE10_RXP USB2_3P USB20_P3 <72> -----> Ext USB2 Port 2
M.2 2230(WLAN) ---> <52> PCIE_PTX_DRX_N10 BR3 PCIE10_TXN CD3
<52> PCIE_PTX_DRX_P10 PCIE10_TXP USB2_4N CD4
BN10 USB2_4P
<54> PCIE_PRX_DTX_N11 BN8 PCIE11_RXN/SATA0_RXN CG5
<54> PCIE_PRX_DTX_P11 BN4 PCIE11_RXP/SATA0_RXP USB2_5N CG6
C <54> PCIE_PTX_DRX_N11 BN3 PCIE11_TXN/SATA0_TXN USB2_5P C
<54> PCIE_PTX_DRX_P11 PCIE11_TXP/SATA0_TXP CC1
BL6 USB2_6N CC2 USB20_N6 <38>
M.2 3042(LTE/SATA Cache)---> <52> PCIE_PRX_DTX_N12 BL5 PCIE12_RXN/SATA1A_RXN USB2_6P USB20_P6 <38> -----> UF CAM
<52> PCIE_PRX_DTX_P12 BN2 PCIE12_RXP/SATA1A_RXP CG8
<52> PCIE_PTX_DRX_N12 BN1 PCIE12_TXN/SATA1A_TXN USB2_7N CG9 USB20_N7 <52>
<52> PCIE_PTX_DRX_P12 PCIE12_TXP/SATA1A_TXP USB2_7P USB20_P7 <52> -----> M2 3042(WWAN)
BK6 CB8
<68> PCIE_PRX_DTX_N13 BK5 PCIE13_RXN USB2_8N CB9 USB20_N8 <66>
<68> PCIE_PRX_DTX_P13 BM4 PCIE13_RXP USB2_8P USB20_P8 <66> -----> USH
<68> PCIE_PTX_DRX_N13 BM3 PCIE13_TXN CH5
<68> PCIE_PTX_DRX_P13 PCIE13_TXP USB2_9N USB20_N9 <66>
BJ6 USB2_9P
CH6
USB20_P9 <66> -----> Option to FPR in PB
<68> PCIE_PRX_DTX_N14 BJ5 PCIE14_RXN CC3
<68> PCIE_PRX_DTX_P14 BL2 PCIE14_RXP USB2_10N CC4 USB20_N10 <52>
<68> PCIE_PTX_DRX_N14 BL1 PCIE14_TXN USB2_10P USB20_P10 <52> -----> M.2 2230(BT)
<68> PCIE_PTX_DRX_P14 PCIE14_TXP CC5 USBCOMP RC47 1 2 113_0402_1%
M2 2280 SSD (4 Lane) ---> BG5 USB2_COMP CE8 USB2_ID @ RC3371 2 0_0201_5%
<68> PCIE_PRX_DTX_N15 BG6 PCIE15_RXN/SATA1B_RXN USB2_ID CC6 VBUSSENSE RC49 1 2 1K_0402_5%
<68> PCIE_PRX_DTX_P15 BL4 PCIE15_RXP/SATA1B_RXP USB2_VBUSSENSE
<68> PCIE_PTX_DRX_N15 BL3 PCIE15_TXN/SATA1B_TXN CK6
<68> PCIE_PTX_DRX_P15 PCIE15_TXP/SATA1B_TXP GPP_E9/USB2_OC0#/GP_BSSB_CLK CK5 USB_OC0# <71>
BE5 GPP_E10/USB2_OC1#/GP_BSSB_DI CK8 USB_OC2# USB_OC1# <72>
Reserve
<68> PCIE_PRX_DTX_N16 BE6 PCIE16_RXN/SATA2_RXN GPP_E11/USB2_OC2# CK9 USB_OC3# Reserve
<68> PCIE_PRX_DTX_P16 BJ4 PCIE16_RXP/SATA2_RXP GPP_E12/USB2_OC3#
<68> PCIE_PTX_DRX_N16 BJ3 PCIE16_TXN/SATA2_TXN CP8 HDD_DEVSLP 1
<68> PCIE_PTX_DRX_P16 PCIE16_TXP/SATA2_TXP GPP_E4/DEVSLP0 CR8 PAD~D @ T417
PCIE_RCOMPN CE6 GPP_E5/DEVSLP1 CM8 M3042_DEVSLP <52>
RC50 1 2 100_0402_1% PCIE_RCOMPP CE5 PCIE_RCOMP_N GPP_E6/DEVSLP2 M2280_DEVSLP <68>
PCIE_RCOMP_P CN8 HDD_DET#
CR28 GPP_E0/SATAXPCIE0/SATAGP0 CM10 M3042_PCIE#_SATA
Jony _12/21: Refer RVP keep it setting GPP_H12/M2_SKT2_CFG_0 GPP_E1/SATAXPCIE1/SATAGP1 M3042_PCIE#_SATA <58>
570990_CFL_U_DDR4_RVP_CRB_Sch_Rev0p8.pdf CP28 CP10 M2280_PCIE_SATA#
B CN28 GPP_H13/M2_SKT2_CFG_1 GPP_E2/SATAXPCIE2/SATAGP2 M2280_PCIE_SATA# <68> B
CM28 GPP_H14/M2_SKT2_CFG_2 CN7
GPP_H15/M2_SKT2_CFG_3 GPP_E8/SATALED#/SPI1_CS1#
AR3
RSVD_69
WHL-U42_BGA1528

8 of 20

+3.3V_RUN

M2280_PCIE_SATA# 2 1
RC764 10K_0402_5%
HDD_DET# 2 1
RC765 10K_0402_5%
M3042_PCIE#_SATA 2 1
RC766 10K_0402_5%
USB_OC3# @ RC757 1 2 20K_0402_5%
USB_OC0# @ RC758 1 2 20K_0402_5% HDD_DET# @ RC520 1 2 1K_0402_5% +3.3V_ALW_PCH

USB_OC1# @ RC759 1 2 20K_0402_5% M3042_PCIE#_SATA @ RC521 1 2 1K_0402_5%

USB_OC2# @ RC760 1 2 20K_0402_5% M2280_PCIE_SATA# @ RC730 1 2 1K_0402_5% USB_OC3# RC836 2 1 10K_0402_5%
USB_OC0# RC837 2 1 10K_0402_5%
USB_OC1# RC839 2 1 10K_0402_5%
USB_OC2# RC838 2 1 10K_0402_5%

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, CPU(5/14)PCIE,USB,SATA
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 10 of 109
5 4 3 2 1
 5 4 3 2 1

Jony_1221: Refer RVP is 200 K ohm

570990_CFL_U_DDR4_RVP_CRB_Sch_Rev0p8.pdf CC21
1 2

15P_0402_50V8J

200K_0402_1%
2

3
4
YC1

RC59
CPU@ 24MHZ_12PF_8Y24000034
UC1J XTAL24_IN_CPU 1 2 XTAL24_IN

1
2
EMI@ RC728 0_0402_5%

1
CLOCK SINGNALS CLK_ITPXDP_N
AW2 AU1 @ RC530 1 2 0_0201_5%
<52> CLK_PCIE_N0 CLKOUT_PCIE_N_0 CLKOUT_ITPXDP_N CLK_ITPXDP_P CLK_ITPXDP_N_R <79>
AY3 AU2 @ RC298 1 2 0_0201_5%
<52> CLK_PCIE_P0 CLKREQ_PCIE#0_R CLKOUT_PCIE_P_0 CLKOUT_ITPXDP_P CLK_ITPXDP_P_R <79>
@RF@ RC297 1 2 0_0201_5% CF32 CC22
M.2 3042 WWAN---> <52> CLKREQ_PCIE#0
RC189 2 1 10K_0402_5% GPP_B5/SRCCLKREQ0# BT32 SUSCLK XTAL24_OUT_CPU 1 2 XTAL24_OUT 1 2
+3.3V_RUN GPD8/SUSCLK SUSCLK <52,68>
BC1 EMI@ RC729 0_0402_5%
D <52> CLK_PCIE_N1 CLKOUT_PCIE_N_1 XTAL24_IN_CPU D
BC2 CK3 @CC93 2 1 0.1U 16V K X5R 0201 15P_0402_50V8J
<52> CLK_PCIE_P1 CLKREQ_PCIE#1_R CLKOUT_PCIE_P_1 XTAL_IN XTAL24_OUT_CPU
@RF@ RC526 1 2 0_0201_5% CE32 CK2
M.2 2230 WLAN---> <52> CLKREQ_PCIE#1
RC522 2 1 10K_0402_5% GPP_B6/SRCCLKREQ1# XTAL_OUT
+3.3V_RUN XCLK_BIASREF
BD3 CJ1 RC402 1 2 60.4_0402_1%
<68> CLK_PCIE_N2 CLKOUT_PCIE_N_2 XCLK_BIASREF REFCLK_CNV
BC3 CM3 1 2
<68> CLK_PCIE_P2 CLKREQ_PCIE#2_R CLKOUT_PCIE_P_2 CLKIN_XTAL REFCLK_CNV_L <52>
@RF@ RC727 1 2 0_0201_5% CF30 ESD@ LC5 BLM15BD121SN1D_2P~D
M.2 2280 SSD---> <68> CLKREQ_PCIE#2
RC525 2 1 10K_0402_5% GPP_B7/SRCCLKREQ2# BN31 PCH_RTCX1 LC5 place near CPU side CC23
+3.3V_RUN RTCX1 PCH_RTCX2 PCH_RTCX1
BH3 BN32 ESD Request 1 2
BH4 CLKOUT_PCIE_N_3 RTCX2 0419 ESD YuHeng: follow Intel recommendation PCH_RTCX2
RC523 2 1 10K_0402_5% CLKREQ_PCIE#3_R CE31 CLKOUT_PCIE_P_3 BR37 SRTCRST# RC56 1 2 20K_0402_5% 15P_0402_50V8J
+3.3V_RUN GPP_B8/SRCCLKREQ3# SRTCRST# +RTC_CELL_PCH
BR34

1
BA1 RTCRST# CC24 1 2 1U_0201_6.3V6M
<70> CLK_PCIE_N4 CLKOUT_PCIE_N_4
BA2 RC66 YC2
<70> CLK_PCIE_P4 CLKREQ_PCIE#4_R CLKOUT_PCIE_P_4 PCH_RTCRST# <58,79>
@RF@ RC528 1 2 0_0201_5% CE30 32.768KHZ_12.5PF_9H03200042
Card Reader ---> <70> CLKREQ_PCIE#4
RC51 2 1 10K_0402_5% GPP_B9/SRCCLKREQ4# PCH_RTCRST# RC57 1 2 20K_0402_5%
10M_0402_5%
ESR MAX=50k ohm
+3.3V_RUN

2
BE1

1
<42> CLK_PCIE_N5 BE2 CLKOUT_PCIE_N_5 CC25 1 2 1U_0201_6.3V6M CC26
<42> CLK_PCIE_P5 @RF@ RC529 1 2 0_0201_5% CLKREQ_PCIE#5_R CF31 CLKOUT_PCIE_P_5 1 2 PCH_RTCX2_R 1 2
AR---> <42> CLKREQ_PCIE#5
RC190 2 1 10K_0402_5% GPP_B10/SRCCLKREQ5# @ RC532 0_0402_5%
+3.3V_RUN
W HL-U42_BGA1528 15P_0402_50V8J
10 of 20 1 2
1 2

@ CMOS1 SHORT PADS~D

REFCLK_CNV 2 1
CMOS1 DVT1.0 footprint change to SHORTPADS-NPM RC751 10K_0402_5%
CMOS1 must take care short & touch risk on layout placement
SUSCLK 1 2
@ RC48 1K_0402_5%

+3.3V_ALW_DSW

2 1 LAN_W AKE# PCH_PLTRST# 1 2

PLTRST_TPM# <66>
RC323 10K_0402_5% @ RC60 0_0201_5%

2 1 PCH_PCIE_W AKE# PCH_PLTRST#_AND 1 2

RC67 1K_0402_5% @ RC738 0_0201_5%
C +3.3V_ALW_PCH C

+1.0V_VCCST
5

2 1 VCCST_PW RGD SIO_SLP_SUS# 1 2

PCH_PLTRST# <18> VCCDSW_EN_GPIO PCH_PRIM_EN <78,87>
RC71 1K_0402_5% 1 DS3@ RC441 0_0201_5%
P

B 4 PCH_PLTRST#_AND
O PCH_PLTRST#_AND <38,42,52,68,70>
2 NDS3@ DC1 @NDS3@
A
G

2 1 PCH_PW ROK UC7 1 2 2 1 VCCDSW _EN_Q RC442 1 2

RC439RC440RE536RC215RC441RC442 <58> VCCDSW_EN
@ RC536 10K_0402_5% MC74VHC1G08DFT2G_SC70-5 @ RC65 @ RC445 0_0201_5% 0_0201_5%
3

100K_0402_5% RB751S-40_SOD523-2
Support DS3 V X V X V X
NDS3@ DC2
2

1 2
<63,85> ALW_PWRGD_3V_5V
No Support DS3 X V X V X V
RB751S-40_SOD523-2

'V' mean POP, 'X' mean DE-POP

+3.3V_ALW_PCH

3.3V_CAM_EN# 1 2
PCH GLITCH ISSUE MITIGATION(PDG p.130) For deglitch,
refer to 575412_WHL_U_PDG rev0p8 RC834 100K_0402_5%

2 1 SIO_SLP_SUS#
100K_0402_5% RC229 +3.3V_ALW_DSW
2 1 8/21 can change to 10K for merge to RP
0.33U_0402_10V6K @ CC1465
PCH_BATLOW # 1 2
2 1 SIO_SLP_S4#
S4 power side PD need @,need check AC_PRESENT
RC72 10K_0402_5%
100K_0402_5% RC232 1 2
2 1 CPU@ RC555 10K_0402_5%
0.33U_0402_10V6K @ CC1467 UC1K
+RTC_CELL_PCH
2 1 SIO_SLP_S3# SYSTEM POWER MANAGEMENT BJ37 SIO_SLP_S0#
PCH_PLTRST# GPP_B12/SLP_S0# SIO_SLP_S0# <9,17,66,79,87>
100K_0402_5% RC231 BJ35 BU36
SYS_RESET# GPP_B13/PLTRST# GPD4/SLP_S3# SIO_SLP_S3# <17,42,59,79>
2 1 CN10 BU27 INTRUDER# 1 2
<79> SYS_RESET# PCH_RSMRST#_AND SYS_RESET# GPD5/SLP_S4# SIO_SLP_S5# SIO_SLP_S4# <17,79,86,87>
0.33U_0402_10V6K @ CC1468 BR36 BT29 RC69 1M_0402_5%
<63,79> PCH_RSMRST#_AND RSMRST# GPD10/SLP_S5# SIO_SLP_S5# <79>
2 1 SIO_SLP_A# 1H_CPUPW RGD_R @ RC77 1 2 1K_0402_5% H_CPUPW RGD AR2 BU29
T355 @ PAD~D VCCST_PW RGD_CPU BJ2 PROCPWRGD SLP_SUS# SIO_SLP_LAN# SIO_SLP_SUS# <58> +3.3V_ALW_PCH
100K_0402_5% RC233 RC78 1 2 62_0402_5% BT31
<59,79> VCCST_PWRGD VCCST_PWRGOOD SLP_LAN#
B 2 1 Follow PDG P.251 BT30 B
0.33U_0402_10V6K @ CC1469 CR10 GPD9/SPL_WLAN# BU37 SIO_SLP_A# SIO_SLP_WLAN# <78>
<58,79> SYS_PW ROK SYS_PWROK GPD6/SLP_A# SIO_SLP_A# <79>
BP31 VRALERT# 1 2
SIO_SLP_W LAN# <88> PCH_PWROK PCH_PWROK
2 1 BP30 BU28 RC73 10K_0402_5%
<58> PCH_DPWROK DSW_PWROK GPD3/PWRBTN# SIO_PWRBTN# <58,79>
100K_0402_5% RC234 BU35 1 2
GPP_A13 GPD1/ACPRESENT PCH_BATLOW # AC_PRESENT <58>
2 1 1 BV34 BV36 @ RC344 10K_0402_5%
T380 @ PAD~D GPP_A15 GPP_A13/SUSWARN#/SUSPWRDACK GPD0/BATLOW#
0.33U_0402_10V6K @ CC1470 ME_SUS_PWR_ACK is for LPC use only 1 BY32
T381 @ PAD~D GPP_A15/SUSACK# +3.3V_ALW
SUSACK# is for LPC use only
2 1 SIO_SLP_LAN# BU30 BR35 INTRUDER#
<42,58,59> PCH_PCIE_WAKE# LAN_W AKE# WAKE# INTRUDER# SIO_SLP_LAN#
100K_0402_5% RC761 BU32 1 2
<58> LAN_WAKE# PM_LANPHY_ENABLE BU34 GPD2/LAN_WAKE# 3.3V_CAM_EN#
2 1 1 CC37 @ RC68 10K_0402_5%
T422 @ PAD~D GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# 3.3V_CAM_EN# <38>
0.33U_0402_10V6K @ CC1471 CC36 VRALERT#
GPP_B2/VRALERT#
2 1 SIO_SLP_S5# BT27 INPUT3VSEL
100K_0402_5% @ RC230 INPUT3VSEL

2 1 PCH_PLTRST#
100K_0402_5% @ RC237 W HL-U42_BGA1528
+3.3V_ALW_PCH
11 of 20
1211 change
Follow NB14 UU AR, Intel CNVi recommendation RC237 pop,
But measure cold reset and Global reset sequence timing fail, So depop RC237

2
@ RC451
0 = 3.3V supply is 3.3V +/- 5% (3.3V for bring up)
20K_0402_5%
1 = 3.3V supply is 3.0V +/- 5%
+3.3V_ALW_PCH

1
INPUT3VSEL
2 1 SIO_SLP_S0#

2
100K_0402_5% RC763 +3.3V_ALW_PCH
RC452
4.7K_0402_5%
2

@ RC248

1
2.2K_0402_5%
1

1 2 SYS_RESET# ESD Request

<79> XDP_DBRESET# 0419 ESD YuHeng: follow Intel recommendation
@ RC243 0_0201_5%
1 SYS_RESET# REFCLK_CNV
A
RC215 CC78 A
0.1U_0402_25V6
@ESD@

POP NO Support Deep sleep 0.1U_0402_25V6

2

4.7P_0402_50V8C
ESD@ CC1477
DE-POP Support Deep sleep 1
1

Follow ICL_2/23 CKT

PCH_DPW ROK 1 2 PCH_RSMRST#_AND
2

H_CPUPW RGD VCCST_PW RGD PCH_PLTRST#_AND 2

CC302

@NDS3@
RC215
1

1
100P_0402_50V8J
ESD@

100P_0402_50V8J
ESD@

0.01UF_0402_25V7K

100K_0402_1%

10K_0402_5%

.047U_0402_16V7K
ESD@ CC196

1 0_0201_5%
@
DELL CONFIDENTIAL/PROPRIETARY
1

1
CC266

RC220

RC75

ESD Request:place near CPU side ESD Request:place near CPU side
2

https://Dr-Bios.com
CC300

CC301

Compal Electronics, Inc.

2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
For ESD solution TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
CPU(6/14)CLK,PM,RTC
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
ESD Request:place near CPU side
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 11 of 109
5 4 3 2 1
 5 4 3 2 1

CPU@
UC1G
RC92 1 2 33_0402_5% HDA_SYNC BN34
D <56> HDA_SYNC_R 1 2 HDA_BIT_CLK BN37 HDA_SYNC/I2S0_SFRM CH36 D
EMI@ RC93 33_0402_5%
<56> HDA_BIT_CLK_R 1 2 HDA_SDOUT BN36 HDA_BCLK/I2S0_SCLK AUDIO SDIO / SDXC GPP_G0/SD_CMD CL35 MACO_EN 1 CAM_MIC_CBL_DET# <38>
RC561 33_0402_5%
<56> HDA_SDOUT_R 1 2 BN35 HDA_SDO/I2S0_TXD GPP_G1/SD_DATA0 CL36 TBT_CIO_PLUG_EVENT# PAD~D @T452
RC562 1K_0402_5%
<79> ME_FWP_PCH <56> HDA_SDIN0 BL36 HDA_SDI0/I2S0_RXD GPP_G2/SD_DATA1 CM35 CPU_GC6_FB_EN 1 TBT_CIO_PLUG_EVENT# <42>
1 2 33_0402_5% HDA_RST# BL35 HDA_SDI1/I2S1_RXD/SNDW1_DATA GPP_G3/SD_DATA2 CN35 CONTACTLESS_DET# PAD~D @T383
RC560
<56> HDA_RST#_R CK23 HDA_RST#/I2S1_SCLK/SNDW1_CLK GPP_G4/SD_DATA3 CH35 HOST_SD_WP# CONTACTLESS_DET# <66>
GPP_D23/I2S_MCLK GPP_G5/SD_CD# CK36 AUD_PWR_EN HOST_SD_WP# <70>
GPP_G6/SD_CLK SMART_SPK_DET0# AUD_PWR_EN <56>
1218 BL37 CK34
SMART_SPK_DET0# <56>
HDA_BIT_CLK_R BL34 I2S1_SFRM/SNDW2_CLK GPP_G7/SD_WP
Follow NB14 UU AR I2S1_TXD/SNDW2_DATA
Add 'CNVI_EN#' net connection to GPP_H3
1 CNV_RF_RESET# CJ32
<52> CNV_RF_RESET# CH32 GPP_H1/I2S2_SFRM/CNV_BT_I2S_BCLK/CNV_RF_RESET#
RF@CC27
47P_0402_50V8J CLKREQ_CNV# CH29 GPP_H0/I2S2_SCLK/CNV_BT_I2S_SCLK
2 <52> CLKREQ_CNV# CNVI_EN# CH30 GPP_H2/I2S2_TXD/CNV_BT_I2S_SDI/MODEM_CLKREQ BW36 ISH_P_SENSOR_INT#
<52> CNVI_EN# GPP_H3/I2S2_RXD/CNV_BT_I2S_SDO GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7 BY31 2.7MM_CAM_DET# ISH_P_SENSOR_INT# <38>
1 DMIC_CLK0_CPU CP24 GPP_A16/SD_1P8_SEL 2.7MM_CAM_DET# <38>
@ T404 PAD~D
@ T405 PAD~D 1 DMIC_DATA0_CPU CN24 GPP_D19/DMIC_CLK0/SNDW4_CLK
Close to RC93 GPP_D20/DMIC_DATA0/SNDW4_DATA CK33
KB_DET# CK25 SD_1P8_RCOMP CM34 SD_RCOMP RC116 1 2 200_0402_1%
<63> 1 KB_DET# DGPU_PWROK CJ25 GPP_D17/DMIC_CLK1/SNDW3_CLK SD_3P3_RCOMP
@ T419 PAD~D
GPP_D18/DMIC_DATA1/SNDW3_DATA
SPKR CF35
<56> SPKR GPP_B14/SPKR
WHL-U42_BGA1528

7 of 20

C C

+3.3V_ALW_PCH

2 1 CAM_MIC_CBL_DET#
RC725 10K_0402_5%

+3.3V_ALW_PCH RF Request. Place near CPU side (Intel MOW)

2 1 SPKR
@ RC183 2.2K_0402_5% HDA_RST# HDA_SDIN0 HDA_SDOUT
+3.3V_RUN

CONTACTLESS_DET# TOP SWAP STRAP

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C
2 1 1 1 1
RC278 10K_0402_5% HIGH ENABLE
B AUD_PWR_EN B

@RF@ CC331

@RF@ CC332

@RF@ CC333
2 1
RC279 10K_0402_5% LOW(DEFAULT) DISABLE
Internal 20k PD 2 2 2

2 1 HOST_SD_WP#
RC292 10K_0402_5%

+3.3V_ALW_PCH
+3.3V_ALW_PCH

2 1 KB_DET#
RC288 10K_0402_5% 2 1 HDA_SDOUT
@ RC187 4.7K_0402_5%
1206 change
Follow NB14 UU AR
'CNV_RF_RESET#' change to 75K PD from 71.5K
'CLKREQ_CNV#' change to 71.5K PD from 75K Flash Descriptor Security override
1 2 CLKREQ_CNV#
RC752 71.5K_0402_1%
HIGH DISABLE
1 2 CNV_RF_RESET# LOW(DEFAULT) ENABLE
RC640 75K_0402_5%

1 2 CNVI_EN#
RC868 75K_0402_5%

1218
A Follow NB14 UU AR A
Add 75K PD for 'CNVI_EN#'

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, CPU(7/14)MISC,JTAG,HDA,SDIO
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 12 of 109
5 4 3 2 1
 5 4 3 2 1

1 2 CFG0 1 2 CFG7
@ RC120 1K_0201_1% @ RC411 1K_0201_1%

EAR-STALL/NOT STALL RESET PEG DEFER TRAINING

SEQUENCE AFTER PCU PLL IS LOCKED
1: (DEFAULT) PEG TRAIN IMMEDIATELY
CFG0 1:(DEFAULT)NORMAL OPERATION; NO STALL CFG7 FOLLOWING XXRESETB DE ASSERTION
0:STALL 0: PEG WAIT FOR BIOS FOR TRAINING
D D

1 2 CFG1 1 2 CFG8
@ RC405 1K_0201_1% @ RC412 1K_0201_1%

<79> CFG[0..19]
CPU@
UC1Q
PCH/ PCH LESS MODE SELECTION ALLOW THE USE OF CFG ON LOCKED UNITS RESERVED SIGNALS
F37 1
1: DISABLED(DEFAULT); IN THIS CASE, CFG WILL BE
CFG0 T4 RSVD_TP5 F34 1 PAD~D @ T16
1: (DEFAULT) NORMAL OPERATION DISABLED IN LOCKED UNITS AND ENABLED IN UN-LOCKED UNITS AND PAD~D @ T17
CFG1 0: PCH-LESS MODE
CFG8 0: EENABLED; CFG WILL BE CFG1 R4 CFG_0 RSVD_TP4
AVAILABLE REGARDLESS OF THE LOCKING OF THE UNIT CFG2 T3 CFG_1 CP36 1
R3 CFG_2 IST_TRIG CN36 1 PAD~D @ T18
CFG3
CFG4 J4 CFG_3 RSVD_TP3 PAD~D @ T19
CFG5 M4 CFG_4 BJ36
1 2 CFG2 1 2 CFG9 CFG6 J3 CFG_5 RSVD15 BJ34
@ RC406 1K_0201_1% @ RC413 1K_0201_1% CFG7 M3 CFG_6 RSVD14
CFG8 R2 CFG_7 BK34 1
CFG9 N2 CFG_8 TP_1 BR18 1 PAD~D @ T20
CFG10 R1 CFG_9 TP_2 PAD~D @ T21
CFG11 N1 CFG_10
CFG12 J2 CFG_11
PCI EXPRESS STATIC LANE REVERSAL NO SVID PROTOCOL CAPABLE VR CONNECTED CFG13 L2 CFG_12 BT9
FOR ALL PEG PORTS CFG14 J1 CFG_13 RSVD21 BT8
CFG15 L1 CFG_14 RSVD20
CFG2 1: (DEFAULT)NORMAL OPERATION CFG9 1:VRS SUPPORTING SVID PROTOCOL ARE PRESENT CFG_15 BP8
0: LANE REVERSAL 0: NO VR SUPPORTING SVID RSVD18
CFG16 L3 BP9
CFG18 N3 CFG_16 RSVD19
CFG17 L4 CFG_18 CR4 1
C CFG19 N4 CFG_17 RSVD29 PAD~D @ T360 C
1 2 CFG3 1 2 CFG10 Refer RVP CFG_RCOMP Keep 49.9 ohm to GND CFG_19 CP3
@ RC407 1K_0201_1% @ RC414 1K_0201_1% 570990_CFL_U_DDR4_RVP_CRB_Sch_Rev0p8.pdf RSVD26 CR3
2 1 CFG_RCOMP AB5 RSVD27
RC624 49.9_0201_1% CFG_RCOMP
2 1 ITP_PMODE W4
+1.0V_PRIM_XDP ITP_PMODE
RC125 1.5K_0201_5% BP36 @ RC848 2 1 0_0201_5%
CG2 VSS_434
CG1 RSVD25
PCH/ PCH LESS MODE SELECTION SAFE MODE BOOT <79> ITP_PMODE RSVD24
AT3
1:(DEFAULT) NORMAL OPERATION CFG10 1: POWER FEATURES ACTIVATED DURING RESET RSVD12
CFG3 0: PCH-LESS MODE 0: POWER FEATURES (ESPECIALLY CLOCK GATINE ARE NOT ACTIVATED Refer RVP CFG_RCOMP Keep 1.5K to 1.0 VA
RSVD13
AU3
570990_CFL_U_DDR4_RVP_CRB_Sch_Rev0p8.pdf
H4
H3 RSVD34
RSVD33 AN1
BV24 RSVD8 AN2
1 2 CFG4 1 2 CFG11 RSVD22 RSVD9
BV25
RC723 1K_0201_1% @ RC415 1K_0201_1% RSVD23 AN4
RSVD11 AN3
RSVD10
need check AL2
0: AN EXTERNAL DISPLAY PORT DEVICE PORT IS CONNECTED TO THE EMBEDDED PORT RSVD72
1: NO PHYSICAL DISPLAY PORT ATTACHED TO EMBEDDED DISPLAY PORT G3 AL1
G4 RSVD66 RSVD73
DMI AC COUPLING - JUST A PLACE HOLDER. RSVD67
DISPLAY PORT PRESENCE STRAP NOT APPLICABLE FOR ULX-ULT
AL4
1:(DEFULT) RSVD74 AL3
CFG4 0: ENABLED CFG11 DMI WILL BE CONFIGURED AS HALF SWING DC COUPLED
1: DISABLED; BK36 RSVD75
0:DMI WILL BE CONFIGURED AS FULL SWING AC COUPLED RSVD17
BK35 BP34 1
RSVD16 TP_4 BP35 1 PAD~D @ T361
W3 TP_3 PAD~D @ T363
AM4 RSVD35 +1.0V_VCCSTG
1 2 CFG5 1 2 CFG12 RSVD7
B
@ RC416 1K_0201_1% C34 @ RC420 2 1 0_0201_5% B
@ RC409 1K_0201_1% AM3 RSVD68
RSVD6 A34 1
RSVD_TP1 PAD~D @ T364

100_0201_1%
B35 1
RSVD_TP2 PAD~D @ T365

@ RC436
CR35 1
1 2 CFG6
A35 RSVD28 PAD~D @ T423
@ RC410 1K_0201_1% PM SYNC LEGACY RSVD1
D34

2
RSVD30 AH26 @ RC5631 2 0_0201_5%
1: (DEFAULT) PMSYNC 2.0 G2 RSVD36 AJ27 @ RC5641 2 0_0201_5%
CFG12 0 : LEGACY G1 RSVD32 RSVD37
RSVD31 E1 SKTOCC# @ RC5651 2 0_0201_5%
SKTOCC#
1206 change
WHL-U42_BGA1528 Follow NB14 UU AR
PCIE PORT BIFURCATION STRAPS 1 2 CFG13 Add T423 for CNVi Intel request
20 of 20
@ RC417 1K_0201_1%
11: DEVICE1 FUNTION 1, DEVICE 1 FUNCTION2 DISABLED
10: DEVICE1 FUNTION 1, ENABLED DEVICE 1 FUNCTION2 DISABLED

CFG5,6
PCH/ PCH LESS MODE SELECTION PMSYNC AYNC MODE- PM SYNC

01: DEVICE1 FUNTION 1, DISABLED, DEVICE 1 FUNCTION2 ENABLED 1: (DEFAULT)SYNCHCRONOUS (1 24 MHZ CYCLE PER BIT)
00: DEVICE 1 FUNCTION 1 ENABLED, DEVICE 1 FUNCTION 2 ENABLED
CFG13 0: ASYNC - 4-24MHZ CYCLES PER BIT

1 2 CFG14 1 2 CFG15
@ RC418 1K_0201_1% @ RC419 1K_0201_1%
A A

DELL CONFIDENTIAL/PROPRIETARY
CFG14 CFG15 Compal Electronics, Inc.

https://Dr-Bios.com
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, CPU(8/14)CFG,RSVD
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 13 of 109
5 4 3 2 1
 5 4 3 2 1

+1.0V_VCCST TOUCH_SCREEN_PD# 1 2 TOUCH_SCREEN_PD#_R

@ RC566 0_0201_5%
RC2181 2 1K_0201_1% H_THERMTRIP#_R

@ RC2191 2 49.9_0201_1% H_CATERR# Merion Limit height

CPU@
UC1D
QC4 change to SB000014O00 H=0.6mm(MAX)
H_CATERR# AA4 T6 +3.3V_RUN
AR1 CATERR# PROC_TCK U6 CPU_XDP_TCLK <79>
+1.0V_VCCSTG <58> PECI_EC PROCHOT#_R PECI PROC_TDI CPU_XDP_TDI <79>
<58,84,88> PROCHOT# PROCHOT# RC84 1 2 499_0402_1% Y4 CPU MISC JTAG Y5
PROCHOT# PROC_TDO CPU_XDP_TDO <79>

1
1 2 H_THERMTRIP#_R BJ1 T5 TOUCH_SCREEN_PD# don't move to RPC,
<23,24,59> H_THERMTRIP# THRMTRIP# PROC_TMS CPU_XDP_TRST# CPU_XDP_TMS <79>
@ RC559 0_0201_5% AB6 @ RC104
RC5581 2 1K_0201_1% PROCHOT# U1 PROC_TRST# 1 2 10K_0201_5%
<79> XDP_OBS0_R U2 BPM#_0 @ RC86 51_0201_5%
<79> XDP_OBS1_R BPM#_1

1
1 XDP_OBS2_R U3 W6 @ QC4
T366 @ PAD~D PCH_JTAG_TCK <79>

2
D 1 XDP_OBS3_R U4 BPM#_2 PCH_TCK U5 TOUCH_SCREEN_PD# 2 S1
D
T367 @ PAD~D BPM#_3 PCH_TDI PCH_JTAG_TDI <79> G1 TOUCH_SCREEN_PD
W5 D1 6
PCH_TDO P5 PCH_JTAG_TDO <79> 4
+3.3V_RUN MEM_INTERLEAVED PCH_TMS PCH_JTAG_TMS <79> TOUCH_SCREEN_PD S2
CE9 Y6 5
TOUCH_SCREEN_PD# GPP_E3/CPU_GP0 PCH_TRST# XDP_JTAGX CPU_XDP_TRST# <79> G2
CN3 P6 D2
TOUCHPAD_INTR# GPP_E7/CPU_GP1 PCH_JTAGX XDP_JTAGX <79>
CB34 1 2 +1.0V_VCCSTG PJX138K_SOT563-6
<58,63> TOUCHPAD_INTR#

3
@ RC82 1 2 10K_0201_5% TOUCH_SCREEN_PD# CC35 GPP_B3/CPU_GP2 @ RC87 1K_0201_5%
<38> TOUCH_SCREEN_DET# GPP_B4/CPU_GP3 W2
PROC_PREQ# CPU_XDP_PREQ# <79> 1219 Change TOUCH_SCREEN_PD#_R <38>
2 1 TOUCHPAD_INTR# W1
CPU_POPIRCOMP PROC_PRDY# CPU_XDP_PRDY# <79>
RC567 10K_0201_5% BP27
PCH_POPIRCOMP BW25 PROC_POPIRCOMP
PCH_OPIRCOMP

EDRAM_OPIO_RCOMP L5
RSVD70

1
EOPIO_RCOMP N5
Reserve for Panel side TS PH voltage problem

49.9_0201_1%

49.9_0201_1%
RSVD71

RC106

RC107

1
49.9_0201_1%

49.9_0201_1%
WHL-U42_BGA1528

@ RC108

@ RC109
4 of 20

2
+3.3V_ALW_PCH
need check

RC108,RC109

2
This is applicable only for CFL U43e. These pins are
RSVD in WHL and hence can be left unconnected
@ RC843
10K_0201_5%

1
MEM_INTERLEAVED

PCH_JTAG_TDO PCH_JTAG_TDI XDP_JTAGX

@ESD@ CC303

@ESD@ CC304

@ESD@ CC305

1
C C

0.1U_0201_25V6K

0.1U_0201_25V6K

0.1U_0201_25V6K
1 1 1
RC844
10K_0201_5%
2 2 2

2
DIMM TYPE

HIGH Interleave

ESD request,Place near CPU side.

LOW Non-Interleave

B B

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, CPU(9/14)XDP
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 14 of 109
5 4 3 2 1
 5 4 3 2 1

PSC(Primary side cap) : Place as close to the package as possible

BSC(Backside cap) : Place on secondary side, underneath the package
+VCC_CORE +VCC_CORE
CPU@
Component placement order: UC1L
Package edge > 0402 caps > 0805 caps > Bulk caps >Power source AN9
CPU POWER 1 OF 4
AW24
AN10 VCCCORE5 VCCCORE35 AW25
AN24 VCCCORE1 VCCCORE36 AW26
+VCC_CORE: 0.55~1.5V, 29A AN26
AN27
VCCCORE2
VCCCORE3
VCCCORE37
VCCCORE38
AW27
AY24
+VCC_EDRAM: 1V, 2.5A AP2
AP9
VCCCORE4
VCCCORE6
VCCCORE44
VCCCORE45
AY26
BA5
D AP24 VCCCORE9 VCCCORE48 BA7 D
+V1.8S_EDRAM: 1.8V, 50mA - REMOVE AP26 VCCCORE7
VCCCORE8
VCCCORE49
VCCCORE50
BA8
AR5 BA25
+VCC_EOPIO: 0.8~1V, 2A - REMOVE AR6 VCCCORE13
VCCCORE14
VCCCORE46
VCCCORE47
BA27
AR7 BB2
AR8 VCCCORE15 VCCCORE51 BB26
AR10 VCCCORE16 VCCCORE52 BC5
AR25 VCCCORE10 VCCCORE56 BC6
AR27 VCCCORE11 VCCCORE57 BC7
CPU@ AT9 VCCCORE12 VCCCORE58 BC9
UC1O AT24 VCCCORE19 VCCCORE59 BC10
AT26 VCCCORE17 VCCCORE53 BC26
RESERVED SIGNALS VCCCORE18 VCCCORE54
K12 AA24 AU5 BC27
K14 RSVD48 RSVD38 AA26 AU6 VCCCORE24 VCCCORE55 BD5
K15 RSVD49 RSVD39 AB25 AU7 VCCCORE25 VCCCORE63 BD8
K17 RSVD50 RSVD40 AC24 AU8 VCCCORE26 VCCCORE64 BD10
K18 RSVD51 RSVD41 AC25 AU9 VCCCORE27 VCCCORE60 BD25
K20 RSVD52 RSVD42 AC26 AU24 VCCCORE28 VCCCORE61 BD27
L25 RSVD53 RSVD43 AD24 AU25 VCCCORE20 VCCCORE62 BE9
M24 RSVD54 RSVD44 AD26 AU26 VCCCORE21 VCCCORE69 BE24
M26 RSVD55 RSVD45 V25 VCCEOPIO_SENSE 1 AU27 VCCCORE22 VCCCORE65 BE25
P24 RSVD56 RSVD46 T25 VSSEOPIO_SENSE 1 PAD~D @ T368 AV2 VCCCORE23 VCCCORE66 BE26 +VCC_CORE
P26 RSVD57 RSVD47 PAD~D @ T369 AV5 VCCCORE30 VCCCORE67 BE27
R24 RSVD58 AV7 VCCCORE32 VCCCORE68 BF2
RSVD59 VCCCORE33 VCCCORE70

100_0402_1%
R25 AV10 BF9
R26 RSVD60 AV27 VCCCORE29 VCCCORE73 BF24
RSVD61 VCCCORE31 VCCCORE71 Close CPU

RC150
AW5 BF26
AW6 VCCCORE39 VCCCORE72 BG27 @ RC430
AW7 VCCCORE40 VCCCORE74 0_0201_5%

2
W25 AW8 VCCCORE41 AN6 VCCSENSE_R 1 2
V24 RSVD62 AW9 VCCCORE42 VCC_SENSE AN5 VSSSENSE_R 1 2 VCC_SENSE_IA <88>
Y25 RSVD63 AW10 VCCCORE43 VSS_SENSE VSS_SENSE_IA <88>
RSVD64 VCCCORE34

1
H_CPU_SVIDALRT#

100_0402_1%
C Y24 AA3 0_0201_5% C
RSVD65 VIDALERT# @ RC429
+VCC_CORE_G0 VIDSCLK_R

RC151
1 BB9 AA1
T371 @ PAD~D +VCC_CORE_G1 RSVD3 VIDSCK
1 BC24
T372 @ PAD~D +VCC_CORE_G2 RSVD4 VIDSOUT_R
WHL-U42_BGA1528 1 AY9 AA2
T373 @ PAD~D

2
1 +VCC_CORE_G3 BB24 RSVD1 VIDSOUT
T374 @ PAD~D RSVD2
15 of 20 Y3
RSVD5
BG3 +1.0V_VCCSTG_R 2 1
VCCSTG1 @ RC153 0_0603_5% +1.0V_VCCSTG
WHL-U42_BGA1528 [email protected]
12 of 20

VCCOPC,VCCOPC_1P8,VCCEOPIO for SKYLAKE-U 2+3e

(w/ on package cache)

+1.0V_VCCST
SVID ALERT

1
56_0402_1%
CAD Note: Place the PU resistors close to CPU

RC154
RC154 close to CPU 1000 - 1500mils
B B

2
2 1 H_CPU_SVIDALRT#
<88> VIDALERT_N
220_0402_5% RC155

+1.0V_VCCST
SVID DATA

100_0402_1%
1
CAD Note: Place the PU resistors close to CPU

RC156
RC156close to CPU 1000 - 1500mils

2
0_0201_5% 2 1 @ RC157 VIDSOUT_R
<88> VIDSOUT

+1.0V_VCCST
SVID CLK

1
43_0402_5%
@ RC158
CAD Note: Place the PU resistors close to CPU
RC158close to CPU 1000 - 1500mils

2
0_0201_5% 2 1 @ RC159 VIDSCLK_R
<88> VIDSCLK
A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, CPU(10/14)PWR-VCC CORE
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 15 of 109
5 4 3 2 1
 5 4 3 2 1

THE BALLOUT ONLY FOR WHL ES2 CPU

D D
+VCCGT: 0.55~1.5V, 54A
+VCCGTX : 0.55~1.5V, 7A
+VCC_CORE +VCC_GT +VCC_GT

1.5V@54A
CPU@
UC1M
CPU POWER 2 OF 4
A5 D15
A6 VCCGT8 VCCGT58 D17
A8 VCCGT9 VCCGT59 D18
A11 VCCGT10 VCCGT60 D20
A12 VCCGT1 VCCGT61 E4
A14 VCCGT2 VCCGT64 F5
A15 VCCGT3 VCCGT69 F6
A17 VCCGT4 VCCGT70 F7
A18 VCCGT5 VCCGT71 F8
A20 VCCGT6 VCCGT72 F11
VCCGT7 VCCGT65 F14
AA9 ES1/ES2 VCCGT66 F17
AB2 VCCGT11/VCCCORE75 VCCGT67 F20
AB8 VCCGT13/VCCCORE76 VCCGT68 G11
AB9 VCCGT14/VCCCORE77 VCCGT73 G12
AB10 VCCGT15/VCCCORE78 VCCGT74 G14
AC8 VCCGT12/VCCCORE79 VCCGT75 G15
AD9 VCCGT16/VCCCORE80 VCCGT76 G17
AE8 VCCGT17/VCCCORE81 VCCGT77 G18
AE9 VCCGT19/VCCCORE82 VCCGT78 G20
C AE10 VCCGT20/VCCCORE83 VCCGT79 H5 C
AF2 VCCGT18/VCCCORE84 VCCGT87 H6
AF8 VCCGT22/VCCCORE85 VCCGT88 H7
AF10 VCCGT23/VCCCORE86 VCCGT89 H8
AG8 VCCGT21/VCCCORE87 VCCGT90 H11
AG9 VCCGT24/VCCCORE88 VCCGT80 H12
AH9 VCCGT25/VCCCORE89 VCCGT81 H14
AJ8 VCCGT26/VCCCORE90 VCCGT82 H15
AJ10 VCCGT28/VCCCORE91 VCCGT83 H17
AK2 VCCGT27/VCCCORE92 VCCGT84 H18
AK9 VCCGT29//VCCCORE93 VCCGT85 H20
AL8 VCCGT30/VCCCORE94 VCCGT86 J7
AL9 VCCGT32/VCCCORE95 VCCGT95 J8
AL10 VCCGT33/VCCCORE96 VCCGT96 J11
AM8 VCCGT31/VCCCORE97 VCCGT91 J14
V2 VCCGT34/VCCCORE98 VCCGT92 J17
Y10 VCCGT115/VCCCORE99 VCCGT93 J20
Y8 VCCGT119/VCCCORE100 VCCGT94 K2
VCCGT120/VCCCORE101 VCCGT98 K11
B3 VCCGT97 L7
B4 VCCGT39 VCCGT100 L8
B6 VCCGT40 VCCGT101 L10
B8 VCCGT41 VCCGT99 M9
B11 VCCGT42 VCCGT102 N7
B14 VCCGT35 VCCGT104 N8
B17 VCCGT36 VCCGT105 N9
B20 VCCGT37 VCCGT106 N10
C2 VCCGT38 VCCGT103 P2
C3 VCCGT49 VCCGT107 P8
C6 VCCGT51 VCCGT108 R9
C7 VCCGT52 VCCGT109 T8
C8 VCCGT53 VCCGT111 T9 +VCC_GT
B C11 VCCGT54 VCCGT112 T10 B
C12 VCCGT43 VCCGT110 U8

100_0402_1%
C14 VCCGT44 VCCGT114 U10
VCCGT45 VCCGT113

1
C15

RC160
C17 VCCGT46 V9
C18 VCCGT47 VCCGT116 W8
VCCGT48 VCCGT117
Close CPU
C20 W9
D4 VCCGT50 VCCGT118

2
D7 VCCGT62
D11 VCCGT63 E3 VCCGT_SENSE_R@ RC632 1 2 0_0201_5%
D12 VCCGT55 VCCGT_SENSE D2 VSSGT_SENSE_R@ RC631 1 2 0_0201_5% VCC_SENSE_GT <88>
D14 VCCGT56 VSSGT_SENSE VSS_SENSE_GT <88>
VCCGT57

100_0402_1%
WHL-U42_BGA1528
13 of 20

RC161
2
A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, CPU(11/14)PWR-VCCGT
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 16 of 109
5 4 3 2 1
 5 4 3 2 1

+1.2V_DDR: 1.2V, 3.5A

+1.0V_VCCST: 1V, 120mA; VCCPLL: 1V, 120mA RF Request
+1.2V_MEM
+1.0V_VCCSTG: 1V, 40mA
+VCCPLL_OC: 1.2V, 260mA
+1.0VS_VCCIO: 0.85~0.95V, 3.1A

RF@ CC1478

RF@ CC1479
1200P_0402_50V7K

680P_0402_50V7K
1 1
D
+VCC_SA: 1.15V, 5.1A D

2 2
+1.0VS_VCCIO
+1.2V_MEM CPU@
+1.0V_VCCST UC1N
[email protected]
CPU POWER 3 OF 4 VCCIO1
PSC [email protected] AK26
[email protected] AH32 VDDQ1 VCCIO2 AL24
close to package AH36 VDDQ2 VCCIO3 AL25
AM36 VDDQ3 VCCIO4 AL26

1U_0201_6.3V6M
place as close as CPU VDDQ4 VCCIO5
1 AN32 AL27
PDG0.8 P.479 0402 0801 Confirmed with AW32 VDDQ5 VCCIO6 AM25
Intel can change to 0201 AY36 VDDQ6 VCCIO7 AM27

CC28
BE32 VDDQ7 VCCIO8 BH24
+1.2V_MEM +VCCPLL_OC 2 BH36 VDDQ8 VCCIO9 BH25
+VCCPLL_OC source 1 2
R32
Y36
VDDQ9
VDDQ10
VDDQ11
VCCIO10
VCCIO11
VCCIO12
BH26
BH27
BJ24
@ RZ119 0_0402_5% VCCIO13 BJ26
VCCIO14 BP16 +VCC_SA
BC28 VCCIO15 BP18
UZ27 RSVD1 VCCIO16
1 BP11 BG8 [email protected]
2 1 2 VIN1 +1.0V_VCCSTG BP2 VCCST1 VCCSA2 BG10
CZ102 1U_0201_6.3V6M VIN2 VCCST2 VCCSA1 BH9
7 6 VCCSA3 BJ8
VIN thermal VOUT BG1 VCCSA5 BJ9
2 VCCSTG1 VCCSA6
3 BG2 BJ10
+5V_ALW VBIAS VCCSTG2 VCCSA4 +1.0VS_VCCIO
CZ303 BK8
VCCSTG_EN 1 2 VCCPLL_EN 4 5 BL27 VCCSA9 BK25
0.1U_0201_10V6K
@ RZ120 0_0201_5% ON GND 1 BM26 VCCPLL_OC1 VCCSA7 BK27
+1.0V_VCCSTG VCCPLL_OC2 VCCSA8 BL8 Close CPU
VCCSA13

1
EM5201V_DFN8_3X3 BR11 BL9
1 2 BT11 VCCPLL1 VCCSA14 BL10 RC163
<11,17,42,59,79> SIO_SLP_S3# VCCPLL2 VCCSA10
@ RZ1418 0_0201_5% [email protected] BL24 100_0402_1%
VCCSA11 BL26
VCCSA12 BM24

1U_0201_6.3V6M

2
1 2 VCCSA15 BN25
<9,11,66,79,87> SIO_SLP_S0# 1 VCCSA16
@ RZ1419 0_0201_5% 0801 Confirmed with

CC29
PDG0.8 P.479 0402 Intel can change to 0201 BP28 VCCIO_SENSE
VCCIO_SENSE VSSIO_SENSE VCCIO_SENSE <87>
BP29
C 2 VSSIO_SENSE VSSIO_SENSE <87> C

BE7 @ RC425 1 2 0_0201_5%

Follow 575962 RVP V0P7,VCCSFR_OC enable gated by VCCSTG_EN VSSSA_SENSE
VCCSA_SENSE
BG7 @ RC426 1 2 0_0201_5%

1
100_0402_1%
W HL-U42_BGA1528 @ RC165
0_0201_5%

RC164
14 of 20
+VCCPLL_OC 1 2
+VCC_SA

2
RC166 100_0402_1%
PSC [email protected] +1.0V_VCCST
close to package
Follow RVP rev1.0
PSC
[email protected]

1U_0201_6.3V6M

0.1U_0201_10V6K
close to package VSS_SENSE_SA <88>
1 1
+1.0V_VCCSTG source PDG0.8 P.479 0402 PDG0.8 P.479 VCC_SENSE_SA <88>

CC430

CC1480

22U_0603_6.3V6M
0801 Confirmed with 0805 Reserve

1U_0201_6.3V6M

0.1U_0201_10V6K
+1.0V_VCCSTG +1.0V_VCCST Intel can change to 0201 MOW WW30

CC96
2 2 1x22U/47U 0805 1 1 1
PDG0.8 P.479 0201

CC31

CC1462
1 2
+1.0V_PRIM @ RZ151 0_0603_5%
pop option with UZ19 2 2 2
1

+3.3V_RUN 2 1 JUMP@
CZ105 1U_0201_6.3V6M UZ19 PJP2
1 PAD-OPEN1x1m PDG0.8 P.479 0402
2 VIN1 0801 Confirmed with
VIN2
2

Intel can change to 0201

100K_0402_5%

+5V_ALW +1.0V_VCCSTG_C 1
RZ1422

7 6 2 CC96 follow Intel MOW WW30 change to pop

VIN thermal VOUT CZ106 but 22U_0805 shortage,so use 22U_0603.
3 0.1U_0201_10V6K
VBIAS
1

+3.3V_ALW 4 5
@ RZ1420 1 2 ON GND
<6,87> CPU_C10_GATE#
0_0201_5%
EM5201V_DFN8_3X3
4.4mohm/6A
5

1 TR=12.5us@Vin=1.05V
P

B 4 VCCSTG_EN
2 O WHL_U PDG rev0.8 P.479
<17,58,59,78,87> RUN_ON A WHL_U PDG rev0.8 P.479
G

B VCCIO: B
UZ35 VDDQ: Primary Side cap
3

MC74VHC1G08DFT2G_SC70-5
Primary Side cap 4x 1uF 0201
1x 22uF 0603 + 6x 10uF 0402 +1.0VS_VCCIO
@ RZ320 1 2 0_0201_5%
Primary or Secondary Side
Secondary Side cap 6x 10uF 0402
Follow 575962 RVP V0P7,VCCSTG RAIL design +1.2V_MEM
4x 1uF 0402/0201 + 3x 10uF 0402 Primary Side PDG P.479 0201

Placeholder Only

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
1 1 1 1 4x 10uF 0402
Primary Side PDG P.479 22U 0603,10U 0402

CC1458

CC1459

CC1460

CC1461
2 2 2 2
22U_0603_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
+1.0V_VCCST source 1 1 1 1 1 1 1
CC32

CC33

CC34

CC35

CC36

CC37

CC38
@ RC864
0_0603_5% PDG P.479 0402
2 1
RC864 Co-lay 2 2 2 2 2 2 2 Primary or Secondary Side
JUMP@ with PJP1
+1.0V_PRIM PJP1
UZ21 2 1

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
+1.0V_VCCST 1 1 1 1 1 1
2 1 1

CC51

CC52
CC234

CC235

CC236

CC237
CZ100 1U_0201_6.3V6M 2 VIN1
VIN2 PAD-OPEN1x1m
+5V_ALW 7 6 +1.0V_VCCST_C 1 2
Secondary SidePDG P.479 1U 0402/0201,10U 0402
2 2 2 2 2 2
VIN thermal VOUT CZ101 0.1U_0201_10V6K
3
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

VBIAS
VCCST_EN 1 1 1 1 1 1 1
1 2 4 5 PDG P.479 0402
CC45

CC46

CC195
CC1454

CC1455

CC1456

CC1457
<11,17,42,59,79> SIO_SLP_S3#
@ RZ1416 0_0201_5% ON GND Placeholder
1 2 EM5201V_DFN8_3X3 2 2 2 2 2 2 2
<11,79,86,87> SIO_SLP_S4#
@ RZ1417 0_0201_5%

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
1 1 1 1

CC39

CC40

CC41

CC42
1 2
4.4mohm/6A
<17,58,59,78,87> RUN_ON
@ RZ1423 0_0201_5% TR=12.5us@Vin=1.05V
2@ 2@ 2@ 2@
A A
Follow 575962 V0p7 PDG page519,Premium design Vccst gated by RUN_ON

DELL CONFIDENTIAL/PROPRIETARY

https://Dr-Bios.com
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT CPU(12/14)PWR-VCCIO,MEM
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 17 of 109
5 4 3 2 1
 5 4 3 2 1

close UC1 <100mil

+1.0V_PRIM +1.0V_APLL

LC1 1 2 LQM18PN2R2NC0L_2P~D

@ RC422 +3.3V_ALW_PCH
0.01_0603_1% +1.0V_PRIM
1 1

22U_0603_6.3V6M

22U_0603_6.3V6M
1 2 [email protected]

@ CC85

@ CC86
+1.8V_PRIM [email protected]
2 2 [email protected] CC67/CC68 close to BP20 PDG0.8 P.505 1

1U_0201_6.3V6M
CPU@ 0402 reserve
CC75 close to CP29
CC98 close to CP17 UC1P 0801 Confirmed with

@ CC75
1 1

1U_0201_6.3V6M

1U_0201_6.3V6M
Intel can change to 0201,
1

1U_0201_6.3V6M
D CPU POWER 4 OF 4 Follow MOW Delete CC74 D
BP20 CB16 2

CC68

CC67
PDG0.8 P.505 0402 BW16 VCCPRIM_1P05_1 VCCPRIM_3P3_3

CC98
0801 Confirmed with 2 2 BW18 VCCPRIM_1P05_9 +RTC_CELL_PCH
Intel can change to 0201 2 BW19 VCCPRIM_1P05_10
BY16 VCCPRIM_1P05_11 BR23 [email protected]
PDG0.8 P.504 0402 CA14 VCCPRIM_1P05_12 VCCRTC
0801 Confirmed with VCCPRIM_1P05_14 BY20 1 1 CC72/CC73 close to BR23

1U_0201_6.3V6M
+1.0V_PRIM

0.1U_0201_6.3V6K
Intel can change to 0201*2 CC15 VCCPRIM_1P05_13 BP24 DCPRTC
CD15 VCCPRIM_1P8_1 DCPRTC

CC72

CC73
1U_0201_6.3V6M
CD16 VCCPRIM_1P8_4 PDG P.505 0201 reserve
VCCPRIM_1P8_5 1 2 2
0809 BSOD +3.3V_ALW_PCH CP17 BR20

@ CC76
+1.0V_PRIM Pop LC2 INDUCTOR,CC100 22U_0603 +1.0V_CLK VCCPRIM_1P8_8 VCCPRIM_1P05_3 +1.0V_PRIM
depop RC175 CB22 BT12
Add CC103 22U_0603 [email protected] +1.0V_APLL
CB23 VCCPRIM_3P3_4 VCCAPLL_1P05_3 2
LC2 1 2 LQM18PN2R2NC0L_2P~D CC22 VCCPRIM_3P3_5 BP14 PDG0.8 P.505 0402
[email protected] +1.0V_PRIM
CC23 VCCPRIM_3P3_6 VCCA_BCLK_1P05 0801 Confirmed with
@ RC175 CD22 VCCPRIM_3P3_7 BR14 Intel can change to 0201
VCCPRIM_3P3_8 VCCAPLL_1P05_1
[email protected] +1.0V_APLL PCH Internal VRM
0.01_0603_1% 1 1 1 1 CD23 close to BP24

1U_0201_6.3V6M

1U_0201_6.3V6M
22U_0603_6.3V6M

22U_0603_6.3V6M
1 2 +1.0V_PRIM_CORE CP29 VCCPRIM_3P3_9
VCCPRIM_3P3_10 BU12 +VCCDPHY_1P24
[email protected]
CC83

CC70
CC103

CC100

VCCA_SRC_1P05 +1.0V_PRIM
[email protected] BU15

4.7U_0402_6.3V6M
2 2 2 2 BU22 VCCPRIM_CORE1 CP5
CC66 close to BV18 VCCPRIM_CORE2 VCCA_XTAL_1P05
[email protected] +1.0V_CLK PCH Internal VRM
BV15 1 close to CP25
BV16 VCCPRIM_CORE3 BY24 [email protected]

CC84
1

1U_0201_6.3V6M
VCCPRIM_CORE4 VCCDPHY_1P24_2 +VCCLDOSRAM_1P24
PDG0.8 P.504 0402 reserve BV18 CA24 PDG P.505 0402

@ CC66
VCCPRIM_CORE5 VCCDPHY_1P24_4 CAD NOTE: CAPs
0801 Confirmed with BV19 PCH Internal VRM
Intel can change to 0201 BV20 VCCPRIM_CORE6 BY23 2
CC83/CC70 close to CP5 VCCPRIM_CORE7 VCCDPHY_1P24_1
CC100/CC103 one is close to the PDG0.8 P.505 0402 2 BV22 CA23
0801 Confirmed with BW20 VCCPRIM_CORE8 VCCDPHY_1P24_3 CP25 +3.3V_ALW_DSW
CPU and the other is far from the CPU. Intel can change to 0201*2 +VCCPDSW_1P05 VCCPRIM_CORE9 VCCDPHY_1P24_5
BW22
CA12 VCCPRIM_CORE10 BT23
VCCPRIM_CORE11 VCCDSW_3P3_2
[email protected]
[email protected] CA16
CA18 VCCPRIM_CORE12 BR12 [email protected]
PCH Internal VRM 1

1U_0201_6.3V6M
VCCPRIM_CORE13 VCCA_19P2_1P05 +1.0V_PRIM
close to BT24 CA19

@ CC1463
1

1U_0201_6.3V6M
CA20 VCCPRIM_CORE14
VCCPRIM_CORE15
CC1463 close to BR24
PDG0.8 P.505 0402 0801 Confirmed with CB12 +1.8V_PRIM

CC65
Intel can change to 0201 CB14 VCCPRIM_CORE16 2 PDG0.8 P.505 0402 reserve
2 CB15 VCCPRIM_CORE17 CC18 0801 Confirmed with
C PDG rev0.8 P.509 [email protected] C
+1.0V_APLL VCCPRIM_CORE18 VCCPRIM_1P8_2 CC19 Intel can change to 0201
Place an 22uF edge cap not more than VCCPRIM_1P8_3
12 mm away measuring from package edge. BT24 CD18 1

1U_0201_6.3V6M
VCCDSW_1P05 VCCPRIM_1P8_6 CD19

@ CC1464
+1.0V_MPHYGT BU14 VCCPRIM_1P8_7 CP23
[email protected] VCCAPLL_1P05_4 VCCPRIM_1P8_9 CC1464 close to CP23
PDG0.8 P.505 0402 reserve
[email protected] BV12 BW23 [email protected] 2 0801 Confirmed with
+1.0V_PRIM +1.0V_MPHYGT VCCPRIM_MPHY_1P05_1 VCCPRIM_3P3_2 +3.3V_ALW_PCH Intel can change to 0201
JUMP@ BW12

22U_0603_6.3V6M
PJP3 BW14 VCCPRIM_MPHY_1P05_3
1 VCCPRIM_MPHY_1P05_4
1 2 PDG P.504 0603 BY12

CC71
BY14 VCCPRIM_MPHY_1P05_5 BP23 [email protected] +3.3V_ALW_PCH
PAD-OPEN1x3m VCCPRIM_MPHY_1P05_6 VCCPRIM_3P3_1
2 [email protected] BV2 CB36
+1.0V_AMPHYPLL CORE_VID0 <87>
+1.0V_MPHYGT source +1.0V_APLL [email protected] BR15
VCCAMPHYPLL_1P05

VCCAPLL_1P05_2
GPP_B0/CORE_VID0
GPP_B1/CORE_VID1
CB35 CORE_VID1 <87>

+1.0V_PRIM
[email protected] CC12
VCCDUSB_1P05
+3.3V_ALW_PCH LC4 [email protected] BR24
+3.3V_ALW_DSW VCCDSW_3P3_1
close UC1 <120mil BLM18EG221TN1D_2P~D
0809 BSOD 1 2 VCCHDA [email protected] BT20
+1.0V_MPHYGT Pop LC3 INDUCTOR,CC102 22U_0603 +1.0V_AMPHYPLL VCCHDA
depop RC173
1031 change
Add CC104 22U_0603
PDG P.505 no decoup. 2 PDG P.505 no decoup. +3.3V_ALW_PCH [email protected] BV23
VCCSPI
1

BT18
+1.0V_PRIM VCCPRIM_1P05_4
LC3 1 2 LQM18PN2R2NC0L_2P~D @RF@ RC845 RF@ CC95 BT19
BU18 VCCPRIM_1P05_5
0_0201_5% 2.2P_0201_25V VCCPRIM_1P05_7
@ RC173 1 BU19
1 1 1 1
1U_0201_6.3V6M

1U_0201_6.3V6M
22U_0603_6.3V6M

22U_0603_6.3V6M

0.01_0603_1% VCCPRIM_1P05_8
+1.0V_MPHYGT
2

1 2 BT22
CC80

CC69
CC104

CC102

+1.0V_PRIM VCCPRIM_1P05_6
1 BP22
2 2 2 2 RF@ CC77 VCCPRIM_1P05_2
2.2P_0201_25V BV14
VCCPRIM_MPHY_1P05_2
2 WHL-U42_BGA1528
16 of 20
CC80/CC69 close to BV2
CC102/CC104 one is close to the PDG0.8 P.505 0402
CPU and the other is far from the CPU. 0801 Confirmed with
B Intel can change to 0201*2 B

+3.3V_ALW_DSW +3.3V_ALW_PCH
QC7 change to SB00000SS00
1 2 For Merion layout limit height
@NDS3@RC440 0_0402_5% +3.3V_ALW

1 2
@ RC214 0_0201_5%
DS3@ QC7
NTK3139PT1G_SOT723-3

1 2 +3.3V_ALW_DSW_R 1 3
D

DS3@ RC439 0_0402_5%

499K_0402_1%
DS3@ RC432
1
22U_0402_6.3V6M

22U_0402_6.3V6M

1 1
G
2
@ CC279

@ CC280

2 2
2

100K_0402_5%
2
0.1U_0402_25V6K

49.9K_0402_1%
DS3@ RC433

RC431
1

@
CC340
2

RC439RC440RE536RC215RC441RC442
2

A Support DS3 V X V X V X A
1

D
L2N7002WT1G_SC-70-3

No Support DS3 X V X V X V
DS3@ QC6

2
VCCDSW_EN_GPIO <11>
G
'V' mean POP, 'X' mean DE-POP S
3

DELL CONFIDENTIAL/PROPRIETARY

https://Dr-Bios.com
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, CPU(13/14)PCH PWR
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 18 of 109
5 4 3 2 1
 5 4 3 2 1

CPU@
UC1R CPU@ CPU@
D GND 1 OF 3
UC1S UC1T D
CR34 BL7 BT35 GND 2 OF 3 BY25 GND 3 OF 3
BT5 VSS_1 VSS_73 AE25 D6 VSS_145 VSS_217 J18 N6 CF23
BY5 VSS_2 VSS_74 BM33 AL32 VSS_146 VSS_218 AU32 B37 VSS_290 VSS_362 V4
CP35 VSS_3 VSS_75 CM5 BT36 VSS_147 VSS_219 BY28 CB3 VSS_291 VSS_363 BE30
CM37 VSS_4 VSS_76 AE27 D8 VSS_148 VSS_220 J21 P10 VSS_292 VSS_364 CF28
CK37 VSS_5 VSS_77 BM35 AL7 VSS_149 VSS_221 AV25 B5 VSS_293 VSS_365 W10
AW1 VSS_6 VSS_78 CM9 D9 VSS_150 VSS_222 BY33 CB33 VSS_294 VSS_366 BE31
CM1 VSS_7 VSS_79 AE30 AM10 VSS_151 VSS_223 J24 P3 VSS_295 VSS_367 CF3
BD6 VSS_8 VSS_80 BM36 BU11 VSS_152 VSS_224 AV28 B7 VSS_296 VSS_368 W27
AY4 VSS_9 VSS_81 CN13 E23 VSS_153 VSS_225 BY35 CB4 VSS_297 VSS_369 CF4
B34 VSS_10 VSS_82 AE7 AM28 VSS_154 VSS_226 J33 P33 VSS_298 VSS_370 W30
E35 VSS_11 VSS_83 BM9 E27 VSS_155 VSS_227 AV3 B9 VSS_299 VSS_371 BF3
A4 VSS_12 VSS_84 CN17 AM33 VSS_156 VSS_228 BY36 CB7 VSS_300 VSS_372 CG33
AE24 VSS_13 VSS_85 AF27 BU23 VSS_157 VSS_229 J36 P36 VSS_301 VSS_373 W7
AE26 VSS_14 VSS_86 BN30 E29 VSS_158 VSS_230 AV33 BA10 VSS_302 VSS_374 BF33
AF25 VSS_15 VSS_87 CN21 AM35 VSS_159 VSS_231 J6 CC11 VSS_303 VSS_375 CG7
AG24 VSS_16 VSS_88 AF3 BU24 VSS_160 VSS_232 AV36 P4 VSS_304 VSS_376 BF36
AG26 VSS_17 VSS_89 BN7 E31 VSS_161 VSS_233 C1 BA28 VSS_305 VSS_377 Y26
AH24 VSS_18 VSS_90 CN25 BU25 VSS_162 VSS_234 K21 P7 VSS_306 VSS_378 BF4
AH25 VSS_19 VSS_91 AF30 E33 VSS_163 VSS_235 AV4 BA3 VSS_307 VSS_379 CH31
B2 VSS_20 VSS_92 CN29 AN25 VSS_164 VSS_236 C21 CC20 VSS_308 VSS_380 Y27
B36 VSS_21 VSS_93 AF33 BU7 VSS_165 VSS_237 K22 R27 VSS_309 VSS_381 BG25
C36 VSS_22 VSS_94 BP15 E9 VSS_166 VSS_238 AV6 BB3 VSS_310 VSS_382 Y30
C37 VSS_23 VSS_95 AF36 AN28 VSS_167 VSS_239 C25 CC25 VSS_311 VSS_383 BG28
CN1 VSS_24 VSS_96 AF4 BV11 VSS_168 VSS_240 K24 R28 VSS_312 VSS_384 CJ11
CN2 VSS_25 VSS_97 CN5 F12 VSS_169 VSS_241 AV8 BB33 VSS_313 VSS_385 Y33
CN37 VSS_26 VSS_98 AF7 AN29 VSS_170 VSS_242 C29 CC28 VSS_314 VSS_386 CJ14
CP2 VSS_27 VSS_99 BP25 F15 VSS_171 VSS_243 K25 R29 VSS_315 VSS_387 Y35
C D1 VSS_28 VSS_100 CN9 AN30 VSS_172 VSS_244 AW28 BB36 VSS_316 VSS_388 BH28 C
A32 VSS_29 VSS_101 AG10 F18 VSS_173 VSS_245 C33 CC31 VSS_317 VSS_389 CJ19
F33 VSS_30 VSS_102 BP3 AN31 VSS_174 VSS_246 K27 R30 VSS_318 VSS_390 Y7
A3 VSS_31 VSS_103 CP1 BV3 VSS_175 VSS_247 AW29 BB4 VSS_319 VSS_391 BH29
BJ7 VSS_32 VSS_104 BP32 F2 VSS_176 VSS_248 C4 CC7 VSS_320 VSS_392 CJ23
CJ36 VSS_33 VSS_105 CP11 AN7 VSS_177 VSS_249 K28 R31 VSS_321 VSS_393 BH32
A36 VSS_34 VSS_106 AH27 BV31 VSS_178 VSS_250 AW3 BC25 VSS_322 VSS_394 CJ28
BK10 VSS_35 VSS_107 BP33 F21 VSS_179 VSS_251 C9 CD11 VSS_323 VSS_395 BH33
CJ4 VSS_36 VSS_108 CP13 AN8 VSS_180 VSS_252 K29 T27 VSS_324 VSS_396 CJ33
AB27 VSS_37 VSS_109 AH28 BV33 VSS_181 VSS_253 AW30 CD12 VSS_325 VSS_397 BH35
BK2 VSS_38 VSS_110 BP4 F24 VSS_182 VSS_254 CA11 T30 VSS_326 VSS_398 CJ35
CK1 VSS_39 VSS_111 CP15 BV4 VSS_183 VSS_255 K3 BC29 VSS_327 VSS_399 BP19
AB3 VSS_40 VSS_112 AH29 F3 VSS_184 VSS_256 AW31 CD14 VSS_328 VSS_400 BR16
BK28 VSS_41 VSS_113 BP7 AP3 VSS_185 VSS_257 CA15 T33 VSS_329 VSS_401 BY18
AB30 VSS_42 VSS_114 CP19 BW11 VSS_186 VSS_258 K30 T35 VSS_330 VSS_402 BY19
BK3 VSS_43 VSS_115 AH30 F4 VSS_187 VSS_259 AY33 BC32 VSS_331 VSS_403 CC16
CK4 VSS_44 VSS_116 CP21 AP33 VSS_188 VSS_260 CA22 CD24 VSS_332 VSS_404 BU16
AB33 VSS_45 VSS_117 AH31 BW15 VSS_189 VSS_261 K31 T36 VSS_333 VSS_405 CC14
BK33 VSS_46 VSS_118 BR19 G21 VSS_190 VSS_262 AY35 CD25 VSS_334 VSS_406 BR22
CK7 VSS_47 VSS_119 CP27 AP36 VSS_191 VSS_263 K32 T7 VSS_335 VSS_407 BU20
AB36 VSS_48 VSS_120 AH33 G27 VSS_192 VSS_264 B12 BC8 VSS_336 VSS_408 CD20
BK4 VSS_49 VSS_121 BR25 AP4 VSS_193 VSS_265 K4 CE33 VSS_337 VSS_409 BT14
CL2 VSS_50 VSS_122 AH35 G33 VSS_194 VSS_266 B15 U26 VSS_338 VSS_410 BP12
AB4 VSS_51 VSS_123 CP37 AR28 VSS_195 VSS_267 CA25 BD28 VSS_339 VSS_411 CB24
BK7 VSS_52 VSS_124 AJ25 G35 VSS_196 VSS_268 K9 CE35 VSS_340 VSS_412 CC24
CM13 VSS_53 VSS_125 BT15 G36 VSS_197 VSS_269 B18 U7 VSS_341 VSS_413 J5
AB7 VSS_54 VSS_126 AJ28 AT33 VSS_198 VSS_270 CB11 BD33 VSS_342 VSS_414 U24
BL25 VSS_55 VSS_127 BT16 BW24 VSS_199 VSS_271 L27 CE36 VSS_343 VSS_415 BD7
CM17 VSS_56 VSS_128 CP9 G9 VSS_200 VSS_272 B21 V26 VSS_344 VSS_416 AR4
B AC10 VSS_57 VSS_129 AJ7 AT35 VSS_201 VSS_273 L33 BD35 VSS_345 VSS_417 AU4 B
BL28 VSS_58 VSS_130 CR2 H21 VSS_202 VSS_274 B23 CE7 VSS_346 VSS_418 AW4
CM21 VSS_59 VSS_131 AK3 AT36 VSS_203 VSS_275 L35 V27 VSS_347 VSS_419 BA6
AC27 VSS_60 VSS_132 CR36 BW7 VSS_204 VSS_276 B25 BD36 VSS_348 VSS_420 BC4
BL29 VSS_61 VSS_133 AK33 H27 VSS_205 VSS_277 CB18 CF11 VSS_349 VSS_421 BE4
CM25 VSS_62 VSS_134 D21 AT4 VSS_206 VSS_278 L36 V3 VSS_350 VSS_422 BE8
AC30 VSS_63 VSS_135 AK36 BY11 VSS_207 VSS_279 B27 BE10 VSS_351 VSS_423 BA4
BL30 VSS_64 VSS_136 BT25 AU10 VSS_208 VSS_280 CB19 CF14 VSS_352 VSS_424 BD4
CM29 VSS_65 VSS_137 D25 BY15 VSS_209 VSS_281 L6 V30 VSS_353 VSS_425 BG4
BL31 VSS_66 VSS_138 AK4 H9 VSS_210 VSS_282 B29 BE28 VSS_354 VSS_426 CJ2
CM31 VSS_67 VSS_139 BT28 AU28 VSS_211 VSS_283 CB2 CF19 VSS_355 VSS_427 CJ3
AD33 VSS_68 VSS_140 AL28 BY22 VSS_212 VSS_284 N25 V33 VSS_356 VSS_428 AM5
BL32 VSS_69 VSS_141 BT33 J12 VSS_213 VSS_285 B31 BE29 VSS_357 VSS_429 CM4
CM33 VSS_70 VSS_142 D5 AU29 VSS_214 VSS_286 CB20 CF2 VSS_358 VSS_430 AC5
AD35 VSS_71 VSS_143 AL29 J15 VSS_215 VSS_287 N27 V36 VSS_359 VSS_431 AG5
VSS_72 VSS_144 VSS_216 VSS_288 CB25 BE3 VSS_360 VSS_432 CR6
VSS_289 VSS_361 VSS_433
W HL-U42_BGA1528
W HL-U42_BGA1528 W HL-U42_BGA1528
17 of 20
18 of 20 19 of 20

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
MCP(14/14)VSS
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 19 of 109
5 4 3 2 1
 5 4 3 2 1

D D

Reserve
C C

B B

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
SOC or PCH / FCH
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 20 of 109
5 4 3 2 1
 5 4 3 2 1

D D

Reserve
C C

B B

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
SOC or PCH / FCH
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 21 of 109
5 4 3 2 1
 5 4 3 2 1

D D

Reserve
C C

B B

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
SOC or PCH / FCH
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 22 of 109
5 4 3 2 1
 5 4 3 2 1

<7>

<7>
DDR_A_DQS#[0..7]

DDR_A_D[0..63]
For DDR4
<7> DDR_A_DQS[0..7]

<7> DDR_A_MA[0..16]

Layout Note:
Place near JDIMM1

D
Merion Limit height
CD17 change to SGA0000AM00 H=1.0mm(MAX)
Link LOTES_ADDR0206-P001A02 done 0410 D

+1.2V_MEM
Refence WHL RVP rev0.7
WHL_U PDG rev0.8 P.92
VDDQ:
CONN@
4 near each side of the DIMM JDIMM1A
DDR_A_CLK0 DDR_A_D2 +1.2V_MEM +1.2V_MEM
connector close to VDD pins <7> DDR_A_CLK0 DDR_A_CLK#0
137
CK0(T)
REVERSE
DQ0
8
DDR_A_D5
CONN@
10U_0603_10V6M

10U_0603_10V6M

10U_0603_10V6M

10U_0603_10V6M

10U_0603_10V6M

10U_0603_10V6M

10U_0603_10V6M

10U_0603_10V6M

220U_D7_2VM_R4.5M
139 7 JDIMM1B
16x 10uF 0603 <7>
<7>
DDR_A_CLK#0
DDR_A_CLK1
DDR_A_CLK1
DDR_A_CLK#1
138 CK0#(C)
CK1(T)
DQ1
DQ2
20 DDR_A_D1
DDR_A_D7
REVERSE
140 21 111 141
1 16x 1uF 0402 <7> DDR_A_CLK#1 CK1#(C) DQ3 DDR_A_D0 VDD1 VDD11

@ CD17
4 112 142
Placeholder
1

1
DDR_A_CKE0 DQ4 DDR_A_D4 VDD2 VDD12
CD1

CD2

CD3

CD4

CD5

CD6

CD7

CD8
+ 109 3 117 147
<7> DDR_A_CKE0 DDR_A_CKE1 CKE0 DQ5 DDR_A_D6 VDD3 VDD13
110 16 118 148
1x 330uF 7343 <7> DDR_A_CKE1 CKE1 DQ6 17 DDR_A_D3 123 VDD4 VDD14 153
2

2
DDR_A_CS#0 DQ7 DDR_A_DQS0 VDD5 VDD15
2 VPP: <7> DDR_A_CS#0 DDR_A_CS#1
149
S0# DQS0(T)
13
DDR_A_DQS#0
124
VDD6 VDD16
154
157 11 129 159
DIMM pin side, 1 per DIMM <7> DDR_A_CS#1
PAD~D @ T50 1 162 S1# DQS0#(C) 130 VDD7 VDD17 160
S2#/C0 DDR_A_D8 VDD8 VDD18
2x 10uF 0603 PAD~D @ T51 1 165
S3#/C1 DQ8
28
29 DDR_A_D13
135
136 VDD9 VDD19
163

2x 1uF 0402 <7> DDR_A_ODT0

DDR_A_ODT0 155 DQ9 41 DDR_A_D15 VDD10
DDR_A_ODT1 161 ODT0 DQ10 42 DDR_A_D11 +DDR_VREF_A_CA +3.3V_RUN_DIMM1 255 258
<7> DDR_A_ODT1 ODT1 DQ11 DDR_A_D12 VDDSPD VTT +0.6V_DDR_VTT
24
+1.2V_MEM +2.5V_MEM DDR_A_BG0 115 DQ12 25 DDR_A_D10 +DDR_VREF_A_CA 164 257
<7> DDR_A_BG0 DDR_A_BG1 BG0 DQ13 DDR_A_D9 VREFCA VPP1 +2.5V_MEM
113 38 259
<7> DDR_A_BG1 DDR_A_BA0 BG1 DQ14 DDR_A_D14 VPP2
150 37
<7> DDR_A_BA0 DDR_A_BA1 BA0 DQ15 DDR_A_DQS1
145 34 1 99
<7> DDR_A_BA1 BA1 DQS1(T) DDR_A_DQS#1 VSS1 VSS48
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

10U_0603_10V6M

10U_0603_10V6M
32 2 102
DDR_A_MA0 144 DQS1#(C) 5 VSS2 VSS49 103
1 1 1 1 1 1 1 1 1 1 1 1 DDR_A_MA1 A0 DDR_A_D32 VSS3 VSS50
133 50 6 106
DDR_A_MA2 A1 DQ16 DDR_A_D36 VSS4 VSS51
CD9

CD10

CD11

CD12

CD13

CD14

CD15

CD16

CD18

CD19

CD20

CD21
132 49 9 107
DDR_A_MA3 131 A2 DQ17 62 DDR_A_D34 10 VSS5 VSS52 167
2 2 2 2 2 2 2 2 2 2 2 2 DDR_A_MA4 128 A3 DQ18 63 DDR_A_D35 14 VSS6 VSS53 168
DDR_A_MA5 126 A4 DQ19 46 DDR_A_D37 15 VSS7 VSS54 171
DDR_A_MA6 127 A5 DQ20 45 DDR_A_D33 18 VSS8 VSS55 172
DDR_A_MA7 122 A6 DQ21 58 DDR_A_D39 19 VSS9 VSS56 175
DDR_A_MA8 125 A7 DQ22 59 DDR_A_D38 22 VSS10 VSS57 176
0801 Confirmed with 0801 Confirmed with DDR_A_MA9 121 A8 DQ23 55 DDR_A_DQS4 23 VSS11 VSS58 180
Intel 1U can change to 0201 Intel 1U can change to 0201 DDR_A_MA10 146 A9 DQS2(T) 53 DDR_A_DQS#4 26 VSS12 VSS59 181
DDR_A_MA11 120 A10_AP DQS2#(C) 27 VSS13 VSS60 184
DDR_A_MA12 119 A11 70 DDR_A_D41 30 VSS14 VSS61 185
DDR_A_MA13 158 A12 DQ24 71 DDR_A_D45 31 VSS15 VSS62 188
DDR_A_MA14 151 A13 DQ25 83 DDR_A_D46 35 VSS16 VSS63 189
C DDR_A_MA15 A14_WE# DQ26 DDR_A_D43 VSS17 VSS64 C
156 84 36 192
WHL_U PDG rev0.8 P.92 DDR_A_MA16 152 A15_CAS# DQ27 66 DDR_A_D40 39 VSS18 VSS65 193
A16_RAS# DQ28 VSS19 VSS66
VTT: DDR_A_ACT# DQ29
67 DDR_A_D44
DDR_A_D42
40
VSS20 VSS67
196
114 79 43 197
Place on VTT plane close to SODIMM <7> DDR_A_ACT# ACT# DQ30 80 DDR_A_D47 44 VSS21 VSS68 201
DDR_A_PARITY DQ31 DDR_A_DQS5 VSS22 VSS69
2x 10uF 0603(1 cap stuffed, 1 placeholder) <7> DDR_A_PARITY DDR_A_ALERT#
143
116 PARITY DQS3(T)
76
74 DDR_A_DQS#5
47
48 VSS23 VSS70
202
205
Layout Note: 4x 1uF 0402 <7> DDR_A_ALERT# JDIMM1_EVENT# 134 ALERT# DQS3#(C) 51 VSS24 VSS71 206
DDR_DRAMRST#_R EVENT# DDR_A_D29 VSS25 VSS72
Place near VDDSPD: 108
RESET# DQ32
174
173 DDR_A_D25
52
56 VSS26 VSS73
209
210
1
JDIMM1.258 Place close to DIMM DQ33 187 DDR_A_D30 57 VSS27 VSS74 213
@ CD29 254 DQ34 186 DDR_A_D26 60 VSS28 VSS75 214
2x 0.1uF 0402 0.1U_0402_25V6
<8,24,79> DDR_XDP_W AN_SMBDAT
253 SDA DQ35 170 DDR_A_D28 61 VSS29 VSS76 217
<8,24,79> DDR_XDP_W AN_SMBCLK SCL DQ36 VSS30 VSS77
2x 2.2uF 0402 2
DIMM1_SA2 DQ37
169 DDR_A_D24
DDR_A_D27
64
VSS31 VSS78
218
166 183 65 222
DIMM1_SA1 260 SA2 DQ38 182 DDR_A_D31 68 VSS32 VSS79 223
DIMM1_SA0 SA1 DQ39 DDR_A_DQS3 VSS33 VSS80
Refence WHL RVP rev0.7 +3.3V_RUN
256
SA0 DQS4(T)
179
DDR_A_DQS#3
69
VSS34 VSS81
226
177 72 227
DQS4#(C) 73 VSS35 VSS82 230
+0.6V_DDR_VTT 92 195 DDR_A_D23 77 VSS36 VSS83 231
CB0_NC DQ40 VSS37 VSS84
1

91 194 DDR_A_D16 78 234

@ RD10 101 CB1_NC DQ41 207 DDR_A_D22 81 VSS38 VSS85 235
0_0603_5% 105 CB2_NC DQ42 208 DDR_A_D20 82 VSS39 VSS86 238
88 CB3_NC DQ43 191 DDR_A_D18 85 VSS40 VSS87 239
CB4_NC DQ44 DDR_A_D19 VSS41 VSS88
10U_0603_10V6M

10U_0603_10V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

87 190 86 243
2

+3.3V_RUN_DIMM1 100 CB5_NC DQ45 203 DDR_A_D17 89 VSS42 VSS89 244

1 1 1 1 CB6_NC DQ46 VSS43 VSS90
1

DDR_A_D21
@ CD63

104 204 90 247

CB7_NC DQ47 DDR_A_DQS2 VSS44 VSS91
CD22

CD23

CD24

CD69

CD70

2.2U_0402_6.3V6M

0.1U_0201_10V6K

1 1 97 200 93 248
95 DQS8(T) DQS5(T) 198 DDR_A_DQS#2 94 VSS45 VSS92 251
2

2 2 2 2 +1.2V_MEM DQS8#(C) DQS5#(C) VSS46 VSS93

CD27

CD28

98 252
216 DDR_A_D52 VSS47 VSS94
2 2 12 DQ48 215 DDR_A_D49 262 261
33 DM0#/DBI0# DQ49 228 DDR_A_D55 264 GND1 GND2 263
0801 Confirmed with 54 DM1#/DBI1# DQ50 229 DDR_A_D51 NPTH2 NPTH1
Intel 1U can change to 0201 75 DM2#/DBI2# DQ51 211 DDR_A_D48 LOTES_ADDR0206-P001A
178 DM3#/DBI3# DQ52 212 DDR_A_D53
199 DM4#/DBI4# DQ53 224 DDR_A_D54
220 DM5#/DBI5# DQ54 225 DDR_A_D50
241 DM6#/DBI6# DQ55 221 DDR_A_DQS6
96 DM7#/DBI7# DQS6(T) 219 DDR_A_DQS#6
DM8#/DBI8# DQS6#(C)
B B

237 DDR_A_D57
DQ56 236 DDR_A_D60
DQ57 249 DDR_A_D62
DQ58 250 DDR_A_D59 JDIMM1_EVENT# 1 2
DIMM Select +3.3V_RUN +3.3V_RUN +3.3V_RUN

+DDR_VREF_A_CA
DQ59
DQ60
DQ61
232
233
245
DDR_A_D61
DDR_A_D56
DDR_A_D63
@ RD14 1K_0402_5%
H_THERMTRIP# <14,24,59>

DQ62
1

246 DDR_A_D58
@ RD4 @ RD6 @ RD8 DQ63 242 DDR_A_DQS7
0_0201_5% 0_0201_5% 0_0201_5% DQS7(T) 240 DDR_A_DQS#7
DQS7#(C)
0.1U_0201_6.3V6K

2.2U_0402_6.3V6M
2

DIMM1_SA0 1 1
LOTES_ADDR0206-P001A +1.2V_MEM
DIMM1_SA1
CD25

CD26

DIMM1_SA2
SA0 SA1 SA2

1
1K_0402_1%
2 2
1

* DIMM1 0 0 0

RD15
@ RD5 @ RD7 @ RD9
DIMM2 1 0 0 0_0201_5% 0_0201_5% 0_0201_5%
+DDR_VREF_A_CA +DDR_VREF_CA

2
DIMM3 0 1 0
2

1 2
DIMM4 1 1 0 RD17 2_0402_1%
+1.2V_MEM

0.022U_0402_16V7K
+1.2V_MEM

1K_0402_1%
1

1
RD16

CD31
UD1
1
470_0402_1%

1 5 1 2
NC VCC @ CD32 0.1U_0201_10V6K

2
RD11

2
<7> DDR_VTT_CTRL

2
A 4
Y 0.6V_DDR_VTT_ON <86>

1
24.9_0402_1%
3
2

GND

RD18
1 2
+3.3V_RUN
74AUP1G07SE-7_TSSOP5 RD19 100K_0402_5%
@ RD12 1 2 0_0201_5% DDR_DRAMRST#
<24> DDR_DRAMRST#_R DDR_DRAMRST# <7>

2
A
6/8 Change to SA00007WE00 DII A

DELL CONFIDENTIAL/PROPRIETARY

https://Dr-Bios.com
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT DDR4 DIMMA
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 23 of 109
5 4 3 2 1
 5 4 3 2 1

For DDR4
<7> DDR_B_DQS#[0..7]

<7> DDR_B_D[0..63]

<7> DDR_B_DQS[0..7]

<7> DDR_B_MA[0..16]

Link LOTES_ADDR0206-P001A02 done 0410

CONN@
JDIMM2A
Layout Note: DDR_B_CLK0 137 REVERSE 8 DDR_B_D1
<7> DDR_B_CLK0 DDR_B_CLK#0 CK0(T) DQ0 DDR_B_D4
Place near JDIMM2 <7> DDR_B_CLK#0 DDR_B_CLK1
139
138 CK0#(C) DQ1
7
20 DDR_B_D6
+1.2V_MEM CONN@
JDIMM2B
+1.2V_MEM

<7> DDR_B_CLK1 DDR_B_CLK#1 CK1(T) DQ2 DDR_B_D7

140 21 REVERSE
D <7> DDR_B_CLK#1 CK1#(C) DQ3 DDR_B_D0 D
4 111 141
DDR_B_CKE0 109 DQ4 3 DDR_B_D5 112 VDD1 VDD11 142
Merion Limit height <7> DDR_B_CKE0 DDR_B_CKE1 110 CKE0 DQ5 16 DDR_B_D3 117 VDD2 VDD12 147
<7> DDR_B_CKE1 CKE1 DQ6 DDR_B_D2 VDD3 VDD13
CD49 change to SGA0000AM00 H=1.0mm(MAX) DDR_B_CS#0 149 DQ7
17
13 DDR_B_DQS0
118
123 VDD4 VDD14
148
153
+1.2V_MEM
Refence WHL RVP rev0.7
WHL_U PDG rev0.8 P.92 <7> DDR_B_CS#0 DDR_B_CS#1 157 S0# DQS0(T) 11 DDR_B_DQS#0 124 VDD5 VDD15 154
<7> DDR_B_CS#1 S1# DQS0#(C) VDD6 VDD16
VDDQ: PAD~D @ T54 1
1
162
165 S2#/C0 28 DDR_B_D13
129
130 VDD7 VDD17
159
160
PAD~D @ T55
4 near each side of the DIMM S3#/C1 DQ8 29 DDR_B_D11 135 VDD8 VDD18 163
DDR_B_ODT0 DQ9 DDR_B_D14 VDD9 VDD19
10U_0603_10V6M

10U_0603_10V6M

10U_0603_10V6M

10U_0603_10V6M

10U_0603_10V6M

10U_0603_10V6M

10U_0603_10V6M

10U_0603_10V6M

220U_D7_2VM_R4.5M
connector close to VDD pins <7> DDR_B_ODT0 DDR_B_ODT1
155
161 ODT0 DQ10
41
42 DDR_B_D10
136
VDD10
1 16x 10uF 0603(2 DIMMS TOTAL) <7> DDR_B_ODT1
DDR_B_BG0
ODT1 DQ11
DQ12
24 DDR_B_D9
DDR_B_D8
+DDR_VREF_B_CA +3.3V_RUN_DIMM2 255
VDDSPD VTT
258
+0.6V_DDR_VTT

@ CD49
115 25
16x 1uF 0402(2 DIMMS TOTAL) <7> DDR_B_BG0 BG0 DQ13
1

1
DDR_B_BG1 DDR_B_D12 +DDR_VREF_B_CA
CD33

CD34

CD35

CD36

CD37

CD38

CD39

CD40
+ 113 38 164 257
<7> DDR_B_BG1 +2.5V_MEM
Placeholder <7> DDR_B_BA0
DDR_B_BA0
DDR_B_BA1
150 BG1
BA0
DQ14
DQ15
37 DDR_B_D15
DDR_B_DQS1
VREFCA VPP1
VPP2
259
145 34
1x 330uF 7343 <7> DDR_B_BA1
2

2
2 BA1 DQS1(T) 32 DDR_B_DQS#1 1 99
DDR_B_MA0 DQS1#(C) VSS1 VSS48
VPP: DDR_B_MA1
144
A0 DDR_B_D32
2
VSS2 VSS49
102
133 50 5 103
DIMM pin side, 1 per DIMM DDR_B_MA2 132 A1 DQ16 49 DDR_B_D37 6 VSS3 VSS50 106
DDR_B_MA3 A2 DQ17 DDR_B_D38 VSS4 VSS51
2x 10uF 0603 DDR_B_MA4
131
128 A3 DQ18
62
63 DDR_B_D35
9
10 VSS5 VSS52
107
167
2x 1uF 0402 DDR_B_MA5 126 A4 DQ19 46 DDR_B_D36 14 VSS6 VSS53 168
DDR_B_MA6 127 A5 DQ20 45 DDR_B_D33 15 VSS7 VSS54 171
DDR_B_MA7 122 A6 DQ21 58 DDR_B_D34 18 VSS8 VSS55 172
DDR_B_MA8 125 A7 DQ22 59 DDR_B_D39 19 VSS9 VSS56 175
+1.2V_MEM +2.5V_MEM DDR_B_MA9 121 A8 DQ23 55 DDR_B_DQS4 22 VSS10 VSS57 176
DDR_B_MA10 146 A9 DQS2(T) 53 DDR_B_DQS#4 23 VSS11 VSS58 180
DDR_B_MA11 120 A10_AP DQS2#(C) 26 VSS12 VSS59 181
DDR_B_MA12 119 A11 70 DDR_B_D41 27 VSS13 VSS60 184
DDR_B_MA13 A12 DQ24 DDR_B_D47 VSS14 VSS61
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

10U_0603_10V6M

10U_0603_10V6M
158 71 30 185
DDR_B_MA14 151 A13 DQ25 83 DDR_B_D43 31 VSS15 VSS62 188
1 1 1 1 1 1 1 1 1 1 1 1 DDR_B_MA15 A14_WE# DQ26 DDR_B_D42 VSS16 VSS63
156 84 35 189
DDR_B_MA16 A15_CAS# DQ27 DDR_B_D45 VSS17 VSS64
CD41

CD42

CD43

CD44

CD45

CD46

CD47

CD48

CD50

CD51

CD52

CD53
152 66 36 192
A16_RAS# DQ28 67 DDR_B_D46 39 VSS18 VSS65 193
2 2 2 2 2 2 2 2 2 2 2 2 DDR_B_ACT# 114 DQ29 79 DDR_B_D40 40 VSS19 VSS66 196
<7> DDR_B_ACT# ACT# DQ30 DDR_B_D44 VSS20 VSS67
80 43 197
DDR_B_PARITY 143 DQ31 76 DDR_B_DQS5 44 VSS21 VSS68 201
<7> DDR_B_PARITY DDR_B_ALERT# PARITY DQS3(T) DDR_B_DQS#5 VSS22 VSS69
116 74 47 202
<7> DDR_B_ALERT# JDIMM2_EVENT# ALERT# DQS3#(C) VSS23 VSS70
134 48 205
0801 Confirmed with 0801 Confirmed with DDR_DRAMRST#_R 108 EVENT# 174 DDR_B_D17 51 VSS24 VSS71 206
Intel 1U can change to 0201 Intel 1U can change to 0201 <23> DDR_DRAMRST#_R RESET# DQ32 DDR_B_D20 VSS25 VSS72
173 52 209
C DQ33 DDR_B_D22 VSS26 VSS73 C
187 56 210
254 DQ34 186 DDR_B_D19 57 VSS27 VSS74 213
1 <8,23,79> DDR_XDP_W AN_SMBDAT SDA DQ35 DDR_B_D16 VSS28 VSS75
253 170 60 214
<8,23,79> DDR_XDP_W AN_SMBCLK SCL DQ36 DDR_B_D21 VSS29 VSS76
CD61 @ 169 61 217
DIMM2_SA2 166 DQ37 183 DDR_B_D23 64 VSS30 VSS77 218
0.1U_0402_25V6
2 DIMM2_SA1 260 SA2 DQ38 182 DDR_B_D18 65 VSS31 VSS78 222
DIMM2_SA0 256 SA1 DQ39 179 DDR_B_DQS2 68 VSS32 VSS79 223
SA0 DQS4(T) 177 DDR_B_DQS#2 69 VSS33 VSS80 226
DQS4#(C) 72 VSS34 VSS81 227
WHL_U PDG rev0.8 P.92 92 195 DDR_B_D25 73 VSS35 VSS82 230
CB0_NC DQ40 DDR_B_D29 VSS36 VSS83
VTT: DDR_DRAMRST#_R
91
101 CB1_NC DQ41
194
207 DDR_B_D27
77
78 VSS37 VSS84
231
234
Place on VTT plane close to SODIMM 105 CB2_NC DQ42 208 DDR_B_D30 81 VSS38 VSS85 235
CB3_NC DQ43 DDR_B_D24 VSS39 VSS86
2x 10uF 0603(1 cap stuffed, 1 placeholder) 88
87 CB4_NC DQ44
191
190 DDR_B_D28
82
85 VSS40 VSS87
238
239
4x 1uF 0402 CB5_NC DQ45 VSS41 VSS88

3
100 203 DDR_B_D26 86 243
CB6_NC DQ46 DDR_B_D31 VSS42 VSS89
ESD@ DD1
CEST523NC5VB_SOT-523-3
104 204 89 244
VDDSPD: 97 CB7_NC DQ47 200 DDR_B_DQS3 90 VSS43 VSS90 247
Layout Note: Place close to DIMM 95 DQS8(T) DQS5(T) 198 DDR_B_DQS#3 93 VSS44 VSS91 248
DQS8#(C) DQS5#(C) VSS45 VSS92
Place near 2x 0.1uF 0402
+1.2V_MEM
216 DDR_B_D48
94
98 VSS46 VSS93
251
252
JDIMM2.258 2x 2.2uF 0402 1 12 DQ48 215 DDR_B_D49 VSS47 VSS94
33 DM0#/DBI0# DQ49 228 DDR_B_D51 262 261
54 DM1#/DBI1# DQ50 229 DDR_B_D54 264 GND1 GND2 263
75 DM2#/DBI2# DQ51 211 DDR_B_D52 NPTH2 NPTH1
1206 change
178 DM3#/DBI3# DQ52 212 DDR_B_D53 LOTES_ADDR0206-P001A
DD1 close to CD61 DM4#/DBI4# DQ53 DDR_B_D50
+3.3V_RUN 0821 ESD team request to add DD1. 199 224
DM5#/DBI5# DQ54 DDR_B_D55
+0.6V_DDR_VTT Refence WHL RVP rev0.7 220
DM6#/DBI6# DQ55
225
DDR_B_DQS6
241 221
1

96 DM7#/DBI7# DQS6(T) 219 DDR_B_DQS#6

@ RD26 DM8#/DBI8# DQS6#(C)
0_0603_5%
10U_0603_10V6M

10U_0603_10V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

237 DDR_B_D57
1 1 1 1
2
1

+3.3V_RUN_DIMM2 DQ56 DDR_B_D60

@ CD66

236
DQ57 DDR_B_D59
CD54

CD55

CD56

CD71

CD72

249
DQ58 250 DDR_B_D63
2

2 2 2 2 DQ59 DDR_B_D61
2.2U_0402_6.3V6M

0.1U_0201_10V6K

1 232
DQ60
1

233 DDR_B_D56
DQ61 DDR_B_D58
CD59

CD60

245
DQ62 246 DDR_B_D62
2

2 DQ63 242 DDR_B_DQS7

B B
DQS7(T) 240 DDR_B_DQS#7
0801 Confirmed with DQS7#(C)
Intel 1U can change to 0201

LOTES_ADDR0206-P001A

DIMM Select +3.3V_RUN +3.3V_RUN +3.3V_RUN

1

+DDR_VREF_B_CA +1.2V_MEM
@ RD20 @ RD22 @ RD24

1
1K_0402_1%
0_0201_5% 0_0201_5% 0_0201_5%

RD28
2

0.1U_0201_6.3V6K

2.2U_0402_6.3V6M

DIMM2_SA0 +DDR_VREF_B_CA +DDR_VREF_B_DQ

1 1

2
DIMM2_SA1
DIMM2_SA2 JDIMM2_EVENT#
CD57

CD58

1 2
SA0 SA1 SA2 @ RD27 1K_0402_5%
H_THERMTRIP# <14,23,59>
1 2
1

2 2 RD30 2_0402_1%
DIMM1 0 0 0

0.022U_0402_16V7K
@ RD21 @ RD23 @ RD25

1K_0402_1%
DIMM2 1 0 0 0_0201_5% 0_0201_5% 0_0201_5%

1
RD29

CD62
* DIMM3 0 1 0
2

DIMM4 1 1 0

2
2

24.9_0402_1%

1
RD31
2
A A

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 5 4 3 2 1

CONN@ Due to SB12/14 Mic. receive path is different between Touch and
JEDP1 +TS_PWR
Non-Touch Panel, so add TOUCH_SCREEN_DET# pin for different verb
41
42 GND_1 1
1
2 table
Need change SP01001SS10
43 GND_2 2 3
GND_3 3 PRIVACY_ENABLE <58>
44 4
TOUCH SCREEN & IR CAMERA connector
For 2 LANE EDP & 5V_TSP
45 GND_4 4 5
GND_5 5 2.7MM_CAM_DET# <12>
46 6
47 GND_6 6 7
GND_7 7 DMIC0 <56>
48 8 CONN@
49 GND_8 8 9 JIRTS1
GND_9 9 DMIC_CLK0 <56> +3.3V_RUN
50 10 +3.3V_RUN_F
1
GND_10 10 1 PCH_PLTRST#_AND <11,42,52,68,70>
51 11 2
GND_11 11 USB20_N6_R +3.3V_CAM 2 TS_I2C_SDA TS_INT# <9> Touch pull up at the panel side

100P_0402_50V8J
RF@

82P_0402_50V8J
RF@
52 12 3
GND_12 12 USB20_P6_R 3 TS_I2C_SCL TS_I2C_SDA <9>
53
GND_13 13
13
4
4
TS_I2C_SCL <9> For Merion 3mm IR CAM ALS & P-Sensor

1
54 14 1 2 5 TS_I2C_SDA 2 1
55 GND_14 14 15 @RF@ RZ1470 0_0201_5%
CAM_MIC_CBL_DET# <12> 5 6 IR_CAM_DET# <9>
@ RV98 2.2K_0201_5%
RF Request
GND_15 15 6 TS_I2C_SCL

CA5

CA6
56 16 Pin15: LOOP_BACK 7 2 1

2
57 GND_16 16 17 7 8 @ RV99 2.2K_0201_5% +3.3V_RUN
GND_17 17 +BL_PWR_SRC 8 3MM_CAM_DET# <9> TS_INT# +13.5VB
58 18 9 2 1
D GND_18 18 9 ISH_I2C1_ALS_SDA TOUCH_SCREEN_PD#_R <14> ISH_I2C1_ALS_SDA D
59 19 10 ISH_I2C1_ALS_SDA <9>
@ RV311 100K_0201_5% 2 1
60 GND_19 19 20 10 11 ISH_I2C1_ALS_SCL TS_INT# 2 1 RV740 2.2K_0201_5%
GND_20 20 BIA_PWM 11 ISH_ALS_INT# ISH_I2C1_ALS_SCL <9> ISH_I2C1_ALS_SCL
61 21 EMI@ LV1 1 2 12 @ RV319 1K_0201_5% 2 1
GND_21 21 DISP_ON 12 P_SENSOR_PW R_SAVE# ISH_ALS_INT# <9>
62 22 BLM15PX221SN1D_2P RF Request 13 RV741 2.2K_0201_5%
GND_22 22 13 ISH_P_SENSOR_INT# P_SENSOR_PWR_SAVE# <9> ISH_ALS_INT#
63 23 14 2 1
GND_23 23 14 ISH_P_SENSOR_INT# <12>

100P_0201_50V8J
RF@ CZ3
64 24 15 +3.3V_ALS_PWR 1 RV742 2.2K_0201_5%
65 GND_24 24 25 15 16
66 GND_25 25 26 +LCDVDD 16 17 FZ2 +3.3V_RUN
67 GND_26 26 27 EDP_HPD <6> 17 18 +13.5VB_IR 2 1
RF Request
GND_27 27 EDP_HPD 18 +13.5VB 2 P_SENSOR_PW R_SAVE#
68 28 1 2 2 1
69 GND_28 28 29 @ RV7 100K_0402_5% 19 1A_65V_T0603FF1000TM TS_I2C_SDA 1 2 @ RV743 10K_0201_5%
GND_29 29 LCD_TST <58> G1 ISH_P_SENSOR_INT#
70 30 20 @RF@ CV54 33P_0201_50V8J 2 1
GND_30 30 +LCDVDD G2
71 31 Reserve for EA 1031 change @ RV744 10K_0201_5%
72 GND_31 31 32 TOUCH_SCREEN_DET# ACES_50208-0180N-P01 TS_I2C_SCL 1 2
GND_32 32 EDP_AUXN_C TOUCH_SCREEN_DET# <14>
73 33 CV1 2 1 0.1U_0402_25V6 @RF@ CV55 33P_0201_50V8J
GND_33 33 EDP_AUXP_C EDP_AUXN <6> +3.3V_ALS_PWR +3.3V_RUN
74 34 CV2 2 1 0.1U_0402_25V6
GND_34 34 35 EDP_TXP0_C CV3 2 1 0.1U_0402_25V6
EDP_AUXP
EDP_TXP0
<6>
<6>
Link ACES_50208-0180N-P01 done 0323
35 36 EDP_TXN0_C CV4 2 1 0.1U_0402_25V6 1 2
36 37 EDP_TXP1_C CV5 2 1 0.1U_0402_25V6
EDP_TXN0 <6> 0824 change footprint to ACES_50208-0180N-P01_18P-T-S RZ1476 0_0603_5%
37 EDP_TXN1_C EDP_TXP1 <6>
38 CV6 2 1 0.1U_0402_25V6
38 EDP_TXN1 <6>
39 1031 change,RZ1476 reserve for FUSE location
39 40
40 LCD_CBL_DET# <9>
I-PEX_20879-040E-01

+BL_PWR_SRC

Relink I-PEX_20879-040E-01 done 0827 LCDVDD POWER

Backlight POWER

1A_65V_T0603FF1000TM
1031 change

FV1
RF Request place as close as JEDP1 RF Request +3.3V_ALW
+LCDVDD 1213 change +3.3V_CAM +BL_PW R_SRC 1213 change +TS_PW R @ CV17
Add CZ313 for RF request Add CZ314 for RF request +LCDVDD +EDP_VDD 1 2

1
1217 1217 JUMP@ UV24
Change CZ313 to CV757 Change CZ314 to CV758 +13.5VB QV1 PJP12 0.01UF_0402_25V7K
1 2 1 6
6+BL_PW R_SRC_P OUT IN DV3

D
4 5 2 5 UV24_SET 1 2 3

S
C GND SET P2 LCD_VCC_TEST_EN <58> C
2 PAD-OPEN1x1m RV102 20K_0201_5%
EN_LCDPWR
12P_0201_50V8J
RF@ CV20

82P_0201_50V8J
RF@ CV21

100P_0201_50V8J
RF@ CV751

100P_0201_50V8J
RF@ CV752

27P_0201_25V8
RF@CV757

12P_0402_50V8J
RF@ CV22

82P_0402_50V8J
RF@ CV23

120P_0402_50V8J
RF@ CV750

12P_0402_50V8J
RF@ CV24

82P_0402_50V8J
RF@ CV25

120P_0402_50V8J
RF@ CV753

27P_0402_50V8J
RF@ CV758

12P_0402_50V8J
RF@ CV18

82P_0402_50V8J
RF@ CV19

120P_0402_50V8J
RF@ CV754
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 @ RV101 3 4 1

1000P_0402_50V7K
FLAG EN(/EN) N

0.1U_0402_25V6
1 2

G
270K_0402_5%
2

1
100K_0402_5%
AO6405_TSOP6 1 0.01_1206_1% 2
ENVDD_PCH <6>

3
CV13
2
P1

RV4
1 G527ATP1U_TSOT23-6
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

CV15

RV3
@ CV16 BAT54CTB_SOT-523

1
2
10U_0402_10V6M Change to SA00006Y700(H=1mm) DV3 change to SCS00008B80

2
2
For Merion layout placement For Merion layout limit height
BL_PWR_SRC_ON

QV2
2N7002KTB_SOT523-3
place as close as JEDP1

0.01U_0402_50V7K
1
1 2 1 3

S
CV14
RV5 47K_0402_5%

G
2
+BL_PWR_SRC +LCDVDD +3.3V_CAM +TS_PW R +3.3V_RUN
<58> EN_INVPW R
0212 change
0.1U_0603_50V7K

0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K

QV2 change from SB00000NK00 QZ1 change to SB00000SS00

1 1 1 1
WebCAM For Merion layout limit height
1

to SB00000SI00
@

@ @ @ @
+3.3V_CAM +3.3V_RUN_F +3.3V_RUN
CV11

CV12

CZ202

CZ2

CA7

For parts shortage problem

2

2 2 2 2 QZ1
NTK3139PT1G_SOT723-3
FZ1
1 3 1 2

S
Close to JEDP1.17~19 Close to JEDP1.30~31 Close to JEDP1.11 Close to JEDP1.1 Close to JEDP1.10
0.5A_65V_T0603FF0500TM
Merion Limit height

G
2
DV13,DV14,DZ10,DZ21 change to H=0.9mm(MAX) 1031 change
1 2
+3.3V_RUN DMIC_CLK0 TS_I2C_SCL <11> 3.3V_CAM_EN#
@ RZ388 0_0201_5%

0.1U_0402_25V6K
1
TS_I2C_SDA
10K_0402_5%

DMIC0 @
2

CZ220
DV1
RV8

B B
2

3
EMI@

2
EDP_BIA_PWM
ESD@ DV13
CEST523NC5VB_SOT-523-3

ESD@ DZ10
CEST523NC5VB_SOT-523-3
3 LZ1
EDP_BIA_PWM <6> USB20_N6_R
1 2
BIA_PWM <10> USB20_N6 1 2
1
1

2 BIA_PWM_EC TOUCH_SCREEN_DET#
BIA_PWM_EC <58> USB20_P6_R
4 3
<10> USB20_P6 4 3
1
4.7K_0402_5%

1
BAT54CW _SOT323-3 If touch panel, GPIO Low-> Touch Mic. EQ ; DLM0NSN900HY2D_4P
RV1

1206 change 1206 change

others the GPIO is High -> Non-Touch Mic. EQ
2

+3.3V_RUN
10K_0402_5%
2
RV325

DV2
For Touchscreen +TS_PWR

0.5A_65V_T0603FF0500TM
3 USB20_P6_R ISH_I2C1_ALS_SCL
PANEL_BKLEN <6> 1031 change
1

3MM_CAM_DET#

1
DISP_ON 1 USB20_N6_R ISH_I2C1_ALS_SDA
2
PANEL_BKEN_EC <58>
2

+3.3V_RUN

FV2
QV8 change to SB00000SS00
4.7K_0402_5%

ESD@ DV14
CEST523NC5VB_SOT-523-3

ESD@ DZ21
CEST523NC5VB_SOT-523-3

For Merion layout limit height

1

+5V_RUN
10K_0402_5%

BAT54CW _SOT323-3
2
RV2

@ RV733 1 2 0_0603_5%
RV734

+5V_RUN

2
QV8

47K_0402_5%
2
NTK3139PT1G_SOT723-3
+3.3V_RUN

RV6
2

+TS_PW R_QV8 1 3+3.3V_5V_RUN_QV8

S
1

2.7MM_CAM_DET#
1206 change 1206 change

100K_0402_5%
@ RV732 1 2 0_0603_5% +3.3V_RUN

1
1

G
2
RV326
1 2
0212 change @ RV400 0_0201_5%
QV7 change from SB00000NK00

2
to SB00000SI00

2N7002KTB_SOT523-3
Merion13 Merion14

1
For parts shortage problem Touchscreen power Touchscreen power

0.1U_0402_25V6K
D

1
QV7
@ RV323 1 2 0_0201_5% 2 @
<58> 3.3V_TS_EN

CV635
A G A
@ RV324 1 2 0_0201_5% S
+3.3V +5V
<9> PCH_3.3V_TS_EN

2
3
Depop RV733,Pop RV732 Depop RV732,Pop RV733

DELL CONFIDENTIAL/PROPRIETARY

https://Dr-Bios.com
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT eDP CONN & Touch screen
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 38 of 109
5 4 3 2 1
 5 4 3 2 1

D D

Reserve
C C

B B

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
DP
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 39 of 109
5 4 3 2 1
 5 4 3 2 1

Based on EMI & EE test result

Change location LV31~LV38 to 5.6Ohm
RV26,RV29,RV32,RV35 to 130Ohm

EMI@ RV56 1 2 5.6_0402_5%

HDMI_L_TX_P2
HCM1012GH900BP_4P

2
1 2 HDMI_TX_P2 2 3 EMI@
<42> AR_DP1_P0 2 3
CV31 0.1U_0402_25V6 RV26
130_0402_5%
1 2 HDMI_TX_N2 1 4
<42> AR_DP1_N0 1 4
CV32 0.1U_0402_25V6

1
@EMI@ LV3 HDMI_L_TX_N2
D D
EMI@ RV57 1 2 5.6_0402_5%

EMI@ RV58 1 2 5.6_0402_5%

HDMI_L_TX_P1 +5V_RUN
HCM1012GH900BP_4P

2
1 2 HDMI_TX_P1 2 3 EMI@
<42> AR_DP1_P1 2 3
CV33 0.1U_0402_25V6 RV29

0.1U_0201_10V6K
130_0402_5%
1 2 HDMI_TX_N1 1 4
<42> AR_DP1_N1 1 4 1
CV34 0.1U_0402_25V6

1
HDMI_L_TX_N1

@
@EMI@ LV6

1
CV39
EMI@ RV59 1 2 5.6_0402_5% +VHDMI_VCC
2

IN

AP2330W-7_SC59-3
EMI@ RV60 1 2 5.6_0402_5%
HDMI_L_TX_P0
HCM1012GH900BP_4P

UV2

0.1U_0201_10V6K

10U_0603_10V6M
2
1 2 HDMI_TX_P0 2 3 EMI@
<42> AR_DP1_P2 2 3 1 1
CV35 0.1U_0402_25V6 RV32

GND

OUT
130_0402_5% @
HDMI_TX_N0

CV40

CV41
1 2 1 4
<42> AR_DP1_N2 1 4 2 2
CV36 0.1U_0402_25V6

3
@EMI@ LV9 HDMI_L_TX_N0
EMI@ RV61 1 2 5.6_0402_5%
HDMI connector
EMI@ RV62 1 2 5.6_0402_5%
HDMI_L_CLKP Link HMRBL-A41L0F done 0123
HCM1012GH900BP_4P JHDMI1 CONN@

2
2 1 HDMI_CLKP 2 3 EMI@ HDMI_HPD 19
<42> AR_DP1_P3 0.1U_0402_25V6 2 3 HP_DET
CV37 RV35 18
130_0402_5% 17 +5V
2 1 HDMI_CLKN 1 4 +3.3V_RUN HDMI_CTRL_DATA 16 DDC/CEC_GND
<42> AR_DP1_N3 0.1U_0402_25V6 1 4 HDMI_CTRL_CLK SDA
CV38 15

1
C
@EMI@ LV12 HDMI_L_CLKN 14 SCL C
2 1 HDMI_CEC 13 Reserved
EMI@ RV63 1 2 5.6_0402_5% 10K_0402_5% @ RV19 HDMI_L_CLKN 12 CEC 20
11 CK- GND4 21
HDMI_L_CLKP 10 CK_shield GND3 22
HDMI_L_TX_N0 9 CK+ GND2 23
8 D0- GND1
HDMI_L_TX_P0 7 D0_shield
HDMI_L_TX_N1 6 D0+
5 D1-
HDMI_L_TX_P1 4 D1_shield
HDMI_L_TX_N2 3 D1+
2 D2-
HDMI_L_TX_P2 1 D2_shield
D2+
ACON_HMRBL-A41L0F

+3.3V_RUN
1M_0402_5%

0212 change
2

QV5 change from SB00000NK00

RV20

to SB00000SI00
2

For parts shortage problem

G
1

3 1 HDMI_HPD 1 2
<42> AR_DP1_HPD RV21 20K_0402_5%
S

QV5
2N7002KTB_SOT523-3
B B
HDMI_TX_P2 RV10 1 2 470_0402_1% HDMI_OB
HDMI_TX_N2 RV11 1 2 470_0402_1%
HDMI_TX_P1 RV12 1 2 470_0402_1%
HDMI_TX_N1 RV13 1 2 470_0402_1%
HDMI_TX_P0 RV14 1 2 470_0402_1%
HDMI_TX_N0 RV15 1 2 470_0402_1%
HDMI_CLKP RV16 1 2 470_0402_1%
+3.3V_RUN HDMI_CLKN RV17 1 2 470_0402_1%

1
D QV4
RV18 1 2 10K_0402_5% 2 2N7002KTB_SOT523-3
+3.3V_RUN
G
QV3A +VHDMI_VCC S
2

L2N7002DW1T1G_SC88-6 0212 change

3
1 6 HDMI_CTRL_CLK 1 2 QV4 change from SB00000NK00
<42> AR_DP1_CTRL_CLK
RV22 2.2K_0402_5% to SB00000SI00
5

For parts shortage problem

4 3 HDMI_CTRL_DATA 1 2
<42> AR_DP1_CTRL_DATA
RV23 2.2K_0402_5%
QV3B
L2N7002DW1T1G_SC88-6

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
HDMI CONN
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 40 of 109
5 4 3 2 1
 5 4 3 2 1

D D

Reserve
C C

B B

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
CRT
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 41 of 109
5 4 3 2 1
 5 4 3 2 1

+3.3V_TBT_FLASH_R +3.3V_TBT_LC

+3.3V_TBT_FLASH_R +3.3V_TBT_FLASH_R
+3.3V_TBT_LC 1 2 +3.3V_ALW _PCH
@ RT9 0_0201_5%

10K_0201_5%

10K_0201_5%

10K_0201_5%

10K_0201_5%
3.3K_0201_5%

2.2K_0201_5%

2.2K_0201_5%

3.3K_0201_5%
1

1
CT1 TBT_CIO_PLUG_EVENT# RT391 1 2 10K_0402_5%
For backdrive issue

RT5

RT6

RT7

RT8
0.1U_0201_10V6K
2

RT1

RT2

RT3

RT4
1

2
UT2 TBT_JTAG_TDI
8 1 TBT_ROM_CS# TBT_JTAG_TMS
TBT_ROM_HOLD# 7 VCC CS# 2 TBT_ROM_DO TBT_JTAG_TCK
D TBT_ROM_CLK 6 HOLD#(IO3) DO(IO1) 3 TBT_ROM_W P# TBT_JTAG_TDO +3.3V_TBT D
TBT_ROM_DI 5 CLK WP#(IO2) 4
DI(IO0) GND Rework Debug Pin1 +3.3V_TBTA_LC, Pin6 GND
W 25Q80DVSSIG_SO8

AR_DP1_CTRL_DATA RT12 1 2 2.2K_0201_5%

AR_DP1_CTRL_CLK RT13 1 2 2.2K_0201_5%

UT1A
CT2 1 2 0.22U_0201_6.3V6M PCIE_PTX_C_DRX_P5 Y23 V23 PCIE_PRX_C_DTX_P5 CT6 1 2 0.22U_0201_6.3V6M
<10> PCIE_PTX_DRX_P5 PCIE_PTX_C_DRX_N5 PCIE_RX0_P PCIE_TX0_P PCIE_PRX_DTX_P5 <10>
CT3 1 2 0.22U_0201_6.3V6M Y22 V22 PCIE_PRX_C_DTX_N5 CT7 1 2 0.22U_0201_6.3V6M
<10> PCIE_PTX_DRX_N5 PCIE_RX0_N PCIE_TX0_N PCIE_PRX_DTX_N5 <10>
CT4 1 2 0.22U_0201_6.3V6M PCIE_PTX_C_DRX_P6 T23 P23 PCIE_PRX_C_DTX_P6 CT8 1 2 0.22U_0201_6.3V6M
<10> PCIE_PTX_DRX_P6 PCIE_PTX_C_DRX_N6 PCIE_RX1_P PCIE_TX1_P PCIE_PRX_DTX_P6 <10> SNK0_DDC_data/clk – connect to 2k PU only if
P22 PCIE_PRX_C_DTX_N6

PCIe GEN3
CT5 1 2 0.22U_0201_6.3V6M T22 CT9 1 2 0.22U_0201_6.3V6M SRC0 is connected and support HDMI (a.i HDMI
<10> PCIE_PTX_DRX_N6 PCIE_RX1_N PCIE_TX1_N PCIE_PRX_DTX_N6 <10>
PCIE_PTX_C_DRX_P7 or DP++ connector). Otherwise can be 100k PD.
CT123 1 2 0.22U_0201_6.3V6M M23 K23 PCIE_PRX_C_DTX_P7 CT127 1 2 0.22U_0201_6.3V6M
<10> PCIE_PTX_DRX_P7 PCIE_PTX_C_DRX_N7 PCIE_RX2_P PCIE_TX2_P K22 PCIE_PRX_C_DTX_N7 PCIE_PRX_DTX_P7 <10> SNK1_DDC_data – connect to 100k PD. If SRC0
CT124 1 2 0.22U_0201_6.3V6M M22 CT128 1 2 0.22U_0201_6.3V6M
<10> PCIE_PTX_DRX_N7 PCIE_RX2_N PCIE_TX2_N PCIE_PRX_DTX_N7 <10> support HDMI, connect as SNK0_CFG1 to GPU
CT125 1 2 0.22U_0201_6.3V6M PCIE_PTX_C_DRX_P8 H23 F23 PCIE_PRX_C_DTX_P8 CT129 1 2 0.22U_0201_6.3V6M and/or appropriate AUX/DDC demux control
<10> PCIE_PTX_DRX_P8
CT126 1 2 0.22U_0201_6.3V6M PCIE_PTX_C_DRX_N8 H22 PCIE_RX3_P PCIE_TX3_P F22 PCIE_PRX_C_DTX_N8 CT130 1 2 0.22U_0201_6.3V6M PCIE_PRX_DTX_P8 <10> SNK1_DDC_clk – connect to 100k PD.
<10> PCIE_PTX_DRX_N8 PCIE_RX3_N PCIE_TX3_N PCIE_PRX_DTX_N8 <10>
V19 L4 TBT_PERST#
<11> CLK_PCIE_P5 PCIE_REFCLK_100_IN_P PERST_N
T19
<11> CLK_PCIE_N5 PCIE_REFCLK_100_IN_N
AC5 N16 TBT_PCIE_RBIAS 1 2 +3.3V_TBT_SX
<11> CLKREQ_PCIE#5 PCIE_CLKREQ_N PCIE_RBIAS RT34 3.01K_0201_1%
CT10 1 2 0.1U_0201_10V6K CPU_DP1_P0_C AB7 R2 AR_DP1_P0 AR_DP1_P0 1 2 AR_DP1_N0 PCIE_W AKE#_AR RTD3@
<6> CPU_DP1_P0 AR_DP1_P0 <40> RT455 1 2 10K_0402_5%
CT11 1 2 0.1U_0201_10V6K CPU_DP1_N0_C AC7 DPSNK0_ML0_P DPSRC_ML0_P R1 AR_DP1_N0 @ CT201 1P_0201_50V8C
<6> CPU_DP1_N0 DPSNK0_ML0_N DPSRC_ML0_N AR_DP1_N0 <40> AR_DP1_P1 AR_DP1_N1 TBTA_I2C_INT
1 2 RT16 1 2 10K_0201_5%
CT12 1 2 0.1U_0201_10V6K CPU_DP1_P1_C AB9 N2 AR_DP1_P1 @ CT202 1P_0201_50V8C TBTB_I2C_INT RT17 1 2 10K_0201_5%
<6> CPU_DP1_P1 CPU_DP1_N1_C DPSNK0_ML1_P DPSRC_ML1_P AR_DP1_N1 AR_DP1_P1 <40> AR_DP1_P2 AR_DP1_N2
CT13 1 2 0.1U_0201_10V6K AC9 N1 1 2
<6> CPU_DP1_N1 DPSNK0_ML1_N DPSRC_ML1_N AR_DP1_N1 <40>

SOURCE PORT 0
@ CT203 1P_0201_50V8C TBT_I2C_SDA RT18 1 2 2.2K_0201_5%
CPU

SINK PORT 0
CT14 1 2 0.1U_0201_10V6K CPU_DP1_P2_C AB11 L2 AR_DP1_P2 AR_DP1_P3 1 2 AR_DP1_N3 TBT_I2C_SCL RT19 1 2 2.2K_0201_5%
<6> CPU_DP1_P2 CPU_DP1_N2_C DPSNK0_ML2_P DPSRC_ML2_P AR_DP1_N2 AR_DP1_P2 <40>
DDI1 <6> CPU_DP1_N2
CT15 1 2 0.1U_0201_10V6K AC11
DPSNK0_ML2_N DPSRC_ML2_N
L1
AR_DP1_N2 <40>
@ CT204 1P_0201_50V8C

CT16 1 2 0.1U_0201_10V6K CPU_DP1_P3_C AB13 J2 AR_DP1_P3 TDOCK_BATLOW # RT20 1 2 10K_0201_5%

<6> CPU_DP1_P3
CT17 1 2 0.1U_0201_10V6K CPU_DP1_N3_C AC13 DPSNK0_ML3_P DPSRC_ML3_P J1 AR_DP1_N3 AR_DP1_P3 <40> Close UT1
<6> CPU_DP1_N3 DPSNK0_ML3_N DPSRC_ML3_N AR_DP1_N3 <40> TBT_SRC_CFG1
CT18 1 2 0.1U_0201_10V6K CPU_DP1_AUXP_C Y11 W19
Intel Review request RT338 1 2 10K_0201_5%
<6> CPU_DP1_AUXP
C <6> CPU_DP1_AUXN CT19 1 2 0.1U_0201_10V6K CPU_DP1_AUXN_C W11 DPSNK0_AUX_P
DPSNK0_AUX_N
DPSRC_AUX_P
DPSRC_AUX_N
Y19 20180518 TBT_CIO_PLUG_EVENT#
RTD3_CIO_PW R_EN
@ RT371 1 2 10K_0201_5%
C
RTD3@ RT372 1 2 10K_0201_5%
AA2 G1 AR_DP1_HPD
<6> CPU_DP1_HPD DPSNK0_HPD DPSRC_HPD AR_DP1_HPD <40>
Y5 N6 TBT_DP_RBIAS 2 1
<6>
<6>
CPU_DP1_CTRL_CLK
CPU_DP1_CTRL_DATA
R4 DPSNK0_DDC_CLK DPSRC_RBIAS RT35 14K_0201_1% Intel review request for TBT RTD3 20170810 (KWmlk)
DPSNK0_DDC_DATA U1 TBT_I2C_SDA
CPU_DP2_P0_C GPIO_0 TBT_I2C_SCL TBT_I2C_SDA <44>
CT177 1 2 0.1U_0201_10V6K AB15 U2
<6> CPU_DP2_P0 CPU_DP2_N0_C DPSNK1_ML0_P GPIO_1 TBT_ROM_W P# TBT_I2C_SCL <44> TBTA_LSRX
CT176 1 2 0.1U_0201_10V6K AC15 V1 RT21 1 2 1M_0201_5%
<6> CPU_DP2_N0 DPSNK1_ML0_N

LC GPIO
GPIO_2 V2 TBT_TMU_CLK_OUT TBTA_LSTX RT22 1 2 1M_0201_5%
CT172 1 2 0.1U_0201_10V6K CPU_DP2_P1_C AB17 GPIO_3 W1 PCIE_W AKE#_AR TBTA_HPD RT23 1 2 100K_0201_5%
<6> CPU_DP2_P1 CPU_DP2_N1_C DPSNK1_ML1_P GPIO_4 TBT_CIO_PLUG_EVENT# CPU_DP1_HPD
CT171 1 2 0.1U_0201_10V6K AC17 W2 RT24 1 2 100K_0201_5%
<6> CPU_DP2_N1 DPSNK1_ML1_N GPIO_5 AR_DP1_CTRL_DATA TBT_CIO_PLUG_EVENT# <12> RTD3_CIO_PW R_ENNRTD3@RT25
Y1 1 2 100K_0402_5%
CPU_DP2_P2_C GPIO_6 AR_DP1_CTRL_CLK AR_DP1_CTRL_DATA <40> RTD3_USB_PW R_EN
CT174 1 2 0.1U_0201_10V6K AB19 Y2 RT26 1 2 100K_0201_5%
CPU <6> CPU_DP2_P2 DPSNK1_ML2_P AR_DP1_CTRL_CLK <40>

SINK PORT 1
CT168 1 2 0.1U_0201_10V6K CPU_DP2_N2_C AC19 GPIO_7 AA1 TBT_SRC_CFG1 TBT_FORCE_PW R RT27 1 2 10K_0201_5%
<6> CPU_DP2_N2 DPSNK1_ML2_N GPIO_8 TBTA_I2C_INT TBT_TMU_CLK_OUT
DDI2 CT173 1 2 0.1U_0201_10V6K CPU_DP2_P3_C AB21 POC_GPIO_0
J4
E2 TBTB_I2C_INT TBTA_I2C_INT <44> CPU_DP2_HPD
RT28
RT29
1
1
2
2
100K_0201_5%
100K_0201_5%
<6> CPU_DP2_P3 DPSNK1_ML3_P POC_GPIO_1

POC GPIO
CT170 1 2 0.1U_0201_10V6K CPU_DP2_N3_C AC21 D4 RTD3_USB_PW R_EN
<6> CPU_DP2_N3 DPSNK1_ML3_N POC_GPIO_2 TBT_FORCE_PW R
H4
CT169 1 2 0.1U_0201_10V6K CPU_DP2_AUXP_C Y12 POC_GPIO_3 F2 TDOCK_BATLOW # TBT_FORCE_PW R <6>
<6> CPU_DP2_AUXP CPU_DP2_AUXN_C DPSNK1_AUX_P POC_GPIO_4 SIO_SLP_S3# TBTB_LSTX
<6> CPU_DP2_AUXN CT175 1 2 0.1U_0201_10V6K W12 D2 RT31 1 2 100K_0201_5%
DPSNK1_AUX_N POC_GPIO_5 F1 RTD3_CIO_PW R_EN SIO_SLP_S3# <11,17,59,79> TBTB_LSRX RT32 1 2 100K_0201_5%
CPU_DP2_HPD POC_GPIO_6 RTD3_CIO_PW R_EN <6> TBTB_HPD
Y6 RT33 1 2 100K_0201_5%
<6> CPU_DP2_HPD DPSNK1_HPD E1 TEST_EN 1 2
DPSNK1_DDC_CLK Y8 TEST_EN RT36 100_0201_5%
DPSNK1_DDC_CLK
Misc

SNK0_CONFIG1 N4 AB5 TEST_PW RGD 1 2

DPSNK1_DDC_DATA TEST_PWR_GOOD RT37 100_0201_5%
2 1 DPSNK_RBIAS Y18 F4 TBT_RESET_N_EC
RT38 14K_0201_1% DPSNK_RBIAS RESET_N TBT_RESET_N_EC <44,58>
TBT_JTAG_TDI Y4 D22 XTAL_25_IN EMI@ RT394 1 2 0_0201_5% XTAL_25_IN_R
TBT_JTAG_TMS V4 TDI XTAL_25_IN D23 XTAL_25_OUT EMI@ RT40 1 2 0_0201_5% XTAL_25_OUT_R
TBT_JTAG_TCK T4 TMS XTAL_25_OUT
TBT_JTAG_TDO W4 TCK AB3 TBT_ROM_DI DPSNK1_DDC_CLK RT128 1 2 100K_0201_5%
TDO
MISC EE_DI TBT_ROM_DO
YT1
SNK0_CONFIG1
AC4 3 1 RT129 1 2 100K_0201_5%
1 2 TBTA_RBIAS H6 EE_DO AC3 TBT_ROM_CS# OUT IN
RT39 4.75K_0402_0.5% TBTA_RSENSE J6 RBIAS EE_CS_N AB4 TBT_ROM_CLK 4 2
RSENSE EE_CLK GND2 GND1

27P_0402_50V8J

27P_0402_50V8J
1

1
A15 B7 25MHZ 20PF FL2500123Z
<45> TBT_A_TRX_DTX_P1 PA_RX1_P PB_RX1_P

CT20

CT21
B15 A7
<45> TBT_A_TRX_DTX_N1 PA_RX1_N PB_RX1_N

2
A17 A9
<45> TBT_A_TTX_DRX_P1 B17 PA_TX1_P PB_TX1_P B9
<45> TBT_A_TTX_DRX_N1 PA_TX1_N PB_TX1_N
B B
A19 A11
<45> TBT_A_TTX_DRX_P0 B19 PA_TX0_P PB_TX0_P B11 RTD3@
<45> TBT_A_TTX_DRX_N0 PA_TX0_N PB_TX0_N TBT RTD3 Support +3.3V_ALW CT360
TBT PORTS

B21 A13 0.1U_0201_10V6K

<45> TBT_A_TRX_DTX_P0 PA_RX0_P PB_RX0_P
A21 B13 1 2
<45> TBT_A_TRX_DTX_N0 PA_RX0_N
Port A

PORT B

PB_RX0_N
Type C <44> TBTA_AUXP
Y15 Y16 1 2
W15 PA_DPSRC_AUX_P PB_DPSRC_AUX_P W16 NRTD3@ RT496 0_0201_5%
<44> TBTA_AUXN PA_DPSRC_AUX_N PB_DPSRC_AUX_N

5
TBTA_USB20_P E20 E19
<44> TBTA_USB20_P TBTA_USB20_N PA_USB2_D_P PB_USB2_D_P
D20 D19 1 2 1

P
<44> TBTA_USB20_N PA_USB2_D_N PB_USB2_D_N <11,38,52,68,70> PCH_PLTRST#_AND B TBT_PERST#_R TBT_PERST#
@ RT492 0_0201_5% 4 1 2
TBTA_LSTX A5 B4 TBTB_LSTX 1 2 2 O @ RT495 0_0201_5%
PA_LSTX PB_LSTX <6> PCH_TBT_PERST# A

G
<44> TBTA_LSTX TBTA_LSRX A4 B5 TBTB_LSRX @ RT493 0_0201_5%

100K_0201_5%
POC
POC

<44> TBTA_LSRX PA_LSRX PB_LSRX

2
TBTA_HPD M4 G2 TBTB_HPD

RTD3@ RT494
RTD3@ UT34

3
<44> TBTA_HPD PA_DPSRC_HPD PB_DPSRC_HPD MC74VHC1G08DFT2G_SC70-5
2 1 TBTA_USB2_RBIAS H19 F19 TBTB_USB2_RBIAS 2 1
PA_USB2_RBIAS PB_USB2_RBIAS
RT41 499_0201_1% RT42 499_0201_1%
AC23 D6

1
AB23 THERMDA MONDC_SVR
THERMDA A23
V18 ATEST_P B23
PCIE_ATEST ATEST_N
AC1 DEBUG E18
TEST_EDM USB2_ATEST
L15 W13 RTD3@
N15 FUSE_VQPS_64 MONDC_DPSNK_0 +3.3V_ALW CT237
FUSE_VQPS_128 W18 0.1U_0201_10V6K
C23 MONDC_DPSNK_1 TBT_RTD3_W AKE# 1 2 RTD3@ 1 2
C22 MONDC_CIO_0 AB2 <6> TBT_RTD3_W AKE# @ RT456 0_0201_5% UT32
MONDC_CIO_1 MONDC_DPSRC PCH_PCIE_W AKE# 1 2 1 5
ALPINE-RIDGE_BGA337 <11,58,59> PCH_PCIE_W AKE# @RTD3@ RT445 0_0201_5% NO V+
PCIE_W AKE# 1 2 3 4 PCIE_W AKE#_AR_R 1 2 PCIE_W AKE#_AR
<52,59,68> PCIE_W AKE# @ RT448 0_0201_5% NC COM @ RT441 0_0201_5%
6 2
<58> RTD3_SELECT IN GND

2
@RTD3@

2
RTD3@ TS5A3159ADCKR_SC70-6 RT440
RT447 1M_0201_5%
10K_0201_5%
IN NC NO

1
1
A A

L COM X
H X COM

DELL CONFIDENTIAL/PROPRIETARY

https://Dr-Bios.com
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, TBT-AR-SP(1/2) DP,PCIE
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 42 of 109
5 4 3 2 1
 5 4 3 2 1

Merion Limit height

RT48,RT49 change to 0201 from 0603

+0.9V_TBT_DP +0.9V_TBT_USB X10 +3.3V_TBT_SX change connect to +3.3V_ALW

+3.3V_VDD_PIC +3.3V_TBT_SX +3.3V_ALW

@JUMP@
PJP6 +3.3V_TBT

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
D 1 2 1 2 D
1 1 1 1 1 1 1 1 1 @ RT48 0_0201_5% VCC3P3_SVR:3.3V @ 0.6A max
CT25

CT26

CT27

CT28

CT29

CT30

CT31

CT32

CT33
PAD-OPEN1x1m +3.3V_TBT_LC 1 2
@RT49 0_0201_5%
No solder +3.3V_TBT_S0
2 2 2 2 2 2 2 2 2

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
CT44

CT45

CT46

CT47
1 1 1 1 1 1 1

CT41

CT42

CT43
2 2 2 2 2 2 2

R13
+0.9V_TBT_DP

R6

H9
F8
+0.9V_TBT_PCIE +0.9V_TBT_CIO UT1B
L8 A2 VCC0P9_SVR:0.9V @ 1.8A max

VCC3P3_SX

VCC3P3_S0

VCC3P3A
VCC3P3_LC
L11 VCC0P9_DP_0 VCC3P3_SVR_0 A3
VCC0P9_DP_1 VCC3P3_SVR_1 Minimum of 4vias must be used
L12 B3
M8 VCC0P9_DP_2 VCC3P3_SVR_2 +0.9V_TBT_SVR
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
T11 VCC0P9_DP_3
T12 VCC0P9_DP_4 L9

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
1 1 1 1 1 1 1 VCC0P9_DP_5 VCC0P9_SVR_0
CT34

CT35

CT36

CT37

CT38

CT39

CT40
L6 M9
M6 VCC0P9_ANA_DPSRC_0 VCC0P9_SVR_1 E12
VCC0P9_ANA_DPSRC_1 VCC0P9_SVR_ANA_0 1 1 1 1 1 1 1

CT48

CT49

CT50

CT51

CT52

CT53

CT54
V11 E13
2 2 2 2 2 2 2 V12 VCC0P9_ANA_DPSNK_0 VCC0P9_SVR_ANA_1 F11
+0.9V_TBT_PCIE V13 VCC0P9_ANA_DPSNK_1 VCC0P9_SVR_ANA_2 F12
VCC0P9_ANA_DPSNK_2 VCC0P9_SVR_ANA_3 F13 2 2 2 2 2 2 2
M13 VCC0P9_SVR_ANA_4 F15
M15 VCC0P9_PCIE_0 VCC0P9_SVR_ANA_5 J9
M16 VCC0P9_PCIE_1 VCC0P9_SVR_SENSE
L19 VCC0P9_PCIE_2
N19 VCC0P9_ANA_PCIE_1_0 C1 +TBT_SVR_IND LT1 1 2 0.6UH_MND-04ABIR60M-XGL_20%
L18 VCC0P9_ANA_PCIE_1_1 SVR_IND_0 C2

47U_0603_6.3V6M

47U_0603_6.3V6M

47U_0603_6.3V6M
VCC0P9_ANA_PCIE_2_0 SVR_IND_1

CT55

CT56

CT57
M18 D1 1 1 1
+0.9V_TBT_USB N18 VCC0P9_ANA_PCIE_2_1 SVR_IND_2 Share Same GND plane
VCC0P9_ANA_PCIE_2_2

VCC
with SVR_VSS of AR
R15 A1
R16 VCC0P9_USB_0 SVR_VSS_0 B1 2 2 2
+0.9V_TBT_CIO VCC0P9_USB_1 SVR_VSS_1 B2
R8 SVR_VSS_2
C VCC0P9_CIO_0 C
R9 SVR_VSS:Minimum of 4 vias must be used. +0.9V_TBT_LVR_OUT Intel review request
TBT Power circuit R11
R12
VCC0P9_CIO_1
VCC0P9_CIO_2 F18 Change 10U*4 to

1U_0201_6.3V6M

1U_0201_6.3V6M
Follow Intel recommendation VCC0P9_CIO_3 VCC0P9_LVR_0 H18

10U_0402_6.3V6M

10U_0402_6.3V6M
Add RT497 10K +VCC3V3_ANA_PCIE L16
VCC3P3_ANA_PCIE
VCC0P9_LVR_1
VCC0P9_LVR_2
J11 1 1 1 1 47U*3
+VCC3V3_ANA_USB2 J16

CT59

CT60

CT61

CT62
+3.3V_RUN +3.3V_TBT H11 20160324

1U_0201_6.3V6M

1U_0201_6.3V6M
VCC3P3_ANA_USB2 VCC0P9_LVR_SENSE

10K_0201_5%
1
JUMP@ 1 1 A6 V5
VSS_ANA_0 VSS_ANA_80 2 2 2 2

RT497

CT63

CT64
PJP5 A8 V6
2 1 A10 VSS_ANA_1 VSS_ANA_81 V8
2 1 A12 VSS_ANA_2 VSS_ANA_82 V9
JUMP_43X79 2 2 A14 VSS_ANA_3 VSS_ANA_83 V15

2
A16 VSS_ANA_4 VSS_ANA_84 V16
A18 VSS_ANA_5 VSS_ANA_85 V20
A20 VSS_ANA_6 VSS_ANA_86 W5
A22 VSS_ANA_7 VSS_ANA_87 W6
B6 VSS_ANA_8 VSS_ANA_88 W8
B8 VSS_ANA_9 VSS_ANA_89 W9
B10 VSS_ANA_10 VSS_ANA_90 W20
B12 VSS_ANA_11 VSS_ANA_91 W22
B14 VSS_ANA_12 VSS_ANA_92 W23
B16 VSS_ANA_13 VSS_ANA_93 Y9
B18 VSS_ANA_14 VSS_ANA_94 Y13
B20 VSS_ANA_15 VSS_ANA_95 Y20
B22 VSS_ANA_16 VSS_ANA_96 AA22
D8 VSS_ANA_17 VSS_ANA_97 AA23
D9 VSS_ANA_18 VSS_ANA_98 AB6
D11 VSS_ANA_19 VSS_ANA_99 AB8
LT2 change footprint to D12 VSS_ANA_20 VSS_ANA_100 AB10
CHILI_PBY160808T-300Y-N_2P D13 VSS_ANA_21 VSS_ANA_101 AB12
follow DFX request D15 VSS_ANA_22 VSS_ANA_102 AB14
D16 VSS_ANA_23 VSS_ANA_103 AB16
VSS_ANA_24 VSS_ANA_104

GND
+3.3V_TBT_S0 change pn to SHI0000N600 +3.3V_TBT D18 AB18
E8 VSS_ANA_25 VSS_ANA_105 AB20
1 2 E9 VSS_ANA_26 VSS_ANA_106 AB22
LT2 1UH_LQM18PN1R0MFHD_20% E11 VSS_ANA_27 VSS_ANA_107 AC6
1U_0201_6.3V6M

47U_0603_6.3V6M

47U_0603_6.3V6M

E15 VSS_ANA_28 VSS_ANA_108 AC8

E16 VSS_ANA_29 VSS_ANA_109 AC10
1 1 1 VSS_ANA_30 VSS_ANA_110
CT67

CT68

CT69

B E22 AC12 B
E23 VSS_ANA_31 VSS_ANA_111 AC14
F9 VSS_ANA_32 VSS_ANA_112 AC16
2 2 2 F16 VSS_ANA_33 VSS_ANA_113 AC18
F20 VSS_ANA_34 VSS_ANA_114 AC20
G22 VSS_ANA_35 VSS_ANA_115 AC22
G23 VSS_ANA_36 VSS_ANA_116 D5
H1 VSS_ANA_37 VSS_0 E4
H2 VSS_ANA_38 VSS_1 E5
H12 VSS_ANA_39 VSS_2 E6
H13 VSS_ANA_40 VSS_3 F5
H15 VSS_ANA_41 VSS_4 F6
H16 VSS_ANA_42 VSS_5 H5
H20 VSS_ANA_43 VSS_6 H8
J5 VSS_ANA_44 VSS_7 J8
J18 VSS_ANA_45 VSS_8 J12
J19 VSS_ANA_46 VSS_9 J13
J20 VSS_ANA_47 VSS_10 J15
J22 VSS_ANA_48 VSS_11 L13
J23 VSS_ANA_49 VSS_12 M11
K1 VSS_ANA_50 VSS_13 M12
K2 VSS_ANA_51 VSS_14 N8
L5 VSS_ANA_52 VSS_15 N9
L20 VSS_ANA_53 VSS_16 N11
L22 VSS_ANA_54 VSS_17 N12
L23 VSS_ANA_55 VSS_18 N13
M1 VSS_ANA_56 VSS_19 T6
M2 VSS_ANA_57 VSS_20 T8
M5 VSS_ANA_58 VSS_21 T9
M19 VSS_ANA_59 VSS_22 T13
VSS_ANA_60 VSS_23
VSS_ANA_66
VSS_ANA_67
VSS_ANA_68
VSS_ANA_69
VSS_ANA_70
VSS_ANA_71
VSS_ANA_72
VSS_ANA_73
VSS_ANA_74
VSS_ANA_75
VSS_ANA_76
VSS_ANA_77
VSS_ANA_78
VSS_ANA_79
M20 T15
N5 VSS_ANA_61 VSS_24 T16
N20 VSS_ANA_62 VSS_25 T18
N22 VSS_ANA_63 VSS_26 AB1
N23 VSS_ANA_64 VSS_27 AC2
VSS_ANA_65 VSS_28
P1
P2
R5
R18
R19
R20
R22
R23
T1
T2
T5
T20
U22
U23

ALPINE-RIDGE_BGA337
A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, TBT-AR-SP(2/2) VCC/VSS
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 43 of 109
5 4 3 2 1
 5 4 3 2 1

+3.3V_TBTA_FLASH +3.3V_TBTA_FLASH For AR port1

2

2
3.3K_0201_5%

3.3K_0201_5%

3.3K_0201_5%

3.3K_0201_5%
1 UPD1_SMBCLK_R
1 2
CT70 <58> UPD1_SMBCLK @ RT58 0_0201_5%
RT50

RT51

RT52

RT53
0.1U_0201_10V6K
2 1 2 UPD1_SMBDAT_R
<58> UPD1_SMBDAT
1

1
@ RT59 0_0201_5%
UT6
8 1 TBTA_ROM_CS#_PD 1 2 UPD1_SMBINT#_R
D TBTA_ROM_HOLD#_PD VCC CS# TBTA_ROM_DO_PD <58> UPD1_SMBINT# D
7 2 @ RT60 0_0201_5%
TBTA_ROM_CLK_PD 6 HOLD#(IO3) DO(IO1) 3 TBTA_ROM_W P#_PD
TBTA_ROM_DI_PD 5 CLK WP#(IO2) 4
DI(IO0) GND
GD25Q80CSIGR_SO8

+5V_ALW
JUMP@ +20V_TBTA_VBUS_1 RF requeat
PJP8 TI is 1x47uf+1x0.1uf
1 2 +5V_ALW _PDA
X10 +3.3V_VDD_PIC_PDA change connect to +3.3V_ALW
+3.3V_VDD_PIC +3.3V_VDD_PIC_PDA
PAD-OPEN1x2m

100P_0402_50V8J~D
RF@ CT22
22U_0603_10V6M

22U_0603_10V6M

22U_0603_10V6M

22U_0603_10V6M
1 1 1 1

1
1 2

CT75

CT76

CT77

CT78
@ RT482 0_0201_5%
+3.3V_ALW

2
2 2 2 2
1 2
@ RT483 0_0201_5%

+TBTA_LDO_BMC
+VCC1V8D_TBTA_LDO @ RT64 1 2 0_0201_5%
+VCC1V8A_TBTA_LDO
@ RT65 1 2 0_0201_5%
+3.3V_VDD_PIC_PDA

HV_GATE1_A

HV_GATE2_A
2.2U_0402_16V6K

2.2U_0402_16V6K

2.2U_0402_16V6K
1 1 1
TI is 3x1uf
+5V_ALW _PDA

CT71

CT72

CT73

10U_0402_6.3V6M
1
2 2 2 1 2

CT74
DIV = R2/(R1+R2) Follow TI SPEC @ RT63 0_0201_5%
Factory Device Description CT74 change to 10U

H10

C11
D11
A11
B11

B10

A10
Configuration 2

H1

B1

K1

A2

E1

A6
A7
A8
B7

B9

A9
C DIV_min DIV_max +3.3V_TBTA_FLASH UT5
C

F1

VIN_3V3

VDDIO

LDO_1V8A

PP_CABLE

PP_5V0_1
PP_5V0_2
PP_5V0_3
PP_5V0_4

GND_1
GND_2
GND_3
GND_4

SENSEP

HV_GATE1

HV_GATE2
LDO_1V8D

LDO_BMC

SENSEN
UFP only I2C_ADDR
5V @0.9A Sink capability with "Ask for Max/" for D1
<42> TBT_I2C_SDA
2

0.00 0.08 0 anything from 0.9 -3.0A D2 I2C_SDA1 +20V_TBTA_VBUS_1

TBT Alternate Modes not supported +3.3V_TBTA_FLASH <42> TBT_I2C_SCL I2C_SCL1
C1
DisplayPort Alternate Modes not supported 10K_0201_1% <42> TBTA_I2C_INT I2C_IRQ1_N TI has 1x1uf
TI VID supported RT76 +3.3V_ALW
@ RT66 1 2 3.3K_0201_5% UPD1_SMBDAT_R A5 +3.3V_PDA_VOUT +3.3V_TBTA_FLASH
1

UFP only PD1_GPIO8 @ RT67 1 2 3.3K_0201_5% UPD1_SMBCLK_R B5 I2C_SDA2 H11

I2C_SCL2 VBUS_1

1
5V @0.9A Sink capability with "Ask for Max/" for @ RT68 1 2 10K_0201_5% UPD1_SMBINT#_R B6 J10

CT82
1U_0603_50V6K

1U_0201_6.3V6M

10U_0402_6.3V6M
I2C_IRQ2_N VBUS_2
1

0.10 0.18 1 anything from 0.9 -3.0A J11

TBT Alternate Modes not supported VBUS_3 1 1

CT83

CT84
RT377 B2 K11

2
DisplayPort Alternate Modes -Sink, C and D pin configuration C2 GPIO0 VBUS_4
TI VID supported 43K_0402_1% <82,84> EN_PD_HV_1
RT71 1 2 1M_0201_5% PD1_GPIO2 D10 GPIO1
G11 GPIO2 2 2
2

UFP only C10 GPIO3

5V @3.0A Source capability <42> TBTA_HPD GPIO4
0.20 0.28 2 E10 H2
TBT Alternate Modes not supported G10 GPIO5 VOUT_3V3
DisplayPort Alternate Modes not supported D7 GPIO6
TI VID supported PD1_GPIO8 H6 GPIO7
GPIO8 G1
GPIO8: USB_TYPEC_FAULT# TBTA_ROM_CLK_PD LDO_3V3
UFP only A3
0.30 0.38 3 5V @3.0A Source capability TBTA_ROM_DI_PD B4 SPI_CLK
TBT Alternate Modes not supported Follow ARD 0.98 Thunderbolt Route USB2.0 ports as per WHL architecture TBTA_ROM_DO_PD A4 SPI_MOSI
DisplayPort Alternate Modes -Sink, C and D pin configuration 1 2 TBTA_ROM_CS#_PD B3 SPI_MISO K6
TI VID supported <10> USB20_P1 SPI_SS_N C_USB_TP TBTA_TOP_P <45>
@ RT400 1 2 0_0201_5% L6
TBTA_TOP_N <45>
<10> USB20_N1 TBTA_USB20_P_R C_USB_TN
@ RT401 1 2 0_0201_5% L5
<42> TBTA_USB20_P TBTA_USB20_N_R USB_RP_P
DRP @ RT402 1 2 0_0201_5% K5
5V @0.9-3.0A Sink capability <42> TBTA_USB20_N UART_MOSI USB_RP_N
@ RT403 0_0201_5%
0.40 0.48 5V @3.0A Source capability 1 2 E2 K7
TBT Alternate Modes not supported UART_MISO UART_TX C_USB_BP TBTA_BOT_P <45>
4 @ RT83 0_0201_5% F2 L7
DisplayPort Alternate Modes not supported UART_RX C_USB_BN TBTA_BOT_N <45>
TI VID supported SW D_DATA
@ T219 PAD~D 1 F4
Accepts data and power role swaps, but does not SW D_CLK SWD_DATA
initiate. @ 1 G4 TI has 2x220pf
UART_MOSI T220 PAD~D SWD_CLK TBTA_CC1 <45>
2 1 L9
RT81 100K_0201_5% Follow TI SPEC C_CC1 L10
DRP 2 1 UART_MISO RT86 change to 100K C_CC2 WHEN CONNECT BUSPOWERZ TO GND,

220P_0402_50V8J

220P_0402_50V8J
5V @0.9-3.0A Sink capability TBTA_MRESET TBTA_CC2 <45>
@ RT82 1M_0201_5% RT86 2 1 100K_0201_5% E11 CONNECT ALSO RPD_Gn to C_CCn 1 1
5V @3.0A Source capability MRESET
TBT Alternate Modes not supported K9 1 2

CT85

CT86
0.50 0.58 5
DisplayPort Alternate Modes - Source, C, D, and E TI ref ckt: 100k L4 RPD_G1 K10 @ RT104 1 2 0_0201_5%
B pin configurations. <42> TBTA_LSTX B
Intel ref ckt: 1M K4 TBT_LSTX/R2P RPD_G2 @ RT105 0_0201_5% +3.3V_TBTA_FLASH 2 2
TI VID supported <42> TBTA_LSRX TBT_LSRX/P2R
Accepts power role swaps but will not initiate.
Accepts data role swap to UFP and can initiate. TBTA_LSTX TBTA_DEBUG3 TBTA_DBG_CTL1
1 2 L3 E4 RT106 1 2 10K_0201_5%
DRP TBTA_LSRX @ RT89 1 2 0_0201_5% TBTA_DEBUG4 K3 DIG_AUD_P/DEBUG3 DEBUG_CTL1 D5 TBTA_DBG_CTL2 RT107 1 2 10K_0201_5%
5V @0.9-3.0A Sink capability @ RT90 0_0201_5% DIG_AUD_N/DEBUG4 DEBUG_CTL2
5V @3.0A Source capability
0.60 0.68 6 TBT Alternate Modes not supported UPD1_SMBCLK_R L2
DisplayPort Alternate Modes - Source, C, D, and E UPD1_SMBDAT_R K2 DEBUG1
pin configurations. DEBUG2
TI VID supported
Accepts power role swaps but will not initiate. K8
TBTA_AUXP_C C_SBU1 TBTA_SBU1 <45>
Accepts data role swap to DFP and can initiate. CT80 1 2 0.1U_0201_10V6K J1
<42> TBTA_AUXP TBTA_AUXN_C AUX_P
CT81 1 2 0.1U_0201_10V6K J2 L8
<42> TBTA_AUXN AUX_N C_SBU2 TBTA_SBU2 <45>
0.70 1.00 7 Infinite boot retry from Flash to Host I/F cycles.
+3.3V_TBTA_FLASH
F10
BUSPOWER_N F11 TBTA_RESET_N_EC_R 1 2
+3.3V_TBTA_FLASH RESET_N @ RT110 0_0201_5% TBT_RESET_N_EC <42,58>

HRESET
TBTA_AUXN_C TBTA_ROSC

GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21

GND_22
GND_23
GND_24
RT95 2 1 100K_0201_5% G2

GND_5

GND_6
GND_7
GND_8
GND_9
R_OSC
1

15K_0201_1%

SS
2

RT96 2 1 100K_0201_5% TBTA_AUXP_C

RT100

@ RT98 SN1804044ZBHR_NFBGA96

A1
D6
E5
E6
E7
F5
G5
H4
H5
B8
D8
E8
F6
F7
F8
G6
G7
G8
H7
H8
L1
L11
0_0201_5%
2
1

+VCC1V8D_TBTA_LDO 1 2
@ RT97 0_0201_5%

100K_0201_5%
1

0_0201_5%
1
2

RT101

@ RT103
CT87
@ RT99
0_0201_5% 0.22U_0402_16V7K
2

1
1

A A

DELL CONFIDENTIAL/PROPRIETARY

https://Dr-Bios.com
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT [Type C]PD Controller TI
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 44 of 109
5 4 3 2 1
 5 4 3 2 1

M
e
r
i
o
n
u
s
e
S
M
T
t
y
p
e
,
n
o
t
H
y
b
r
i
d
+20V_TBTA_VBUS +20V_TBTA_VBUS
RF Request
+20V_TBTA_VBUS
+20V_TBTA_VBUS

JUSBC1 CONN@
A1 B12
GND_1 GND_4

1
TBT_A_TTX_C_DRX_P1 A2 B11 TBT_A_TRX_C_DTX_P1
TBT_A_TTX_C_DRX_N1 A3 SSTXP1 SSRXP1 B10 TBT_A_TRX_C_DTX_N1 ESD@
SSTXN1 SSRXN1

12P_0402_50V8J
RF@ CT189

82P_0402_50V8J
RF@ CT190
1 1 DT4
2 1 A4 B9 2 1 AZ4A24-01F.R7G_DFN0603P2Y2
CT99 0.47U_0201_25V VBUS_1 VBUS_4 CT100 0.47U_0201_25V
TBTA_CC2 A5 B8 TBTA_SBU1
D <44> TBTA_CC2 TBTA_SBU1 <44> Merion Limit height D

2
CC1 SBU2 2 2
<44> TBTA_BOT_P 0_0201_5% 2 1 RT123 @EMI@TBTA_BOT_P_R A6 B7 TBTA_TOP_N_R 0_0201_5% 2 1 RT121 @EMI@ TBTA_TOP_N <44> DT4 change to H=0.32mm(MAX)
0_0201_5% 2 1 RT122 @EMI@TBTA_BOT_N_R A7 DP1 DN2 B6 TBTA_TOP_P_R 0_0201_5% 2 1 RT120 @EMI@
<44> TBTA_BOT_N DN1 DP2 TBTA_TOP_P <44>
TBTA_SBU2 A8 B5 TBTA_CC1

Bottom
<44> TBTA_SBU2 SUB1 CC2 TBTA_CC1 <44>
2 1 A9 B4 2 1

TOP
0.47U_0201_25V CT101 VBUS_2 VBUS_3 CT102 0.47U_0201_25V
TBT_A_TRX_C_DTX_N0 A10 B3 TBT_A_TTX_C_DRX_N0
TBT_A_TRX_C_DTX_P0 A11 SSRXN2 SSTXN2 B2 TBT_A_TTX_C_DRX_P0
SSRXP2 SSTXP2
A12 B1
GND_2 GND_3
1 4
GND_5 GND_8
2 3
5 GND_6 GND_7 6
7 GND_9 GND_10 8
NPTH_1 NPTH_2
JAE_DX07SD24JJ2R1300~D

Link DX07SD24JJ2R1300 done 0123

Remove Low Speed VBUS-Short Protection

C C

AC coupling is recommended for

Place holder for future VBUS-short VBUS-short protection on SSRX lines. If not
fix (reduce current surge) needed, place 0 Ohm resistor instead.
TBT_A_TRX_DTX_P0 RT190 1 2 2.2_0201_1% TBT_A_TRX_R_DTX_P0 CT326 1 2 0.33U_0201_25V6K TBT_A_TRX_C_DTX_P0
<42> TBT_A_TRX_DTX_P0 TBT_A_TRX_DTX_N0 RT191 1 2 2.2_0201_1% TBT_A_TRX_R_DTX_N0 CT327 1 2 0.33U_0201_25V6K TBT_A_TRX_C_DTX_N0
<42> TBT_A_TRX_DTX_N0
TBT_A_TTX_DRX_P0 RT192 1 2 2.2_0201_1% TBT_A_TTX_R_DRX_P0 CT95 1 2 0.22U_0201_25V6K TBT_A_TTX_C_DRX_P0
<42> TBT_A_TTX_DRX_P0 TBT_A_TTX_DRX_N0 TBT_A_TTX_R_DRX_N0 TBT_A_TTX_C_DRX_N0
RT193 1 2 2.2_0201_1% CT96 1 2 0.22U_0201_25V6K
<42> TBT_A_TTX_DRX_N0
ESD@ DT5 ESD@ DT13
TBT_A_TRX_DTX_P1 RT194 1 2 2.2_0201_1% TBT_A_TRX_R_DTX_P1 CT328 1 2 0.33U_0201_25V6K TBT_A_TRX_C_DTX_P1
<42> TBT_A_TRX_DTX_P1 TBT_A_TRX_DTX_N1 RT195 1 2 2.2_0201_1% TBT_A_TRX_R_DTX_N1 CT329 1 2 0.33U_0201_25V6K TBT_A_TRX_C_DTX_N1 TBT_A_TTX_R_DRX_P0 1 2 TBT_A_TRX_R_DTX_P0 1 2
<42> TBT_A_TRX_DTX_N1
TBT_A_TTX_DRX_P1 RT196 1 2 2.2_0201_1% TBT_A_TTX_R_DRX_P1 CT97 1 2 0.22U_0201_25V6K TBT_A_TTX_C_DRX_P1 DESD3V3Z1BCSF-7 X2-DSN0603-2 DESD3V3Z1BCSF-7 X2-DSN0603-2
<42> TBT_A_TTX_DRX_P1 TBT_A_TTX_DRX_N1 TBT_A_TTX_R_DRX_N1 TBT_A_TTX_C_DRX_N1
RT197 1 2 2.2_0201_1% CT98 1 2 0.22U_0201_25V6K
<42> TBT_A_TTX_DRX_N1
ESD@ DT6 ESD@ DT14
TBT_A_TTX_R_DRX_N0 1 2 TBT_A_TRX_R_DTX_N0 1 2

DESD3V3Z1BCSF-7 X2-DSN0603-2 DESD3V3Z1BCSF-7 X2-DSN0603-2

Discharge SSTX/SSRX resistors - must be ESD@ DT9 ESD@ DT17

B
placed if 330nF cap is being used. TBT_A_TRX_R_DTX_P1 1 2 TBT_A_TTX_R_DRX_P1 1 2 B

TBT_A_TTX_C_DRX_P1 1 2 TBT_A_TRX_C_DTX_P1 1 2 DESD3V3Z1BCSF-7 X2-DSN0603-2 DESD3V3Z1BCSF-7 X2-DSN0603-2

RT491 221K_0201_1% RT221 221K_0201_1%
TBT_A_TTX_C_DRX_N1 1 2 TBT_A_TRX_C_DTX_N1 1 2 ESD@ DT10 ESD@ DT18
RT490 221K_0201_1% RT222 221K_0201_1%
TBT_A_TTX_C_DRX_P0 1 2 TBT_A_TRX_C_DTX_P0 1 2 TBT_A_TRX_R_DTX_N1 1 2 TBT_A_TTX_R_DRX_N1 1 2
RT488 221K_0201_1% RT219 221K_0201_1%
TBT_A_TTX_C_DRX_N0 1 2 TBT_A_TRX_C_DTX_N0 1 2 DESD3V3Z1BCSF-7 X2-DSN0603-2 DESD3V3Z1BCSF-7 X2-DSN0603-2
RT489 221K_0201_1% RT220 221K_0201_1%

Mf
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i
ol
na
1y
4
Dr
To
3u
9t
Dn
,
Tg
4
0
c
h
a
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g
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p
i
n
d
e
f
i
n
e
o
r

o
u
t

i
DT39 ESD@ DT40 ESD@
TBTA_SBU1 1 1 TBTA_SBU1 TBTA_SBU2 TBTA_SBU2
10 9 1 1 10 9
TBTA_TOP_N_R 2 2 9 8 TBTA_TOP_N_R TBTA_BOT_N_R 2 9 8 TBTA_BOT_N_R
2
TBTA_TOP_P_R 4 4 7 7 TBTA_TOP_P_R TBTA_BOT_P_R 4 7 7 TBTA_BOT_P_R
4
TBTA_CC1 5 5 6 6 TBTA_CC1 TBTA_CC2 5 5 6 6 TBTA_CC2

3 3 3 3

8 8
A A
AZ1045-04F_DFN2510P10E-10-9 AZ1045-04F_DFN2510P10E-10-9

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
USB 3.0 CONN TYPE C
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 45 of 109
5 4 3 2 1
 5 4 3 2 1

D D

Reserve
C C

B B

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
TYPE-C_Port2 (1/2)
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 46 of 109
5 4 3 2 1
 5 4 3 2 1

D D

Reserve
C C

B B

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
TYPE-C_Port2 (2/2)
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 47 of 109
5 4 3 2 1
 5 4 3 2 1

D D

Reserve
C C

B B

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
TYPE-C_Port3 (1/2)
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 48 of 109
5 4 3 2 1
 5 4 3 2 1

D D

Reserve
C C

B B

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
TYPE-C_Port3 (2/2)
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 49 of 109
5 4 3 2 1
 5 4 3 2 1

Reserve for external PD power

+3.3V_TBTA_FLASH +3.3V_VDD_PIC
+5V_ALW
DT1,DT2,DT3 change footprint to
1N4148WS-7-F_SOD323-2
follow DFX request 1 2
D @ RT399 0_0402_5% D
@ DT1 +5V_PD_VDD
2 1
+5V_TBT_VBUS @ UT7
1N4148W S-L_SOD323-2 1 5 +3.3V_VDD_PIC_R @ RT398 1 2 0_0402_5%
@ DT2 VCC VOUT
2 1 2
GND

100K_0402_5%

0.1U_0201_10V6K

1U_0201_10V6M
@ RT111

1
@ RT393

@ CT88

@ CT89

100P_0201_25V8J
@RF@ CT359
1N4148W S-L_SOD323-2 1 1 1 2 3 4
EN ADJ/NC

2.2U_0402_10V6M

0.1U_0201_10V6K
100K_0402_5% 1 1 1

@ CT91

@ CT92
1
AP2112K-3.3TRG1_SOT23-5
2 2 @ CT90

2
1U_0201_10V6M 2 2 2
2

+20V_TBTA_VBUS_1 RF Request

@ UT8
place near UT7 place near UT17

1U_0603_25V6K
1
VCC

@ CT94
@DT3

1
1 2 +5V_TBTA_VBUS_D 3
VOUT 2
1N4148W S-L_SOD323-2 GND

2
AP2204R-5.0TRG1_SOT89-3
1U_0201_10V6M

1
@ CT193

C C

1031 change

B B

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
[Type C]PD Power
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 50 of 109
5 4 3 2 1
 5 4 3 2 1

D D

Reserve
C C

B B

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
LAN
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 51 of 109
5 4 3 2 1
 5 4 3 2 1

+3.3V_WWAN RF Request
+2.7V_ANT +1.8V_ANT +1.8V_PRIM
NGFF slot E Key E 1206 change
Follow NB14 UU AR

100P_0201_25V8J

100P_0201_25V8J
Add RZ603 for CNVi intel request
NGFF slot B Key B W W AN_FULL_PW R_EN

27P_0201_25V8
RF@CZ307

RF@CZ233

27P_0201_25V8
RF@CZ308

RF@CZ234
2 1 1 1 1 1 Close to connector
RZ43 10K_0402_5% +3.3V_WLAN

100P_0402_50V8J
CONN@ +3.3V_WWAN
CNV_BRI_PTX_DRX_R

RF@ CZ198
JNGFF2 CONN@ JNGFF1 @ RZ603 1 2 10K_0402_5%
2 2 2 2 1 2

1
1 2 USB20_P10_R 3 GND_1 3.3VAUX_1 4
<58> NGFF_CONFIG_3 CONFIG_3 3.3V_1 USB20_N10_R USB_D+ 3.3VAUX_2
3 4 5 6
5 GND_1 3.3V_2 6 W W AN_FULL_PW R_EN 7 USB_D- LED1# 8
WWAN_FULL_PWR_EN <9>

2
USB20_P7_L 7 GND_2 FULL_CARD_POWER_OFF# 8 WWAN_RADIO_DIS#_R CNV_PRX_DTX_N1 9 GND_2 PCM_CLK 10 CNV_RF_RESET#
USB20_N7_L USB_D+ W_DISABLE# SLOT2_SATA_LED# <6> CNV_PRX_DTX_N1 CNV_PRX_DTX_P1 SIDO_CLK PCM_SYNC CNV_RF_RESET# <12,52>
9 10 1 2 11 12
11 USB_D- LED1# @ RZ1477 0_0201_5%
place near JNGFF2 <6> CNV_PRX_DTX_P1 13 SDIO_CMD PCM_IN 14 CLKREQ_CNV#_R 2 1 CLKREQ_CNV#
GND_3 CNV_PRX_DTX_N0 SDO_DAT0 PCM_OUT CLKREQ_CNV# <12>
1211 change,add netname +2.7V_ANT_R and +1.8V_ANT_R 15 16 0_0201_5% @ RZ1385
<6> CNV_PRX_DTX_N0 CNV_PRX_DTX_P0 17 SDO_DAT1 LED2# 18
Module provides for 4x4 Antenna use <6> CNV_PRX_DTX_P0 19 SDO_DAT2 GND_3 20
D 20 +2.7V_ANT_R RZ90 1 2 0_0603_5% CLK_CNV_PRX_DTX_N 21 SDO_DAT3 UART_WAKE# 22 CNV_BRI_PRX_DTX_R 1 2 D
I2S_CLK +2.7V_ANT <6> CLK_CNV_PRX_DTX_N CLK_CNV_PRX_DTX_P SDIO_WAKE# UART_RX CNV_BRI_PRX_DTX <9>
21 22 23 RZ1381 22_0402_5%
<58> NGFF_CONFIG_0 CONFIG_0 I2S_RX +1.8V_ANT_R <6> CLK_CNV_PRX_DTX_P SDIO_RESET#
23 24 RZ91 1 2 0_0603_5% +1.8V_ANT
<58> W W AN_W AKE# WOWWAN# I2S_TX GPS_DISABLE#_R
2 1 25 26
@RF@ RZ326 0_0201_5% 27 DPR W_DISABLE2# 28 1031 change,RZ90 RZ91 reserve for FUSE location
PCIE_PRX_L_DTX_N11 29 GND_4 I2S_WA 30 UIM_RESET 32 CNV_RGI_PTX_DRX_R
PCIE_PRX_L_DTX_P11 PERN1/USB3.0-RX-/SSIC-RXN UIM-RESET UIM_CLK UART_TX CNV_RGI_PRX_DTX_R CNV_RGI_PTX_DRX_R <9>
31 32 33 34 RZ1383 1 2 22_0402_5%
PERP1/USB3.0-RX+/SSIC-RXP UIM-CLK UIM_DATA +SIM_PWR PCIE_PTX_C_DRX_P10 35 GND_4 UART_CTS CNV_BRI_PTX_DRX_R CNV_RGI_PRX_DTX <9>
33 34 CZ12 1 2 0.1U_0402_25V6 36
PCIE_PTX_L_DRX_N11 GND_5 UIM-DATA <10> PCIE_PTX_DRX_P10 PCIE_PTX_C_DRX_N10 37 PETP0 UART_RTS CNV_BRI_PTX_DRX_R <9>
35 36 CZ13 1 2 0.1U_0402_25V6 38
Swap PN for support SATA PCIE_PTX_L_DRX_P11 37 PETN1/USB3.0-TX-/SSIC-TXN UIM-PWR 38 WLAN <10> PCIE_PTX_DRX_N10
39 PETN0 CLink_RST 40 PCH_CL_RST1# <8>
PETP1/USB3.0-TX+/SSIC-TXP DEVSLP ISH_I2C2_SCL_R M3042_DEVSLP <10> GND_5 CLink_DATA PCH_CL_DATA1 <8>
39 40 2 1 41 42
GND_6 GPIO_0 ISH_I2C2_SDA_R @ RZ76 2 ISH_I2C2_SCL <9> <10> PCIE_PRX_DTX_P10 PERP0 CLink_CLK W LAN_COEX3 PCH_CL_CLK1 <8>
41 42 1 0_0201_5% 43 44
<10> PCIE_PRX_DTX_P12 PERN0/SATA-B+ GPIO_1 ISH_I2C2_SDA <9> <10> PCIE_PRX_DTX_N10 PERN0 COEX3 W LAN_COEX2
43 44 @ RZ77 0_0201_5% 45 46
<10> PCIE_PRX_DTX_N12 45 PERP0/SATA-B- GPIO_2 46 47 GND_6 COEX2 48 W LAN_COEX1
GND_7 GPIO_3 <11> CLK_PCIE_P1 REFCLKP0 COEX1
CZ210 1 2 0.1U_0402_25V6 PCIE_PTX_C_DRX_N12 47 48 9/24: Reserve for embedded location ,refer Intel PDG 0.9 49 50 W IGIG_32KHZ 0_0201_5% 2 1@ RZ56
<10> PCIE_PTX_DRX_N12 PETN0/SATA-A- GPIO_4 <11> CLK_PCIE_N1 REFCLKN0 SUSCLK(32KHz) SUSCLK <11,68>
CZ211 1 2 0.1U_0402_25V6 PCIE_PTX_C_DRX_P12 49 50 PCH_PLTRST#_AND 51 52 PCH_PLTRST#_AND
<10> PCIE_PTX_DRX_P12 PETP0/SATA-A+ PERST# GND_7 PERST0# BT_RADIO_DIS#_R PCH_PLTRST#_AND <11,38,42,68,70>
51 52 53 54
GND_8 CLKREQ# PCIE_W AKE# CLKREQ_PCIE#0 <11> <11> CLKREQ_PCIE#1 PCIE_W AKE# CLKEQ0# W_DISABLE2# WLAN_WIGIG60GHZ_DIS#_R 9/24: Reserve for embedded location ,refer Intel PDG 0.9
53 54 55 56
<11> CLK_PCIE_N0 REFCLKN PEWAKE# W W AN_MIPI_ANT_DAT <42,59,68> PCIE_W AKE# PEWAKE0# W_DISABLE1# ISH_UART0_RXD_R
55 56 57 58 @ RZ78 2 1 0_0201_5%
<11> CLK_PCIE_P0 REFCLKP NC_1 W W AN_MIPI_ANT_CLK CNV_PTX_DRX_N1 GND_8 I2C_DATA ISH_UART0_TXD_R
57 58 59 60 @ RZ79 2 1 0_0201_5%
GND_9 NC_2 WWAN_COEX3 <6> CNV_PTX_DRX_N1 RSRVD/PETP1 I2C_CLK
59 60 @RF@ RZ128 1 2 0_0201_5% W LAN_COEX3 CNV_PTX_DRX_P1 61 62 ISH_UART0_CTS#_R @ RZ80 2 1 0_0201_5%
ANTCTL0 COEX3 WWAN_COEX2 <6> CNV_PTX_DRX_P1 RSRVD/PETN1 ALERT
61 62 @RF@ RZ129 1 2 0_0201_5% W LAN_COEX2 63 64
ANTCTL1 COEX2 WWAN_COEX1 GND_9 RSVD_1 REFCLK_CNV_L <11>
63 64 @RF@ RZ130 1 2 0_0201_5% W LAN_COEX1 CNV_PTX_DRX_N0 65 66
ANTCTL2 COEX1 SIM_DET <6> CNV_PTX_DRX_N0 CNV_PTX_DRX_P0 RSRVD_2/PERP1 RSVD_3
65 66 67 68
ANTCTL3 SIM_DETECT <6> CNV_PTX_DRX_P0 RSRVD_4/PERN1 RSVD_5

1
W W AN_ANT_CONFIG

10K_0402_5%
@ RZ752
67 68 69 70 1206 change
69 RESET# SUSCLK 70 @RF@ RZ373 1 2 0_0201_5% CNV_COEX1 CLK_CNV_PTX_DRX_N 71 GND_10 RSVD_6 72 Follow NB14 UU AR, for CNVI CLK request
<54,58> NGFF_CONFIG_1 CONFIG1/PEDET_OC-PCIE/GND-SATA 3.3V_3 CNV_COEX1 <6> <6> CLK_CNV_PTX_DRX_N RSVD_7 3.3VAUX_3
71 72 @RF@ RZ372 1 2 0_0201_5% CNV_COEX2 CLK_CNV_PTX_DRX_P 73 74
GND_10 3.3V_4 CNV_COEX2 <6> <6> CLK_CNV_PTX_DRX_P RSVD_8 3.3VAUX_4
73 74 @RF@ RZ374 1 2 0_0201_5% CNV_COEX3 75
GND_11 3.3V_5 CNV_COEX3 <6> GND_11
75

2
<58> NGFF_CONFIG_2 CONFIG2/USB3.0IND/GND-OTHER

1
470_0402_1%
i7@ RZ1450
77 76 +3.3V_ALW
78 76 GND_13 GND_12
0103 change
79 NPTH_1 GND_12 77 79 78

100K_0402_5%
NPTH_2 GND_13 NPTH_2 NPTH_1

RZ377
1
LOTES_APCI0128-P005A 1218

2
DEREN_40-42313-06711RHFAN ANT_CONFIG Antenna Configuration Add RZ827 connect to CNVI_EN# for reserve
RZ1450

Link DEREN_40-42313-06711RHFAN done 0410 Pop 4x4 Antenna Link APCI0128-P005A done 0122

2
0_0201_5% 2 1 @ RZ827
<58> CNV_DET#_EC CNVI_EN# <12>
Depop 2x2 Antenna
RF Request Place close JNGFF2 connector
+3.3V_WWAN 1218
C C
+3.3V_WWAN Change net name from CNV_RF_RESET to CNV_DET#_EC

1
1213 change
Add CZ311 and CZ312 for RF request D
.047U_0402_16V7K

.047U_0402_16V7K

33P_0402_50V8J

33P_0402_50V8J

2 G QZ17
1
1
3
0r
cn
h
a
n
gLg
e
<12,52> CNV_RF_RESET#
47P_0402_50V8J

100P_0402_50V8J

2000P_0402_50V7K

PJE138K_SOT523-3
RF@
22U_0603_6.3V6M

RF@ CZ24

100U_B3_6.3VM_R45M
RF@CZ26

27P_0402_50V8J
RF@ CZ311

27P_0402_50V8J
RF@ CZ312

MCf
eZ
i
o6
1
4a

ie0
m
t 0
i
h
e
i
g
h
t0
1 75K PD at PCH side S
RF@ CZ25
1

1
CZ20

1 1 VGS(th)Max=1.5V
2m
c
hS
nA

t
o
ST
G0
A
0
0
0
6
8
0
0

3
1

1
CZ17

CZ18

CZ19

CZ21

+
CZ23

r
o

G
0
0
5
0
1130 change
2

1 2 WLAN_WIGIG60GHZ_DIS#_R
2

2 2 2 <58> W LAN_W IGIG60GHZ_DIS#

DZ1
RB751S-40_SOD523-2
1 2 BT_RADIO_DIS#_R
<58> BT_RADIO_DIS#
DZ2
RB751S-40_SOD523-2
MF
e
r
i
o
nl
d
e
l
e
ep
t
Ry
I
2
7
~p
Rl
I
3
0e

+3.3V_WLAN
M
e
r
i
o
n
1
4
s
w
a
p
L
I
1
6
,
L
I
1
7
n
e
t
f
o
r
l
a
y
o
u
t
r
o
u
t
i
n
g

o
r
a
y
o
u
t
l
a
o
u
t
a
c
m
e
n
t

LI16 RF@
1 2 PCIE_PRX_L_DTX_N11
<54> PCIE_PRX_SW_DTX_N11

0.01UF_0402_25V7K

0.1U_0201_10V6K

10U_0603_10V6M

0.01UF_0402_25V7K

0.1U_0201_10V6K

4.7U_0402_10V6M
4 3 PCIE_PRX_L_DTX_P11
<54> PCIE_PRX_SW_DTX_P11 1 1 1 1

1
1 2 WWAN_RADIO_DIS#_R
<58> WWAN_RADIO_DIS#

CZ28

CZ30

CZ27

CZ29

CZ31

CZ32
HCM1012GH900BP_4P DZ5

2
2 2 2 2
RB751S-40_SOD523-2
WWAN_MIPI_ANT_DAT and WWAN_MIPI_ANT_CLK
GPS_DISABLE#_R
Follow KW13 MLK delete CI29,CI30 <58> GPS_DISABLE#
1 2
(1)The trace length < 30cm
1
LI17 RF@
2 PCIE_PTX_L_DRX_N11
DZ6
RB751S-40_SOD523-2 This max length guidance is practical level of definition.
<54> PCIE_PTX_SW_DRX_N11
(2)Spacing to all other signal need 4x line width Place near JNGFF1.72/JNGFF1.74 Place near JNGFF1.2/JNGFF1.4
4 3 PCIE_PTX_L_DRX_P11
B
<54> PCIE_PTX_SW_DRX_P11
For WWAN 4x4 Antenna B
HCM1012GH900BP_4P RF Request Place near JNGFF1 connector
+3.3V_WLAN 1213 change RF request
1130 change CONN@ 1130 change CONN@ CZ206 and CZ207 from depop to pop and Change Value from 100p to 27p
@RF@ JANT1 @RF@ JANT2
RZ1460 1 2 0_0201_5% 1 RZ1461 1 2 0_0201_5% 1
2 1 2 1

SIM Card Push-Push +1.8V_ANT

3 2 +1.8V_ANT
3 2

15P_0402_50V8J

15P_0402_50V8J

15P_0402_50V8J

15P_0402_50V8J

100P_0402_50V8J~D

100P_0402_50V8J~D
+2.7V_ANT W W AN_MIPI_ANT_CLK 3 +2.7V_ANT W W AN_MIPI_ANT_CLK 3
4 4

RF@ CZ33

RF@ CZ34

RF@ CZ35

RF@ CZ36

RF@ CZ204

RF@ CZ205

27P_0402_50V8J
RF@ CZ206

27P_0402_50V8J
RF@ CZ207
W W AN_MIPI_ANT_DAT 5 4 W W AN_MIPI_ANT_DAT 5 4
5 5 1 1

1
JSIM1 CONN@ 6 6
C8 3
DW5821e SPEC Request 7 GND1 7 GND1
UIM_DATA RFU1 GND1 GND2 GND2

2
C7 4 8 8 2 2
C6 IO GND2 5 @ESD@
RF Request 9 GND3 9 GND3
MF
e
rr
i
o
nl
d
e
l
e
ep
t
Ry
I
4
7
,
Rp
4a
I
8

C5 VPP GND3 6 DZ13 10 GND4 10 GND4

+SIM_PWR GND GND4 UIM_DATA UIM_DATA GND5 GND5
o
a
y
o
u
t
l
a
o
u
t
l
c
e
m
e
n
t

C4 7 1 1 10 9 11 11
UIM_CLK C3 RFU2 GND5 8 12 GND6 12 GND6
UIM_RESET C2 CLK GND6 9 UIM_CLK 2 2 9 8 UIM_CLK 13 GND7 13 GND7
RST GND7 GND8 GND8
4.7U_0402_6.3V6M

C1
VCC UIM_RESET 4 7 7 UIM_RESET I-PEX_20854-005E-00 I-PEX_20854-005E-00
4
1

SIM_DET SIM_DET
CZ37

5 5 6 6
1 10 Relink 20854-005E-00 done 0827 RF Request
2

SIM_DET 2 DLSW NPTH1 11 3 3

MF
e
rr
i
o
nl
d
eu
l
e
ep
t
Ry
I
4
9
,
Rp
Il
5
0c
DTSW NPTH2 LI8 RF@
USB20_P7_L RF Request

o
a
y
o
t
l
a
o
u
t
a
e
m
e
n
t
TAISO_159-1000300600 8 1 2
<10> USB20_P7
+2.7V_ANT +1.8V_ANT +2.7V_ANT +1.8V_ANT
Link TAISO_159-1000300600 done 0903 USB20_N7_L

120P_0402_50V8
RF@ CZ227

120P_0402_50V8
RF@ CZ228

120P_0402_50V8
RF@ CZ229

120P_0402_50V8
RF@ CZ230
AZ1045-04F_DFN2510P10E-10-9 4 3
<10> USB20_N7
1 1 1 1
MCM1012B900F06BP_4P
LI9 RF@
2 2 2 2 1 2 USB20_N10_R
+SIM_PWR <10> USB20_N10
RF Request
4 3 USB20_P10_R
place CZ227,CZ228 as close as JANT1 place CZ229,CZ230 as close as JANT2 <10> USB20_P10
@RF@ RZ335
1

UIM_CLK
15K_0402_5%

MCM1012B900F06BP_4P
47P_0402_50V8J
@RF@ CZ38

A A
1

STATE # CONFIG_0 CONFIG_1 CONFIG_2 CONFIG_3 Module Type M3042_PCIE#_SATA

2

+SIM_PWR
UIM_DATA UIM_RESET
2

GND GND GND GND SSD-SATA High

33P_0402_50V8J

33P_0402_50V8J
@RF@ RZ334

@RF@ CZ39

@RF@ CZ40
1
51_0402_5%

0.1U_0402_25V6
RF@ CZ41

1 GND HIGH GND GND SSD-PCIE(2 lane) Low

1

DELL CONFIDENTIAL/PROPRIETARY
HIGH GND GND GND W WAN Low
2

https://Dr-Bios.com
Compal Electronics, Inc.
2

Title
14 HIGH GND HIGH HIGH HCA-PCIE(1 lane) Low PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT NGFF Card
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size
15 HIGH HIGH HIGH HIGH NA Low Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 52 of 109
5 4 3 2 1
 5 4 3 2 1

D D

Reserve
C C

B B

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
WIGIG / WIDI
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 53 of 109
5 4 3 2 1
 5 4 3 2 1

D D

PCIE/USB MUX/DEMUX SW
Link TI HD3SS3212 done
+3.3V_WWAN

0.01U_0402_16V7K

.1U_0402_16V7K

10U_0402_10V6M
Follow TI SPEC
1 1 1 Add reserved CZ156 10uF.
C C

@ CZ156
CZ154 change to 0.01uF feom 0.1uF.

CZ154

CZ155
2 2 2

UZ29
1
USB3_PRX_DTX_P4 19 NC1 6
<10> USB3_PRX_DTX_P4 USB3_PRX_DTX_N4 B0p VCC
18 10
<10> USB3_PRX_DTX_N4 B0n NC2
CZ150 1 2 0.1U_0402_10V7K USB3_PTX_C_DRX_P4 17
<10> USB3_PTX_DRX_P4 B1p
CZ151 1 2 0.1U_0402_10V7K USB3_PTX_C_DRX_N4 16 3 PCIE_PRX_SW_DTX_P11
<10> USB3_PTX_DRX_N4 B1n A0p 4 PCIE_PRX_SW_DTX_N11 PCIE_PRX_SW_DTX_P11 <52>
PCIE_PRX_DTX_P11 A0n PCIE_PTX_SW_DRX_P11 PCIE_PRX_SW_DTX_N11 <52>
15 7
<10> PCIE_PRX_DTX_P11 PCIE_PRX_DTX_N11 14 C0p A1p 8 PCIE_PTX_SW_DRX_N11 PCIE_PTX_SW_DRX_P11 <52>
<10> PCIE_PRX_DTX_N11 CZ152 1 2 0.22U_0402_10V6K PCIE_PTX_C_DRX_P11 13 C0n A1n PCIE_PTX_SW_DRX_N11 <52>
<10> PCIE_PTX_DRX_P11 2 0.22U_0402_10V6K PCIE_PTX_C_DRX_N11 C1p
CZ153 1 12
<10> PCIE_PTX_DRX_N11 C1n 5
NGFF_CONFIG_1 9 GND1 11
<52,58> NGFF_CONFIG_1 SEL GND2 20
2 GND3 21
OEn PGND

Function SEL OEn HD3SS3212RKSR_VQFN20_2P5X4P5

B to A L L
C to A H L
All ports Hi-Z,
IC power down X H

B B

STATE # CONFIG_0 CONFIG_1 CONFIG_2 CONFIG_3 Module Type M3042_PCIE#_SATA

0 GND GND GND GND SSD-SATA HIGH

1 GND HIGH GND GND SSD-PCIE(2 lane) LOW

8 HIGH GND GND GND WWAN LOW

14 HIGH GND HIGH HIGH HCA-PCIE(1 lane) LOW

15 HIGH HIGH HIGH HIGH NA LOW

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
USB/PCIE MUX HD3SS3212
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 54 of 109
5 4 3 2 1
 5 4 3 2 1

D D

Reserve
C C

B B

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Reserve for PCIE device
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 55 of 109
5 4 3 2 1
 5 4 3 2 1

+3.3V_RUN_AUDIO

+5V_RUN_AUDIO
2 1 +3.3V_RUN_AUDIO_IO LA13 SPKR_R
+5V_RUN_PVDD_Lplace close to pin41 place close to pin46 BEEP_R

100P_0402_50V8J
LA12 BLM15PX600SN1D_2P 1 2

10K_0402_5%

100P_0402_50V8J
HCB2012KF-121T50_2P

1
0.1U_0201_10V6K

10U_0603_10V6M

0.1U_0201_10V6K

10U_0603_10V6M

0.1U_0201_10V6K

10U_0603_10V6M

0.1U_0201_10V6K

10U_0603_10V6M

@ CA72

10K_0402_5%
1W x 1ch, 4ohm (Transducer spec is 8Ohm/0.5Watt per unit, there are two transducer units in one speaker box.) 1 1 1 1 1 600 Ohm/2A 1 1

1
+3.3V_RUN_AUDIO_DVDD

CA45

CA47

CA60

RA51

@ CA62
2 1
Only Merion14 support 3 vendor
Internal Speakers Header

CA55

CA56

CA46

CA48

CA59

RA45
LA14 BLM15PX600SN1D_2P

2
CONN@

2
2 2 2 2 2 2 2

0.1U_0201_10V6K

10U_0603_10V6M
40 mils trace keep 20 mil spacing JSPK1

2
10 1

2
GND2

1
CA10

CA61
9
INT_SPK_L+ EMI@ LA6 1 2 BLM15PD800SN1D_2P INT_SPKR_L+ 8 GND1
INT_SPK_L- EMI@ LA7 1 2 BLM15PD800SN1D_2P INT_SPKR_L- 7 8

2
INT_SPK_R+ EMI@ LA8 1 2 BLM15PD800SN1D_2P INT_SPKR_R+ 6 7 2
INT_SPK_R- INT_SPKR_R- 6
EMI@ LA9 1 2 BLM15PD800SN1D_2P
SMART_SPK_DET0# 4
5
5
Swap JSPK1 for correct routing place close to pin18
<12> SMART_SPK_DET0# SMART_SPK_DET1# 3 4
D <9> SMART_SPK_DET1# 2 3 D
1 2
1 place close to pin3 RF Request
+5V_RUN_AUDIO +1.8V_RUN +5V_RUN_AUDIO
@EMI@ CA22

@EMI@ CA23

@EMI@ CA19

@EMI@ CA24

ACES_50278-00801-001
1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

place close to pin40 LA5 place close to pin20

1

+3.3V_RUN +3.3V_RUN +VDDA_AVDD1 1 2 +1.8V_RUN_AUDIO @ RA3 1 2 0_0603_5%

Link ACES_50278-00801-001 DONE 0809 BLM15PX600SN1D_2P
INT_SPKR_L+

10U_0603_10V6M

0.1U_0201_10V6K

10U_0603_10V6M

0.1U_0201_10V6K
2

INT_SPKR_L-
1 1

1
CA8

CA58

CA57
CA9

12P_0402_50V8J
RF@ CA63

68P_0402_50V8J
RF@ CA64
@ESD@ RA66 RA67 1 1

2
2

3
DA6 10K_0402_5% 10K_0402_5% 2 2

L03ESDL5V0CG3-2_SOT-523-3
2

2
SMART_SPK_DET0# SMART_SPK_DET1#
2 2
Close to UA1
Vendor1 Vendor2 Vendor3
Smart Amp Vendor FG VECO Zylux

1
SMART_SPK_DET0# UA1
(PCH_GPP_G7) High Low High

1
SMART_SPK_DET1# 34 AUD_PC_BEEP 2 1 SPKR_R 1 2
(PCH_GPP_C22) High High Low 6 PCBEEP CA27 2 1 0.1U_0402_25V6 BEEP_R RA12 1 2 1K_0402_5%
SPKR <12>
I2C DATA BEEP <58>
30 RING2 CA28 0.1U_0402_25V6 RA13 1K_0402_5%
7 MIC2-L/RING2 SLEEVE/RING2 please keep 40 mils trace width
Close to UA1 pin14 I2C CLK 31 SLEEVE
15 MIC2-R/SLEEVE AUD_HP_OUT_L/ AUD_HP_OUT_Rplease keep 15 mils trace width
HDA_BIT_CLK_R DMIC_CLK0 INT_SPKR_R+ <12> HDA_SYNC_R SYNC LINE1_L HP_OUT_L
36 2 1
INT_SPKR_R- HDA_BIT_CLK_R LINE1-L
100P_0402_50V8J

14 CA43 10U_0603_10V6M
<12> HDA_BIT_CLK_R BCLK LINE1_R HP_OUT_R RF Request
RF@ RA17

RF@ CA54

35 2 1
LINE1-R
1

HDA_SDOUT_R +1.8V_RUN_AUDIO +1.8V_RUN

33_0402_5%

17 CA44 10U_0603_10V6M
<12> HDA_SDOUT_R SDATA-OUT INT_SPK_L+
@ESD@ 42
SPK-OUT-L+
2

3
DA7 13
2

DC DET/EPAD INT_SPK_L-

L03ESDL5V0CG3-2_SOT-523-3
43
2

3
1 2 HDA_SDIN0_R 16 SPK-OUT-L-
2

<12> HDA_SDIN0 RA9 33_0402_5% SDATA-IN 44 INT_SPK_R-

SPK-OUT-R-
10P_0402_50V8J
RF@ CA33

RF@ CA69
Place RA9 close to codec 11
I2S-MCLK INT_SPK_R+

33P_0402_50V8J
place close to UA1 pin5 45
SPK-OUT-R+
1

12P_0402_50V8J
RF@ CA65

68P_0402_50V8J
RF@ CA66
10 1 1 1
I2S-BCLK HP_OUT_L AUD_HP_OUT_L
1

27 1 2
HPOUT-L 16.2_0402_1% RA7
2

9 26 HP_OUT_R 1 2 AUD_HP_OUT_R
C I2S-OUT HPOUT-R 2 2 2 C
16.2_0402_1% RA8
12
I2S-LRCK

EMI@

EMI@
8
I2S-IN

330P_0402_50V8J

330P_0402_50V8J
1 1
1
I2S-EN/SPDIF-OUT/GPIO2/DMIC-DATA34/DMIC-CLK-IN

CA73

CA74
100K_0402_5% 1 2 RA52
4
<38> DMIC0 GPIO0/DMIC-DATA12 2 2
DMIC_CLK0 2 1 DMIC_CLK0_CODEC 5
+3.3V_RUN_AUDIO <38> DMIC_CLK0 22_0402_5% RA14 EMI@ GPIO1/DMIC-CLK
+3.3V_RUN_AUDIO 10K_0402_5% 2 1 RA18 PD# 2
PDB
Place closely to Pin 48. 1U_0201_6.3V6M 2 1 CA31 48
RF Request
100K_0402_1% 200K_0402_1%
1

AUD_SENSE_A JD1
2 1 AUD_SENSE_B 47 +3.3V_RUN_AUDIO
RA59

+3.3V_RUN_AUDIO JD2
100K_0402_1% RA61
2 1 1031 change
2.2U_0402_6.3V6M CA35
2

AUD_SENSE_A 2 1 38
VREF
0.1U_0402_25V6

100K_0402_5% RA44
1

@ CA41

2 1 39
10U_0603_10V6M CA51 LDO1-CAP 1 2
RA60

+RTC_CELL
@ RA54 2 0_0402_5%

12P_0402_50V8J
RF@ CA67

68P_0402_50V8J
RF@ CA68
2 1 32 33 1 +3.3V_RTC_LDO 1 1
2

10U_0603_10V6M CA25 MIC2-CAP 5VSTB/AUX MODE @ RA53 0_0402_5%

40 +VDDA_AVDD1
2

SLEEVE 2 1 +MIC2-VREFO-R 29 AVDD1

AUD_HP_NB_SENSE
Add for solve MIC2-VREFO-R +1.8V_RUN_AUDIO
2.2K_0402_5% RA6 20 2 2
pop noise and CPVDD/AVDD2
RING2 2 1 +MIC2-VREFO-L 28
detect issue 2.2K_0402_5% RA5 MIC2-VREFO-L 3 +3.3V_RUN_AUDIO_DVDD
DVDD
18 +3.3V_RUN_AUDIO_IO
DVDD-IO
CPVEE 25 41 +5V_RUN_PVDD_L
CPVEE PVDD1
CBN 24 46
CBN PVDD2
CBP 23 49
CBP G
CLASS-D POWER DOWN CONTROL CIRCUIT
2 1 21 37
10U_0603_10V6M CA52 LDO2-CAP AVSS1
B 2 1 19 22 B
10U_0603_10V6M CA53 LDO3-CAP AVSS2 Add this Filter to avoid other
components/chips be influenced
HP-Out-Right Nokia-MIC

ALC3254-VA3-CG_MQFN48_6X6
HP-Out-Lef t iPhone-MIC
@ RA48 1 2 0_0201_5%

CBP CPVEE
@ DA8 1 2
<58> NB_MUTE#
1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

RB751S-40_SOD523-2 PD# 1 1 1 1

680P_0402_50V7K
@ESD@ CA13
1
CA29

CA76

CA49

CA77

1 2 Global Headset
<12> HDA_RST#_R
@ RA50 0_0201_5%
HDA_Link is 3.3V,no need level shift circuit 2 2 2 2
2 Universal Jack
CBN
JHP1 CONN@
Place CA29/CA76 close to Codec 7
RING2 ESD@ LA10 1 2 BLM15PX330SN1D_2P RING2_R 4 GND
AUD_HP_OUT_L EMI@ LA15 1 2 BLM15PX330SN1D_2P AUD_HP_OUT_L1 1 #4 G/M
0809 change to 1U 0201*2 for MLCC shortage #1 L/R Normal
only Samsung,Taiyo,Murata can use Open
5
JUMP@ #5
Power sequence +5V_RUN_AUDIO(501us) > +3.3V_RUN_AUDIO(1204 us) > +1.5V_RUN PJP17
1 2 AUD_HP_NB_SENSE 6
+5V_RUN +5V_RUN_AUDIO #6 AGND
+5V_RUN_AUDIO PAD-OPEN1x2m AUD_HP_OUT_R EMI@ LA16 1 2 BLM15PX330SN1D_2P AUD_HP_OUT_R1 2
2.5A SLEEVE ESD@ LA11 1 2 BLM15PX330SN1D_2P SLEEVE_R 3 #2 R/L
JUMP@ #3 M/G
Reserve for support D3 cold
1

680P_0402_50V7K
680P_0402_50V7K

680P_0402_50V7K

680P_0402_50V7K
@JUMP@ PJP18 SINGA_2SJ3095-085111F

ESD@

EMI@

EMI@

ESD@
PJP15 1 2 ESD@ ESD@ ESD@
+3.3V_RUN +3.3V_RUN_AUDIO

3
PAD-OPEN1x1m DA1 DA2 DA3
+5V_RUN Link 2SJ3095-085111F done 0123

AZ5123-02S.R7G_SOT23-3

AZ5125-02S.R7G_SOT23-3

AZ5123-02S.R7G_SOT23-3

680P_0402_50V7K
@ESD@ CA12
PAD-OPEN1x1m
500mA 2 2 2 1 1

CA1

CA2

CA3

CA4
@ UZ5
2

1 14 +5V_RUN_AUDIO_UZ5 1 2
2 VIN1_1 VOUT1_2 13 @ CZ125 0.1U_0201_10V6K 1 1 1 2 2
VIN1_2 VOUT1_1
A 3 12 1 2 place at AGND and DGND plane A
<12> AUD_PWR_EN ON1 CT1 220P_0402_50V7K
@ CZ126

1
4 11 1 2
+5V_ALW VBIAS GND @ RA35 0_0402_5%
5 10 1 2
ON2 CT2 @ CZ127 1000P_0402_50V7K JUMP@
6 9 @JUMP@ PJP16 1 2 PJP19
+3.3V_RUN VIN2_1 VOUT2_2 +3.3V_RUN_AUDIO_UZ5
7 8 1 2 @ RA36 0_0402_5% 1 2
VIN2_2 VOUT2_1 +3.3V_RUN_AUDIO
15 PAD-OPEN1x1m

EM5209VF_SON14_2X3
GPAD PAD-OPEN1x1m
1 2 @ RA37
1 2
0_0402_5%
DELL CONFIDENTIAL/PROPRIETARY

https://Dr-Bios.com
@ CZ128 0.1U_0201_10V6K
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Codec ALC3204
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 56 of 109
5 4 3 2 1
 5 4 3 2 1

D D

Reserve
C C

B B

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Audio Ampfilper
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 57 of 109
5 4 3 2 1
 5 4 3 2 1

+3.3V_ALW
+3.3V_FPBTN
1 2 +RTC_CELL_VBAT UPD1_SMBDAT 1 2
+RTC_CELL
@ RE32 0_0402_5% RE302 2.2K_0402_5%
UPD1_SMBCLK

0.1U_0201_10V6K
1 1 2
FPR_SSO_EN#

CE11
1 2 RE303 2.2K_0402_5%
RE706 10K_0402_5% UPD1_SMBINT# 1 2
+3.3V_ALW_UE1 FPR_UEFI_MGMT#
JUMP@ 1 2 RE91 100K_0402_5%

1U_0201_6.3V6M
2 BSMB_W P_INT#

0.1U_0201_10V6K

0.1U_0201_10V6K
PJP22 RE707 10K_0402_5% 1 2
1 2 FPR_LOW _PW R_MODE# 1 2 @ RE92 100K_0402_5%
+3.3V_ALW 1 1 1 PBAT_CHARGER_SMBDAT

10U_0402_6.3V6M
RE708 10K_0402_5% 1 2

CE14
FPR_SCAN_INT#

CE13

CE23
1 PAD-OPEN1x1m 1 2 RE37 2.2K_0402_5%
RE709 100K_0402_5% PBAT_CHARGER_SMBCLK 1 2
2 2 2

CE16
RE43 2.2K_0402_5%
W P_GPU_SMDAT 1 2
2 UE1 @ RE524 2.2K_0402_5%
F2 TYPEC_ID W P_GPU_SMCLK 1 2
GPIO033/RC_ID0 SYSTEM_ID TYPEC_ID <59>
A2 J10 @ RE525 2.2K_0402_5%
+3.3V_ALW_UE1 VBAT GPIO034/RC_ID1/SPI0_CLK BOARD_ID SYSTEM_ID <59> SIO_SLP_SUS#_R
J13 BOARD_ID <59>
1 2
B7 GPIO036/RC_ID2/SPI0_MISO E7 GPIO003 1 NDS3@ RE561 100K_0402_5%
D 2 1 VTR_ANALOG GPIO003/SMB00_DATA/SPI0_CS# D7 GPIO004 1 PAD~D @ T390 Follow KW13 MLK NGFF_CONFIG_1 1 2 D
+3.3V_ALW_UE1 GPIO004/SMB00_CLK/SPI0_MOSI PAD~D @ T391
0.1U_0201_10V6K

0.1U_0201_10V6K

22U_0402_6.3V6M

0.1U_0201_10V6K
100_0402_1% RE314 K2 RE562 2.2K_0402_5%
VREF_ADC G3 RUNPW ROK
1 1 1 1 +3.3V_EC_PLL GPIO057/VCC_PWRGD GPS_DISABLE#
CE19

CE20

@ CE17
F1 H5
VTR_PLL GPIO060/KBRST/48MHZ_OUT GPS_DISABLE# <52>

CE18
G11
GPIO104/UART0_TX HOST_DEBUG_TX <79> NGFF_CONFIG_2
H1 G12 ME_FWP <79> 1 2
2 2 2 2 VTR_REG GPIO105/UART0_RX B13 RTCRST_ON_POW ER RE803 100K_0402_5%
G8 GPIO127/A20M/UART0_CTS# F10 UPD1_SMBINT# NGFF_CONFIG_0 1 2
+VSS_PLL M9 VTR1 GPIO225/UART0_RTS# UPD1_SMBINT# <44> RE804 100K_0402_5%
+3.3V_ALW_UE1 VTR2 PCIE_W AKE#_R NGFF_CONFIG_3
close to pin G8/M9 N5 N13 1 2
+3.3V_ALW_UE1 +1.8V_PRIM_VTR3 VTR3 GPIO025/TIN0/nEM_INT/UART_CLK PCIE_WAKE#_R <59>
N12 RE805 100K_0402_5%
PCH_DPW ROK_EC GPIO026/TIN1 PTP_DISABLE# <63>
0.1U_0201_10V6K
1 <11> 1 2 F8 M11
PCH_DPWROK RUN_ON_EC GPIO020 GPIO027/TIN2 FPR_PWR_EN# <66> USB_PW R_EN2#
DS3@ RE536 0_0201_5% E8 H9 1 2
RF Request <59> RUN_ON_EC SIO_EXT_W AKE#_EC GPIO045 GPIO030/TIN3 FPR_SSO_EN# <66>
CE15

1 2 M12 @ RE806 100K_0402_5%

+3.3V_ALW <9> SIO_EXT_WAKE# BT_RADIO_DIS# GPIO120 VGA_IDENTIFY USB_POW ERSHARE_EN#
@ RE703 0_0201_5% C2 L9 1 2
2 <52> BT_RADIO_DIS# GPIO166 GPIO017/GPTP-IN5
F9 M10 RE807 100K_0402_5%
<83,84> PBAT_PRES# SIO_SLP_SUS#_R GPIO175 GPIO151/ICT4 NGFF_CONFIG_1 <52,54> USB_PW R_EN1#
1 2 N4 N9 1 2
<11> SIO_SLP_SUS# PANEL_MONITOR GPIO230 GPIO152/GPTP-OUT3 NGFF_CONFIG_0 <52>
DS3@ RE349 43K_0402_1% M8 RE808 100K_0402_5%
<79> PANEL_MONITOR GPIO231 USB_POW ERSHARE_VBUS_EN 1
K8 C11 2
<11> AC_PRESENT GPIO233 GPIO156/LED0 BREATH_LED# <64>
Close to pin H1 D10 RE809 100K_0402_5%
GPIO157/LED1 BAT1_LED# <64>
<8>
SML1_SMBDATA E11 D11 AC_DIS
GPIO007/SMB03_DATA/PS2_CLK0B GPIO153/LED2 BAT2_LED# <64> 1 2
D8 E1
<8> SML1_SMBCLK W W AN_W AKE# GPIO010/SMB03_CLK/PS2_DAT0B GPIO226/LED3 LCD_VCC_TEST_EN <38> @ RE83 100K_0402_5%
12P_0402_50V8J
RF@ CE59

68P_0402_50V8J
RF@ CE60

1 1 M13 GPS_DISABLE#
<52> WWAN_WAKE# FPR_LOW _PW R_MODE# K12 GPIO110/PS2_CLK2 1 2
E5
<66> FPR_LOW_PWR_MODE# W LAN_W IGIG60GHZ_DIS# L13 GPIO111/PS2_DAT2 GPIO005/SMB01_DATA/GPTP-OUT4 USH_EXPANDER_SMBDAT <66> RE12 100K_0402_5%
B3 W LAN_W IGIG60GHZ_DIS#
<52> WLAN_WIGIG60GHZ_DIS# GPIO112/PS2_CLK1A GPIO006/SMB01_CLK/GPTP-OUT7 VCCDSW _EN USH_EXPANDER_SMBCLK <66> 1 2
K11 M7
2 2 <11,79> SIO_PWRBTN# SLP_W LAN#_GATE_R GPIO113/PS2_DAT1A GPIO012/SMB07_DATA/TOUT3 3.3V_W IGIG_EN VCCDSW_EN <11> RE8 100K_0402_5%
1 2 K10 M4 1 W W AN_W AKE#
<78> SLP_WLAN#_GATE GPIO114/PS2_CLK0A/nEC_SCI GPIO013/SMB07_CLK/TOUT2 PBAT_CHARGER_SMBDAT PAD~D @ T399 VCCDSW _EN 1 2
@ RE552 0_0201_5%<59> N11 M3
LID_CL_SIO# GPIO115/PS2_DAT0A GPIO130/SMB10_DATA/TOUT1 PBAT_CHARGER_SMBCLK PBAT_CHARGER_SMBDAT <83,84> RE38 10K_0402_5%

0.1U_0402_25V6
E10 N2 LED_MASK#
<63> CLK_TP_SIO_I2C_DAT GPIO154/SMB02_DATA/PS2_CLK1B GPIO131/SMB10_CLK/TOUT0 PBAT_CHARGER_SMBCLK <83,84> 1 2
C12 N10
<63> DAT_TP_SIO_I2C_CLK GPIO155/SMB02_CLK/PS2_DAT1B GPIO132/SMB06_DATA LED_MASK# NGFF_CONFIG_2 <52> RE21 10K_0402_5%

@ CE66
A12 LED_MASK# <64> THERMTRIP1# 1 2

1
JTAG_TDI E9 GPIO140/SMB06_CLK/ICT5 B6 WP_GPU_SMDAT_R @ RE817 1 2 0_0201_5%
<79> JTAG_TDI JTAG_TDO GPIO145/SMB09_DATA/JTAG_TDI GPIO141/SMB05_DATA/SPI1_CLK/UART0_DCD# W P_GPU_SMCLK_R WP_GPU_SMDAT <92> RE301 10K_0402_5%
F6 F7 @ RE818 1 2 0_0201_5% PCIE_W AKE#_R
<79> JTAG_TDO JTAG_CLK GPIO146/SMB09_CLK/JTAG_TDO GPIO142/SMB05_CLK/SPI1_MOSI/UART0_DSR# UPD1_SMBDAT WP_GPU_SMCLK <92> 1 2
C8 B4
<79> JTAG_CLK

2
RE35
JTAG_TMS C5 GPIO147/SMB08_DATA/JTAG_CLK GPIO143/SMB04_DATA/SPI1_MISO/UART0_DTR# C3 UPD1_SMBCLK UPD1_SMBDAT <44> FPR_PW R_EN# 1 2 10K_0402_5%
<79> JTAG_TMS JTAG_RST# GPIO150/SMB08_CLK/JTAG_TMS GPIO144/SMB04_CLK/SPI1_CS#/UART0_RI# UPD1_SMBCLK <44>
JUMP@ G13 RE704 10K_0402_5%
PJP20 JTAG_RST# J4 I_BATT_R RE64 1 2 300_0402_5%
I_BATT <84> BC_DAT_ECE1117 1 2
1 2 E3 GPIO200/ADC00 J5 I_SYS_R RE312 1 2 300_0402_5%
1218
+1.8V_PRIM +1.8V_PRIM_VTR3
Delete RE100 and Change net name
<77> TACH_FAN1
D1 GPIO050/FAN_TACH0/GTACH0 GPIO201/ADC01 J6 NB_MODE# 1
I_SYS <84,88>
W W AN_RADIO_DIS#
RE365 100K_0402_5%
1 <42,44> TBT_RESET_N_EC LCD_TST GPIO051/FAN_TACH1/GTACH1 GPIO202/ADC02 TOUCHPAD_INTR#_R PAD~D @ T348 PRIM_PW RGD 1 2
PAD-OPEN1x1m from CNVI_RF_RESET to CNVI_EN# M2 G2 @ RE318 1 2 0_0201_5%
<38> LCD_TST GPIO052/FAN_TACH2/LRESET# GPIO203/ADC03 USH_PW R_STATE#_R TOUCHPAD_INTR#
<14,63> RE10 100K_0402_5%

0.1U_0402_25V6
CE22 <77> PWM_FAN1 L10 H2 @ RE608 2 1 0_0201_5% BT_RADIO_DIS#
CNV_DET#_EC GPIO053/PWM0/GPWM0 GPIO204/ADC04 USB_POW ERSHARE_VBUS_EN USH_PWR_STATE# <66> 1 2
0.1U_0201_10V6K L11 J2
C 2 <52> CNV_DET#_EC PCH_RSMRST# GPIO054/PWM1/GPWM1 GPIO205/ADC05 USB_POW ERSHARE_EN# USB_POWERSHARE_VBUS_EN <71> FPR_DET# RE11 100K_0402_5% C

@ CE68
M5 J3 1 2
<63,79>
PCH_RSMRST# GPIO055/PWM2/SHD_CS#/(RSMRST#) GPIO206/ADC06 USB_POWERSHARE_EN# <71>

1
CE21 PS_ID J8 K3 USB_PW R_EN1# RE606 100K_0402_5%
1 <82> PS_ID GPIO056/PWM3/SHD_CLK GPIO207/ADC07 AUX_EN_W OW L USB_PWR_EN1# <72> PRIVACY_ENABLE
0.1U_0201_10V6K N1 D3 1 2
<38> BIA_PWM_EC FPR_SCAN_INT# GPIO001/PWM4 GPIO210/ADC08 LOM_CABLE_DETECT# AUX_EN_WOWL <78>
L8 D2 @ RE820 100K_0402_5%
<66> FPR_SCAN_INT#

2
HW _ACAVIN_NB N6 GPIO002/PWM5 GPIO211/ADC09 E2 BC_INT#_ECE1117 SSD_SCP# 1 2
2 <82,84> HW _ACAVIN_NB GPIO014/PWM6/GPTP-IN6 GPIO212/ADC10 USB_PW R_EN2# BC_INT#_ECE1117 <63>
Close to pin N5 J9 G5 @ RE821 100K_0402_5%
<38> PANEL_BKEN_EC BEEP H11 GPIO015/PWM7 GPIO213/ADC11 F5 PRIVACY_ENABLE PTP_DISABLE# 1 2
<56> BEEP FPR_DET# D9 GPIO035/PWM8/CTOUT1 GPIO214/ADC12 K4 DCIN2_EN @ RE601 1 2 0_0201_5% PRIVACY_ENABLE <38> RE605 100K_0402_5%
<66> FPR_DET# AC_DIS GPIO133/PWM9 GPIO215/ADC13 DCIN2_EN_R <82> ACAV_IN
<84> AC_DIS H12 L1
GPIO134/PWM10/UART1_RTS# GPIO216/ADC14 LAN_W AKE# PCH_PCIE_WAKE# <11,42,59> +RTC_CELL

0.1U_0402_25V6
G10 L3
<66> BCM5882_ALERT# GPIO135/UART1_CTS# GPIO217/ADC15 LAN_WAKE# <11>
MSCLK H10
<79> MSCLK GPIO170/TFDP_CLK/UART1_TX CV2_ON_R VCI_IN1#

@ CE67
MSDATA G9 H8 RE539 1 2 100_0402_5% 1 2
<79> MSDATA GPIO171/TFDP_DATA/UART1_RX GPIO222/SER_IRQ CV2_ON <66>

1
J7 3.3V_TS_EN RE507 100K_0402_5%
+3.3V_ALW GPIO223/SHD_IO0 SSD_SCP# 3.3V_TS_EN <38> VCI_IN2#
+3.3V_ALW A4 L6 1 2
<56> NB_MUTE# EN_INVPW R GPIO022/GPTP-IN0 GPIO224/GPTP-IN4/SHD_IO1 PRIM_PW RGD SSD_SCP# <68>
B2 L7 1 2 1.0V_PRIM_PWRGD <87> RE508 100K_0402_5%
<38> EN_INVPWR

2
2 1 LOM_CABLE_DETECT# RESET_IN# GPIO023/GPTP-IN1 GPIO227/SHD_IO2 VBUS2_ECOK@ RE361 VCI_IN3#
RE362 1 2100K_0402_5% C1 M6 1 2 0_0201_5% 1 2
@ RE505 100K_0402_5% IMVP_VR_ON_EC N7 GPIO024/nRESETI GPIO016/GPTP-IN7/SHD_IO3/ICT3 @ RE603 0_0201_5% VBUS2_ECOK_R <82> RE822 100K_0402_5%
2 1 USH_DET# <59> IMVP_VR_ON_EC K9 GPIO031/GPTP-OUT1 D6 BGPO0 1
@ RE526 10K_0402_5% <66> FPR_UEFI_MGMT# N8 GPIO032/GPTP-OUT0 BGPO0 C7 PAD~D @ T341
ACAV_IN <79,84,91> I_BATT_R CE3 1 2 2200P_0402_50V7K
2 1 BCM5882_ALERT# <79> M_BIST GPIO040/GPTP-OUT2 GPIO164/VCI_OVRD_IN A5
RTD3_SELECT VCI_OUT ALWON <85>
RE532 4.7K_0402_5% F13 D5 RE59 close to UE1 at least 250mils I_SYS_R
<42> RTD3_SELECT GPIO121/PVT_IO0 GPIO163/VCI_IN0# VCI_IN1# POWER_SW_IN# <59,79> +PECI_VREF CE4 1 2 2200P_0402_50V7K
E13 B5 2 1
<82> AC_DISC# GPIO124/GPTP-OUT6/PVT_CS# GPIO162/VCI_IN1# VCI_IN2# +1.0V_VCCST
C13 D4 0_0402_5% @ RE59
<66> USH_DET# BSMB_W P_INT#_R GPIO125/GPTP-OUT5/PVT_CLK GPIO161/VCI_IN2# VCI_IN3#

0.1U_0201_10V6K
<92> BSMB_W P_INT# @ RE819 1 2 0_0201_5% E12 E4
GPIO126/PVT_IO3 GPIO000/VCI_IN3#

1
CV2_ON_R RTCRST_ON PRIVACY_ENABLE

CE25
1 2 F11 1 2
RE810 100K_0402_5% W W AN_RADIO_DIS# F12 GPIO122/BCM0_DAT/PVT_IO1 C6 RE802 1M_0402_5%
IMVP_VR_ON_EC <52> WWAN_RADIO_DIS# GPIO123/BCM0_CLK/PVT_IO2 GPIO165/32KHZ_IN/CTOUT0 3.3V_WWAN_EN <78> PCH_RSMRST#
1 2 D12 1 2
<63> BC_DAT_ECE1117

2
RE811 100K_0402_5% D13 GPIO046/BCM1_DAT F3 32KHZ_OUT @ CE54 1 2 10P_0402_50V8J RE342 10K_0402_5%
<63> BC_CLK_ECE1117 GPIO047/BCM1_CLK GPIO221/GPTP-IN3/32KHZ_OUT
1 2 RUN_ON_EC +3.3V_ALW2 SYS_PW ROK 1 2
RE812 100K_0402_5% F4 RE56 10K_0402_5%
<52> NGFF_CONFIG_3 SYSPW R_PRES GPIO041/SYS_SHDN# +PECI_VREF I_SYS_R
@ RE57 2 1 1K_0402_5% B1 J11 1 2
1 2 TBT_RESET_N_EC K7 SYSPWR_PRES GPIO044/VREF_VTT K13 PECI_EC_R RE60 1 2 43_0402_5% @ RE313 10K_0402_5%
1031 change PECI_EC <14>
GPIO011/nSMI GPIO042/PECI_DAT/SB-TSI_DAT
1

RE95 100K_0402_5% @ RE602 1 2 0_0201_5% VBUS1_ECOK N3 J12 M3042_PCIE#_SATA LCD_TST 1 2

<82> VBUS1_ECOK_R GPIO021/LPCPD# GPIO043/SB-TSI_CLK REM_DIODE1_N M3042_PCIE#_SATA <10>
100K_0402_5%

K6 A8 CE24 1 2 2200P_0402_50V7K RE20 100K_0402_5%

<8,79> ESPI_RESET# ESPI_ALERT# GPIO061/LPCPD#/ESPI_RESET# DN1_DP1A REM_DIODE1_P REM_DIODE1_N EN_INVPWR
RE58

H7 A7 1 2
<8> ESPI_ALERT# GPIO063/SER_IRQ/ESPI_ALERT# DP1_DN1A REM_DIODE2_N REM_DIODE1_P REM_DIODE1_N <59> RE55
K1 A10 CE26 1 2 2200P_0402_50V7K 100K_0402_5%
GPIO064/LRESET# DN2_DP2A REM_DIODE2_P REM_DIODE2_N REM_DIODE1_P <59>
G7 A9
REM_DIODE2_N <59>
2

+1.8V_PRIM_VTR3 <8,79> ESPI_CLK_5105 H6 GPIO065/PCI_CLK/ESPI_CLK DP2_DN2A B9 REM_DIODE2_P

<8,79> ESPI_CS# GPIO066/LFRAME#/ESPI_CS# DN3_DP3A REM_DIODE2_P <59>
K5 B8
<8,79> ESPI_IO0 GPIO070/LAD0/ESPI_IO0 DP3_DN3A REM_DIODE4_N +3.3V_RUN
L4 A11 CE27 1 2 2200P_0402_50V7K
<8,79> ESPI_IO1 GPIO071/LAD1/ESPI_IO1 DN4_DP4A
1

G6 B10 REM_DIODE4_P REM_DIODE4_N

B <8,79> ESPI_IO2 REM_DIODE4_N <59> B
@ RE823 L5 GPIO072/LAD2/ESPI_IO2 DP4_DN4A C10 +VR_CAP REM_DIODE4_P
<8,79> ESPI_IO3 ENABLE_DS# GPIO073/LAD3/ESPI_IO3 VIN VSET_5105 REM_DIODE4_P <59>
100K_0402_5% L2 C9 VSET_5105 <59>
SSD_SCP_PW R_EN M1 GPIO067/CLKRUN# VSET B11 3.3V_TS_EN 1 2
<78> SSD_SCP_PWR_EN RESET_OUT GPIO100/nEC_SCI VCP I_ADP <84>
@ RE548 1 2 0_0201_5% G4 H3 THERMTRIP2# @ RE547 100K_0402_5%

VSS_ANALOG
THERMTRIP2# <59>
2

SSD_SCP_PW R_EN <11,79> SYS_PWROK @ RE600 1 2 0_0201_5% DCIN1_EN L12 GPIO106/PWROK GPIO103/THERMTRIP2# B12 THERMTRIP1#
<82> DCIN1_EN_R GPIO107/nSMI THERMTRIP1# H13 PROCHOT#_R1 1 2 +3.3V_ALW
VSS_ADC

VSS_PLL
VR_CAP
MEC_XTAL1 A1 GPIO160/PWM11/PROCHOT# RE288 100_0402_5% PROCHOT# <14,84,88>
MEC_XTAL2_R A3 XTAL1
VSS1

VSS2

VSS3

+3.3V_ALW
XTAL2 VGA_IDENTIFY 1 2
100K_0402_5%

RE84 100K_0402_5%
2

MEC5105_W FBGA169_11X11 VGA_IDENTIFY 1 2

A6

A13

E6

H4

J1

C4

G1
RE63

@ RE85 100K_0402_5%
+1.8V_PRIM_VTR3
+VR_CAP

+VSS_PLL
1

1U_0201_6.3V6M

JTAG_RST# RE549 1
VGA_IDENTIFY
CE31

100K_0402_5% WHL Supprot NDS3 only

+RTC_CELL_PCH +RTC_CELL
Discrete 0
1

2 QE15
2

Deep Sleep support

1U_0201_6.3V6M

ENABLE_DS# LP2301BLT1G_SOT23-3 UMA 1

1

1
@SHORT PADS~D
JTAG1 @

100_0402_1%

1
@ RE65

1 3

S
non Deep Sleep 1
CE30

1U_0201_6.3V6M

10K_0402_5%
@ RE550
Deep Sleep 0 Follow ARD 0.98

1
2 100K_0402_5% 1

G
2

2
RE546
CE63
2

+RTC_CELL_PCH +RTC_CELL

Merion Limit height

2
2

2 DE2

2
QE2 change to SB000014O00 H=0.6mm(MAX) 2 1 1 2
@RE551 0_0402_5%
RB751S-40_SOD523-2
+3.3V_ALW 1 RE94
D RE543 1 2
QE17 2 RTCRST_ON_POW ER_R1 1 2 RTCRST_ON_POW ER_R 1 2 RTCRST_ON_POW ER 75_0402_5% PCH_RTCRST# <11,79>
For EMI request
100K_0402_5%
2

1
L2N7002W T1G_SC-70-3 G @ RE565 0_0201_5% D
MEC_XTAL2_R ESPI_CLK_5105 RTCRST_ON

0.1U_0402_25V6
S 1M_0402_5% 2 QE12
3
RE68

22P_0402_50V8J

100K_0402_5%
G L2N7002W T1G_SC-70-3

1
@ CE64
S

3
33_0402_5%
1

1
RE541
RE93
@EMI@

A A
1
1

QE2

CE65
100K_0201_5%
RE350

S1
@ RE290 2
32 KHz Clock <17,59,78,87> RUN_ON
2

2
0_0201_5% G1
D1 6 RUN_ON#

2
4
2

RUN_ON# 5 S2
2

33P_0402_50V8J

G2
D2
YE1
PJX138K_SOT563-6
@EMI@

3
1

MEC_XTAL1 1 2 MEC_XTAL2 8/28 schematic review

1 2
CE57

1219 Change +3.3V_RUN

DELL CONFIDENTIAL/PROPRIETARY
10P_0402_50V8J

10P_0402_50V8J

RE67 10K_0402_5%
2

32.768KHZ_9PF_X1A000141000200 RUNPWROK
1

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Compal Electronics, Inc.
CE28

CE29

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
2

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT EC MEC5105
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 58 of 109
5 4 3 2 1
 5 4 3 2 1

For Merion UMA

+RTC_CELL
PCIE_WAKE# <42,52,68>

1
100K_0402_5%
@ CE10

RE31
1 2 1 2 1 2
<58> PCIE_WAKE#_R PCH_PCIE_WAKE# <11,42,58>
@ RE275 0_0201_5% @ RE274 0_0201_5%
0.1U_0201_10V6K

2
D D
1 2 Stuff RE275 and no stuff RE274 keep E5 design
<58,79> POWER_SW_IN# POWER_SW#_MB <66,77,79>
RE33 1K_0402_5% Stuff RE274 and no stuff RE275 to save two GPIOs on EC(PCH_PCIE_WAKE# should be output with OD)

2.2U_0402_6.3V6M
1

CE12
2 1
2 0_0201_5% @ RE304
Merion Limit height
1031 change
+3.3V_ALW @ CE53
UE4 change to SA00007YE00 H=0.4mm(MAX)
+3.3V_ALW 1 2
+3.3V_ALW

100K_0402_5%
1
RE25
0.1U_0201_10V6K UE4

5
1 6
IMVP_VR_ON_EC 1 NC1 VCC

P
<58> IMVP_VR_ON_EC B IMVP_VR_ON
4 2 5
RE26 SIO_SLP_S3# 2 O A NC2
<11,17,42,59,79> SIO_SLP_S3#

2
A

G
LID_CL_SIO# 2 1 UE3 3 4
<58> LID_CL_SIO# LID_CL# <64> GND Y VCCST_PWRGD <11,79>

.047U_0402_16V7K
MC74VHC1G08DFT2G_SC70-5

3
10_0402_5% 74AUP1G07FZ4-7_X2-DFN1410-6

CE8
RF Request

2
IMVP_VR_ON <88>
+3.3V_ALW 2 1
0_0201_5% @ RE280
6/8 Change to SA00007WE00 DII

68P_0402_50V8J
1
RUN_ON_EC 2 1

RF@ CE61
<58> RUN_ON_EC RUN_ON <17,58,78,87>
0_0201_5% @ RE292
2

+3.3V_ALW @ CE52

1 2

0.1U_0201_10V6K

5
1

P
C B C
4
2 O
A

G
UE5
MC74VHC1G08DFT2G_SC70-5

3
+3.3V_ALW
+3.3V_ALW
+3.3V_ALW

1
1

1
RE300
RE343 RE79 33K_0402_5%
130K_0402_5% 4.3K_0402_1%

2
<58> SYSTEM_ID

2
<58> TYPEC_ID <58> BOARD_ID 0212 change

1
1

1
CE47
CE62 CE40 4700P_0402_25V7K

2
4700P_0402_25V7K 4700P_0402_25V7K

2
RE343 CE62 REV RE79 CE40 REV RE300 CE47 PANEL SIZE
240K 4700p Single Port ACE w/o AR 240K 4700p X00 240K 4700p 11"
Single Port ACE w/AR
* 130K 4700p 130K 4700p X01 130K 4700p 12"
62K 4700p Dual Port ACE w/o AR 62K 4700p X02 62K 4700p 13"
33K 4700p Dual Port ACE w/AR 33K 4700p X03 * 33K 4700p 14"
8.2K 4700p Dual Port ACE (w/AR +w/o AR) 8.2K 4700p reserved 8.2K 4700p 15"
4.3K 4700p * 4.3K 4700p A00 4.3K 4700p 17"
B RE69 2K 4700p 2K 4700p 2K 4700p 15P B
1 2
+1.0VS_VCCIO +3.3V_ALW THERMTRIP2# <58>
1K 4700p 1K 4700p 1K 4700p
SIO_SLP_S3# 8.2K_0402_5%
<11,17,42,59,79> 1
LMBT3904WT1G_SC70-3
2

CE36
TYPEC_ID rise time is measured from 0%~63.2%. BOARD_ID rise time is measured from 0%~63.2%. SYSTEM_ID rise time is measured from 0%~63.2%.
G

C 0.1U_0201_10V6K
2
QE4

1 3 1 2 2
RE70 2.2K_0402_5% B VSET_5105
D

+1.0V_VCCST E VSET_5105 <58>

3

0.1U_0402_25V6
@ QE11

1
1.58K_0402_1%
L2N7002W T1G_SC-70-3

1
1 2

CE38

RE77
@ RE90 0_0402_5%
<14,23,24> H_THERMTRIP#

2
Thermal diode mapping
5085 Channel Locat i on Rest=1.58K , Tp=96 degree???
Place under CPU Rest=1.33K , Tp=93 degree
Place CE35 close to the QE3 as possible
DP1/DN1 CPU (QE3)
REM_DIODE1_P <58>
100P_0402_50V8J

DP2/DN2 2280 SSD (QE5)

2

1
@ CE35

C
DN2a/DP2a DDR (QE7) 2
1

B
E QE3
3

DP3/DN3 NA LMBT3904W T1G_SC70-3

REM_DIODE1_N <58>
DP4/DN4 CPU VR (QE6)
DP2/DN2 for WiGig on QE5, place QE5 close
to WiGig and CE37 close to QE5
DP4/DN4 for Skin on
A QE6, place QE6 close to DN2a/DP2a for DDR on QE7, place QE7 close A
Vcore VR choke. to DDR and CE46 close to QE7
REM_DIODE4_P <58> REM_DIODE2_P <58>
LMBT3904WT1G_SC70-3
100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J
2

1
@CE39

C E C
1

1
@ CE46

@ CE37

2 B
2 2
B B
DELL CONFIDENTIAL/PROPRIETARY
1

E QE6
C
QE7 E QE5
3

LMBT3904W T1G_SC70-3 LMBT3904W T1G_SC70-3

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Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
REM_DIODE4_N <58> REM_DIODE2_N <58>
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT MEC5105 support
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 59 of 109
5 4 3 2 1
 5 4 3 2 1

D D

Reserve
C C

B B

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Secure & Reset IC
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 60 of 109
5 4 3 2 1
 5 4 3 2 1

1K 2.2K
Merion SMBus Block Diagram +3.3V_ALW_PCH +3.3V_RUN
1K 2.2K
CK14 MEM_SMBCLK
L2N7002DW1T1G DDR_XDP_WAN_SMBCLK 253
SMB MEM_SMBDATA DIMMA
CH15 L2N7002DW1T1G DDR_XDP_WAN_SMBDAT 254 A0h
@499
253

+3.3V_ALW_PCH 254 DIMMB

D @499 A2h D

CH14 SML0_SMBCLK

SML 0 CF15 SML0_SMBDATA

51
@1K XDP
53
WHL-U +3.3V_ALW_PCH
@1K
CN15 SML0B_SMBDATA

SML 0B SML0B_SMBCLK
CM15

SML 1

CM24 CN23
1K
C
SML1_SMBDATA C

SML1_SMBCLK
+3.3V_ALW_PCH
1K

E11 D8

03 03
0x46(8-bit)
2.2K
KBC @3.3K PD
TPS65982
2.2K +3.3V_ALW +3.3V_TBTA_FLASH
MEC 5106 @3.3K

C3 UPD1_SMBCLK B5
04
B4 UPD1_SMBDAT A5 I2C
04
F10 UPD1_SMBINT# B6

2.2K

+3.3V_ALW
2.2K
B B

B3
01 USH_EXPANDER_SMBCLK C9
E5 USH
01 USH_EXPANDER_SMBDAT C10

2.2K CV3 USH/B

+3.3V_TP
2.2K
02 C12 DAT_TP_SIO_I2C_CLK 2

02 E10 CLK_TP_SIO_I2C_DAT 3 TP

Only Merion14 @2.2K

+3.3V_ALW
@2.2K
WP_GPU_SMCLK
@100 ohm 4
05 F7 Reserved
05 B6 WP_GPU_SMDAT @100 ohm 5 Wireless Power
@100 ohm Connector
E12 BSMB_W P_INT# 6

2.2K 21
Charger
A 22 A
+3.3V_ALW
2.2K
10
100 ohm 4
N2 PBAT_CHARGER_SMBCLK
100 ohm 5
BATTERY
10 M3 PBAT_CHARGER_SMBDAT CONN DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

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PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
SMBus block diagram
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 61 of 109
5 4 3 2 1
 5 4 3 2 1

D D

Reserve
C C

B B

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
LEDs (Controller)
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 62 of 109
5 4 3 2 1
 5 4 3 2 1

RF Request
Touch Pad +3.3V_TP
KB_DET#
RF@ CZ84
1 2
68P_0402_50V8J

BC_INT#_ECE1117 1 2
1 @RF@ CZ85 68P_0402_50V8J
+3.3V_RUN +3.3V_TP
+3.3V_TP RF@CZ83 BC_DAT_ECE1117 1 2
JUMP@ 68P_0402_50V8J @RF@ CZ86 68P_0402_50V8J
PJP35 2
1 2 BC_CLK_ECE1117 1 2

4.7K_0402_5%

4.7K_0402_5%
D @RF@ CZ87 68P_0402_50V8J D

1
PAD-OPEN1x1m
DAT_TP_SIO_R

RZ18

RZ19
1 2
@RF@ CZ88 68P_0402_50V8J
PS2 CLK_TP_SIO_R 1 2

2
@RF@ CZ89 68P_0402_50V8J
2 1 DAT_TP_SIO_R
<58> DAT_TP_SIO_I2C_CLK
@ RZ22 0_0201_5%
2 1 CLK_TP_SIO_R
<58> CLK_TP_SIO_I2C_DAT
@ RZ23 0_0201_5%

10P_0402_50V8J

10P_0402_50V8J
1

1
I2C1_SDA_TP_R

CZ80

CZ81
2 1
@ RZ346 0_0201_5%
Keyboard
2

2
2 1 I2C1_SCK_TP_R CONN@
@ RZ347 0_0201_5% JKBTP1
KB_DET# 1
<12> KB_DET# 2 1
3 2
I2C From EC 4 3
5 4
+5V_RUN 5
+3.3V_ALW 6
BC_INT#_ECE1117 7 6
+3.3V_TP +3.3V_TP <58> BC_INT#_ECE1117 BC_DAT_ECE1117 8 7
<58> BC_DAT_ECE1117 8
9
BC_CLK_ECE1117 10 9
<58> BC_CLK_ECE1117 10
2PTP_DISABLE#_R +3.3V_TP +3.3V_ALW +5V_RUN

10K_0402_5%

10K_0402_5%
C 1 11 C
<58> PTP_DISABLE# 11

1
@ @ +3.3V_TP @ RZ1475 0_0201_5% 12
12
1

1
2.2K_0402_5% DAT_TP_SIO_R

2.2K_0402_5%

RZ116

RZ117
13
RZ20 CLK_TP_SIO_R 13

RZ21
14
14

0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K
15 1 1 1
15

@
16

2
<14,58> TOUCHPAD_INTR# 16

CZ90

CZ91

CZ92
17
2

2
I2C1_SDA_TP_R 18 17
1 2 I2C1_SDA_TP_R I2C1_SCK_TP_R 19 18 2 2 2
<9> I2C1_SDA_TP 19
@ RZ26 0_0201_5% 20
1 2 I2C1_SCK_TP_R 20
<9> I2C1_SCK_TP
@ RZ29 0_0201_5%

I2C From CPU 21

22 GND1 Place close to JKBTP1
GND2

HRS_TF31-20S-0P5SH-800

Link HRS_TF31-20S-0P5SH-800 done 0313

Plan is for I2C to be driven by the EC for Win7 and Pre-OS (will utilize Intel I2C drivers for Win7)
For Win8.1 and 10 the EC will control TP over I2C Pre-OS and then the PCH will drive I2C when in Windows
Route PS2 from EC to the touch pad also for contingency plan if I2C has issues

B B

RSMRST circuit
PROM_BIOS_R <8>
1
1K_0402_5%

+3.3V_ALW
RZ401

@ CZ82
1 2
MP depop RZ401; MP RZ400 change to short pad
2

0.1U_0201_10V6K
5

1 2 PROM_BIOS 1
P

<58,79> PCH_RSMRST# B
RZ400 10K_0402_5% 4 PCH_RSMRST#_AND <11,79>
2 O
<11,85> ALW_PWRGD_3V_5V A
G

UZ6
3

MC74VHC1G08DFT2G_SC70-5

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

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PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Keyboard
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 63 of 109
5 4 3 2 1
 5 4 3 2 1

Battery LED
1 2 BATT_WHITE#
<58> BAT2_LED#
RZ361 150_0402_5%

1 2 BATT_YELLOW#
<58> BAT1_LED#
RZ28 150_0402_5%
D D

1213 change for ME request

From 330ohm to 150ohm

LED P/N change to SC50000FL00 from SC50000BA00

C C

Breath LED for Merion 14

+3.3V_ALW +5V_ALW
QZ7A LED3
@ CZ93 L2N7002DW 1T1G_SC88-6 LTW -C193DC-C_W HITE
1 2 1 6 BREATH_LED#_Q 1 2 BREATH_WHITE_LED_SNIFF# 1 2
<58> BREATH_LED#
RZ32 1K_0402_5%
0.1U_0201_10V6K
Place LED3 close to SW3
5

2
1 1031 change
P

<58> LED_MASK# B MASK_BASE_LEDS#

4
2 O
<59,64> LID_CL# A
G

UZ10
MC74VHC1G08DFT2G_SC70-5
3

MASK_BASE_LEDS#

LID SWITCH LED board CONN

+3.3V_ALW

HRS_TF31-4S-0P5SH-800
1

B UZ1 6 B
5 GND2
GND

2 3 GND1
VDD VOUT LID_CL# <59,64>
+5V_ALW
APX8131AI-TRG_SOT23-3
Place CZ94 near UZ1. 4
BATT_YELLOW # 3 4
<79> BATT_YELLOW#BATT_W HITE# 3
2
1 2
1
0.1U_0201_10V6K

1 JLED1
@ CZ94

CONN@
2
Hall sensor: SA00009EM00 Link TF31-4S-0P5SH-800 done 0504
(MAX hight is 1.45mm)

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
LED & LID
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 64 of 109
5 4 3 2 1
 5 4 3 2 1

D D

Reserve
C C

B B

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Reserve for KB/TP/LED/LID
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 65 of 109
5 4 3 2 1
 5 4 3 2 1

For ST/Nuvoton TPM +3.3V_ALW

1 2 USH_EXPANDER_SMBCLK
RZ8 2.2K_0402_5%
1 2 USH_EXPANDER_SMBDAT
+3.3V_ALW _PCH
1 2 RZ9 2.2K_0402_5%
@ST33@ RZ1408 0_0402_5%
+3.3V_ALW_PCH 1 2 USH_PWR_STATE#
750@ RZ1409 1 2 0_0402_5% +3.3V_VPS_UZ12 RZ10 100K_0402_5%

1031 change
750@ RZ89 1 2 0_0402_5% +UZ12_TPM
TPM_PIRQ# +3.3V_RUN
1 2
RZ69 10K_0402_5%
+3.3V_ALW 750@ RZ1410 1 2 0_0402_5% +3.3V_ALW_UZ12
USH CONN
D CONN@ D
+3.3V_RUN
1 2 JUSH1
@ RZ362 10K_0402_5% 28
27 GND2
1 2 TPM_GPIO0 GND1
<9,11,17,79,87> SIO_SLP_S0# 1031 change
@ST33@ RZ112 0_0201_5% @ RZ1414 1 2 0_0201_5% POW ER_SW #_MB_USH
26
1 2 TPM_GPIO0_NU <59,77,79> POWER_SW#_MB @ RZ1411 1 2 0_0201_5% FPR_RST#_USH
25 26
750@ RZ1407 0_0201_5% <66> FPR_RST# CV2_ON 24 25
<58> CV2_ON USB20_N9_USH 24
23
<66> USB20_N9_USH USB20_P9_USH 23
22
<66> USB20_P9_USH 22
UZ12 21
20 21
22 +3.3V_VPS_UZ12 19 20
+UZ12_TPM VPS <10> USB20_N8 19
8 18
+3.3V_ALW _UZ12 NiC_5 <10> USB20_P8 18
750@ CZ75

0.1U_0201_10V6K
ST33@CZ54

10U_0603_10V6M
ST33@CZ55

0.1U_0201_10V6K
750@ CZ53
1 17
NiC_1 17
10U_0402_6.3V6M

0.1U_0201_10V6K
750@ CZ50

750@ CZ52

1 1 1 16
<58> USH_EXPANDER_SMBCLK 16
10U_0402_6.3V6M

0.1U_0201_10V6K
750@ CZ51

1 1 31 15
NiC_21 <58> USH_EXPANDER_SMBDAT 15
1 1 16 14
@ RZ61 1 2 0_0201_5% PCH_SPI_CS#2_R 20 NiC_13 27 <58> BCM5882_ALERT# 13 14
<8> PCH_SPI_CS#2 SPI_CS# NiC_17 2 2 2 13
18 26 12
2 2 VPRO@ <9> TPM_PIRQ# SPI_PIRQ# NiC_16 25 11 12
NiC_15 +3.3V_ALW 11
2 2 RZ59 1 2 49.9_0402_1% PCH_SPI_D0_2_R 21 30 10
<8> PCH_SPI_D0_R1 MOSI NiC_20 10
RZ58 1 2 49.9_0402_1% PCH_SPI_D1_2_R 24 29 TPM_GPIO0_NU
+5V_ALW
9
<8> PCH_SPI_D1_R1 VPRO@ MISO NiC_19 28 8 9
TPM_GPIO0 NiC_18 +3.3V_VPS_UZ12 +3.3V_RUN 8
6 14 7
GPIO NiC_11 +5V_RUN FPR_SCAN_INT#_R 7
place CZ50, CZ75 as close as UZ12.8 15 place CZ53,CZ54,CZ55 as close as UZ12.22 @ RZ114 1 2 0_0201_5% 6
NiC_12 <58,66> FPR_SCAN_INT# USH_PW R_STATE# 6
place CZ51, CZ52 as close as UZ12.1 13 5
NiC_10 12 <58> USH_PWR_STATE# 2 1 CONTACTLESS_DET#_R 4 5
NiC_9 <12> CONTACTLESS_DET# 4
VPRO@ RZ60 1 2 49.9_0402_1% PCH_SPI_CLK_2_R 19 11 DZ8 RB751S-40_SOD523-2 3
<8> PCH_SPI_CLK_R1 SPI_CLK NiC_8 3
10 @ RZ1473 1 2 0_0201_5% NFC_ACTIVITY_STATUS#_R 2
NiC_7 5 1 2
NiC_4 4 <58> USH_DET# 1
7 NiC_3 3 HRS_TF31C-26S-0P5SH-800
Close to UZ12 PP NiC_2
32
PCH_SPI_CLK_2_R
RF Request
NiC_22 23 Link HRS_TF31C-26S-0P5SH-800 done 0313
17 NiC_14 9
<11> PLTRST_TPM# SPI_RST# NC_6
33_0402_5%

+3.3V_ALW 2
GND0
2

@EMI@

33
THPAD
RZ63

C
ST33HTPH2032AHC1_VQFN32_5X5 For NPTC750 Close to JUSH1 C
1
0.1U_0402_25V6

Depop RZ112, RZ1408 +5V_ALW +5V_RUN +3.3V_RUN +3.3V_ALW

Pop RZ1407, RZ1409, RZ89, RZ1410, CZ50~CZ53, CZ75
1

@EMI@

12P_0402_50V8J
RF@ CZ57

68P_0402_50V8J
RF@ CZ58

1 1
CZ56

0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K
2

1 1 1 1
2 2
Link SA0000C5G10 symbol done 0725

@
CZ64

CZ66

CZ67

CZ68
2 2 2 2

+5V_ALW RF Request +5V_RUN +3.3V_RUN +3.3V_ALW

RF Request

68P_0402_50V8J
RF@ CZ69

68P_0402_50V8J
RF@ CZ71

68P_0402_50V8J
RF@ CZ72

68P_0402_50V8J
RF@ CZ73
USH_EXPANDER_SMBCLK 1 2 1 1 1 1
FP in PWR BUTTON connector @RF@ CZ62 68P_0402_50V8J
USH_EXPANDER_SMBDAT 1 2
@RF@ CZ63 68P_0402_50V8J 2 2 2 2
USB20_P9_FP 1 2
USB20_P9 <10>
@ RZ1389 0_0201_5%
NEED CONFIRM MODULE PINDEFINE USB20_N9_FP
@ RZ1388
1 2
0_0201_5%
USB20_N9 <10>
CONN@ JFPBTN1 1 2
USB20_P9_USH <66>
@ RZ351 0_0201_5%
1 FPR_DET# 1 2
1 FPR_DET# <58> USB20_N9_USH <66>
2 @ RZ350 0_0201_5%
2 3
3 4 USB20_P9_FP
4 5
5 6 USB20_N9_FP Merion Limit height
6 7 DZ11 change to H=0.9mm(MAX)
2

7 8
8
@ESD@ DZ11
CEST523NC5VB_SOT-523-3

9
9 10 RESERVE 1
B PAD~D @ T418 B
10 11 FPR_LOW _PW R_MODE#
11 FPR_RST# FPR_LOW_PWR_MODE# <58> +3.3V_FPBTN +3.3V_RUN
12
12 FPR_UEFI_MGMT# FPR_RST# <66>
13
13 FPR_UEFI_MGMT# <58>
14
+3.3V_FPBTN
1

14 15 FPR_SCAN_INT# 1 2 +3.3V_ALW
15 FPR_SSO_EN# FPR_SCAN_INT# <58,66>
16 1206 change @ RZ1391 0_0402_5%
16 FPR_SSO_EN# <58>

1 2
FOX_QT510166-L010-7H @ RZ1390 0_0402_5%
QZ18
NTK3139PT1G_SOT723-3
Link FOX_QT510166-L010-7H done
1 3
D

QZ18 change to SB00000SS00

G

For Merion layout limit height

2

+3.3V_FPBTN +3.3V_FPBTN
FPR_PW R_EN#_R 1 2
FPR_PWR_EN# <58>
0.1U_0201_10V6K

@ RZ380 0_0201_5%
1
1

0.1U_0402_25V6K

@
1
CZ309

Compal RZ1392 @
CZ200

Signal FPR Symbol 100K_0201_5%

MB CONN Symbol 2
2

2 GND 1
2

FPR_RST#

4 USB DP(D+) 2
6 USB DM(D-) 3
8 GND 4
10 RESERVED 5
ESD Request 0824 @ESD@ @ESD@
12 FP RESET# 6 DZ14 DZ15
FPR_DET# 1 1 FPR_DET# FPR_UEFI_MGMT# FPR_UEFI_MGMT#
14 +3.3V_FPBTN 7 10 9 1 1 10 9

FPR_SSO_EN# RESERVE 2 2 9 8 RESERVE 2 2 8

A
16 8 +3.3V_FPBTN 9 +3.3V_FPBTN
A
FPR_LOW _PW R_MODE# 4 4 FPR_LOW _PW R_MODE# FPR_SCAN_INT# FPR_SCAN_INT#
15 FPR_SCAN_INT# 9 7 7 4 4 7 7
FPR_RST# 5 5 6 6
FPR_RST# FPR_SSO_EN# 5 5 6 FPR_SSO_EN#
13 FPR_UEFI_MGMT# 10 6

11 FPR_LOW_PWR_MODE# 11 3 3 3 3

8 8
9 NA 12
7 NA 13 AZ1045-04F_DFN2510P10E-10-9 AZ1045-04F_DFN2510P10E-10-9 DELL CONFIDENTIAL/PROPRIETARY
5 NA 14

https://Dr-Bios.com
3 NA 15
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
1 FPR DET(GND) 16 TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT USH & TPM
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 66 of 109
5 4 3 2 1
 5 4 3 2 1

D D

Reserve
C C

B B

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
HDD/ODD/FFS Connector
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 67 of 109
5 4 3 2 1
 5 4 3 2 1

Add Power Decoupling for support Intel Teton Glacier

RF Request
Place close JNGFF3 pin 12,14,16,18 Place close JNGFF3 pin 2,4 Place close JNGFF3 pin 70,72,74
+3.3V_HDD_M2
+3.3V_HDD_M2 +3.3V_HDD_M2 +3.3V_HDD_M2

100P_0402_50V8J~D
68P_0402_50V8J
@RF@ CN60

27P_0402_50V8J
RF@ CN77

RF@ CN78

0.01U_0402_16V7K

0.1U_0402_10V7K

22U_0603_6.3V6M

0.01U_0402_16V7K

0.01U_0402_16V7K

0.1U_0402_10V7K

22U_0603_6.3V6M

0.01U_0402_16V7K

0.01U_0402_16V7K

0.1U_0402_10V7K

22U_0603_6.3V6M
1 1

1
1 1 1 1 1 1 1 1

1
D D

CN79

CN61

CN63

CN80

CN81

CN62

CN64

CN84

CN82

CN86

CN87
2
2 2

2
2 2 2 2 2 2 2 2

Place near JNGFF3

+3.3V_SSD from SSD storage protection power gate control
0212 change
RN130 covering green printing for co-lay materials
2280 SSD 1 2
NGFF slot C Key M @ RN131 0.01_0805_1%
+3.3V_SSD

JUMP@ PJP31
+3.3V_HDD_M2 2 1

JNGFF3 CONN@ PAD-OPEN1x3m

1 2 2.8A 1 2 +3.3V_RUN
3 GND_1 3.3VAUX_1 4 @ RN130 0.01_0805_1%
5 GND_2 3.3VAUX_2 6
<10> PCIE_PRX_DTX_N13 7 PERn3 N/C_1 8 SSD_SCP#_R@ RN129 1 2 0_0201_5%
<10> PCIE_PRX_DTX_P13 PERp3 N/C_2 NVME_LED# SSD_SCP# <58>
9 10 1 2
CN65 2 1 0.22U_0402_10V6K PCIE_PTX_C_DRX_N13 11 GND_3 DAS/DSS# 12 @ RN100 0_0201_5%
<10> PCIE_PTX_DRX_N13 PCIE_PTX_C_DRX_P13 PETp3 3.3VAUX_3
CN66 2 1 0.22U_0402_10V6K 13 14
<10> PCIE_PTX_DRX_P13 PETn3 3.3VAUX_4
15 16
17 GND_4 3.3VAUX_5 18
C <10> PCIE_PRX_DTX_N14 19 PERn2 3.3VAUX_6 20 C
<10> PCIE_PRX_DTX_P14 21 PERp2 N/C_3 22
CN67 2 1 0.22U_0402_10V6K PCIE_PTX_C_DRX_N14 23 GND5 N/C_4 24
<10> PCIE_PTX_DRX_N14 PCIE_PTX_C_DRX_P14 PETp2 N/C_5
CN68 2 1 0.22U_0402_10V6K 25 26
<10> PCIE_PTX_DRX_P14 PETn2 N/C_6
27 28
29 GND6 N/C_7 30
<10> PCIE_PRX_DTX_N15 31 PERn1 N/C_8 32
<10> PCIE_PRX_DTX_P15 33 PERp1 N/C_9 34
CN69 2 1 0.22U_0402_10V6K PCIE_PTX_C_DRX_N15 35 GND7 N/C_10 36
<10> PCIE_PTX_DRX_N15 PCIE_PTX_C_DRX_P15 PETn1 N/C_11
CN70 2 1 0.22U_0402_10V6K 37 38
<10> PCIE_PTX_DRX_P15 PETp1 DEVSLP M2280_DEVSLP <10>
39 40
41 GND8 N/C_12 42
<10> PCIE_PRX_DTX_P16 43 PERn0/SATA-B+ N/C_13 44
<10> PCIE_PRX_DTX_N16 45 PERp0/SATA-B- N/C_14 46
CN71 2 1 0.22U_0402_10V6K PCIE_PTX_C_DRX_N16 47 GND9 N/C_15 48
<10> PCIE_PTX_DRX_N16 PCIE_PTX_C_DRX_P16 PETn0/SATA-A- N/C_16
CN72 2 1 0.22U_0402_10V6K 49 50
<10> PCIE_PTX_DRX_P16 PETp0/SATA-A+ PERST# PCH_PLTRST#_AND <11,38,42,52,70>
+3.3V_HDD_M2 51 52
GND10 CLKREQ# PCIE_W AKE# CLKREQ_PCIE#2 <11>
53 54
<11> CLK_PCIE_N2 REFCLKN PEWake# PCIE_WAKE# <42,52,59>
55 56
M2280_DEVSLP <11> CLK_PCIE_P2 REFCLKP N/C_17
1 2 57 58
@ RN37 10K_0402_5% GND11 N/C_18
if signal is PCIE GEN3/SATA GEN3 maybe change C value
or no need for DG0.9 SATA EXPRESS HDD
Key M
67 68 SUSCLK_R @ RN99 1 2 0_0201_5%
N/C_19 SUSCLK(32kHz) (O)(0/3.3V) SUSCLK <11,52>
69 70
<10> M2280_PCIE_SATA# 71 PEDET (OC-PCIe/GND-SATA) 3.3VAUX_7 72
73 GND_12 3.3VAUX_8 74
75 GND_13 3.3VAUX_9
B GND_14 B
77 76
GND_16 GND_15
79 78
NPTH_2 NPTH_1
LOTES_APCI0170-P001A

Link APCI0170-P001A done 0123

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
M2 2280 Socket
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 68 of 109
5 4 3 2 1
 5 4 3 2 1

D D

Reserve
C C

B B

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
eMMC / UFS
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 69 of 109
5 4 3 2 1
 5 4 3 2 1

+3.3V_RUN

1
JUMP@
PJP14
2
+3.3V_MMI_IN
For PCIE Interface
RF Request
+3.3V_MMI_AUX +3.3V_MMI_IN PAD-OPEN1x2m

+3.3V_MMI_IN +3.3V_MMI_AUX
support D3 Hot(if D3 cold PIN11,PIN27 need Add MOS on/off 3V3AUX)
2 1
D @ RR274 0_0603_5% D
@RF@ CR27 +3.3V_MMI_AUX +3.3V_MMI_IN

@RF@ CR28

@RF@ CR25

@RF@ CR26
12P_0402_50V8J

82P_0402_50V8J

12P_0402_50V8J

82P_0402_50V8J
1 1 1 1

4.7U_0402_6.3V6M

0.1U_0201_10V6K

0.1U_0201_10V6K

10U_0402_6.3V6M
+3.3V_MMI_AUX
2 2 2 2
1 1 1 1

CR4
CR3
MEDIACARD_IRQ#

CR1

CR2
2 1 7/18 Vender suggest.
RR19 10K_0402_5%
2 2 2 2

27
11
UR1

3V3aux
3V3_IN
1 12 +3.3V_RUN_CARD
<11,38,42,52,68> PCH_PLTRST#_AND PERST# CARD_3V3 +DV33_18
2 18 1 2
<11> CLKREQ_PCIE#4 CLK_REQ# DV33_18 CR22 1U_0201_6.3V6M
5
<11> CLK_PCIE_P4 REFCLKP SD/MMCDAT1/RCLK-_R
6 15 SD/MMCDAT1/RCLK- @ RR9 1 2 0_0201_5%
<11> CLK_PCIE_N4 REFCLKN SP1 SD/MMCDAT0/RCLK+_R
16 SD/MMCDAT0/RCLK+ @ RR10 1 2 0_0201_5%
C CR11 1 2 0.1U_0402_25V6 PCIE_PTX_C_DRX_P9 3 RTS5242 SP2 17 SD/MMCCLK @EMI@ RR5 1 2 0_0201_5% SD/MMCCLK_R C
<10> PCIE_PTX_DRX_P9 PCIE_PTX_C_DRX_N9 HSIP SP3 SD/MMCCMD_R

@EMI@ CR21
CR12 1 2 0.1U_0402_25V6 4 19 SD/MMCCMD @ RR6 1 2 0_0201_5%
<10> PCIE_PTX_DRX_N9 PCIE_PRX_C_DTX_P9 HSIN SP4 SD/MMCDAT3_R

5P_0402_50V8C
CR13 1 2 0.1U_0402_25V6 7 20 SD/MMCDAT3 @ RR7 1 2 0_0201_5%
<10> PCIE_PRX_DTX_P9 CR14 1 2 0.1U_0402_25V6 PCIE_PRX_C_DTX_N9 8 HSOP SP5 21 SD/MMCDAT2 @ RR8 1 2 0_0201_5% SD/MMCDAT2_R
<10> PCIE_PRX_DTX_N9 HSON SP6

1
29 SDWP
SP7
32

2
<8> MEDIACARD_IRQ# 31 WAKE#
SD/MMCCD# 30 MS_INS#
+1.2V_LDO SD_CD#
7/18 Vender suggest
CR13 close to UR2.10 22 SD_UHS2_D1P EMI depop locat i on
SD_LN1_P 23 SD_UHS2_D1N
CR9 CR10 close to UR2.14 SD_LN1_M
10
14 AV12 26 SD_UHS2_D0P
DV12S SD_LN0_P 25 SD_UHS2_D0N
SD_LN0_M
4.7U_0402_10V6M

0.1U_0201_10V6K

0.1U_0201_10V6K +1.8V_RUN_CARD 13
SD_VDD2 24 +SDREG2 CR15 1 2
1 1 1

E-PAD
+RREF 9 SDREG228 1U_0201_6.3V6M
CR5

CR6

CR7
RREF GPIO SD_GPIO 2 1 +3.3V_MMI_AUX
10K_0402_5% RR3
2 2 2 RTS5242-GR_QFN32_4X4

33
1

6.2K_0402_1%
RR4
JSD1 CONN@

2
+3.3V_RUN_CARD 4
15 VDD1
+1.8V_RUN_CARD SD/MMCCMD_R VDD2
3
B SD/MMCCLK_R 5 CMD B
CLK
SD/MMCCD# 9
16 CD
SWIO
SD/MMCDAT0/RCLK+_R 7
SD/MMCDAT1/RCLK-_R 8 DAT0/RCLK+
SD/MMCDAT2_R 1 DAT1/RCLK-
SD/MMCDAT3_R 2 DAT2
CD/DAT3
QR1
L2N7002W T1G_SC-70-3 SD_UHS2_D0P 18
+3.3V_RUN_CARD +1.8V_RUN_CARD SD_UHS2_D0N 19 D0+
HOST_SD_W P# SDW P STATUS SDWP 1 3 SD_UHS2_D1P 22 D0-
D

SD_UHS2_D1N 21 D1+
D1- 10
High Low Write Enable 6 GND1 11

4.7U_0402_10V6M

4.7U_0402_10V6M
0.1U_0201_10V6K

0.1U_0201_10V6K
G
2

17 VSS1 GND2 12
2 1 2 1 VSS2 GND3
20 13

CR17

CR19
<12> HOST_SD_WP# VSS3 GND4

CR18

CR20
Low High Write Protect(FW LOCK) 23 14
24 VSS4 GND5 25
1 2 1 2 NPTH1 NPTH2
T-SOL_158-1240902600

Link 158-1240902600 done 0123

CR38,CR39 near JSD1.4 CR40,CR41 near JSD1.14
A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Card Reader RTS5242
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 70 of 109
5 4 3 2 1
 5 4 3 2 1

For Merion 14
+5V_USB_CHG_PWR

JUSB1 CONN@
1
USB20_N2_R 2 VBUS
USB20_P2_R D-

150U_B2_6.3VM_R35M

100U_A_6.3VM_R70M
3
DI4 ESD@ D+

0.1U_0201_10V6K
D 1 @ 1 4 D
USB3_PRX_DTX_N2 1 1 USB3_PRX_DTX_N2 USB3_PRX_DTX_N2 GND5
10 9 1 5
<10> USB3_PRX_DTX_N2 + + USB3_PRX_DTX_P2 6 SSRX- 10
SSRX+ GND1

2
USB3_PRX_DTX_P2 USB3_PRX_DTX_P2

CI32

CI14

CI17
2 2 9 8 7 11
<10> USB3_PRX_DTX_P2 USB3_PTX_C_DRX_N2 GND6 GND2

CEST523NC5VB_SOT-523-3
ESD@ DI5
8 12
2 1 USB3_PTX_C_DRX_N2 4 4 USB3_PTX_C_DRX_N2 2 2 2 USB3_PTX_C_DRX_P2 SSTX- GND3
7 7 9 13
<10> USB3_PTX_DRX_N2 SSTX+ GND4
CI13 0.1U_0402_25V6
2 1 USB3_PTX_C_DRX_P2 5 5 6 6 USB3_PTX_C_DRX_P2 ACON_TCRA2-9U1U93
<10> USB3_PTX_DRX_P2
CI16 0.1U_0402_25V6
3 3

1
1206 change
8
Link ACON_TCRA2-9U1U93 done 0313
AZ1045-04F_DFN2510P10E-10-9

Merion Limit height RF Request

DI5 change to H=0.9mm(MAX) +5V_USB_CHG_PW R

M
e
r
i
o
n
1
4
s
w
a
p
L
I
7
n
e
t
f
o
r
l
a
y
o
u
t
r
o
u
t
i
n
g
EMI@
LI7
C SW _USB20_P2 1 2 USB20_P2_R C
1 2

12P_0402_50V8J
RF@ CI43

68P_0402_50V8J
RF@ CI44
1 1
SW _USB20_N2 4 3 USB20_N2_R
4 3
DLM0NSN900HY2D_4P 2 2
+5V_ALW
+5V_USB_CHG_PWR
UI3
1 12
VIN VOUT
2
<10> USB20_N2 DM_OUT
3
<10> USB20_P2 DP_OUT SW_USB20_P2
10
13 DP_IN 11 SW_USB20_N2
<10> USB_OC0# FAULT# DM_IN
ILIM_SEL 4
ILIM_SEL
5 15
<58> USB_POWERSHARE_VBUS_EN EN ILIM_L 16 RI14 2 1
ILIM_HI 22.1K_0402_1%
6
<58> USB_POWERSHARE_EN# CTL1
7 9
8 CTL2 NC 14
CTL3 GND 17
Thermal Pad

+5V_ALW SLGC55544CVTR_TQFN16_3X3
B B

RI13 2 1 ILIM_SEL Link Seligro SA000097E10 Done

10K_0402_5% MAIN:SLGC55544CVTR

+5V_ALW
47U_0603_6.3V6M

47U_0603_6.3V6M

100P_0402_50V8J

0.1U_0201_10V6K
RF@CI31

1 1 1 1
@ CI34

@ CI33

CI19

2 2 2 2

Place near UI3.1

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
JUSB1+PS
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 71 of 109
5 4 3 2 1
 5 4 3 2 1

For Merion 14

D D

DI1 ESD@
USB3_PRX_DTX_N3 1 1 10 9 USB3_PRX_DTX_N3
<10> USB3_PRX_DTX_N3
USB3_PRX_DTX_P3 2 2 9 8 USB3_PRX_DTX_P3 +USB_EX2_PWR
<10> USB3_PRX_DTX_P3
2 1 USB3_PTX_C_DRX_N3 4 4 7 7 USB3_PTX_C_DRX_N3 JUSB2 CONN@
<10> USB3_PTX_DRX_N3
CI5 0.1U_0402_25V6 1
2 1 USB3_PTX_C_DRX_P3 5 5 USB3_PTX_C_DRX_P3 USB20_N3_R VBUS
6 6 2
<10> USB3_PTX_DRX_P3 USB20_P3_R D-

150U_B2_6.3VM_R35M

100U_A_6.3VM_R70M
CI4 0.1U_0402_25V6 3
D+

0.1U_0201_10V6K
3 3 1 @ 1 4
C USB3_PRX_DTX_N3 5 GND5 C
1 SSRX-
8 + + USB3_PRX_DTX_P3 6 10
SSRX+ GND1

CI103

CI1

CI3
7 11
USB3_PTX_C_DRX_N3 8 GND6 GND2 12
SSTX- GND3

2
AZ1045-04F_DFN2510P10E-10-9 2 2 2 USB3_PTX_C_DRX_P3 9 13
SSTX+ GND4

CEST523NC5VB_SOT-523-3
ESD@ DI2
ACON_TCRA2-9U1U93

EMI@
LI3
USB20_N3 1 2 USB20_N3_R
RF Request <10> USB20_N3 Link ACON_TCRA2-9U1U93 done 0313

1
1 2 0212 change 1206 change
+USB_EX2_PW R
USB20_P3 USB20_P3_R CI103 covering green printing for co-lay materials
4 3
<10> USB20_P3 4 3
M
e
r
i
o
n
1
4
s
w
a
p
L
I
3
n
e
t
f
o
r
l
a
y
o
u
t
r
o
u
t
i
n
g
DLM0NSN900HY2D_4P

DFB request:
12P_0402_50V8J
RF@ CI45

68P_0402_50V8J
RF@ CI46

main SM070003Z00 (INPAQ_MCM1012B900F06BP_4P)

1 1
Footprint use 2nd source SM070004400 (PANAS_EXC24CQ900U_4P) Merion Limit height +USB_EX2_PWR
Pitch change from 0.5mm to 0.55mm
+5V_ALW
DI2 change to H=0.9mm(MAX)
2 2 UI1
1
5 OUT
IN 2
GND

10U_0603_10V6M

0.1U_0201_10V6K
4
B <58> USB_PWR_EN1# EN B
1 3 USB_OC1# <10>
OCB

@ CI6

CI7
SY6288D20AAC_SOT23-5

2
2

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
JUSB2
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 72 of 109
5 4 3 2 1
 5 4 3 2 1

D D

Reserve
C C

B B

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
USB2/USB3 DB
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 73 of 109
5 4 3 2 1
 5 4 3 2 1

D D

Reserve
C C

B B

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Dock
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 74 of 109
5 4 3 2 1
 5 4 3 2 1

D D

Reserve
C C

B B

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Reserve for USB
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 75 of 109
5 4 3 2 1
 5 4 3 2 1

D D

Reserve
C C

B B

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Reserve for USB
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 76 of 109
5 4 3 2 1
 5 4 3 2 1

+3.3V_RUN

1 2 PWM_FAN1
RE48 10K_0402_5%
1 2 TACH_FAN1
RE51 10K_0402_5%

D D

Link 50271-0040N-001 done 0123

JFAN1
1
1 2 PW M_FAN1
2 TACH_FAN1 PWM_FAN1 <58>
3
3 TACH_FAN1 <58>
4 +5V_RUN
4 10U_0402_6.3V6M
5
GND1
1
6 1
GND2 @ DE1
CE32

ACES_50271-0040N-001 BZV55-B5V6_SOD80C2
CONN@
2
2

Fan follow X9 project PIN DEFINE

C
POWER & INSTANT ON SWITCH C

TOP
SW 3
3 1
<59,66,79> POWER_SW#_MB
1213 change
Update SW3 footprint

4 2
SKRBACE010_4P

LED Circuit Control Table

LED_MASK# LID_CL#

B B
Mask All LEDs (Unobtrusive mode) 0 X
Mask Base MB LEDs (Lid Closed) 1 0
Do not Mask LEDs (Lid Opened) 1 1

CPU NGFF Standoff EDP

Fiducial Mark @ H1
H_3P7
@ H2
H_3P7
@ H3
H_3P7
@ H4
H_3P7
@ H5
H_4P0
@ H8
H_4P0
@ H11 @ H12
H_2P6 H_2P6
@ H20 @ H21
H_3P2 H_3P2
@ H14
H_2P3
@ FD1
1
1

FIDUCIAL MARK~D

@ FD2
1
1213 change
FIDUCIAL MARK~D @ H13 @ H15 @ H16 @ H17 @ H18 @ H27 @ H28 From CLIP_0P6X7P0 to CLIP_0P8X7P0 UT1 AR CLIPSCLIP15 CONN@
H_3P1 H_2P6 H_2P6 H_2P6 H_3P1 H_3P6X2P6 H_2P6 CLIP13 CONN@
@ FD3 JUSB2 CLIPS 1 1
1 P1 P1
CLIP7 CONN@ CLIP8 CONN@ CLIP9 CONN@
1

FIDUCIAL MARK~D 1213 change 1 1 1 EMIST_SUL-15A3M EMIST_SUL-15A3M

P1 P1 P1 CLIP17 CONN@
From CLIP_0P6X7P0 to CLIP_0P8X7P0
@ FD4 1 CLIP14 CONN@ CLIP16 CONN@
1 @ H29 @ H30 CLIP_0P8X7P0 CLIP_0P8X7P0 CLIP_0P8X7P0 P1 1 1
H_0P6X2P8
JUSB1 CLIPS H_2P5X0P7 P1 P1
A A
FIDUCIAL MARK~D CLIP1 CONN@ CLIP2 CONN@ CLIP3 CONN@ CLIP12 CONN@ CLIP11 CONN@ CLIP10 CONN@ CLIP_14P1X2P6
1 1 1 1 1 1 EMIST_SUL-15A3M EMIST_SUL-15A3M
P1 P1 P1 P1 P1 P1
DELL CONFIDENTIAL/PROPRIETARY
1

CLIP_0P8X7P0 CLIP_0P8X7P0 CLIP_0P8X7P0 CLIP_0P8X7P0 CLIP_0P8X7P0 CLIP_0P8X7P0

SHDCAN CONN@ @ H31
Compal Electronics, Inc.

https://Dr-Bios.com
1 CLIP4 CONN@ CLIP5 CONN@ CLIP6 CONN@ H_2P5X0P7 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
P1 1 1 1
P1 P1 P1 TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
PWRBTN, PAD, ME, FAN
SION_C7521R_1P-T Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
1

CLIP_0P8X7P0 CLIP_0P8X7P0 CLIP_0P8X7P0 1.0

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 77 of 109
5 4 3 2 1
 5 4 3 2 1

+3.3V_WWAN/+3.3V_LAN source JUMP@ +3.3V_WWAN_UZ43 +1.8V_RUN source

PJP41
1 2 JUMP@
+3.3V_ALW EM5209VF_SON14_2X3 +3.3V_WWAN
1 PJP42 0.013A
15 1 2
GPAD PAD-OPEN1x3m 2.5A RF@ CZ124 +1.8V_PRIM UZ8
+1.8V_RUN
7 8 +3.3V_WWAN_UZ43 1 2 2200P_0402_50V7K PAD-OPEN1x1m
6 VIN2_2 VOUT2_2 9 CZ119 0.1U_0201_10V6K 2 1 7
VIN2_1 VOUT2_1 2 VIN1 VOUT1 8 +1.8V_RUN_UZ8 1 2
3.3V_WWAN_EN 5 10 1 2 @ RZ345 VIN2 VOUT2 CZ120 0.1U_0201_10V6K
<58> 3.3V_WWAN_EN ON2 CT2 CZ109 470P_0402_50V7K 1 2 0_0201_5% RUN_ON_1.8V 3 6 1 2
<17,58,59,78,87> RUN_ON ON CT
D +5V_ALW 4 11 CZ121 470P_0402_50V7K D
VBIAS GND
3 12
RF Request 4
ON1 CT1 +5V_ALW VBIAS 5
2 13 GND1 9
VIN1_2 VOUT1_2 Merion no RJ45 LAN port GND2

1
1 14
VIN1_1 VOUT1_1 @ CZ197
1 2 3.3V_WWAN_EN UZ43 AOZ1336_DFN8_2X2
470P_0402_50V7K

2
RZ40 100K_0402_5%

Reserve R/C for Audio power sequence, +5V->+3.3V->+1.8V

EC request to reserve OR gate for WLAN power enable

+3.3V_ALW_PCH/+3.3V_RUN source JUMP@ +3.3V_ALW
PJP38 0.63A
+3.3V_ALW_PCH

100K_0402_5%
1 2 +3.3V_ALW_PCH

1
+3.3V_ALW

RZ518
PAD-OPEN1x1m
+3.3V_ALW
UZ3

1
20K_0402_5%
+3.3V_ALW_PCH_UZ3

@ RZ379
1 14 1 2

20K_0402_5%
2
2 VIN1_1 VOUT1_1 13 CZ112 0.1U_0201_10V6K
VIN1_2 VOUT1_2 <58> SLP_WLAN#_GATE

RZ1483
@ RZ64 1 2 0_0201_5% 3 12 1 2
<11,87> PCH_PRIM_EN ON1 CT1 CZ113 100P_0402_50V8J Merion Limit height

2
Merion Limit height

2
+5V_ALW 4
VBIAS GND
11 DZ9 change to SCS00008B80 H=0.6mm(MAX)
RUN_ON 5 10 1 2
QZ15 change to SB00001KM00 H=0.9mm(MAX) 1 2

2
<17,58,59,78,87> RUN_ON ON2 CT2 CZ114 1000P_0402_50V7K @ RZ71 0_0201_5%
C C

G
6 9
7 VIN2_1 VOUT2_1 8 +3.3V_RUN_UZ3 1 2 DZ9
VIN2_2 VOUT2_2 CZ115 0.1U_0201_10V6K
1 3 SLP_WLAN#_M 3
15 <11> SIO_SLP_WLAN#
GPAD

S
JUMP@
1 WLAN_PWR_EN
EM5209VF_SON14_2X3 PJP39
1 2 QZ15 2
+3.3V_RUN PJE138K_SOT523-3
PAD-OPEN1x3m
<58> AUX_EN_WOWL BAT54CTB_SOT-523-3
3.435A
1 2
@ RZ70 0_0201_5%

+5V_RUN/+3.3V_WLAN source
Reserve for SSD storage protection power gate control Refence Berlinetta CFL pilot

+3.3V_ALW
JUMP@ +3.3V_ALW
PJP40 3.076A @ UZ53
+3.3V_SSD
1 2
+5V_RUN
1 7
VIN1 VOUT1

5
+5V_ALW @ UZ54 2 8 1 2
UZ47 PAD-OPEN1x2m 1 MC74VHC1G32DFT2G_SC70-5~D VIN2 VOUT2 @ CZ305 0.1U_0201_10V6K

P
+5V_RUN_UZ47 <17,58,59,78,87> RUN_ON INB SSD_EN
1 14 1 2 4 3 6 1 2
2 VIN1_1 VOUT1_1 13 CZ116 0.1U_0201_10V6K SSD_SCP_PWR_EN_D 2 O ON CT @ CZ306 470P_0402_50V7K
VIN1_2 VOUT1_2 INA

G
2
B 3 12 1 2 +5V_ALW
4 B
<17,58,59,78,87> RUN_ON

3
ON1 CT1 CZ117 470P_0402_50V7K @ RZ1472 VBIAS 5
4 11 100K_0402_5% GND1 9
VBIAS GND GND2
WLAN_PWR_EN 5 10 1 2

1
ON2 CT2 CZ118 470P_0402_50V7K 1 2 AOZ1336_DFN8_2X2
6 9 +3.3V_WLAN_UZ47 1 2 @ RZ1471 0_0201_5%
+3.3V_ALW VIN2_1 VOUT2_1
7 8 CZ122 0.1U_0201_10V6K
VIN2_2 VOUT2_2 JUMP@
15 PJP36
GPAD 1 2 +3.3V_WLAN
EM5209VF_DFN14_3X2
PAD-OPEN1x2m
2A EC +1.8V to +3.3V Level Shift
1 2 WLAN_PWR_EN +3.3V_ALW +1.8V_PRIM
RZ38 100K_0402_5%

Merion Limit height

2
@ RZ1474
100K_0402_5%
QZ22 change to SB00001KM00 H=0.9mm(MAX)

2
G
1
SSD_SCP_PWR_EN_D 1 3 SSD_SCP_PWR_EN
SSD_SCP_PWR_EN <58>

S
@ QZ22
PJE138K_SOT523-3

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Power control
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 78 of 109
5 4 3 2 1
 5 4 3 2 1

CONN@ +3.3V_RUN +13.5VB

1
JAPS1 JESPI
1
For BL_PWR_SRC & LCDVDD monitor +LCDVDD
+3.3V_ALW_PCH SIO_SLP_S3# 1 1
2 2

3
<11,17,42,59> SIO_SLP_S3# 2 2
3 3 ESPI_IO0 <8,58>
+3.3V_ALW SIO_SLP_S5# 3 3
4 4 ESPI_IO1 <8,58>
<11> SIO_SLP_S5# SIO_SLP_S4# 4 4
5 5 ESPI_IO2 <8,58>
<11,17,86,87> SIO_SLP_S4# SIO_SLP_A# 5 5 2
6 6
<11> SIO_SLP_A# 6 6 ESPI_IO3 <8,58>

100K_0402_5%
7 7
+3.3V_ALW

1
7 7 ESPI_CS# <8,58>

10K_0402_5%
8 8

1
8 8 ESPI_RESET# <8,58>

RV623
PCH_RTCRST# 9 11 9 +BL_PWR_SRC
<11,58> PCH_RTCRST# 9 GND1 9

RV627
10 12 10 QV18
10 GND2 10 ESPI_CLK_5105 <8,58>
11

1
<59,66,77> POWER_SW#_MB MMBT3906H_SOT23-3
12 11 JXT_FP241AH-010GAAM

2
SYS_RESET# 13 12

47K_0402_5%
2
D <11> SYS_RESET# 13 CONN@ D
14

1
SIO_SLP_S0# 15 14 2 1 PANEL_PW RGD 1 2

RV625
<9,11,17,66,87> SIO_SLP_S0# 15 PANEL_MONITOR <58>
16 @ RV628 0_0201_5%
16

2200P_0402_50V7K
17

J
X
T
_
F
P
2
4
1
A
H
-
0
1
0
G
A
A
M
L
I
N
K
D
O
N
E
DV11

0.1U_0201_25V6K

200K_0402_5%

0.1U_0402_25V6
17 1

1M_0402_5%
18

1
RB751S-40_SOD523-2
18

1
1

2
CV633

1
CV634

RV626

CV632
1

RV624
19 C
20 GND1 BL_PW R_MONITOR 2
2
GND2

2
B

2
2
CVILU_CF4218FH0R0-05-NH QV19 E

2
LMBT3904W T1G_SC70-3

+3.3V_ALW +3.3V_RUN

3
1
10_0402_1%

1
RE71

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

RF Request
2

1
10K_0402_5%

10K_0402_5%

10K_0402_5%

100K_0402_5%
RE813

RE814

RE815

RE816

+13.5VB

@ RE75
2

10K_0402_5%
RE72

RE73

RE74
JDEG1

1
2

+EC_DEBUG_VCC +LCDVDD

100P_0402_50V8J~D
1
1 JTAG_TDI

RV631

47P_0402_50V8J
RF@ CV755

RF@ CV756
2 QV20
JTAG_TDI <58>

2
2 3 JTAG_TMS

1
JTAG_TMS <58> MMBT3906H_SOT23-3 1
3

1
4 JTAG_CLK
4 JTAG_TDO JTAG_CLK <58>
5 RE86

47K_0402_5%
2
5 JTAG_TDO <58>
6 MSCLK

1
10K_0402_5%

2
6 7 MSDATA 1 2 2 1 2

RV630
7 8 HOST_DEBUG_TX
8 DEBUG_TX

2200P_0402_50V7K
11 9 DV12

0.1U_0201_25V6K

200K_0402_5%
12 GND1 9 10 1

1
RB751S-40_SOD523-2
GND2 10

1
1 2

2
CV651
CV652

RV629
<6> SBIOS_TX
JXT_FP241AH-010GAAM @ RE306 0_0201_5%

1
CONN@ 2 C place as close as QV18
LCDVDD_MONITOR

2
2
HOST_DEBUG_TX <58>

2
B
MSDATA <58>
QV21 E
MSCLK <58>

3
C C
1 2
J
X
T
_
F
P
2
4
1
A
H
-
0
1
0
G
A
A
M
L
I
N
K
D
O
N
E

LMBT3904W T1G_SC70-3
@ RE30 0_0201_5%

+1.0V_PRIM +1.0V_PRIM_XDP

@ RC216
1 2
0_0402_5%
M-BIST
<13> CFG[0..19] BATT_YELLOW# <64>
+1.0V_PRIM_XDP
+1.0V_PRIM_XDP CPU_XDP_TCLK 1 2 XDP_JTAGX
CPU XDP XDP_PRSNT_PIN1
@ RC121
1 2 CFG3
0_0201_5% +1.0V_PRIM_XDP
@ RC328 0_0201_5%
XDP_JTAGX <14>

TDO_XDP CPU_XDP_TDO
0.1U_0201_10V6K

0.1U_0201_10V6K

1 2 2 1
CPU_XDP_TDO <14>
@ CC288

@ CC299

1 1 @ RC122 0_0201_5% @ RC850 0_0201_5% @ DZ12

JXDP1 CONN@ TDI_XDP 2 1 CPU_XDP_TDI 1 2
CPU_XDP_TDI <14> <58,84,91> ACAV_IN

3
1 2 @ RC851 0_0201_5%
3 1 2 4 CFG17 XDP_TMS 2 1 CPU_XDP_TMS RB751S-40_SOD523-2
2 2 <14> CPU_XDP_PREQ# 3 4 CPU_XDP_TMS <14> M_BIST_R
5 6 CFG16 2 1
R2
@ RC852 0_0201_5% R1=10K;R2=10K
<14> CPU_XDP_PRDY# 5 6 TRST#_XDP CPU_XDP_TRST# <58> M_BIST BAT1_LED#_R 2
7 8 2 1 @ RZ1415 0_0201_5% QZ3
7 8 CPU_XDP_TRST# <14>
CFG0 9 10 CFG8 @ RC853 0_0201_5% +3.3V_ALW 2 1 LMUN5111T1G_SC70-3
CFG1 11 9 10 12 CFG9 RZ1482 1M_0402_5%
R1
13 11 12 14 XDP_TMS 1 2 PCH_JTAG_TMS 2 1
13 14 PCH_JTAG_TMS <14> <58,63> PCH_RSMRST#
CFG2 15 16 CFG10 @ RC735 0_0201_5% @ RZ1413 330K_0402_5%
Place near 15 16

1
CFG3 17 18 CFG11 TDI_XDP 1 2 PCH_JTAG_TDI C
JXDP1 PCH_JTAG_TDI <14>

1
19 17 18 20 @ RC736 0_0201_5% 2 1 2
1 2 XDP_OBS0 21 19 20 22 CFG19 TDO_XDP 1 2 PCH_JTAG_TDO CZ218 2.2U_0603_10V6K B
<14> XDP_OBS0_R XDP_OBS1 21 22 PCH_JTAG_TDO <14>
@ RC239 1 2 0_0201_5% 23 24 CFG18 @ RC737 0_0201_5% QZ21 E
<14> XDP_OBS1_R

3
@ RC240 0_0201_5% 25 23 24 26 LMBT3904W T1G_SC70-3
1218 Change
CFG4 27 25 26 28 CFG12 1 2
CFG5 29 27 28 30 CFG13 RZ25 150_0402_5%
31 29 30 32 +1.0V_VCCSTG
RC5 need to close to JCPU1 31 32
CFG6 33 34 CFG14
@ RC123 1 33 34 <58,59> POWER_SW_IN#
B 2 1K_0201_5% CFG7 35 36 CFG15 B
<11,59> VCCST_PWRGD 35 36
37 38
CXDP@ RC124 1 2 1K_0201_5% H_VCCST_PWRGD_XDP 39 37 38 40 PCH_JTAG_TDI 1 2
<11,63> PCH_RSMRST#_AND 39 40 CLK_ITPXDP_P_R <11>
41 42 RC569 51_0201_5%
FIVR_EN <11,58> SIO_PWRBTN# 41 42 CLK_ITPXDP_N_R <11> PCH_JTAG_TDO
@ RC217 1 2 0_0201_5% 43 44 1 2
CFG0 @ RC126 1 2 1K_0201_5% FIVR_EN_R 45 43 44 46 ITP_PMODE RC568 100_0201_5%
RESET_OUT#_R 45 46 XDP_DBRESET# ITP_PMODE <13> PCH_JTAG_TMS
@ RC128 1 2 0_0201_5% 47 48 XDP_DBRESET# <11> 1 2
<8> PCH_SPI_DO_XDP 47 48
@ RC129 1 2 0_0201_5% 49 50 RC130 51_0201_5%
<11,58> SYS_PWROK 49 50 TDO_XDP
51 52
<8,23,24> DDR_XDP_WAN_SMBDAT 51 52 TRST#_XDP
53 54
<8,23,24> DDR_XDP_WAN_SMBCLK 53 54 TDI_XDP
55 56
<14> PCH_JTAG_TCK CPU_XDP_TCLK 55 56 XDP_TMS +1.0V_VCCSTG
57 58
<14> CPU_XDP_TCLK 57 58
59 60
59 60 PCH_SPI_DO2_XDP <8>
61
61 CPU_XDP_TMS 1 2
@ RC131
CPU_XDP_TDI
51_0201_5% Service Mode Switch:
62 63 1 2
GND GND @ RC134 51_0201_5% Add a switch to ME_FWP signal to unlock the ME region and
CPU_XDP_TDO 1 2 allow the entire region of the SPI flash to be updated using FPT.
JXT_FP270H-061G1AM RC135 100_0201_5%
+1.0VS_VCCIO
+3.3V_ALW_PCH 0212 Change
2 1 FIVR_EN_R Link FP270H-061G1AM done 0131 CPU_XDP_TRST# 1 2
RC132 150_0402_5% @ RC136 51_0201_5% ME_FW P 1 2 ME_FWP_PCH
+1.0V_VCCST CPU_XDP_TCLK 1 2 @ RC221 0_0201_5%

2
RC139 51_0201_5% PT,ST pop RC222 and SW1; MP pop RC221
2 1 FIVR_EN +3.3V_ALW_PCH @ RC222
@ RC235 150_0402_5% 1K_0402_5%
2

2 1 FIVR_EN
CXDP@ RC133
1.5K_0201_5%

1
@ RC236 10K_0201_5% @ SW 1
+3.3V_ALW_DSW 1
ME_FWP_PCH 2 1
<12> ME_FWP_PCH ME_FW P C
3
<58> ME_FWP
1

2
1.5K_0201_5%
4
TDO_XDP H_VCCST_PW RGD_XDP G1

@ RC241
5
PCH_SPI_DO_XDP G2
Place near JXDP1.48
@ESD@ CC306

@ESD@ CC307

+3.3V_RUN SSAJ120100_3P
RESET_OUT#_R XDP_DBRESET#
0.1U_0201_25V6K

0.1U_0201_25V6K

1 1 ME_FWP PCH has internal 20K PD. Link SSAJ120100 done 0514
1

XDP_DBRESET# SIO_PWRBTN# (suspend power rail)

0.1U_0201_25V6K

2 1 1
CXDP@ CC326

RC137 3K_0402_5% FLASH DESCRIPTOR SECURITY OVERRIDE

+1.0V_PRIM_XDP 2 2
@ CC334

0.1U_0201_25V6K

A 1 A
0.1U_0201_25V6K

2
1 LOW = ENABLE (DEFAULT) -->Pin2 & Pin3 short
@ CC269

1 2 CPU_XDP_PREQ# HIGH = DISABLE (ME can update) -->Pin1 & Pin2 short
@ RC138 51_0201_5% 2 Place near JXDP1.41
2
ESD request,Place near JXDP1 side.

Place near JXDP1.47

DELL CONFIDENTIAL/PROPRIETARY

https://Dr-Bios.com
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT XDP/CMC/APS...debug
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 79 of 109
5 4 3 2 1
 5 4 3 2 1

D D

Reserve
C C

B B

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Google Debug & INAs
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 80 of 109
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

DELL CONFIDENTIAL/PROPRIETARY

https://Dr-Bios.com
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D PWR-Block Diagram
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Size Document Number Rev
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1.0
LA-G871P
Date: Tuesday, March 05, 2019 Sheet 81 of 109
5 4 3 2 1
 5 4 3 2 1

+3.3V_ALW

@0@ PR3 22_0805_5%

PD803

2
1 2 PR892
0_0402_5%
PR4
+3.3V_VDD_DCIN 2 1 2
+20V_TBTA_VBUS_1
PSID circuit, it need with >6KV ESD 2.2K_0402_5%
+20V_LDO_input 1
EMI@ PL3 PR5 PU2

1000P_0402_50V7K
BLM15AG102SN1D_2P 33_0402_5% 1 3 1 2
NB_PSID PS_ID VCC +19.5V_DC_IN

PC11
2 1 1 3 1 2

S
PS_ID <58>
3 BAT54CW_SOT323-3 PR893
PQ2 VOUT 2 22_0805_5%

2
GND

1
FDV301N-G_SOT23-3 +5V_ALW

82P_0402_50V8J
G
2

PC12
RT9058-33GX_SOT89-3

1
PR6

2
100K_0402_1% PC10
PD4 @ESD@ 4.7U_0402_6.3V6M

2
1

@RF@
L03ESDL5V0CG3-2_SOT-523-3 C
2 PQ3 PR7
B LMBT3904WT1G_SC70-3 10K_0402_1%
E

3
1

2
1
PR8

1
15K_0402_1%

2
D D

PD5
S SCH DIO 5A 100V 15UA 0.88V TO227-3
2
1
3
+19.5V_DC_IN
+19.5V_DC_IN_SS S2
S1
PQ9 PQ4
EMI@ PL4 EMZB08P03VL_P_DFN33-8-5 EMZB08P03V_EDFN3X3-8-5
FBMJ4516HS720NT_2P Capacitors on +19.5V_DC_IN net need < 1000pF 1 1
1 2 2 2 +19.5V_SDC_IN

AO3409 P-CHANNEL SOT-23

AO3409 P-CHANNEL SOT-23

1
3 5 5 3

0.022U_0402_25V7K
1M_0402_5%
PR10

PR11
1

PQ5
PC4
499K_0402_1%
0.022U_0402_25V7K
300K_0402_5%

1
1M_0402_5%
PR31

4
1

3
S

PQ11

PC6
4.7K_0805_5%

2
1

1
G

PR12
2

10U_0603_25V6M
1000P_0402_50V7K

0.1U_0402_25V6

2
1

3
S
PC5

PC7

100K_0402_5%
CONN@ PJPDC1

2
1

1
+3.3V_VDD_DCIN
G
7 2
PR13

1
GND2 6

PC8
+3.3V_VDD_DCIN PR15
2

2
GND1 5

PR14
D 100K_0402_5%
2

2
5 4

1
EMI@

@EMI@

4 3 +19.5V_DCIN_JACK
PR32

L2N7002DW1T1G_SC88-6
2

PR16

1
3 2

1
9 1M_0402_5%

49.9K_0402_1%
8 NPTH2
2 1 PR17

100K_0402_5%
NPTH1
1

1
100K_0402_5%

L2N7002DW1T1G_SC88-6
2
1

6
PR33
CVILU_CI0805M1HRC-NH PR46
S1_OVP <82>
0_0402_5% PR18 PR19

2
2
3

PQ1A
1M_0402_5% 0_0402_5%
PR41 2 1 2

L2N7002WT1G_SC-70-3
2
PQ10B
0_0402_5% PR20
2

1
1 2 5 PQ12 D 0_0402_5%

1
6

PQ7
L2N7002WT1G_SC-70-3 2 1 2
L2N7002DW1T1G_SC88-6

1
PR47 D G

L2N7002DW1T1G_SC88-6
4
PQ10A

0_0402_5% 2 S

3
1
1 2 2
+3.3V_VDD_DCIN S
G
PR49

3
0_0402_5%
1

VBUS1_ECOK_R <58,82> PR25

PQ1B
0_0402_5%

2
1

5 1 2
@ PC13 @0@ VBUS2_ECOK_R <58,82> HW_ACAVIN_NB <58,82,84>
0.1U_0402_10V7K PR43 PR24

4
1 2 0_0402_5% 100K_0402_5%

2
L2N7002WT1G_SC-70-3
2

PR22

1
PR42 0_0402_5% D
5

PQ6
0_0402_5% 1 2 2
<58,82,84> HW_ACAVIN_NB 1 2 1 G
P

B 4 S

3
1 2 2 O PQ8
A
G

L2N7002WT1G_SC-70-3
1

PR44 @ PR45
3

0_0402_5% 3 1
<58> DCIN1_EN_R
@ PU3 10K_0402_5%
C MC74VHC1G08DFT2G_SC70-5 C
G
2

2
1
100K_0402_5%

1
PR28

1
100K_0402_5%

0.1U_0402_25V6
1
PR865

PC865

PR27
2

100K_0402_5%
2

2
2

+3.3V_ALW +3.3V_VDD_DCIN

DCIN_AC_Detector PD801
@ PC801 S SCH DIO 5A 100V 15UA 0.88V TO227-3
0.01UF_0402_25V7K 2
1 2 1
3

PR866
0_0402_5% S4 S5
1 2
PQ800 +20V_VBUS_DC_SS PQ801
EMZB08P03VL_P_DFN33-8-5 EMZB08P03V_EDFN3X3-8-5
+3.3V_VDD_DCIN @ PD800 1 1
+19.5V_DC_IN

AO3409 P-CHANNEL SOT-23

3 +3.3V_VDD_DCIN 2 2
+3.3V_VDD_DCIN
3 5 5 3
+19.5V_SDC_IN

0.47U_0402_25V6K
1

1
1

1500P_0402_50V7K
AO3409 P-CHANNEL SOT-23
LM393_P
PR801 PR802

1
PQ803

PQ805
2

PC803

499K_0402_1%
+3.3V_VDD_PIC 300K_0402_5% 300K_0402_5%

4
1

1
499K_0402_1%
3

3
S S
+3.3V_ALW

PR803

PC802
BAT54CW_SOT323-3

PR804
2

2
G G
2 2

100K_0402_5%
PR805

2
1
1.8M_0402_1%

2
1

1
1 2 +3.3V_VDD_PIC +3.3V_VDD_PIC +3.3V_ALW

PR862
D D

1
PR806 PR807
1K_0402_1% 100K_0402_5% PR808
1
422K_0402_1%

100K_0402_5%
LM393_P

100K_0402_5%

2
1

1
@ PR851
102K_0402_1%

PR858

49.9K_0402_1%
L2N7002DW1T1G_SC88-6
@
2

2
1

1
1 2
PR800

PR811
@ PR852

2
PR809

PR810 6 PR812 PR813 100K_0402_5%

100K_0402_5% 0_0402_5% 49.9K_0402_1% 100K_0402_5%
2

PU800A

3
2

6 2

2
8

AS393MMTR-G1_MSOP8
PQ802A
PQ814

L2N7002DW1T1G_SC88-6
EN_PD_HV_1# 2
2

3 2

2
1
D

PQ806B
3 L2N7002WT1G_SC-70-3 PR814

L2N7002DW1T1G_SC88-6
P

(>17.1V) + 1 HW_ACAVIN_NB 2 5 1 2
O HW_ACAVIN_NB <58,82,84>

PQ804A
2 PR857 G

L2N7002DW1T1G_SC88-6
<58,82> VBUS2_ECOK_R
1

-
G

PQ804B
0_0402_5% S 2 PR816 0_0402_5%

4
1 2 1 2 5
220P_0402_50V7K

PR861
24.9K_0402_1%

100P_0402_50V8J

1200P_0402_50V7K
4
1

3
37.4K_0402_1%

0_0402_5%

L2N7002DW1T1G_SC88-6
1
1

1
PR817

PC800

PC804

PR859 0_0402_5%
L2N7002DW1T1G_SC88-6

4
1

1
PQ802B
PR815

PC805

0_0402_5%

2
1 2 5
+3.3V_VDD_PIC
2

6
2

@0@ PR860 PR819

2

PQ806A
B 0_0402_5% <58,82> VBUS1_ECOK_R 100K_0402_5% PR820 B

2
1 2 2 1 2
+3.3V_ALW2 EN_PD_HV_1 <44,82,84>
1

@0@
PR856 0_0402_5%

1
1 2 0_0402_5%

@ PC814
2

PR853 0.1U_0402_10V7K
5

0_0402_5% PR818
1 2 1 1 2
P

<44,82,84> EN_PD_HV_1 B 4
1 2 2 O 0_0402_5%
A
G

EMI Part +20V_TBTA_VBUS_1 PR854

3

EMI@ PL801 0_0402_5% @ PU801 @ PR855

5A_Z80_20M_0805_2P MC74VHC1G08DFT2G_SC70-5 10K_0402_5%
+20V_TBTA_VBUS 1 2
2

+20V_TBTA_VBUS_1
1 2
PL800
5A_Z80_20M_0805_2P
100P_0402_50V8J

100P_0402_50V8J

PQ807
100K_0402_5%

EMI@
1
1000P_0402_50V7K

L2N7002WT1G_SC-70-3
0.1U_0402_25V6
1

1
@EMI@ PC806

EMI@ PC807

@EMI@ PC808

PR823

EMI@ PC809

3 1 +3.3V_ALW +3.3V_ALW
S

<58> DCIN2_EN_R
2

2
2

1
G
2
1

100K_0402_5%

@ PR825
1
100K_0402_5%

@ PR824 100K_0402_5%
+3.3V_ALW
PR822

PR826 100K_0402_5%
PR821

0_0402_5%

2
1 2
<58,82> VBUS1_ECOK_R
2

1
2

1 2
<58,82> VBUS2_ECOK_R
PR828 CMOUT <84>
+20V_VBUS_DC_SS PR827 100K_0402_5%
0_0402_5% AC_DISC# <58>

2
+20V_TBTA_VBUS_1 +3.3V_ALW +3.3V_VDD_PIC
+3.3V_ALW
PR829
0_0402_5%
1 2

L2N7002DW1T1G 2N SC88-6
+3.3V_VDD_DCIN

L2N7002DW1T1G 2N SC88-6

L2N7002DW1T1G 2N SC88-6
6

3
+3.3V_ALW

PQ810A
PR830 D D D D

PQ811B
100K_0402_5% 2 5 2 5
S1 OVP

PQ810B
499K_0402_1%

499K_0402_1%

G G G G
1

<58,82,84> HW_ACAVIN_NB
102K_0402_1%

2
@ PR870

PR831

PD802 S S S S
L2N7002DW1T1G 2N SC88-6

4
PR832

PQ811A
30MA_30V_0.5UA_0.4V_SOD323-2 PR833

L2N7002DW1T1G 2N SC88-6
1 2 100K_0402_5%
2

+3.3V_ALW
PQ808A

PR836 PR834 D
L2N7002DW1T1G 2N SC88-6
1

LM393_P 2

1500P_0402_50V7K
0_0402_5% 0_0402_5%
1 2 S1_OVP 1 2 +3.3V_ALW
PR835 <44,82,84> EN_PD_HV_1
G
S1_OVP <82>

1
47K_0402_1%

PC810
LM393_P
3

D S PR838
1

PU800B
3

1
PQ808B

5 100K_0402_5%
2

2
8

AS393MMTR-G1_MSOP8 PR840 G PR839

5 0_0402_5% 100K_0402_5% @
P

PROCHOT#_CHG <84>

2
+ 7 1 2 5 PQ813B S
4

A 6 O @0@ PR841 A
10U_0402_6.3V6M

2.2U_0402_25V6M

L2N7002WT1G_SC-70-3
2

-
1

1
L2N7002DW1T1G_SC88-6 0_0402_5% D D
97.6K_0402_1%

100P_0402_50V8J

PQ812
1 2 2 2
37.4K_0402_1%

PQ809A
4
1

1
PR842

PC811

PC812

PC813

G L2N7002DW1T1G 2N SC88-6 G
3
PR843

PR844 D S

3
1 2 5 S
<58,82,84> HW_ACAVIN_NB
2

1
G PQ809B
0_0402_5% L2N7002DW1T1G 2N SC88-6
2

S
4
6

1 2
OVP setting:5.4V PQ813A @0@ PR845

https://Dr-Bios.com
L2N7002DW1T1G_SC88-6 2 0_0402_5%
EN_PD_HV_1 <44,82,84>

DELL CONFIDENTIAL/PROPRIETARY
1

PR846
10K_0402_5%
Compal Electronics, Inc.
Title
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DC Connector/1Type-C PD Selector
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Size Document Number Rev
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1.0
LA-G871P
Date: Tuesday, March 05, 2019 Sheet 82 of 109

5 4 3 2 1
 5 4 3 2 1

+COINCELL
COIN RTC Battery
PD1 ESD@ PD2 ESD@
D CEST523NC5VB__SOT-523-3 CEST523NC5VB__SOT-523-3 RTC_DET# <8> D

1
1

1
PR2
1K_0402_5%
+3.3V_RTC_LDO

1
D

+Z4012 2
2 PQ13

3
G L2N7002WT1G_SC-70-3

10M_0402_5%
S

3
1
EMI@ PL1
FBMJ4516HS720NT_2P

PR9
3

2
1 2
Primary Battery Connector

2
EMI@ PL2
FBMJ4516HS720NT_2P
+RTC_CELL
+13.2VB_PBATT_C +3.3V_ALW
1 2 +13.2VB_BATT
CONN@ PBATT1 PD3

1
1 1 2
1 2 BAS40CW_SOT323-3
2

1
3 PR38
3 PBAT_SMBCLK_C PBAT_CHARGER_SMBCLK <58,84>
4 100_0402_5% PC3
2200P_0402_50V7K

4 5 PBAT_SMBDAT_C 1 2 1U_0402_25V6K
27P_0402_50V8J

PBAT_CHARGER_SMBDAT <58,84> PR1

2
5 6 PBAT_PRES#_C
PC2

6
1

7 PR39 100K_0402_5%
EMI@ PC1

2
7 8 100_0402_5%
8 9 1 2
PBAT_PRES# <58,84>
2

9 10
@RF@

10 11 PR40
GND1 12 100_0402_5% CONN@ JRTC1
GND2 1 3
DEREN_40-42251-01001RHF +COINCELL 2 1 G1 4
2 G2
ACES_50271-0020N-001

GND

C C

B B

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Battery Connector/ RTC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Re v
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-G871P
Date: Tuesday, March 05, 2019 Sheet 83 of 109

5 4 3 2 1
 A B C D

EMI@ PL700

1UH_PCMB051H-1R0MS_8A_20%
+19.5V_AC 1 2
+19.5V_SDC_IN +19.5V_CHARGER
PR700
0.01_1206_1% @JUMP@ PJP700

1 4 1 2
+13.5VB
2 3 PAD-OPEN 4x4m

10U_0805_25VAK

10U_0805_25VAK

10U_0805_25VAK
SMF4L22A_SOD123FL2

0.1U_0402_25V6

2200P_0402_50V7K
1

1
PC702

PC703

@ PC704
PD701

@EMI@ PC700

@EMI@ PC701
1

2
2

2
1 1

CSIN_CHG_R
CSIP_CHG_R

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M
1

15U_B2_25VM_R100M
1

1
PC707

PC708

PC709

PC710
+

PC715
footprint change to
SMF4L22A_SOD123FL2

2
2

10U_0603_25V6M
1

15U_B2_25VM_R100M
1

1
+

@ PC705

PC706
PR701 PR702
1_0603_1% 1_0603_1%

2
2
+13.5VB

2200P_0402_50V7K
2

0.1U_0402_25V6
1

1
@EMI@ PC720

@EMI@ PC721
PC719
4.7U_0402_6.3V6M

2
1 2

1U_0402_25V6K

1U_0402_25V6K

1U_0402_25V6K
82P_0201_50V8J

82P_0201_50V8J

82P_0201_50V8J

2200P_0201_16V7K

2200P_0201_16V7K
0.1U_0201_25V6K

0.1U_0201_25V6K

0.1U_0201_25V6K

0.1U_0201_25V6K
1

1
PC725

PC726

1
PC728

PC729

PC730

PC731

PC732

PC733

PC734

PC735

PC722

PC723
1
2

2
PC727

2
0.47U_0402_25V6K

1BST1_CHG_R2
Not to change short pad

RF@

RF@

RF@

RF@

RF@

RF@

RF@

RF@

@RF@

@RF@
+19.5V_SDC_IN PR703
0_0603_5%
1 2 ADP_CHG
PD700
2 1
+19.5V_DC_IN_SS
1

30MA_30V_0.5UA_0.4V_SOD323-2
PR705
PR704

22P_0201_25V8

22P_0201_25V8
442K_0402_1%

47P_0201_25V8J

47P_0201_25V8J
100P_0201_25V8J

100P_0201_25V8J
PD702
+13.5VB 2 1 3.3_0603_1% 1 1 RF demand

1
2 2

PC756

PC757

PC758

PC759

PC760

PC761
2

2
ACIN_CHG
30MA_30V_0.5UA_0.4V_SOD323-2

CSIP_CHG

CSIN_CHG

BOOT1_CHG

UG1_CHG

LX1_CHG

LG1_CHG
PD704

2
2 2
1
1

2 1

RF@

RF@

RF@

RF@

RF@

RF@
PC736 PR706
+20V_VBUS_DC_SS 0.1U_0402_25V6 100K_0402_5%
PR707
4.7_0603_5%
RB520SM-30T2R_EMD2-2 1 2 VDD_CHG
2

PR708
1_0805_5%~D @0@ PR746 PU700

16

15

14

13

12

11

10

33
9
0_0402_5% ISL9538BHRTZ-T_TQFN32_4X4
PC737 HW_ACAVIN_NB 1 2

BOOT1

UGATE1

PHASE1

LGATE1
CSIN

PAD
ADP

CSIP

ASGATE
1

2.2U_0402_25V6M
+13.5VB_VCHGR

9
1 2 PR709 DCIN_CHG
0_0402_5% 17 8 VDDP_CHG 1 2 UG1_CHG 1 8 LG1_CHG LG2_CHG 8 1 UG2_CHG PQ702

D1_3

D1_3
1 2 DCIN VDDP G1 G2 PL701 G2 G1 PR711 EMZB08P03V_EDFN3X3-8-5
1 2 VDD_CHG 18 7 LG2_CHG PC738 LX1_CHG 2 7 2.2UH_PCMB103T-2R2MS_13A_20%7 2 LX2_CHG 0.005_1206_1% 1
VDD LGATE2 S1/D2 D2/S1_3 D2/S1_3 S1/D2
2

<91> ACIN_CHG LX2_CHG

4.7U_0402_6.3V6M 2 +13.2VB_BATT
PC739 PR710 @0@ PR712 19 6 3 6 1 2 6 3 1 4 3 5
4.7U_0402_6.3V6M 0_0402_5% ACIN PHASE2 D1_1 D2/S1_2 D2/S1_2 D1_1
100K_0402_1%
1 2 OTGEN/CMIN_CHG 20 5 UG2_CHG 4 5 5 4 2 3

S2

S2
OTGEN/CMIN UGATE2 D1_2 D2/S1_1 LX1_CHG LX2_CHG D2/S1_1 D1_2
1

4
<91> ACAV_IN1 <58,83> PBAT_CHARGER_SMBDAT
1 PR713 2 0_0402_5% SDA_CHG 21 4 BOOT2_CHG 1 2 BST2_CHG_R
1 2

10

10
SDA BOOT2

1
4.7_1206_5%

4.7_1206_5%

10U_0603_25V6M

10U_0603_25V6M
1

PQ703 1 PR715 2 0_0402_5% SCL_CHG 22 3 VSYS_CHG PC740 PR714 PQ700 PQ701

EMI@ PR717

EMI@ PR718
<58,83> PBAT_CHARGER_SMBCLK SCL VSYS
1

1
D
PR716 0.47U_0402_25V6K 4.7_0603_5% AOE6936_DFN5X6E8-10 AOE6936_DFN5X6E8-10

PC741

PC742
OTGPG/CMOUT

2 154K_0402_1% 1 PR719 2 PROCHOT#_CHG 23 2 CSOP_CHG

<14,58,88> PROCHOT#
AMON/BMON

<58> AC_DIS PROCHOT# CSOP

G 0_0402_5%

1SNUB1_CHG 2

1SNUB2_CHG 2

2
1

CSON_CHG
BATGONE

S 24 1

4700P_0402_25V7K
<82> PROCHOT#_CHG
3

ACOK CSON

1
L2N7002WT1G_SC-70-3 BGATE PR721
CMOP
PROG

ACOK_CHG
PSYS

VBAT

1 2 0_0402_5%

@ PC743
1 2
+13.5VB

680P_0402_50V7K

680P_0402_50V7K

2
PR720 PR722 0_0402_5%

BGATE_CHG
2

1M_0402_1%
OTGPG/CMOUT_CHG
25

26

27

28

29

30

31

32

@ PR723 PC744

EMI@ PC746

EMI@ PC747
100K_0402_1% 10P_0402_50V8J 1 2
PR724 1 2 1 2
105K_0402_1% COMP_CHG

AMON/BMON_CHG

PSYS_CHG
2 PR725 1 PROG_CHG

VBAT1_CHG

BGATE_CHG

2
3
100K_0402_1% @ PC745 3

1 2 BATGONE_CHG
<58,83> PBAT_PRES# 0.1U_0402_25V6
PR726
100K_0402_1%
1 2
+3.3V_ALW
PR727 0_0402_5%
<82> CMOUT
1 2 @ PC748
1U_0402_25V6K
@0@ PR745 0_0402_5% 1 2
PROCHOT# 1 2

PR733
1_0603_1%
1 2 CSOP_CHG_R
PSYS R on CPU Controller site
499_0402_1%
1
PR728

0.1U_0402_25V6
560P_0402_50V7K

1
1
PC750

PC752
1

1
@ PC749

1U_0402_25V6K
0_0402_5%

0_0402_5%

0_0402_5%

1 2 CSON_CHG_R
PR729

PR743

PR731
2

2
2

PR734
0.01UF_0402_25V7K

LM393_P
1

1_0603_1%
PC751

@0@ PR735
1 2 0_0402_5%
I_BATT

I_ADP
2

1 2
PC753
0.22U_0402_25V6K PR736
<58,88>
I_SYS

0_0402_5% PC754
<44,82> EN_PD_HV_1
1 2 3 0.1U_0402_10V7K
1 2
1

5
<58>

<58>
I_BATT

1 2 2
I_ADP

<58,82> HW_ACAVIN_NB

1
1 2 1 PR740

100K_0402_1%

P
PR737 PR741 IN1 4 1 2

PR739
ACAV_IN1 1 O ACAV_IN <58,79,91>
PR738 0_0402_5% PD705 2 2
Close to EC ADP_I pin +13.2VB_BATT IN2

G
1

4 100_0402_5% BAT54CW_SOT323-3 0_0402_5% 4

1
100K_0402_1%
@ PC755 0_0402_5% PU701

PR744
0.1U_0402_25V6 MC74VHC1G08DFT2G_SC70-5
2

For IT8010 voltage leakage issue

2
Compal Electronics, Inc.
DELL CONFIDENTIAL/PROPRIETARY Title
Charger

https://Dr-Bios.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 84 of 109
A B C D
 A B C D E

PR119
0_0402_5%
PGOOD_3V 1 2
PGOOD_5V ALW_PWRGD_3V_5V <11,63>
1 2

1 PR120 1
0_0402_5%

PR102 +13.5VB
499K_0402_1%
+13.5VB ENLDO_3V5V 1 2

JUMP@ PJP100 PR100 PC102 3VALWP

1
+13.5VB_3V BST_3V BST_3V_R
TDC 6.51A

499K_0402_1%
1 2 1 2 1 2

PR103
PAD-OPEN 1x2m~D 0_0603_5% 0.1U_0402_25V6 Peak Current 9.3 A
2200P_0402_50V7K

10U_0603_25V6M

10U_0603_25V6M
OCP Current 11.5 A

1
27P_0201_25V8

82P_0402_50V8J
0.1U_0402_25V6

PU100

2
1

1
RF@ PC100

RF@ PC103

RF@ PC131

PC133

PC134

PC105

PC104

IN4

IN3

IN2

IN1

BS
1

1
RF@ PC101

LX_3V 6 20 PL100

2
LX1 LX3 1.5UH_9A_20%_7X7X3_M
2

RF@ 2
LX_3V

100P_0402_50V8J

100P_0402_50V8J
7 19 1 2
GND1 LX2 +3.3V_ALWP
RF@

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
@EMI@ PR106
8 SY8288BRAC_QFN20_3X3 18 PR104
GND2 GND4

4.7_1206_5%
0_0402_5%
9 17 LDO_3V 1 2
RF demand PG LDO +3.3V_ALW2

27P_0402_50V8J
PC106

PC107

PC108

PC109

PC110

PC129

PC161

PC162

100P_0402_50V8J
PC135

PC136
10 16
NC1 NC3

1
PR105

OUT

NC2

2
EN2

EN1
21 1 2 +3.3V_RTC_LDO @ @

FF
GND3

1 SNUB_3V
2

2
PR107 0_0402_5%

11

12

13

14

15

680P_0402_50V7K

RF@

RF@
100K_0402_5% 3.3V LDO 150mA~300mA

@EMI@ PC112
2 1 2 2
+3.3V_ALW

2
ENLDO_3V5V
PC111 Vout is 3.234V~3.366V
4.7U_0402_6.3V6M

2
PGOOD_3V

JUMP@ PJP102
PC113 PR108 +3.3V_ALWP 1 2 +3.3V_ALW
1000P_0402_50V7K 1K_0402_5% 1 2
3V5V_EN FB_3V 1 2 1 2 JUMP_43X118

+13.5VB JUMP@ PJP103

+5V_ALWP 1 2 +5V_ALW
JUMP@ PJP101 PR111 PC114 1 2
1 2 +13.5VB_5V BST_5V 1 2 BST_5V_R 1 2 JUMP_43X118

PAD-OPEN 1x2m~D 0_0603_5% 0.1U_0402_25V6

10U_0603_25V6M

10U_0603_25V6M
2200P_0402_50V7K
27P_0201_25V8

82P_0402_50V8J
0.1U_0402_25V6

1
RF@ PC115

RF@ PC116

RF@ PC132

PC139

PC140

PC117

PC118

PU102
1

1
RF@ PC141

IN4

IN3

IN2

IN1

BS
2

LX_5V 6 20 PL101
2

RF@ 2

LX1 LX3
100P_0402_50V8J

100P_0402_50V8J

1.5UH_9A_20%_7X7X3_M
LX_5V
RF@

7 19 1 2 +5V_ALWP
3 GND1 LX2 3

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
4.7_1206_5%
@EMI@ PR112
8 SYV828CRAC_QFN20_3X3 18
GND2 GND4

27P_0201_25V8
9 17 1 2
RF demand PG VCC

100P_0402_50V8J

100P_0402_50V8J
PC120

PC121

PC122

PC123

PC124

PC130

PC163

PC164

PC137

PC138

PC142
1 SNUB_5V

1
10 16 PC119
NC1 NC2 2.2U_0402_6.3V6M
OUT

LDO

2
EN2

EN1

21 @ @
FF

RF@ 2

RF@ 2
GND3

680P_0402_50V7K
@EMI@ PC125

RF@
11

12

13

14

15

@ PR113
100K_0402_5% 5V LDO 150mA~300mA

2
1 2
+3.3V_ALW +5V_ALW2
ENLDO_3V5V

3V5V_EN

PGOOD_5V
PC126
Not to change short pad
4.7U_0402_6.3V6M 5VALWP
2

1 2
<58> ALWON
PR114 TDC 7.54 A
0_0402_5%
Peak Current 7.9A
3V5V_EN
OCP Current 11.5 A
1M_0402_1%
1

1
PR116

PC127 PR117
PC128 1000P_0402_50V7K 1K_0402_5%
FB_5V 1 2 1 2
4.7U_0402_6.3V6M
2
2

4 4
EN1 and EN2 dont't floating

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +5V_ALW/3.3V_ALW
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 85 of 109
A B C D E
 5 4 3 2 1

D D

+13.5VB
JUMP@ PJP202
1 2 +13.5VB_DDR
PU200
PAD-OPEN 1x2m~D RF@ RF@
27P_0201_25V8
10U_0603_25V6M

10U_0603_25V6M

82P_0402_50V8J
100P_0201_25V8J

0.1U_0402_25V6
1

+3.3V_ALW 10 19 PR202 PC204

IN OT 4.7_1206_5% 680P_0402_50V7K
PC200

PC201

RF@ PC230

RF@ PC231

RF@ PC202

RF@ PC203

13 18 PR203 PC205 1 2 SNUB_DDR1 2

2

BYP PG
1U_0201_6.3V6M

1U_0201_6.3V6M
VCC_DDR 14 12 1
0_0603_5%
BS_DDR 2
0.1U_0402_25V6
BS_DDR_R
1 2
+1.2V_DDRP
VCC BS
1

1
PC226

PC206
C PL201 C

1
LX_DDR

2.2U_0402_6.3V6M
4 11 1 2
VTTGND LX

PC207
1UH_PCMB063T-1R0MS_12A_20%
2

FB_DDR

330P_0402_50V7K
9 16
RF demand
2
PGND FB

1
102K_0402_1%
1
+1.2V_DDRP

PC208

PR204
15 8 PC209
+3.3V_ALW SGND VDDQSNS

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

10U_0603_10V6M

10U_0603_10V6M

2200P_0402_50V7K

100P_0402_50V8J
22U_0603_6.3V6M
R1

@EMI@ PC216

@EMI@ PC217
7 1 2

2
VLDOIN

1
PC210

PC211

PC212

PC213

PC214

PC223
2
1

ILMT_DDR 17 6
@0@ PR205 ILMT VTT +0.6VSP

2
The current limit is 0_0402_5% 1 5
S5 VTTSNS
set to 8A, 12A or 16A

1
VTTREF_DDR

100K_0402_1%
2 3
SIO_SLP_S4#_R
2

when this pin is pull S3 VTTREF

PR206
ILMT_DDR R2

1U_0201_6.3V6M

1U_0201_6.3V6M

22U_0603_6.3V6M
low, floating or pull
0.6V_DDR_VTT_ON_R

1
PC227

PC218
high SY8210AQVC_QFN19_4X3

PC219
+1.2V_DDR OCP set 12A

2
1

2
@0@ PR207
0_0402_5% Layout for Pin4,9,15
VTTGND , PGND seperate GND via

27P_0201_25V8

100P_0402_50V8J

100P_0402_50V8J
2

PC228

PC224

PC225
PGNE Cin_cap shape GND via

1
SGND alone GND

RF@2
RF@

RF@
1 2
B <11,17,79,87> SIO_SLP_S4# B
0.1U_0402_10V7K

PR208
1M_0402_5%
1

0_0402_5%
@ PC221
@ PR209

+1.2V_DDRP +1.2V_MEM +0.6VSP +0.6V_DDR_VTT

2

JUMP@ PJP200 JUMP@ PJP201

2

JUMP_43X118 JUMP_43X39
1 2 1 2
PR210 1 2 1 2
0_0402_5%
1 2
<23> 0.6V_DDR_VTT_ON
1M_0402_5%

0.1U_0402_10V7K
1

+1.2V_DDR 0.6Volt +/- 5%

PR212

@ PC222

TDC 5.433A TDC 1.05A

2

Mode S3 S5 VOUT VTT Peak Current 7.761A Peak Current 1.5A

Normal H H on on
2

Stadby L H on off OCP Current 12A Fix by IC OCP Current 2A (fix)

Shutdown L L off off
Note: S3 - sleep ; S5 - power off

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +1.2V_MEN/+0.6V_DDR_VTT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 86 of 109
5 4 3 2 1
 5 4 3 2 1

Follow WHL RVP PR429

<6,17> CPU_C10_GATE#
1
0_0402_5%
2 +3.3V_ALW
LPM LOGIC VID1 LOGIC VID0 LOGIC OUTPUT VOLTAGE

1
1.0V_PRIM_PWRGD <58> @0@
PR404
PR313 JUMP@ PJP302 1 2
0 X X 0(LPM)
<9,11,17,66,79> SIO_SLP_S0# 0_0402_5%
1 2
+3.3V_ALW +1.05VALWP 1
1 2
2 +1.0V_PRIM SY8057BQDC 1 0 0 0.80
@0@ PR425 JUMP@ PJP401

2
100K_0402_5% JUMP_43X118 0_0402_5% JUMP_43X79
1 2
1 0 1 0.95
@ PC350 PR402 +1VS_VCCIOP 1 2 +1.0VS_VCCIO 1 1 0 1.00
1 2 RF@ PR303 RF@ PC302 <17,58,59,78> RUN_ON 1 2
4.7_1206_5% 680P_0402_50V7K

LPM_1VS_VCCIO
SNUB_1.05VALWP 1 1 1 1.05

EN_1VS_VCCIO
+13.5VB 0.022U_0402_25V7K 1 2 1 2 0_0402_5%

1
0.1U_0402_25V6
JUMP@ PJP301 PU301

@ PC402
+13.5VB_1.05VALWP
1 2 2 9 PR304 PC304 PR403

100P_0402_50V8J
IN1 PG 0_0603_5% 0.1U_0402_25V6 1M_0402_1%
BST_1.05VALWP BST_1.05VALWP_R

2
82P_0201_50V8J

82P_0201_50V8J

10U_0603_25V6M

10U_0603_25V6M
PAD-OPEN 1x2m~D 3 1 1 2 1 2 PL301

27P_0201_25V8
IN2 BS

1
0.68UH_7.9A_20%_5X5X3_M

PC317

PC318

PC301

PC305

PC306
LX_1.05VALWP
+1.05VALWP

2
4 6 1 2 @ PL405

RF@ PC303
IN3 LX1

13

14

15

16

17
3A_Z120_40M_0603_2P

330P_0402_50V7K
2

2
5 19 1 2 PU401
Vin=3~17V

100P_0402_50V8J

100P_0402_50V8J
IN4 LX2

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
RF@
+1.0VS_VCCIO

RF@

RF@

EN

LPM

PGND1

PGND2

TP
1

1
D 7 20 D

PC307

RF@ PC315

RF@ PC316
GND1 LX3 JUMP@ PJP403 TDC 2.1 A
+5V_ALW

PC308

PC309

PC310

PC311
FB_1.05VALWP VIN_1VS_VCCIO

22.1K_0402_1%
1
8 14 1 2 12 1
+1VS_VCCIOP Peak Current 4 A

2
GND2 FB PVIN2 VOS

PR306
VCC_1.05VALWP
PR312 18 17
PAD-OPEN1x1m
PL402 OCP Current 6 A Fix by IC

10U_0603_10V6M

10U_0603_10V6M
GND3 VCC

1
22K_0402_1% 1UH_1277AS-H-1R0N-P2_3.3A_30%
EN_1.05VALWP LX_1VS_VCCIO TYP MAX

1
1 2 11 10
+3.3V_ALW 11 2 1 2
+1VS_VCCIOP

PC403

PC404
1K_0402_5%
<11,78,87> PCH_PRIM_EN

2
1
EN NC1 PVIN1 SW1
Choke DCR 48.0mohm

PR308
1 13 12 PC313

2
ILMT NC2

1
0.1U_0402_25V6

22U_0603_6.3V6M

22U_0603_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
PR302 2.2U_0402_6.3V6M SY8057BQDC_QFN16_3X3

PC360

1
1M_0402_1% 15 16 10 3

PC406

PC407

PC425

PC426
+3.3V_ALW BYP NC3 AVIN SW2

2
21
2

2
PAD

1U_0201_6.3V6M

1U_0201_6.3V6M
2

100P_0402_50V8J
PC312

PC314

SNUB_1VS_VCCIO
VID0_1VS_VCCIO

47P_0402_50V8J
1

1
0.1U_0402_25V6
SY8286RAC_QFN20_3X3 PR311 9 4

PC408

PC405
PC409
VID0 PG @EMI@ PR405
29.4K_0402_1%

AGND
4.7_0603_5%
RF demand

VID1
+3.3V_ALW

FBS
@ PR413 PR414

SS
RF@

RF@
@EMI@

2
10K_0402_1% 10K_0402_1%
VID0_1VS_VCCIO

5
1

1
@0@ @EMI@ PC401
VID1_1VS_VCCIO +1VS_VCCIOP

SS_1VS_VCCIO
PR307
+1.0V_PRIM

FBS_1VS_VCCIO
VID1_1VS_VCCIO
0_0402_5% 470P_0402_50V7K

2
TDC 3.642A

1
ILMT_1.05VALWP
2

1
Not to change short pad
Peak Current 5.203A @0@ PR421
1

@0@
OCP Current 9 A Fix by IC PR415
10K_0402_1%
@ PR416
10K_0402_1%
0_0402_5%

TYP MAX

2
1
PR310

0_0402_5%
2

2
Choke DCR 11.0mohm , 12.0mohm 1 2

PR427
0_0402_5%
VCCIO_SENSE <17>
2

PR422
0_0402_5% Sense net-name follow HW site (Need to check)

2
1 2
VSSIO_SENSE <17>
PR412
0_0402_5%
The current limit is set to 6A, 9A or 12A when this pin
is pull low, floating or pull high

PR430
+1.8V_PRIM 0_0402_5%
TDC 1.56 A <9> VR_LPM_R#
1 2
+3.3V_ALW
Peak Current 2.229 A
OCP Current 3.2 A f i x by I C Wake on Voice function

1
@ PR410
10K_0402_1%
C C
22U_0603_6.3V6M

@ PL502

2
1

JUMP@ PJP502
PC530

3A_Z120_40M_0603_2P
1 2 1 2 LPM LOGIC VID1 LOGIC VID0 LOGIC OUTPUT VOLTAGE
+1.8VALWP +1.8V_PRIM
2

JUMP@ PJP402
JUMP@ PJP501
PAD-OPEN1x1m
JUMP_43X79
0 X X 0.75(LPM)

LPM_1V_PRIM_CORE
VIN_1.8VALW PR406
1 2 1 2
+3.3V_ALW 1 2 +1.0V_PRIM_COREP 1 2 +1.0V_PRIM_CORE 1 0 0 0.9

EN_1V_PRIM_CORE
Imax= 2A, Ipeak= 3A <11,78,87> PCH_PRIM_EN SY8057CQDC
PAD-OPEN1x1m
FB=0.6V 1 0 1 0.95
22K_0402_1%

1
0.1U_0402_25V6
1 1 0 1.00

PC411
@ PR407
PU501
PL501 1M_0402_1%
1 1 1 1.05

2
1UH_1277AS-H-1R0N-P2_3.3A_30%
LX_1.8VALW
PR314 4 3 1 2
+1.8VALWP

2
0_0402_5% IN LX @ PL406
1.0V_PRIM_PWRGD
1

1 2 5 2

13

14

15

16

17
3A_Z120_40M_0603_2P
Follow WHL
68P_0402_50V8J

PG GND RF@ PR502 1 2 PU402

Vin=3~17V
1

22U_0603_6.3V6M

22U_0603_6.3V6M
6 1 (576715_WHL_U_DDR4_HDK_HW_Design_Kit_Rev0p5)
PC503

EN

LPM

PGND1

PGND2

TP
FB EN
1

1
4.7_0603_5%

PC501

PC504
1SNUB_1.8VALW

PR501 JUMP@ PJP404

VIN_1V_PRIM_CORE
2

RT8097ALGE_SOT23-6
+3.3V_ALW 1 2 12 1
+1.0V_PRIM_COREP
2

2
PR504 20K_0402_1% PVIN2 VOS
EN_1.8VALW
<11,78,87> PCH_PRIM_EN 1 2
Rup +3.3V_ALW PL404
2

10U_0603_10V6M

10U_0603_10V6M
1UH_1277AS-H-1R0N-P2_3.3A_30%
PAD-OPEN1x1m LX_1V_PRIM_CORE

1
0_0402_5% 11 2 1 2
+1.0V_PRIM_COREP

PC412

PC413
1

RF@ PC506 PVIN1 SW1

1

@ PR505 @ PC505

22U_0603_6.3V6M

22U_0603_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
1M_0402_1% 680P_0402_50V7K SY8057CQDC_QFN16_3X3
2

1
.1U_0402_16V7K 10 3

PC424

PC415

PC427

PC428
2

AVIN SW2
FB_1.8VALW Rup
2

2
1SNUB_1V_PRIM_CORE
1

1
100P_0402_50V8J
2200P_0402_50V7K
9 4

47P_0402_50V8J
VID0 PG
1

1
0.1U_0402_25V6
RF@ PR409
+1.0V_PRIM_CORE

PC417

PC416
PC418

PC414
PR417 PR418
Rdown

VID0_1V_PRIM_CORE
TDC 2.237 A

1
AGND
PR506 10K_0402_1% 10K_0402_1% 4.7_0603_5%

VID1

0_0402_5%
2

FBS
10K_0402_1%

SS
Note: Peak Current 3.195A

PR315
VID0_1V_PRIM_CORE

2
RF@

RF@
@EMI@

@EMI@
2

When design Vin=5V, please stuff snubber VID1_1V_PRIM_CORE OCP Current 6.8 A Fix by IC

5
to prevent Vin damage TYP MAX

2
RF@ PC419

FBS_1V_PRIM_CORE
Choke DCR 48.0mohm

1.0V_PRIM_PWRGD
VID1_1V_PRIM_CORE
1

SS_1V_PRIM_CORE
680P_0402_50V7K

2
@0@ PR408
@ PR419 @ PR420 0_0402_5%
Vout=0.6V* (1+Rup/Rdown) 10K_0402_1% 10K_0402_1% 1 2
<18> CORE_VID0

2
@0@ PR411
0_0402_5% PR423
1 2 1 2
<18> CORE_VID1
0_0402_5%

1M_0402_1%

1
PR428
@ PR424
100K_0402_1%
@

2
B B

2
+2.5V_MEM
TDC 0.645A by power budget
AP7361 U-DFN3030-8 Pd limit=1.7W
Peak loading=0.921A.
JUMP@ PJP505
VIN_2.5V_MEM
Pd=(3.3-2.5)*0.921=0.7368W < 1.7W
1 2
+3.3V_ALW OCP Current 1.5 A f i x by I C
PAD-OPEN1x1m
4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

PU503
1

EM1109V-AD_DFN3308-8_3X3
PC514

@ PC517

9 JUMP@ PJP506
GND2 VOUT_2.5V_MEM
Downsize from 0603 to 0402 1 1 2
2

8 OUT +2.5V_MEM
1

IN 2
NC1 PAD-OPEN1x1m
1

7
NC3 3 PR515 PC515
A 6 ADJ/NC 21.5K_0402_1% 0.01UF_0402_25V7K A
2

NC2
1

PR513 4
EN_2.5V_MEM PC516
2

1 2 5 GND1
<11,17,79,86> SIO_SLP_S4# EN 22U_0603_6.3V6M
ADJ_2.5V_MEM
2

0_0402_5%
1

@ PC513
@ PR514 .1U_0402_16V7K PR516
2

1M_0402_1% 10K_0402_1%
intel needs PD 100K for PCH GLITCH ISSUE MITIGATION
2

(pull-down on HW site )
2

DELL CONFIDENTIAL/PROPRIETARY

https://Dr-Bios.com
Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1VALWP/VCCIO/PRIM_CORE/1.8V/2.5V
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-G871P
Date: Tuesday, March 05, 2019 Sheet 87 of 109

5 4 3 2 1
 5 4 3 2 1

+1.0V_VCCST
VCC_SA U42
PR602 TDC 4.0A

0.1U_0402_25V6
1 2

1
45.3_0402_1%
+5V_ALW Peak Current 6A

75_0402_1%

100_0402_1%

PC602
PR605
PR601

PR604
0_0402_5% OCP current 10A

2
PR603
@ 1 2
+13.5VB_CPU Choke DCR 6.2 m ohm

2
49.9_0402_1%
1 2PR618 0_0402_5%

4.7U_0402_6.3V6M
<15> VIDSCLK

1U_0402_25V6K
1 2

1
PC603
<15> VIDALERT_N 0_0402_5% PR625 JUMP@ PJP603

PC604
1 2
D
<14,58,84> PROCHOT#
PR678
100_0402_1%<15> VIDSOUT 1 2
+13.5VB_VCCSA +13.5VB D

2
10_0402_1% PR626

2
1 2 1 2 PAD-OPEN1x1m

PC605 47P_0402_50V8J PR612 1.91K_0402_1%

+3.3V_RUN 1 2
+13.5VB_VCCSA
<11> PCH_PWROK 1 2
PR614 0_0402_5% 1 2
1 2

SVID_ALERT#_PWR_CPU
<59> IMVP_VR_ON
PH601 near PU610 MOS Side PR608

VR_ENABLE_CPU_CORE
PR616 0_0402_5%

VR_READY_CPU_CORE
100K_0402_5%

VR_HOT#_CPU_CORE

SVID_DAT_PWR_CPU
SVID_CLK_PWR_CPU
PH601 1 2

PROG2_CPU_CORE
PROG1_CPU_CORE

10U_0603_25V6M

10U_0603_25V6M

82P_0201_50V8J
PR610

VIN_CPU_CORE
470K_0402_5%_B25/50 4700K

27P_0201_25V8
VCC_CPU_CORE
10K_0402_1% PR620 0_0402_5%

1
PR611

PC612

PC608

PC609

PC610
1 2 1 2 @ PR613 1 2
<58,84> I_SYS
97.6K_0402_1% 9.31K_0402_1%
1 2 1 2 PR693

2
PR631 PC613 11.8K_0402_1%
1 2

RF@

RF@
27.4K_0402_1% 330P_0402_50V7K
1 2

PSYS_CPU_CORE
PC614 PR617 Low noise MLCC
2200P_0402_50V7K 4.3K_0402_1% PSYS R on CPU site
UG_SA
1 2 1 2

40
39
38
37
36
35
34
33
32
31
PU602
@ PC616 PR619 2.2_0603_5%

VR_ENABLE
VR_READY

SCLK

SDA
VCC
VIN
VR_HOT#

ALERT#

PROG1
PROG2
68P_0402_50V8J BST_SA_R 1 2
1 2 @ PC617 @ PR621
PU614

1
1200P_0402_50V7K 316_0402_1% 1 30 PWM_C_SA PC611
PSYS PWM_C

1
1 2 1 2 IMON_B_IA 2 29 FCCM_C_SA 0.22U_0402_25V6K ISL95808HRZ-TS2778_DFN8_2X2~D PQ614
<15> VCC_SENSE_IA NTC_B_IA 3 IMON_B FCCM_C ISUMN_C_SA
@ PR622 28 AONH36334 _DFN3X3A8-10

D1_3

D1_2

D1_1

G1
2
@ PC618 2.49K_0402_1% COMP_B_IA 4 NTC_B ISUMN_C 27 1 8 PL614
FB_B_IA COMP_B ISUMP_C UGATE PHASE
0.082U_0402_16V7K

1 2 1 2 5 26 0.47UH_NA_12.2A_20%
FB_B RTN_C FB_C_SA BST_SA FCCM_SA10 9 LX_SA
@ PC620

6 25 2 7 4 1
RTN_B FB_C BOOT FCCM D1 D2/S1 +VCC_SA
1

330P_0402_50V7K 7 24 COMP_C_SA
ISUMN_B_IA 8 ISUMP_B COMP_C 23 IMON_C_SA PWM_SA 3 6 3 2

RF@
PC621 PR623

S2_1

S2_2

S2_3
C
PC619 820P_0402_25V7 2K_0402_1% 9 ISUMN_B IMON_C 22 PWM VCC C

G2
2

ISEN1_B PWM_A PWM_A_GT <89>

1
LG_SA

4.7_1206_5%
1 2 1 2 1 2 10 21 4 5
ISEN2_B FCCM_A FCCM_A_GT <89> GND LGATE

1
PR606

TP
ISUMN_A
ISUMP_A
PR624

PWM1_B
PWM2_B

COMP_A

8
FCCM_B

PR627
IMON_A
0.01UF_0402_25V7K 41 0_0402_5%

NTC_A

RTN_A
AGND 3.65K_0603_1%

FB_A
<15> VSS_SENSE_IA

1
PWM_C_SA 2

2
Local sense put on HW site

2
PR679
+5V_ALW

1SNUB_SA
11
12
13
14
15
16
17
18
19
ISUMN_A_GT 20
ISL95857CHRTZ-T_TQFN40_5X5 0_0402_5%

680P_0402_50V7K
1

ISUMN_SA
ISUMP_SA
4.7U_0402_6.3V6M
COMP_A_GT
<89> ISUMP_IA

IMON_A_GT

FCCM_C_SA 2
<89> FCCM_B_IA

NTC_A_GT

FB_A_GT
4.99K_0402_1%

PC622
PC685
<89> PWM1_B_IA
2

2
<89> PWM2_B_IA
PR628

@ PR658 PC625
20M_0402_5% 330P_0402_50V7K
PH603 near PU612 MOS Side

2
0.022U_0402_16V7K

0.1U_0402_25V6

1 2

RF@
PR629
1

11K_0402_1%

86.6K_0402_1%
1

1
33P_0402_50V8J

2.49K_0402_1%
PR633

PC624

PC626

1 2
10K_0402_5%_B25/50 4250K

PR630
PH603

1
2200P_0402_50V7K

4700P_0402_25V7K
PR632 PC627 470K_0402_5%_B25/50 4700K
2

2
1
PH602 near PL610 Choke Side

2200P_0402_50V7K

PC628
@ @ 1K_0402_1% 1 2 1 2
2

ISUMP_SA
PH602

1 2 1 2

2
365_0402_1%
PR647 PR635 1 2

1
@ PR638 27.4K_0402_1% 10K_0402_1%

2.61K_0402_1%
1

1
PC630

PR640
523_0402_1% 1 2 PR636 634_0402_1%
2

PC631
1 2 PC629 PR639

PR642
<89> ISUMN_IA 2200P_0402_50V7K 3.09K_0402_1% 1 2 1 2

10KB_0402_5%
U42@ PC635 1 2 1 2

0.033U_0402_25V7K
0.022U_0402_16V7K PC632 PR641

2
1
ISEN1_IA

1K_0402_1%

11K_0402_1%
1 2 PC636 1000P_0402_50V7K 1K_0402_1%

4700P_0402_25V7K
33P_0402_50V8J

PR643
1

1
PR644

PC633
1 2

PC637
U42@ PC638

1
B 0.022U_0402_16V7K PC639 PR645 PR646 PC640 B

2
1 2 ISEN2_IA 1500P_0402_50V7K 316_0402_1% 1 2 1 2
1 2 1 2

PH604
U22@ PR634 316_0402_1% 2200P_0402_50V7K

330P_0402_50V7K
0_0402_5% Not to change short pad

2
39.2K_0402_1%
.1U_0402_16V7K

1 2 1 2 PR649
1

1
PR648 1 2
+5V_ALW

1
ISUMN_SA
PC641

PC643

PR651
1 2 1.91K_0402_1% PC642
<89> ISEN1_IA
2K_0402_1%

0.068U_0402_16V7K 1.62K_0402_1% PC644

2

2K_0402_1%
<89> ISEN2_IA U22@ PR615 Not to change short pad 1 2 .1U_0402_16V7K PH604 near PL614 Choke Side

2
.1U_0402_16V7K

PR652
0_0402_5% 1 2

2
1
PR650

PC645
2

1 2
PC646

680P_0402_50V7K
@
2200P_0402_25V7K
VSS_SENSE_SA <17>

PC601
1 2
1

PC647

2
680P_0402_50V7K
PC649
2

@ 0.01UF_0402_25V7K
1 2
PR656
<16> VCC_SENSE_GT 11K_0402_1%

1
1 2
@ PC650 @ PC652
PR657 0.082U_0402_16V7K

2
@ PC651 330P_0402_50V7K
PH605
1 2 4.42K_0402_1% 1 2
Local sense put on HW site
0.082U_0402_16V7K

1 2 1 2
PH605 near PL612 Choke Side
@ PC653

330P_0402_50V7K
1

@ PR653 10K_0402_5%_B25/50 4250K VCC_SENSE_SA <17>

2 1 ISUMN_GT <89>
2

PC654 20M_0402_5%
A A
1 2
ISUMP_GT <89>
0.01UF_0402_25V7K

<16> VSS_SENSE_GT DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

https://Dr-Bios.com
Title

CPU_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-G871P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Tuesday, March 05, 2019 Sheet 88 of 109

5 4 3 2 1
 5 4 3 2 1

+13.5VB
JUMP@ PJP601
1 2

PAD-OPEN 4x4m
VCC_core (U42)
+13.5VB_CPU TDC 48A
@EMI@ PL602
1 2
Peak Current 70A
OCP current 84A

RF@

RF@

RF@

RF@
9A Z80 10M 1812_2P
Choke DCR 0.9 +-5%m ohm

100U_D_20VM_R55M

100U_D_20VM_R55M
27P_0201_25V8
10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

82P_0201_50V8J
1 1

0.1U_0402_25V6

2200P_0402_50V7K
1

1
+ +
PC682

PC656

PC657

PC658

PC606

PC607
1

1
PC659

PC660

PC689

PC690
D Follow as below D

WHL U42 15W, Core (IA) VR TDC value has been increased from 42A to 48A.
2

2
2 2
This new value will be reflected in WHL PDG/Power Map document next release

2
Low noise MLCC
in WW13 (IBP# 575412).

PL610
0.15UH_MMD-06CZER15MEX5L__35A_20%
PU610
10 11 LX1_IA 4 1
9 PGND1
VIN2
SW1
SW2
12 +VCC_CORE
3 2
8 13

ISEN1P_IA
ISEN1N_IA
0.1U_0402_25V6

VIN1 GL1

1
PC655
BST1_IA_R

4.7_1206_5%
1

+5V_ALW

1
1 2 7 14
PC686

6 PHASE PGND2 15 PR667 PR666

RF@ PR663
0.22U_0402_25V6K NC1 PVCC 3.65K_0603_1% U42@ PR668 10_0402_1%
2

1 2 BST1_IA 5 16 1 2 1 2

4.7U_0402_6.3V6M

2
4 BOOT NC2 17 100K_0402_1%
PR660

2
AGND1 NC3

PC661
3.9_0603_1%
VCC1_IA 3

SNUB1_IA
FCCM1_IA 2 VCC 19 <88> ISEN1_IA

2
PR688 PWM1_IA 1 FCCM GL2 18
1_0603_5% PWM AGND2 VCC_GT (U42)
1 2 FDMF3035_PQFN31_5X5 ISEN2N_IA 1 2
TDC 18A
@ PR670 +13.5VB_VCCGT Peak Current 31A
+5V_ALW

680P_0402_50V7K

<88,89>
4.7U_0402_6.3V6M

ISUMP_IA

<88,89>
ISUMN_IA
100K_0402_1%
OCP current 37.2A
1

1
PC676

RF@ PC662
C C
Choke DCR 0.9 +-5%m ohm
2

27P_0201_25V8
10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

82P_0201_50V8J
0.1U_0402_25V6

2200P_0402_50V7K
JUMP@ PJP602

1
PR659 1 2

PC675

PC674

PC664

PC665

PC666

PC667

RF@ PC691

RF@ PC692
0_0402_5% +13.5VB_VCCGT +13.5VB_CPU
<88,89> FCCM_B_IA 1 2 PAD-OPEN 1x2m~D

2
PR687

RF@

RF@
0_0402_5%
1 2 Low noise MLCC
<88> PWM1_B_IA
RF demand

EMI@ PR669 EMI@ PC670

4.7_1206_5% 680P_0402_50V7K
1 2 SNUB_GT 1 2
10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M
U42@ PC683

U42@ PC684

U42@ PC672

U42@ PC673
1

PL612
PU612 0.15UH_MMD-06CZER15MEX5L__35A_20%
2

Low noise MLCC 10 11 LX_GT 4 1

9 PGND1 SW1 12 +VCC_GT
VIN2 SW2 3 2
8 13

0.1U_0402_25V6
U42@ PL613 VIN1 GL1
PC663

BST_GT_R
+5V_ALW

1
1 2 7 14

PC687
0.15UH_MMD-06CZER15MEX5L__35A_20% PHASE PGND2 PR661
U42@ PU613 6 15
10 11 LX2_IA 4 1 0.22U_0402_25V6K NC1 PVCC 3.65K_0603_1%
+VCC_CORE

2
9 PGND1 SW1 12 1 2 BST_GT 5 16

4.7U_0402_6.3V6M
VIN2 SW2 3 2 4 BOOT NC2 17
PR665

2
AGND1 NC3

1
8 13

PC668
3.9_0603_1%
4.7_1206_5%

ISEN2P_IA
VIN1 GL1
1

<88>

<88>
ISEN2N_IA VCC_GT

ISUMP_GT

ISUMN_GT
U42@ PC671 3
BST2_IA_R

B B
0.1U_0402_25V6

+5V_ALW VCC

1
1 2 7 14 FCCM_GT 2 19
U42@ PC688

RF@U42@ PR676

2
PHASE PGND2 FCCM GL2
1

6 15 U42@ PR674 U42@ PR675 U42@ PR673 PWM_GT 1 18

0.22U_0402_25V6K NC1 PVCC 3.65K_0603_1% PR680 PWM AGND2
10_0402_1%
1 2 BST2_IA 5 16 1 2 1 2 1_0603_5% FDMF3035_PQFN31_5X5
4.7U_0402_6.3V6M
2

U42@ PR672 4 BOOT NC2 17 100K_0402_1% 1 2

+5V_ALW

2
AGND1 NC3
1

U42@ PC697

3.9_0603_1% VCC2_IA <88> ISEN2_IA

3

4.7U_0402_6.3V6M
SNUB2_IA

FCCM2_IA 2 VCC 19 @ PR677

2

FCCM GL2

1
PWM2_IA 1 18 ISEN1N_IA 1 2

PC669
PWM AGND2 100K_0402_1%
U42@ PR691 FDMF3035_PQFN31_5X5

2
1_0603_5%
1 2
+5V_ALW

<88,89>
ISUMN_IA
<88,89>
ISUMP_IA
680P_0402_50V7K
4.7U_0402_6.3V6M
1

PR662
U42@ PC677

RF@U42@ PC678

0_0402_5%
1 2
<88> FCCM_A_GT
2

PR664
0_0402_5%
1 2
<88> PWM_A_GT
PR671
0_0402_5%
<88,89> FCCM_B_IA
1 2

PR692
0_0402_5%
<88> PWM2_B_IA
1 2

A A

DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL CPU_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 89 of 109
5 4 3 2 1

https://Dr-Bios.com
 4
3
2
1
+VCC_CORE

2 1 2 1 2 1 2 1 2 1 2 1

A
A

PC1089 PC1071 PC1051 PC1031 PC1011 PC1000

1U_0201_6.3V6M 47U_0603_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1 2 1 2 1

PC1090 PC1072 PC1052 PC1032 PC1012 PC1001

1U_0201_6.3V6M 47U_0603_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1 2 1

PC1073 PC1053 PC1033 PC1013 PC1002

47U_0603_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1 2 1

2
1
+
PC1091 PC1074 PC1054 PC1034 PC1014 PC1003
330U_D2_2.5VM_R9M 47U_0603_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1 2 1

2
1
+
PC1092 PC1075 PC1055 PC1035 PC1015 PC1004
470U_D2_2VM_R4.5M 47U_0603_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1 2 1

2
1
+
PC1093 PC1076 PC1056 PC1036 PC1016 PC1005
220U_D7_2VM_R4.5M 47U_0603_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1 2 1

2
1
+
@ PC1094 PC1077 PC1057 PC1037 PC1017 PC1006
220U_D7_2VM_R4.5M 47U_0603_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1 2 1

2
1
+
PC1095 PC1078 PC1058 PC1038 PC1018 PC1007
330U_D2_2.5VM_R9M 47U_0603_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1 2 1

PC1079 PC1059 PC1039 PC1019 PC1008

47U_0603_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

B
B

2 1 2 1 2 1 2 1 2 1 2 1

RF@ PC1096 PC1080 PC1060 PC1040 PC1020 PC1009

100P_0201_25V8J 47U_0603_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1

RF@ PC1097 @ PC1081 PC1061 PC1041

100P_0201_25V8J 22U_0603_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M
2 1 2 1 2 1

RF@ PC1098 @ PC1082 PC1062 PC1042

27P_0201_25V8 22U_0603_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M
2 1 2 1 2 1 2 1

RF@ PC1099 @ PC1083 PC1063 PC1043

82P_0201_50V8J 22U_0603_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M
2 1 2 1 2 1 2 1
220u_D7
470u_D2
330u_D2
1U_0201

RF@ PC1180 @ PC1084 PC1064 PC1044

47U_0603
22U_0603

27P_0201_25V8 22U_0603_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M

+VCC_CORE

2 1 2 1 2 1 2 1

RF demand
RF@ PC1181 @ PC1085 PC1065 PC1045
27P_0201_25V8 22U_0603_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M
2 1 2 1 2 1 2 1

@ PC1086 PC1066 PC1046

22U_0603_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M
*1pcs
*2 pcs

2 1 2 1 2 1
*42 pcs
*10 pcs

@ PC1087 PC1067 PC1047

22U_0603_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M
2 1 2 1 2 1

C
C

@ PC1088 PC1068 PC1048

Place on CPU:

22U_0603_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M

2 1 2 1

PC1069 PC1049
1U_0201_6.3V6M 1U_0201_6.3V6M
2 1 2 1

PC1070 PC1050
*1pcs + reserve 1 pcs

1U_0201_6.3V6M 1U_0201_6.3V6M
*20 pcs +reserve 8 pcs
+VCC_GT

+VCC_SA

2 1 2 1 2 1
2
1
+

PC1142 PC1131 PC1116 PC1101

330U_D3_2.5VY_R6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
2
1
+

2 1 2 1
PC1143 PC1132 PC1117 PC1102
RF@ PC1166 PC1151 330U_D3_2.5VY_R6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
100P_0201_25V8J 22U_0603_6.3V6M 2 1 2 1 2 1

https://Dr-Bios.com
2 1 2 1
PC1133 PC1118 PC1103

D
D

RF@ PC1167 PC1152 2 1 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

100P_0201_25V8J 22U_0603_6.3V6M 2 1 2 1 2 1

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2 1 RF@ PC1146
100P_0201_25V8J PC1134 PC1119 PC1104
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS RF@ PC1168 PC1153 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
27P_0201_25V8 22U_0603_6.3V6M 2 1 2 1 2 1 2 1
2 1 2 1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

RF@ PC1147 PC1135 PC1120 PC1105

RF@ PC1169 PC1154 100P_0201_25V8J 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
RF demand

82P_0201_50V8J 22U_0603_6.3V6M 2 1 2 1 2 1
2 1 2 1 RF@ PC1148
27P_0201_25V8 PC1136 PC1121 PC1106
PC1155 2 1 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
22U_0603_6.3V6M 2 1 2 1 2 1
2 1 RF@ PC1149
82P_0201_50V8J PC1137 PC1122 PC1107
RF demand

PC1156 2 1 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

Size
Title

22U_0603_6.3V6M 2 1 2 1 2 1
Date:

2 1
PC1138 PC1123 PC1108
PC1157 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
22U_0603_6.3V6M 2 1 2 1
2 1
PC1139 PC1109
PC1158 1U_0201_6.3V6M 22U_0603_6.3V6M
22U_0603_6.3V6M 2 1 2 1
2 1
Document Number

PC1140 PC1110
PC1159 1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1
Tuesday, March 05, 2019

22U_0603_6.3V6M
2 1
PC1141 PC1111
330u_D3
1U_0201

PC1160 1U_0201_6.3V6M 22U_0603_6.3V6M

22U_0603

2 1
22U_0603 *11 pcs

22U_0603_6.3V6M
2 1
E
E

LA-G871P

PC1112
PC1161 22U_0603_6.3V6M
2 1
+VCC_SA Place on CPU

22U_0603_6.3V6M
Sheet

PC1113
22U_0603_6.3V6M
90

2 1
*2 pcs

CPU Decoupling CAP

*23 pcs
*11 pcs

Compal Electronics, Inc.

PC1114
of

22U_0603_6.3V6M
2 1
+VCC_GT Place on CPU:

PC1115
22U_0603_6.3V6M
109
DELL CONFIDENTIAL/PROPRIETARY

R ev
1.0
4
3
2
1
 5 4 3 2 1

D D

PC3002
0.01UF_0402_25V7K
1 2
+3.3V_VDD_DCIN

AZV3002
PR3002 Icc=12uA_max
200K_0402_1%
1 2 Vout=3.15V@Vcc=3.3V and Io=3mA
PR3003 PR3001
Vf 1.9056V-1.98V-2.0544V 300K_0402_1% 0_0402_5%
1 2 PU3000 1 2
ACIN_CHG <84>

1
AZV3002RL-7_U-FLGA8_1P65X1P65 PD3001

L2N7002DW1T1G 2N SC88-6
@ PC3001 Not to change short pad
82P_0201_50V8J RB520SM-30T2R_EMD2-2

VCC

3
1 2

2
2

PQ3000B
+VCC_CORE PR3004 IN-1 - 1 1 2 NO_SMOKE_OVP 5
OUT1

1
1U_0201_6.3V6M

1U_0201_6.3V6M
200K_0402_1% 3 +
1 2 IN+1 PR3012

4
PC3008

PC3009
C 1K_0201_1% C

L2N7002DW1T1G 2N SC88-6
PR3005 6
IN-2 -

6
402K_0402_1% 7 1 2
1 2 5 OUT2
IN+2 + PR3013

PQ3000A
@ PR3006 @ PC3003 1K_0201_1% NO_SMOKE_UVP 2

VEE

1
1U_0201_6.3V6M

1U_0201_6.3V6M
0_0402_5% 82P_0201_50V8J

2
1 2 1 2

1
PC3010

PC3011
PD3002

2
+13.5VB RB520SM-30T2R_EMD2-2
PD3000
3 PR3007

1
237K_0402_1%
1 1 2

2 PR3008
+3.3V_VDD_DCIN
43.2K_0402_1%
Vref 0.72V-0.75V-0.78V
BAT54CW_SOT323-3 1 2
@ PR3009
@ PC3004 14.7K_0402_1%
82P_0201_50V8J 1 2 RB520SM
1 2 ACAV_IN1 <84>
PR3010
147K_0402_1%
Vf =0.29V@1mA
1 2 Ir =1uA @Vr=10V
ACAV_IN <58,79,84>
PR3011
VIN 4.9952V-5.19V-5.3848V 43.2K_0402_1%
3.3V+-4%
PD3000 VF =0.32V@1mA 1 2

PC3005
1 2

0.22U_0402_10V6K

B B

A A

DELL CONFIDENTIAL/PROPRIETARY

https://Dr-Bios.com
Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Charger UVP/VCORE OVP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-G871P
Date: Tuesday, March 05, 2019 Sheet 91 of 109

5 4 3 2 1
 5 4 3 2 1

D D

@EMIWL@ PL901
FBMJ4516HS720NT_2P

1 2

@EMIWL@ PL902
FBMJ4516HS720NT_2P
+19.5VB_WC_C 1 2 +19.5VB_WC_SDC
+19.5VB_WC_SDC

C C

PD901 @ESDWL@ PD902 @ESDWL@

L03ESDL5V0CG3-2_SOT-523-3 L03ESDL5V0CG3-2_SOT-523-3

1
1

1
Wireless Power Connector

3
2

3
@CONN@WC1 @WL@ PR953
1 100_0402_5%
1 2 1 2
2 3
3 4 WP_SMBCLK_C
WP_GPU_SMCLK <58>
2200P_0402_50V7K

4 5 WP_SMBDAT_C 1 2
5 WP_INT_C WP_GPU_SMDAT <58>
6 @WL@ PR954
@EMIWL@ PC906

6 BSMB_WP_INT# <58>
1

7 100_0402_5%
7 8 1 2
8 9 @WL@ PR955
2

9 10 100_0402_5%
10 11 1 2
GND1 +3.3V_ALW
12
GND2 @WL@ PR956
DEREN_40-42251-01001RHF 0_0402_5%

GND

B B

A A

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Compal Electronics, Inc.
Title

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AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
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LA-G871P
Date: Tuesday, March 05, 2019 Sheet 92 of 109

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DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title

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THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Reserve for PWR
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DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
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Date: Tuesday, March 05, 2019 Sheet 93 of 109

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DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

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Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve for PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
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DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-G871P
Date: Tuesday, March 05, 2019 Sheet 94 of 109
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DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

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Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
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AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
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Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
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DELL CONFIDENTIAL/PROPRIETARY

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Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve for PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
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DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
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Date: Tuesday, March 05, 2019 Sheet 97 of 109

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DELL CONFIDENTIAL/PROPRIETARY

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Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve for PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
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Date: Tuesday, March 05, 2019 Sheet 98 of 109

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 5 4 3 2 1

U42
PC626 U42@ PR613 U42@ PR621 U42@ PC624 U42@

D
0.1U_0402_25V6 97.6K_0402_1% 316_0402_1% 0.022U_0402_16V7K D

PR638 U42@ PR622 U42@ PC616 U42@ PC617 U42@

523_0402_1% 2.49K_0402_1% 68P_0402_50V8J 1200P_0402_50V7K

U22
PC626 U22@ PR613 U22@ PR621 U22@ PC624 U22@

0.047U_0402_25V7K 84.5K_0402_1% 316_0402_1% 0.033U_0402_25V7K

PR638 U22@ PR622 U22@ PC616 U22@ PC617 U22@

422_0402_1% 1.65K_0402_1% 33P_0402_50V8K 1200P_0402_50V7K

C C

B B

A A

DELL CONFIDENTIAL/PROPRIETARY

https://Dr-Bios.com
Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BOM Option
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
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Date: Tuesday, March 05, 2019 Sheet 99 of 109

5 4 3 2 1
 5 4 3 2 1

Version Change List ( P. I. R. List )

Item Page# Date Issue Solution
Description Description Rev.
P089 06/04 Fairchild & AOS Dr.MOS vendor remove PVCC reserved resistors Delete reserved PR686/PR689/PR681 on PVCC side X01
1
P082 1. PC624 change to SE076223K80 (S CER CAP 0.022U 16V K X7R 0402)
2 P086 06/08 Change to common P/N 2. PC804 change to SE074221K80 (S CER CAP 220P 50V K X7R 0402) X01
P088 07/02 3. PC633 change to SE075472K80 (S CER CAP 4700P 25V K X7R 0402)
D D
P089 4. PL201 change to SH00000YE00 (common P/N)
5. PL614 change to SH00001ED00 (common P/N)

3 P090 07/12 Merion Top side Z-height limitation 1. Un-stuff PC1094 (@) X01
2. Add stuff PC1095 - 330uF (Bottom side)
1. Change the PR636 from 665 Ohm to 634 Ohm. - (VCCSA Ri)
4 P088 07/13 CPU intel validation form test tune value -> SD00000Z280, S RES 1/16W 634 +-1% 0402 X01
P099 2. Change the PR640 from 374 Ohm to 365 Ohm. - (VCCGT Ri)
-> SD034365080, S RES 1/16W 365 +-1% 0402
3. Change the PC646 from 0.047uF to 0.0022uF. - (VCCGT RC)
-> SE075222K80, S CER CAP 2200P 25V K X7R 0402
4. Change the PC642 from 0.033uF to 0.068uF. - (VCCGT RC)
-> SE000003J80, S CER CAP 0.068U 16V K X7R 0402
5. Change the PC621 from 680pF to 820pF. - (VCCIA FB RC).
-> SE000008980, S CER CAP 820P 25V K X7R 0402
6. Change the PR611 from 1.87kOhm to 9.31kOhm. - (PROG2)
-> SD034931180, S RES 1/16W 9.31K +-1% 0402

5 P082 ESD request

P083 07/20 PD1, PD2, PD4 change to SCA00002A00 for ESD demand X01
Need stuff item :
PU2/ PC10/ PC11/ PR47/ PR33/ PR27/ PR17/ PD800 / PR806 / PR809/ PR832/ PR859 / PR810 / PR813 X01

6 P082 07/30 LPS function test fail on G3 mode. Need to return LDO(PU2) design circuit. Need delete location : PR48 / PR34 / PR35 / PR36 / PR37/ PR847 / PR848 / PR849/ PR850
Need un-stuff item : PR851 / PR860 / PR852
C C

7 P082 07/30 PQ8 gate for Back drive issue Add R/C delay PR865/PC865 : 100K(SD028100380) and 0.1uF_0402_25V(SE00000G880) X01

PR800 change to 422K_0402_1% (SD034422380)

8 P082 08/10 PR815 change to 37.4K_0402_1% (SD034374280) X01
LM393 resistor value fine tune PR832 change to 102K_0402_1% (SD028102380)
PR843 change to 37.4K_0402_1% (SD034374280)
PR831 change to 1M_0402_1% (SD034100480)
PR842 change to 191K_0402_1% (SD034191380)

9 P088 08/10 ISL95857 CPU Controller change to Rev.C PR651 value change to 39.2K for ISL95857C X01

10 P082
P083 08/15 Follow Schematic naming rule Re-define the RTC/DCIN/Battery connector from @ to CONN@. X01
PJPDC1 - SP02001A500
11 P082 08/15 Check and modify connector P/N for ME request PBATT1 - SP02001A700 X01
P083 JRTC1 - SP02000RO00
1. Modify PR312 / PR406 value from 0 ohm to 22K_0402_1% (SD034220280)
2. PC411 change to stuff X01
12 P087 08/15 R/C delay fine tune for WHL bring up sequence 3. Add PC360 : 0.1uF_0402_25V (SE00000G880)

13 P091 08/20 Remove double pull down resistor Un-stuff PR505 / PR407 X01
1. PC301 pop & change from 0.1u to 82pF
14 All 08/20 RF request 2. PR502/PC506 change to pop (Snubber not to downsize) X01
08/30 3. PC1096/PC1097 change to pop
B B
4. PC1166/PC1167 change to pop
5. PC1146/PC1147 change to pop
6. Add PC101 27pF for RF +3.3V input
7. Add PC141 27pF for RF +5V input
8. Add PC230 27pF, PC231 100pF for RF +1.2V_DDR input
9. Add PC317 27pF, PC318 82pF for RF +1.05V_ALWP input
10. Add PC609 27pF, PC610 82pF for RF +VCC_SA input
11. Add PC689 27pF, PC690 82pF for RF +13.5VB_CPU input
12. Add PC691 27pF, PC692 82pF for RF +13.5VB_VCCGT input
13. Add PC1098 27pF, PC1099 82pF for RF +VCC_CORE input
14. Add PC1148 27pF, PC1149 82pF for RF +VCC_GT input
15. Add PC1168 27pF, PC1169 82pF for RF +VCC_SA input
16. Add PC756,PC759 (22pF)/ PC757, PC760 (47pF)/ PC758, PC761 (100pF)
17. Reserve PC2 (27pF)
18. Add PC1180, PC1181 (27pF)

Add RTC detect circuit

15 P083 08/21 RTC issue for HW request 1. Add PR9 10Mohm X01
2. Add PQ13 MOS

16 P091 08/22 Charger UVP & VCORE OVP circuit Add Charger UVP & VCORE OVP circuit X01
1. Add un-stuff PR870 and pull up source is +20V_VBUS_DC_SS ; 499K_0402_1% (SD034499380)
17 08/22 LPS function modify 2. Modify PR831 value to 499K_0402_1% (SD034499380) and pull up source change to +20V_TBTA_VBUS_1 X01
P082 09/11 3. Modify PR842 value to 97.6K_0402_1% (SD034976280)
4. PC811 change to SE00000UD00 (10U 6.3V M X5R 0402)
1. PD800 change to un-stuff
18 P082 08/22 Modify 1 barrel / 1 Type-C External LDO circuit for Charger UVP & VCORE OVP circuit design 2. Add PR866 0_0402_5% X01
A A
3. Add PD803 (BAT54CW_SOT323-3)
4. Add un-stuff PR868 0_0603_5%

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
PWR P.I.R
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number R ev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0

Date: Tuesday, March 05, 2019 Sheet 100 of 109

5 4 3 2 1
 5 4 3 2 1

Version Change List ( P. I. R. List )

Item Page# Date Issue Solution
Description Description Rev.
19 P088 IA input : PC658 / PC657 / PC656 / PC682 / PC683 / PC684 / PC672 / PC673
P089 08/22 CPU VR input Low noise MLCC PCB footprint update : C_0603-S3 GT input : PC675 / PC674 / PC664 / PC665
SA input : PC612 / PC608 X01
IA output : PC1071 / PC1072 / PC1073 / PC1074 / PC1075/ PC1076 / PC1077 / PC1078 / PC1079 / PC1080
D D

20 P090 08/22 Un-stuffed CPU +VCC_CORE output MLCC change value Change reserve location from 47uF to 22uF (Keep un-stuff)
PC1081 / PC1082 / PC1083 / PC1084 / PC1085 / PC1086 / PC1087 / PC1088 X01

21 P089 08/22 Remove double net name Remove PU610 / PU612 / PU613 Dr.MOS pin 15(PVCC) double net name
X01

Change PU301, PU501 powergood connection netname Change connection to 1.0V_PRIM_PWRGD from 1.8V_PRIM_PWRGD (PU301, PU501) X01
22 P087 08/23
1. Add PR313 : 100K_0402_5%
23 P087 2. Add PR314 / PR315 : 0 ohm ( X01
08/28 R/C for WHL sequence 3. Reserve PC350 footprint to PG (1.0V_PRIM_PWRGD) signal

Change to Stuff : PR46 / PR41 / PR858 / PR857 / PQ12 / PR49 / PQ814 / PR861 X01
24 P089 08/28 1 barrel / 1 Type-C change solution 2 Un-stuff : PR856 / PR43

25 P091 09/04 Disable Charger UVP & VCORE OVP function Un-stuff PR3001 for disable No Smoke function X01

26 P090 09/14 DCIN AC detect tune value Change PR817 to SD034249280 (S RES 1/16W 24.9K +-1% 0402) X01

Jump BOM structure change

27 All 09/11 Follow schematic naming rule Solder -> JUMP@ X01
C
Not Solder -> @JUMP@ C

1. PR3002 change to 200K_0402_1% (SD034200380)

1 P091 11/05 Charger UVP/VCORE OVP circuit 2. PR3003 change to 300K_0402_1% (SD034300380) X02
3. PR3001 change to stuff
4. Add PC3008 / PC3009 on NO_SMOKE_OVP
5. Add PC3010 / PC3011 on NO_SMOKE_UVP

2 P084 11/05 Charger IC PU700 & CPU Controller IC PU602 change P/N for MP 1. PU700 change P/N to SA0000BWG0L for MP X02
P088 2. PU602 change P/N to SA0000BYJ0L for MP

3 P090 11/05 1. Check PQ4/PQ801/PQ702 1st parts is SB00001MT00 X02

Barrel & typeC B2B MOSFET P/N change (SB00001MT00 - AONR21357 1P DFN3X3-8) .
2. PQ9 / PQ800 CPN change to SB00001BX1L (EMZB08P03V 1P EDFN3X3-8)

4 All 11/28 0 ohm short pad total 69 pcs PR19, PR20, PR22, PR25, PR861, PR42, PR44, PR46, PR47, PR49, X02
PR100, PR104, PR105, PR111, PR119, PR120, PR203, PR208, PR210, PR304,
PR314, PR315, PR402, PR423, PR504, PR513, PR602, PR603, PR606, PR614,
PR616, PR620, PR625, PR659, PR662, PR664, PR679, PR687, PR709, PR713,
PR715, PR719, PR721, PR722, PR727, PR729, PR731, PR736, PR737, PR740,
PR741, PR743, PR814, PR816, PR818, PR820, PR826, PR827, PR829, PR834,
PR836, PR840, PR844, PR853, PR854, PR858, PR859, PR671, PR692

5 P082 11/28 Barrel & typeC B2B control circuit Change to un-stuff parts : PC13 / PU3 / PR45 / PC814 / PU801 / PR855 X02

P084
6 P089 12/03 Add " -NPM " PCB Footprint to cover green paint for Co-lay Depop Component. PJP700 -> JUMP_43X118-NPM X02
B B
PL602 -> 9A_Z80_1812_2P-NPM

7 P082 12/04 ESD Request PD1, PD2 change P/N to SCA00004700, S ZEN ROW CEST523NC5VB 3P C/A SOT-523 AU X02
Due to AMZ SCA00002X00 has be removed in ESD common pool

8 P082 12/12 PD803 voltage derating back up solution 1. Remove PR868 reserve 0ohm X02
2. Add PR892 / PR893 for PD803 voltage derating back up solution.
 SD002220A80 - S RES 1/8W 22 +-5% 0805
3. PD803 Pin 1 add net name : +20V_LDO_INPUT

9 P084 12/13 Charger input current sense R for more quickly sensing PR701 / PR702 change to 1_0603_1% (SD014100B80) for more quickly sensing X02

10 P091 12/13 Charger UVP/VCORE OVP circuit 1. PR3010 change value from 14.7K to 147K(SD034147380) for more sequence margin. X02
2. PR3011 change value from 4.32K to 43.2K(SD034432280) for more sequence margin.

11 P085 12/13 RF Request Add PC228 27pF on +1.2VDDRP, PC142 27pF on +5V_ALWP for RF demand X02
P086
1. PR421 change to depop (@0@)
12 P087 12/28 +1.0VS_VCCIO change from local sense to remote sense 2. PR412, PR422 change to pop X02

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
PWR P.I.R
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number R ev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0

Date: Tuesday, March 05, 2019 Sheet 101 of 109

5 4 3 2 1
 5 4 3 2 1

Version Change List ( P. I. R. List )

Item Page# Date Issue Solution
Description Description Rev.
1 P088 PR41, PR857, PR866, PR427, PR429
P089 02/18 0 ohm short pad total 74 pcs (DVT2.0 + A00)
A00

D D

2 P091 02/18 Charger UVP/VCORE OVP circuit 1. Add PR3012, PR3013 on VCORE_OVP & Charger_UVP
02/22 2. PR3005 change to 402k_0402_1% (SD034402380) and stuff for VCORE OVP design tolerance A00

C C

B B

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
PWR P.I.R
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number R ev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0

Date: Tuesday, March 05, 2019 Sheet 102 of 109

5 4 3 2 1
 5 4 3 2 1

D D

NVPRO@ RC734 NVPRO@ RC570 NVPRO@ RC571 NVPRO@ RC572 NVPRO@ RC25 NVPRO@ RC26 NVPRO@ RZ58 NVPRO@ RZ59 NVPRO@ RZ60

33_0201_1% 33_0201_1% 33_0201_1% 33_0201_1% 10_0201_1% 10_0201_1% 33_0402_1% 33_0402_1% 33_0402_1%

NVPRO@ RC27 NVPRO@ RC29
NVPRO@ RC33 NVPRO@ UC5

10_0201_1% 10_0201_1%
33_0201_1% GD25B64CYIGR
NVPRO@ RC30

10_0201_1%
C C

B B

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Bom option
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 103 of 109
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Stack-up
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-G871P
Date: Tuesday, March 05, 2019 Sheet 104 of 109
5 4 3 2 1
 5 4 3 2 1

Version Change List ( P. I. R. List )

Issue Solution
Item Page# Date Description Description Rev.
1 All 2018/07/23 Updated page define according to Dell request Updated page define according to Dell request. 0.2(X01)
1.Modified QZ3 footprint to correct 1.Change QZ3 footprint to SOT-323 from SOT-23.
D 2 79 2018/07/23 2.Modified parts pin define to correct 2.Change SW1 pin define. 0.2(X01) D

3 09 2018/07/23 Modified parts pin define to correct Change JASA1 pin define(swap pin1&4,pin2&3). 0.2(X01)
1.Modified parts location to align with X9 1.Change CT358 location to CT82.
4 44 2018/07/23 2.Change PD controller to 65982DD 2.Change UT5 part to SA0000C800 from SA0000BIJ00. 0.2(X01)

5 11 2018/07/23 RTC elapsed time can not meet the Spec(spec:+/- 2 secs) Change CC23,CC26 part to 15P_0402_50V8J from 12P_0402_50V8J. 0.2(X01)
1.Modified parts BOM Structure 1.Change RC24 BOM Structure to @NVPRO from @.
6 50 2018/07/23 2.Modified layout Limit height problem 2.Change QC2 part to SB000014X00 from SB00000PV00. 0.2(X01)

7 52 2018/07/23 Modified parts pin define to correct Change JANT1,JANT2 pin define(swap pin1&5,pin2&4). 0.2(X01)

8 102 2018/07/23 Modified NVPRO BOM option RZ58~RZ60 to correct Change RZ58~RZ60 BOM option part to 33_0402_1% from 33_0201_1%. 0.2(X01)

9 56 2018/07/23 Modified according to ESD request Change DA2 part to SCA00001A00 from SC600001600. 0.2(X01)
1.Modified layout Limit height problem 1.Change DZ11 part to SCA00002A00 from SCA00001B00.
C 10 66 2018/07/23 2.Change ST TPM to ST33HTPH2032AHC1(MP version) 2.Change UZ12 part to SA0000C5G10 from SA00009SO40. 0.2(X01) C
3.Add FPR_RST# pull high,align with merion13 3.Add RZ1392(100K_0201_5%)pull high to +3.3V_FPBTN.
11 59 2018/07/23 Modified layout Limit height problem Change UE4 part to SA00007YE00 from SA00007WE00. 0.2(X01)
Change DZ9 part to SCS00008B80 from SCS00006400.
12 78 2018/07/23 Modified layout Limit height problem Change QZ15,QZ22 part to SB00001KM00 from SB00000VD00. 0.2(X01)

13 14 2018/07/23 Modified layout Limit height problem Change QC4 part to SB000014X00 from SB00000PV00. 0.2(X01)

14 38 2018/07/23 Modified layout Limit height problem Change QV2,QV7 part to SB00000NK00 from SB00000UO00. 0.2(X01)
1.Change QV4,QV5 part to SB00000NK00 from SB00000UO00.
1.Modified layout Limit height problem 2.Change RV26,RV29,RV32,RV35 part to 130_0402_5% from 300_0402_5%.
15 40 2018/08/09 2.Modified parts according to EMI & EE test result 0.2(X01)
Change LV31~38 to 5.6_0402_5% from SHI00006Q00.
Change LV31~38 location to RV56~RV63.
1.Change netname to M_BIST from M_BITS.
1.Dell request to modify M_BIST circuit Change RZ1413 part to SD028330380(330K_0201_5%) from SD00000HX80(221K_0201_1%).
2.Modified parts to correct capacitance voltage Add location RZ1482(1M_0402_5%) pull up to +3.3V_ALW.
16 79 2018/08/09 3.Delete unnecessary parts, align with X10 projects 0.2(X01)
Change RZ1413,DZ12 to depop from pop.
B
2.Change CZ218 part to SE00000UC00(1U_0201_6.3V6M) from SE000013500(1U_0201_10V6M). B
3.Delete location RV632(0_0402_5%).
1.Change CC65,CC66,CC73,CC75,CC98,CC1463,CC1464,CC67,CC80,CC83 part to
SE00000UC00(1U_0201_6.3V6M) from SE000000K80(1U_0402_6.3V6K).
Add location CC68,CC69,CC70(1U_0201_6.3V6M).
Change CC72 part to SE000000580(0.1U_0201_6.3V6K) from SE095104K80(0.1U_0402_10V6K).
Delete location CC74(0.1U_0402_10V6K).
2.Change LC1~LC3 part to SHI0000XL00(2.2uH 0603 INDUC) from SM01000RR00(0603 Bead).
1.Modified parts downsize according to Intel confirmed Change CC100,CC102 part to SE00000M000(22U_0603_6.3V6M) from
2.Modified parts according to Intel BSOD issue recommend
17 18 2018/08/09 3.Reserved WHEA circuit SE00001500(47U_0603_6.3V6M). 0.2(X01)
4.Reserved WHEA R/C Filter circuit Add location CC103,CC104(22U_0603_6.3V6M).
Change LC2,LC3,CC100,CC102 to pop from depop.
Change RC173,RC175 to depop from pop.
3.Delete location RC846(0_0201_5%).
Change CC85,CC86 part to SE00000M000(22U_0603_6.3V6M) from SE000007280(2.2P_0201_25V)
Change LC1 BOM Structure to @ from @RF@.
Change CC85,CC86 BOM Structure to @ from RF@.
4.Add location RC864(0_0603_5%).
1.Change netname to VCI_IN3# from NFC_ACTIVITY_STATUS#.
A 1.Modified according to GPIO map v1.4 Change netname to PTP_DISABLE# from TP_DISABLE#.
18 58 2018/08/09 2.Modified parts to correct capacitance voltage 0.2(X01) A
2.Change CE14,CE30,CE31,CE63 part to SE00000UC00(1U_0201_6.3V6M)
from SE000013500(1U_0201_10V6M).
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
EE P.I.R
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number R ev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-G871P
Date: Tuesday, March 05, 2019 Sheet 105 of 109
5 4 3 2 1
 5 4 3 2 1

Version Change List ( P. I. R. List )

Issue Solution
Item Page# Date Description Description Rev.
19 70 2018/08/09 Modified parts to correct capacitance voltage Change CR15,CR22 part to SE00000UC00(1U_0201_6.3V6M) from SE000013500(1U_0201_10V6M). 0.2(X01)
1.Change Non-Vpro UC6 ROM parts,
align UC5 ROM parts vendor 1.Change UC6 part to SA0000A8J10(GIGADEVICE) from SA00005VV20(WINBOND).
D 20 08 2018/08/09 2.Change netname to GPP_C2 from PCH_SMB_ALERT#. 0.2(X01) D
2.Modified according to GPIO map v1.4
21 44 2018/08/09 Modified parts to correct capacitance voltage Change CT83 part to SE00000UC00(1U_0201_6.3V6M) from SE000013500(1U_0201_10V6M). 0.2(X01)
22 06 2018/08/09 Modified netname to correct Change netname to GPP_H23 from GPPC_H23. 0.2(X01)
1.Change CD25 part to SE000000580(0.1U_0201_6.3V6K) from SE095104K80(0.1U_0402_10V6K).
1.Change parts follow sourcer request 2.Change CD9~CD16,CD18,CD19,CD23,CD24,CD69,CD70 part to SE00000UC00(1U_0201_6.3V6M)
23 23 2018/08/09 2.Modified parts downsize according to Intel confirmed 0.2(X01)
from SE000000K80(1U_0402_6.3V6K).
1.Change CD57 part to SE000000580(0.1U_0201_6.3V6K) from SE095104K80(0.1U_0402_10V6K).
1.Change parts follow sourcer request 2.Change CD41~CD48,CD50,CD51,CD55,CD56,CD71,CD72 part to SE00000UC00(1U_0201_6.3V6M) 0.2(X01)
24 24 2018/08/09 2.Modified parts downsize according to Intel confirmed from SE000000K80(1U_0402_6.3V6K).
Change CC28,CC29,CC31,CC430 part to SE00000UC00(1U_0201_6.3V6M)
25 17 2018/08/09 Modified parts downsize according to Intel confirmed from SE000000K80(1U_0402_6.3V6K). 0.2(X01)
1.Change CA29,CA49 part to SE00000YB00(1U_0201_6.3V6K) from SE080105K80(1U_0603_10V6K)
Add location CA76,CA77(1U_0201_6.3V6K).
1.Modified parts downsize according to RTK confirmed 2.Change netname to SMART_SPK_DET0# from SPK_DET#.
2.Modified according to GPIO map v1.4 3.Change RA53 to pop from depop.
26 56 2018/08/09 3.Modified AUX mode pin power rail to +3.3V_RTC_LDO Change RA54 to depop from pop. 0.2(X01)
C
4.Modified parts to correct capacitance voltage 4.Change CA31 part to SE00000UC00(1U_0201_6.3V6M) from SE000013500(1U_0201_10V6M). C

5.Modified smart amp. to support 3rd vendor 5.Change JSPK1 part to SP02000HC10(8pin) from SP020019S00(6pin).
Add location RA67(10K_0402_5%) pull high to +3.3V_RUN.
Add JSPK1.6 net SMART_SPK_DET1# connect to GPP_C22.
Delete net NFC_ACTIVITY_STATUS#.
Change RZ1473 pin1 to NC.
27 66 2018/08/09 Modified according to GPIO map v1.4 Change netname to PTP_DISABLE# from TP_DISABLE#. 0.2(X01)
Change netname to PTP_DISABLE#_R from TP_DISABLE#_R.
28 9 2018/08/09 Modified according to GPIO map v1.4 Add GPP_C22 net SMART_SPK_DET1# connect to JSPK1.6. 0.2(X01)
29 77 2018/08/09 Modified Semi-circular screw holes footprint Change H26,H7,H6,H25,H9,H24,H23,H22 footprint to H_xPxN(NPTH). 0.2(X01)
30 58 2018/08/20 Modified layout Limit height problem Change QE2 part to SB000014X00 from SB00000PV00. 0.2(X01)
31 66 2018/08/20 Modified layout Limit height problem Change QZ18 part to SB000017J00 from SB00001FT00. 0.2(X01)
32 11 2018/08/20 CMOS1 PAD 蓋 蓋 蓋 Change CMOS1 footprint to SHORTPADS-NPM from SHORTPADS. 0.2(X01)
Change CC96 part to SE00000M000(22U_0603_6.3V6M) from SE000001120(22U_0805_6.3V6M)
33 11 2018/08/20 Modified parts according to Intel MOW WW30 [0805 part shortage]. 0.2(X01)
Change CC96 to pop from depop.
B B

Modified CNV DT topology series resistor value

34 09 2018/08/20 according to Intel MOW WW32 Change RC710,RC711 part to SD028330A80(33_0402_5%) from SD028750A80(75_0402_5%). 0.2(X01)

35 23 2018/08/20 Modified layout Limit height problem Change CD17 part to SGA0000AM00(220U_D7_2V) from SGA00006A00(330U_D3_2.5V). 0.2(X01)

36 24 2018/08/20 Modified layout Limit height problem Change CD49 part to SGA0000AM00(220U_D7_2V) from SGA00006A00(330U_D3_2.5V). 0.2(X01)

37 59 2018/08/20 Modified Board ID resistor to X01 Change RE79 part to SD028130380(130K_0402_5%) from SD028240380(240K_0402_5%). 0.2(X01)
Change CZ227~CZ230 part to SE071121J80(120P_0402_50V8J) from
SE071101J80(100P_0402_50V8J).
Change CZ227~CZ230 to pop from depop. 0.2(X01)
38 52 2018/08/20 Modified parts according to RF request Change CZ307,CZ308 part to SE174270J80(27P_0201_25V8J) from
SE000011F00(100P_0201_25V7K).
Change CZ307,CZ308 to pop from depop.
Add location CZ233,CZ234 SE174101J80(100P_0201_25V8J).

A 39 50 2018/08/20 Modified parts to NPO capacitance Change CT359 part to SE174101J80(100P_0201_25V8J) from SE000011F00(100P_0201_25V7K). 0.2(X01) A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
EE P.I.R
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number R ev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-G871P
Date: Tuesday, March 05, 2019 Sheet 106 of 109
5 4 3 2 1
 5 4 3 2 1

Version Change List ( P. I. R. List )

Issue Solution
Item Page# Date Description Description Rev.
40 24 2018/08/22 Modified parts according to ESD request Add location DD1(SCA00002A00). 0.2(X01)
41 70 2018/08/22 Modified parts to correct capacitance voltage Change CR15,CR22 part to SE00000UC00(1U_0201_6.3V6M) from SE000013500(1U_0201_10V6M). 0.2(X01)
D D
Delete location T143 test point.
42 58 2018/08/22 Add RTC(coin battery) voltage detect circuit Change EC side GPIO011 pin netname to RTC_DET# from GPIO011.
Add offpage RTC_DET#. 0.2(X01)
1.Fixed power sequence EA request 1.Change RE361 pin 2 net connection to 1.0V_PRIM_PWRGD from 1.8V_PRIM_PWRGD.
43 58 2018/08/23 2.Modified RTC(coin battery) voltage detect circuit 2.Add location RE401 SD043100280(10K_0201_5%) pull up to +1.8V_PRIM_VTR3. 0.2(X01)

44 70 2018/08/23 Fixed double net problem Delete net SDWP_Q. 0.2(X01)

45 78 2018/08/23 Fixed double net problem Delete net +3.3V_SSD_UZ53. 0.2(X01)
46 01 2018/08/23 Add Motherboard DPN(PWB) Add Merion14 PWB DD1CY. 0.2(X01)
47 66 2018/08/24 Modified parts according to ESD request Add location DZ14,DZ15(SC300001Y00). 0.2(X01)
1.Delete Semi-circular screw hole 1.Delete location H26,H7,H6,H25,H9,H24,H23,H22.
48 66 2018/08/27 2.Delete unnecessary screw hole 2.Delete location H19. 0.2(X01)

49 38 2018/08/27 Update EDP connector symbol Update JEDP1 connector symbol. 0.2(X01)
50 52 2018/08/27 Update 4x4 Antenna connectors symbol Update JANT1,JANT2 connectors symbol. 0.2(X01)
C C

51 52 2018/08/27 Modified JSPK1 pin define to correct routing Swap JSPK1 pin define(1 to 8,2 to 7...). 0.2(X01)
52 58 2018/08/28 Modified SSD_SCP# pull up to reserved Change location RE821 to depop from pop. 0.2(X01)
1.Fixed power sequence EA request 1.Change CZ113 part to SE071101J80(100P_0402_50V8J) from SE074471K80(470P_0402_50V7K).
53 78 2018/08/31 2.Modified WLAN_PWR_EN pull up power rail according to 2.Add location RZ1483 SD028200280(20K_0402_5%) pull up to +3.3V_ALW. 0.2(X01)
Intel recommend Change RZ379 to depop from pop.
3.Delete unnecessary parts, align with X10 projects 3.Delete reserved location RZ375(20K_0402_5%).
54 01 2018/08/31 Modified Motherboard DPN(PWB) according to PJE request Change Merion14 PWB to 7YM2P from DD1CY. 0.2(X01)
1.Change CN61,CN62 part to SE102104K0(0.1U_0402_10V7K)
1.Modified M.2 2280 Power Decoupling for support from SE00000SV00(0.1U_0201_10V6K).
55 68 2018/08/31 Intel Teton Glacier Add location CN79,CN80,CN81,CN82,CN84 SE076103K80(0.01U_0402_16V7K). 0.2(X01)
2.Delete unnecessary parts, align with X10 projects Add location CN86 SE102104K00(0.1U_0402_10V7K).
Add location CN87 SE00000M000(22U_0603_6.3V6M).
2.Delete location RN125~RN128,RN77,RN78,RN81,RN82(0_0201_5%).
Delete reserved location RE375(0_0201_5%).
56 79 2018/08/31 Delete unnecessary parts, align with X10 projects Delete location RE560(0_0201_5%). 0.2(X01)
B Delete location RC740(0_0201_5%).
57 11 2018/08/31 Delete unnecessary parts, align with X10 projects Delete net PCH_PLTRST#_EC. 0.2(X01) B
Delete location RZ87(0_0201_5%).
58 66 2018/08/31 Delete unnecessary parts, align with X10 projects Delete reserved location DZ7(SCS00006300). 0.2(X01)
Change RZ1473 to depop from pop.
Change location CA78 to CA29.
59 56 2018/08/31 Modified location to correct Change location CA79 to CA49. 0.2(X01)

60 52 2018/09/03 JSIM1 footprint change to use 2nd source footprint Change JSIM1 footprint to TAISO_159-1000300600 from JAE_SF51S006V4DR1000Q. 0.2(X01)
61 09 2018/09/04 Modified CNV_RGI_DT pull up follow Intel RVP Change RC842 part to SD028200280(20K_0402_5%) from SD028100280(10K_0402_5%). 0.2(X01)
62 08 2018/09/04 Modified GPP_C2 pull up follow Intel RVP Change RC266 part to SD028470180(4.7K_0402_5%) from SD028220180(2.2K_0402_5%). 0.2(X01)
Change RZ1387,RV100 to SD00000ZS00(0.01_0603_1%) from SD00000XJ00(0.01_0805_1%).
63 38 2018/09/05 Reserved FUSE package location Add location RZ98,RV103 SD00000ZS00(0.01_0603_1%).(footprint is FUSE SP040007G00) 0.2(X01)

64 58 2018/09/07 Modified FPR pull up power rail Change RE706~RE709 pull up power rail to +3.3V_FPBTN from +3.3V_RUN. 0.2(X01)

A 65 38 2018/09/11 Modified part according to sourcer request Change CV15 part to SE00000G880(0.1U_0402_25V6) from SE074104K80(0.1U_0402_50V7K). 0.2(X01) A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
EE P.I.R
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number R ev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-G871P
Date: Tuesday, March 05, 2019 Sheet 107 of 109
5 4 3 2 1
 5 4 3 2 1

Version Change List ( P. I. R. List )

Issue Solution
Item Page# Date Description Description Rev.
1.Modified M-BIST circuit for DC mode LED flash issue 1.Change CZ218 part to SE00000X880(2.2U_0201_6.3V6M) from SE00000UC00(1U_0201_6.3V6M)
66 79 2018/10/31 2.Modified part according to sourcer request 2.Chane CZ218 part to SE000008880(2.2U_0402_6.3V6M) from SE00000X880(2.2U_0201_6.3V6M)0.3(X02)

D 67 56 2018/10/31 Modified part according to sourcer request Chane CA35 part to SE000008880(2.2U_0402_6.3V6M) from SE00000X880(2.2U_0201_6.3V6M). 0.3(X02) D
1.Modified part according to sourcer request 1.Chane CE12 part to SE000008880(2.2U_0402_6.3V6M) from SE00000X880(2.2U_0201_6.3V6M).
68 59 2018/10/31 2.Modified Board ID resistor to X02 2.Change RE79 part to SD028620280(62K_0402_5%) from SD028130380(130K_0402_5%). 0.3(X02)
1.Change location RV100 to FV1,RV103 to FV2,RZ98 to FZ1,RZ1387 to FZ2.
1.Add Fuse part,modified location Change RV100,RV103,RZ98,RZ1387 part to SP040007G00(Fuse 1A_0603).
69 38 2018/10/31 2.Modified part to reserved Fuse location 2.Change RZ1476 part to SD013000080(0_0603_5%) from SD028000080(0_0402_5%). 0.3(X02)
3.Modified CAM,Touch Fuse 3.Change FZ1,FV2 part to SP040007F00(Fuse 0.5A_0603) from SP040007G00(Fuse 1A_0603).
70 18 2018/10/31 Modified CPU BV23 pin power rail follow Intel RVP Change CPU BV23 pin power rail to +3.3V_ALW_PCH from +3.3V_SPI. 0.3(X02)
Change RZ10(100K_0402_5%) to pop from depop.
71 66 2018/10/31 Modified parts align with X10 projects Change RZ1414(0_0201_5%) to depop from pop. 0.3(X02)
Change RTC_DET# net connection to PCH side(GPP_D3) from EC side(GPIO011).
72 58 2018/10/31 Modified RTC_DET# net connection to PCH from EC side Delete location RE401 pull up SD043100280(10K_0201_5%). 0.3(X02)
Change RTC_DET# net connection to PCH side(GPP_D3) from EC side(GPIO011).
73 08 2018/10/31 Modified RTC_DET# net connection to PCH from EC side Add location RC866 pull up SD043100280(10K_0201_5%). 0.3(X02)

74 64 2018/10/31 Modified part follow LED light test result Change RZ32 to SD028100180(1K_0402_5%) from SD028330080(330_0402_5%). 0.3(X02)
C C

1.Modified parts shortage problem 1.Change QZ17 from SB00001GC00 to SB00001KM00

75 52 2018/11/30 2.Modified part according to RF request 2.Change RZ1460(0_0201_5%) and RZ1461(0_0201_5%) from depop to pop 0.3(X02)
3.Modified layout Limit height problem 3.Change part CZ26 from SGA00005T00(H.max=1.9mm) to SGA00006800(H.max=1.1mm)
76 11 2018/12/06 Follow NB14 UU AR, follow Intel CNVi recommendation Change RC237(100k_0402_5%) from depop to pop 0.3(X02)
1.Add RZ603 CNV_BRI_PTX_DRX_R pull up(10k_0402_5%) to +1.8_PRIM for reserve
77 52 2018/12/06 Follow NB14 UU AR, follow Intel CNVi recommendation 2.Delete location RZ371(0_0201_5%) and RZ81(0_0201_5%) 0.3(X02)
1.Change RC752 from SD028750280(75k_0402_5%) to SD034715280(71.5k_0402_1%)
78 12 2018/12/06 Follow NB14 UU AR, follow Intel CNVi recommendation 2.Change RC640 from SD034715280(71.5k_0402_1%) to SD028750280(75k_0402_5%) 0.3(X02)

79 13 2018/12/06 Follow NB14 UU AR, follow Intel CNVi recommendation UC1.CR35 add test point(T423) 0.3(X02)
Intel CNVi recommendation RC237 pop,But cold reset
80 11 2018/12/11 and global reset sequence timing fail,So depop RC237 Change RC237(100k_0402_5%) from pop to depop 0.3(X02)

81 52 2018/12/11 Add 4X4 WWAN netname Add netname +2.7V_ANT_R connect to JNGFF2.20, +1.8v_ANT_R connect to JNGFF2.24 0.3(X02)
B Add CI103(150U_B2_6.3VM_R35M) reserve Co-lay with CI1(100U_A_6.3VM_R70M) material
82 72 2018/12/11 Add CAP for reserve material shortage problem shortage problem 0.3(X02) B

83 77 2018/12/13 Modified according to DFX request Change CLIP1~CLIP12 form CLIP_0P6X7P0 to CLIP_0P8X7P0 0.3(X02)
1.Change CZ206 and CZ207 from depop to pop and change value from 100P to 27P
84 52 2018/12/13 Modified according to RF request 2.Add CZ311 and CZ312(27P_0402_50V8J) on +3.3V_WWAN for RF request 0.3(X02)
1.Add CZ313(27P_0201_25V8) on +LCDVDD for RF request
85 38 2018/12/13 Modified according to RF request 2.Add CZ314(27P_0402_50V8J) on +BL_PWR_SRC for RF request 0.3(X02)

86 64 2018/12/13 Modified according ME request Change RZ28 from SD028330080(330_0402_5%) to SD028150080(150_0402_5%) 0.3(X02)
1.Change Location from CZ313 to CV757
87 38 2018/12/17 Modified location to correct 2.Change Location from CZ314 to CV758 0.3(X02)
Add RC867(0_0201_5%) reserve for BITS392123, can't play music after resume from CMS
88 9 2018/12/18 Reserve for MOV issue with headphone connected 0.3(X02)
Follow spyglass, reserve for after global reset CNVI Add CNVI_EN# net connection to PCH side(GPP_H3), add RC868 PD(75K_0402_5%)
89 12 2018/12/18 module lost issue for CNVI_EN# 0.3(X02)
A Follow spyglass, reserve for after global reset CNVI 1.Add RZ827(0_0201_5%) connect to CNVI_EN# For reserve
90 52 2018/12/18 module lost issue 2.Change net name from CNV_RF_RESET to CNV_DET#_EC 0.3(X02) A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

https://Dr-Bios.com
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
EE P.I.R
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number R ev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.