Building a 4-bit Number

Crunching Machine
Assignment no.1
EE-222 Microprocessor Systems

Contents
1 Administrivia 3

1.1 Learning Objectives 3

1.2 Deliverables and Time-line 3

1.3 Marks Distribution 3

2 Introduction 4

3 Components (Logic ICs) Used 4

4 Arithmetic Logic Unit 4

4.1 Combinational Logic 4

4.2 Circuit Assembly 5

5 Data Registers 6

5.1 Functionality and Time Synchronization 6

5.2 Testing 8

5.3 Output Register 10

5.4 Register De-multiplexing 11

6 Control Logic 12

6.1 Instruction Memory 12

6.2 Program Counter 13

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6.3 Instruction Encoding 14

7 Programming 15

7.1 Fibonacci Numbers 16

8 Concluding Remarks 17

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1 Administrivia
1.1 Learning Objectives
This assignment will enable you to,

• Understand the basic principle of computing.

• Understand how computer processors are built with logic elements.

• Understand bare metal programming stack.

• Link Logic Design Concepts with this course.

1.2 Deliverables and Time-line

You are required to deliver and demonstrate a working hardware model of
this assignment by February 21, 2022 at 9am. You are also required to
submit a one-page report on LMS showing the snapshot of your final design
and the features implemented. A thorough understanding of the assignment
is necessary which will help you in oral viva.

1.3 Marks Distribution

The following marks distribution is tentative and is subjected to change
without any prior notice to the students.

Hardware Demo Viva Total Marks

20 10 30

2 Introduction
This assignment will introduce a design of a simple 4-bit number crunching
machine (which you may also call as 4-bit Microprocessor) and a

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walkthrough of its programming. You must transform this design into a
working hardware model with the help of logic ICs.
The design is divided into three parts Arithmetic Logic Unit (ALU), Data
Registers and Control Logic.

3 Components (Logic ICs) Used

• 4-bit D-type Registers

• 4-bit Binary Full Adder

• 4-bit Binary Counter

• Quad 2-Data Selectors

• 2-Line to 4-Line Decoder

• AND, OR, NOT and XOR Gates

• Parallel Address, Parallel 8-bit I/O EEPROM

4 Arithmetic Logic Unit

The Arithmetic Logic Unit (ALU) is the most basic and important part of any
computing machine. All the arithmetic or logical operations are performed
through it. The ALU used in this assignment will be able to perform binary
addition as well as 2’s complement binary subtraction.

4.1 Combinational Logic

The circuit requirement is to add or subtract two 4-bit numbers and
generate a carry. In order to choose between add and subtract operations,
we will be using a selection bit. The boolean equation for such a circuit can
be realized as,
Out = (A + B)S0 OR (A − B)S

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Here “A” and “B” are the two inputs, “Out” is the output and “S”,the selection
bit.
Subtraction will be carried out by inverting the bits (i.e. taking 1’s
complement) of B and raising the “carry in” of adder to logic 1, in order to
add an extra bit which will eventually generate 2’s complement of B.

A − B = A + (10s complement of B) + 1(carry in)

A − B = A + (20s complement of B)
For inverting the bits we will use XOR gate with one input tied to the
selection bit S, and the other to the input bit, such that when selection bit
goes 1, the property of XOR, B ⊕ 1 = B0 can be used and when it is 0 the input
passes unaffected B ⊕ 0 = B.

4.2 Circuit Assembly

The block diagram of ALU is shown in Figure 1.

Figure 1: Arithmetic Logic Unit (ALU)

Selection bit (S)Function

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 0Out = A + B 1Out = A − B

5 Data Registers
At least two 4-bit registers are required to hold the data for ALU. The output
of these two registers, say RA and RB, are directly connected to the two
inputs of the ALU, A and B respectively. The output of these registers is
always enabled i.e. they are always channeling data into the ALU. However
the input to these registers is controlled and data can only enter into them
when the input enable bit of RA and RB is at logic 1.

Figure 2: Register-ALU Assembly

5.1 Functionality and Time Synchronization

To start the computation, we need to load some initial values to RA and RB.
Moreover, we would also like to utilize these registers to save the output of
ALU too. In order to achieve this dual functionality, we need to add a 4-bit
1-out-of-2 data MUX before the input of registers. One of the MUX inputs
would be connected to ALU’s output and the other one to custom input. The
selection bit of this MUX, say Sreg must be 0 to let the ALU’s data pass
through and 1 for custom value. The updated datapath is shown in Figure 3.

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 A small D flip-flop is also placed adjacent to ALU to store the carry bit
into it on positive edge of clock so that we can examine the status of
arithmetic operation performed by ALU.
Here the concept of clock is important. We know that registers are made
of flip-flops that only store data on the positive edge of clock (assuming the
enable signal is 1, otherwise clock edges are in-effective). The small triangle
on RA and RB in Figure 3 symbolizes input clock.

Let’s see an example. Suppose through custom input (in past), 2 was
stored in RA and 3 in RB. Now, enable of RA is 1, enable of RB is 0, selection bit
(S) of ALU is 0 and Sreg is also 0. At the output of ALU, the sum 5 is present.
As soon as the positive edge of clock comes, 5 got stored in RA (as its enable
pin was high) and appears at the output of RA, the output of ALU becomes 8.
But due to “internal gate delays”, 8 appears a few nano-seconds after the
positive edge had passed and now it cannot enter any register until next
positive edge arrives. We can turn down the enable pins of registers to zero,
to make clock edges in-effective so that the incoming 8 may not replace
previously stored 5.

Figure 3: Modified Register-ALU Assembly

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5.2 Testing
Let’s test our design with a small “swapping” example. Usually when we
swap the values of two variables, we use another temporary variable to hold
data for sometime,

Initial state: x = a, y = b
{
temp = x
x=y
y = temp
}
Final state: x = b, y = a

However, there is another smart algorithm to swap data of two registers

without using any third register,

Initial state: x = a, y = b
{
x=x+y
y=x−y
x=x−y
}
Final State: x = b, y = a

There are four control signals (Sreg, enRA, enRB and S) and the 4-bit custom
input in our hands. First we shall load “a” to RA and “b” to RB, afterwhich we
will execute the algorithm. Here “a” and “b” are the 4-bit custom inputs.

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Figure 4: “Swapping” Control Signals Timing diagram

Step 1 Step 2

Step 3

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 Step 5

5.3 Output Register

A small addition to our design, the output register RO. We shall use this
register to store the final result after all the processing for the user to refer.
The register is directly connected with RA.

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 Figure 5: Output Register

5.4 Register De-multiplexing

There are now three signals associated with the registers, enA, enB and enO.
In order to reduce these signals we will use a 2-to-4 decoder (two inputs
and four outputs) with a truth table shown below,

Input (D0,D1)Output (O0,O1,O2,O3)

001000
010100
100010
110001

Now the outputs of decoder are connected such that O0 to enA, O1 is to enB
and O2 to enO,
Input (D0,D1)Output
00RA input enabled
01RB input enabled
10RO input enabled
11no operation

Keep in mind, from now onward we will call the value of D0D1, “address” of
the corresponding register.

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 Figure 6: Design with Decoder Incorporated

6 Control Logic
We cannot apply logic values on the control signals manually, all the time. In
order to avoid this inconvenience, we can store the values of control signals
in a non-volatile memory (ROM or EEPROM) and connect its output lines to
our design. Let’s call the values of the control signal stored in the memory
as Instructions.
6.1 Instruction Memory
Memory is an array (having rows and columns) of cells, which can store
binary data (1 or 0). For our design we will talk about those memories
having 8 cells (or bits) in each row. Each 8-bit wide row can be accessed by
its address starting from zero to (length of array - 1). We will store the set of
control signals one in each row. For example in “swapping” test, the set of
control signals was {110x, 101x, 0100, 0011, 0101}. We can store 110x in

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row(0), 101x in row(1) and so on. For an 8-bit row, each set of signals (also
called “instruction”) will take only four bits, the rest of bits, we don’t care.

6.2 Program Counter

In order to set the signals (or instruction) on the control lines of our design
before the positive edge of clock arrives, we will be using a 4-bit counter
connected to address line of instruction memory, such that initially the
value of counter is zero with zeroth row activated. As soon as the positive
edge of clock comes, zeroth instruction is executed by our design as well as
the counter gets incremented. Now the value of counter is one and row 1 of
instruction memory is activated. The incoming positive edge will execute
this instruction and the process goes on.

Figure 7: Memory and Program Counter

The program counter must have a 4-bit input and a load control such that
when some custom input is applied to 4-bit input of counter and load
control is kept high on the arrival of positive edge, the counter stores that
custom input into it and start counting from that specific value on the next
edge of clock. We wish to design a combinational logic around this feature
of counter.

Load = J OR (C AND “Carry out00)

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 Figure 8: Jump Logic

Here “J” and “C” are control signals in our hand such that when we apply
some custom input to counter and raise J to 1, the counter starts counting
from custom input. Similarly, when the carry out from ALU is 1 and we raise
C to 1, the counter starts counting from custom input. This phenomenon is
known as “JUMP” or “BRANCH” in computing language.

6.3 Instruction Encoding

Since the rows of instruction memory are 8-bits wide, we wish to adjust our
all control signals to these 8-bits. Moreover, our custom input is also
supposed to be a part of this instruction. One scheme to adjust all these
signals is,

Figure 9: 8-bit wide instruction

1. Jump (J): The seventh bit or MSB of the instruction is fixed for Jump.
Whenever we set it to 1, the custom input will be loaded in the
program counter.

2. Carry jump (C): The sixth bit is fixed for “jump if ALU operation
produces a carry”. Whenever we set it to 1, the custom input will be
loaded in the program counter.

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 3. Register Address (D1D0): The fifth and fourth bit of instruction is
fixed for register address. The values 00, 01, 10 and 11 corresponds to
RA, RB, RO and no register, respectively.

4. ALU or Custom input (Sreg): The third bit is reserved for multiplexing
ALU or custom input. When it is 0, ALU’s output is directed to
registers’ input otherwise, the custom input.

5. Custom input (immediate): The last three bits, zeroth, first and
second are reserved for custom input. Due to adjustment problem, we
have to compromise custom input length (to 3-bits only). The fourth
bit is hard wired to zero (ground), which means, we can only load
values ranging from 0 to 7 (either in program counter or registers).

6. ADD or SUB (S): The second bit of the instruction has dual function.
Apart from being part of custom input, it is also connected to ALU
selection bit S. This decision is taken based on the observation that
when ALU is performing either addition or subtraction, there is no
interference of custom input. Similarly, when we are loading some
custom input to either registers or counter, we don’t care about ALU
processing.

7 Programming
There are 9 functions we can perform with this machine. The functions and
the set of control signals for them are,

Function J C D1 D0 Sreg S

Custom Input

RA = R A + R B 0 0 0 0 0 0 0 0
RB = R A + R B 0 0 0 1 0 0 0 0
RA = RA − RB 0 0 0 0 0 1 0 0
RB = RA −RB 0 0 0 1 0 1 0 0
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 RO = RA 0 0 1 0 0 0 0 0
RA = imm 0 0 0 0 1 imm[2 imm[1] imm[0]
]
RB = imm 0 0 0 1 1 imm[2 imm[1] imm[0]
]
Jump to imm if 0 1 1 1 0 imm[2 imm[1] imm[0]
carry out ]
Jump to imm 1 0 1 1 0 imm[2 imm[1] imm[0]
]

Figure 10: 4-bit Number Crunching Machine

7.1 Fibonacci Numbers

Below is a Program that will produce Fibonacci sequence in the output
register.

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 0 RA = 0 00001000 load zero to A
1 RB = 1 00011001 load 1 to B
2 RO = RA 00100000 push A to output
3 RB = R A + R B 00010000 Add A to B
4 jump if carry 01110000 If A+B produce carry jump to start
5 RA = R A + R B 00000000 Swap A and B
6 RB = RA − RB 00010100 Swap A and B
7 RA = RA − RB 00000100 Swap A and B
8 jump to 2 10110010 jump to 3rd instruction
8 Concluding Remarks
The design of a number crunching machine presented in this document is
actually a baby processor core. All the processing units integrated into your
laptops, mobiles and embedded devices are based on the same basic
principle. You can implement some other interesting programs like
multiplying two numbers or generating tables of 1, 2, 3, ..., etc. You can
extend the functionality of this machine by adding more operations to the
ALU, increase the data chunk size from 4-bits to 6, 8, ...etc.
In short, if you are able to successfully complete this assignment and can
extend or adapt it according to your need, you have gained a strong hold on
the basics of Processors. This assignment will bridge the gap between
EE-212 Digital Logic Design and EE-222 Microprocessor System.

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