Colibri Computer Module

Carrier Board Design Guide

 Colibri Carrier Board Design Guide

Issued by: Toradex Document Type: Carrier Board Design Guide

Purpose: This document is a guideline for developing a carrier board that confirms to the specifications
for the Colibri Computer Module

Document 1.5
Version:

Revision History Version Remarks

Date

13 April 2015 V1.0 Initial Release: Preliminary Version

28 Sept 2015 V1.1 Correct figure 3 and figure 4 in section 2.3.2 (positive and negative USB
signals were swapped in schematics)

22 October 2015 V1.2 Corrections in figure 4 in section 2.3.2 (pull up resistor of USB_OC# and
pull down of USBH_EN where swapped)
Correction in typical pull up value for I2C in section 2.9

15 June 2016 V1.3 Add section 2.1.4 “Pin Reset State”

Section 2.16: Updated information to input voltage range
Section 2.17: Add note to the usage of PXA270
Section 3.1.3: insert information to nVDD_FAULT, nGPIO_RESET, and
nBATT_SENSE
Section 3.5: Add information to bulk capacitors.

06 April 2017 V1.4 Section 2.2, Ethernet: Minor correction in figure 2

Section 2.5, HDMI/DVI: Correction in figure 12 (differential pair
impedance value)
All reference schematic images: Cosmetic update.
Section 1.2, Section 4 & Section 5: Updated web-links

14 Dec 2018 V1.5 Section 2.2.2: Add recommendation for ESD protection diodes
Section 2.3.1: Add note regarding default polarity of USB_H_PWR_EN
Section 2.3.2: Add USB OTG reference schematic
Section 2.3.2: Remove 15k pull down on USB data signals
Section 2.3.2.3: Change to active low version of power switch (TPS2042
instead of TPS2052)
Section 2.15.3: Update recommendation for unused touch signals
Section 2.16.1: Correct pin numbers

Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected] Page | 2
 Colibri Carrier Board Design Guide

1 Introduction ....................................................................................................................... 5
1.1 Overview ............................................................................................................................. 5
1.2 Additional Documents .......................................................................................................... 5
1.2.1 Layout Design Guide ................................................................................................. 5
1.2.2 Colibri Module Datasheets ......................................................................................... 5
1.2.3 Toradex Developer Centre ......................................................................................... 5
1.2.4 Colibri Evaluation Board Schematics .......................................................................... 5
1.2.5 Pinout Designer ........................................................................................................ 6
1.3 Abbreviations ....................................................................................................................... 6
2 Interfaces ........................................................................................................................... 8
2.1 Architecture ......................................................................................................................... 8
2.1.1 Standard Interfaces ................................................................................................... 8
2.1.2 Interfaces on Alternative Functions ............................................................................. 8
2.1.3 Pin Numbering .......................................................................................................... 9
2.1.4 Pin Reset State ......................................................................................................... 9
2.2 Ethernet ............................................................................................................................ 10
2.2.1 Ethernet Signals ...................................................................................................... 10
2.2.2 Reference Schematics ............................................................................................. 10
2.2.3 Unused Ethernet Signals Termination ....................................................................... 11
2.3 USB .................................................................................................................................. 11
2.3.1 USB Signals ........................................................................................................... 11
2.3.2 Reference Schematics ............................................................................................. 12
2.3.3 Unused USB Signal Termination .............................................................................. 13
2.4 Parallel RGB LCD Interface ................................................................................................ 14
2.4.1 Parallel RGB LCD Signals ....................................................................................... 14
2.4.2 Reference Schematics ............................................................................................. 14
2.4.3 Unused Parallel RGB Interface Signal Termination .................................................... 17
2.5 HDMI/DVI .......................................................................................................................... 18
2.5.1 HDMI/DVI Signals ................................................................................................... 18
2.5.2 Reference Schematics ............................................................................................. 18
2.5.3 Unused HDMI/DVI Signal Termination ...................................................................... 20
2.6 Analogue VGA ................................................................................................................... 21
2.6.1 VGA Signals ........................................................................................................... 21
2.6.2 Reference Schematics ............................................................................................. 21
2.6.3 Unused VGA Interface Signal Termination ................................................................ 22
2.7 Parallel Camera Interface ................................................................................................... 22
2.7.1 Parallel Camera Signals .......................................................................................... 22
2.7.2 Unused Parallel Camera Interface Signal Termination ............................................... 23
2.8 SD/MMC/SDIO .................................................................................................................. 23
2.8.1 SD/MMC/SDIO Signals ............................................................................................ 23
2.8.2 Reference Schematics ............................................................................................. 24
2.8.3 Unused SD/MMC/SDIO Interface Signal Termination ................................................. 24
2.9 I2C .................................................................................................................................... 24
2.9.1 I2C Signals .............................................................................................................. 24
2.9.2 Real-Team Clock (RTC) recommendation ................................................................. 24
2.9.3 Unused I2C Signal Termination................................................................................. 25
2.10 UART ................................................................................................................................ 25
2.10.1 UART Signals ...................................................................................................... 25
2.10.2 Reference Schematics ......................................................................................... 26
2.10.3 Unused UART Signal Termination ......................................................................... 27
2.11 SPI ................................................................................................................................... 28
2.11.1 SPI Signals .......................................................................................................... 28
2.11.2 Unused SPI Signal Termination ............................................................................ 28
2.12 CAN .................................................................................................................................. 28
2.12.1 Reference Schematics ......................................................................................... 28
2.13 PWM................................................................................................................................. 29

Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected] Page | 3
 Colibri Carrier Board Design Guide

2.13.1 PWM Signals ....................................................................................................... 29

2.13.2 Reference Schematics ......................................................................................... 29
2.13.3 Unused PWM Signal Termination .......................................................................... 29
2.14 Analogue Audio ................................................................................................................. 30
2.14.1 Analogue Audio Signals ....................................................................................... 30
2.14.2 Reference Schematics ......................................................................................... 30
2.14.3 Unused Analogue Audio Signal Termination .......................................................... 31
2.15 Touch Panel Interface ........................................................................................................ 32
2.15.1 Resistive Touch Signals ....................................................................................... 32
2.15.2 Reference Schematics ......................................................................................... 32
2.15.3 Unused Touch Panel Interface Signal Termination ................................................. 32
2.16 Analogue Inputs ................................................................................................................. 33
2.16.1 Analogue Input Signals ......................................................................................... 33
2.16.2 Unused Analogue Inputs Signal Termination .......................................................... 33
2.17 Parallel Memory Bus (External Memory Bus) ....................................................................... 33
2.17.1 Memory Bus Signals ............................................................................................ 33
2.17.2 Unused Memory Bus Signals Termination ............................................................. 35
2.18 GPIO ................................................................................................................................ 35
2.18.1 Preferred GPIO Signals ........................................................................................ 35
2.18.2 Unused GPIO Termination .................................................................................... 35
3 Power Management ........................................................................................................... 36
3.1 Power Signals ................................................................................................................... 36
3.1.1 Digital Supply Signals .............................................................................................. 36
3.1.2 Analogue Supply Signals ......................................................................................... 36
3.1.3 Power Management Signals .................................................................................... 36
3.2 Power Block Diagram ......................................................................................................... 37
3.3 Power States ..................................................................................................................... 39
3.4 Power-Up Sequence .......................................................................................................... 39
3.5 Reference Schematics ....................................................................................................... 40
4 Mechanical and Thermal Consideration ............................................................................... 42
4.1 Module Connector.............................................................................................................. 42
4.2 Fixation of the Module ........................................................................................................ 42
4.3 Thermal Solution................................................................................................................ 44
4.4 Module Size ...................................................................................................................... 44
5 Appendix A – Physical Pin Definition and Location ............................................................... 45

Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected] Page | 4
 Colibri Carrier Board Design Guide

1 Introduction

1.1 Overview

This document guides the development of a customized carrier board for the Colibri computer
module. It describes the different interfaces and contains reference schematics. This document
reflects only the standardized primary function of the Colibri modules. The alternative functions are
not guaranteed to be compatible between different Colibri modules. These interfaces are described
in the datasheet of each computer module. Some Colibri modules do not feature the full set of
standard interfaces. Therefore, it is strongly recommended to read the datasheets of the modules
that are intended to be used with the carrier board.

Some of the Colibri computer module interfaces such as High-Speed USB, Ethernet, etc. require
special layout considerations regarding trace impedance and length matching. Please carefully
read the Toradex Layout Design Guide for additional information related to the routing of these
interfaces.

1.2 Additional Documents

1.2.1 Layout Design Guide

This document contains layout requirement specifications for the high-speed signals and helps in
avoiding problems related to the layout.

http://developer.toradex.com/carrier-board-design/carrier-board-design-guides

1.2.2 Colibri Module Datasheets

There is a datasheet available for every Colibri module. Amongst other things, this document
describes the type-specific interfaces and the alternative function of the pins. Before starting the
development of a customized carrier board, please check this document to find out whether the
required interfaces are really available on the selected modules.

https://www.toradex.com/computer-on-modules/colibri-arm-family

1.2.3 Toradex Developer Centre

You can find a lot of additional information at the Toradex Developer Centre, which is updated
with the latest product support information on a regular basis.

Please note that the Developer Centre is common for all Toradex products. You should always
check to ensure if the information is valid or relevant for the specific Colibri modules.

http://www.developer.toradex.com

1.2.4 Colibri Evaluation Board Schematics

We provide the complete schematics plus the Altium project file for the Colibri Evaluation Board for
free. This is a great help when designing your own Carrier Board.

http://developer.toradex.com/products/colibri-evaluation-board

Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected] Page | 5
 Colibri Carrier Board Design Guide

1.2.5 Pinout Designer

This is an interactive and useful tool for configuring the pin muxing of the Colibri and Apalis
modules. It can be really helpful in custom carrier board development on Toradex modules and for
checking the compatibility of existing carrier boards with our modules.

http://developer.toradex.com/carrier-board-design/pinout-designer-tool

1.3 Abbreviations

Abbreviation Explanation
ADC Analogue to Digital Converter
AGND Analogue Ground - separate ground for analogue signals
Automatically Medium Dependent Interface Crossing - a PHY with Auto-MDIX f is able to detect whether
Auto-MDIX
RX and TX need to be crossed (MDI or MDIX)
CAD Computer-Aided Design - in this document is referred to PCB Layout tools
CAN Controller Area Network - a bus that is manly used in automotive and industrial environment
Code Division Multiplex Access - abbreviation often used for a mobile phone standard for data
CDMA
communication
CEC Consumer Electronic Control - HDMI feature that allows to control CEC compatible devices
CPU Central Processor Unit
CSI Camera Serial Interface
DAC Digital to Analogue Converter
Display Data Channel - interface for reading out the capability of a monitor, in this document DDC2B
DDC
(based on I2C) is always meant
DRC Design Rule Check - a tool for checking whether all design rules are satisfied in a CAD tool
DSI Display Serial Interface
DVI Digital Visual Interface - digital signals are electrical compatible with HDMI
DVI-A Digital Visual Interface Analogue only - signals are compatible with VGA
DVI-D Digital Visual Interface Digital only - signals are electrical compatible with HDMI
DVI-I Digital Visual Interface Integrated - combines digital and analogue video signals in one connector
EDA Electronic Design Automation - software for schematic capture and PCB layout (CAD or ECAD)
EDID Extended Display Identification Data - timing setting information provided by the display in a PROM
EMI Electromagnetic Interference - high frequency disturbances
Embedded Multi Media Card - flash memory combined with MMC interface controller in a BGA package,
eMMC
used as internal flash memory
ESD Electrostatic Discharge - high voltage spike or spark that can damage electrostatic- sensitive devices
Flat Panel Display Link - high-speed serial interface for liquid crystal displays. In this document also called
FPD-Link
LVDS interface.
GBE Gigabit Ethernet - Ethernet interface with a maximum data rate of 1000Mbit/s
GND Ground
GPIO General Purpose Input/Output pin that can be configured to be either an input or output
GSM Global System for Mobile Communications
HDA High Definition Audio (HD Audio) - digital audio interface between CPU and audio codec
HDCP High-Bandwidth Digital Content Protection - copy protection system that is used by HDMI beside others
High-Definition Multimedia Interface - combines audio and video signal for connecting monitors, TV sets
HDMI
or Projectors, electrical compatible with DVI-D
I2C Inter-Integrated Circuit - two wire interface for connecting low speed peripherals
I2S Integrated Interchip Sound - serial bus for connecting PCM audio data between two devices
IrDA Infrared Data Association - infrared interface for connecting peripherals
JTAG Joint Test Action Group - widely used debug interface
LCD Liquid Crystal Display
LSB Least Significant Bit
Low-Voltage Differential Signaling - electrical interface standard that can transport very high-speed
LVDS
signals over twisted-pair cables. Many standard interfaces like PCIe or SATA use this interface standard.

Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected] Page | 6
 Colibri Carrier Board Design Guide

Abbreviation Explanation
Since the first successful application was the Flat Panel Display Link, LVDS has become synonymous for
this interface. In this document, the term LVDS is used for the FPD-Link interface.
MIPI Mobile Industry Processor Interface Alliance
MDI Medium Dependent Interface - physical interface between Ethernet PHY and cable connector
MDIX Medium Dependent Interface Crossed - an MDI interface with crossed RX and TX interfaces
PCI Express Mini Card - card form factor for internal peripherals. The interface features PCIe and USB
mini PCIe
2.0 connectivity
MMC MultiMediaCard - flash memory card
MSB Most Significant Bit
mSATA Mini-SATA - a standardized form factor for small solid state drive, similar dimensions as mini PCIe
N/A Not Available
N/C Not Connected
OD Open Drain
USB On-The-Go - a USB host interface that can also act as USB client when connected to another host
OTG
interface
OWR One Wire (1-Wire) - low speed interface which needs just one data wire plus ground
PCB Printed Circuit Board
PCI Peripheral Component Interconnect - parallel computer expansion bus for connecting peripherals
PCIe PCI Express - high-speed serial computer expansion bus, replaces the PCI bus
Pulse-Code Modulation - digital representation of analogue signals and a standard interface for digital
PCM
audio
PD Pull Down Resistor
PHY Physical Layer of the OSI model
PMIC Power Management IC - integrated circuit that manages amongst others the power sequence of a system
PU Pull-up Resistor
PWM Pulse-Width Modulation
RGB Red Green Blue - color channels in common display interfaces
RJ45 Registered Jack - common name for the 8P8C modular connector that is used for Ethernet wiring
RS232 Single ended serial port interface
RS422 Differential signaling serial port interface - full duplex
RS485 Differential signaling serial port interface - half duplex, multi drop configuration possible
Removable User Identity Module - identifications card for CDMA phones and networks, an extension of
R-UIM
the GSM SIM card
S/PDIF Sony/Philips Digital Interconnect Format - optical or coaxial interface for audio signals
SATA Serial ATA, high-speed differential signaling interface for hard drives and SSD
SD Secure Digital - flash memory card
SDIO Secure Digital Input Output - an external bus for peripherals that uses the SD interface
SIM Subscriber Identification Module - identification card for GSM phones
System Management Bus (SMB) - two wire bus based on the I2C specifications, used specially in x86
SMBus
design for system management.
SoC System on a Chip - IC which integrates the main component of a computer on a single chip
Small Outline Dual Inline Memory Module - form factor for mobile RAM modules, the Colibri module uses
SO-DIMM
the SO-DIMM (DDR, 2.5V variant) connector as main interface
SPI Serial Peripheral Interface Bus - synchronous four wire full duplex bus for peripherals
TIM Thermal Interface Material - thermal conductive material between CPU and heat spreader or heat sink
Transition-Minimized Differential Signaling - serial high-speed transmitting technology that is used by DVI
TMDS
and HDMI
TVS Diode Transient-Voltage-Suppression Diode - diode that is used to protect interfaces against voltage spikes
Universal Asynchronous Receiver/Transmitter - serial interface, in combination with a transceiver a
UART
RS232, RS422, RS485, IrDA or similar interface can be achieved
USB Universal Serial Bus - serial interface for internal and external peripherals
VCC Positive supply voltage
VGA Video Graphics Array - analogue video interface for monitors

Table 1: Abbreviations

Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected] Page | 7
 Colibri Carrier Board Design Guide

2 Interfaces

2.1 Architecture
2.1.1 Standard Interfaces

The standard interfaces on the Colibri module family intent to provide electrical and functional
compatibility between module family members. The table below shows an overview of the
standard interfaces that are provided by a Colibri module. The “GPIO Capable” column indicates
whether the assigned pins are intent to be also used as GPIOs. “Yes” and “No” are self-
Explanatory. “Optional” indicates that it may be possible for some modules, but not all.

The “Standard” column indicates the number of interfaces that the specification allows for in the
standard pin-out. Customers should consult the datasheet for specific Colibri module variants to
check which of the interfaces are available for that module.

GPIO
Description Standard Note
Capable
4/5 Wire Resistive Touch 1 Touch wiper shared with analogue input 4 No
Analogue Inputs 4 Minimum 8 bit resolution, 0-3.3V nominal range No
Analogue Audio 1 Line in L&R, Microphone in, Headphone out L&R No
Fast Ethernet 1 No
Located on dedicated FFC connector
HDMI (TDMS) 1 No
(availability depending on Module)
I2C 1 Additional dedicated DDC available on FFC connector Yes
Parallel Camera 1 8 bit BT.656 (other modes may available) Yes
Parallel LCD 1 18 bit resolution (additional bits may available) Yes
Parallel Memory Bus 1 Supported bus width depends on Module Optional
PWM 4 Yes
SDIO 1 4 bit Yes
SPI 1 Yes
UART 3 1x Full Featured, 1x CTS/RTS, 1x RXD/TXD only Yes
USB 2 1x shared host/client, 1x host only No
Located on dedicated FFC connector
VGA 1 No
(availability depending on Module)

Table 2: Standard Interfaces

2.1.2 Interfaces on Alternative Functions

Many SoC pins can be used for more than one function. This allows the modules provide many
additional interfaces to the standard set. For example, in the Colibri standard there is only one SPI
interface listed. Nevertheless, some modules can provide up to 6 SPI interfaces.

Please note that there are a few restrictions of using the interfaces that are provided as alternative
functions of the pins. There is limited compatibility between their availability at different modules.
For a design to be compatible with a wide range of Colibri modules, it is recommended to mainly
use the standard interfaces. The various pins can be used for only one function each
simultaneously.

The configuration of the alternative function interfaces can be quite complex. Toradex provides a
powerful tool which helps the development engineer to resolve pin muxing conflicts. The tool is
called Pinout Designer. It reduces the complexity of this important task. More information including
its download link can be found here:
http://developer.toradex.com/carrier-board-design/pinout-designer-tool

Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected] Page | 8
 Colibri Carrier Board Design Guide

The interfaces on the alternative functions are not described in this document since they differ
between the modules. Information related to these functions can be found in the datasheets of the
modules.

2.1.3 Pin Numbering

The diagrams in the figures below show the pin numbering schema on both sides of the module.
The schema is equals to the JEDEC MO-224 DDR SO-DIMM standard. The odd pin numbers are
located on the top side of the module.

Pin1 Pin39 Pin47 Pin199

Pin2 Pin40 Pin42 Pin200

Figure 1: Colibri Module Pin Numbering Schema

2.1.4 Pin Reset State

The datasheets of the Colibri module provide information about the default reset status of the IO
pins. Please be aware, the pin reset status is only guaranteed during the release of the reset
signal. Some of the modules switches the IO bank voltages in order to follow the power up
sequence of the SoC. This means, the IO pins can have an undefined state between applying the
main power to the module until the nRESET_OUT is released. For carrier board designs that do not
allow undefined pin states, it is recommended to make sure that the peripheral devices are not
getting powered before the nRESET_OUT is released. Another solution can be gating the according
IO signals with the nRESET_OUT signal.

Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected] Page | 9
 Colibri Carrier Board Design Guide

2.2 Ethernet

The Colibri module standard features a fast 10/100Mbit Ethernet (10/100Base-TX) interface port.
The required center tap circuit can differ between the modules. Different assembly options might
be needed for supporting the complete Colibri module family. Some modules support Auto MDIX,
which means they can swap the transmitting with the receiving lanes. Read the corresponding
datasheet of the module for more information about the availability of the Auto MDIX function.

2.2.1 Ethernet Signals

Colibri Colibri Power

I/O Type Description
Pin Signal Name Rail
189 ETH_1_TXO+ I Analogue 100BASE-TX: Transmit + (Auto MDIX: Receive +)
187 ETH_1_TXO- I Analogue 100BASE-TX: Transmit - (Auto MDIX: Receive -)
195 ETH_1_RXI+ O Analogue 100BASE-TX: Receive + (Auto MDIX: Transmit +)
193 ETH_1_RXI- O Analogue 100BASE-TX: Receive - (Auto MDIX: Transmit -)
191 AGND_LAN Ethernet ground, on some modules connected to common GND
183 ETH_1_LINK_AKT O CMOS 3.3V LED indication output for link activity on the Ethernet port
185 ETH_1_SPEED100 O CMOS 3.3V LED indication output for 100Mbit/s

Table 3: Ethernet Signals

2.2.2 Reference Schematics

Ethernet connectors with integrated magnetics are preferable. If a design with external magnetics
is chosen, additional care has to be taken to route the signals between the magnetics and Ethernet
connector.

The LED output signals ETH_1_LINK_AKT and ETH_1_SPEED100 can be connected directly to the
LED of the Ethernet jack with suitable serial resistors. There is no need for additional buffering if
the current drawn does not exceeds 10mA.

The Fast Ethernet interface uses the ETH_1_TXO as transmitting lanes and the ETH_1_RXI as
receiving lane. If the Ethernet PHY features Auto-MDIX, the signal lanes RX and TX could be
swapped. We strongly recommend not swapping the RX and TX lanes in order to keep the
compatibility with all Colibri modules.

The required center tap circuit depends on the supported modules. Currently, the Ethernet
controller on the PXA270 module is the only one which requires a different center tap circuit since
it does not support Auto-MDIX. All the other currently available modules feature a current control
PHY which requires 3.3V supply at the center tap of the RX and TX lanes. Since all the Ethernet PHY
manufacturer are tending to change from current mode to voltage mode which requires leaving
the center tab pins of the magnetics unconnected, we recommend to add additional 0R resistors
into the center tab lines. This ensures that the carrier board design is ready for any future Colibri
module with voltage mode PHY.

The magnetics provide a certain ESD protection which is sufficient for many designs. However,
especially in Power over Ethernet (PoE) systems, additional transient voltage suppressor diodes
(TVS) are highly recommended to be placed between the module and the magnetics. More
information can be found in the following application note from Microchip:
http://ww1.microchip.com/downloads/en/AppNotes/00002157B.pdf

Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected] Page | 10
 Colibri Carrier Board Design Guide

L10 R10 R11 R12 Module

3.3V 2A ETH_AVCC
220R@ 100MHz C4 8 C49 NA 0R 0R All except PXA270

+
0R NA 0R PXA270
47uF 47uF Ethernet Connector
6.3V 6.3V NA NA NA Reserved for future modules
(Integrated Magnetics)
ETHERNET[0..5] ETH_AVCC
GND GND X17
ETH_TX 0_P 1
TD +
X1B 100nF R20
183 ETH_LINK_ACT C45 16V 50R R10 R12 ETH_CT_TX 4
ETH_LINK_ACT GND CT_TX D
185 ETH_SPEED R21 0R 0R
ETH_SPEED
50R
NA
ETH_TX 0_N 2
TD -
187 ETH_TX0_N
ETH_TX0-
189 ETH_TX0_P ETH_RX I_P 3
ETH_TX0+ RD +
100nF R22
191 C46 16V 50R R11 ETH_CT_RX 5
ETH_GND GND GND CT_RX D
R23 0R
193 ETH_RXI_N ETH_RX I_N 50R 6
ETH_RXI- RD -
195 ETH_RXI_P
ETH_RXI+
9 7
R24 150R 3.3V LED_Left_ A NC
Colibri - Ethernet ETH_LINK_ACT 10
LED_Left_ C CH S GND
8
12 S1
3.3V LED_R ight_ A SHIELD
2 of 16 ETH_SPEED R25 150 R 11 S2
LED_R ight_ C SHIELD
1473005 -1
C47 C44 J00- 0065N L
100nF 100nF
SHIELD
16 V 16V

GND GND

Figure 2: Fast Ethernet with Integrated Magnetics Reference Schematic

2.2.3 Unused Ethernet Signals Termination

All unused Ethernet signals can be left unconnected.

2.3 USB

The Colibri modules feature two USB interfaces. One of the two USB interfaces can be configured
to be used as either the host or client. The other interface can only be used as host. Some of the
Colibri modules use the USB client port for debugging and recovery purpose. Therefore, it is
recommended to have the interface accessible even for carrier board designs which do not need
any USB ports.

2.3.1 USB Signals

Colibri Colibri Power

I/O Type Description
Pin Signal Name Rail
139 USB_H_DP I/O USB 3.3V Positive Differential Signal for USB Host port
141 USB_H_DM I/O USB 3.3V Negative Differential Signal for USB Host port
143 USB_C_DP I/O USB 3.3V Positive Differential Signal for the shared USB Host / Client port
145 USB_C_DM I/O USB 3.3V Negative Differential Signal for the shared USB Host / Client port

Table 4: USB Data Signals

If you use the USB Host function you need to generate the 5V USB supply voltage on your carrier
board. The Colibri modules provide two optional signals for USB power supply control (PWR_EN
and OC). We recommend using the following pins to ensure the best possible compatibility.
However, use of these signals is not mandatory and other GPIOs may be used instead.
In the USB client mode, an additional signal is required that detects whether the client is connected
to a host interface (VBUS_DETECT). Please note that this pin is only 3.3V tolerant. Therefore, an
additional logic level shifter (simplest solution is a voltage divider) is required.

Colibri Colibri Power

I/O Type Description
Pin Signal Name Rail
This pin enables the external USB voltage supply. By default, this
129 USB_H_PWR_EN O CMOS 3.3V
pin is active low.
USB overcurrent, this pin can signal an over current condition in
131 USB_H_OC I CMOS 3.3V
the USB supply
137 USB_C_VBUS_DETECT I CMOS 3.3V Use this pin to detect if VBUS is present (5V USB supply). Please
note that this pin is only 3.3V tolerant

Table 5: USB Control Signals

Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected] Page | 11
 Colibri Carrier Board Design Guide

2.3.2 Reference Schematics

2.3.2.1 USB 2.0 Client Schematic Example

The differential USB data signals require a common mode choke to be placed. Make sure that the
selected choke is certified for USB 2.0 High Speed. The same is also required for the TVS diodes.
The VBUS_DETECT signal is only 3.3V tolerant on the Colibri module. The simplest solution is to
use a voltage divider.
X1C X2
L2
145 USBO1_D_N 2 3 USBO1_D_CON_N 2
USBC_N D-
143 USBO1_D_P 1 4 USBO1_D_CON_P 3
USBC_P D+
90R@100MHz
VCC_USBO1
137 USBO1_VBUS 1
PIN_137/USBC_CABLEDET VCC
131 S1
PIN_131/USB_OC
129 D1 4 S2
PIN_129/USB_P_EN GND
141 3 4 61729-0010BLF
USBH_N
139 5V_ESD 5V SHIELD
USBH_P L3 L1
Colibri - USB 2 5
SHIELD C1
4A 2A
39R@100MHz 220R@100MHz
3 of 16 R73 1 6 100nF
1473005-1 560R GND_USBO1 GND
R74 SHIELD
1K RCLAMP0504S Optional
VCC_USBO1
GND
R3
330R
LED1
GREEN
GND

Figure 3: USB 2.0 Client Reference Schematic

2.3.2.2 USB 2.0 OTG Schematic Example

The Colibri standard does not support the full USB OTG function. However, it is possible to
implement a circuit on the carrier board that allows to change the role from host to client
depending on the level of the ID pin of a Micro-AB jack. The reference schematic differs from other
USB OTG solution, since the module itself does not use directly the ID pin for detecting whether
the port is supposed to be set in client or host mode. The pin is indirectly used.

If no cable is plugged into the Micro-AB jack, the port is configured to host mode and the 5V
power output (VCC_USB2 in the schematic below) is disabled. If a Micro-B is plugged in (ID pin is
floating on such plugs), the VCC_USB2 comes from the cable since the system gets plugged into a
host. With help of the voltage divider, the USB_C_DET signal gets around 3.3V. This signalizes the
module that it has been connected to a host and need to switch to client mode.

If a Micro-A connector is inserted, the ID pin gets shorted to ground. This ID pin enables the output
of the TPS2042 power switch. This voltage on the VCC_USB2 rail is used to power any client device
that is connected to the port. Additionally, the ID pin keeps over a diode the USB_C_DET signal
low, even though the VCC_USB2 rail went up to 5V. This makes sure the module remains in host
mode in order to be able to communicate with the client device that is plugged in.

Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected] Page | 12
 Colibri Carrier Board Design Guide

VCC_USB2
X12
1 Alternative part for connector X12:
L15 VCC
USBC_N 1 4 USB_CLIENT_N 2 - TE/Tyco, 1981584-1
D-
USBC_P 2 3 USB_CLIENT_P 3 S1
D+
USB_ID 4 S2
90R@100MHz ID C129
VCC_USB2 5 S3 R37
GND 1nF
1M
2KV
ZX62-AB-5PA(31)
USB Host / Client

6
X1C
C104
D11 GND Micro-AB type GND CHASSIS_GND
100nF
143 16V
USBC_P

RCLAMP0504S
145
USBC_N
GND
137 USB_C_DET
PIN_137/USBC_CABLEDET
131 USB_OC
PIN_131/USB_OC
129
PIN_129/USB_P_EN

1
139 3.3V
USBH_P
141
USBH_N
Colibri - USB R61 GND
D12B 100K
3 of 16 USB_ID
1473005-1
BAT54C 3.3V

R50
USB_OC 100K

3.3V 5V
IC1
2 8
V_IN OC_1#
1 5
GND GND OC_2#
3 7
EN_1# OUT_1 L18
USB_ID 4 6
EN_2# OUT_2 2A VCC_USB2
C42 220R@100MHz C43
TPS2042BD R115
22uF 100nF
10V 16V 560R

GND GND

USB_C_DET USB_C_DET

R116
1K

GND

Figure 4: USB 2.0 OTG Reference Schematic

2.3.2.3 USB 2.0 Host Connector Schematic Example
The carrier board needs to provide 5V USB bus power on the USB host jacks. According to the USB
2.0 specifications, the maximum current drawn per port is limited by 500mA. The bus power needs
to be in the range of 4.75V to 5.25V measured at the USB host jack for any load current from 0mA
to 500mA. In order to ensure that an out of spec device or a defective device is not damaging the
5V power rail on the carrier board, it is recommended adding a current limiting IC. This device
detects overcurrent situation and switches off the corresponding USB bus power. The overcurrent
signal (USB_H_OC) is used to notify the host controller about the occurrence of an overcurrent shut
down event.
The inrush current needs to be taken into account while designing the USB bus power. USB devices
are allowed to have a maximum input capacitor at the bus power of 10µF. The maximum inrush
charge is limited to 50µC. This means that the power rail at the USB host jack needs to be tolerant
of this inrush current. A good approach is to place a large capacitor (e.g. 100µF) at the rail.

3.3V Optional
5V IC? VCC_USBH VCC_USBH
R2 220R@100MHz
2 7
100K V_IN OUT_1 2A
+

USBH_EN# 3 C1 C2 C3 R1
EN_1# 100nF 100uF L3 1nF
USBH_OC# 8 16V 10V 50V 330R
OC_1#
3.3V LED1
X1C R3 4 6GND GND GND_USBH
EN_2# OUT_2 GREEN
145 100K 5
USBC_N OC_2#
143 1 GND
USBC_P GND GND
GND
137 TPS2042BD X2
PIN_137/USBC_CABLEDET
131 USBH_OC#
PIN_131/USB_OC
129 USBH_EN#
PIN_129/USB_P_EN
1 S1
L1 VCC
141 USBH2_D_N 2 3 USBH2_D_CON_N 2 S2
USBH_N D-
139 USBH2_D_P 1 4 USBH2_D_CON_P 3 S3
USBH_P D+
Colibri - USB D2 4 S4
90R@100MHz GND
3 of 16 2 1 292303-1
1473005-1 D- D+ L2
2A
SHIELD
220R@100MHz
TPD2EUSB30DRTR
GND_USBH GND
GND

Figure 5: USB 2.0 Host Reference Schematic

2.3.3 Unused USB Signal Termination

Colibri Colibri
Recommended Termination
Pin Signal Name
139 USB_H_DP Leave NC if not used
141 USB_H_DM Leave NC if not used
143 USB_C_DP Leave NC if not used

Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected] Page | 13
 Colibri Carrier Board Design Guide

Colibri Colibri
Recommended Termination
Pin Signal Name
145 USB_C_DM Leave NC if not used
129 USB_H_PWR_EN Leave NC if not used
131 USB_H_OC Add pull-up resistor or disable the overcurrent function in software
137 USB_C_VBUS_DETECT Leave NC if not used
Table 6: Unused USB Signals Termination

2.4 Parallel RGB LCD Interface

The Colibri modules feature one parallel RGB LCD interface as main display interface. As standard,
the Colibri modules feature the interface with 18-bit color depth. Some modules support color
depth of 16-bit or 24-bit. Unfortunately, the color mapping of these modes can be different
between the modules. Therefore, Toradex recommends using the interface in the 18-bit color
mode for the best compatibility between all Colibri modules. Dithering can help reducing the
visible color banding of gradients in lower color depth systems. Consider using 18-bit color
mapping with enabled dithering instead of 24-bit mapping. Carefully check which modules support
color dithering.

2.4.1 Parallel RGB LCD Signals

Colibri Colibri Power

I/O Type Description
Pin Signal Name Rail
52 LCD_1_18bit_R0 O CMOS 3.3V
54 LCD_1_18bit_R1 O CMOS 3.3V
66 LCD_1_18bit_R2 O CMOS 3.3V
Red LCD data signals (LSB: 0, MSB: 5)
64 LCD_1_18bit_R3 O CMOS 3.3V
57 LCD_1_18bit_R4 O CMOS 3.3V
61 LCD_1_18bit_R5 O CMOS 3.3V
80 LCD_1_18bit_G0 O CMOS 3.3V
46 LCD_1_18bit_G1 O CMOS 3.3V
62 LCD_1_18bit_G2 O CMOS 3.3V
Green LCD data signals (LSB: 0, MSB: 5)
48 LCD_1_18bit_G3 O CMOS 3.3V
74 LCD_1_18bit_G4 O CMOS 3.3V
50 LCD_1_18bit_G5 O CMOS 3.3V
76 LCD_1_18bit_B0 O CMOS 3.3V
70 LCD_1_18bit_B1 O CMOS 3.3V
60 LCD_1_18bit_B2 O CMOS 3.3V
Blue LCD data signals (LSB: 0, MSB: 5)
58 LCD_1_18bit_B3 O CMOS 3.3V
78 LCD_1_18bit_B4 O CMOS 3.3V
72 LCD_1_18bit_B5 O CMOS 3.3V
44 LCD_1_18bit_DE O CMOS 3.3V Data Enable (other names: Output Enable)
56 LCD_1_18bit_PCLK O CMOS 3.3V Pixel Clock (other names: Dot Clock, L_PCLK_WR)
68 LCD_1_18bit_HSYNC O CMOS 3.3V Horizontal Sync (other names: Line Clock, L_LCKL_A0)
82 LCD_1_18bit_VSYNC O CMOS 3.3V Vertical Sync (other names: Frame Clock, L_FCLK)

Table 7: Parallel RGB LCD Signals

2.4.2 Reference Schematics

2.4.2.1 18-bit Display Schematic Example

The parallel RGB interface can cause problems in passing the electromagnetic radiation tests when
used with high pixel clocks frequency. Especially if a display is connected over long flat flex cables.
The reduction of the radiation needs to be taken in account. Keep the flat flex cables as short as

Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected] Page | 14
 Colibri Carrier Board Design Guide

possible. Series resistors in the data lines reduce the slew rate of the signals which reduces the
radiation problem but can introduce signal quality and timing problems. The serial resistor value is
a trade-off between electromagnetic radiation reduction and signal quality. A good starting value
is 22Ω.

Figure 6: 18bit Parallel RGB Display Reference Schematic

2.4.2.2 VGA DAC Schematic Example

A few Colibri modules feature a dedicated VGA interface on an FFC connector. Nevertheless, it is
recommended adding a parallel RGB to VGA converter if a VGA interface is needed which is
compatible with all modules. Since only the 18-bit color depth is compatible between the different
modules, it is recommended to use this mode even if the DAC is capable of 24-bit.

Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected] Page | 15
 Colibri Carrier Board Design Guide

Figure 7: VGA DAC Reference Schematic

2.4.2.3 LVDS Transmitter Schematic Example

Since the electromagnetic radiation of the parallel RGB interface is not easy to handle, it is
recommended to attach liquid crystal displays with high resolutions by using an LVDS interface.
LVDS also reduces problems associated with long cables. The Colibri standard does not feature a
dedicated LVDS LCD interface. Nevertheless, a parallel RGB to LVDS transmitter can be placed on
the carrier board in order to get an LVDS interface.

Since there are different LVDS color mapping available, check with your display vendor how the
RGB signals need to be connected to the transmitter in order to be compatible.

Figure 8: LVDS Transmitter Reference Schematic

Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected] Page | 16
 Colibri Carrier Board Design Guide

18-bit Color Mapping

The color mapping for the 18-bit LVDS interface is standardized and is shown in the following
picture:
LVDS1_A_CLK+
LVDS1_B_CLK+

LVDS1_A_TX0+/-
LVDS1_B_TX0+/-
G0 R5 R4 R3 R2 R1 R0

LVDS1_A_TX1+/-
LVDS1_B_TX1+/-
B1 B0 G5 G4 G3 G2 G1

LVDS1_A_TX2+/-
LVDS1_B_TX2+/-
DE VSYNC HSYNC B5 B4 B3 B2

Previous Cycle Current Cycle Next Cycle

Figure 9: 18-bit LVDS Color Mapping

24-bit JEIDA Color Mapping

The JEIDA color mapping is compatible with the 18bit LVDS interface. Therefore, the mapping is
sometimes also called “24bit / 18bit Compatible Color Mapping”. The signal names of the color
bits are renamed (e.g. the 18bit R5 is renamed to 24bit R7) but the position of the MSB is kept the
same. The additional least significant bits R0, R1, G0, G1, B0 and B1 are located at the additional
fourth LVDS data pair.
LVDS1_A_CLK+
LVDS1_B_CLK+

LVDS1_A_TX0+/-
LVDS1_B_TX0+/-
G2 R7 R6 R5 R4 R3 R2

LVDS1_A_TX1+/-
LVDS1_B_TX1+/-
B3 B2 G7 G6 G5 G4 G3

LVDS1_A_TX2+/-
LVDS1_B_TX2+/-
DE VSYNC HSYNC B7 B6 B5 B4

LVDS1_A_TX3+/-
LVDS1_B_TX3+/-
N/A B1 B0 G1 G0 R1 R0

Previous Cycle Current Cycle Next Cycle

Figure 10: 24-bit JEIDA LVDS Color Mapping

24-bit VESA Color Mapping

Most of the 24bit LVDS displays follow the VESA Color mapping. The VESA color mapping does not
rename the signal bits. This means that the position of the MSB is changed since they are available
at the additional data pair. Therefore, the VESA color mapping is not compatible with the 18bit
interface.
LVDS1_A_CLK+
LVDS1_B_CLK+

LVDS1_A_TX0+/-
LVDS1_B_TX0+/-
G0 R5 R4 R3 R2 R1 R0

LVDS1_A_TX1+/-
LVDS1_B_TX1+/-
B1 B0 G5 G4 G3 G2 G1

LVDS1_A_TX2+/-
LVDS1_B_TX2+/-
DE VSYNC HSYNC B5 B4 B3 B2

LVDS1_A_TX3+/-
LVDS1_B_TX3+/-
N/A B7 B6 G7 G6 R7 R6

Previous Cycle Current Cycle Next Cycle

Figure 11: 24-bit VESA LVDS Color Mapping

2.4.3 Unused Parallel RGB Interface Signal Termination

All unused parallel RGB interface signals can be left unconnected.

Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected] Page | 17
 Colibri Carrier Board Design Guide

2.5 HDMI/DVI

The HDMI and DVI interface uses a TMDS compatible physical link to transfer video and optional
audio data. While electrically, HDMI and DVI are both similar, but there can be a few differences in
their protocols. HDMI is the successor of DVI and specifies the additional transport for audio data
and content protection (HDCP). As HDMI is backward compatible, HDMI devices (monitor,
television set etc.) work with DVI signals. Forward compatibility is not guaranteed. Not all DVI
displays accept the HDMI protocol or are HDCP compatible. Please read the datasheet of the
Colibri modules for more information about the provided HDMI and DVI protocols.

The HDMI and DVI interface define different connectors. There are passive adapters available in
both types. Please be advised that both HDMI and HDCP require to be licensed. The HDMI/DVI
signals are available on a dedicated FFC connector. Check carefully to confirm which modules
provide the interface.

2.5.1 HDMI/DVI Signals

Colibri Colibri Power

I/O Type Description
FFC Pin Signal Name Rail
2 HDMI_1_CLK_P O TDMS HDMI/DVI differential clock positive
3 HDMI_1_CLK_N O TDMS HDMI/DVI differential clock negative
5 HDMI_1_DATA0_P O TDMS HDMI/DVI differential data lane 0 positive
6 HDMI_1_DATA0_N O TDMS HDMI/DVI differential data lane 0 negative
8 HDMI_1_DATA1_P O TDMS HDMI/DVI differential data lane 1 positive
9 HDMI_1_DATA1_N O TDMS HDMI/DVI differential data lane 1 negative
11 HDMI_1_DATA2_P O TDMS HDMI/DVI differential data lane 2 positive
12 HDMI_1_DATA2_N O TDMS HDMI/DVI differential data lane 2 negative
14 HDMI_1_HPD I CMOS 3.3V Hot plug detect
16 HDMI_DDC_SDA I/O OD 3.3V I2C interface for reading the extended display identification data (EDID)
15 HDMI_DDC_SCL O OD 3.3V over DDC.

Table 8: HDMI/DVI Signals

2.5.2 Reference Schematics

2.5.2.1 DVI Schematic Example

There are different configurations of DVI connectors available. The DVI-D (digital) contains only the
native DVI signals The DVI-A (analogue) provides no DVI signals. Only the analogue VGA signals
are provided. The DVI-I (integrated) combines the digital DVI signals and the analogue VGA
signals. For the DVI-A and DVI-I, there are passive adapters available for the D-SUB VGA
connector. There is only one DDC channel available on the DVI-I interface. Therefore, the
connector is not designed to use both links (DVI and VGA) contemporaneously. Nevertheless, there
are Y-cables available which provides a DVI and VGA output contemporaneously. Such cables are
not standardized and provide normally the DDC only on the DVI or VGA output. Please be aware
of the DDC when using such a Y-cable.
The following schematic example shows a DVI-I implementation. It can also be used as an example
for a DVI-D design, just remove the analogue VGA signals. The sync signals for the VGA signals
need to be level shifted from 3.3V to 5V. The same is necessary for the DDC signals. The TDMS
signals need to be ESD protected by using diodes. The schematic example shows a discrete
solution for the level shifting and protection. There are also integrated solutions available.

Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected] Page | 18
 Colibri Carrier Board Design Guide

Figure 12: DVI-I Reference Schematic

2.5.2.2 HDMI Schematic Example

The HDMI connector does not feature an Analogue VGA interface, but there is an optional
Consumer Electronics Control (CEC) interface available on the connector. The location of the CEC
signal is not standardized on the Colibri modules. Check the datasheet of the modules for more
information to the position of the signal. The CEC is a single- wire interface that is used to control
consumer audio and video devices such as television set or AV receivers. There are many different
trade names for CEC (VIERA Link, Anynet+, EasyLink, Aquos Link, BRAVIA Link, etc.). The CEC is a
3.3V interface. Nevertheless, it is recommended to add level shifter from the internal 3.3V logic
level. This eliminates problems with displays that pull-up the signal to other voltage levels.

The I2C signals for the DDC and the hot plug detection (HPD) need to be shifted to/from the 5V
logic level of the HDMI to the Colibri level of 3.3V. The HPD has a 100kΩ pull down resistor
already on the baseboard

Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected] Page | 19
 Colibri Carrier Board Design Guide

X2 X1
1 TMDS_DATA2_P 1
GND DIFF90_50 TDMS_D 2P
2 TMDS_CLK_P TMDS_CLK_P 2
DIFF90_50 GND TDMS_D2 _Shield
3 TMDS_CLK_N TMDS_CLK_N TMDS_DATA2_N 3
TDMS_D2 N
4
GND
5 TMDS_DATA0_P DIFF90_50 TMDS_DATA0_P TMDS_DATA1_P 4
DIFF90_50 TDMS_D 1P
6 TMDS_DATA0_N TMDS_DATA0_N 5
GND TDMS_D1 _Shield
7 TMDS_DATA1_N 6
GND TDMS_D1 N
8 TMDS_DATA1_P DIFF90_50 TMDS_DATA1_P
9 TMDS_DATA1_N DIFF90_50 TMDS_DATA1_N TMDS_DATA0_P 7
TDMS_D 0P
10 8
GND GND TDMS_D0 _Shield
11 TMDS_DATA2_P DIFF90_50 TMDS_DATA2_P TMDS_DATA0_N 9
TDMS_D0 N
12 TMDS_DATA2_N DIFF90_50 TMDS_DATA2_N
13 TMDS_CLK_P 10
TDMS_C LKP
14 HOTPLUG_DETE CT_T 11
GND TDMS_C LK_Shield
15 DDC_SCL_T TMDS_CLK_N 12
TDMS_C LKN
16 DDC_SDA_T D1 D2

4
17 13
GND CEC
18 14
HEC
19
GND
20 HDMI_I2C_SCL 15
DDR_SCL

3
21 HDMI_I2C_SDA 16
GND DDR_SDA
22
23 SHIELD RC LAMP050 4S SHIELD RC LAMP050 4S 17 S1
GND
GND SH1
24 S2
SH2
5V_HDMI 18 S3
R1 PWR_ 5V_50 mA SH3
52435 -2471 HOTPLUG_DETECT HOTP LUG_DETECT 19 S4
HotPlug_ HECDP SH4
FFC Connector 1K
C1
D3 1002944 9-111RLF

4
220pF
SHIELD
50V
D4
5V_HDMI GND
5V 5V_HDMI

RC LAMP050 4S BAT54

3
R2
1.8K
L1 SHIELD HDMI_I2C_SCL
500 mA
220R @100MHz
C2
4.7pF
5V_HDMI 50V

R3 GND
1.8K
L2
HDMI_I2C_SDA
500 mA
220R @100MHz
C3
4.7pF
50V

GND

Figure 13: HDMI Reference Schematic

2.5.3 Unused HDMI/DVI Signal Termination

All unused HDMI/DVI signals can be left unconnected. The HPD has a 100kΩ pull down resistor on
the module.

Colibri Colibri
Recommended Termination
Pin Signal Name
2 HDMI_1_CLK_P Leave NC if not used
3 HDMI_1_CLK_N Leave NC if not used
5 HDMI_1_DATA0_P Leave NC if not used
6 HDMI_1_DATA0_N Leave NC if not used
8 HDMI_1_DATA1_P Leave NC if not used
9 HDMI_1_DATA1_N Leave NC if not used
11 HDMI_1_DATA2_P Leave NC if not used
12 HDMI_1_DATA2_N Leave NC if not used
14 HDMI_1_HPD Leave NC if not used, 100kΩ resistor on Colibri module
16 HDMI_DDC_SDA Add pull-up resistor or disable the I2C function in software
15 HDMI_DDC_SCL Add pull-up resistor or disable the I2C function in software

Table 9: Unused HDMI/DVI Signals Termination

Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected] Page | 20
 Colibri Carrier Board Design Guide

2.6 Analogue VGA

Some Colibri modules feature a dedicated VGA interface on the HDMI FFC connector. For systems
which need to be compatible with a wide range of Colibri modules, it is recommended to use a
parallel RGB to VGA DAC instead of the dedicated VGA interface.

2.6.1 VGA Signals

Colibri Colibri Power

I/O Type Description
FFC Pin Signal Name Rail
18 VGA_1_R O Analogue Analogue red video (0 to 0.7V)
20 VGA_1_G O Analogue Analogue green video (0 to 0.7V)
22 VGA_1_B O Analogue Analogue blue video (0 to 0.7V)
24 VGA_1_HSYNC O CMOS 3.3V Horizontal sync
23 VGA_1_VSYNC O CMOS 3.3V Vertical sync
3.3V/
16 HDMI_DDC_SDA I/O OD
5V tolerant I2C interface for reading the extended display identification data
3.3V/ (EDID) over DDC. Signal shared with the HDMI interface
15 HDMI_DDC_SCL O OD
5V tolerant

Table 10: VGA Signals

2.6.2 Reference Schematics

The horizontal and vertical sync signals need to be level shifted on the baseboard. The DDC signals
on the FFC connector do not require a level shifter since these signals are 5V tolerant. If a different
I2C interface is used as DDC, the shifters are needed. In the VGA connector standard, the carrier
board needs to provide 5V power supply for the EDID memory on the DDC. This allows the system
to read out the EDID information of an attached display even if it is not powered. Unfortunately,
some displays source the 5V internally and also provide internal pull-up resistors to the I2C lines.
This can cause back feeding problems. Therefore we recommend connecting the display and pull-
up resistor 5V supply over a diode to the module supply.

It is mandatory to place on every analogue RGB signal a 150Ω resistor to ground. Place this
resistor as close to the VGA connector as possible. Before this resistor, the signal trace can be
routed with 50Ω impedance. After the resistor, the signal should be routed with 75Ω impedance.
Depending on the layer stack up, 75Ω traces cannot be reached since the trace with is getting too
small. In this case, lower traces impedance (e.g. 50Ω) can be used but the trace length should be
kept short.

All signals on the VGA D-SUB connector need to be ESD protected. TSR diodes can be used. It is
recommended to add a PI-filter to the analogue RGB signals. The values for the capacitors and
inductors depend on the maximum required display resolution. The PI-filter reduces EMI problems,
but also limits the maximum bandwidth of the VGA signal.

Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected] Page | 21
 Colibri Carrier Board Design Guide

IC1
R4 L1
2 4 CRT_HSYNC
A Y 500 mA
33R 220R@100MHz
C12
5
5V VCC 47pF
C13
100nF 50V
16V 3 1
GND GND NC
GND
SN7 4LVC1G17
VGA Connector
IC2
R5 L2
2 4 CRT_VSYNC X24A
A Y 500 mA
33R 220R@100MHz
C14
5 CRT_RED 1
5V VCC 47pF 6
C15 6
100nF 50V
GND
16V 3 1 11 11 1
GND GND NC
FFC Connector GND CRT_GREEN 2 7
X6 SN7 4LVC1G17 7
24 CRT_HSYNC _T DDC_ DATA
GND
12
12 2
23 CRT_VSYNC _T C18 10pF CRT_BLUE 3 8
50V GND L3
22 CRT_BLUE_T CRT_BLUE 8 13 3
600 mA GND
21 R9 150R 40R@100MHz C19 50V CRT_HSYNC 13
GND GND 9
20 CRT_GREEN_T VGA_5V 4
10pF
19 C20 10pF R305 9 14 4
50V GND L4
18 CRT_RED_T CRT_GREEN CRT_VSYNC 120R 14 10
600 mA
17 R10 150R 40R@100MHz C21 50V 5
GND GND GND 15 5
16 DDC_DATA_T 10pF 10
GND
15 DDC_CLK_T C22 10pF DDC_CLK 15
GND L5
14 VGA_5V VGA_5V 50V CRT_RED
600 mA
13 R13 150R 40R@100MHz C23 50V
GND GND
12 R17 R19 10pF HDR15SN-H
11 1.8KR 1.8KR
L8
10 DDC_ DATA X24B HDR15SN-H
500 mA
9 220R @100MHz
8
500 mA
DDC_CLK SHIELD
7 L9
220R @100MHz C33 C3 2
6 SHIELD2
4.7p F 4.7pF
5 50V 50V
4 D2 D5 D1

4
RCLAMP0504S

RCLAMP0504S
3 GND GND SHIELD2 SHIELD2
5V VGA_5V
2
1 BAT54

FH1 2-24S-0.5SV(55) 6

3
GND SHIELD2
PLACE D1, D3, D4, D5 NEAR THE DVI-I CONNECTOR

Figure 14: VGA Reference Schematic

2.6.3 Unused VGA Interface Signal Termination

All unused VGA interface signals can be left unconnected.

2.7 Parallel Camera Interface

The Colibri module form factor features an 8 bit parallel camera interface as a standard interface.
Depending on the module, there are maybe additional bits available in the type specific area. Only
the 8 bit YUV and ITU-R BT.656 format mode is intent to keep compatible between Colibri
modules. Consult the Colibri datasheets in order to get more information about the additional
available input modes (e. g. Bayer, RGB etc.)

2.7.1 Parallel Camera Signals

Colibri Colibri Power

I/O Type Description
Pin Signal Name Rail
101 CAM_1_Y0/C0 I CMOS 3.3V
103 CAM_1_Y1/C1 I CMOS 3.3V
79 CAM_1_Y2/C2 I CMOS 3.3V
97 CAM_1_Y3/C3 I CMOS 3.3V
Video input pixel data
67 CAM_1_Y4/C4 I CMOS 3.3V
59 CAM_1_Y5/C5 I CMOS 3.3V
85 CAM_1_Y6/C6 I CMOS 3.3V
65 CAM_1_Y7/C7 I CMOS 3.3V
96 CAM_1_PCLK I CMOS 3.3V Video input pixel clock
81 CAM_1_VSYNC I CMOS 3.3V Video input vertical sync
94 CAM_1_HSYNC I CMOS 3.3V Video input horizontal sync
Master clock output for the camera. Some Camera might do not need
75 CAM_1_MCLK O CMOS 3.3V
this clock since they use other clock sources

Table 11: Parallel Camera Signals

Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected] Page | 22
 Colibri Carrier Board Design Guide

2.7.2 Unused Parallel Camera Interface Signal Termination

All unused parallel camera input signals can be left unconnected if the interface is disabled in
software. It depends on the module whether the signals can be used as GPIO when they are not
used as camera interface.

2.8 SD/MMC/SDIO

The Colibri module form factor features one SD/MMC interfaces as standard interface. The
interface provide up to 4 data bit which can be used for interfacing SD and MMC cards as well as
SDIO interface peripherals. Depending on the module, there might be additional data signals in
order to get an 8bit interface. This bit width is used by MMCplus cards and eMMC memory chips.
The additional data bits are not intent to be compatible between different Colibri modules.

The SD cards know different bus speed modes. The required signal voltage depends on the bus
speed mode. For example the SDR104 mode requires 1.8V signaling. In the Colibri module
definition, all GPIO capable interfaces including the SD/MMC/SDIO are defined for 3.3V. Some
Colibri modules might be capable to switch the voltages of the SD card interface pins to a 1.8V,
but it is not mandatory. Read the according datasheet of the Colibri module.

Even if the bus speed mode requires the signaling voltage of 1.8V, the supply of the card itself is
still 3.3V. Pay attention to the SD card signal pull-up resistors on the carrier board. If the 1.8V
mode should be supported by the carrier board, the voltage for the pull-up resistors also needs to
be switchable. Some Colibri modules might allow removing the pull-up resistors on the carrier
board and using the internal ones only. In this case, this is the preferred solution. Even if the
external pull-up resistors are not mandatory, we recommend adding not assembled pull-up
resistors to the 3.3V rail in order to be compatible with future modules.

Bus Speed Mode Max. Clock Frequency Max. Bus Speed Signal Voltage
Default Speed 25 MHz 12.5 MByte/s 3.3V
High Speed 50 MHz 25 MByte/s 3.3V
SDR12 25 MHz 12.5 MByte/s 1.8V
SDR25 50 MHz 25 MByte/s 1.8V
DDR50 50 MHz 50 MByte/s 1.8V
SDR50 100 MHz 50 MByte/s 1.8V
SDR104 208 MHz 104 MByte/s 1.8V

Table 12: SD Card Bus Speed Modes

2.8.1 SD/MMC/SDIO Signals

Colibri Colibri Power

I/O Type Description
Pin Signal Name Rail
192 SD_1_DATA0 I/O CMOS 3.3V
49 SD_1_DATA1 I/O CMOS 3.3V Data signals [3:0], used for SD, MMC and SDIO interfaces, add
51 SD_1_DATA2 I/O CMOS 3.3V external pull-up resistors

53 SD_1_DATA3 I/O CMOS 3.3V

190 SD_1_CMD I/O CMOS 3.3V Command signal, add external pull-up resistor
47 SD_1_CLK O CMOS 3.3V Clock output

Table 13: 4bit SD/MMC/SDIO Signals

Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected] Page | 23
 Colibri Carrier Board Design Guide

2.8.2 Reference Schematics

Even if the selected module does not require pull-up resistors on the data and command lines, it is
recommended to place such resistors in the customer design and just not assemble them. This
makes sure that the module is compatible with other Colibri modules. There is no dedicated card
detect signal available. Any free GPIO capable signal could be used, but we recommend using the
signal on Pin 43 (CTRL_WAKE_0) whenever possible. There is also no dedicated write protection
signal available on the standard Colibri pin-out. Any free GPIO capable signal can be used if the
write protection function is required.

2.8.2.1 SD Card Slot Reference Schematics

3.3V

R50 R51 R52 R53 R54

33K 68K 68K 68K 68K

X15A

X1K
SD/MMC Holder
43 SODIMM_43_S RA34D 22 R MM_CD MM_DAT_0 7
WAKEUP / MMC_CD DAT_0
47 SODIMM_47_S RA34B 22 R MM_CLK MM_DAT_1 8
PIN_47 / MMC_CLK DAT_1
49 SODIMM_49_S RA34A 22 R MM_DAT_1 MM_DAT_2 9 3.3 V_SD 3.3V
PIN_49 / MMC_DAT_1 DAT_2
51 SODIMM_51_S RA1D 22 R MM_DAT_2 MM_DAT_3 1
PIN_51 / MMC_DAT_2 DAT_3 L2 5
53 SODIMM_53_S RA1C 22 R MM_DAT_3 4
PIN_53 / MMC_DAT_3 VCC 2A
190 SODIMM_190_S RA32A 22 R MM_CMD MM_CMD 2 220R@100MHz
PIN_190 / MMC_CMD CMD C9 4 C9 5
192 SODIMM_192_S RA32B 22 R MM_DAT_0 MM_CLK 5
PIN_192 / MMC_DAT_0 CL K 10uF 100nF
6.3V 16 V
Colibri - MMC MM_CD 10
CD GND
3
11 6
WP GND
11 of 16 3.3V TP 6
GND
1473005 -1 M90- 03011-03YD
R60 X15B
10K S1
GND
S2
GND
S3 SHIELD
GND
C9 6 S4
10nF GND
25 V
M90- 03011-03YD
GND

Figure 15: SD Card Slot Reference Schematic

2.8.3 Unused SD/MMC/SDIO Interface Signal Termination

All unused SD interface signals can be left unconnected.

2.9 I2C

The Colibri module form factor features one general purpose I2C interface. Additional, some
Colibri modules feature a dedicated DDC interface on the HDMI FFC connector.

The I2C as well as the DDC interfaces do not feature any pull-up resistors on the module. It is
required to add pull-up resistors to the data and clock lines on the carrier board. The pull-up
resistor values are normally between 1kΩ and 10kΩ. A small pull-up resistor increases the power
consumption while a large resistor could lead to problems in the signal quality. The optimum size
of the resistor depends on the capacitive load on the I2C lines and the required bus speed. 4.7kΩ is
a suitable value for many applications.

2.9.1 I2C Signals

Colibri Colibri Power

I/O Type Description
Pin Signal Name Rail
General purpose I2C data signal,
194 I2C_1_SDA I/O OD 3.3V
pull-up resistor required on carrier board
General purpose I2C clock signal,
196 I2C_1_SCL O OD 3.3V
pull-up resistor required on carrier board

Table 14: I2C Signals

2.9.2 Real-Team Clock (RTC) recommendation

The RTC on the module is not designed for ultra-low power consumption. Therefore, a standard
lithium coin cell battery can drain faster than allowed for certain designs. If a rechargeable RTC
battery is not the solution, it is recommended to use an external ultra-low power RTC IC on the
carrier board instead. In this case, add the external RTC to the I2C interface of the module.

Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected] Page | 24
 Colibri Carrier Board Design Guide

3.3V

R48
470R

D8
D9
R49 BAT54

10R
BAT54

1
+
BAT1
HU2032- LF
3.3V

-
2
R45 R4 6 R47
4.7K 4.7K 100K IC7 GND
C90
7 1 27pF 50 V
OUT OSCI

2
OSC1
X1G 32.768 KHz

1
196 SODIMM_196_S RA32D 22R 6
PIN_196 / I2C_SCL SCL C91
194 SODIMM_194_S RA32C 22R 5 2 27pF 50 V
PIN_194 / I2C_SDA SDA OSCO

GND
Colibri - I2C
7 of 16 8
VCC
1473005 -1
C93 C9 2
100nF 22uF
16V 25 V
4
VSS
3
NF

M41T0M6 GND
Backup during Battery change: about 0.6 sec/uF

Figure 16: External RTC Reference Schematic

2.9.3 Unused I2C Signal Termination

All unused I2C can be left unconnected if the corresponding I2C port is switched off in software.
Otherwise, it is recommended to keep the pull-up resistors available. Unused I2C signals can be
configured to be GPIO.

2.10 UART

The Colibri module form factor features three UART interfaces. Even though the UART_A is
specified as full featured UART, some modules might not provide all the control signals. Please
read the corresponding datasheet of the module carefully. UART_A is the standard console output
interface for the Linux and Windows Embedded Compact operating system. It is desirable to keep
at least the RX and TX signals of this port accessible for system debugging.

UART_B features RTS and CTS signals for hardware flow control while UART_C do not feature any
flow control signals. Some modules might provide the additional flow control signals on non-
standard pins.

2.10.1 UART Signals

Colibri Colibri Power

I/O Type Description
Pin Signal Name Rail
33 UART_A_RX I CMOS 3.3V Received Data
35 UART_A_TX O CMOS 3.3V Transmitted Data
27 UART_A_RTS O CMOS 3.3V Request to Send
25 UART_A_CTS I CMOS 3.3V Clear to Send
23 UART_A_DTR O CMOS 3.3V Data Terminal Ready
29 UART_A_DSR I CMOS 3.3V Data Set Ready
37 UART_A_RI I CMOS 3.3V Ring Indicator
31 UART_A_DCD I CMOS 3.3V Data Carrier Detect
36 UART_B_RX I CMOS 3.3V Received Data
38 UART_B_TX O CMOS 3.3V Transmitted Data
34 UART_B_RTS O CMOS 3.3V Request to Send
32 UART_B_CTS I CMOS 3.3V Clear to Send
19 UART_C_RX I CMOS 3.3V Received Data
21 UART_C_TX O CMOS 3.3V Transmitted Data

Table 15: UART Signals

Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected] Page | 25
 Colibri Carrier Board Design Guide

2.10.2 Reference Schematics

2.10.2.1 Full Featured RS232 Reference Schematics

The RS232 interface can be classified as Data Terminal Equipment (DTE) or Data Communication
Equipment (DCE). This classification is inherited from the usage of the interface for modems. The
signal direction of these modes is different. Some Colibri modules might allow changing the mode,
and therefore, also the data direction, but this is not a mandatory requirement. According to the
Colibri specifications, the interface is intent to be used in the DTE configuration.

DTE Direction
Signal Name Usage DCE Direction
(Colibri standard)
UART_A_RXD Received Data Data from DCE to DTE Input Output
UART_A_TXD Transmitted Data Data from DTE to DCE Output Input
DTE request to DCE to be prepared to
UART_A_RTS Request to Send Output Input
receive data
UART_A_CTS Clear to Send DCE indicates ready to accept data Input Output
UART_A_DTR Data Terminal Ready DTE indicates presence to DCE Output Input
UART_A_DSR Data Set Ready DCE is ready to receive commands or data Input Output
DCE announce to have detected an incoming
UART_A_RI Ring Indicator Input Output
ring signal on the telephone line
DCE announce to be connected to the
UART_A_DCD Data Carrier Detect Input Output
telephone line

Table 16: RS232 Signal Modes

X1J IC7 A X28B

23 SODIMM_23_S RA2D 22 R UART1_DTR UARTA_RTS 14 9 UARTA_R S232_L_RTS
PIN_23 / UART_A_DT R T1IN T1OUT
25 SODIMM_25_S RA2C 22 R UART1_CTS UARTA_TXD 13 10 UARTA_R S232_L_TXD
PIN_25 / UART_A_CTS T2IN T2OUT
27 SODIMM_27_S RA2B 22 R UART1_RTS UARTA_DTR 12 11 UARTA_R S232_L_DTR UARTA_RS232_L_DCD
PIN_27 / UART_A_RTS T3IN T3OUT L1
29 SODIMM_29_S RA2A 22 R UART1_DSR UARTA_RS232_L_DSR
PIN_29 / UART_A _DSR L6
31 SODIMM_31_S RA3D 22 R UART1_DCD 20 UARTA_RS232_L_RXD
PIN_31 / UART_A _DCD R2 OUTB L2
33 SODIMM_33_S RA3C 22 R UART1_RXD UARTA_DCD 19 4 UARTA_R S232_L_DCD UARTA_RS232_L_RTS
PIN_33 / UART_A _RXD R1 OUT R1IN L7
35 SODIMM_35_S RA3B 22 R UART1_TXD UARTA_RI 18 5 UARTA_R S232_L_RI UARTA_RS232_L_TXD
PIN_35 / UART_A _TXD R2 OUT R2IN L3
37 SODIMM_37_S RA3A 22 R UART1_RI UARTA_DSR 17 6 UARTA_R S232_L_DSR UARTA_RS232_L_CTS
PIN_37 / UART_A_RI R3 OUT R3IN L8
UARTA_RXD 16 7 UARTA_R S232_L_RXD UARTA_RS232_L_DTR
R4 OUT R4IN L4
32 UARTA_CTS 15 8 UARTA_R S232_L_CTS UARTA_RS232_L_RI
PIN_32 / UART_B_CTS R5 OUT R5IN L9
34 3.3V IC7 B
PIN_34 / UART_B_RTS L5
36 26 25 22
PIN_36 / UART_B_R XD C44 VCC GND C45 3.3V FORC EOFF#
38 23
PIN_38 / UART_B_TXD 100nF C48 100nF 3.3V FORC EON
27 3 16V GND
16V V+ V-
19 GND 21
100nF 178-009-613R571
PIN_19 / UART_C_RXD 16V INVALID #
21 28 1
PIN_21 / UART_C_TXD C1+ C2+ C4 9
GND C51 SN65C3243D BR
100nF 100nF
Colibri - UART 16V 24
C1 - C2 -
2 16V

10 of 16 SN65C3243D BR
1473005 -1

Figure 17: RS232 Reference Schematic

2.10.2.2 RS422 Reference Schematics

The RS422 is a full-duplex serial interface with differential pair signals. This allows higher data
rates and longer distances as with the RS232. Since the RS422 has separate RX and TX signal pairs,
no additional control signals are required for changing the signal direction. This means, the RS422
requires only the RX and TX signals of the UART interface. Therefore, it is possible to use any of the
three standard UART interfaces of the Colibri standard.

The RS422 specification does not contain a connector. Therefore, there is no standard connector
for this interface available. The reference schematic below uses the 9 pin D-sub connector (DE-9).
Peripherals might have a different pin-out even if they use a DE-9 connector.
X1J
23
PIN_23 /UART_A _DTR
25
PIN_25 / UART_A _CTS
27 3.3V
PIN_27 / UART_A _RTS X55A
29 IC4
PIN_29 / UART_A _DSR
31 13
PIN_31 / UART_A _DCD VCC
33 14
PIN_33 / UART_A _RXD C4 1 VCC
35 12 UARTC_RS 422_RXD+
PIN_35 / UART_A _TXD 100nF Rx+ GND 1
37 16 V 1 6
PIN_37 / UART_A _RI NC
8
NC
R5 7 2
GND 120 R
32 7
PIN_32 / UART_B _CTS
34 RE# 3 11 UARTC_RS 422_RXD- 3
PIN_34 / UART_B _RTS GND nR E Rx-
36 UARTC_RS 422_TXD+ 8
PIN_36 / UART_B _RXD
38 DE 4 9 UARTC_RS 422_TXD+ UARTC_RS 422_RXD+ 4
PIN_38 / UART_B _TXD 3.3V DE Tx+
UARTC_RS 422_TXD- 9
19 SODIMM_19_S RA14B 22R UARTC_RX D 2 UARTC_RS 422_RXD- 5
PIN_19 / UART_C_RX D RO
21 SODIMM_21_S RA14A 22R UARTC_TX D 5
PIN_21 / UART_C_TX D DI
10 UARTC_RS 422_TXD-
Tx-
Colibri - UART 6
GND
7 1734351-1
GND
10 of 16
1473005 -1 GND ADM3491 ARZ

Figure 18: RS422 Reference Schematic

Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected] Page | 26
 Colibri Carrier Board Design Guide

2.10.2.3 RS485 Reference Schematics

The RS485 interface is a half-duplex serial interface with differential pair signals. Instead of two
differential pair wires (RS422), only one pair is used for transmitting and receiving the data. The
bus allows multi point connections. Since the transceiver needs to be set either in the transmitting
or receiving mode, an additional control signal is required. It is recommended to use the RTS signal
of the corresponding UART interface. The RTS signal is only available on the UART_A and UART_B
as Colibri standard interface. The schematic below inverts the RTS signal for the data enable input
of the transceiver. Some modules allow inverting the signal in software, but it is recommended to
use the inverter circuit shown below in order to maintain compatibility with different modules and
drivers provided by Toradex. For some applications, it is desirable that the UART controller does
not see the TX message on its RX pins (echo of the sent message). In this case, the receive enable
pin (RE#) can be driven as well with the RTS signal. This turns off the RX output buffer while
sending a message.
Like the RS422, the RS485 specification also does not describe a standard connector. The reference
schematic below uses a DE-9 connector which may have a different pin-out as some peripheral
devices.
X1J 3.3V X55A
23 IC4 3.3V
PIN_23 / UART_A_DTR
25 13
PIN_25 / U ART_A_CTS VCC
27 14
PIN_27 / UART_A _RTS C41 VCC GND 1
29
100nF
12 R58 6
PIN_29 / UART_A _DSR Rx+ 680 R
31 16 V 1 2
PIN_31 / UART_A _DCD
33 8
NC NA
PIN_33 / UART_A _RXD NC
7
GND
PIN_35 / UART_A _TXD
35 UARTB _RS485_D+ 3
37 RE# 3 11 8
PIN_37 / UART_A _RI nRE Rx- R57
120R 4
32 DE 4 9 UARTB _RS485_D- 9
PIN_32 / UART_B _CTS DE Tx+
34 R1 2 22R 5
PIN_34 / UART_B _RTS
36 R1 0 22R UARTB _RXD 2
PIN_36 / UART_B _RXD RO
38 R11 22R UARTB _TXD 5 R60
PIN_38 / UART_B _TXD DI 680 R
10
19 6
Tx- NA 1734351-1
PIN_19 / UART_C_RXD GND
21 7 GND
PIN_21 / UART_C_TXD GND
IC2
2 R20 GND ADM3491ARZ
Colibri - UART 3.3V
A Y
4
0R
10 of 16 5 NA R2 1
Assemble R20 and remove R21
1473005 -1 VCC
100 K
ECHO disabled (the sender does
3 1 not get an echo of the sent message )
GND NC
GND
SN74 LVC1 G04DC KR
GND

Figure 19: RS485 Reference Schematic

2.10.2.4 IrDA Reference Schematics

IrDA is an optical wireless communication interface. There are different physical layer modulation
schemes available. Make sure which modes are supported by the specific Colibri module and the
peripheral devices. For compatibility reasons, it is recommended to use UART_C for the IrDA
implementation. Some modules only feature the IrDA function on this UART instance.
X1J X30
23 UARTC_TXD 3
PIN_23 / UART_A_DTR TXD
25 UARTC_RXD 4
PIN_25 / UART_A_CTS RXD
27
PIN_27 / UART_A_RTS
29 R6 6 22R UARTC_IRDA_LED 1 LED_A
PIN_29 / UART_A_DSR 3.3V_SW
31 2 LED_K
PIN_31 / UART_A_DCD
33 7
PIN_33 / UART_A_RXD NC
35 R67
PIN_35 / UART_A_TXD R6 8 0R
37 UARTC_IRDA_VCC 6
PIN_37 / UART_A_RI 3.3V_SW VCC
+

C57 C62
4.7R 100n F 4.7uF
32 16V 10V 8
PIN_32 / UART_B_CTS GND GND
R6 9
34 UARTC_IRDA_SD 5
PIN_34 / UART_B_RTS GND SD
36 100K
PIN_36 / UART_B_RXD TFDU4101
38
PIN_38 / UART_B_TXD
IrDA Transceiver
19 R10 22R
PIN_19 / UART_C_RXD
21 R11 22R
PIN_21 / UART_C_TXD

Colibri - UART
10 of 16
147300 5-1

Figure 20: IrDA Reference Schematic

2.10.3 Unused UART Signal Termination

Unused UART interface signals can be left unconnected. For debugging purpose, it is
recommended to have at least the UART1_RXD and UART1_TXD signals available.

Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected] Page | 27
 Colibri Carrier Board Design Guide

2.11 SPI

The serial peripheral interface (SPI) bus is a synchronous, full duplex interface. The Colibri module
form factor features one SPI interface. The interface has a chip select signal as compatible
standard. Some module may feature additional chip select signal or additional SPI interfaces as
secondary function of other pins.

The clock polarity and phase of the SPI bus is not standardized. Some peripherals are latching the
data on the positive edge of the clock while others are latching it at the negative edge. The SPI
modes describe these different behaviors. Make sure that the according Colibri module and the
peripheral device can be set to the same SPI mode.

SPI Mode Clock Clock Description

Polarity Phase
0 0 0 Clock is positive polarity and the data is latched on the positive edge of SCK
1 0 1 Clock is positive polarity and the data is latched on the negative edge of SCK
2 1 0 Clock is negative polarity and the data is latched on the positive edge of SCK
4 1 1 Clock is negative polarity and the data is latched on the negative edge of SCK

Table 17: SPI Modes

2.11.1 SPI Signals

The SPI bus consists of one master and one or many slaves. In the Colibri standard, the module is
the SPI master. Some modules might allow to be used also as SPI slaves. Some modules may
provide this function on different, non-standard pins.

Colibri Colibri Power

I/O Type Description
Pin Signal Name Rail
92 SPI_1_MOSI O CMOS 3.3V Master Output, Slave Input
90 SPI_1_MISO I CMOS 3.3V Master Input, Slave Output
86 SPI_1_CS0 O CMOS 3.3V Slave Select
88 SPI_1_CLK O CMOS 3.3V Serial Clock

Table 18: SPI Signals

2.11.2 Unused SPI Signal Termination

Unused SPI signals can be left unconnected.

2.12 CAN

The Colibri form factor does not provide a controller area network (CAN) bus as a standard
interface. Some modules feature dedicated CAN interface signals. For the other modules, it is
recommended to add an SPI to CAN controller on the carrier board for providing a CAN interface.
This section describes how to add a CAN controller to the SPI interface. If you intent to use the
dedicated CAN interface signals, please read the datasheet of the Colibri module.

2.12.1 Reference Schematics

Besides a controller, the CAN interface requires a transceiver on the carrier board. Normally, the
CAN interface needs to be galvanically isolated from the Colibri computer module. There are
transceivers with integrated signal isolation coupler and isolated DC/DC converters available (for
example the Analog Devices ADM3053). The other solution is to use separate components for the
transceiver, signal coupler and DC/DC converter. There are different type of connectors used for
the CAN interface. The reference schematic below uses a DE-9 connector. Since this is not an
official standard, some devices might have a different pin-out.

Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected] Page | 28
 Colibri Carrier Board Design Guide

5V IC10 CAN_5 V_ISO

8 12
C104 C105 VCC VISOOUT C106 C107
10uF 100nF 100nF 10uF
10V 16V 9 11 16V 10V
GND1_3 GND2_2

3.3V 3.3V GND CAN_ GND_I SO X32A

X1D R90 R91 3.3V CAN_5 V_ISO CAN_5 V_ISO

120R 120R
RESET_EXT#
26 NA U1
6 19 R100 CAN_PGND
RESET_OUT #
87
VIO VISOIN
U6
LED17 LED16 C109 C108 C110 C111 0R
3.3V CAN_L
100nF 10nF 10nF 100nF U2
BATT_ FAULT#
24
RED GREEN
16V 25V 3
GND1_2 GND2_1
20 25V 16 V CAN_H U7
22 IC18 1 13 R99
VDD_ FAULT# 100nF GND1_1 GND2_4 U3
20 3 GND 7 16 CAN_ GND_I SO 100 R
GND VDD CL KOUT/SOF GND1_4 GND2_3
U8
Colibri - Reset C159 16V 10
GND1_5 U4
RESET_OUT # 19 6 R101 CAN_PW
nRESET NC U9
4 of 16 CAN_INT# 13 15 0R
U5
1473005 -1
nINT NC NA
4 1 CAN_TX 5 CAN_ GND_I SO
nTX0RTS TX CAN TX D
X1F 5 15
nTX1RTS CANL 178- 009- 613R571
73 SODIMM_73 RA30C 22 R CAN_INT# 7 CAN 17
PIN_73 / CAN_INT# nTX2RTS CANH
86 SODIMM_86 RA9C 22 R SSP_FRM 12 2 CAN_RX 4 CAN Connector
PIN_86 / SSPFRM nRX0BF RXCAN RXD
88 SODIMM_88 RA9D 22 R SSP_SCLK 11 14 R107 R108
PIN_88 / SSPSCLK nRX1BF VREF R10 6 56R 56R
90 SODIMM_90 RA11A 22 R SSP_RXD 2 18
PIN_90 / SSPRXD NC RS
92 SODIMM_92 RA11B 22 R SSP_TXD SSP_SCLK 14 9 OSC3 0R
PIN_92 / SSPTXD SCK OSC1
SSP_TXD 16 8 1 2 ADM3053BRWZ
SI OSC2
CAN_GND_I SO 47nF
Colibri - SSP/CAN SSP_FRM 18
nCS C162 C163 C112
SSP_RXD 17 10 16.0 MHz
SO VSS 22pF 22pF 16 V
6 of 16 50V 50V
1473005 -1 MCP2515 T-I/ST GND CAN_ GND_I SO
GND GND

Figure 21: CAN Reference Schematic

2.13 PWM

The Colibri module form factor defines four general purpose pulse width modulator (PWM)
outputs. Please note that two of the four PWM signals are located on pins that are also used for the
standard parallel camera interface. These PWM outputs can only be used if the according camera
pins are not in use. The maximum output frequency and the available duty cycle steps can also
vary between the different Colibri modules.

2.13.1 PWM Signals

Colibri Colibri Power

I/O Type Description
Pin Signal Name Rail
59 PWM_A O CMOS 3.3V General purpose PWM output, pin also used for camera interface
28 PWM_B O CMOS 3.3V General purpose PWM output
30 PWM_C O CMOS 3.3V General purpose PWM output
67 PWM_D O CMOS 3.3V General purpose PWM output, pin also used for camera interface

Table 19: PWM Signals

2.13.2 Reference Schematics

The PWM output signals can be used for example to drive, motors, LEDs, robotic servos or fans. It is
possible to get an analogue signal with a simple low-pass filter. A very common usage is driving of
the backlight of liquid crystal displays.
3.3V

R124
120 R
3.3 V
LED3
GREEN

120 R
6

2 T5A
SI-1024-X LED4
R128 GREEN
100 K
1

X1E
3

59 GND GND T5B

SODIMM_59 RA29D 22R PWM_A 5
PIN_59 / PW M_A SI-1024-X
28 SODIMM_28 RA33A 22R PWM_B R131
PIN_28 / PW M_B
4

30 SODIMM_30 R98 10K PWM_C 3 100 K

PIN_30 / PW M_C
67 SODIMM_67 R99 10K PWM_D 2
PIN_67
1 GND GND
C154 C155
Colibri - PWM 330nF 330nF
16 V 16 V X2
5 of 16 GND
1473005 -1 GND GND

Figure 22: PWM Example Schematic

2.13.3 Unused PWM Signal Termination

Unused PWM signals can be left unconnected.

Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected] Page | 29
 Colibri Carrier Board Design Guide

2.14 Analogue Audio

2.14.1 Analogue Audio Signals

If only single channel (mono) line input or headphone output is required, it is recommended to use
the left channel.

Colibri Colibri Power

I/O Type Description
Pin Signal Name Rail
1 ANALOG_AUDIO_MIC_IN I Analogue 3.3V Microphone input
3 ANALOG_AUDIO_MIC_GND Analogue Microphone pseudo-ground
5 ANALOG_AUDIO_LINEIN_L I Analogue 3.3V Left line input
7 ANALOG_AUDIO_LINEIN_R I Analogue 3.3V Right line input
Headphone left output (can also be used as line
15 ANALOG_AUDIO_HEADPHONE_L O Analogue 3.3V
left output)
Headphone right output (can also be used as line
17 ANALOG_AUDIO_HEADPHONE_R O Analogue 3.3V
right output)
Headphone pseudo-ground (do not connect to
13 ANALOG_AUDIO_HEADPHONE_GND Analogue
ground!)

Table 20: Analogue Audio Signals

2.14.2 Reference Schematics

Depending on the module, the headphone output signals can have a DC offset. A common
solution is adding series capacitors to the headphone signal lines. If the headphone output signals
are used only as line output signals, 1µF series capacitors are sufficient. If the signals are used for
driving headphones, larger capacitors (47µF and more) are recommended. Some Colibri modules
provide a virtual headphone ground that can be used instead of the series capacitors in order to
reduce the BOM cost. Please note this solution only works if the attached device is isolated from
the module ground. For example, this works perfectly for headphones, but does not work for an
audio amplifier that uses the same ground as the module.

The line-in and microphone signals do not require serial capacitors since they are already placed
on the module. Some microphones (e.g. the widely used electret microphones) require a phantom
power. The reference schematic below shows a suitable solution for common electret microphone
capsules. Please note that some microphones require providing the phantom power on the middle
ring of the 3.5mm jack while others need to be powered over the tip of the 3.5mm jack which is
also used for the audio signals. The Colibri modules features a special analog ground for the
microphone. This is basically a switched ground. Using this ground instead of the regular analog
ground allows switching off the phantom power when the microphone is not in use.

Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected] Page | 30
 Colibri Carrier Board Design Guide

AUDIO[0..6] Top Jack

X1H X26C
1 MIC_IN LINEIN_L 35
PIN_1 / MIC_IN
3 MIC_GND 34
PIN_3 / MIC_GND
33
5 LINEIN_L LINEIN_R 32
PIN_5 / LINEIN_L
7 LINEIN_R 1
PIN_7
_ / LINEIN_R
C1 C2
13 HEADPHONE_GND
15pF 15pF
50V
LINE IN - Blue
50V
PIN_13 / HEADPHONE_GND C8
15 HEADPHONE_L MIC_G ND 3 of 3
PIN_15 / HEADPHONE_L
17 HEADPHONE_R PJ3X01RF0 4B-H
PIN_1 7 / HEADPHONE_R TP1 15pF
HEADPHONE_GND 50V
GND
Colibri -Audio TP2
AUDIO_AGND

Middle Jack
8 of 16 47uF X26B
147300 5-1 HEADPHONE_L C4 + 6.3V HEADPHONE_AC_L 25
24
23
Audio VCC Circuit 47uF
AUD IO_AVCC HEADPHONE_R C5 + 6.3V HEADPHONE_AC_R 22
5V IC6 1
C6 C7
1 5
Vin Vout 15pF
50V
15pF
50V
HEADP. OUT - Green
C8 9 C8 8 C8
2.2uF 3.3V
3
2.2uF
2 of 3
E L24 15pF 50V
6.3V 4 2 6.3V PJ3X01RF0 4B-H
N/C GND 2A
220R @100MHz
NC P511SN33T 1G GND AUDIO_AGND
GND AUD IO_AGND GND
Bottom Jack
X26A
AUD IO_ AVCC AUD IO_AGND MIC_I N 5
X1A R1 4
10 9 AUDIO _AVCC 2.2K 3
VDD _ANALOG PIN_9 / VSS_AUDIO R3
12 11 2
VDD _ANALOG PIN_11 / VSS_AUDIO
3.3V R2 2.2K 1
C9 100R
39
GND 15pF MIC IN - Pink
40 41 50V
VCC_BATT GND
42 83 2 of 3
3V3 GND

+
84 109 C10 Place close to PJ3X01RF0 4B-H
3V3 GND 47uF
108 147 6.3V Microphone Connector X26D
3V3 GND
182 181 S1
3V3 GND C11 SHIELD
148 197 S2
3V3 GND SHIELD
198
3V3 GND
199 15pF SHIELD
S3 SHIELD
200 50V S4
3V3 SHIELD
GND GND AUDIO_AGND
JA3333L -D11P-4F

Colibri - Power Supply

1 of 16
147300 5-1

Figure 23: Analogue Audio Reference Schematic

AUDIO[0..6] Top Jack
X1H X26C
1 MIC_IN LINEIN_L 35
PIN_1 / MIC_IN
3 MIC_GND 34
PIN_3 / MIC_GND
33
5 LINEIN_L LINEIN_R 32
PIN_5 / LINEIN_L
7 LINEIN_R 1
PIN_7 / LINEIN_R C1 C2

13 HEADPHONE_GND
_
15pF 15pF LINE IN - Blue
50V 50V
PIN_13 / HEADPHONE_GND
15 HEADPHONE_L 3 of 3
PIN_15 / HEADPHONE_L
17 HEADPHONE_R PJ3X01RF0 4B-H
PIN_17 / HEADPHONE_R C3
15pF
AUD IO_AGND
Colibri -Audio 50V
Middle Jack
8 of 16 GND X26B
147300 5-1 HEADPHONE_L 25
24
Audio VCC Circuit
AUDIO_AVCC 23
5V IC6 HEADPHONE_R 22
1 5 1
Vin Vout C6 C7
C8 9 3 C88
15pF 15pF HEADP. OUT - Green
2.2uF 3.3V 2.2uF 50V 50V
E L24
6.3V 4 2 6.3V
2A
HEADPHONE_GND 2 of 3
N/C GND
220R @100MHz Virtual ground (voltag e offset) PJ3X01RF0 4B-H
C8
NC P511SN33T 1G Do not connect to normal ground! 15pF
GND AUD IO_AGND GND 50V
Bottom Jack
AUDIO_AVCC AUDIO_AGND GND X26A
X1A MIC_IN 5
10 9 4
VDD _ANALOG PIN_9 / VSS_AUD IO
12 11 AUD IO_AVCC R1 2.2K 3
VDD _ANALOG PIN_11 / VSS_AUD IO
3.3V 2
39 R2 R3 2.2K 1
GND C9 100R
40 41
VCC _BATT GND 15pF MIC IN - Pink
42 83 50V
3V3 GND
84 109 2 of 3
3V3 GND
+

108 147 C10 PJ3X01RF0 4B-H

3V3 GND 47uF
182
3V3 GND
181 6.3V Place close to
148 197 Microphone Connector X26D
3V3 GND
198 199 MIC_GND S1
3V3 GND SHIELD
200 Switched ground S2
3V3 SHIELD
GND C11
15pF SHIELD
S3 SHIELD
50V S4
SHIELD
Colibri - Power Supply
JA3333L -D11P-4F
1 of 16 GND
147300 5-1

Figure 24: Analogue Audio Reference Schematic (using virtual and switched grounds)

2.14.3 Unused Analogue Audio Signal Termination

The unused analogue audio signals can be left unconnected. Please note, even if the analogue
audio interface is not used at all, the analogue 3.3V power pins of the module (pin 10 and 12) still
needs to be powered. Alternatively, the analogue power can be connected to the digital 3.3V
power rail.

Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected] Page | 31
 Colibri Carrier Board Design Guide

2.15 Touch Panel Interface

The Colibri module standard features a touch panel interface for resistive touch screens. This
allows integrating touch screen solution with a minimum amount of components on the carrier
board. This standard supports four-wire resistive touch screens. Some modules also support five-
wire touch. Read the corresponding datasheet of the module for more information.

2.15.1 Resistive Touch Signals

Colibri Colibri Power

I/O Type Description
Pin Signal Name Rail
14 TOUCH_4-wire_PX I/O Analogue 3.3V X+ (4-wire)
16 TOUCH_4-wire_MX I/O Analogue 3.3V X- (4-wire)
18 TOUCH_4-wire_PY I/O Analogue 3.3V Y+ (4-wire)
20 TOUCH_4-wire_MY I/O Analogue 3.3V Y- (4-wire)

Table 21: Digital Audio Signals

2.15.2 Reference Schematics

In order to reduce the noise that is picked up by the display or long cables, it is recommended to
add capacitor to the touch screen signals. 1nF to 10nF is a good choice. It is also recommended to
add clamping diodes in order to protect the input of the touch screen controller against ESD.
X16
X1I 6
14 AN1_TSPX AN1_TSPX 5
PIN_14 / TOUCH_TSPX
16 AN1_TSMX AN1_TSPY 4
PIN_16 / TOUCH_TSMX
18 AN1_TSPY AN1_TSMX 3
PIN_18 / TOUCH_TSPY
20 AN1_TSMY AN1_TSMY 2
PIN_20 / TOUCH_TSMY
1
C100 C101 C102 C103
Colibri -Touch D8
1nF 1nF 1nF 1nF
TSW-103- 07- G-D
50V 50V 50V 50V
2.54mm Male
9 of 16 4 3
147300 5-1
5 2 GND
GND

6 1

RCLAMP050 4S

Figure 25: Touch Interface Reference Schematic

2.15.3 Unused Touch Panel Interface Signal Termination

Unused touch panel signals can be left unconnected or pull down the signals individually with
10kΩ resistors. It is recommended to disable the corresponding drivers.

Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected] Page | 32
 Colibri Carrier Board Design Guide

2.16 Analogue Inputs

The Colibri modules feature up to four analogue input channels. The supported sampling rates and
resolution are dependent on the modules. The input voltage range for most modules is from 0V to
3.3V. Please check the according datasheet for the input voltage range. The ADC reference is the
analogue input voltage rail. The analogue input channels are not designed to be used for high
precision measurement tasks. The interface can be used for battery voltage monitoring (additional
circuit required), ambient light sensors, or simple analogue joystick input devices.

2.16.1 Analogue Input Signals

Colibri Colibri Power

I/O Type Description
Pin Signal Name Rail
8 Analogue Input <0> I Analogue 3.3V ADC input (3.3V max)
6 Analogue Input <1> I Analogue 3.3V ADC input (3.3V max)
4 Analogue Input <2> I Analogue 3.3V ADC input (3.3V max)
ADC input (3.3V max), some modules might use this input for
2 Analogue Input <3> I Analogue 3.3V
the five wire resistive touch interface.

Table 22: Analogue Input Signals

2.16.2 Unused Analogue Inputs Signal Termination

The unused analogue input signals can be left unconnected or tied to the ground. It is
recommended to disable the corresponding inputs in the driver or disable the whole ADC block if
not used.

2.17 Parallel Memory Bus (External Memory Bus)

The Colibri form factor reserves several module edge pins as parallel memory bus. This bus can be
used for interfacing high-speed peripherals like FPGAs, DSPs, Ethernet controllers, CAN
controllers, etc. The supported data and address width as well as some control signal are
dependent on the module. Some modules do not even provide a compatible parallel bus on the
dedicated signal pins. Carefully check the datasheets of the modules for more information about
the supported modes. Additionally, the Pinout Designer tool can be a useful source of information.
This tool allows comparing the different bus modes and data/address widths. Special care has to
be taken if a carrier board is designed for PXA270: Since the Colibri PXA270 uses the parallel
memory bus also internally, it is not allowed to use the pins for anything else than for this
dedicated function. Proper glue logic is needed or the pins need to be left unconnected.

2.17.1 Memory Bus Signals

Colibri Colibri Power

I/O Type Description
Pin Signal Name Rail
111 BUS_A00 O CMOS 3.3V
113 BUS_A01 O CMOS 3.3V
115 BUS_A02 O CMOS 3.3V
117 BUS_A03 O CMOS 3.3V
119 BUS_A04 O CMOS 3.3V
121 BUS_A05 O CMOS 3.3V Address signals. The actual available number of address signals
123 BUS_A06 O CMOS 3.3V varies from module.

125 BUS_A07 O CMOS 3.3V

110 BUS_A08 O CMOS 3.3V
112 BUS_A09 O CMOS 3.3V
114 BUS_A10 O CMOS 3.3V
116 BUS_A11 O CMOS 3.3V

Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected] Page | 33
 Colibri Carrier Board Design Guide

Colibri Colibri Power

I/O Type Description
Pin Signal Name Rail
118 BUS_A12 O CMOS 3.3V
120 BUS_A13 O CMOS 3.3V
122 BUS_A14 O CMOS 3.3V
124 BUS_A15 O CMOS 3.3V
188 BUS_A16 O CMOS 3.3V
186 BUS_A17 O CMOS 3.3V
184 BUS_A18 O CMOS 3.3V
146 BUS_A19 O CMOS 3.3V
144 BUS_A20 O CMOS 3.3V
142 BUS_A21 O CMOS 3.3V
140 BUS_A22 O CMOS 3.3V
138 BUS_A23 O CMOS 3.3V
136 BUS_A24 O CMOS 3.3V
134 BUS_A25 O CMOS 3.3V
149 BUS_D00 I/O CMOS 3.3V
151 BUS_D01 I/O CMOS 3.3V
153 BUS_D02 I/O CMOS 3.3V
155 BUS_D03 I/O CMOS 3.3V
157 BUS_D04 I/O CMOS 3.3V
159 BUS_D05 I/O CMOS 3.3V
161 BUS_D06 I/O CMOS 3.3V
163 BUS_D07 I/O CMOS 3.3V
165 BUS_D08 I/O CMOS 3.3V
167 BUS_D09 I/O CMOS 3.3V
169 BUS_D10 I/O CMOS 3.3V
171 BUS_D11 I/O CMOS 3.3V
173 BUS_D12 I/O CMOS 3.3V
175 BUS_D13 I/O CMOS 3.3V
177 BUS_D14 I/O CMOS 3.3V
179 BUS_D15 I/O CMOS 3.3V Data signals. The actual available data bits vary from modules.
150 BUS_D16 I/O CMOS 3.3V The major part of modules only supports 16 bit data.

152 BUS_D17 I/O CMOS 3.3V

154 BUS_D18 I/O CMOS 3.3V
156 BUS_D19 I/O CMOS 3.3V
158 BUS_D20 I/O CMOS 3.3V
160 BUS_D21 I/O CMOS 3.3V
162 BUS_D22 I/O CMOS 3.3V
164 BUS_D23 I/O CMOS 3.3V
166 BUS_D24 I/O CMOS 3.3V
168 BUS_D25 I/O CMOS 3.3V
170 BUS_D26 I/O CMOS 3.3V
172 BUS_D27 I/O CMOS 3.3V
174 BUS_D28 I/O CMOS 3.3V
176 BUS_D29 I/O CMOS 3.3V
178 BUS_D30 I/O CMOS 3.3V
180 BUS_D31 I/O CMOS 3.3V
126 BUS_DQM0 O CMOS 3.3V Byte Enable Mask, corresponds to D[7:0]
128 BUS_DQM1 O CMOS 3.3V Byte Enable Mask, corresponds to D[15:8]

Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected] Page | 34
 Colibri Carrier Board Design Guide

Colibri Colibri Power

I/O Type Description
Pin Signal Name Rail
130 BUS_DQM2 O CMOS 3.3V Byte Enable Mask, corresponds to D[23:16]
132 BUS_DQM3 O CMOS 3.3V Byte Enable Mask, corresponds to D[31:24]
105 BUS_nCS0 O CMOS 3.3V
Chip select signals, all required chip select signals should be
107 BUS_nCS1 O CMOS 3.3V
pulled up on the carrier board.
106 BUS_nCS2 O CMOS 3.3V
91 BUS_nOE O CMOS 3.3V Output Enable
99 BUS_nPWE O CMOS 3.3V Buffered Write Enable
89 BUS_nWE O CMOS 3.3V Write Enable
93 BUS_RDnWR O CMOS 3.3V Buffered Write Enable
95 BUS_RDY I CMOS 3.3V Ready/Busy/Wait signal

Table 23: Memory Bus Signals

2.17.2 Unused Memory Bus Signals Termination

All unused memory bus signals can be left unconnected. On the Colibri PXA270, the memory bus
interface is also used on the module for connecting the RAM, flash and Ethernet controller.
Therefore, the bus signal pins cannot be used for any other purpose on this module. On other
modules, it might be possible to use the unused bus signals as GPIO or for other alternative
functions.

2.18 GPIO

Many of the interface pins can also be used as general purpose input output pin (GPIO) for
alternative function. Theoretically, any unused interface pin that serves GPIO function can be used.
Since some interface pins do not provide GPIO functionality on certain Colibri modules, there is a
list of preferred GPIO pins. For compatibility reason, we recommend using the first pin on this list.
Please note that there might be additional restrictions in using the GPIO functions on certain
modules. For example, two pins share the same GPIO instance and therefore cannot be used
independently of each other on some modules. More information can be found in the datasheet of
the module.

2.18.1 Preferred GPIO Signals

Colibri Power
I/O Type Description
Pin Rail
19, 21, 23, 25, 27, 28, 29, 30, 31, 32, 33, 34, 35,
36, 37, 38, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52,
53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65,
66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 78, 79, I/O CMOS 3.3V General purpose GPIO
80, 81, 82, 85, 86, 88, 90, 92, 95, 97, 98, 99, 100,
101, 102, 103, 104, 105, 106, 107, 127, 129, 131,
133, 135, 137, 190, 192, 194, 196

Table 24: Dedicated GPIO Signals

2.18.2 Unused GPIO Termination

The GPIO signals do not need to be terminated if they are not in use.

Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected] Page | 35
 Colibri Carrier Board Design Guide

3 Power Management

3.1 Power Signals

3.1.1 Digital Supply Signals

Colibri Colibri Power

I/O Type Description
Pin Signal Name Rail
42, 84,108, 148,182,198, 200 VCC I PWR 3.3V Main power supply input for the module
39, 41, 83, 109,147, 181, 197,
GND I PWR Common signal and power ground
199
RTC supply, connect this pin to 3.3V even if
40 VCC_BACKUP I PWR 3.3V
the internal RTC is not used

Table 25: Digital Supply Signals

3.1.2 Analogue Supply Signals

Colibri Colibri Power

I/O Type Description
Pin Signal Name Rail
Power supply for the analogue part of the
10, 12 AVDD_AUDIO I PWR 3.3V
module
9, 11 VSS_AUDIO I PWR Ground for the analogue part of the module

Table 26: Analogue Supply Signals

The analogue power supply is used on the module for the analogue circuits. 3.3 Volt need to be
provided to this input even if the analogue part is not used in a design. In this case, the pins can
be connected to the main power input of the module. For a better audio quality, it is
recommended to add separate filters to the analogue power supply rail. For the best quality, a
separate power supply with linear voltage regulator is recommended.

3.1.3 Power Management Signals

Colibri Colibri Power

I/O Type Description
Pin Signal Name Rail
nRESET_EXT
26 I CMOS 3.3V Active low reset input
(CTRL_RESET_MICO)
nRESET_OUT
87 O CMOS 3.3V Active low reset output
(CTRL_RESET_MOCi)
Active low main module wake input signal, needs a pull-up
43 CTRL_WAKE_0 I CMOS 3.3V
resistor on the baseboard if wake function is used
22 nVDD_FAULT I Analog Only available on PXA270, can be left unconnected
22 nGPIO_RESET I CMOS 3.3V Only available on PXA3xx, can be left unconnected
24 nBATT_SENSE I Analog Only available on PXA270 and PXA3xx, can be left unconnected

Table 27: Power Management Signals

In order to make the direction of the power management signals clear, the ending MICO or MOCI
are added. MICO is the abbreviation for “Module Input, Carrier board Output” while MOCI stands
for “Module Output, Carrier board Input”

Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected] Page | 36
 Colibri Carrier Board Design Guide

3.2 Power Block Diagram

Module
7-24 V 7-24V 3.3V
VCC

input 3.3V
Jack Buck
Enable

VCC_BACKUP
RTC
RTC
Battery

5V
5V
Buck
Enable
AVDD_AUDIO
3.3V Analog
Filter
Circuit
For better quality use
dedicated LDO from 5V rail

CTRL_WAKE_0

Power Management
Peripheral
Devices on
Carrier Board

nRESET_OUT

nRESET_EXT

Figure 26: Power Block Diagram

If the internal RTC of the module is not used or the analog audio and resistive touch interface is
not required, the carrier board power supply can be further simplified. It is important that even if
RTC and/or the analog interfaces are not used, its corresponding supply rails need to be served by
the carrier board.

Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected] Page | 37
 Colibri Carrier Board Design Guide

Module
7-24 V 7-24V 3.3V
VCC

input 3.3V
Jack Buck
Enable

VCC_BACKUP
RTC

5V
5V
Buck
Enable
AVDD_AUDIO
Analog
Circuit

CTRL_WAKE_0

Power Management
Peripheral
Devices on
Carrier Board

nRESET_OUT

nRESET_EXT

Figure 27: Power Block Diagram (without RTC an analog interfaces)

Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected] Page | 38
 Colibri Carrier Board Design Guide

3.3 Power States

The Colibri module and carrier board has different power states. The table below describes the
behavior during different states and which power rails and peripherals are active. These are just
the standard power states. If additional power saving is necessary, it is possible to introduce other
states in which some of the carrier board peripherals are switched off. In this case, free GPIO can
be used to switch off unused peripheral power rails.

Abbr. Name Description Module Carrier Board

UPG Unplugged No power is applied to the No main VCC and AVDD_AUDIO No power supply input, RTC
system, except the RTC battery applied, maybe VCC_BACKUP battery maybe inserted
might be available available
SUS Suspend System is suspended and waits CPU is suspended, wakeup Power rails are available on
for wakeup sources to trigger capable peripherals are running carrier board, peripherals might
while others might be switched be stopped by software
off
RUN Running System is running All power rails are available, CPU All power rails are available,
and peripherals are running peripherals are running
RST Reset System is put in reset state by All power rails are available, CPU All power rails are available,
holding nRESET low and peripherals are in reset state peripherals are in reset state

Table 28: Available Colibri Power States

The figure shown below shows a sequence diagram of the different power states. The module
automatically goes into the running mode when the main power rail is applied to the module. In
the running mode, the system can be set to be suspended by the software. There might be
different wake up sources available. Read the datasheet of the corresponding module for more
information about the available wakeup events. All Colibri modules have it in common that the
CTRL_WAKE_0 wakes up the module if the signal level goes low. If compatibility between the
modules is needed, use this pin as the general wake signal.

Unlike the Apalis module family, the Colibri modules do not provide a shutdown state in which the
module can switch off the carrier board peripheral supplies. The Colibri module does not have a
dedicated signal for turning off the peripheral supplies. Nevertheless, some modules can be shut
down (depending on the used operating system). In the standard carrier board architecture, all
power rails will remain on.
Remove VCC
from Module

Apply VCC Suspend request

to Module

UPG RUN SUS

Remove VCC Wake event

from Module
Figure 28: Power State Diagram

3.4 Power-Up Sequence

The Colibri module starts booting as soon as the main voltage rail is applied to the module. It is
important that the main input voltage rises monotonically. The RTC rail (VCC_BACKUP) needs to be
applied before or together with the main voltage. It is not allowed to apply the analogue voltage
supply before applying the main voltage.

Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected] Page | 39
 Colibri Carrier Board Design Guide

The peripheral power rails on the carrier board needs to be ramped-up in a correct sequence. The
sequence starts normally with the highest voltage (e.g. 5V) followed by the lower voltages (e.g.
3.3V then 1.5V and so on). Peripherals normally require that a lower voltage rails is never present
if a higher rail is missing. Check the datasheet of all peripheral components on the carrier board
for a proper sequencing.

State UPG UPG -> RUN RUN

VCC_BACKUP

7-27V Carrier Board in

VCC input for Module

Normal Power up (UPG -> RUN)

>0ms
AVDD_AUDIO for Module

Perpherals Rails on CB

Module internal Rails

Module internal Reset

>0ms

nRESET_OUT

nRESET_EXT

CTRL_WAKE_0

Figure 29: Power-Up Sequence

3.5 Reference Schematics

Place enough power supply bypass capacitors to the voltage inputs of the peripheral devices (see
Toradex Layout Design Guide). Place a bypass capacitor to each power input pin of the Colibri
module. Be wary of the total capacity on a voltage rail when switching the voltage. If the rails are
switched on too fast, the current peaks for charging all the bypass capacitors can be very high. This
can produce unacceptable disturbances or can trigger an overcurrent protection circuit. Maybe the
switching speed needs to be limited. The following figure shows a simple voltage rail switch circuit.
C1 and R1 limit the switching speed. The values need to be optimized according to the
requirements. It is recommended to place a bypass capacitor (C2) close to the switching transistor.

+V3.3
2 3 +V3.3_SWITCHED
R2 C2 C1 T1
100K 100nF 10nF 1 IRLML6401
16V 16V
GND R1
47K
6
ENABLE_V3.3_SWITCHED T2
2 SI1016CX
1
GND

Figure 30: Simple Voltage Switch Circuit

The carrier board needs to provide the 3.3V main voltage for the module as well as all voltage rails
for the peripheral devices. Check the maximum current consumption of the Colibri modules that

Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected] Page | 40
 Colibri Carrier Board Design Guide

are intent to be used with the carrier board. Currently, the Colibri T30 is the module with the
highest current consumption. This module can draw up to 1.2A. In order to leave enough margins,
take 2A into the power budget for the Colibri T30 module. Do not forget taking the additional
current consumption of the peripheral devices on the 3.3V rail into the budget.

In order to satisfy the in-rush current during start-up of a Colibri module we recommend using
bulk capacitors of about 450µF in total on the main 3.3V power supply.

The nRESET_EXT and nRESET_OUT do not need any pull-up resistors on the carrier board since
these resistors are already placed on the module. The CTRL_WAKE_0 requires a pull-up resistor on
the carrier board if the wake function is implemented.
X2
2 L1 36R @100MHz
GND_IN 10 A GND
3
1 L2
PW R_IN 10 A 12V_FILT_UNREG
36R @ 100MHz
RAPC722X C1 5 C1 4
10uF 10uF
Power IN 50 V 50V

GND
12 V_FILT_UNREG

12V_FILT_UNREG 9 VREG5 6
EN5
21 12 8 5
VREG5 EN VO T2B C1 C2
VREG5 10 100m A nom . C65 FDS6982AS
EN3 10uF 10uF
200m A max.! R34 10uF 14 R4 1 4 50V 50V
4.7R 10V DR VH
V5FILT 4.7 R
GND 6 13 3 GND GND 3.3V
VFB VBST
32 20 C7 8
GND GND V5FILT V5FI LT 100nF L2 1 4.7u H
C6 7 15 16 V
1uF R42
LL
16 V 100 K 8 6.2A
11 7
PGOOD T2A
R36 0R 31 GND FDS6982AS NA
GND TONSEL

+
19 16 2 C3 C4 C5
VREG3 VREG3 DR VL 150uF 150uF 150uF
12V_FILT_UNREG 100m A nom . C6 10V 10 V 10 V
22 200m A max.! 10uF 7 1
VIN 6.3V COMP
C7 18
10uF CS
50V GND R43 R44 24m R
Place sense resistor close to TPS
5 10K pin 17 and input capacitors
GND
4 17
VREF2 VREF2 C87 PGND
33 C7 4
HS 1nF 1nF
R157
50V 50V V5FILT
TPS51120 IC5A TP S5112 0 IC5C 3.3K
GND GND GND GND NA GND

VREG5 12 V_FILT_UNREG
SW2 6
1 3 29 1 5
GND EN VO C8 C9
T1B
2 4 FDS6982AS
10uF 10uF
TD -03XB 27 R3 3 4 50V 50V
DR VH
Reset Button V5FILT 4.7 R
3 28 3 GND GND 5V
VFB VBST
X1D C6 6
100nF L2 0
26 RESET_MICO# 26 16 V 8.2u H
R35
RESET_EXT# LL
87 RESET_MOCI# 100 K 8 6.25 A
RESET_OUT#
30 7
PGOOD T1A FDS6982AS
24
BATT_ FAULT#

+
+

22 25 2 C10 C11 C12

VDD_ FAULT# DR VL 150uF 150uF 150uF
10V 10 V 10 V
Colibri - Reset 2
COMP
1 NA
23
CS
4 of 16 R38 R37 15mR
1473005 -1 6.2K Place sense resistor close to TPS
pin 24 and input capacitors
C75 24
2.7nF PGND R156
50V
V5FILT
3.6K
GND TP S5112 0 IC5B GND NA GND
Audio VCC Circuit AUDIO_AVCC
5V IC6
1 5
Vin Vout
RESET_MOCI#
C89 3
C8 8 RESET_MOCI# Reset for peripherals
2.2uF 3.3V E 2.2uF L2 4
6.3V 4 2 6.3V
N/C GND 2A
220R@ 100MHz
NC P511SN33T1G
GND AUDIO_AGND GND

Place bead close to pin 9/11 on Colibri SODIMM Connector

Module Power Supply

AUDIO_AVCC AUDI O_AGND
3.3V D14 X1A
10 9
VDD_ ANALOG PIN_9/ VSS_AUDIO
12 11
C93 VDD_ ANALOG PIN_11/VSS_AUDIO
BAT54
100nF
D9 16V 39
R4 9 GND
VCC_INTRTC 40 41
VCC_ BATT GND
10 R 42 83
C7 1 3V3 GND
BAT54 84 109
1

100nF 3V3 GND

GND
+

16V 108 147

3V3 GND
182 181
GND 3V3 GND
BAT1 3.3 V 148 197
3V3 GND
HU2032-LF 198 199
-

Place close to SODIMM pins 3V3 GND

2

200
3V3
GND
+

C79 C80 C81 C82 C94 C95

22uF 4.7uF 4.7uF 4.7uF 100nF 100nF
GND 10V 10V 10 V 10V 16V 16V Colibri - Power Supply
1 of 16
GND 1473005 -1

Figure 31: Simple Power Supply Reference Schematic

Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected] Page | 41
 Colibri Carrier Board Design Guide

4 Mechanical and Thermal Consideration

4.1 Module Connector

The Colibri modules fit into a regular 2.5V (DDR1) SO-DIMM200 memory socket. Please note there
are two version of 200pin SO-DIMM connector available. The Colibri module is only compatible
with the variant that is designed for DDR1 modules with 2.5V. The 1.8V DDR2 variant has a
different notch position and is therefore not compatible.

There are many suitable connectors from different manufacturers available in different stacking
height. A selection of SO-DIMM200 socket manufacturers is listed below:

CONCRAFT: http://www.concraft.com.tw/connector_products_ddr.html
Morethanall Co Ltd.: http://www.morethanall.com
Tyco Electronics (AMP): http://www.te.com
NEXUS COMPONENTS GmbH: http://www.nexus-de.com
FCI http://www.fci.com

4.2 Fixation of the Module

The SO-DIMM connector features a locking mechanism which is reliable for many applications. In
order to ensure the proper connection of a module at high vibration and/or shock situations,
additional fixation might be required. The Colibri module offers different solutions for the fixation.

Figure 32: Colibri Fastener

Toradex offers Colibri Fastener for an easy to install fixation. Two fasteners are required for
holding the module. The fastener support SO-DIMM connector height of 5.2mm only. If a
connector with a different height is used, another fixation solution is required. Please note,
inserting the Colibri module is critical, if done wrong the Colibri can be damaged due mechanical
stress! More information including a module inserting guide can be found here:
http://developer.toradex.com/products/colibri-fastener

Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected] Page | 42
 Colibri Carrier Board Design Guide

Figure 33: Colibri Module with Fastener

Instead of using the holes on the module for the fastener, it can also be used for fixing the module
with screws. Select a suitable spacer which matches the SO-DIMM connector stacking height. The
holes in the module have a diameter of 2.0mm. Therefore, M1.5, M1.6, or M1.8 screws can be
used. Please note the maximum allowed head and washer diameter is 6mm.
67.6

63.6

D2.0 D1.2
3.5
27.0

36.7
6.0

Figure 34: Location of Mounting Holes

The third option is to solder down the module. The modules feature a half open through-hole
solder pad. These holes can be used for soldering the module down with solder pins. Please note
the solder pads are connected to the ground plane of the module. Some of the older modules
might do not feature the pads. Please contact the Toradex support team for more information.

Figure 35: Thru-Hole Solder Pads for Fixation

Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected] Page | 43
 Colibri Carrier Board Design Guide

4.3 Thermal Solution

The Colibri modules are designed to be used without additional heat spreader or heat sink. Most
of the Colibri modules feature thermal throttling mechanism. The module measures the current
temperature of the SoC. If it reaches a critical limit, it starts throttling down the CPU speed or shuts
the system completely down in order to prevent damages. Please read the corresponding
datasheets for more information to the thermal behavior.

 If you only use the peak performance for a short time period, heat dissipation is less of a
problem because most of the module will reduce the power consumption when full
performance is not required.
 A lower die temperature will also lower the power consumption due to smaller leakage
currents.
 If you need the full CPU/Graphics performance over a long period of time, make sure that
you are able to dissipate sufficient thermal energy to the environment.

In general, more effectively the generated thermal energy is transported to the environment, the
better performance you get out of the computer module. Therefore, it might be necessary to add a
thermal solution. The best solution is to glue a suitable heat sink directly to the top of the SoC.
Since the module PCB is only 1mm thick, the board is not very stiff. Appling force to the SoC can
bend PCB which destroys the module. Therefore, pay attention when mounting a thermal solution
on the module that the module is not cracked due to bending stress.

4.4 Module Size

67.6

63.6 max.2.2
max.3.0

D2.0

bottom side (facing the carrier board)

R2
.0
27.0

36.7
20.0

1.0
6.0

4.0

Pin 1 Pin 39 Pin 199 Pin 2 Pin 1

15.35 1.0

Figure 36: Module Dimensions Top Side (dimensions in mm)

Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected] Page | 44
 Colibri Carrier Board Design Guide

5 Appendix A – Physical Pin Definition and Location

The following table contains the information about the standard functions on the module edge
connector pins. Not all modules feature the complete set of standard function. Please read
carefully the function lists in the datasheet of the modules. The Toradex Pinout Designer can be a
useful tool for checking the availability of functions on certain modules. It helps configuring the pin
muxing. More information and download link can be found here:
http://developer.toradex.com/carrier-board-design/pinout-designer-tool

Module Bottom Side SO-DIMM Pin Module Top Side

Analogue Input <3> 2 1 Audio Analogue Microphone Input
Analogue Input <2> 4 3 Audio Analogue Microphone GND
Analogue Input <1> 6 5 Audio Analogue Line-In Left
Analogue Input <0> 8 7 Audio Analogue Line-In Right
Audio_Analogue VDD 10 9 Audio_Analogue GND
Audio_Analogue VDD 12 11 Audio_Analogue GND
Resistive Touch PX 14 13 Audio Analogue Headphone GND
Resistive Touch MX 16 15 Audio Analogue Headphone Left
Resistive Touch PY 18 17 Audio Analogue Headphone Right
Resistive Touch MY 20 19 UART_C RXD
VDD Fault Detect 22 21 UART_C TXD
Battery Fault Detect 24 23 UART_A DTR
nReset In 26 25 UART_A CTS, Keypad_In<0>
PWM<B> 28 27 UART_A RTS
PWM<C> 30 29 UART_A DSR
UART_B CTS 32 31 UART_A DCD
UART_B RTS 34 33 UART_A RXD
UART_B RXD 36 35 UART_A TXD
UART_B TXD 38 37 UART_A RI, Keypad_In<4>
VCC_BATT 40 39 GND

3V3 42 41 GND
LCD RGB DE 44 43 WAKEUP Source<0>, SDCard CardDetect
LCD RGB Data<7> 46 45 WAKEUP Source<1>
LCD RGB Data<9> 48 47 SDCard CLK
LCD RGB Data<11> 50 49 SDCard DAT<1>
LCD RGB Data<12> 52 51 SDCard DAT<2>
LCD RGB Data<13> 54 53 SDCard DAT<3>
LCD RGB PCLK 56 55 PS2 SDA1
LCD RGB Data<3> 58 57 LCD RGB Data<16>
LCD RGB Data<2> 60 59 PWM<A>, Camera Input Data<7>
LCD RGB Data<8> 62 61 LCD RGB Data<17>
LCD RGB Data<15> 64 63 PS2 SCL1
LCD RGB Data<14> 66 65 Camera Input Data<9>, Keypad_Out<3>, PS2 SDA2
LCD RGB HSYNC 68 67 PWM<D>, Camera Input Data<6>
LCD RGB Data<1> 70 69 PS2 SCL2
LCD RGB Data<5> 72 71 Camera Input Data<0>, LCD Back-Light GPIO
LCD RGB Data<10> 74 73
LCD RGB Data<0> 76 75 Camera Input MCLK
LCD RGB Data<4> 78 77
LCD RGB Data<6> 80 79 Camera Input Data<4>
LCD RGB VSYNC 82 81 Camera Input VSYNC
3V3 84 83 GND
SPI CS 86 85 Camera Input Data<8>, Keypad_Out<4>
SPI CLK 88 87 nReset Out
SPI RXD 90 89 nWE
SPI TXD 92 91 nOE

Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected] Page | 45
 Colibri Carrier Board Design Guide

Camera Input HSYNC 94 93 RDnWR

Camera Input PCLK 96 95 RDY
Camera Input Data<1> 98 97 Camera Input Data<5>
Keypad_Out<1> 100 99 nPWE
102 101 Camera Input Data<2>
104 103 Camera Input Data<3>
nCS2 106 105 nCS0
3V3 108 107 nCS1
ADDRESS8 110 109 GND
ADDRESS9 112 111 ADDRESS0
ADDRESS10 114 113 ADDRESS1
ADDRESS11 116 115 ADDRESS2
ADDRESS12 118 117 ADDRESS3
ADDRESS13 120 119 ADDRESS4
ADDRESS14 122 121 ADDRESS5
ADDRESS15 124 123 ADDRESS6
DQM0 126 125 ADDRESS7
DQM1 128 127
DQM2 130 129 USB Host Power Enable
DQM3 132 131 USB Host Over-Current Detect
ADDRESS25 134 133
ADDRESS24 136 135 SPDIF_IN
ADDRESS23 138 137 USB Client Cable Detect, SPDIF_OUT
ADDRESS22 140 139 USB Host DP
ADDRESS21 142 141 USB Host DM
ADDRESS20 144 143 USB Client DP
ADDRESS19 146 145 USB Client DM
3V3 148 147 GND
DATA16 150 149 DATA0
DATA17 152 151 DATA1
DATA18 154 153 DATA2
DATA19 156 155 DATA3
DATA20 158 157 DATA4
DATA21 160 159 DATA5
DATA22 162 161 DATA6
DATA23 164 163 DATA7
DATA24 166 165 DATA8
DATA25 168 167 DATA9
DATA26 170 169 DATA10
DATA27 172 171 DATA11
DATA28 174 173 DATA12
DATA29 176 175 DATA13
DATA30 178 177 DATA14
DATA31 180 179 DATA15
3V3 182 181 GND
ADDRESS18 184 183 Ethernet Link/Activity Status
ADDRESS17 186 185 Ethernet Speed Status
ADDRESS16 188 187 Ethernet TXO-
SDCard CMD 190 189 Ethernet TXO+
SDCard DAT<0> 192 191 Ethernet GND
I2C SDA 194 193 Ethernet RXI-
I2C SCL 196 195 Ethernet RXI+
3V3 198 197 GND
3V3 200 199 GND

Table 29: Physical Pin Definition and Location

Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected] Page | 46
 Colibri Carrier Board Design Guide

DISCLAIMER:
Copyright © Toradex AG. All rights reserved. All data is for information purposes only and not
guaranteed for legal purposes. Information has been carefully checked and is believed to be
accurate; however, no responsibility is assumed for inaccuracies.
Brand and product names are trademarks or registered trademarks of their respective owners.
Specifications are subject to change without notice.

Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected] Page | 47