THE THREE ERAS OF SCALING
In the semiconductor industry, transistor scaling is a technique used to make transistor smaller
and more efficient, leading to faster and more powerful electronic devices. The three eras of
transistor scaling are the Geometrical Scaling (1975-2002), Equivalent Scaling (2003-2004) and
3D Power Scaling (2025-2040). Geometrical scaling which characterised the 70s, 80s and 90s
was aimed at the reduction of the horizontal and vertical physical dimensions in conjunction
with improved performance of planar transistors. However, major upcoming materials were
identified by the NTRS (The National Technology Roadmap for Semiconductors) between 1994
and 1997 and a proposal to extend the NTRS was made to the WSC (World Semiconductor
Council) due to which the ITRS (International Technology Roadmap for Semiconductors) was
formed and the research activities necessary to completely restructure the MOS transistor and
the necessary methodology were approved and launched worldwide.
This new approach to restructuring the transistor was named “equivalent scaling”. The goal of
this program consisted of reducing the historical time of ~25 years between major transistor
innovations to less than half in order to save the semiconductor industry from reaching a major
crisis. Strained silicon, high-κ/metal gate, FinFET, and use of other semiconductor materials
(e.g., germanium) represented the main features of this scaling approach. By 2011 all these new
process modules were successfully introduced into high volume manufacturing. Because of this
environmental change system integrators finally regained full control of the business model. No
longer was a faster microprocessor triggering the design of a new PC but on the contrary the
design of a new smart phone generated the requirements for new ICs and other related
components.
Under these conditions it became clear in 2012 that the ITRS needed to adapt and morph to the
new ecosystem, which was going to take some time. During the preparation of the 2013 ITRS it
was also assessed that horizontal (2D) features were going to be approaching the range of a few
nanometers shortly beyond 2020 which made it clear that the semiconductor industry was
going to be running out of horizontal space by then, which is shown in Fig 1 on the next page.
The major question was which products were going to reach these 2D limits first. In addition,
the rapid increase in the number of transistors (i.e., 2×/2-years) and the comparably rapid
increase in operating frequency throughout the 80s and 90s drove the power dissipation of
microprocessors way beyond the 100 W by the 2003−2005 timeframe. This implied that number
of transistors and frequency could no longer simultaneously increase.
The solution to this problem first came from companies producing Flash memories. In fact,
multiple companies announced in 2014 that future products were going to fully utilize the
vertical dimension, as shown in Fig 2 on the next page. Under these conditions the electronics
industry decided to convert to a multicore architecture and continued to increase the number of
transistors at historical rate but limited the operating frequency to few gigahertz. All the above
considerations indicated that the structure of integrated circuits needed to evolve from 2D to
3D structures and transistor design needed to be aimed at reduced power consumption as
opposed to be optimized for maximum operating frequency. For these reasons, the third scaling
method which aimed at transition to complete vertical device structures was named “3D Power
Scaling” by the IRDS to symbolically include in a very succinct way all the challenges facing the
semiconductor and electronics industries in the next 15 years.
Fig 1 2D Scaling Reaching Fundamental limits beyond 2020
Fig 2 Flash Memory aggressively adopts 3 D scaling in 2014
