09-01-2023
Programmable Peripheral Interface
8255
It is an I/O port chip used for interfacing
I/O devices with microprocessor system.
It is device used to implement parallel
data transfer between processor and slow
peripheral devices like ADC, DAC,
keyboard, 7-segment display, LCD etc.
8255 Architecture
1
09-01-2023
Programmable Peripheral Interface
8255
8255A has three ports
PORT A
PORT B
PORT C
Port A and Port B are 8 bit parallel ports
Port C can be split into two parts
PORT C lower (PC0-PC3)
PORT C upper (PC7-PC4)
Programmable Peripheral Interface
8255
These three ports are further divided into
two groups
Group A includes PORT A and upper PORT C
Group B includes PORT B and lower PORT C
These two groups can be programmed in
three different modes
2
09-01-2023
Pin Diagram
Functions of Pins
Data bus(D0-D7):These are 8-bit bi-directional buses,
connected to 8086 data bus for transferring data
CS: This is Active Low signal. It stands for Chip Select. A
LOW on this input selects the chip and enables the
communication between the 8255 and the CPU
Read: This is Active Low signal, when it is Low the
microprocessor reads data from a selected I/O port of
8255
Write: This is Active Low signal, when it is Low the
microprocessor writes data into a selected I/O port
3
09-01-2023
Functions of Pins
Address (A0-A1):This is used to select the
ports.
A1 A0 Select
0 0 Port A
0 1 Port B
1 0 Port C
Control
1 1
Register
Functions of Pins
RESET: This is used to reset the device. That
means clear control registers
PA0-PA7:It is the 8-bit bi-directional I/O pins
used to send the data to peripheral or to
receive the data from peripheral
PB0-PB7:Similar to PA
PC0-PC7:This is also 8-bit bidirectional I/O pins.
These lines are divided into two groups
PC0 to PC3 (Lower Groups)
PC4 to PC7 (Higher groups)
4
09-01-2023
Data Bus Buffer
It is a 8-bit bidirectional Data bus
Used to interface between 8255 data bus
with system bus
The internal data bus and Outer pins D0-
D7 pins are connected in internally
The direction of data buffer is decided by
Read/Control Logic
Read/Write Control Logic
This is getting the input signals from
control bus and Address bus
Control signals are RD and WR
Address signals are A0,A1,and CS
8255 operation is enabled or disabled by
CS
5
09-01-2023
Read Operation
Write Operation
Group A and Group B Control
Group A and B get the Control Signal from CPU
and send the command to the individual control
blocks
Group A send the control signal to port A and
Port C (Upper) PC7-PC4
Group B send the control signal to port B and
Port C (Lower) PC3-PC0
6
09-01-2023
Group A and Group B Control
PORT A
This is a 8-bit buffered I/O latch.
It can be programmed by mode 0, mode 1, mode 2
PORT B
This is a 8-bit buffer I/O latch.
It can be programmed by mode 0 and mode
1
PORT C
It can be programmed by bit set/reset
operation
Operation Modes in 8255
Two operating modes
I/O mode (mode 0, mode 1, mode2)
Bit Set/Reset mode
7
09-01-2023
Input/ Output Mode
Three operating modes
Mode-0 (simple I/O port)
Mode-1 (Handshake I/O port)
Mode-2 (Bidirectional I/O port)
Mode 0 (Simple I/O)
In this mode, Port A and B is used as two 8-bit ports and
Port C as two 4-bit ports
Each port can be programmed in either input mode or
output mode
Ports in mode 0 is used to interfaces LEDs, Hexa keypad
and 7 segment LEDS to the processor
8
09-01-2023
Mode 1 (I/O with Handshake)
In this mode, Port A and B is used as 8-bit I/O ports
They can be configured as either input or output ports
Each port uses three lines from port C as handshake
signals
Handshaking signals control the i/p or o/p action of the
specified port
Mode 1 (Input Handshake)
Input device gives STB signal ( active low ) to 8255 before sending data. If
8255 already has some data, then it doesn’t allow the Input device to send
data.
8255 accepts data and stores it in the input buffer register. As soon as it
receives the data, it gives an IBF signal ( input buffer is full ) . If IBF = 1, it
does not allow any other data to enter 8255 PPI.
Now 8255 has data that should be sent to 8086. It makes INTR high, which
means it is interrupting the processor.
Whenever the processor is free, it services this INTR. Then the Processor
sends an RD ( active low ) signal and makes data transfer via data bus.
As soon as the RD signal is given , INTR gets low.
9
09-01-2023
Mode 1 (Output Handshake)
8255 sends an interrupt whenever it is ready to accept data from the
processor
Whenever 8086 needs to send a signal (condition provided INTR is active),
then 8086 sends WR ( active low ) signal
If 8255 has already some data in it, then INTR will be low, and 8086 will
not be able to send data to 8255 PPI
As 8255 receives data it resets OBF (output buffer is full (it is active low
signal ))
Then the Output device acknowledges the received input
Mode 2 (Bidirectional I/O)
In this mode, Port A can be configured as the
bidirectional port and Port B either in Mode 0 or Mode 1
Port A uses five signals from Port C as handshake signals
for data transfer
The remaining three signals from Port C can be used
either as simple I/O or as handshake for Port B
10
09-01-2023
Bit Set/Reset Mode
This mode is used to set or reset the bits of the
Port-C only
For BSR mode always D7 will be 0
Control Words
Two control words
I/O mode set control word (MSW)
Bit set/reset control word (BSR)
MSW is used to specify I/O functions
BSR is used to set/reset individual pins of
Port C
Both the control words are written in the
same control register
11
09-01-2023
Command Word
12
09-01-2023
13
09-01-2023
MOV AL, 83H
OUT CWR, AL
IN AL, PORTB
OUT PORTA, AL
IN AL, PORTC
AND AL, 0FH
MOV CL, 04H
ROL AL, CL
OUT PORTC, AL
HLT
14
