STP10NK70ZFP

STP10NK70Z
N-CHANNEL 700V - 0.75Ω - 8.6A - TO220-TO220FP
Zener-Protected SuperMESH™ MOSFET

General features Package

Type VDSS RDS(on) ID Pw

STP10NK70Z 700 V <0.85 Ω 8.6 A 110 W

STP10NK70ZFP 700 V <0.85 Ω 8.6 A 35 W

■ EXTREMELY HIGH dv/dt CAPABILITY

3 3
2 2
■ IMPROVED ESD CAPABILITY 1 1

■ 100% AVALANCHE TESTED TO-220 TO-220FP

■ GATE CHARGE MINIMIZED
■ VERY LOW INTRINSIC CAPACITANCES
■ VERY GOOD MANUFACTURING
REPEABILITY Internal schematic diagram
Description
The SuperMESH™ series is obtained through an
extreme optimization of ST’s well established
strip-based PowerMESH™ layout. In addition to
pushing on-resistance significantly down, special
care is taken to ensure a very good dv/dt
capability for the most demanding applications.

Applications
■ HIGH CURRENT, HIGH SPEED SWITCHING
■ IDEAL FOR OFF-LINE POWER SUPPLIES,
ADAPTOR AND PFC

Order codes

Sales Type Marking Package Packaging

STP10NK70Z P10NK70Z TO-220 TUBE

STP10NK70ZFP P10NK70ZFP TO-220FP TUBE

Rev 2
August 2005 1/13
www.st.com 13
1 Electrical ratings STP10NK70Z - STP10NK70ZFP

1 Electrical ratings

Table 1. Absolute maximum ratings

Symbol Parameter Value Unit

TO-220 TO-220FP

VDS Drain-Source Voltage (VGS = 0) 700 V

VDGR Drain-gate Voltage (RGS = 20kΩ) 700 V
VGS Gate-Source Voltage ± 30 V

ID Drain Current (continuous) at TC = 25°C 8.6 8.6 (Note 3) A

ID Drain Current (continuous) at TC = 100°C 5.4 5.4 (Note 3) A

IDM Note 2 Drain Current (pulsed) 34 34 (Note 3) A

PTOT Total Dissipation at TC = 25°C 150 35 W

Derating Factor 1.20 0.28 W/°C

Vesd(G-S) G-S ESD (HBM C=100pF, R=1.5kΩ) 4000 V
dv/dt
Peak Diode Recovery voltage slope 4.5 V/ns
Note 1
VISO Insulation Withstand Volatge (DC) -- 2500 V

Tj Operating Junction Temperature

-55 to 150 °C
Tstg Storage Temperature

Table 2. Thermal data

TO-220 TO-220FP Unit

Rthj-case Thermal Resistance Junction-case Max 0.83 3.6 °C/W

Rthj-amb Thermal Resistance Junction-amb Max 62.5 °C/W
Maximum Lead Temperature For Soldering
Tl 300 °C
Purpose

Table 3. Avalanche characteristics

Symbol Parameter Max Value Unit

Avalanche Current, repetitive or

IAR 8.6 A
Not-Repetitive (pulse width limited by Tj max)
Single Pulse Avalanche Energy
EAS 350 mJ
(starting Tj=25°C, ID=IAR, VDD = 50V)

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STP10NK70Z - STP10NK70ZFP 2 Electrical characteristics

2 Electrical characteristics

(TCASE = 25 °C unless otherwise specified)

Table 4. On/off states

Symbol Parameter Test Conditions Min. Typ. Max. Unit

Drain-Source Breakdown
V(BR)DSS ID = 1mA, V GS= 0 700 V
Voltage

Zero Gate Voltage Drain VDS = Max Rating, 1 µA

IDSS
Current (VGS = 0) VDS = Max Rating,Tc = 125°C 50 µA

Gate Body Leakage Current

IGSS VGS = ±20V, VDS = 0 ±10 µA
(VDS = 0)

VGS(th) Gate Threshold Voltage VDS= VGS, ID = 100 µA 3 3.75 4.5 V

Static Drain-Source On
RDS(on) VGS= 10 V, ID= 4.5 A 0.75 0.85 Ω
Resistance

Table 5. Dynamic
Symbol Parameter Test Conditions Min. Typ. Max. Unit

gfs Note 4 Forward Transconductance VDS =15V, ID = 4.5A 7.7 S

Ciss Input Capacitance 2000 pF
Coss Output Capacitance VDS =25V, f=1 MHz, V GS=0 190 pF
Crss Reverse Transfer Capacitance 41 pF

Coss eq.
Equivalent Ouput Capacitance VGS=0, VDS =0V to 560V 98 pF
Note 5
Qg Total Gate Charge VDD=560V, ID = 9 A 64 90 nC
Qgs Gate-Source Charge VGS =10V 12 nC
Qgd Gate-Drain Charge (see Figure 17) 33 nC

Table 6. Switching times

Symbol Parameter Test Conditions Min. Typ. Max. Unit

VDD=350 V, ID=4.5 A,
td(on) Turn-on Delay Time 22 ns
RG=4.7Ω, VGS=10V
tr Rise Time 19 ns
(see Figure 18)
VDD=350 V, ID=4.5A,
td(off) Turn-off Delay Time 46 ns
RG=4.7Ω, VGS=10V
tf Fall Time 19 ns
(see Figure 18)
tr(Voff) Off-voltage Rise Time VDD=560 V, ID=9A, 11 ns
tf Fall Time RG=4.7Ω, VGS=10V 10 ns
tc Cross-over Time (see Figure 18) 22 ns

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2 Electrical characteristics STP10NK70Z - STP10NK70ZFP

Table 7. Source drain diode

Symbol Parameter Test Conditions Min. Typ. Max. Unit

ISD Source-drain Current 8.6 A

ISDMNote 2 Source-drain Current (pulsed) 34 A

VSDNote 4 Forward on Voltage ISD=8.6 A, V GS=0 1.6 V

trr Reverse Recovery Time 720 ns

ISD=9A, di/dt = 100A/µs,
Qrr Reverse Recovery Charge 5.4 µC
VDD=35 V, Tj=150°C
IRRM Reverse Recovery Current 15 A

Table 8. Gate-source zener diode

Symbol Parameter Test Conditions Min. Typ. Max. Unit

BVGSO Gate-Source Igs=±1mA

30 V
Note 6 Breakdown Voltage (Open Drain)

(1) ISD ≤8.6 A, di/dt ≤200A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX

(2) Pulse width limited by safe operating area
(3) Limited only by maximum temperature allowed
(4) Pulsed: pulse duration = 300µs, duty cycle 1.5%
(5) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0
to 80%VDSS
(6)The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s ESD capability, but
also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this
respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device’s
integrity. These integrated Zener diodes thus avoid the usage of external components.

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STP10NK70Z - STP10NK70ZFP 2 Electrical characteristics

2.1 Electrical Characteristics (curves)

Figure 1. Safe Operating Area for TO-220 Figure 2. Thermal Impedanc for TO-220

Figure 3. Safe Operating Area for TO-220FP Figure 4. Thermal Impedance for TO-220FP

Figure 5. Output Characteristics Figure 6. Transfer Characteristics

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2 Electrical characteristics STP10NK70Z - STP10NK70ZFP

Figure 7. Transconductance Figure 8. Static Drain-Source on Resistance

Figure 9. Gate Charge vs Gate -Source Figure 11. Capacitance Variations

Voltage

Figure 10. Normalized Gate Threshold Voltage Figure 12. Normalized on Resistance vs
vs Temperatute Temperature

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STP10NK70Z - STP10NK70ZFP 2 Electrical characteristics

Figure 13. Source-drain Diode Forward Figure 14. Normalized BVDSS vs Temperature
Characteristics

Figure 15. Maximum Avalanche Energy vs

Temperature

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3 Test circuits STP10NK70Z - STP10NK70ZFP

3 Test circuits

Figure 16. Switching Times Test Circuit For Figure 17. Gate Charge Test Circuit
Resistive Load

Figure 18. Test Circuit For Indictive Load Figure 20. Unclamped Inductive Load Test
Switching and Diode Recovery Circuit
Times

Figure 19. Unclamped Inductive Waveform

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STP10NK70Z - STP10NK70ZFP 4 Package mechanical data

4 Package mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK®

packages. These packages have a Lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in compliance
with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also
marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are
available at: www.st.com

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4 Package mechanical data STP10NK70Z - STP10NK70ZFP

TO-220 MECHANICAL DATA

mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
A 4.40 4.60 0.173 0.181
b 0.61 0.88 0.024 0.034
b1 1.15 1.70 0.045 0.066
c 0.49 0.70 0.019 0.027
D 15.25 15.75 0.60 0.620
E 10 10.40 0.393 0.409
e 2.40 2.70 0.094 0.106
e1 4.95 5.15 0.194 0.202
F 1.23 1.32 0.048 0.052
H1 6.20 6.60 0.244 0.256
J1 2.40 2.72 0.094 0.107
L 13 14 0.511 0.551
L1 3.50 3.93 0.137 0.154
L20 16.40 0.645
L30 28.90 1.137
øP 3.75 3.85 0.147 0.151
Q 2.65 2.95 0.104 0.116

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STP10NK70Z - STP10NK70ZFP 4 Package mechanical data

TO-220FP MECHANICAL DATA

mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
A 4.4 4.6 0.173 0.181
B 2.5 2.7 0.098 0.106
D 2.5 2.75 0.098 0.108
E 0.45 0.7 0.017 0.027
F 0.75 1 0.030 0.039
F1 1.15 1.7 0.045 0.067
F2 1.15 1.7 0.045 0.067
G 4.95 5.2 0.195 0.204
G1 2.4 2.7 0.094 0.106
H 10 10.4 0.393 0.409
L2 16 0.630
L3 28.6 30.6 1.126 1.204
L4 9.8 10.6 .0385 0.417
L5 2.9 3.6 0.114 0.141
L6 15.9 16.4 0.626 0.645
L7 9 9.3 0.354 0.366
Ø 3 3.2 0.118 0.126
E
A

D
B

L3
L6
L7
F1

G1

G
H

F2

1 2 3
L5
L2 L4

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5 Revision History STP10NK70Z - STP10NK70ZFP

5 Revision History

Date Revision Changes

22-Aug-2005 2 Inserted Ecopack indication

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STP10NK70Z - STP10NK70ZFP 5 Revision History

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by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
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