Proceedings of the Sixth International Conference on Inventive Computation Technologies [ICICT 2021]

IEEE Xplore Part Number: CFP21F70-ART; ISBN: 978-1-7281-8501-9

High Performance Digital to Analog Converter

Using CMOS 45nm Technology

David Solomon Raju Y1 K Shyamala,2 Ch. Sumalatha,3

Associate Professor, ECE Dept., Assistant Professor, ECE Dept., Assistant Professor, ECE Dept.,
Holy M ary Institute of Technology & Science, Holy M ary Institute of Technology & Science, Shadan Women’s College of Engineering and
Hyderabad, India. Hyderabad, India Technology, Hyderabad, India.
[email protected] [email protected] [email protected]
2021 6th International Conference on Inventive Computation Technologies (ICICT) | 978-1-7281-8501-9/21/$31.00 ©2021 IEEE | DOI: 10.1109/ICICT50816.2021.9358566

J.Sunilkumar4
Assistant professor, ECE Dept,
Vignan’s Institute of Management and Technology for Women, Hyderabad, India, [email protected] m

Abstract - This article represents about 8-bit digital to analog

converter (DAC). A digital to analog converter (DAC) takes a II. Literature survey
digital signal and converts it to an analog signal (i.e; continuous
form) to drive the interfaces with the real-world such as a
speaker in the cell phone or the LED display on your watch. As In [1], the author proposed a 65 nm CMOS 6-bit 60 GS/s Time
such, anytime a digital circuit has to interface to a display or a Interleaved DAC with Full-Binary Sub-DACs. The more
speaker or an antenna or any number of other devices that need integrated DAC'S are interfacing with the multiple 2-channel
to be driven by an analog input and required a digital to analog 6-bit indistinguishable 20 Gs/s DAC'S. The DAC which has
converter (DAC). Digital to analog converter (DAC) is more exactly two children or zero for each node makes the DAC
efficient and substantially more accurate to do signal processing firm and powerless. By the heterogeneous analog signal and
in the digital domain (i.e language used by computers). This enhancing timing remove the bug in the software in the major
article represents a digital to analog converter (DAC). The DAC areas. The archetype DAC achieved a low figure of merit and
was implemented by using 45nm CMOS technology. It also a high SFDR ratio. In [2], the author proposed a 12-bit 20-
consumes 1.46mW of power from 1.8v supply voltage. The noise
margin of the DAC is 9dB. MS/s SAR ADC with Fast-Binary-Window DAC Switching in
Keywords—Current mirror, Differential amplifier, 180nm CMOS. The main drawback of the DAC in is the total
capacitance. This leads to the standardization of the capacitor
Common source amplifier, R-2R DAC
technique which is typically used for a mismatch. The main
I. Introduction usage of this standardization technique is to correct the errors
in the capacitor by using digital post-processing by consuming
The real-world information (or) data is in the form of analog. additional power and implementing complicated hardware.
The storing of digital information (or) data is easy when Another scheme called capacitance swapping is introduced to
compared to storing analog data. There are few benefits of improve the linearity of DAC by interchanging the total
storing digital information i) Analog information [1] requires capacitance one half with the other half. To have finer
more memory to store the digital form. ii) Digital signal linearity, DAC error which is caused by the capacitor
contains less noise iii) Digital data is encoded and refuge mismatch through the MSB capacitor switching error is
features. In real-time applications digital to analog converter is randomized it is removed to decrease the SNR [7] i.e signal to
used to receive the signal and analog to digital converter to noise ratio. [2]. In [3], the author suggested a Systematic
send the signal through the transmitter. The analog data if method to find an Optimized Quad-Quadrant Random Walk
interfaces the digital data [2] by using the [5] in real-world Sequence for reducing the Mismatch effect in Current Steering
applications. The sensors to sense the environment changes DAC. Linear distribution: The density of the oxide and
and gives the output then transducer is used to convert any stupefy of the wafer are the main causes for which linear error
form of signal to the electrical s ignal and vice versa. There are profile was shown in source current array L(x, y) = gL* cos θ*
many uses of DAC in electronic devices like in the i-phone x + gL * sin θ * y (Gradient angle is denoted by θ, gL is
because it is not having inbuilt headphones for converting denoted by linear gradient slope). Quadratic distribution:
audio, communications for converting digital data into analog Quadratic profile variation is shown by the mechanical stress
data, mobile phones, etc. There are two types of DAC [3-6] on the temperature gradient and the die Q(x, y) = gQ* x2(x2 −
they are summing amplifier and the R-2R ladder DAC. The y2) − a0 (parameters gQ and a θ are the dependent on the
output voltage of the DAC is 2.7v. technology). Joint distribution: It is the emplacement of linear

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 Proceedings of the Sixth International Conference on Inventive Computation Technologies [ICICT 2021]
IEEE Xplore Part Number: CFP21F70-ART; ISBN: 978-1-7281-8501-9

and quadratic distributions scaling factor for the ratio of linear

and quadratic error distribution is denoted by L(x, y) = w *
L(x, y) + Q(x, y) (5) here, w denotes the scaling factor for the
ratio of the linear and quadratic errors’ contribution. In [4], the
author proposed a Study of Gray Code Input DAC Using
MOSFETs for Glitch Reduction. Here, DAC glitches are
reduced using a technique input gray code using spice
simulation the operation to reduce glitches in DAC’S is
designed using MOSFETS. Here, the paradox of gray code
input DAC’S is displayed because it is believed the good
topologies do not exist. It can concluded that gray code input
DAC’S can reduce the glitches. In [4], the author summarized
the Low noise Output Stage for Overlapping Audio DAC. Fig:1. Schematic of CMOS Basic Current Mirror
This is based on the T/H circuit and de-glitch method. The As shown in the above-designed circuit, there are two NMOS
design approaches make it attractive for the o/p stage with an transistors. The two transistors are considered to be in a
SC-DAC to achieve low noise performance. The T/H circuit is working state when they are biased by 5v through VDD and
useful as a first filter in between SC-DAC and analog filter for given power supply 5 uA of transistor NMOS 2 through drain
a continuous-time reconstruction, and its effectiveness can be terminal and the gate terminal of NMOS 1. The 5uA current is
realized through de-glitching method. The utilization of the passing through NMOS 2 through the drain. This drain
T/H circuit is useless if de-glitching method is not considered . terminal and gate of NMOS 1 are shorted. The source terminal
This article is arranged in the following manner. Section I of the two transistors is grounded. The current is tested by
describes the introduction of the research work. Section II connecting the ammeter to the drain of NMOS 1.
details the literature survey. Section III explains the simulation
results of the proposed system such as current mirror,
differential amplifier, common source amplifier, operational
amplifier, and digital to analog converter. Section V concludes
the research work.

III. Simulation results of the proposed system

1. CURRENT MIRROR:
A current mirror is an electronic [8] circuit that is designed in
such a way that it copies a current from one active transistor
by controlling the current in another transistor by maintaining
the output current constant. The current mirror is a basic
current mirror. This current mirror also behaves as an
important block in an analog circuit as it plays an important . Fig: 2. Simulation results of the current mirror
role to find the all characteristics of a circuit and giving the
desired output. One of the important factors of this current The current source given to this current mirror is the
mirror is it is used to stabilize the current against any changes conventional current. By giving the input power supply of 5
in the environment. There are four types of current mirrors. uA have observed that the output is saturated of 5uA. This
Among all the types, a primitive current mirror is used in output is measured using an ammeter. As the output obtained
which the two transistors maintains the stability and also it is equal to the input power supply of 5uA, so that the current
consumes less area as compared to a cascaded current mirror is a mirror between the two transistors.
which in turn uses 6 transistors and consumes a large area.
The basic current mirror is used to supply the bias currents and 2. DIFFERENTIAL AMPLIFIER:
the active loads to the circuits. It can also be used to provide a
practical current mirror. The differential amplifier [9] is an electronic circuit that is
designed in such an amplifier that amplifies the difference
between the two input voltages. The differential amplifiers are
less sensitive to noise (CMRR>>1) and one of the important
factors is biasing i.e., biasing resistors doesn’t affect the
differential gain requires any bypass capacitors.

Cutoff region: VGS<=Vt

Active region: VDS<=Vov

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 Proceedings of the Sixth International Conference on Inventive Computation Technologies [ICICT 2021]
IEEE Xplore Part Number: CFP21F70-ART; ISBN: 978-1-7281-8501-9

Saturation region: VDS>= Vov 3. COMMON SOURCE AMPLIFIER:

As shown in the designed circuit his differential amplifier

consists of four transistors. Among the four transistors, two of
them are PMOS transistors and two of them are NMOS
transistors. To this differential amplifier Circuit, feed the
inverting input signal and the non-inverting input signal. The
inverting input terminal is given to NMOS 2 to work as an
amplifier. The input is provided to the non-inverting terminal
then the circuit acts as a comparator. The current mirror output
voltage is given as input voltage to this differential amplifier
i.e.500mV. The Vss is identical between the two NMOS
transistors. The drain terminal of NMOS 2 and gate terminal
of PMOS 1are shorted. Drain terminals of both PMOS Fig: 4. Schematic of common source amplifier.
transistors are connected to Vdd.
In designing a MOSFET amplifier, a common source
amplifier, common drain amplifier, and common gate
amplifier were used. Among these three types, a common
source amplifier plays an important role. The common source
amplifier [10] is used as a transconductance amplifier or
voltage amplifier. This type of amplifier can provide high
power gain, medium current, and voltage gains according to
the input and output impudence. This common source
amplifier is having high input impudence and low output
impudence. But the output obtained inverses the input
provided to the circuit i.e., 180'phase change [2].
As shown in the above-designed circuit this common source
consists of two transistors, one of the trans istors is PMOS
transistor and the other transistor is NMOS transistor. The
transistor which is near to the Vdd is called a pull-up transistor
Fig 3 (a): schematic differential amplifier and the transistor near to the ground is called a pull-down
transistor. The biasing voltage is V2 and the biasing voltage
input is given to the PMOS transistor. The Vdd is connected
2.1 Simulation of the differential amplifier to the source terminal of the PMOS transistor and the source
terminal of NMOS is grounded. The input voltage is given to
the NMOS transistor through the gate and V3 is an AC signal.
And V4 is a sinusoidal signal which is used to measure
amplitude and frequency. This V4 voltage acts as the function
generator to the common source circuit. For the sinusoidal
signal, the amplitude is 500mV and the frequency is 10 kHz.

3.1 Simulation of Common source amplifier:

Fig: 3 (b). Simulation results of the differential amplifier

The above graph is obtained by designing the appropriate
differential amplifier circuit. The output terminal is connected
across the source of PMOS 2 to drain of NMOS 2 and given
input as 500mV the output is obtained as 5V. The phase shift
is 0’ or 360’.The gain 68db is obtained by plotting the
frequency on x-axis as it is 10 KHZ and magnitude on y-axis
Fig: 5. Simulation results of common source amplifier.
The output of this common source circuit is measured through
the drain terminal of both NMOS and PMOS transistors. From

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 Proceedings of the Sixth International Conference on Inventive Computation Technologies [ICICT 2021]
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the graph obtained, it is observed that by giving the input 4.1 Simulation of operation amplifier
voltage source as 0.5v to obtain the output voltage of 3.8v
.input voltage: 0.5v
output voltage: 3.8v
phase.shift:180’

4. OPERATIONAL AMPLIFIER

Fig 7. Simulation results of the operational amplifier

The op-amp consists of sinusoidal with Input is 0.5v, output is

5.34 V, and the gain is 44db.

5. DIGITAL TO ANALOG CONVERTER

Fig: 6. Schematic of the operational amplifier

The operational amplifier is an electronics component, which

plays an important role in the electronics industry. It contains
two inputs such as the first is called a non-inverting band Fig 8. Schematic of 8 Bit DAC
second is called an inverting terminal. The basic role of the
operational amplifier is to enhance the voltage gain, input
impudence, and slew rate. And reduce the output impudence. Digital to analog signal is an electronic element that is mainly
The basic building blocks of conventional operational used to change the digital information into analog information.
amplifiers are the current mirror which is used to maintain In memories and communication systems the role of Digital to
current stability in the entire two-stage operational amplifier. analog signal is more. The operation of analog to digital
The conventional differential amplifier which is used to converter role is opposite to the digital to an analog signal.
amplify difference of two signals applied across their inputs, if Digital to analog signal takes the digital data in terms of
input applied at inverting side it acts as a conventional high binary levels or pulses with different timing periods with
gain amplifier. If input signal applied at the non-inverting side constant amplitude of 5 volts. Digital to an analog signal is
it acts as an arithmetic circuit and common source amplifier mainly implemented by the R-2R Ladder network [11]. With
which are used to amplify the signal in voltage levels among the constant value of resistors 20K and 10K resistors is in the
the entire amplifiers common source amplifier will amply an series and parallel. In this proposed model, 8-bit binary data is
important role in enhancing the gain. Based on the feedback, implemented, which is taken from pulses with different timing
the elements like resistor and capacitor gain the value of the periods. All these 8-bit digital signals are transferred through a
operational amplifier along with the changes. CMOS Two-stage operational amplifier.
The two inputs such as V1 and V2 and the two outputs were
observed. Op-amp consists of 3 main blocks namely, current
mirror, Differential Amplifier, and common Source. The
inverting and non-inverting signals are connected to the op-
amp. The input signal is given to Differential Amplifier with
pulse signal then the output receives from Common Source as
a sinusoidal signal.

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Table 1. 4-bit Binary input data with pulses Noise Margin 9 58 60 71

BIT-1 BIT-2 BIT-3 BIT-4 dB
RT =5ns RT =5ns RT=5ns RT=5ns FOM 1.59u 19787ns 11636ns 9362ns

IV. CONCLUSION: The main purpose of this research is to

PR=20ns PR=400ns PR=400n PR=80
resolve the transistors with more power consumption. The
s purpose has been achieved by introducing a new DAC idea.
When the results are compared with previous results, it is
observed that the technology operates with 180nm, along with
PW=95ns PW=200ns PW=800n PW=160 12-bit resolution, and consumes more power, and supply
voltage. Whereas overlapping of the audio DAC affects the
0ns glitching method. From these, it can concluded that the
proposed system is operated using Tanner CMOS
45nmtechnology which achieves better 8-bit DAC consumed
power 1.46mW with noise margin = 9dB is quite small
compared with previous approaches.
.
REFERENCES

[1] J. A. Schoeff, “An inherently linear 12 bit DAC,” IEEE J. Solid-

StateCircuits, vol. SC-14, no. 12, pp. 904–911, Dec. 1979.
[2] J. Bastos, M. Steyaert, and W. Sansen, “A high yield 12-bit 250-
MS/sCMOS D/A converter,” in Proc. IEEE Custom Int. Circuits
Conf.(CICC), May 1996, pp. 20.6.2–20.6.4.
[3] A.Van den Bosch, M. Borremans, M. St eyaert, andW. Sansen, “A 10-bit1-
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[4] K. Lakshmikumar, R. Hadaway, and M. Copeland, “Characterization and
modeling of mismatch in MOS transistors for precision analog design,”IEEE
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[5] M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G.Welbers, “ Macthing
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pp. 1433–1439, Oct. 1989.
[6] J. McCreary and P. Gray, “All-MOS charge redistribution analog-to-
digital conversion techniques,” IEEE J. Solid-State Circuits, vol. SC-10,
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[7] M. Pelgrom, A. Duinmaijer, and A. Welbers, "Matching
properties of MOS t ransistors", IEEE J. Solid-State
The graph representation in the digital input to get the output Circuits, vol. 24, pp.1433 -1440 1989
is the Noise Margin is 9db. The output for DAC is 2.7V, and [8] Y. Cong and R. Geiger "A 1.5 V 14 b 100 MS/s self-calibrated DAC",
IEEE ISSCC Dig. Tech. Papers, pp.128 -130 2003
Power Consumption is 1.46m watts. [9] Y. T ang et al., "A 14b 200MS/s DAC with SFDR>78dBc,
IM3<-83dBc and NSD<-163dBm/Hz across the whole
Table 2.Comparison table nyquist band enabled by dynamic-mismatch mapping," in
Symp. on VLSI Circ., pp. 151-152, June 2010.
[10] W.-H. T seng, C.-W. Fan and J.-T . Wu, "A 12b 1.25 GS/s
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45nm [11] Stanley Y.-S. Chen, N.-S Kim, J. Rabaey, "A 10b 600MS/s Multi-mode
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Power 1.46mw 20.07mw 22mw 52.5mw
consumption

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