UNIT-I

8-bit Microprocessors

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Microprocessor
A central processing unit (CPU) contained within a single chip. Today,
all computer CPUs are microprocessors. The term originated in the
1970s when CPUs up until that time were all comprised of several chips.
Thus, when the entire CPU (processor) was miniaturized onto a single
chip, the term "micro" processor was coined.

Microprocessor is often abbreviated MPU for "microprocessor unit" or

just MP, the latter also spelled with the Greek µ symbol for micro or the
letter "u" as an alternate (µP or uP).

They Started as 8-Bit

The first microprocessors were created by Texas Instruments, Intel and a
Scottish electronics company. Who was really first has been debated.
First-generation 8-bit families were Intel's 8080, Zilog's Z80

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MicroProcessor Unit (MPU)
Central Processor Unit (CPU)

Input 1
+
- Output
Input 2 *
/

8 Bits, 16 Bits, 32 Bits, 64 Bits

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MicroProcessor unit (MPU)

8 bits => Z-80, Z-180, MCS-51, PIC, AVR

16 bits = > 80286, M16, MSP430, Arm7
32 bits = > M32, 68332
64 bits => Pentium4…

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 Microprocessor

Address Data
O Data Bus
A A
I/O cpu MEM cpu D ROM D RAM I O I/O
D D
c
I
o
n
t
D
Request Decoder
Read/write

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8085 Functional Block Diagram

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Example: Instruction Fetch Operation

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 Bus and CPU
Bus: A shared group of wires used for communicating
signals among devices
• address bus: the device and the location within the
device that is being accessed
• data bus: the data value being communicated
• control bus: describes the action on the address and data
buses

CPU: Core of the processor, where instructions are executed

• High-level language: a = b + c
• Assembly language: add r1 r2 r3
• Machine language: 0001001010111010101

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 The 8085 Bus Structure

Address Bus
 Consists of 16 address lines: A0 – A15

 Operates in unidirectional mode: The address

bits are always sent from the MPU to peripheral
devices, not reverse.

 16 address lines are capable of addressing a

total of 216 = 65,536 (64k) memory locations.

 Address locations: 0000 (hex) – FFFF (hex)

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 The 8085 Bus Structure
Data Bus
 Consists of 8 data lines: D0 – D7

 Operates in bidirectional mode: The data bits are

sent from the MPU to peripheral devices, as well
as from the peripheral devices to the MPU.

 Data range: 00 (hex) – FF (hex)

Control Bus
 Consists of various lines carrying the control
signals such as read / write enable, flag bits.

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The 8085: CPU Internal Structure

Simplified block diagram

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 The 8085: CPU Internal Structure
Registers
 Six general purpose 8-bit registers: B, C, D, E, H, L
 They can also be combined as register pairs to
perform 16-bit operations: BC, DE, HL

 Registers are programmable (data load, move, etc.)

Accumulator
 Single 8-bit register that is part of the ALU !

 Used for arithmetic / logic operations – the result is

always stored in the accumulator.
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 The 8085: CPU Internal Structure
Flag Bits
 Indicate the result of condition tests.
 Carry, Zero, Sign, Parity, etc.

 Conditional operations (IF / THEN) are executed

based on the condition of these flag bits.
Program Counter (PC)
 Contains the memory address (16 bits) of the
instruction that will be executed in the next step.

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Flags
The ALU includes five flip-flops, which are set or reset after an
operation according to data conditions of the result in the
accumulator and other registers. They are called
Zero(Z), Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC)
flags; their bit positions in the flag register are shown in the Figure
below. The most commonly used flags are Zero, Carry, and Sign.
The microprocessor uses these flags to test data conditions.

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 Contains five flags known as flag registers:
• Sign flag, S indicates sign of a value
• Zero flag, Z, tells if a arithmetic or logical
instruction produced 0 for a result.
• Parity flag, P, is set to 1 if result contains even
number of 1’s
• Carry flag, CY, is set when an arithmetic
operation generates a carry out.
•Auxiliary carry flag, generates a carry out from a
lower half of a result to a upper half.
Example:
0000 1111 + 0000 1000 = 0001 0111 17
 Example: Instruction Fetch Operation

 All instructions (program steps) are stored in memory.

 To run a program, the individual instructions must

be read from the memory in sequence, and executed.

 Program counter puts the 16-bit memory address of the

instruction on the address bus
 Control unit sends the Memory Read Enable signal to
access the memory
 The 8-bit instruction stored in memory is placed on the data
bus and transferred to the instruction decoder
 Instruction is decoded and executed

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Example: Instruction Fetch Operation

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Pin diagram

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Pin Description
The following describes the function of each pin:
A8 - A15
Address Bus; The most significant 8 bits of the memory address or
the 8 bits of the I/O address.
AD0 - 7
Multiplexed Address/Data Bus; Lower 8 bits of the memory address (or I/0
address) appear on the bus during the first clock cycle of a machine state. It
then becomes the data bus during the second and third clock cycles.

ALE (Output)
Address Latch Enable: It occurs during the first clock cycle of a
machine state and enables the address to get latched into the on chip
latch of peripherals. The falling edge of ALE is set to guarantee setup
and hold times for the address information.

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SO, S1 (Output)
Data Bus Status. Encoded status of the bus cycle:
S1 S0
O O HALT
0 1 WRITE
1 0 READ
1 1 FETCH

RD
READ; indicates the selected memory or I/O device is to be read and that
the Data Bus is available for the data transfer.

WR
WRITE; indicates the data on the Data Bus is to be written into the selected
memory or I/O location. Data is set up at the trailing edge of WR.
READY (Input)
If Ready is high during a read or write cycle, it indicates that the memory or
peripheral is ready to send or receive data. If Ready is low, the CPU will wait
for Ready to go high before completing the read or write cycle.

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HOLD (Input)
HOLD; indicates that another Master is requesting the use of the
Address and Data Buses. The CPU, upon receiving the Hold request
will relinquish the use of buses as soon as the completion of the
current machine cycle. Internal processing can continue.
The processor can regain the buses only after the Hold is removed.

HLDA (Output)
HOLD ACKNOWLEDGE; indicates that the CPU has received the Hold
request and that it will relinquish the buses in the next clock cycle.
HLDA goes low after the Hold request is removed. The CPU takes the
buses one half clock cycle after HLDA goes low.

INTR (Input)
INTERRUPT REQUEST; is used as a general purpose interrupt. It is
sampled only during the next to the last clock cycle of the instruction.
If it is active, the Program Counter (PC) will be inhibited from
incrementing and an INTA will be issued. During this cycle a RESTART
or CALL instruction can be inserted to jump to the interrupt service
routine. The INTR is enabled and disabled by software. It is disabled
by Reset and immediately after an interrupt is accepted. 23
INTERRUPTS-
RST 7.5 ~~ Highest Priority
RST 6.5
RST 5.5 Lowest Priority
The priority of these interrupts is ordered as shown above. These
interrupts have a higher priority than the INTR.
TRAP (Input)
Trap interrupt is a nonmaskable restart interrupt. It is recognized at
the same time as INTR. It is unaffected by any mask or Interrupt
Enable. It has the highest priority of any interrupt.
RESET IN (Input)
Reset sets the Program Counter to zero and resets the Interrupt Enable and
HLDA flipflops. None of the other flags or registers (except the instruction
register) are affected The CPU is held in the reset condition as long as Reset
is applied.

RESET OUT (Output)

Indicates CPlJ is being reset. Can be used as a system RESET. The signal is
synchronized to the processor clock.
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X1, X2 (Input)
Crystal or R/C network connections to set the internal clock generator X1 can
also be an external clock input instead of a crystal. CLK (Output)
Clock Output for use as a system clock when a crystal or R/ C network is
used as an input to the CPU. The period of CLK is twice the X1, X2 input
period.

IO/M (Output)
IO/M indicates whether the Read/Write is to memory

SID (Input) Serial input data line The data on this line is loaded
into accumulator bit .
SOD (output) Serial output data line.
Vcc +5 volt supply.
Vss
Ground Reference.

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 8085 Addressing Modes

• Microprocessor needs
memory address to
access data from the
memory.
• Assembly language
may use several
addressing modes to
accomplish this task.

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The 8085 Addressing Modes The instructions MOV B, A or MVI
A, 82H are to copy data from a source into a destination. In
these instructions the source can be a register, an input port,
or an 8-bit number (00H to FFH). Similarly, a destination can
be a register or an output port. The sources and destination
are operands. The various formats for specifying operands
are called the ADDRESSING MODES. For 8085, they are:
1. Immediate addressing. 2. Register addressing.3. Direct
addressing. 4. Indirect addressing.

Immediate addressing Data is present in the instruction. Load

the immediate data to the destination provided.
Example: MVI R,data
Register addressing
Data is provided through the registers.
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Example: MOV Rd, Rs
Direct addressing Used to accept data from outside devices to
store in the accumulator or send the data stored in the
accumulator to the outside device. Accept the data from the port
00H and store them into the accumulator or Send the data from
the accumulator to the port 01H.

Indirect Addressing This means that the Effective Address is

calculated by the processor. And the contents of the address (and
the one following) is used to form a second address. The second
address is where the data is stored.

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Instruction Format
An instruction is a command to the microprocessor to perform a
given task on a specified data. Each instruction has two parts: one
is task to be performed, called the operation code (opcode), and
the second is the data to be operated on, called the operand. The
operand (or data) can be specified in various ways. It may include
8-bit (or 16-bit ) data, an internal register, a memory location, or 8-
bit (or 16-bit) address.
In some instructions, the operand is implicit.

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These instructions are 1-byte instructions performing three different tasks. In
the first instruction, both operand registers are specified. In the second
instruction, the operand
B is specified and the accumulator is assumed. Similarly, in the third instruction,
the
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accumulator is assumed to be the implicit operand. These instructions are
MOV rd, rs
rd <-- rs copies contents of rs into rd.
Coded as 01 ddd sss where ddd is a code for one of the 7
general registers which is the destination of the data, sss is the
code of the source register.
Example: MOV A,B
Coded as 01111000 = 78H ADD r
A <-- A + r

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MVI r,data
r <-- data
Example: MVI A,30H coded as 3EH 30H as two contiguous bytes.
This is an example of immediate addressing.
ADI data
A <-- A + data

Three-Byte Instructions
In a three-byte instruction, the first byte specifies the opcode, and
the following two bytes specify the 16-bit address. Note that the
second byte is the low-order address and the third byte is the
high-order address.
opcode + data byte + data byte
For example:

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This instruction would require three memory locations to store in memory.

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8085 Timing Processes
The crux of instruction execution consists of the READ and WERITE
operations which involve data transfer between the processor and
memory or input/output devices. All 8085 instructions have various
characteristic sequences of these READ and WRITE operations.
Each such READ and WRITE operation constitutes a machine cycle(M).
The instruction of 8085 take 1-6 machine cycles. Each machine cycle
consist of a number clock period/cycles, called T-state. Each machine
cycle consists of 3-6 clock cycles.

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n Define following terms:
1) Instruction cycle – it is the time required to complete the execution of an
instruction. 8085 has instructions which consume one to six machine cycles.
2) Machine Cycle – it is defined as the time required to complete one operation of
accessing memory, I/O, or acknowledging an external request. This cycle may consists
of three to six T-states

T – state – It is defined as one subdivision of the operation performed in one clock

period. These subdivisions are internal states synchronized with the system clock and
each T – state is precisely equal to one clock period.

Tristate Devices:
Tri-state logic devices have three stages: logic 1, logic 0 and high impedance. The term
TRI – STATE is a trade mark of National Semiconductor and is used to represent three
logic states. A tri-state device has has a third line called enable. When this line is
activated, the device functions the same way as ordinary logic devices. When this third
line is disabled, the logic device goes into high impedance state – as if it were
disconnected from the system. Ordinarily, current is required to drive a device in logic 0
or logic 1 states. In high impedance state, practically no current is drawn from the
system.
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Consider the example of fetching the machine code of instruction MOV C, A (0100
1111 = 4F) stored at the address 2005

Step1: Program Counter places the 16-bit memory address on the address bus.
In Timing diagram, during the T-state T1 the higher order memory address 20H is
placed on the address lines A15-A8, the lower order address 05H is placed on the bus
AD7-AD0, and ALE signal goes high. The status signal IO/M goes low, indicating this
is a memory-related operation.
Step2: The control unit sends the control signal RD to enable the memory chip
The control signal RD is sent out during the clock period T2, thus enabling the memory
chip. This signal is active for two clock periods.
Step3: The byte from the memory location is placed on the data bus.
When the memory is enabled, the instruction byte (4F) is placed on the bus AD7 – AD0
and transferred to the microprocessor. The RD signal causes 4F to be placed on the
multiplexed bus and when RD goes high, it causes the bus to go into high impedance
Step4: The byte is placed in the instruction decoder of the microprocessor and the task
is carried out according to the instruction.
The instruction decoder decodes the machine code and the contents of the accumulator
are copied into register C. This task is performed during periodT4.

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 8085 INSTRUCTION SET

1.DATA TRANSFER OPERATION

2.ARITHMATIC OPERATIONS

3.LOGICAL OPERATION
 DATA TRANSFER
IT COPIES DATA FROM A REGISTER (I/O or MEMORY)
CALLED THE SOURCE TO ANOTHER REGISTER (I/O or
MEMORY) CALLED THE DESTINATION

HERE THE CONTENTS OF SOURCE ARE NOT

TRANSFERRED BUT ARE COPIED INTO THE
DESTINATION REGISTER WITHOUT MODIFYING
THE CONTENTS OF THE SOURCE
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ADDITION

• The contents of the accumulator are 93H and the contents

of the register C are B7H. Add both the contents ?
• Soln:- ADD C
CY D7 D6 D5 D4 D3 D2 D1 D0
A : 93H = 1 0 0 1 0 0 1 1
+
C : B7H = 1 0 1 1 0 1 1 1

SUM (A) : 4AH = 1 0 1 0 0 1 0 1 0

Flag Status : S=0 , Z=0 , Cy=1

 LOGICAL OPERATIONS
• It can perform all logic function’s of the hardwired logic through it’s
instruction set.
• Instruction’s :
ANA : Logically AND the content’s of a register.
ANI : Logically AND 8-bit data.
ORA : Logically OR the content’s of the register.
ORI : Logically OR 8-bit data.
XRA : Exclusive OR the content’s of the register.
XRI : Exclusive OR 8-bit data.
Overview of Logic Operations
How RIM sets the Accumulator’s
different bits
7 6 5 4 3 2 1 0

M5.5
M7.5
M6.5
P6.5
P7.5

P5.5
SDI

IE
RST5.5 Mask
Serial Data In RST6.5 Mask
RST7.5 Mask
} 0 - Available
1 - Masked

RST5.5 Interrupt Pending

RST6.5 Interrupt Pending
RST7.5 Interrupt Pending Interrupt Enable
Value of the Interrupt Enable
Flip Flop

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 How SIM Interprets the
Accumulator7 6 5 4 3 2 1 0

M5.5
M7.5
M6.5
MSE
SDO

R7.5
SDE
XXX
RST5.5 Mask
Serial Data Out RST6.5 Mask
RST7.5 Mask
} 0 - Available
1 - Masked

Enable Serial Data Mask Set Enable

0 - Ignore bit 7 0 - Ignore bits 0-2
1 - Send bit 7 to SOD pin 1 - Set the masks according
to bits 0-2

Not Used Force RST7.5 Flip Flop to reset

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1. What are the various registers in 8085?
Accumulator register, Temporary register, Instruction register, Stack Pointer, Program Counter
are the various registers in 8085 .

2. In 8085 name the 16 bit registers?

Stack pointer and Program counter all have 16 bits.

3. What are the various flags used in 8085?

Sign flag, Zero flag, Auxillary flag, Parity flag, Carry flag.

4. What is Stack Pointer?

Stack pointer is a special purpose 16-bit register in the Microprocessor, which holds the
address of the top of the stack.

5. What is Program counter?

Program counter holds the address of either the first byte of the next instruction to be fetched
for execution or the address of the next byte of a multi byte instruction, which has not been
completely fetched. In both the cases it gets incremented automatically one by one as the
instruction bytes get fetched. Also Program register keeps the address of the next instruction.

6. Which Stack is used in 8085?

LIFO (Last In First Out) stack is used in 8085.In this type of Stack the last stored information
can be retrieved first.
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7. What happens when HLT instruction is executed in processor?
The Micro Processor enters into Halt-State and the buses are tri-stated.

8. What is meant by a bus?

A bus is a group of conducting lines that carriers data, address, & control signals.

9. What is Tri-state logic?

Three Logic Levels are used and they are High, Low, High impedance state. The high and low
are normal logic levels & high impedance state is electrical open circuit conditions. Tri-state
logic has a third line called enable line.

10. Give an example of one address microprocessor?

8085 is a one address microprocessor.

11. In what way interrupts are classified in 8085?

In 8085 the interrupts are classified as Hardware and Software interrupts.

12. What are Hardware interrupts?

TRAP, RST7.5, RST6.5, RST5.5, INTR.

13. What are Software interrupts?

RST0, RST1, RST2, RST3, RST4, RST5, RST6, RST7.
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14. Which interrupt has the highest priority?
TRAP has the highest priority.

15. Name 5 different addressing modes?

Immediate, Direct, Register, Register indirect, Implied addressing modes.

16. How many interrupts are there in 8085?

There are 12 interrupts in 8085.

17. What is clock frequency for 8085?

3 MHz is the maximum clock frequency for 8085.

18. What is the RST for the TRAP?

RST 4.5 is called as TRAP.

19. In 8085 which is called as High order / Low order Register?

Flag is called as Low order register & Accumulator is called as High order Register.

20. What are input & output devices?

Keyboards, Floppy disk are the examples of input devices. Printer, LED / LCD display, CRT
Monitor are the examples of output devices.

21. Can an RC circuit be used as clock source for 8085?

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Yes, it can be used, if an accurate clock frequency is not required. Also, the component cost is
low compared to LC or Crystal.
22. Why crystal is a preferred clock source?
Because of high stability, large Q (Quality Factor) & the frequency
that doesn’t drift with aging. Crystal is used as a clock source most of
the times.

23. Which interrupt is not level-sensitive in 8085?

RST 7.5 is a raising edge-triggering interrupt.

24. What does Quality factor mean?

The Quality factor is also defined, as Q. So it is a number, which
reflects the lossness of a circuit. Higher the Q, the lower are the losses.

25. What are level-triggering interrupt?

RST 6.5 & RST 5.5 are level-triggering interrupts.

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