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Chapter-1Preamble
1.1 Introduction
In our proposed system we are using two ZigBee Transceiver based embedded
system based on ARM microcontroller. One system is installed inside the vehicle and other
system is installed at the entrance. When the vehicle enter at the entrance it was identiIied by
the ZigBee Transceiver installed at the gate by veriIying code oI the vehicle
ZigBeetransceiver.Then the ZigBee based system at the gate asks driver to enter password.
This password is also veriIied by the system at the entrance gate. Once both the vehicle
identiIication and the driver authentication has done then the system send the inIormation to
the security guard at the gate. According to this inIormation the guard allows or denies access
to the vehicle inside the premises.


Figure 1.1.1: Block diagram oI kit.
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1.2 Statement of the Problems
1.2.1 Present model
Manual security system in INDIA,specially in allvery important places like
Parliament and VidhanSoudha.
In the Parliament and VidhanSoudha,we have weak security system(manual security
system) like iI someone has red light vehicle or any government vehicle then he can
easily enter in the parliament and that was the main reason whatever happened in the
parliament like MILITANT attack.

Figure 1.2.1.1: Present Scenario

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1.2.2Remedies oI present model
AUTOMATIC ZIGBEE WIRLESS VEEHICULAR INDENTIFICATION AND
AUTHENTICATION Security based systems.

Figure 1.2.2.1: Remedy Ior Present Scenario
There are two module in our present model(module1 and module2), now module 1
we will installed at the entrance oI the parliament gate and module2 we will installed
inside the vehicle.
Now when the vehicle enter at the entrance it will identiIied by the ZIGBEE
transceiver installed at the gate.
AIter that the ZIGBEE based system at the gate asks the driver to enter the password
and this password is also veriIied by the system at the entrance gate.
Now once both the vehicle identiIication is and the driver authentication has been
done then the inIormation is being sent by the system to the security guard at the gate.
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According to this inIormation the guard will allows or denies access to the vehicle
inside the premises.
1.3 Objective of study
Provide Security in all very important places as well as very important people
through ZIGBEE WIRLESS VEEHICULAR INDENTIFICATION AND
AUTHENTICATION SYSTEM.
Use oI ZigBee module ensures the system to be low cost and low power consumable
system.
User-Iriendly interIace and simple system setup.
1.4 Scope of study
vehlcles ldenLlflcaLlon aL vls places
A8LlAM-@vls PCMPC@Ls(all hlh level hoLels) and aparLmenLs
1.5 Review of literature
@he 8031 MlcroconLroller and embedded sysLems by MAZlul and LC daLasheeLs and Lhe
user manual for Lhe LC2148
1.6: Methodology
@hree Lype of meLhodoloy we are uslnle
ofLware mbedded C and vlsual baslc
@oolskell llash malc
@A8C@ uvlC LC2148(A8M7)mlcroconLroller
1.7 Limitation of study
Only one limitation
we are using two module in our project that is module 1 and module2.
Module1 we will installed at the entrance oI the gate and module2 we will installed
inside the vehicle.
Now suppose iI someone take module2 which we have installed inside the vehicle
and he will installed the same module2 in his vehicle


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And take the worst case also, suppose he knows the password also then he can break
the security system.

2. HARDWARE DISCRIPTION
2.1 LPC2148 MICROCONTROLLER
2.1.1 General Description

The LPC2141/42/44/46/48 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-SCPU

with real-time emulation and embedded trace support, that combine microcontroller with
embedded high-speed Ilash memory ranging Irom 32 kB to 512 kB. A 128-bit widememory
interIace and a unique accelerator architecture enable 32-bit code execution atthe maximum
clock rate. For critical code size applications, the alternative 16-bit Thumbmode reduces code
by more than 30 with minimal perIormance penalty.Due to their tiny size and low power
consumption, LPC2141/42/44/46/48 are ideal Iorapplications where miniaturization is a key
requirement, such as access control andpoint-oI-sale. Serial communications interIaces
ranging Irom a USB 2.0 Full-speed device,multiple UARTs, SPI, SSP to I2C-bus and on-
chip SRAM oI 8 kB up to 40 kB, make thesedevices very well suited Ior communication
gateways and protocol converters, soItmodems, voice recognition and low end imaging,
providing both large buIIer size and highprocessing power. Various 32-bit timers, single or
dual 10-bit ADC(s), 10-bit DAC, PWMchannels and 45 Iast GPIO lines with up to nine edge
or level sensitive external interrupt pins make these microcontrollers suitable Ior industrial
control and medical systems.

2.1.2 Features
16-bit/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package.
8 kB to 40 kB oI on-chip static RAM and 32 kB to 512 kB oI on-chip Ilash memory.
128-bit wide interIace/accelerator enables high-speed 60 MHz operation.
In-System Programming/In-Application Programming (ISP/IAP) via on-chip
bootloader soItware. Single Ilash sector or Iull chip erase in 400 ms and programming
oI256 bytes in 1 ms.
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EmbeddedICE RT and Embedded Trace interIaces oIIer real-time debugging with
theon-chip RealMonitor soItware and high-speed tracing oI instruction execution.
USB 2.0 Full-speed compliant device controller with 2 kB oI endpoint RAM.
In addition, the LPC2146/48 provides 8 kB oI on-chip RAM accessible to USB by
DMA.
One or two (LPC2141/42 vs. LPC2144/46/48) 10-bit ADCs provide a total oI
6/14analog inputs, with conversion times as low as 2.44 ms per channel.
Single 10-bit DAC provides variable analog output (LPC2142/44/46/48 only).
Two 32-bit timers/external event counters (with Iour capture and Iour
comparechannels each), PWM unit (six outputs) and watchdog.
Low power Real-Time Clock (RTC) with independent power and 32 kHz clock input.
Multiple serial interIaces including two UARTs (16C550), two Fast I2C-bus (400
kbit/s), SPI and SSP with buIIering and variable data length capabilities.
Vectored Interrupt Controller (VIC) with conIigurable priorities and vector addresses.
Up to 45 oI 5 V tolerant Iast general purpose I/O pins in a tiny LQFP64 package.
Up to 21 external interrupt pins available.
60 MHz maximum CPU clock available Irom programmable on-chip PLL with
settling time oI 100 ms.
On-chip integrated oscillator operates with an external crystal Irom 1 MHz to 25
MHz.
Power saving modes include Idle and Power-down.
Individual enable/disable oI peripheral Iunctions as well as peripheral clock scaling
Ior additional power optimization.
Processor wake-up Irom Power-down mode via external interrupt or BOD.
Single power supply chip with POR and BOD circuits: CPU operating voltage range
oI 3.0 V to 3.6 V (3.3 V 10 ) with 5 V tolerant I/O pads.



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2.1.3 Block diagram oI LPC2148

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Figure 2.1.3.1: Lpc2148 block diagram

2.1.4 PIN DETAILS OF LPC2148
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Figure 2.1.4.1: Lpc2148 pin details

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2.2 ZIGBEE

Figure2.2.1:zigbeemodules
The XBee and XBee-PRO OEM RF Modules were engineered to meet IEEE 802.15.4
standards and support the unique needs oI low-cost, low-power wireless sensor networks.
The modules require minimal power and provide reliable delivery oI data between devices.
The modules operate within the ISM 2.4 GHz Irequency band and are pin-Ior-pin compatible
with each other.
2.2.1 Features
Long Range Data Integrity
Indoor/Urban: up to 100` (30 m)
Outdoor line-oI-sight: up to 300` (100 m)
Transmit Power: 1 mW (0 dBm)
Receiver Sensitivity: -92 dBm
Low Power
TX Current: 45 mA (3.3 V)
RX Current: 50 mA (3.3 V)
Power-down Current: 10 A
ADC and I/O Line Support
O Analog-to-digital conversion, Digital I/OI/O Line Passing
Advanced Networking & Security
O Retries and Acknowledgements
O DSSS (Direct Sequence Spread Spectrum)
O Each direct sequence channels has over 65,000 unique network
addresses available
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O Source/Destination Addressing
O Unicast & Broadcast Communications
O Point-to-point, point-to-multipoint and peer-to-peer topologies
supported
O Coordinator/End Device operations
Easy-to-Use
O conIiguration necessary Ior out-oI box RF communications
O Free X-CTU SoItware (Testing and conIiguration soItware)
O AT and API Command Modes Ior conIiguring module parameters
O Extensive command set
O Small Iorm Iactor
2.2.2 Mounting Considerations
The XBee/XBee-PRO RF Module was designed to mount into a receptacle (socket) and
thereIore does not require any soldering when mounting it to a board. The XBee
Development Kits contain RS-232 and USB interIace boards which use two 20-pin
receptacles to receive modules.

Figure 2.2.2.1: Mounting Considerations
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The receptacles used on MaxStream development boards are manuIactured by
Century Interconnect. Several other manuIacturers provide comparable mounting solutions;
however, MaxStream currently uses the Iollowing receptacles:
Through-hole single-row receptacles - Samtec P/N: MMS-110-01-L-SV (or equivalent)
SurIace-mount double-row receptacles - Century Interconnect P/N: CPRMSL20-D-0-1 (or
equivalent)
SurIace-mount single-row receptacles - Samtec P/N: SMM-110-02-SM-S
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2.2.3 PinSignals

Table: 2.2.3.1 pin signals oI zigbee.











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2.3 Dot Matrix Liquid Crystal Display Controller/Driver

2.3.1 Description

The HD44780U dot-matrix liquid crystal display controller and driver LSI displays alpha
numeric, Japanese kana characters, and symbols. It can be conIigured to drive a dot-matrix
liquid crystal display under the control oI a 4- or 8-bit microprocessor. Since all the Iunctions
such as display RAM, character generator, and liquid crystal driver, required Ior driving a
dot-matrix liquid crystal display are internally provided on one chip, a minimal system can
be interIaced with this controller/driver. A single HD44780U can display up to one 8-
character line or two 8 character lines. The HD44780U has pin Iunction compatibility with
the HD44780S which allows the user to easily replace an LCD-II with an HD44780U. The
HD44780U character generator ROM is extended to generate 208 5 8 dot character Ionts
and 32 5 10 dot character Ionts Ior a total oI 240 diIIerent character Ionts. The low power
supply (2.7V to 5.5V) oI the HD44780U is suitable Ior any portable battery-drivenproduct
requiring low power dissipation.

2.3.2 Features
4 5 8 and 5 10 dot matrix possible
4 Low power operation support:
2.7 to 5.5V
4 Wide range oI liquid crystal display driver power
3.0 to 11V
4 Liquid crystal drive waveIorm
A (One line Irequency AC waveIorm)
4 Correspond to high speed MPU bus interIace
2 MHz (when VCC 5V)
4 4-bit or 8-bit MPU interIace enabled
4 80 8-bit display RAM (80 characters max.)
4 9,920-bit character generator ROM Ior a total oI 240 character Ionts
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208 character Ionts (5 8 dot)
32 character Ionts (5 10 dot)
4 64 8-bit character generator RAM
8 character Ionts (5 8 dot)
4 character Ionts (5 10 dot)
4 16-common 40-segment liquid crystal display driver
4 Programmable duty cycles
1/8 Ior one line oI 5 8 dots with cursor
1/11 Ior one line oI 5 10 dots with cursor
1/16 Ior two lines oI 5 8 dots with cursor
4 Wide range oI instruction Iunctions:
Display clear, cursor home, display on/oII, cursor on/oII, display
character blink, cursor shiIt, display shiIt
4 Pin Iunction compatibility with HD44780S
4 Automatic reset circuit that initializes the controller/driver aIter power on
4 Internal oscillator with external resistors
4 Low power consumption
2.4 Power Supply Unit
This supplies power to the entire circuit. Here we use a step down transIormer to obtain the
voltage Irom the mains. This unregulated voltage is regulated using Iull wave rectiIiers and
regulators, to obtain required voltage.

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Figure 2.4.1:Input and Output wave forms

2.4.1 POWER SUPPLY CAPACITORS
This consists oI two types oI capacitors
1. Power supply Iilter capacitors
2. Power supply decoupling capacitors

2.4.2 Power supply Iilter capacitors
According to Thumbs rule Ior one milliamp current, one microIarad capacitor has to be
used. Applying this rule we have used two capacitors
1. 470F This capacitor supplies current the microcontroller and LCD, which might
require higher current, hence higher value oI capacitance.
2. 100F This capacitor supplies current to the op-amp which might require lower
current, hence lower value oI capacitance.


Figure 2.4.2.1: power supply capacitors
2.4.3 Power supply decoupling capacitors
They are connected right across the supply pins. We know that energy can neither be created
nor be destroyed. It can only be converted Irom one Iorm to another. In the path oI supplying
power to the IC, there will be many wires or tracks which act as inductors. The property oI
inductor, according to Lenz`s law is that it does not allow sudden shoot up oI current. Hence
these capacitors act as storage devices which help in supplying current to ICs. Also all the
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circuits are operated only by a single supply because oI which there might be disturbances in
the supply. These capacitors do not allow disturbances in the power supply.

2.4.4 VOLTAGE REGULATOR
A voltage regulator is a circuit that supplies a constant voltage regardless oI the changes in
load currents. It may be used to produce a Iixed DC output Irom variable DC (which contains
small amount oI AC in it). Although voltage regulators can be designed using op-amp, it is
quicker and easier to use IC voltage regulators. IC voltage regulators are versatile and
inexpensive and are available with Ieatures such as programmable output, current voltage
boosting and internal short circuit current limiting, thermal shut down and Iloating operations
Ior high voltage applications. IC voltage regulators are oI Iollowing types;
Fixed output voltage regulators
Adjustable output voltage regulators
Switching regulators
Special regulators
Except switching regulator, all types oI regulators are called linear regulators. Here we have
used Iixed output voltage regulators only in which positive voltage regulator is a type oI it.
2.4.5 POSITIVE VOLTAGE REGULATOR
These ICs are designed as Iixed voltage regulators and with adequate heat sinking can deliver
output currents in excess oI 1 A. The ICs have internal thermal overload protection and
internal short circuit current limiting. Proper operation requires a common ground between
input and output voltages. In addition to this, the diIIerence between the input and output
voltages called dropout voltage, must be typically 2.0 V.
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Further a capacitance Ci is required iI the voltage regulator is located at an appreciable
distance Irom the power supply Iilter. Co is not needed but it may be required to improve the
transient response oI the regulator.

Figure2.4.5.1(a): posltlve voltoqe teqolotot Figure2.4.5.1(b): 7805 IC
2.4.6 HEAT SINK
In the process oI regulation, input voltage should be 3V more than the output voltage, in
order to regulate. Due to this there will be a voltage across the regulator and current Ilowing
through it. We know that PVI, hence there will be generation oI power which causes
heating up oI the components. Hence this heat has to be dissipated. This is done using heat
sink.
A heat sink is an environment or object that absorbs and dissipates heat Irom another object
using thermal contact (either direct or radiant). Heat sinks are used in a wide range oI
applications wherever eIIicient heat dissipation is required
Heat sinks Iunction by eIIiciently transIerring thermal energy ("heat") Irom an object at a
relatively high temperature to a second object at a lower temperature with a much greater
heat capacity. This rapid transIer oI thermal energy quickly brings the Iirst object into
thermal equilibrium with the second, lowering the temperature oI the Iirst object, IulIilling
the heat sink's role as a cooling device. EIIicient Iunction oI a heat sink relies on rapid
transIer oI thermal energy Irom the Iirst object to the heat sink, and the heat sink to the
second object. The most common design oI a heat sink is a metal device with many pins. The
high thermal conductivity oI the metal combined with its large surIace area due to the pins
results in the rapid transIer oI thermal energy to the surrounding, cooler material. This cools
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the heat sink and whatever it is in direct thermal contact with. It is an anodized black
component. It is black in color because black is a good radiator (black body radiation).

Figure 2.4.6.1: eat sink with aluminum holder to mount regulator

2.5 Introduction to Serial Communication
2.5.1 Introduction
The purpose oI this application note is to attempt to describe the main elements in Serial
Communication. This application note attempts to cover enough technical details oI RS232,
RS422 and RS485
2.5.2 DCE and DTE Devices

DTE stands Ior Data Terminal Equipment, and DCE stands Ior Data Communications
Equipment. These terms are used to indicate the pin-out Ior the connectors on a device and
the direction oI the signals on the pins. Your computer is a DTE device, while most other
devices such as modem and other serial devices are usually DCE devices. RS-232 has been
around as a standard Ior decades as an electrical interIace between Data Terminal Equipment
(DTE) and Data Circuit-Terminating Equipment (DCE) such as modems or DSUs. It appears
under diIIerent incarnations such as RS-232C, RS-232D, V.24, V.28 or V.10. RS-232 is used
Ior asynchronous data transIer as well as synchronous links such as SDLC, HDLC, Frame
Relay and X.25

2.5.3 Synchronous data transIer

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In program-to-program communication, synchronous communication requires that each end
oI an exchange oI communication respond in turn without initiating a new communication. A
typical activity that might use a synchronous protocol would be a transmission oI Iiles Irom
one point to another. As each transmission is received, a response is returned indicating
success or the need to resend.
2.5.4 Asynchronous data transIer
The term asynchronous is usually used to describe communications in which data can be
transmitted intermittently rather than in a steady stream. For example, a telephone
conversationis asynchronous because both parties can talk whenever they like. II the
communication were synchronous, each party would be required to wait a speciIied interval
beIore speaking. The diIIiculty with asynchronous communications is that the receiver must
have a way to distinguish between valid data and noise. In computer communications, this is
usually accomplished through a special start bit and stop bit at the beginning and end oI each
piece oI data. For this reason, asynchronous communication is sometimes called start-stop
transmission.

2.5.5 RS232

RS-232 (Recommended standard-232) is a standard interIace approved by the Electronic
Industries Association (EIA) Ior connecting serial devices. In other words, RS-232 is a long
established standard that describes the physical interIace and protocol Ior relatively low-
speed serial data communication between computers and related devices. An industry trade
group, the Electronic Industries Association (EIA), deIined it original Ior teletypewriter
devices. In 1987, the EIA released a new version oI the standard and change the name to
EIA-232-D. Many people, however, still reIer to the standard as RS 232C, or just RS-232.
RS-232 is the interIace that your computer uses to talk to and exchange data with your
modem and other serial devices. The serial ports on most computers use a subset oI the RS-
232C standard.

2.5.6 RS232 on DB9 (9-pin D-type connector)

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There is a standardized pinout Ior RS-232 on a DB9 connector, as shown below


Table 2.5.6:pinout Ior RS-232


2.5.7 RS232 on RJ-45

RJ-45 (Registered Jack-45) is an eight-wire connector used commonly to connect computers
onto local-area networks (LAN), especially Ethernets. In other words, RJ-45 is a single-line
jack Ior digital transmission over ordinary phone wire, either untwisted or twisted. The
interIace has eight pins or positions. For Iaster transmissions in which you're connecting to
an Ethernet 10BASET network, you need to use twisted pair wire. RS232D, EIA/TIA - 561
standard is applied when connecting to or Irom a serial port with a 8 position Modular Jack
(RJ45) though it is not widely used as such.



Figure 2.5.7.1: RJ-45 connector
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Table 2.5.7.2: Rs232 standard
2.5.8 Signal Description

TxD: - This pin carries data Irom the computer to the serial device
RXD: - This pin carries data Irom the serial device to the computer
DTR signals: - DTR is used by the computer to signal that it is ready to communicate
with the serial device like modem. In other words, DTR indicates to the Dataset (i.e.,
the modem or DSU/CSU) that the DTE (computer) is ON.
DSR: - Similarly to DTR, Data set ready (DSR) is an indication Irom the Dataset that
it is ON.
DCD: - Data Carrier Detect (DCD) indicates that carrier Ior the transmit data is ON.
RTS: - This pin is used to request clearance to send data to a modem
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CTS: - This pin is used by the serial device to acknowledge the computer's RTS
Signal. In most situations, RTS and CTS are constantly on throughout the
communication session.
Clock signals (TC, RC, and XTC): - The clock signals are only used Ior
synchronouscommunications. The modem or DSU extracts the clock Irom the data
stream and provides asteady clock signal to the DTE.
Note that the transmit and receive clock signals do not have to be the same, or
even at the same baud rate.
CD: - CD stands Ior Carrier Detect. Carrier Detect is used by a modem to signal that
it has amade a connection with another modem, or has detected a carrier tone. In
other words, this issued by the modem to signal that a carrier signal has been received
Irom a remote modem.
RI: - RI stands Ior Ring Indicator. A modem toggles(keystroke) the state oI this line
when anincoming call rings your phone. In other words, this is used by an auto
answer modem to signalthe receipt oI a telephone ring signal
The Carrier Detect (CD) and the Ring Indicator (RI) lines are only available in
connections to amodem. Because most modems transmit status inIormation to a PC
when either a carrier signalis detected (i.e. when a connection is made to another
modem) or when the line is ringing, thesetwo lines are rarely used.

2.5.9 Limitations oI RS-232
RS-232 has some serious shortcomings as an electrical interIace.
Firstly, the interIace presupposes a common ground between the DTE and DCE. This is a
reasonable assumption where a short cable connects a DTE and DCE in the same room, but
with longer lines and connections between devices that may be on diIIerent electrical busses,
this may not be true. We have seen some spectacular electrical events causes by "uncommon
grounds".

Secondly, a signal on a single line is impossible to screen eIIectively Ior noise.
Byscreening the entire cable one can reduce the inIluence oI outside noise, but internally
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generated noise remains a problem. As the baud rate and line length increase, the eIIect oI
capacitance between the cables introduces serious crosstalk until a point is reached where the
data itselI is unreadable.

Using low capacitance cable can reduce crosstalk. Also, as it is the higher Irequencies
that are the problem, control oI slew rate in the signal (i.e., making the signal more rounded,
rather than square) also decreases the crosstalk. The original speciIications Ior RS-232 had
no speciIication Ior maximum slew rate.

Voltage levels with respect to ground represent the RS 232 signals. There is a wire Ior
each signal, together with the ground signal (reIerence Ior voltage levels). This interIace is
useIul Ior point-to-point communication at slow speeds. For example, port COM1 in a PC
can be used Ior a mouse, port COM2 Ior a modem, etc. This is an example oI point-to-point
communication: one port, one device. Due to the way the signals are connected, a common
ground is required. This implies limited cable length - about 30 to 60 meters maximum.
(Main problems are interIerence and resistance oI the cable.) Shortly, RS 232 was designed
Ior communication oI local devices, and supports one transmitter and one receiver.

2.6 InterIacing a 4x4 Keyboard to an AT91 Microcontroller
2.6.1 Introduction

This Application Note describes programming techniques implemented on the AT91 ARM-
based microcontroller Ior scanning a 4x4 Keyboard matrix usually Iound in both consumer
and industrial applications Ior numeric data entry.

2.6.2 Keyboard interIace

In this application, a 4x4 matrix keypad requiring eight Input/Output ports Ior interIacing is
used as an example. Rows are connected to Peripheral Input/Output (PIO) pins conIigured as
output. Columns are connected to PIO pins conIigured as input with interrupts. In this
conIiguration, Iour pull-up resistors must be added in order to apply a high level on the
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corresponding input pins as shown in Figure 1. The corresponding hexadecimal value oI the
pressed key is sent on Iour LEDs.




Figure 2.6.2.1: I/O conIiguration oI keyboard
2.6.2.1 I/O conIiguration
Rows are connected to Iour PIO pins conIigured as outputs. Columns are connected to Iour
PIO pins conIigured as inputs with interrupts. The idle state oI these pins is high level due to
Iour pull-up resistors. PIO interrupt is generated by a low level applied to these pins (caused
by a key pressed). Four additional PIO pins are conIigured as outputs to send the value oI the
pressed key to LEDS.
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2.6.2.2 Timer Counter ConIiguration

The Timer Counter is conIigured in waveIorm operating mode with RC compare interrupt.
The Timer Counter is initialized to be incremented on internal clock cycles. The debouncing
time is programmable by initializing the RC compare register value according to the clock
source selected. A soItware trigger is used to reset the timer counter and start the counter
clock.

2.6.2.3 Interrupt

When a key is pressed, a low level is applied to the pin corresponding to the column
associated to the key (pins conIigured as inputs with interrupts). A Ialling edge applied to a
column pin creates a PIO interrupt. Then, the processor executes the PIO interrupt subroutine
(debouncing) and comes back to its previous state (in the main program). AIter debouncing
time, a RC compare timer interrupt occurs and the processor then executes the timer interrupt
subroutine (decoding the pressed key) and comes back to its previous state (in the main
program).

2.6.2.4 Keyboard Scan

The Keyboard used is a 4x4 matrixes Keyboard. Columns are connected to pins conIigured
as inputsand having the input change interrupt enabled. The initial state oI these pins is high
level due to Iour external pull-up resistors. The state machine is initialized to start with Iast
scan which outputs zeroes to all rowsand detects all keys at the same time. When a key is
pressed, a low level is applied to the corresponding column and causes a PIO interrupt to
detect the Iirst edge. Once any key is detected, debouncing is started. The attempt to press a
key on a physical keypad and have this activity detected can Iail as a result oI several noise
sources, glitches, spikes, etc., to mention some oI the possible causes oI de bounce problems.
The timer is used to eliminate all noise oI less than a Iew milliseconds. Normally this is
dependent on the mechanical characteristics oI the keys. In this application example, a 20ms
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programmable de bouncing time is used. AIter debouncing is completed, a detailed scan is
executed. A second Iast scan is done to assure that any detection made during the Iirst Iast
scan stage was not just noise. Then, rows are conIigured as inputs. When a key is pressed a
high level is applied in the corresponding row.



Figure 2.6.2.4: eyboard Scan Method










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3. Functional description
3.1 Architectural overview
The ARM7TDMI-S is a general purpose 32-bit microprocessor, which oIIers high
perIormance and very low power consumption. The ARM architecture is based on
Reduced Instruction Set Computer (RISC) principles, and the instruction set and related
decode mechanism are much simpler than those oI microprogrammed Complex
Instruction Set Computers (CISC). This simplicity results in a high instruction throughput
and impressive real-time interrupt response Irom a small and cost-eIIective processor
core.
Pipeline techniques are employed so that all parts oI the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being Ietched Irom memory.
The ARM7TDMI-S processor also employs a unique architectural strategy known as
Thumb, which makes it ideally suited to high-volume applications with memory
restrictions, or applications where code density is an issue.
The key idea behind Thumb is that oI a super-reduced instruction set. Essentially, the
ARM7TDMI-S processor has two instruction sets:
The standard 32-bit ARM set.
A 16-bit Thumb set.
The Thumb set`s 16-bit instruction length allows it to approach twice the density oI
standard ARM code while retaining most oI the ARM`s perIormance advantage over a
traditional 16-bit processor using 16-bit registers. This is possible because Thumb code
operates on the same 32-bit register set as ARM code.
Thumb code is able to provide up to 65 oI the code size oI ARM, and 160 oI the
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perIormance oI an equivalent ARM processor connected to a 16-bit memory system.
The particular Ilash implementation in the LPC2141/42/44/46/48 allows Ior Iull speed
execution also in ARM mode. It is recommended to program perIormance critical and
short code sections (such as interrupt service routines and DSP algorithms) in ARM
mode. The impact on the overall code size will be minimal but the speed can be increased
by 30 over Thumb mode.

3.2 On-chip flash program memory
The LPC2141/42/44/46/48 incorporate a 32 kB, 64 kB, 128 kB, 256 kB and 512 kB Ilash
memory system respectively. This memory may be used Ior both code and data storage.
Programming oI the Ilash memory may be accomplished in several ways. It may be
programmed In System via the serial port. The application program may also erase and/or
program the Ilash while the application is running, allowing a great degree oI Ilexibility Ior
data storage Iield Iirmware upgrades, etc. Due to the architectural solution chosen Ior an
on-chip boot loader, Ilash memory available Ior user`s code on LPC2141/42/44/46/48 is
32 kB

3.3 On-chip static RAM
On-chip static RAM may be used Ior code and/or data storage. The SRAM may be
accessed as 8-bit, 16-bit, and 32-bit. The LPC2141, LPC2142/44 and LPC2146/48
provide 8 kB, 16 kB and 32 kB oI static RAM respectively.
In case oI LPC2146/48 only, an 8 kB SRAM block intended to be utilized mainly by the
USB can also be used as a general purpose RAM
3.4 Interrupt controller
The Vectored Interrupt Controller (VIC) accepts all oI the interrupt request inputs and
categorizes them as Fast Interrupt Request (FIQ), vectored Interrupt Request (IRQ), and
non-vectored IRQ as deIined by programmable settings. The programmable assignment
scheme means that priorities oI interrupts Irom the various peripherals can be dynamically
assigned and adjusted.
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Fast interrupt request (FIQ) has the highest priority. II more than one request is assigned
to FIQ, the VIC combines the requests to produce the FIQ signal to the ARM processor.
The Iastest possible FIQ latency is achieved when only one request is classiIied as FIQ,
because then the FIQ service routine does not need to branch into the interrupt service
routine but can run Irom the interrupt vector location. II more than one request is assigned
to the FIQ class, the FIQ service routine will read a word Irom the VIC that identiIies which
FIQ source(s) is (are) requesting an interrupt.
Vectored IRQs have the middle priority. Sixteen oI the interrupt requests can be assigned
to this category. Any oI the interrupt requests can be assigned to any oI the 16 vectored
IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest.
Non-vectored IRQs have the lowest priority.
The VIC combines the requests Irom all the vectored and non-vectored IRQs to produce
the IRQ signal to the ARM processor. The IRQ service routine can start by reading a
register Irom the VIC and jumping there. II any oI the vectored IRQs are pending, the VIC
provides the address oI the highest-priority requesting IRQs service routine, otherwise it
provides the address oI a deIault routine that is shared by all the non-vectored IRQs. The
deIault routine can read another VIC register to see what IRQs are active.
3.4.1 Interrupt sources
Each peripheral device has one interrupt line connected to the Vectored Interrupt
Controller, but may have several internal interrupt Ilags. Individual interrupt Ilags may also
represent more than one interrupt source.
3.5 Pin connect block
The pin connect block allows selected pins oI the microcontroller to have more than one
Iunction. ConIiguration registers control the multiplexers to allow connection between the
pin and the on chip peripherals. Peripherals should be connected to the appropriate pins
prior to being activated, and prior to any related interrupt(s) being enabled. Activity oI any
enabled peripheral Iunction that is not mapped to a related pin should be considered
undeIined.
The Pin Control Module with its pin select registers deIines the Iunctionality oI the
microcontroller in a given hardware environment.
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AIter reset all pins oI Port 0 and Port 1 are conIigured as input with the Iollowing
exceptions: II debug is enabled, the JTAG pins will assume their JTAG Iunctionality; iI
trace is enabled, the Trace pins will assume their trace Iunctionality. The pins associated
with the I2C0 and I2C1 interIace are open drain.
3.6 Fast general purpose parallel I/O
Device pins that are not connected to a speciIic peripheral Iunction are controlled by the
GPIO registers. Pins may be dynamically conIigured as inputs or outputs. Separate
registers allow setting or clearing any number oI outputs simultaneously. The value oI the
output register may be read back, as well as the current state oI the port pins.
LPC2141/42/44/46/48 introduce accelerated GPIO Iunctions over prior LPC2000 devices:
GPIO registers are relocated to the ARM local bus Ior the Iastest possible I/O timing.
Mask registers allow treating sets oI port bits as a group, leaving other bits
unchanged.
All GPIO registers are byte addressable.
Entire port value can be written in one instruction.
3.6.1 Features
Bit-level set and clear registers allow a single instruction set or clear oI any number oI
bits in one port.
Direction control oI individual bits.
Separate control oI output set and clear.
All I/O deIault to inputs aIter reset.
3.7 10-bit ADC
The LPC2141/42 contain one and the LPC2144/46/48 contain two analog to digital
converters. These converters are single 10-bit successive approximation analog to digital
converters. While ADC0 has six channels, ADC1 has eight channels. ThereIore, total
number oI available ADC inputs Ior LPC2141/42 is 6 and Ior LPC2144/46/48 is 14.
3.7.1 Features
10 bit successive approximation analog to digital converter.
Measurement range oI 0 V to VREF (2.0 V VREF VDDA).
Each converter capable oI perIorming more than 400,000 10-bit samples per second.
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Every analog input has a dedicated result register to reduce interrupt overhead.
Burst conversion mode Ior single or multiple inputs.
Optional conversion on transition on input pin or timer match signal.
Global Start command Ior both converters (LPC2142/44/46/48 only).
3.8 10-bit DAC
The DAC enables the LPC2141/42/44/46/48 to generate a variable analog output. The
maximum DAC output voltage is the VREF voltage.
3.8.1 Features
10-bit DAC.
BuIIered output.
Power-down mode available.
3.9 USB 2.0 device controller
The USB is a 4-wire serial bus that supports communication between a host and a
number (127 max) oI peripherals. The host controller allocates the USB bandwidth to
attached devices through a token based protocol. The bus supports hot plugging,
unplugging, and dynamic conIiguration oI the devices. All transactions are initiated by the
host controller.
The LPC2141/42/44/46/48 is equipped with a USB device controller that enables
12 Mbit/s data exchange with a USB host controller. It consists oI a register interIace,
serial interIace engine, endpoint buIIer memory and DMA controller. The serial interIace
engine decodes the USB data stream and writes data to the appropriate end point buIIer
memory. The status oI a completed USB transIer or error condition is indicated via status
registers. An interrupt is also generated iI enabled.
A DMA controller (available in LPC2146/48 only) can transIer data between an endpoint
buIIer and the USB RAM.
3.9.1 Features
Fully compliant with USB 2.0 Full-speed speciIication.
Supports 32 physical (16 logical) endpoints.
Supports control, bulk, interrupt and isochronous endpoints.
Scalable realization oI endpoints at run time.
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Endpoint maximum packet size selection (up to USB maximum speciIication) by
soItware at run time.
RAM message buIIer size based on endpoint realization and maximum packet size.
Supports SoItConnect and GoodLink LED indicator. These two Iunctions are sharing
one pin.
Supports bus-powered capability with low suspend current.
Supports DMA transIer on all non-control endpoints (LPC2146/48 only).
One duplex DMA channel serves all endpoints (LPC2146/48 only).
Allows dynamic switching between CPU controlled and DMA modes (only in
LPC2146/48).
Double buIIer implementation Ior bulk and isochronous endpoints.
3.10 UARTs
The LPC2141/42/44/46/48 each contain two UARTs. In addition to standard transmit and
receive data lines, the LPC2144/46/48 UART1 also provides a Iull modem control
handshake interIace.
Compared to previous LPC2000 microcontrollers, UARTs in LPC2141/42/44/46/48
introduce a Iractional baud rate generator Ior both UARTs, enabling these microcontrollers
to achieve standard baud rates such as 115200 with any crystal Irequency above 2 MHz.
In addition, auto-CTS/RTS Ilow-control Iunctions are Iully implemented in hardware
(UART1 in LPC2144/46/48 only).
3.10.1 Features
16 byte Receive and Transmit FIFOs.
Register locations conIorm to 550 industry standard.
Receiver FIFO trigger points at 1, 4, 8, and 14 bytes
Built-in Iractional baud rate generator covering wide range oI baud rates without a
need Ior external crystals oI particular values.
Transmission FIFO control enables implementation oI soItware (XON/XOFF) Ilow
control on both UARTs.
LPC2144/46/48 UART1 equipped with standard modem interIace signals. This
module also provides Iull support Ior hardware Ilow control (auto-CTS/RTS).
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3.11 I2C-bus serial I/O controller
The LPC2141/42/44/46/48 each contain two I2C-bus controllers.
The I2C-bus is bidirectional, Ior inter-IC control using only two wires: a serial clock line
(SCL), and a serial data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver or a transmitter with the
capability to both receive and send inIormation (such as memory)). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transIer or is only addressed. The I2C-bus is a multi-master bus, it can be
controlled by more than one bus master connected to it.
The I2C-bus implemented in LPC2141/42/44/46/48 supports bit rates up to 400 kbit/s
(Fast I2C-bus).

3.11.1 Features
Compliant with standard I2C-bus interIace.
Easy to conIigure as master, slave, or master/slave.
Programmable clocks allow versatile rate control.
Bidirectional data transIer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption oI serial
data on the bus.
Serial clock synchronization allows devices with diIIerent bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transIer.
The I2C-bus can be used Ior test and diagnostic purposes.
3.12 SPI serial I/O controller
The LPC2141/42/44/46/48 each contain one SPI controller. The SPI is a Iull duplex serial
interIace, designed to handle multiple masters and slaves connected to a given bus. Only
a single master and a single slave can communicate on the interIace during a given data
transIer. During a data transIer the master always sends a byte oI data to the slave, and
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the slave always sends a byte oI data to the master.

3.12.1 Features
Compliant with SPI speciIication.
Synchronous, Serial, Full Duplex, Communication.
Combined SPI master and slave.
Maximum data bit rate oI one eighth oI the input clock rate.
3.13 SSP serial I/O controller
The LPC2141/42/44/46/48 each contain one SSP. The SSP controller is capable oI
operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and
slaves on the bus. However, only a single master and a single slave can communicate on
the bus during a given data transIer. The SSP supports Iull duplex transIers, with data
Irames oI 4 bits to 16 bits oI data Ilowing Irom the master to the slave and Irom the slave
to the master. OIten only one oI these data Ilows carries meaningIul data.
3.13.1 Features
Compatible with Motorola`s SPI, TI`s 4-wire SSI and National Semiconductor`s
Microwire buses.
Synchronous serial communication.
Master or slave operation.
8-Irame FIFOs Ior both transmit and receive.
Four bits to 16 bits per Irame.
3.14 General purpose timers/external event counters
The Timer/Counter is designed to count cycles oI the peripheral clock (PCLK) or an
externally supplied clock and optionally generate interrupts or perIorm other actions at
speciIied timer values, based on Iour match registers. It also includes Iour capture inputs
to trap the timer value when an input signal transitions, optionally generating an interrupt.
Multiple pins can be selected to perIorm a single capture or match Iunction, providing an
application with or` and and`, as well as broadcast` Iunctions among them.
The LPC2141/42/44/46/48 can count external events on one oI the capture inputs iI the
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minimum external pulse is equal or longer than a period oI the PCLK. In this conIiguration,
unused capture lines can be selected as regular timer capture inputs, or used as external
interrupts.
3.14.1 Features
A 32-bit timer/counter with a programmable 32-bit prescaler.
External event counter or timer operation.
Four 32-bit capture channels per timer/counter that can take a snapshot oI the timer
value when an input signal transitions. A capture event may also optionally generate
an interrupt.
Four 32-bit match registers that allow:
- Continuous operation with optional interrupt generation on match.
- Stop timer on match with optional interrupt generation.
- Reset timer on match with optional interrupt generation.
Four external outputs per timer/counter corresponding to match registers, with the
Iollowing capabilities:
- Set LOW on match.
- Set HIGH on match.
- Toggle on match.
- Do nothing on match.
3.15 Watchdog timer
The purpose oI the watchdog is to reset the microcontroller within a reasonable amount oI
time iI it enters an erroneous state. When enabled, the watchdog will generate a system
reset iI the user program Iails to Ieed` (or reload) the watchdog within a predetermined
amount oI time.
3.15.1 Features
Internally resets chip iI not periodically reloaded.
Debug mode.
Enabled by soItware but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
Incorrect/Incomplete Ieed sequence causes reset/interrupt iI enabled.
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Flag to indicate watchdog reset.
Programmable 32-bit timer with internal pre-scaler.
Selectable time period Irom (TPCLK 256 4) to (TPCLK 232 4) in multiples oI
TPCLK 4.
3.16 Real-time clock
The RTC is designed to provide a set oI counters to measure time when normal or idle
operating mode is selected. The RTC has been designed to use little power, making it
suitable Ior battery powered systems where the CPU is not running continuously (Idle
mode).
3.16.1 Features
Measures the passage oI time to maintain a calendar and clock.
Ultra-low power design to support battery powered systems.
Provides Seconds, Minutes, Hours, Day oI Month, Month, Year, Day oIWeek, and Day
oI Year.
Can use either the RTC dedicated 32 kHz oscillator input or clock derived Irom the
external crystal/oscillator input at XTAL1. Programmable reIerence clock divider
allows Iine adjustment oI the RTC.
Dedicated power supply pin can be connected to a battery or the main 3.3 V.
3.17 Pulse width modulator
The PWM is based on the standard timer block and inherits all oI its Ieatures, although
only the PWM Iunction is pinned out on the LPC2141/42/44/46/48. The timer is designed
to count cycles oI the peripheral clock (PCLK) and optionally generate interrupts or
perIorm other actions when speciIied timer values occur, based on seven match registers.
The PWM Iunction is also based on match register events.
The ability to separately control rising and Ialling edge locations allows the PWM to be
used Ior more applications. For instance, multi-phase motor control typically requires three
non-overlapping PWM outputs with individual control oI all three pulse widths and
positions.
Two match registers can be used to provide a single edge controlled PWM output. One
match register (MR0) controls the PWM cycle rate, by resetting the count upon match.
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The other match register controls the PWM edge position. Additional single edge
controlled PWM outputs require only one match register each, since the repetition rate is
the same Ior all PWM outputs. Multiple single edge controlled PWM outputs will all have a
rising edge at the beginning oI each PWM cycle, when an MR0 match occurs.
Three match registers can be used to provide a PWM output with both edges controlled.
Again, the MR0 match register controls the PWM cycle rate. The other match registers
control the two PWM edge positions. Additional double edge controlled PWM outputs
require only two match registers each, since the repetition rate is the same Ior all PWM
outputs.
With double edge controlled PWM outputs, speciIic match registers control the rising and
Ialling edge oI the output. This allows both positive going PWM pulses (when the rising
edge occurs prior to the Ialling edge), and negative going PWM pulses (when the Ialling
edge occurs prior to the rising edge).
3.17.1 Features
Seven match registers allow up to six single edge controlled or three double edge
controlled PWM outputs, or a mix oI both types.
The match registers also allow:
- Continuous operation with optional interrupt generation on match.
- Stop timer on match with optional interrupt generation.
- Reset timer on match with optional interrupt generation.
Supports single edge controlled and/or double edge controlled PWM outputs. Single
edge controlled PWM outputs all go HIGH at the beginning oI each cycle unless the
output is a constant LOW. Double edge controlled PWM outputs can have either edge
occur at any position within a cycle. This allows Ior both positive going and negative
going pulses.
Pulse period and width can be any number oI timer counts. This allows complete
Ilexibility in the trade-oII between resolution and repetition rate. All PWM outputs will
occur at the same repetition rate.
Double edge controlled PWM
Match register updates are synchronized with pulse outputs to prevent generation oI
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erroneous pulses. SoItware must release` new match values beIore they can become
eIIective.
May be used as a standard timer iI the PWM mode is not enabled.
A 32-bit Timer/Counter with a programmable 32-bit Pre scalar.
3.18 System control
3.18.1 Crystal oscillator
On-chip integrated oscillator operates with external crystal in range oI 1 MHz to 25 MHz.
The oscillator output Irequency is called Iosc and the ARM processor clock Irequency is
reIerred to as CCLK Ior purposes oI rate equations, etc. Iosc and CCLK are the same value
unless the PLL is running and connected.
3.18.2 PLL
The PLL accepts an input clock Irequency in the range oI 10 MHz to 25 MHz. The input
Irequency is multiplied up into the range oI 10 MHz to 60 MHz with a Current Controlled
Oscillator (CCO). The multiplier can be an integer value Irom 1 to 32 (in practice, the
multiplier value cannot be higher than 6 on this Iamily oI microcontrollers due to the upper
Irequency limit oI the CPU). The CCO operates in the range oI 156 MHz to 320 MHz, so
there is an additional divider in the loop to keep the CCO within its Irequency range while
the PLL is providing the desired output Irequency. The output divider may be set to divide
by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2,
it is insured that the PLL output has a 50 duty cycle. The PLL is turned oII and
bypassed Iollowing a chip reset and may be enabled by soItware. The program must
conIigure and activate the PLL, wait Ior the PLL to Lock, then connect to the PLL as a
clock source. The PLL settling time is 100 s.
3.18.3 Reset and wake-up timer
Reset has two sources on the LPC2141/42/44/46/48: the RESET pin and watchdog reset.
The RESET pin is a Schmitt trigger input pin with an additional glitch Iilter. Assertion oI
chip reset by any source starts the Wake-up Timer (see Wake-up Timer description
below), causing the internal chip reset to remain asserted until the external reset is
de-asserted, the oscillator is running, a Iixed number oI clocks have passed, and the
on-chip Ilash controller has completed its initialization.
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When the internal reset is removed, the processor begins executing at address 0, which is
the reset vector. At that point, all oI the processor and peripheral registers have been
initialized to predetermined values.
The Wake-up Timer ensures that the oscillator and other analog Iunctions required Ior
chip operation are Iully Iunctional beIore the processor is allowed to execute instructions.
This is important at power on, all types oI reset, and whenever any oI the aIorementioned
Iunctions are turned oII Ior any reason. Since the oscillator and other Iunctions are turned
oII during Power-down mode, any wake-up oI the processor Irom Power-down mode
makes use oI the Wake-up Timer.
The Wake-up Timer monitors the crystal oscillator as the means oI checking whether it is
saIe to begin code execution. When power is applied to the chip, or some event caused
the chip to exit Power-down mode, some time is required Ior the oscillator to produce a
signal oI suIIicient amplitude to drive the clock logic. The amount oI time depends on
many Iactors, including the rate oI VDD ramp (in the case oI power on), the type oI crystal
and its electrical characteristics (iI a quartz crystal is used), as well as any other external
circuitry (e.g. capacitors), and the characteristics oI the oscillator itselI under the existing
ambient conditions.
3.18.4 Brownout detector
The LPC2141/42/44/46/48 include 2-stage monitoring oI the voltage on the VDD pins. II
this voltage Ialls below 2.9 V, the BOD asserts an interrupt signal to the VIC. This signal
can be enabled Ior interrupt; iI not, soItware can monitor the signal by reading dedicated
register.
The second stage oI low voltage detection asserts reset to inactivate the
LPC2141/42/44/46/48 when the voltage on the VDD pins Ialls below 2.6 V. This reset
prevents alteration oI the Ilash as operation oI the various elements oI the chip would
otherwise become unreliable due to low voltage. The BOD circuit maintains this reset
down below 1 V, at which point the POR circuitry maintains the overall reset.
Both the 2.9 V and 2.6 V thresholds include some hysteresis. In normal operation, this
hysteresis allows the 2.9 V detection to reliably interrupt, or a regularly-executed event
loop to sense the condition.
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3.18.5 Code security
This Ieature oI the LPC2141/42/44/46/48 allow an application to control whether it can be
debugged or protected Irom observation.
II aIter reset on-chip boot loader detects a valid checksum in Ilash and reads 0x8765 4321
Irom address 0x1FC in Ilash, debugging will be disabled and thus the code in Ilash will be
protected Irom observation. Once debugging is disabled, it can be enabled only by
perIorming a Iull chip erase using the ISP.
3.18.6 External interrupt inputs
The LPC2141/42/44/46/48 include up to nine edge or level sensitive External Interrupt
Inputs as selectable pin Iunctions. When the pins are combined, external events can be
processed as Iour independent interrupt signals. The External Interrupt Inputs can
optionally be used to wake-up the processor Irom Power-down mode.
Additionally capture input pins can also be used as external interrupts without the option
to wake the device up Irom Power-down mode.
3.18.7 Memory mapping control
The Memory Mapping Control alters the mapping oI the interrupt vectors that appear
beginning at address 0x0000 0000. Vectors may be mapped to the bottom oI the on-chip
Ilash memory, or to the on-chip static RAM.
3.18.8 Power control
The LPC2141/42/44/46/48 supports two reduced power modes: Idle mode and
Power-down mode.
In Idle mode, execution oI instructions is suspended until either a reset or interrupt occurs.
Peripheral Iunctions continue operation during Idle mode and may generate interrupts to
cause the processor to resume execution. Idle mode eliminates power used by the
processor itselI, memory systems and related controllers, and internal buses.
In Power-down mode, the oscillator is shut down and the chip receives no internal clocks.
The processor state and registers, peripheral registers, and internal SRAM values are
preserved throughout Power-down mode and the logic levels oI chip output pins remain
static. The Power-down mode can be terminated and normal operation resumed by either
a reset or certain speciIic interrupts that are able to Iunction without clocks. Since all
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dynamic operation oI the chip is suspended, Power-down mode reduces chip power
consumption to nearly zero.
Selecting an external 32 kHz clock instead oI the PCLK as a clock-source Ior the on-chip
RTC will enable the microcontroller to have the RTC active during Power-down mode.
Power-down current is increased with RTC active. However, it is signiIicantly lower than in
Idle mode.
A Power Control Ior Peripherals Ieature allows individual peripherals to be turned oII iI
they are not needed in the application, resulting in additional power savings during active
and Idle mode.
3.18.9 VPB bus
The VPB divider determines the relationship between the processor clock (CCLK) and the
clock used by peripheral devices (PCLK). The VPB divider serves two purposes. The Iirst
is to provide peripherals with the desired PCLK via VPB bus so that they can operate at
the speed chosen Ior the ARM processor. In order to achieve this, the VPB bus may be
slowed down to 12 to 14 oI the processor clock rate. Because the VPB bus must work
properly at power-up (and its timing cannot be altered iI it does not work since the VPB
divider control registers reside on the VPB bus), the deIault condition at reset is Ior the
VPB bus to run at 14 oI the processor clock rate. The second purpose oI the VPB divider
is to allow power savings when an application does not require any peripherals to run at
the Iull processor rate. Because the VPB divider is connected to the PLL output, the PLL
remains active (iI it was running) during Idle mode.
3.19 Emulation and debugging
The LPC2141/42/44/46/48 support emulation and debugging via a JTAG serial port. A
trace port allows tracing program execution. Debugging and trace Iunctions are
multiplexed only with GPIOs on Port 1. This means that all communication, timer and
interIace peripherals residing on Port 0 are available during the development and
debugging phase as they are when the application is run in the embedded system itselI.
3.19.1 EmbeddedICE
Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging oI
the target system requires a host computer running the debugger soItware and an
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EmbeddedICE protocol convertor.EmbeddedICE protocol convertor converts the remote
debug protocol commands to the JTAG data needed to access the ARM core.
The ARM core has a Debug Communication Channel (DCC) Iunction built-in. The DCC
allows a program running on the target to communicate with the host debugger or another
separate host without stopping the program Ilow or even entering the debug state. The
DCC is accessed as a co-processor 14 by the program running on the ARM7TDMI-S
core. The DCC allows the JTAG port to be used Ior sending and receiving data without
aIIecting the normal program Ilow. The DCC data and control registers are mapped in to
addresses in the EmbeddedICE logic.
3.19.2 Embedded trace
Since the LPC2141/42/44/46/48 have signiIicant amounts oI on-chip memory, it is not
possible to determine how the processor core is operating simply by observing the
external pins. The Embedded Trace Macrocell (ETM) provides real-time trace capability
Ior deeply embedded processor cores. It outputs inIormation about processor execution to
the trace port.
The ETM is connected directly to the ARM core and not to the main AMBA system bus. It
compresses the trace inIormation and exports it through a narrow trace port. An external
trace port analyzer must capture the trace inIormation under soItware debugger control.
Instruction trace (or PC trace) shows the Ilow oI execution oI the processor and provides a
list oI all the instructions that were executed. Instruction trace is signiIicantly compressed
by only broadcasting branch addresses as well as a set oI status signals that indicate the
pipeline status on a cycle by cycle basis. Trace inIormation generation can be controlled
by selecting the trigger resource. Trigger resources include address comparators,
counters and sequencers. Since trace inIormation is compressed the soItware debugger
requires a static image oI the code being executed. SelI-modiIying code can not be traced
because oI this restriction.

3.19.3 RealMonitor
RealMonitor is a conIigurable soItware module, developed by ARM Inc., which enables
real-time debug. It is a lightweight debug monitor that runs in the background while users
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debug their Ioreground application. It communicates with the host using the DCC, which is
present in the EmbeddedICE logic. The LPC2141/42/44/46/48 contain a speciIic
conIiguration oI RealMonitor soItware programmed into the on-chip Ilash memory.

4. RF Module Operation
4.1. Serial Communications
The XBee/XBee-PRO OEM RF Modules interIace to a host device through a logic-level
asynchronous serial port. Through its serial port, the module can communicate with any logic
and voltage compatible UART; or through a level translator to any serial device (For
example: Through a Max- Stream proprietary RS-232 or USB interIace board).
4.1.1. UART Data Flow
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Figure 4.1.1.1(a):
System Data Flow Diagram in a UARTinterIaced environmentLowasserted signals dis
tinguished with horizontal line over signal name.
Serial Data
Data enters the module UART through the DI pin (pin 3) as an asynchronous serial signal.
The sig-nal should idle high when no data is being transmitted. Each data byte consists oI a
start bit (low), 8 data bits (least signiIicant bit Iirst) and a stop bit (high). The Iollowing
Iigure illustrates the serial bit pattern oI data passing through the module.

Figure 4.1.1.1(b): UART data packet 0x1F (decimal number 31) as transmitted
through the RF moduleExample Data Format is 8N1 (bits parity # oI stop bits
The module UART perIorms tasks, such as timing and parity checking, that are needed Ior
data communications. Serial communications depend on the two UARTs to be conIigured
with compatible settings (baud rate, parity, start bits, stop bits, data bits).

4.1.2. Transparent Operation
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Serial-to-RF PacketizationBy deIault, XBee/XBee-PRO RF Modules operate in
Transparent Mode. When operating in this mode, the modules act as a serial line replacement
- all UART data received through the DI pin is queued up Ior RF transmission. When RF
data is received, the data is sent out the DO pin.
Data is buIIered in the DI buIIer until one oI the Iollowing causes the data to be packetized
and transmitted:
1. No serial characters are received Ior the amount oI time determined by the RO (Packetiza-
tion Timeout) parameter. II RO 0, packetization begins when a character is received. 2. The
maximum number oI characters that will Iit in an RF packet (100) is received. 3. The
Command Mode Sequence (GT CC GT) is received. Any character buIIered in the DI
buIIer beIore the sequence is transmitted.
II the module cannot immediately transmit (Ior instance, iI it is already receiving RF data),
the serial data is stored in the DI BuIIer. The data is packetized and sent at any RO timeout or
when 100 bytes (maximum packet size) are received. II the DI buIIer becomes Iull, hardware
or soItware Ilow control must be implemented in order to prevent overIlow (loss oI data
between the host and module).
4.1.3. API Operation
API (Application Programming InterIace) Operation is an alternative to the deIault
Transparent Operation. The Irame-based API extends the level to which a host application
can interact with the networking capabilities oI the module. When in API mode, all data
entering and leaving the module is contained in Irames that deIine operations or events
within the module. Transmit Data Frames (received through the DI pin (pin 3)) include: RF
Transmit Data Frame Command Frame (equivalent to AT commands) Receive Data Frames
(sent out the DO pin (pin 2)) include: RF-received data Irame Command response Event
notiIications such as reset, associate, disassociate, etc. The API provides alternative means oI
conIiguring modules and routing data at the host application layer. A host application can
send data Irames to the module that contain address and payload inIormation instead oI using
command mode to modiIy addresses. The module will send data Irames to the application
containing status packets; as well as source, RSSI and payload inIormation Irom received
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data packets. The API operation option Iacilitates many operations such as the examples
cited below:
-~ Transmitting data to multiple destinations without entering Command Mode -~ Receive
success/Iailure status oI each transmitted RF packet -~ IdentiIy the source address oI each
received packet

4.1.4. Flow Control

Figure 4.1.4.1: Internal Data Flow Diagram

DI (Data In) Buffer
When serial data enters the RF module through the DI pin (pin 3), the data is stored in the DI
BuIIer until it can be processed. Hardware Flow Control (CTS). When the DI buIIer is 17
bytes away Irom being Iull; by deIault, the module de-asserts CTS (high) to signal to the host
device to stop sending data |reIer to D7 (DIO7 ConIiguration) parameter|. CTS is re-asserted
aIter the DI BuIIer has 34 bytes oI memory available. How to eliminate the need for flow
control:
1. Send messages that are smaller than the DI buIIer size. 2. InterIace at a lower baud rate
|BD (InterIace Data Rate) parameter| than the throughput data rate.
Case in which the DI Buffer may become full and possibly overflow:
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II the module is receiving a continuous stream oI RF data, any serial data that arrives on the
DI pin is placed in the DI BuIIer. The data in the DI buIIer will be transmitted over-the-air
when the module is no longer receiving RF data in the network.
ReIer to the RO (Packetization Timeout), BD (InterIace Data Rate) and D7 (DIO7
ConIiguration) command descriptions Ior more inIormation.
DO (Data Out) Buffer
When RF data is received, the data enters the DO buIIer and is sent out the serial port to a
host device. Once the DO BuIIer reaches capacity, any additional incoming RF data is lost.
Hardware Flow Control (RTS). II RTS is enabled Ior Ilow control (D6 (DIO6
ConIiguration) Parameter 1), data will not be sent out the DO BuIIer as long as RTS (pin
16) is de-asserted. Two cases in which the DO Buffer may become full and possibly
overflow:
1. II the RF data rate is set higher than the interIace data rate oI the module, the module will
receive data Irom the transmitting module Iaster than it can send the data to the host.
|2. II the host does not allow the module to transmit data out Irom the DO buIIer because oI
being held oII by hardware or soItware Ilow control.
4.2. ADC and Digital I/O Line Support
The XBee/XBee-PRO RF Modules support ADC (Analog-to-digital conversion) and digital
I/O line passing. The Iollowing pins support multiple Iunctions: To enable ADC and DIO pin
Iunctions:

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Table 4.2: Pin Iunctions and their associated pin numbers and commands
AD AnalogtoDigital Converter,
DIO Digital Input/Output
Pin Iunctions not applicable to this section are denoted within (parenthesis).
To enable ADC and DIO pin Iunctions:|
For ADC Support: Set ATDn 2
For Digital Input support: Set ATDn 3
For Digital Output Low support: Set ATDn 4
For Digital Output High support: Set ATDn 5

4.2.1. I/O Data Format
I/O data begins with a header. The Iirst byte oI the header deIines the number oI samples
Iorth-coming. A sample is comprised oI input data and the inputs can contain either DIO or
ADC. The last 2 bytes oI the header (Channel Indicator) deIine which inputs are active. Each
bit represents either a DIO line or ADC channel.

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Figure 4.2.1(a): Header
Sample data Iollows the header and the channel indicator Irame is used to determine how to
read the sample data. II any oI the DIO lines are enabled, the Iirst 2 bytes are the DIO data
and the ADC data Iollows. ADC channel data is stored as an unsigned 10-bit value right-
justiIied on a 16- bit boundary.

Figure 4.2.1(b):Sample Data
4.2.2. API Support
I/O data is sent out the UART using an API Irame. All other data can be sent and received
using Transparent Operation |reIer to p10| or API Iraming iI API mode is enabled (AP ~ 0).
API Operations support two RX (Receive) Irame identiIiers Ior I/O data: 0x82 Ior RX
(Receive) Packet: 64-bit address I/O 0x83 Ior RX (Receive) Packet: 16-bit address I/O The
API command header is the same as shown in the 'RX (Receive) Packet: 64-bit Address
and 'RX (Receive) Packet: 64-bit Address API types |reIer to p56|. RX data Iollows the
Iormat described in the I/O Data Format section |p12|. Applicable Commands: AP (API
Enable)
4.2.3. Sleep Support
When an RF module wakes, it will always do a sample based on any active ADC or DIO
lines. This allows sampling based on the sleep cycle whether it be Cyclic Sleep (SM
parameter 4 or 5) or Pin Sleep (SM 1 or 2). To gather more samples when awake, set the
IR (Sample Rate) parameter. For Cyclic Sleep modes: II the IR parameter is set, the module
will stay awake until the IT (Samples beIore TX) parameter is met. The module will stay
awake Ior ST (Time beIore Sleep) time. Applicable Commands: IR (Sample Rate), IT
(Samples beIore TX), SM (Sleep Mode), IC (DIO Change Detect)
4.2.4. DIO Pin Change Detect
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When 'DIO Change Detect is enabled (using the IC command), DIO lines 0-7 are
monitored. When a change is detected on a DIO line, the Iollowing will occur:
1. An RF packet is sent with the updated DIO pin levels. This packet will not contain any
ADC samples. 2. Any queued samples are transmitted beIore the change detect data. This
may result in receiving a packet with less than IT (Samples beIore TX) samples.
Note: Change detect will not aIIect Pin Sleep wake-up. The D8 pin (DTR/Sleep RQ/DI8) is
the only line that will wake a module Irom Pin Sleep. II not all samples are collected, the
module will still enter Sleep Mode aIter a change detect packet is sent. Applicable
Commands: IC (DIO Change Detect), IT (Samples beIore TX)
4.2.5. Sample Rate (Interval)
The Sample Rate (Interval) Ieature allows enabled ADC and DIO pins to be read periodically
on modules that are not conIigured to operate in Sleep Mode. When one oI the Sleep Modes
is enabled and the IR (Sample Rate) parameter set, the module will stay awake until IT
(Samples beIore TX) samples have been collected. Once a particular pin is enabled, the
appropriate sample rate must be chosen. The maximum sample rate that can be achieved
while using one A/D line is 1 sample/ms or 1 KHz (Note that the modem will not be able to
keep up with transmission when IR & IT are equal to '1). Applicable Commands: IR
(Sample Rate), IT (Samples beIore TX), SM (Sleep Mode)
4.2.6. I/O Line Passing
Virtual wires can be set up between XBee/XBee-PRO Modules. When an RF data packet is
received that contains I/O data, the receiving module can be setup to update any enabled
outputs (PWM and DIO) based on the data it receives. Note that I/O lines are mapped in
pairs. For example: AD0 can only update PWM0 and DI5 can only update DO5). The deIault
setup is Ior outputs not to be updated, which results in the I/O data being sent out the UART
(reIer to the IU (Enable I/O Output) command). To enable the outputs to be updated, the IA
(I/O Input Address) parameter must be setup with the address oI the module that has the
appropriate inputs enabled. This eIIectively binds the outputs to a particular module`s input.
This does not aIIect the ability oI the module to receive I/O line data Irom other modules -
only its ability to update enabled outputs. The IA parameter can also be setup to accept I/O
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data Ior output changes Irom any module by setting the IA parameter to 0xFFFF. When
outputs are changed Irom their non-active state, the module can be setup to return the out-put
level to it non-active state. The timers are set using the Tn (Dn Output Timer) and PT (PWM
Output Timeout) commands. The timers are reset every time a valid I/O packet (passed IA
check) is received. The IC (Change Detect) and IR (Sample Rate) parameters can be setup to
keep the output set to their active output iI the system needs more time than the timers can
handle.
Note: DI8 can not be used Ior I/O line passing.
Applicable Commands: IA (I/O Input Address), Tn (Dn Output Timeout), P0 (PWM0
ConIiguration), P1 (PWM1 ConIiguration), M0 (PWM0 Output Level), M1 (PWM1 Output
Level), PT (PWM Output Timeout), RP (RSSSI PWM Timer)
4.2.7. ConIiguration Example
As an example Ior a simple A/D link, a pair oI RF modules could be set as Iollows:

Table 4.2.7: ConIiguration Example
These settings conIigure the remote module to sample AD0 and AD1 once each every 20
ms.It then buIIers 5 samples each beIore sending them back to the base module. The base
should then receive a 32-Byte transmission (20 Bytes data and 12 Bytes Iraming) every 100
ms.
4.3. XBee/XBee-PRO Addressing
Every RF data packet sent over-the-air contains a Source Address and Destination Address
Iield in its header. The RF module conIorms to the 802.15.4 speciIication and supports both
short 16-bit addresses and long 64-bit addresses. A unique 64-bit IEEE source address is
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assigned at the Iac-tory and can be read with the SL (Serial Number Low) and SH (Serial
Number High) commands. Short addressing must be conIigured manually. A module will use
its unique 64-bit address as its Source Address iI its MY (16-bit Source Address) value is
'0xFFFF or '0xFFFE. To send a packet to a speciIic module using 64-bit addressing: Set
Destination Address (DL DH) to match the Source Address (SL SH) oI the intended
destination module. To send a packet to a speciIic module using 16-bit addressing: Set DL
(Destination Address Low) parameter to equal the MY parameter and set the DH
(Destination Address High) parameter to 0`.

4.3.1. Unicast Mode
By deIault, the RF module operates in Unicast Mode. Unicast Mode is the only mode that
supports retries. While in this mode, receiving modules send an ACK (acknowledgement) oI
RF packet reception to the transmitter. II the transmitting module does not receive the ACK,
it will re-send the packet up to three times or until the ACK is received. Short 16-bit
addresses. The module can be conIigured to use short 16-bit addresses as the Source
Address by setting (MY 0xFFFE). Setting the DH parameter (DH 0) will conIigure the
Destination Address to be a short 16-bit address (iI DL 0xFFFE). For two modules to
communicate using short addressing, the Destination Address oI the transmitter module must
match the MY parameter oI the receiver. The Iollowing table shows a sample network
conIiguration that would enable Unicast Mode communications using short 16-bit addresses.


Table 4.3.1: Sample Unicast Network ConIiguration (using 16 bit addressing)


Long 64-bit addresses. The RF module`s serial number (SL parameter concatenated to the
SH parameter) can be used as a 64-bit source address when the MY (16-bit Source Address)
parameter is disabled. When the MY parameter is disabled (set MY 0xFFFF or 0xFFFE),
the module`s source address is set to the 64-bit IEEE address stored in the SH and SL
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parameters. When an End Device associates to a Coordinator, its MY parameter is set to
0xFFFE to enable 64- bit addressing. The 64-bit address oI the module is stored as SH and
SL parameters. To send a packet to a speciIic module, the Destination Address (DL DH) on
one module must match the Source Address (SL SH) oI the other.
4.3.2. Broadcast Mode
Any RF module within range will accept a packet that contains a broadcast address. When
conIigured to operate in Broadcast Mode, receiving modules do not send ACKs
(Acknowledgements) and transmitting modules do not automatically re-send packets as is the
case in Unicast Mode. To send a broadcast packet to all modules regardless oI 16-bit or 64-
bit addressing, set the destination addresses oI all the modules as shown below.
Sample Network ConIiguration (All modules in the network):
DL (Destination Low Address) 0x0000FFFF
DH (Destination High Address) 0x00000000 (deIault value)
NOTE: When programming the module, parameters are entered in hexadecimal notation
(without the '0x preIix). Leading zeros may be omitted.
4.4 Modes of Operation
XBee/XBee-PRO RF Modules operate in Iive modes.


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Figure 4.4.1. Modes oI Operation



4.4.1. Idle Mode
When not receiving or transmitting data, the RF module is in Idle Mode. The module shiIts
into the other modes oI operation under the Iollowing conditions:
Transmit Mode (Serial data is received in the DI BuIIer)
Receive Mode (Valid RF data is received through the antenna)
Sleep Mode (Sleep Mode condition is met)
Command Mode (Command Mode Sequence is issued)
4.4.2. Transmit/Receive Modes
RF Data Packets
Each transmitted data packet contains a Source Address and Destination Address Iield. The
Source Address matches the address oI the transmitting module as speciIied by the MY
(Source Address) parameter (iI MY ~ 0xFFFE), the SH (Serial Number High) parameter or
the SL (Serial Number Low) parameter. The Destination Address~ Iield is created Irom the
DH (Destination Address High) and DL (Destination Address Low) parameter values. The
Source Address and/or Destination Address Iields will either contain a 16-bit short or long
64-bit long address. The RF data packet structure Iollows the 802.15.4 speciIication. |ReIer
to the XBee/XBee-PRO Addressing section Ior more inIormation|
Direct and Indirect Transmission
There are two methods to transmit data: Direct Transmission - data is transmitted
immediately to the Destination Address Indirect Transmission - A packet is retained Ior a
period oI time and is only transmitted aIter the destination module (Source Address
Destination Address) requests the data. Indirect Transmissions can only occur on a
Coordinator. Thus, iI all nodes in a network are End Devices, only Direct Transmissions will
occur. Indirect Transmissions are useIul to ensure packet delivery to a sleeping node. The
Coordinator currently is able to retain up to 2 indirect messages.
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Direct Transmission ANonBeaconing Coordinator can be conIigured to use only Direct
Transmission by setting the SP (Cyclic Sleep Period) parameter to '0. Also, a
NonBeaconing Coordinator using indirect transmissions will revert to direct transmission iI it
knows the destination module is awake. To enable this behavior, the ST (Time beIore Sleep)
value oI the Coordinator must be set to match the ST value oI the End Device. Once the End
Device either transmits data to the Coordinator or polls the Coordinator Ior data, the
Coordinator will use direct transmission Ior all subsequent data transmissions to that module
address until ST time (or number oI beacons) occurs with no activity (at which point it will
revert to using indirect transmissions Ior that module address). 'No activity means no
transmission or reception oI messages with a speciIic address. Global messages will not reset
the ST timer.
Indirect Transmission To conIigure Indirect Transmissions in a PAN (Personal Area
Network), the SP (Cyclic Sleep Period) parameter value on the Coordinator must be set to
match the longest sleep value oI any End Device. The SP parameter represents time in
NonBeacon systems and beacons in Beacon-enabled systems. The sleep period value on the
Coordinator determines how long (time or number oI beacons) the Coordinator will retain an
indirect message beIore discarding it. In NonBeacon networks, an End Device must poll the
Coordinator once it wakes Irom Sleep to determine iI the Coordinator has an indirect
message Ior it. For Cyclic Sleep Modes, this is done automatically every time the module
wakes (aIter SP time). For Pin Sleep Modes, the A1 (End Device Association) parameter
value must be set to enable Coordinator polling on pin wake-up. Alternatively, an End
Device can use the FP (Force Poll) command to poll the Coordinator as needed.



CCA (Clear Channel Assessment)
Acknowledgement Prior to transmitting a packet, a CCA (Clear Channel Assessment) is
perIormed on the channel to determine iI the channel is available Ior transmission. The
detected energy on the channel is com-pared with the CA (Clear Channel Assessment)
parameter value. II the detected energy exceeds the CA parameter value, the packet is not
transmitted. Also, a delay is inserted beIore a transmission takes place. This delay is settable
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using the RN (BackoII Exponent) parameter. II RN is set to '0, then there is no delay beIore
the Iirst CCA is per-Iormed. The RN parameter value is the equivalent oI the 'minBE
parameter in the 802.15.4 speciIication. The transmit sequence Iollows the 802.15.4
speciIication. By deIault, the MM (MAC Mode) parameter 0. On a CCA Iailure, the
module will attempt to re-send the packet up to two additional times. When in Unicast
packets with RR (Retries) 0, the module will execute two CCA retries. Broadcast packets
always get two CCA retries.
II the transmission is not a broadcast message, the module will expect to receive an
acknowledgement Irom the destination node. II an acknowledgement is not received, the
packet will be resent up to 3 more times.
II the acknowledgement is not received aIter all transmissions, an ACK Iailure is recorded.
4.4.3. Sleep Mode
Sleep Modes enable the RF module to enter states oI low-power consumption when not in
use. In order to enter Sleep Mode, one oI the Iollowing conditions must be met (in addition to
the module having a non-zero SM parameter value): SleepRQ (pin 9) is asserted. The
module is idle (no data transmission or reception) Ior the amount oI time deIined by the ST
(Time beIore Sleep) parameter. |NOTE: ST is only active when SM 4-5.|

Table 4.4.3(a): Sleep Mode ConIigurations
The SM command is central to setting Sleep Mode conIigurations. By deIault, Sleep Modes
are dis-abled (SM 0) and the module remains in Idle/Receive Mode. When in this state, the
module is constantly ready to respond to serial or RF activity. Higher Voltages.Sleep Mode
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current consumption is highly sensitive to voltage. Voltages above 3.0V will cause much
higher current consumption

Table 4.4.3(b): Sample Sleep Mode Currents

Pin/Host-controlled Sleep Modes
The transient current when waking Irom pin sleep (SM 1 or 2) does not exceed the idle
current oI the module. The current ramps up exponentially to its idle current. Pin Hibernate
(SM 1) Pin/Host-controlled Typical power-down current: 10 A (3.0 VCC)
Wake-up time: 13.2 msec Pin Hibernate Mode minimizes quiescent power (power consumed
when in a state oI rest or inac-tivity). This mode is voltage level-activated; when SleepRQ is
asserted, the module will Iinish any transmit, receive or association activities, enter Idle
Mode and then enter a state oI sleep. The module will not respond to either serial or RF
activity while in pin sleep. To wake a sleeping module operating in Pin Hibernate Mode, de-
assert SleepRQ (pin 9). The module will wake when SleepRQ is de-asserted and is ready
to transmit or receive when the CTS line is low. When waking the module, the pin must be
de-asserted at least two 'byte times aIter CTS goes low. This assures that there is time Ior
the data to enter the DI buIIer.
Pin Doze (SM 2) Pin/Host-controlled Typical power-down current: 50 A Wake-up
time: 2 msec Pin Doze Mode Iunctions as does Pin Hibernate Mode; however, Pin Doze
Ieatures Iaster wake-up time and higher power consumption. To wake a sleeping module
operating in Pin Doze Mode, de-assert SleepRQ (pin 9). The module will wake when
SleepRQ is de-asserted and is ready to transmit or receive when the CTS line is low. When
waking the module, the pin must be de-asserted at least two 'byte times' aIter CTS goes low.
This assures that there is time Ior the data to enter the DI buIIer.



Cyclic Sleep Modes
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Cyclic Sleep Remote (SM 4) Typical Power-down Current: 50 A (when asleep)
Wake-up time: 2 msec The Cyclic Sleep Modes allow modules to periodically check Ior RF
data. When the SM parameter is set to 4`, the module is conIigured to sleep, then wakes
once a cycle to check Ior data Irom a module conIigured as a Cyclic Sleep Coordinator (SM
0, CE 1). The Cyclic Sleep Remote sends a poll request to the coordinator at a speciIic
interval set by the SP (Cyclic Sleep Period) parameter. The coordinator will transmit any
queued data addressed to that speciIic remote upon receiving the poll request. II no data is
queued Ior the remote, the coordinator will not transmit and the remote will return to sleep
Ior another cycle. II queued data is transmitted back to the remote, it will stay awake to allow
Ior back and Iorth communication until the ST (Time beIore Sleep) timer expires. Also note
that CTS will go low each time the remote wakes, allowing Ior communication initiated by
the remote host iI desired.
Cyclic Sleep Remote with Pin Wake-up (SM 5) Use this mode to wake a sleeping remote
module through either the RF interIace or by the de-assertion oI SleepRQ Ior event-driven
communications. The cyclic sleep mode works as described above (Cyclic Sleep Remote)
with the addition oI a pin-controlled wake-up at the remote module. The SleepRQ pin is
edge-triggered, not level-triggered. The module will wake when a low is detected then set
CTS low as soon as it is ready to transmit or receive. Any activity will reset the ST (Time
beIore Sleep) timer so the module will go back to sleep only aIter there is no activity Ior the
duration oI the timer. Once the module wakes (pin-controlled), Iurther pin activity is ignored.
The module transitions back into sleep according to the ST time regardless oI the state oI the
pin.
Cyclic Sleep Coordinator (SM 6)] Typical current Receive current Always awake
NOTE: The SM6 parameter value exists solely Ior backwards compatibility with Iirmware
version 1.x60. II backwards compatibility with the older Iirmware version is not required,
always use the CE (Coordinator Enable) command to conIigure a module as a Coordinator.
This mode conIigures a module to wake cyclic sleeping remotes through RF interIacing. The
Coordinator will accept a message addressed to a speciIic remote 16 or 64-bit address and
hold it in a buIIer until the remote wakes and sends a poll request. Messages not sent directly
(buIIered and requested) are called "Indirect messages". The Coordinator only queues one
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indirect message at a time. The Coordinator will hold the indirect message Ior a period 2.5
times the sleeping period indicated by the SP (Cyclic Sleep Period) parameter. The
Coordinator's SP parameter should be set to match the value used by the remotes.
4.4.4. Command Mode
AT Command Mode To modiIy or read RF Module parameters, the module must Iirst enter
into Command Mode - a state in which incoming characters are interpreted as commands.
Two Command Mode options are supported: AT Command Mode |reIer to section below|
and API Command Mode |p52|.
To Enter AT Command Mode:
Send the 3-character command sequence ' and observe guard times beIore and aIter the
command characters. |ReIer to the 'DeIault AT Command Mode Sequence below.|
DeIault AT Command Mode Sequence (Ior transition to Command Mode): No characters
sent Ior one second |GT (Guard Times) parameter 0x3E8| Input three plus characters
(') within one second |CC (Command Sequence Character) parameter 0x2B.| No
characters sent Ior one second |GT (Guard Times) parameter 0x3E8| All oI the parameter
values in the sequence can be modiIied to reIlect user preIerences. NOTE: Failure to enter
AT Command Mode is most commonly due to baud rate mismatch. Ensure the Baud` setting
on the 'PC Settings tab matches the interIace data rate oI the RF module. By deIault, the
BD parameter 3 (9600 bps). To Send AT Commands:
Send AT commands and parameters using the syntax shown below.

Figure 4.4.4.1: Syntax Ior sending AT Commands
To read a parameter value stored in the RF module`s register, omit the parameter Iield. The
preceding example would change the RF module Destination Address (Low) to '0x1F. To
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store the new value to non-volatile (long term) memory, subsequently send the WR (Write)
command. For modiIied parameter values to persist in the module`s registry aIter a reset,
changes must be saved to non-volatile memory using the WR (Write) Command. Otherwise,
parameters are restored to previously saved values aIter the module is reset. System
Response.When a command is sent to the module, the module will parse and execute the
command. Upon successIul execution oI a command, the module returns an 'OK message.
II execution oI a command results in an error, the module returns an 'ERROR message. To
Exit AT Command Mode:
1. Send the ATCN (Exit Command Mode) command (Iollowed by a carriage return). |OR| 2.
II no valid AT Commands are received within the time speciIied by CT (Command Mode
Timeout) Command, the RF module automatically returns to Idle Mode.














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Chapter 5. Schematic Representation
5.1 Transmitter


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5.2 Receiver
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Chapter 6. Flow of the System
6.1 Flow chart Ior LCD




Figure 6.1.1: Ilow oI the Lcd

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6.2 Flow chart Ior Keypad

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6.3 Flow chart oI complete System

Figure 6.3.1: Flow oI entire system

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6.4 Using the SoItware
Step-1.Open the code in MicrosoIt visual basic.

Figure 6.4.1: MicrosoIt visual basic window.
Step-2.Go to the run tab and select start with Iull compile.

Figure 6.4.2: code compilation window.
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7. RESULT
ZIGBEE WIRLESS VEEHICULAR INDENTIFICATION AND
AUTHENTICATION security based systems is a big break though in the security
Iield.
Minimize militant attacks like whatever had happened in the parliament, hotel Taj
and hotel Oberio.

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8. CONCLUSION

8.1 CONCLUSION
The proposed ZigBee technology based Wireless Vehicle identiIication and driver
authentication system satisIies the much needed requirement oI vehicle security.
Use oI ZigBee module ensures the system to be low cost and low power consumable
system.
User-Iriendly interIace and simple system setup.


8.2 Future Enhancement

OI course aIter 5years our model(project idea)will become obsolete .
AIter 5 years we can use our model with a small modiIication like at that time we will
use GSM concept in place oI ZIGBEE concept.
AIter small changes what we will do. we will installed module1 in any government
parking lot and module2 will installed inside the vehicle .
Now when the vehicle enter at the entrance it will identiIied by the ZIGBEE
transceiver installed at the gate.
AIter that the GSM based system at the gate asks the driver to enter the password and
this password is also veriIied by the system at the entrance gate.
Now once both the vehicle identiIication is and the driver authentication has been
done then the inIormation is being sent by the system to the security guard at the gate.
According to this inIormation the guard will allows or denies access to the vehicle
inside the premises.