70 Digital Signal Processors

Ik: Long Constant

0IkS65535
ind:{**+ * *0+ *0-*BR0+ *BR0-}
that refer to memory, I/O ports, register
Operands can be assembly-time expressions
constants or
of other constants.
addresses, pointers, shift counts and a variety
The complete list of the mnemonics of the various instructions supported by 5X and a brief descrin
tion of each of these instructions are given in Appendix A4. More detailed explanation of these instruc.
tions with examples is given in the TMS30C5X user reference manual. In this chapter, in Section 42
the various addressing modes supported by C5X are discussed. In Sections 4.3-4.5 some of the most
commonly used C5X instructions are explained individually with examples. In chapter 6 application
programs which make use of the instructions explained in the above sections are presented.

4.2 ADDRESSING MODES

C5X processors can address 64K words of program memory and 96K words of data memory. C5Xx
supports the following six addressing modes:
Direct addressing
Memory-mapped register addressing
Indirect addressing
Immediate addressing
Dedicated-register addressing
Circular addressing
The details of each of these
addressing modes are considered next.
4.2.1 Direct Addressing
The data memory used with C5X
processors is split into 512 pages each of 128 words
memory page pointer (DP) in ST 0 holds the address of
the current data
long. The data
addressing mode of C5X, only lower-order 7 bits of the address are memory page. In the direct
9
upper bits are taken from the DP as
shown in specified in the instruction. The
Fig. 4.1.
DP(9) Instruction Register (16)

9 MSBs
15 7 LSBs
6

DP
Direct Memory Address
Fig. 4.1 16-bit data
memory address bus (DAB)
4.2.2
The RAM
Memory-Mapped Register Addressing
area in
page 0 is used for
These locations can be storing some of the
ARO can either be accessed by registers, interrupt vector addresses and
specifying the actual
denoted by the actual address or by the so on.
symbol ARO). Since these memory location (16h) used register name. (e.g., the
registers memory locations for storing its value or by the
correspondingto page 0 are
can be
referTed to as interchangeably
used with the
register names, the
memory-mapped registers (MMRs).
 TMS320C5X Assembly Language Instructions
With memory-mapPed registCr addressing, the
MMRs can be modified
pointer
data page
also be modified. value.
In without 'affecting the cur-
rent addition, any scratch
Ihe pad RAM (DARAM B2) location
mode, except that the memory-mapped
data page0
or
9 MSBs of register addressing mode
the address are operates like the direct address
ents f the DP. This allows the forced to 0 instead of
being loaded with the
thout the overhead of changing the memory-mapped
DP registers of data page 0 to be
modified directiy
emory-mapped register auxiliary register. The following instructions
or

the DP:
addressing mode. Using these instructions does operate in
the
not affect the contents or
LAMM-Load accumulator with memory-mapped
LMMR-Load memory-mapped register register
SAMM-Store accumulator memory-mapped
in

SMMR-Store memory-mapped register register

Example 4.1 The instruction LMMR ARO, #1500h

1500h as shown in Fig. 4.2. Let the loads ofAR0 with the content of the location
content ARO and the data memory location
1500h be 2345h and 6789h, respectively,
executing before executing the instruction.
the instruetion their contents After
become 6789h and 6789h.
Before execution of LMMR ARO, # 1500 h after
execution.
Data mem.
1500 h 6789 h Data mem.
1500 h 6789 h

ARO
2345 h ARO
6789 h

Fig.4.2 Memory-mapped register addressing example 4.1

Before execution of SMMR ARO, # 1500h After execution.

Data mem. Data mem.

1500 h 6789 h 2345 h
1500 h

ARO 2345 h ARO 2345 h

Fig. 4.3 Memory-mapped register addressing example 4.2

The SMMR does the reverse operation.

Example 4.2 Let the content of ARO and the data memory location be 2345h and 6789h, respec
tively, before executing the instniction SMMR ARO, # 1500h. After executing the
instruction their contents become 2345h and 2345h as shown in Fig. 4.3
AMM *
loads lower 16 bits of ACC, i.e., ACCL from the location
f the current AR. The higher 16 bits ACCH is filled with 0.
pointed by the lower-order 7 bius
 72 Digital Signal Pocexsors
2h and
ARR ACC, the valoe of dhta memorlocattons
Example 4.3 1et the content of instruction.
44, After exccution ol the LAMM
825hbe as sbown n pght hand colamn n Fig 44. can he a
o0 the
0Stor contents are asshown corresponds to
vahue in datasitemory locatoan 25h 1s loaded into A a to be
thatthe the higher bits of PAB are made
thefoweronder 7 bits of ARI and
MMRcorresponds to page After execution
LAMM"
Before execution of

ARP
ARP

AR1 325 h
AR1 325 h

Data mem. 6789 h

Data mem. 6789 h
825 h
825 h

Data mem.
Data mem. 8345 h
8345 h
25h 25h

2345 h ACC 8345 h

ACC

4.3
Fig. 4.4 Memory-mapped register addressing example

4.2.3 Immediate Addressing

The immediate addressing mode can be used to load either a 16-bit constant or a constant oflength 13
9or 7. Accordingly itis referred to as long immediate or short immediate addressing mode. This mode
is indicated by the symbol #. For eg, ADD # 56h adds S6h to ACC. Similarly ADD # 4567h adás
4567h to ACC.

4.2.4 Indirect Addressing

The ARs ARO-AR7 are used for accessing data, using indirect addressing mode. In the indirect
addressing mode, out of the eight ARs the one which is currently used for accessing data is denoted by
the register ARP. The contents of ARP can be temporarily stored in the ARB register. The indirect
addressing mode of C5X permits the AR used for the addressing to be updated automatically either
after or before the operand is fetched. Hence a separate instruction is not required to update the AR.
However, if required, the contents of an AR can be incremented or decremented by any 8-bit constant
using SBRK and ADRK instructions. (e.g., SBRK #k, ADRK #k subtracts, adds the constant k from/
to the AR pointed by ARP).
In the indirect addressing mode, the manner in which the
memory address is computed and the
manner in which the AR is altered after the instruction
depends on the instruction. This is indicated to
the assembler by the symbols #, *, *+,*,*0+, *0- *BR0+ and *BR0-. The symbol used to indicate
,

the indirect addressing mode and

the action taken after executing the instruction are given in Table
4.1.
 IMS320C5X Assembly Language Instructions 73

Table 4.1 Various options in the indirect addressing mode of 5X

Symbol
Value of AR pointed by ARP after instruction execution
AR unaltered
AR incremented by 1
AR decremented by 1
0+ AR incremented by the content of INDX
*0- AR decremented by the content of INDX
AR incremented by the content of INDX with reverse
BRO+ carry propagation
AR decremented by the content of INDX with reverse
BRO carry propagation

ldition/subtraction of INDX with AR with reverse carry

details on addit propagation is given in
The
Section 4.2.5.

Example 4.4 Let thevalue of ARP, AR2 and INDX register be 2, 1250h and 2h,respectively,and
the content of the data memory location 1240h-1260hbe filled with the data 2345h.
Let SXM be 0. The value of ACC and AR2 after thefollowing sequence of LAC
load accumulator with shift) instructions are executed is shown in Fig 4
LACC *,0
LACC +, 1
LACC *, 2
LACC *0+, 4
LACC*0-,3
Instruction executed Contents after execution

LACC, 0 ACC 2345h AR2 1250h

LACC +, 1 ACC 468Ah AR2 1251h

LACC ,2 ACC 9786Ah AR2 1250h

LACC 0+, 4 ACC 11A28h AR2 1252h

ACC 8D14h AR2 1250h

LACC0 ,3

Fig. 4.5 Contents of ACC and AR after execution of program in example 4.4

4.2.5 Bit-Reversed Addressing

In the bit-reversed addressing mode, INDX specifies one-half the size of the FFT. The value contained
in the current AR must be equal to 2 , where n is an integer, and the FFT size is 2". An AR points to
 74
Digital Signal Processors
e physical location of a data value. When INDX is added to the current AR, using bit-reversed

address1ng, addresses are generated in a bit-reversed fashio.

Example 4.5 Assume that the ARs are eight bits long, that ARZ represontsthebase address ofte
valué O0001000,
1000, When
When
memory (0110 0000,) and thatINDx contains the
Multiply Accunulate) instriction
MAC OFFÖOh, BRO 1s repeatedly
execufed eight times, the value ofAR2 is modificd as given in 1aple
Table 4.2 Bit-reversed addresses example 4.5

Value of AR2
Instruction executed
0110 0000 (Oth
value)
MAC OFF00h, "BRO+ AR2 =

0110 1000 (1st

value)
MAC OFF00h, "BRO+ AR2 =

MAC OFF00h, BR0+ AR2 = 0110 0100 (2nd value)

MAC OFF00h, "BRO+ AR2 = 0110 1100 (3rd value)
(4th
0110 0010 value)
MAC OFF00h, *BRO+ AR2 =

(5th
0110 1010 value)
MAC OFFO0h, *BRO+; AR2 =

0110 0110 (6th value)

MAC OFFO0h, *BRO+; AR2 =

AR2 0110 1110 (7th value)

MAC OFF00h, *BRO+

4.2.6 Immediate Addressing

The
in immediate addressing, the instruction word(s) contains the value of the immediate operand.
CSX has both 1-word (8-bit, 9-bit and 13-bit constant) short immediate instructions and 2-worda
(16-bit constant) long immediate instructions. Table 4.3 lists the instructions that support immediate

addressing.
Table 4.3 Instructions that support immediate addressin8
Short Immediate (1-word)
8-bit constant 9-bit constant 13-bit constant
ADD LDP MPY
ADRK
LACL
LAR
RPT
SBRK
SUB
Long immediate (2-word) 16-bit constant
ADD AND APL CPL
LACC LAR MPY OPL
OR RPT RPTZ
SPLK SUB XOR XPL

4.2.6.1 Short Immediate Addressing

In short immediate instructions, the operand is contained within the instruction machine code.
 TMS320C5X Assembly Language instructions 75

Example
4.6 ADD #OFFh
In this example, the lower 8 bits are the operand and are added to the ACC by the
CALU.
126.2 Long Immediate Addressing
Long immediate instructions, the operand is contained in the second word of a 2-word instruction.
IThere
n rare
e two
two long immediate addressing modes: one-operand instructions and two-operand instrc

tions.

4.26.3 long Imn. diate Addressing with Single/No Data Memory Access

Example 4.7 ADD #1234h

In this example, the second word (1234h) of the 2-word instruction is added to the
ACCby the CALU.
with Dual Data Memory Access
4.26.4 Long Immediate Addressing
also could apply for a second data memory access for the execution of
The long immediate addressing
the instruction.

Example 4.8 BLDD#2345h, 012h

n this example, the source address (operandl)is fetched via PAB, and the deshna-
tion address (operand2) uses the direct addressing mode. Bits 15 through 8 ofma-
chine codel contain the opcode. Bit 7, with a value of 0, defines the addressing
mode as direct, and bits 6 through 0 contain the dma.

4.2.7 Dedicated-Register Addressing

mode operates like the long immediate addressing mode, except
The dedicated-registered addressing
two special-purpose memory-mapped registers
in the CPU: the
that the address comes from one of advan-
the dynamic bit manipulation register (DBMR). The
block move address register (BMAR) and
mode is that the address of the block of memory to
be acted upon can be
tage of this addressing
of the program.
changed during execution of two ways:
The syntax for dedicated-register addressing
can be stated in one

Specify BMAR by its predefined symbol:

Example 4.9 BLDD BMAR, DATI00; DP 0 memory location 200his

IfBMAR contains the value 200h, then the content of data
the current data page.
copied to data memory location 100 on
Exclude the immediate value from a parallel logic unit (PLU) instruction:

Example 410 OPL DAT10, DP 6

If DBMR contains the value OFFFOh and the address 030Ah contains the value
content off
01h,thenthecontent of datamemory location 030Ah is ORed with the
the DBMR. The resulting value 0FFFih is stored back in memory location 030Ah
 76
Digital Signal Processors
4.2.8 Circular Addressing
filters
Ma: response (FIR) can use

nms convolution, correlation and finite impulse

such as
E window, which contains the most recent data to be
Circular buffers in
memory to implement a sliding via the ARS. The following
c o n c u r r e n t circular buffers operating
POCessed. The C5X supports two
IIve memory-mapped registers control the circular buffer operation:
CBSR1 Circular buffer 1 start register
CBSR2-Circular buffer 2 start register
CBERI-Circular buffer 1 end register
CBER2-Circular buffer 2 end register
circular buffers, the
CBCR Circular buffer control register To define
the circular buffer operation. next, a value between
enables and disables first;
T h e 8 - b i t CBCR buffer registers circular
addresses a r e loaded
into the corresponding The corresponding
s t a r t a n d end loaded into a n AR.
circular buffer is
t h e s t a r t and end registers for the
set.
in the CBCR should be
buffer enable bit