IC Fabrication
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IC Fabrication
• An Integrated Circuit (IC)is an electronic
network fabricated in a single piece of a
semiconductor material.
• Main steps in IC fabrication are
– Wafer formation
– oxidation
– photolithography
– etching
– Doping
– Metallization
– Testing
– Assembly and packaging
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Silicon Manufacture
• Integrated circuits are usually fabricated from silicon.
• A mixture of silica and carbon is heated in a pot (1400º C) . Thus
melted Pure silicon is formed.
• A seed of crystalline silicon is immersed in molten silicon and
gradually pulled out while rotating.
• As this cools, crystals form and grow together into a impure fine-
grained gray solid. This process of growing semiconductor-grade
silicon crystals is called the Czochralski process.
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Wafer formation
• The resulting cylinder of mono crystalline silicon is called an ingot.
• It is customarily sliced using diamond tipped saw into numerous thin circular
sections of about 1mm thick called wafers and need to be polished.
• The wafers used are extremely pure and free from defects. (99.9999999% pure)
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Fabrication Steps
Start with blank wafer
Build inverter from the bottom up
First step will be to form the n-well
Cover wafer with protective layer of SiO2 (oxide)
Remove layer where n-well should be built
Implant or diffuse n dopants into exposed wafer
Strip off SiO2
p substrate
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Oxidation
Grow SiO2 on top of Si wafer
900 – 1200 C with H2O or O2 in oxidation furnace
SiO2
p substrate
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Photoresist
Spin on Photoresist
Photoresist is a light-sensitive organic polymer
Softens where exposed to light
Photoresist
SiO2
p substrate
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Lithography
Expose photoresist through n-well mask
Strip off exposed photoresist
Photoresist
SiO2
p substrate
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Lithography
• It is the process used to transfer
patterns to each layer of the IC.
• Lithography sequence steps are
– Drawing the layer patterns on a
layout editor by the designer.
– In silicon foundry, mask is
generated from the layer patterns
– Transfer the mask pattern to the
wafer surface
– Process the wafer to physically
pattern each layer of the IC.
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Photolithography
• Process of transferring patterns of geometric shapes on
a mask to a thin layer of photosensitive material (called
photoresist ) covering the surface of a semiconductor
wafer using light source.
• Photolithography requires a clean processing room
because dust particles in the air can settle on
semiconductor wafers or lithographic masks and cause
defects that result in circuit failure.
– Particle 1 may result in the formation of a pinhole in the
underlying layer.
– Particle 2 is located near a pattern edge and may cause a
constriction of current flow in a metal runner.
– Particle 3 can lead to a short circuit between the two conducting
regions and render the circuit useless.
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Etch
Etch oxide with hydrofluoric acid (HF)
Only attacks oxide where resist has been exposed
Photoresist
SiO2
p substrate
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Etching
• An etching process selectively removes unwanted portions of a layer during
lithography.
• According to the type of etchants used, Etching can be divided into two types
– Wet etching
– Dry etching
• When a material is attacked by a liquid or vapor etchant, it is removed
isotropically (uniformly in all directions) or anisotropically (uniformity in
vertical direction).
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Wet Etch
• Also called Chemical etching and liquid etching.
• Wet etching is a material removal process that uses liquid chemicals or etchants to remove
materials from a wafer.
• A wet etching process involves multiple chemical reactions that consume the original
reactants and produce new reactants.
• The wet etch process can be described by three basic steps.
(1) Diffusion of the liquid etchant to the structure that is to be removed.
(2) The reaction between the liquid etchant and the material being etched away. A reduction-
oxidation (redox) reaction usually occurs. This reaction entails the oxidation of the material
then dissolving the oxidized material.
(3) Diffusion of the byproducts in the reaction from the reacted surface.
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Dry Etch
• Also called plasma etching, gas etching, physical dry etching, chemical dry
etching, physical-chemical etching
• In dry etching, plasmas or etchant gasses remove the substrate material.
The reaction that takes place can be done utilizing high kinetic energy of
particle beams, chemical reaction or a combination of both.
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Strip Photoresist
Strip off remaining photoresist
Use mixture of acids called piranah etch
Ne essa so esist does ’t elt i e t step
SiO2
p substrate
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N-well
n-well is formed with diffusion or ion implantation
Diffusion
Place wafer in furnace with arsenic gas
Heat until As atoms diffuse into exposed Si
Ion Implanatation
Blast wafer with beam of As ions
Ions blocked by SiO2, only enter exposed Si
SiO2
n well
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Diffusion
• Molecular diffusion is a net transport of molecules from a region of higher concentration to one of lower
concentration by random molecular motion, that results in mixing of materials.
• Diffusion of impurities is accomplished by placing semiconductor wafers in a carefully controlled, high-
temperature quartz-tube furnace and passing a gas mixture that contains the desired dopant through it.
The number of dopant atoms that diffuse into the semiconductor is related to the partial pressure of the
dopant impurity in the gas mixture.
• For diffusion in silicon, boron is the most popular dopant for introducing a p-type impurity, whereas
arsenic and phosphorus are used extensively as n-type dopants.
• These dopants can be introduced in several ways,
– solid sources (e.g., BN for boron, As2O3 for arsenic, and P2O5 for phosphorus)
– liquid sources (BBr3, AsCl3 , and POCl3 )
– gaseous sources (B2H6 (Diborane), AsH3, and PH3 )
However, liquid sources are most commonly used.
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Ion Implantation
• In this process the energetic dopant ions are implanted into the
semiconductor by means of an ion beam. The doping concentration
has a peak distribution inside the semiconductor and the profile of
the dopant distribution is determined mainly by the ion mass and
energy.
• The main advantages of ion implantation are its more precise
control and reproducibility of impurity dopings and its lower
processing temperature compared with those of the diffusion
process.
• The average depth can be controlled by adjusting the acceleration
energy. The dopant dose can be controlled by monitoring the ion
current during implantation.
• The principal side effect is the disruption or damage of the
semiconductor lattice due to ion collisions. Therefore, a subsequent
annealing treatment is needed to remove these damages.
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Channeling
• During Ion implantation, if the implant
beam is aligned with the crystal axis,
the ions penetrate the wafer to a
great depth. This effect is called
channeling.
• To avoid such alignment and to ensure
a predictable profile, the implant( or
the wafer) is tilted by 7-9°.
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Strip Oxide
Strip off the remaining oxide using HF
Back to bare wafer with n-well
Subsequent steps involve similar series of steps
n well
p substrate
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Polysilicon
Deposit very thin layer of gate oxide
< 20 Å (6-7 atomic layers)
Chemical Vapor Deposition (CVD) of silicon layer
Place wafer in furnace with Silane gas (SiH4)
Forms many small crystals called polysilicon
Heavily doped to be good conductor
Polysilicon
Thin gate oxide
n well
p substrate
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Polysilicon Patterning
Use same lithography process to pattern polysilicon
Polysilicon
Thin gate oxide
n well
p substrate
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N-diffusion
Use oxide and masking to expose where n+ dopants should be diffused
or implanted
N-diffusion forms nMOS source, drain, and n-well contact
n well
p substrate
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N-diffusion
Pattern oxide and form n+ regions
Self-aligned process where gate blocks diffusion
Polysilicon is better than metal for self-alig ed gates e ause it does ’t
melt during later processing
n+ Diffusion
n well
p substrate
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N-diffusio o t’d
Dopants were diffused
Usually ion implantation today
n+ n+ n+
n well
p substrate
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N-diffusio o t’d
Strip off oxide to complete patterning step
n+ n+ n+
n well
p substrate
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P-Diffusion
Similar set of steps form p+ diffusion regions for PMOS source and drain and
substrate contact
p+ Diffusion
p+ n+ n+ p+ p+ n+
n well
p substrate
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Contacts
Now we need to wire together the devices
Cover chip with thick field oxide
Etch oxide where contact cuts are needed
Contact
Thick field oxide
p+ n+ n+ p+ p+ n+
n well
p substrate
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Metallization
• Layer of metal is deposited on the
substrate surface to provide electrical
contact to the devices.
• Thickness of metal film can be controlled
by the length of time for sputtering
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Planarization using CMP process
• Chemical mechanical polishing/planarization is a process
of smoothing surfaces with the combination of chemical
and mechanical forces.
• It also offers other advantages, including reduced defect
density and the avoidance of plasma damage (which would
occur in an RIE-based planarization system).
• The CMP process consists of moving the sample surface
against a pad that carries slurry between the sample
surface and the pad. Abrasive particles in the slurry cause
mechanical damage on the sample surface, loosening the
material for enhanced chemical attack or fracturing off the
pieces of surface into a slurry where they dissolve or are
swept away.
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Passivation
• Passivation is the final step in back-end processing .
• It is the p o ess to o e the afe ith a a p ote ti e glass la e o
passi atio la e o o e glass , to p ote t the su fa e agai st da ages
caused by subsequent mechanical handling and dicing.
• Afte a lithog aph se ue e usi g the passi atio ask , the glass is
opened only on top of the bond pads to allow connection to the external
environment(to I/O pads and test probe points if needed).
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Die Preparation
• Die preparation is a step of semiconductor device fabrication during which
a wafer is prepared for IC Packaging and IC testing. The process of
die preparation typically consists of 2 steps
• wafer mounting
• Wafer dicing
– Wafer mounting is a step in which the wafer is mounted on a plastic tape that is
attached to a ring. Wafer mounting is performed right before the wafer is cut into
separate dies. The adhesive film on which the wafer is mounted ensures that the
individual dies remain firmly in place during dicing.
– Wafer dicing (also called die cutting, dicing or singulation ) is the process by
which die are separated from a wafer. In between each functional parts of the circuits
(die) in a wafer, a thin non-functional spacing is foreseen where a saw can safely cut the
wafer without damaging the circuits. This spacing is called scribe line or saw street. The
dicing process can be accomplished by scribing and breaking, by
mechanical sawing (normally with a machine called a dicing saw ) or by laser cutting.
Usually the dicing is performed with a water-cooled circular saw with diamond-tipped
teeth. All methods are typically automated to ensure precision and accuracy.
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