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Poori Padhai: Time: 3 Hours Total Marks: 100

This document is a theory examination for Computer Organization and Architecture. It contains 7 sections with multiple choice and descriptive questions. Section A contains 10 short answer questions worth 2 marks each on topics like computer architecture, bus arbitration, floating point representation, division algorithm, micro operations, RISC, hit ratio, page fault, cycle stealing, and vector interrupts. Section B contains 5 descriptive questions worth 10 marks each related to bus systems, carry look ahead adder, instruction cycle, RAM, and DMA controller. Sections C, D, E, F and G contain longer descriptive questions with one question to be attempted from each section related to addressing modes, processor organization, multiplication using Booth's algorithm, floating point representation, microprogram sequencer

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Yatharth Singh
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52 views

Poori Padhai: Time: 3 Hours Total Marks: 100

This document is a theory examination for Computer Organization and Architecture. It contains 7 sections with multiple choice and descriptive questions. Section A contains 10 short answer questions worth 2 marks each on topics like computer architecture, bus arbitration, floating point representation, division algorithm, micro operations, RISC, hit ratio, page fault, cycle stealing, and vector interrupts. Section B contains 5 descriptive questions worth 10 marks each related to bus systems, carry look ahead adder, instruction cycle, RAM, and DMA controller. Sections C, D, E, F and G contain longer descriptive questions with one question to be attempted from each section related to addressing modes, processor organization, multiplication using Booth's algorithm, floating point representation, microprogram sequencer

Uploaded by

Yatharth Singh
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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B TECH

(SEM-III) THEORY EXAMINATION 2020-21


COMPUTER ORGANIZATION AND ARCHITECTURE
Time: 3 Hours Total Marks: 100
Note: 1. Attempt all Sections. If require any missing data; then choose suitably.

SECTION A
1. Attempt all questions in brief. 2 x 10 = 20
Q no. Question Marks CO
a. Define the term Computer architecture and Computer organization. 2 1
b. What is mean by bus arbitration? List different types of bus arbitration. 2 1
c. Discuss biasing with reference to floating point representation. 2 2
d. What is restoring method in division algorithm? 2 2
e. Define micro operation and micro code. 2 3
f. Write short note on RISC. 2 3
g. Define hit ratio. 2 4
h. What do you mean by page fault? 2 4
i. Explain the term cycle stealing. 2 5

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j. What do you mean by vector interrupt? Explain. 2 5
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SECTION B
2. Attempt any three of the following: 3 x 10 = 30
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Q no. Question Marks CO


a. i. Draw a diagram of bus system using MUX which has four registers of size 4 10 1
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bits each.
ii. Evaluate the arithmetic statement.
X = A + B * [C * D + E * (F + G)]
or

using a stack organized computer with zero address operation instructions.


b. Explain in detail the principle of carry look ahead adder and design 4-bit CLA adder. 10 2
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c. Draw the flowchart for instruction cycle with neat diagram and explain. 10 3
d. Discuss 2 D RAM and 2.5D RAM with suitable diagram. 10 4
e. Draw and explain the block diagram of typical DMA controller. 10 5

SECTION C
3. Attempt any one part of the following:
Q no. Question Marks CO
a. An instruction is stored at location 400 with its address field at location 401.The 10 1
address field has the value 500.A processor register R1 contains the number 200.
Evaluate the effective address if the addressing mode of the instruction is (i) direct (ii)
immediate (iii) relative (iv) register indirect (v) index with R1 as index register
b. What do you mean by processor organization? Explain various types of processor 10 1
organization.

4. Attempt any one part of the following:


Q no. Question Marks CO
a. Show the systemic multiplication process of (20) X (-19) using Booth’s algorithm 10 2
b. Explain IEEE standard for floating point representation. Represent the number (- 10 2
1460.125)10 in single precision and double precision format.

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5. Attempt any one part of the following:
Q no. Question Marks CO
a. What is a micro program sequencer? With block diagram, explain the working of 10 3
micro program sequencer.
b. Differentiate between hardwired and micro programmed control unit. Explain each 10 3
component of hardwired control unit organization.

6. Attempt any one part of the following:


Q no. Question Marks CO
a. Calculate the page fault for a given string with the help of LRU & FIFO page 10 4
replacement algorithm, Size of frames = 4 and string 1 2 3 4 2 1 5 6 2 1 2 3 7 6 3 2 1
236
b. A computer uses RAM chips of 1024*1 capacity. 10 4
i) How many chips are needed & how should their address lines be connected to
provide a memory capacity of 1024*8?
ii) How many chips are needed to provide a memory capacity of 16 KB?

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7. Attempt any one part of the following:
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Q no. Question Marks CO
a. What do you mean by asynchronous data transfer? Explain strobe control and hand 10 5
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shaking mechanism.
b. Discuss the different modes of data transfer. 10 5
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