Esp32-S2 Errata en
Esp32-S2 Errata en
Errata
Introduction
Version 1.0
Espressif Systems
Copyright © 2022
www.espressif.com
Contents
Contents
Errata Description 5
1 System 5
1.1 Leakage current at the VDDA and VDD3P3_RTC pin during shutdown 5
1.2 Random flash download failure 5
2 RTC I2C 6
2.1 The falling edge of RTC_I2C_RESET triggers reset at low temperature 6
3 SPI 6
3.1 SPI is stuck after soft restart from auto suspension 6
4 USB OTG 6
4.1 Abnormal data during AHB bus arbitration by USB OTG 6
5 SAR ADC 7
5.1 Bit 1 of SAR ADC does not flip 7
Revision History 9
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Chip Revision
eFuse Bit
v0.0 v1.0
EFUSE_RD_MAC_SPI_SYS_3_REG[19] 0 0
Major Number
EFUSE_RD_MAC_SPI_SYS_3_REG[18] 0 1
EFUSE_RD_MAC_SPI_SYS_3_REG[20] 0 0
EFUSE_RD_MAC_SPI_SYS_4_REG[6] 0 0
Minor Number
EFUSE_RD_MAC_SPI_SYS_4_REG[5] 0 0
EFUSE_RD_MAC_SPI_SYS_4_REG[4] 0 0
Pin 1
Espressif Logo
Note:
Information about ESP-IDF release that supports a specific chip revision is provided in ESP Product Selector.
Errata Description
Affected Revisions
Category Description v0.0 v1.0
1.1 Leakage current at the VDDA and VDD3P3_RTC pin during
Y
System shutdown
1.2 Random flash download failure Y
2.1 The falling edge of RTC_I2C_RESET triggers reset at low
RTC I2C Y
temperature
SPI 3.1 SPI is stuck after soft restart from auto suspension Y
USB OTG 4.1 Abnormal data during AHB bus arbitration by USB OTG Y
SAR ADC 5.1 Bit 1 of SAR ADC does not flip Y
1 System
1.1 Leakage current at the VDDA and VDD3P3_RTC pin during shutdown
Description
When a chip is connected to the power supply, but the CHIP_PU pin is held low (meaning that the chip powers
off), there will be a leakage current in the µA range at power pins such as VDDA and VDD3P3_RTC.
Workarounds
No.
Projected Solution
In download mode, the first stage bootloader in ROM receives serial data from two different input pins. Among
the two intput pins, pin 24 DAC_2 (GPIO18) is not pulled up by default. If this pin is not pulled up in PCB design
and is left floating, in download mode the first stage bootloader will not function properly (including download
applications) due to interference.
Workarounds
This problem can be bypassed in PCB design by pulling up pin 24 DAC_2. The typical value of the pull-up resistor
is 10 kΩ. All official development boards by Espressif pull this pin up, while official modules are not.
Projected Solution
2 RTC I2C
2.1 The falling edge of RTC_I2C_RESET triggers reset at low temperature
Description
Workarounds
No.
Projected Solution
3 SPI
3.1 SPI is stuck after soft restart from auto suspension
Description
After auto suspend is enabled, if caching is requested while Memory SPI is erasing flash, Memory SPI will
automatically send a SUSPEND command (0x75). If there is a system reset, and Memory SPI is restarted before
sending a RESUME command (0x7A), the state machine of Memory SPI will not be restored. As a result, the
system cannot continue operations.
Workarounds
Projected Solution
4 USB OTG
4.1 Abnormal data during AHB bus arbitration by USB OTG
Description
When USB OTG and other peripherals on ESP32-S2 request the AHB bus at the same time, the AHB bus might
generate wrong arbitration signals, which result in abnormal data during reads and writes by USB OTG. The
competing peripherals include:
• I2S
• SPI
Workarounds
1. Avoid AHB bus competition between USB OTG and above peripherals by not using DMA mode of USB
OTG, or disabling DMA mode of above peripherals.
2. Avoid interrupt while USB OTG is using the AHB bus. Specifically, set USB OTG’s AHB burst transfer to
INCR mode. In this mode, USB OTG will occupy the AHB bus exclusively until the burst transfer is
completed.
Note:
Use the second workaround with care, as it requires adjustment to maximum packet size (MPS) for USB OTG
endpoints, so that burst time is smaller than the timeout period of the competing peripherals.
Projected Solution
5 SAR ADC
5.1 Bit 1 of SAR ADC does not flip
Description
Bit 1 of SAR ADC is always 0, and does not change with measured voltage.
Workarounds
No.
Projected Solution
Fixed in chip revision v1.0. The effective resolution of SAR ADC on chip revision v1.0 is changed from 13 bits to
12 bits. That is, bit 0 is not valid, and the valid bits are bit 1 ∼ bit 12 inclusive.
Developer Zone
• ESP-IDF Programming Guide for ESP32-S2 – Extensive documentation for the ESP-IDF development framework.
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Products
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• ESP32-S2 Series Modules – Browse through all ESP32-S2-based modules.
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• ESP32-S2 Series DevKits – Browse through all ESP32-S2-based devkits.
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Revision History