High Performance, 3.

2 GHz, 14-Output
Fanout Buffer
Data Sheet HMC7043
FEATURES The HMC7043 is designed to meet the requirements of multicarrier
JEDEC JESD204B support GSM and LTE base station designs, and offers a wide range of
Low additive jitter: <15 fs rms at 2457.6 MHz (12 kHz to 20 MHz) clock management and distribution features to simplify baseband
Very low noise floor: −155.2 dBc/Hz at 983.04 MHz and radio card clock tree designs.
Up to 14 LVDS, LVPECL, or CML type device clocks (DCLKs) The HMC7043 provides 14 low noise and configurable outputs
Maximum CLKOUTx/CLKOUTx and SCLKOUTx/SCLKOUTx to offer flexibility in interfacing with many different components in
frequency of 3200 MHz a base transceiver station (BTS) system, such as data converters,
JESD204B-compatible system reference (SYSREF) pulses local oscillators, transmit/receive modules, field programmable
25 ps analog and ½ clock input cycle digital delay gate arrays (FPGAs), and digital front-end ASICs. The HMC7043
independently programmable on each of 14 clock can generate up to seven DCLK and SYSREF clock pairs per the
output channels JESD204B interface requirements.
SPI-programmable adjustable noise floor vs. power consumption
The system designer can generate a lower number of DCLK and
SYSREF valid interrupt to simplify JESD204B synchronization
SYSREF pairs, and configure the remaining output signal paths
Supports deterministic synchronization of multiple
for independent phase and frequency. Both the DCLK and SYSREF
HMC7043 devices
clock outputs can be configured to support different signaling
RFSYNCIN pin or SPI-controlled SYNC trigger for output
standards, including CML, LVDS, LVPECL, and LVCMOS, and
synchronization of JESD204B
different bias conditions to adjust for varying board insertion losses.
GPIO alarm/status indicator to determine system health
Clock input to support up to 6 GHz One of the unique features of the HMC7043 is the independent
48-lead, 7 mm × 7 mm LFCSP package flexible phase management of each of the 14 channels. All
14 channels feature both frequency and phase adjustment. The
APPLICATIONS outputs can also be programmed for 50 Ω or 100 Ω internal and
JESD204B clock generation external termination options.
Cellular infrastructure (multicarrier GSM, LTE, W-CDMA)
The HMC7043 device features an RF SYNC feature that synchro-
Data converter clocking
nizes multiple HMC7043 devices deterministically, that is, ensures
Phase array reference distribution
that all clock outputs start with the same edge. This operation is
Microwave baseband cards
achieved by rephrasing the nested HMC7043 or SYSREF control
GENERAL DESCRIPTION unit/divider, deterministically, and then restarting the output
The HMC7043 is a high performance clock buffer for the dividers with this new phase.
distribution of ultralow phase noise references for high speed data The HMC7043 is offered in a 48-lead, 7 mm × 7 mm LFCSP
converters with either parallel or serial (JESD204B type) interfaces. package with an exposed pad connected to ground.
FUNCTIONAL BLOCK DIAGRAM

CLKOUT0
CLKIN/ ÷ CLKOUT0
CLKIN SCLKOUT1
SCLKOUT1

CLKOUT12
CLKOUT12
÷ SCLKOUT13
SCLKOUT13
RFSYNCIN/ SYSREF
RFSYNCIN CONTROL

SPI 14-CLOCK
SDATA CONTROL DISTRIBUTION
INTERFACE
13114-001

SLEN SCLK

Figure 1.

Rev. B Document Feedback

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HMC7043 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 Terminology .................................................................................... 14
Applications ....................................................................................... 1 Theory of Operation ...................................................................... 15
General Description ......................................................................... 1 Detailed Block Diagram ............................................................ 16
Functional Block Diagram .............................................................. 1 Clock Input Network ................................................................. 16
Revision History ............................................................................... 2 Clock Output Network .............................................................. 17
Specifications..................................................................................... 3 Typical Programming Sequence............................................... 23
Conditions ..................................................................................... 3 Power Supply Considerations ................................................... 24
Supply Current .............................................................................. 3 Serial Control Port ......................................................................... 27
Digital Input/Output (I/O) Electrical Specifications ............... 4 Serial Port Interface (SPI) Control ........................................... 27
Clock Input Path Specifications.................................................. 4 Control Registers ............................................................................ 28
Additive Jitter and Phase Noise Characteristics ....................... 5 Control Register Map ................................................................ 28
Clock Output Distribution Specifications................................. 5 Control Register Map Bit Descriptions ................................... 33
Clock Output Driver Characteristics ......................................... 6 Applications Information .............................................................. 41
Absolute Maximum Ratings ............................................................ 8 Evaluation PCB And Schematic ............................................... 41
ESD Caution .................................................................................. 8 Outline Dimensions ....................................................................... 43
Pin Configuration and Function Descriptions ............................. 9 Ordering Guide .......................................................................... 43
Typical Performance Characteristics ........................................... 11
Typical Application Circuits.......................................................... 13

REVISION HISTORY
7/2016—Rev. A to Rev. B
Changes to Table 1 ............................................................................ 3

5/2016—Rev. 0 to Rev. A
Changes to Table 3 ............................................................................. 4
Change to Maximum Operating Frequency Parameter, Table 7 ..... 7
Added Figure 6, Renumbered Sequentially ................................ 11
Change to Synchronization FSM/Pulse Generator
Timing Section ................................................................................. 21
Changes to Table 20 ........................................................................ 28
Change to Table 22 ......................................................................... 33
Changes to Table 28 ........................................................................ 34
Changes to Table 29 ........................................................................ 35
Change to Table 31 ......................................................................... 36
Change to Table 38 ......................................................................... 37
Changes to Table 41 ........................................................................ 39

12/2015—Revision 0: Initial Version

Rev. B | Page 2 of 43
Data Sheet HMC7043

SPECIFICATIONS
VCC = 3.3 V ± 5%, and TA = 25°C, unless otherwise noted. Minimum and maximum values are given over the full VCC and TA (−40°C to
+85°C) variation, as listed in Table 1.
CONDITIONS
Table 1.
Parameter1 Min Typ Max Unit Test Conditions/Comments
SUPPLY VOLTAGE, VCC
VCC1_CLKDIST 3.135 3.3 3.465 V 3.3 V ± 5%, supply voltage for CLK distribution
VCC2_OUT 3.135 3.3 3.465 V 3.3 V ± 5%, supply voltage for Output Channel 2 and
Output Channel 3
VCC3_OUT 3.135 3.3 3.465 V 3.3 V ± 5%, supply voltage for Output Channel 4, Output
Channel 5, Output Channel 6 and Output Channel 7
VCC4_CLKIN 3.135 3.3 3.465 V 3.3 V ± 5%, supply voltage for the clock input path
VCC5_SYSREF 3.135 3.3 3.465 V 3.3 V ± 5%, supply voltage for the common SYSREF divider
VCC6_OUT 3.135 3.3 3.465 V 3.3 V ± 5%, supply voltage for Output Channel 8, Output
Channel 9, Output Channel 10, and Output Channel 11
VCC7_OUT 3.135 3.3 3.465 V 3.3 V ± 5%, supply voltage for Output Channel 0, Output
Channel 1, Output Channel 12, and Output Channel 13
TEMPERATURE
Ambient Temperature Range, TA −40 +25 +85 °C
1
Maximum values are guaranteed by design and characterization.

SUPPLY CURRENT
For detailed test conditions, see Table 17 and Table 18.

Table 2
Parameter1, 2 Min Typ Max Unit Test Conditions/Comments
CURRENT CONSUMPTION3
VCC1_CLKDIST 87 125 mA
VCC2_OUT4 90 250 mA Typical value is given at TA = 25°C with two LVDS clocks at divide by 8
VCC3_OUT4 52 500 mA Typical value is given at 25°C with two LVDS high performance clocks,
fundamental frequency of the clock input (fO), two SYSREF clocks (off )
VCC4_CLKIN 16 25 mA Typical value is given at TA = 25°C with RF synchronization (RFSYNC) input
buffer off
VCC5_SYSREF 23 35 mA Typical value is given at TA = 25°C with internal RF SYNC path off
VCC6_OUT4 90 500 mA Typical value is given at 25°C with two LVDS high performance clocks at
divide by 2, two SYSREF clocks (off )
VCC7_OUT4 100 500 mA Typical value is given at 25°C with two LVDS clocks at divide by 8, two SYSREF
clocks (off )
Total Current 458 mA
1
Maximum values are guaranteed by design and characterization.
2
Currents include LVDS termination currents.
3
Maximum values are for all circuits enabled in their worst case power consumption mode, PVT variations, and accounting for peak current draw during temporary
synchronization events.
4
Typical specification applies to a normal usage profile (Profile 1 in Table 17) but very low duty cycle currents (sync events) and some optional features are disabled.
This specification assumes output configurations as described in the test conditions/comments column.

Rev. B | Page 3 of 43
HMC7043 Data Sheet
DIGITAL INPUT/OUTPUT (I/O) ELECTRICAL SPECIFICATIONS
Table 3.
Parameter Min Typ Max Unit Test Conditions/Comments
DIGITAL INPUT SIGNALS (RESET, SLEN, SCLK)
Safe Input Voltage Range −0.1 +3.6 V
Input Load 0.3 pF
Input Voltage
Input Logic High 1.2 VCC V
Input Logic Low 0 0.5 V
SPI Bus Frequency 10 MHz
DIGITAL BIDIRECTIONAL SIGNALS
CONFIGURED AS INPUTS (SDATA, GPIO)
Safe Input Voltage Range −0.1 +3.6 V
Input Capacitance 0.4 pF
Input Resistance 50 GΩ
Input Voltage
Input Logic High 1.22 VCC V
Input Logic Low 0 0.24 V
Input Hysteresis 0.2 V Occurs around 0.85 V
GPIO ALARM MUXING/DELAY
Delay from Internal Alarm/Signal to 2 ns Does not include tDGPO
General-Purpose Output (GPO) Driver
DIGITAL BIDIRECTIONAL SIGNALS
CONFIFURED AS OUTPUTS (SDATA, GPIO)
CMOS Mode
Logic 1 Level 1.6 1.9 2.2 V
Logic 0 Level 0 0.1 V
Output Drive Resistance (RDRIVE) 50 Ω
Output Driver Delay (tDGPO) 1.5 + 42 × CLOAD ns Approximately 1.5 ns + 0.69 × RDRIVE × CLOAD
(CLOAD in nF)
Maximum Supported DC Current 1 0.6 mA
Open-Drain Mode External 1 kΩ pull-up resistor
Logic 1 Level 3.6 V 3.6 V maximum permitted; specifications set by
external supply
Logic 0 Level 0.13 0.28 V Against a 1 kΩ external pull-up resistor to 3.3 V
Pull-Down Impedance 60 Ω
Maximum Supported Sink Current1 5 mA
1
Guaranteed by design and characterization for long-term reliability.

CLOCK INPUT PATH SPECIFICATIONS

Table 4.
Parameter Min Typ Max Unit Test Conditions/Comments
CLK INPUT (CLKIN) CHARACTERISTICS
Recommended Input Power, AC-Coupled
Differential −6 +8 dBm
Single-Ended 1 −10 +6 dBm Noise floor degrade by 3 dB at fCLKIN = 2400 MHz
Return Loss −12 dB When terminated with 100 Ω differential
Clock Input Frequency (fCLKIN) 200 3200 MHz Fundamental mode; if <1 GHz, set the low frequency
clock input path enable bit (Register 0x0064, Bit 0)
200 6000 MHz Using clock input ÷ 2
Common-Mode Range 0.4 2.4 V
1
Guaranteed by design and characterization.

Rev. B | Page 4 of 43
Data Sheet HMC7043
ADDITIVE JITTER AND PHASE NOISE CHARACTERISTICS
Table 5.
Parameter 1 Min Typ Max Unit Test Conditions/Comments
ADDITIVE JITTER HMC7044 used as a clock source (see Figure 3)
RMS Additive Jitter <30 fs rms Clock output frequency (fCLKOUT) = 983.04 MHz, BW = 12 kHz to 20 MHz,
clock input slew rate ≥ 8 ns
<15 fs rms fCLKOUT = 2457.6 MHz, BW = 12 kHz to 20 MHz, clock input slew rate ≥ 4 ns
CLOCK OUTPUT PHASE NOISE HMC830 used as a clock source and configured to produce 983.04 MHz
at the output (see Figure 4), input slew rate > 1 V/ns
Absolute Phase Noise
Offset = 1 MHz −144.3 dBc/Hz fCLKOUT = 983.04 MHz, fCLKOUT = 983.04 MHz, divide by 1 at the output
Offset = 10 MHz −154.8 dBc/Hz fCLKOUT = 983.04 MHz, fCLKOUT = 2949.12 MHz, divide by 3 at the output
Offset = 20 MHz −155.2 dBc/Hz fCLKOUT = 983.04 MHz, fCLKOUT = 983.04 MHz, divide by 1 at the output
1
Guaranteed by design and characterization.

CLOCK OUTPUT DISTRIBUTION SPECIFICATIONS

Table 6.
Parameter Min Typ Max Unit Test Conditions/Comments
CLOCK OUTPUT SKEW
CLKOUTx/CLKOUTx to SCLKOUTx/SCLKOUTx Skew 15 |ps| Same pair, same type termination and
Within One Clock Output Pair configuration
Any CLKOUTx/CLKOUTx to Any SCLKOUTx/SCLKOUTx 30 |ps| Any pair, same type termination and
configuration
PROPAGATION DELAY CLKIN to CLKOUTx and SCLKOUTx1 770 820 870 ps fCLKIN = 983.04 MHz, all VCC set to 3.3 V
CLOCK OUTPUT DIVIDER CHARACTERISTICS
12-Bit Divider Range 1 4094 1, 3, 5, and all even numbers up to 4094
SYSREF CLOCK OUTPUT DIVIDER CHARACTERISTICS
12-Bit Divider Range 1 4094 1, 3, 5, and all even numbers up to 4094;
pulse generator behavior is only
supported for divide ratios ≥ 32
CLOCK OUTPUT ANALOG FINE DELAY
Analog Fine Delay
Adjustment Range1 135 670 ps 24 delay steps, fCLKOUT = 983.04 MHz
Resolution 25 ps fCLKOUT = 983.04 MHz (2949.12 MHz/3)
Maximum Analog Fine Delay Frequency 1600 MHz
CLOCK OUTPUT COARSE DELAY (FLIP FLOP BASED)
Coarse Delay Adjustment Range 0 17 ½ CLKIN period 17 delay steps
Coarse Delay Resolution 169.54 ps fCLKIN = 2949.12 MHz
Maximum Frequency Coarse Delay 1500 MHz
CLOCK OUTPUT COARSE DELAY (SLIP BASED)
Coarse Delay
Adjustment Range 1 to ∞ CLKIN period
Resolution 339.08 ps fCLKIN = 2949.12 MHz
Maximum Frequency Coarse Delay 1600 MHz
1
Guaranteed by design and characterization.

Rev. B | Page 5 of 43
HMC7043 Data Sheet
CLOCK OUTPUT DRIVER CHARACTERISTICS
Table 7.
Parameter Min Typ Max Unit Test Conditions/Comments
CML MODE (LOW POWER) RL = 100 Ω, 9.6 mA
−3 dB Bandwidth 1950 MHz Differential output voltage = 980 mV p-p diff
Output Rise Time 175 ps fCLKOUT = 245.76 MHz, 20% to 80%
145 ps fCLKOUT = 983.04 MHz, 20% to 80%
Output Fall Time 185 ps fCLKOUT = 245.76 MHz, 20% to 80%
145 ps fCLKOUT = 983.04 MHz, 20% to 80%
Output Duty Cycle 1 47.5 50 52.5 % fCLKOUT = 1075 MHz (2150 MHz/2)
Differential Output Voltage Magnitude 1390 mV p-p diff fCLKOUT = 245.76 MHz (2949.12 MHz/12)
1360 mV p-p diff fCLKOUT = 983.04 MHz (2949.12 MHz/3)
Common-Mode Output Voltage VCC − 1.05 V fCLKOUT = 245.76 MHz (2949.12 MHz/12)
CML MODE (HIGH POWER) RL = 100 Ω, 14.5 mA
−3 dB Bandwidth 1500 MHz Differential output voltage = 1470 mV p-p diff
Output Rise Time 250 ps fCLKOUT = 245.76 MHz, 20% to 80%
165 ps fCLKOUT = 983.04 MHz, 20% to 80%
Output Fall Time 255 ps fCLKOUT = 245.76 MHz, 20% to 80%
170 ps fCLKOUT = 983.04 MHz, 20% to 80%
Output Duty Cycle1 47.5 50 52.5 % fCLKOUT = 1075 MHz (2150 MHz/2)
Differential Output Voltage Magnitude 2000 mV p-p diff fCLKOUT = 245.76 MHz (2949.12 MHz/12)
1800 mV p-p diff fCLKOUT = 983.04 MHz (2949.12 MHz/3)
Differential Output
Voltage Magnitude 590 mV p-p diff fCLKOUT = 3200 MHz
Power −3.6 dBm diff fCLKOUT = 3200 MHz
Common-Mode Output Voltage VCC − 1.6 V fCLKOUT = 245.76 MHz (2949.12 MHz/12)
LVPECL MODE RL = 150 Ω, 4.8 mA
−3 dB Bandwidth 2400 MHz Differential output voltage = 1240 mV p-p diff
Output Rise Time 135 ps fCLKOUT = 245.76 MHz, 20% to 80%
130 ps fCLKOUT = 983.04 MHz, 20% to 80%
Output Fall Time 135 ps fCLKOUT = 245.76 MHz, 20% to 80%
130 ps fCLKOUT = 983.04 MHz, 20% to 80%
Output Duty Cycle1 47.5 50 52.5 % fCLKOUT = 1075 MHz (2150 MHz/2)
Differential Output Voltage Magnitude 1760 mV p-p diff fCLKOUT = 245.76 MHz (2949.12 MHz/12)
1850 mV p-p diff fCLKOUT = 983.04 MHz (2949.12 MHz/3)
Differential Output
Voltage Magnitude 930 mV p-p diff fCLKOUT = 3200 MHz
Power 0.3 dBm diff fCLKOUT = 3200 MHz
Common-Mode Output Voltage VCC − 1.3 V fCLKOUT = 245.76 MHz (2949.12 MHz/12)
LVDS MODE (LOW POWER) 1.75 mA
Maximum Operating Frequency 1700 MHz Differential output voltage = 320 mV p-p diff
Output Rise Time 135 ps fCLKOUT = 245.76 MHz, 20% to 80%
100 ps fCLKOUT = 983.04 MHz, 20% to 80%
Output Fall Time 135 ps fCLKOUT = 245.76 MHz, 20% to 80%
95 ps fCLKOUT = 983.04 MHz, 20% to 80%
Output Duty Cycle1 47.5 50 52.5 % fCLKOUT = 1075 MHz (2150 MHz/2)
Differential Output Voltage Magnitude 390 mV p-p diff fCLKOUT = 245.76 MHz (2949.12 MHz/12)
Common-Mode Output Voltage 1.1 V fCLKOUT = 245.76 MHz (2949.12 MHz/12)

Rev. B | Page 6 of 43
Data Sheet HMC7043
Parameter Min Typ Max Unit Test Conditions/Comments
LVDS MODE (HIGH POWER) 3.5 mA
Maximum Operating Frequency 1700 MHz Differential output voltage = 600 mV p-p diff
Output Rise Time 145 ps fCLKOUT = 245.76 MHz, 20% to 80%
105 ps fCLKOUT = 983.04 MHz, 20% to 80%
Output Fall Time 145 ps fCLKOUT = 245.76 MHz, 20% to 80%
100 ps fCLKOUT = 983.04 MHz, 20% to 80%
Output Duty Cycle1 47.5 50 52.5 % fCLKOUT = 1075 MHz (2150 MHz/2)
Differential Output Voltage Magnitude 750 mV p-p diff fCLKOUT = 245.76 MHz (2949.12 MHz/12)
730 mV p-p diff fCLKOUT = 983.04 MHz (2949.12 MHz/3)
Common-Mode Output Voltage 1.1 V fCLKOUT = 245.76 MHz (2949.12 MHz/12)
CMOS MODE
Maximum Operating Frequency 600 MHz Single-ended output voltage = 940 mV p-p diff
Output Rise Time 425 ps fCLKOUT = 245.76 MHz, 20% to 80%
Output Fall Time 420 ps fCLKOUT = 245.76 MHz, 20% to 80%
Output Duty Cycle1 47.5 50 52.5 % fCLKOUT = 1075 MHz (2150 MHz/2)
Output Voltage
High VCC V Load current = 1 mA
VCC − 0.5 V Load current = 10 mA
Low 0.07 V Load current = 1 mA
0.5 V Load current = 10 mA
1
Guaranteed by design and characterization.

Rev. B | Page 7 of 43
HMC7043 Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 8. Stresses at or above those listed under Absolute Maximum
Parameter Rating Ratings may cause permanent damage to the product. This is a
VCC1, VCC2, VCC3, VCC4, VCC5, VCC6, VCC7 to −0.3 V to +3.6 V stress rating only; functional operation of the product at these
Ground or any other conditions above those indicated in the operational
Maximum Junction Temperature 125°C section of this specification is not implied. Operation beyond
Thermal Resistance (Channel to Ground Pad) 7°C/W the maximum operating conditions for extended periods may
Storage Temperature Range −65°C to +125°C affect product reliability.
Operating Temperature Range −40°C to +85°C
ESD CAUTION
Peak Reflow Temperature 260°C
ESD Sensitivity Level
Human Body Model (HBM) Class 1C
Charged Device Model (CDM)1 Class 4
1
Per JESD22-C101-F (CDM) standard.

Rev. B | Page 8 of 43
Data Sheet HMC7043

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

SCLKOUT13
SCLKOUT13
SCLKOUT11
SCLKOUT11
VCC7_OUT

VCC6_OUT
CLKOUT12
CLKOUT12

CLKOUT10
CLKOUT10

CLKOUT8
CLKOUT8
41

39

37
43
42

40

38
44
48
47
46
45
CLKOUT0 1 36 SCLKOUT9
CLKOUT0 2 35 SCLKOUT9
SCLKOUT1 3 34 GPIO
SCLKOUT1 4 33 SDATA
RESET 5 HMC7043 32 SCLK
BGAPBYP1 6 31 SLEN
LDOBYP2 7 TOP VIEW 30 VCC5_SYSREF
(Not to Scale)
VCC1_CLKDIST 8 29 RFSYNCIN
SCLKOUT3 9 28 RFSYNCIN
SCLKOUT3 10 27 VCC4_CLKIN
CLKOUT2 11 26 CLKIN
CLKOUT2 12 25 CLKIN

13
14
15
16
17
18
19
20
21
22
23
24
SCLKOUT5
SCLKOUT5
CLKOUT4
CLKOUT4

CLKOUT6
CLKOUT6
SCLKOUT7
SCLKOUT7
RSV

RSV
VCC2_OUT

VCC3_OUT
NOTES

13114-002
1. RSV = RESERVED PIN AND MUST BE TIED TO GROUND.
2. CONNECT THE EXPOSED PAD TO A HIGH QUALITY RF/DC GROUND.

Figure 2.

Table 9. Pin Function Descriptions

Pin No. Mnemonic Type 1 Description
1 CLKOUT0 O True Clock Output Channel 0. Default DCLK profile.
2 CLKOUT0 O Complementary Clock Output Channel 0. Default DCLK profile.
3 SCLKOUT1 O True Clock Output Channel 1. Default SYSREF profile.
4 SCLKOUT1 O Complementary Clock Output Channel 1. Default SYSREF profile.
5 RESET I Device Reset Input. Active high. For normal operation, set RESET to 0.
6 BGAPBYP1 Band Gap Bypass Capacitor Connection. Connect a 4.7 µF capacitor to ground. This pin affects all
internally regulated supplies.
7 LDOBYP2 LDO Bypass 2. Connect a 4.7 µF capacitor to ground. The internal digital supply is 1.8 V. This pin is the
LDO bypass for the SYSREF section.
8 VCC1_CLKDIST P 3.3 V Supply for CLK Distribution.
9 SCLKOUT3 O True Clock Output Channel 3. Default SYSREF profile.
10 SCLKOUT3 O Complementary Clock Output Channel 3. Default SYSREF profile.
11 CLKOUT2 O True Clock Output Channel 2. Default DCLK profile.
12 CLKOUT2 O Complementary Clock Output Channel 2. Default DCLK profile.
13 VCC2_OUT P Power Supply for Clock Group 1 (Southwest)—Channel 2 and Channel 3. See the Clock Grouping,
Skew, and Crosstalk section.
14 RSV R Reserved Pin. This pin must be tied to ground.
15 SCLKOUT5 O True Clock Output Channel 5. Default SYSREF profile.
16 SCLKOUT5 O Complementary Clock Output Channel 5. Default SYSREF profile.
17 CLKOUT4 O True Clock Output Channel 4. Default DCLK profile.
18 CLKOUT4 O Complementary Clock Output Channel 4. Default DCLK profile.
19 VCC3_OUT P Power Supply for Clock Group 2 (South)—Channel 4, Channel 5, Channel 6, and Channel 7. See the
Clock Grouping, Skew, and Crosstalk section.
20 CLKOUT6 O True Clock Output Channel 6. Default DCLK profile.
21 CLKOUT6 O Complementary Clock Output Channel 6. Default DCLK profile.
22 SCLKOUT7 O True Clock Output Channel 7. Default SYSREF profile.
23 SCLKOUT7 O Complementary Clock Output Channel 7. Default SYSREF profile.
24 RSV R Reserved Pin. This pin must be tied to ground.
25 CLKIN I Complementary Clock Input.
26 CLKIN I True Clock Input.

Rev. B | Page 9 of 43
HMC7043 Data Sheet
Pin No. Mnemonic Type 1 Description
27 VCC4_CLKIN P Power Supply for the Clock Input Path.
28 RFSYNCIN I True RF Synchronization Input with Deterministic Delay.
29 RFSYNCIN I Complementary RF Synchronization Input with Deterministic Delay.
30 VCC5_SYSREF P Power Supply for Common SYSREF Divider.
31 SLEN I/O SPI Latch Enable.
32 SCLK I/O SPI Clock.
33 SDATA I/O SPI Data.
34 GPIO I/O Programmable General-Purpose Input/Output.
35 SCLKOUT9 O True Clock Output Channel 9. Default SYSREF profile.
36 SCLKOUT9 O Complementary Clock Output Channel 9. Default SYSREF profile.
37 CLKOUT8 O True Clock Output Channel 8. Default DCLK profile.
38 CLKOUT8 O Complementary Clock Output Channel 8. Default DCLK profile.
39 VCC6_OUT P Power Supply for Clock Group 3 (North)—Channel 8, Channel 9, Channel 10, and Channel 11. See the
Clock Grouping, Skew, and Crosstalk section.
40 CLKOUT10 O True Clock Output Channel 10. Default DCLK profile.
41 CLKOUT10 O Complementary Clock Output Channel 10. Default DCLK profile.
42 SCLKOUT11 O True Clock Output Channel 11. Default SYSREF profile.
43 SCLKOUT11 O Complementary Clock Output Channel 11. Default SYSREF profile.
44 SCLKOUT13 O True Clock Output Channel 13. Default SYSREF profile.
45 SCLKOUT13 O Complementary Clock Output Channel 13. Default SYSREF profile.
46 CLKOUT12 O True Clock Output Channel 12. Default DCLK profile.
47 CLKOUT12 O Complementary Clock Output Channel 12. Default DCLK profile.
48 VCC7_OUT P Power Supply for Clock Group 0 (Northwest)—Channel 0, Channel 1, Channel 12, and Channel 13. See
the Clock Grouping, Skew, and Crosstalk section.
EP Exposed Pad. Connect the exposed pad to a high quality RF/dc ground.
1
O is output, I is input, P is power, R is reserved, and I/O is input/output.

Rev. B | Page 10 of 43
Data Sheet HMC7043

TYPICAL PERFORMANCE CHARACTERISTICS

–100 2.25
HMC7044-CLOCK SOURCE HMC7043 OUTPUT:
HMC7043 AT FUNDEMENTAL MODE 2.10 LVPECL

DIFFERENTIAL OUTPUT VOLTAGE (V p-p)

1MHz, –140.30 dBc/Hz CML100 HIGH
1.95
–110 5MHz, –151.02 dBc/Hz CML100 LOW
10MHz, –151.77 dBc/Hz 1.80 LVDS HIGH
20MHz, –151.97 dBc/Hz
1.65
PHASE NOISE (dBc/Hz)

RMS JITTER = 77.01fs

–120 1.50
1.35
1.20
–130
1.05
0.90
–140 HMC7044 AS CLOCK SOURCE: 0.75
OUTPUT FREQ = 983.04MHz
OUTPUT POWER = 3.7dBm 0.60
1MHz, –140.56dBc/Hz 0.45
–150 5MHz, –153.26dBc/Hz
10MHz, –154.28dBc/Hz 0.30
20MHz, –154.85dBc/Hz 0.15
RMS JITTER (12kHz TO 20MHz): 73.74fs
–160 0

13114-003

13114-100
1 10 100 1000 10000 1.0 1.5 2.0 2.5 3.0 3.5
FREQUENCY OFFSET (kHz) FREQUENCY (GHz)

Figure 3. Additive Jjitter at 983.04 MHz at Output Figure 6.Differential Output Voltage vs. Frequency over Various Modes

–100 2.00
HMC830-CLOCK SOURCE HMC830 AS CLOCK SOURCE:

DIFFERENTIAL OUTPUT VOLTAGE (Vp-p DIFF)

–40°C
HMC7043 OUTPUT FREQ = 983.04MHz +25°C
–110 OUTPUT POWER = 4dBm 1.75 +85°C
1MHz, –144.49dBc/Hz
5MHz, –158.38dBc/Hz
10MHz,–162.61dBc/Hz 1.5
PHASE NOISE (dBc/Hz)

–120 20MHz, –164.29dBc/Hz

1.25
–130
1.00
–140
0.75

–150
HMC7043 OUTPUT: 0.5
AT FUNDEMENTAL MODE
–160 1MHz, –144.31 dBc/Hz
5MHz, –153.46 dBc/Hz 0.25
10MHz, –154.78 dBc/Hz
20MHz, –155.18 dBc/Hz
–170 0

13114-205
13114-004

1 10 100 1000 10000 100M 1G 3G

FREQUENCY OFFSET (kHz) FREQUENCY (Hz)

Figure 4. Absolute Phase Noise Measured at 983.04 MHz at Output Figure 7. LVPECL Differential Output Power vs. Frequency over Various
Temperatures
3.5 0.4
LVPECL
DIFFERENTIAL OUTPUT VOLTAGE (Vp-p DIFF)

CML100 HIGH
3.0 CML100 LOW 0.3
LVDS HIGH
CLKOUT0/CLKOUT0 VOLTAGE (V)

CMOS (NOT IN
DIFFERENTIAL MODE) 0.2
2.5

0.1
2.0
0
1.5
–0.1

1.0
–0.2

0.5
–0.3

0 –0.4
13114-206

13114-007

100M 1G 3.2G 0 0.4 0.8 1.2 1.6 2.0

FREQUENCY (Hz) TIME (ns)

Figure 5. Differential Output Power vs. Frequency over Various Modes Figure 8. Differential CLKOUT0/CLKOUT0 at 2457 MHz, LVPECL

Rev. B | Page 11 of 43
HMC7043 Data Sheet

CLOCK GROUP VALID PHASE ALARM VOLTAGE (V)

1.0 0.6 2.5

0.8
0.4 2.0
CLKOUT0/CLKOUT0 VOLTAGE (V)

0.6

CLOCK OUTPUT VOLTAGE (V)

0.4
0.2 1.5
0.2

0 0 1.0

–0.2
–0.2 0.5
–0.4

–0.6
–0.4 0
–0.8 CLKOUT0 VALID PHASE ALARM
CLKOUT2
–1.0 –0.6 –0.5

13114-011
13114-008
0 1 2 3 4 5 6 7 8 9 10 695 700 705 710 715
TIME (ns) TIME (ns)

Figure 9. Differential CLKOUT0/CLKOUT0 Voltage at 614.4 MHz, LVPECL Figure 12. Output Channel Synchronization After Rephase
CLOCK GROUP VALID PHASE ALARM VOLTAGE (V)

0.6 2.5 30
CLKOUT0
CLKOUT2
VALID PHASE ALARM
0.4 2.0
CLOCK OUPUT VOLTAGE (V)

25
0.2 1.5 DELAY STEP SIZE (ps)

0 1.0 20

–0.2 0.5

15
–0.4 0
–40°C
+25°C
+85°C
–0.6 –0.5 10

13114-012
13114-009

1
2
3
4
5
6
7
8
9

11
10

12
13
14
15
16
17
18
19
20
21
22
23
24
0 200 400 600 800 1000
TIME (ns) DELAY STEP

Figure 10. Output Channel Synchronization Before and After Rephase Figure 13. Analog Delay Step Size vs. Delay Step over Temperature,
LVPECL at 983.04 MHz
800
CLOCK GROUP VALID PHASE ALARM VOLTAGE (V)

0.6 2.5
CLKOUT0 –40°C
CLKOUT2 700 +27°C
VALID PHASE ALARM +85°C
0.4 2.0 600
CLOCK OUTPUT VOLTAGE (V)

DELAY STEP SIZE (ps)

500
0.2 1.5
400

0 1.0 300

200
–0.2 0.5 100

0
–0.4 0
–100 FUND:FUNDAMENTAL MODE AT 2949.12MHz
DIS: ANALOG DELAY IS DISABLED AT 983.04MHz
–0.6 –0.5 –200
FUND
DIS

13114-013

0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
13114-010

330 335 340 345 350

TIME (ns) DELAY STEP

Figure 11. Output Channel Synchronization Before Rephase Figure 14. Analog Delay vs. Delay Setting over Temperature, LVPECL at
983.04 MHz

Rev. B | Page 12 of 43
Data Sheet HMC7043

TYPICAL APPLICATION CIRCUITS

HMC7043 0.1µF HMC7043

HIGH HIGH
LVDS LVDS
100Ω IMPEDANCE DOWNSTREAM 100Ω IMPEDANCE DOWNSTREAM
OUTPUT DEVICE OUTPUT DEVICE
INPUT INPUT

13114-014

13114-018
0.1µF

Figure 15. AC-Coupled LVDS Output Driver Figure 19. DC-Coupled LVDS Output Driver

VCC
HMC7043
100Ω 100Ω
LVPECL- DOWNSTREAM
HMC7043 0.1µF COMPATIBLE DEVICE
OUTPUT (LVPECL)
HIGH
100Ω IMPEDANCE DOWNSTREAM
INPUT DEVICE
50Ω 50Ω

CML 0.1µF 13114-015

OUTPUT
50Ω

13114-019
GND

Figure 16. AC-Coupled CML (Configured High-Z) Output Driver Figure 20. DC-Coupled LVPECL Output Driver

HMC7043 0.1µF HMC7043 DOWNSTREAM

DEVICE
100Ω 100Ω
HIGH (CML)
VCC 100Ω IMPEDANCE DOWNSTREAM VCC
INPUT DEVICE
100Ω 100Ω

13114-020
13114-016

CML 0.1µF CML

OUTPUT OUTPUT

Figure 17. AC-Coupled CML (Internal) Output Driver Figure 21. DC-Coupled CML (Internal) Output Driver

0.1µF HMC7043 HMC7043

3.3V
DRIVER
0.1µF

SELF BIASED
13114-017

REF, VCXO

13114-021
0.1µF INPUTS
0.1µF

Figure 18. CLKIN/CLKIN , RFSYNCIN Input Differential Mode Figure 22. CLKIN, RFSYNCIN Input Single-Ended Mode

Rev. B | Page 13 of 43
HMC7043 Data Sheet

TERMINOLOGY
Phase Jitter and Phase Noise wave, the time jitter is a displacement of the edges from their
An ideal sine wave has a continuous and even progression of ideal (regular) times of occurrence. In both cases, the variations in
phase with time from 0° to 360° for each cycle. Actual signals, timing from the ideal are the time jitter. Because these variations
however, display a certain amount of variation from ideal phase are random in nature, the time jitter is specified in seconds root
progression over time. This phenomenon is phase jitter. Although mean square (rms) or 1 sigma of the Gaussian distribution.
many causes can contribute to phase jitter, one major cause is Time jitter that occurs on a sampling clock for a DAC or an
random noise, which is characterized statistically as being ADC decreases the signal-to-noise ratio (SNR) and dynamic
Gaussian (normal) in distribution. range of the converter. A sampling clock with the lowest possible
This phase jitter leads to the energy of the sine wave in the jitter provides the highest performance from a given converter.
frequency domain spreading out, producing a continuous power Additive Phase Noise
spectrum. This power spectrum is usually reported as a series of Additive phase noise is the amount of phase noise that is
values whose units are dBc/Hz at a given offset in frequency from attributable to the device or subsystem being measured.
the sine wave (carrier). The value is a ratio (expressed in decibels) The phase noise of any external oscillators or clock sources is
of the power contained within a 1 Hz bandwidth with respect to subtracted, which makes it possible to predict the degree to
the power at the carrier frequency. For each measurement, the which the device impacts the total system phase noise when
offset from the carrier frequency is also given. used in conjunction with the various oscillators and clock
It is meaningful to integrate the total power contained within some sources, each of which contributes a phase noise to the total. In
interval of offset frequencies (for example, 10 kHz to 10 MHz). many cases, the phase noise of one element dominates the
This is the integrated phase noise over that frequency offset system phase noise. When there are multiple contributors to
interval and can be readily related to the time jitter due to the phase noise, the total is the square root of the sum of squares of
phase noise within that offset frequency interval. the individual contributors.
Phase noise has a detrimental effect on the performance of analog- Additive Time Jitter
to-digital converters (ADCs), digital-to-analog converters (DACs), Additive time jitter is the amount of time jitter that is attributable to
and RF mixers. It lowers the achievable dynamic range of the the device or subsystem being measured. The time jitter of any
converters and mixers, although they are affected in somewhat external oscillators or clock sources is subtracted, which makes
different ways. it possible to predict the degree to which the device impacts the
Time Jitter total system time jitter when used in conjunction with the various
Phase noise is a frequency domain phenomenon. In the time oscillators and clock sources, each of which contributes a time
domain, the same effect is exhibited as time jitter. When observing jitter to the total. In many cases, the time jitter of the external
a sine wave, the time of successive zero crossings varies. In a square oscillators and clock sources dominates the system time jitter.

Rev. B | Page 14 of 43
Data Sheet HMC7043

THEORY OF OPERATION
The HMC7043 is a high performance, clock distribution IC The HMC7043 provides output clock signals of up to 3.2 GHz,
designed for extending the number of clock signals across the while having the flexibility to support input reference frequencies of
system with minimal noise contribution. The device can be up to 6 GHz when the internal clock division blocks are turned on.
used for distributing the noise sensitive reference clocks for high The higher frequency support enables higher bandwidth RF
speed data converters with either parallel or serial (JESD204B) designs, and allows for distribution of low noise RF phase-locked
interfaces, FPGAs, and local oscillators. The HMC7043 is loop (PLL) voltage controlled oscillator (VCO) outputs as well
designed to meet the requirements of demanding base station as other critical clocks across the system.
designs, and offers a wide range of clock management and One of the key challenges in JESD204B system design is ensuring
distribution features to simplify baseband and radio card clock the synchronization of data converter frame alignment across
tree designs. The device provides 14 low noise and configurable the system, from the FPGA or digital front end (DFE) to ADCs
outputs to offer flexibility in distributing clocks while applying and DACs through a large clock tree that may comprise multiple
frequency division, phase adjustment, cycle slip, and external clock generation and distribution ICs.
signal synchronization options.
There are two input paths on the HMC7043; one is for the clock
The HMC7043 generates up to seven DCLK and SYSREF clock signal that is distributed, and the other may be used as an external
pairs per the JESD204B interface requirements. The system synchronization signal. In typical JESD204B systems, serial data
designer can generate a lower number of DCLK and SYSREF converter interfaces, there may be a need to ensure that all clock
pairs, and configure the remaining output signal paths as signals that are sent to the data converters have phases which are
DCLKs, additional SYSREFs, or other reference clocks with controlled by an FPGA. By virtue of the RF SYNC input, the
independent phase and frequency adjustment. Frequency device ensures that output signals have a deterministic phase
adjustment can be accomplished by selecting the appropriate alignment to this synchronization input. The RF SYNC input
output divider values. can also implement multiple device clock trees by nesting more
One of the unique features of the HMC7043 is the independent than one HMC7043 to generate an even larger clock distribution
flexible phase management of each of the 14 channels. Using a network, while still maintaining phase alignment across the
combination of divider slip based, digital (coarse) and analog clock tree.
(fine) delay adjustments, each channel can be programmed to Offering excellent crosstalk, frequency isolation, and spurious
have a different phase offset. The phase adjustment capability performance, the device generates independent frequencies in
allows the designer to offset board flight time delay variations, both single-ended and differential formats including LVPECL,
match data converter sample windows, and meet JESD204B LVDS, CML, and CMOS, and different bias conditions to
synchronization challenges. The output signal path design of offset varying board insertion losses. The outputs can also be
the HMC7043 is implemented to ensure both linear phase programmed for ac or dc coupling and 50 Ω or 100 Ω internal
adjustment steps and minimal noise perturbation when phase and external termination options.
adjustment circuits are turned on.
The HMC7043 is programmed via a 3-wire serial port interface
(SPI). The HMC7043 is offered in a 48-lead, 7 mm × 7 mm,
LFCSP package with the exposed pad to ground.

Rev. B | Page 15 of 43
HMC7043 Data Sheet
DETAILED BLOCK DIAGRAM
CLK DISTRIBUTION PATH DIVIDER CLKIN
÷1, ÷2 CLKIN
COARSE DIVIDER CYCLE
DIGITAL SLIP/
DELAY (1 TO 4094)
CLKOUT0 SYNC
ANALOG
MUX DELAY RFSYNCIN
CLKOUT0 FUNDAMENTAL MODE SYSREF TIMER
RFSYNCIN

COARSE CYCLE SYNC/PULSOR GPI

DIVIDER SPI
DIGITAL SLIP/ CONTROL
SCLKOUT1 DELAY (1 TO 4094)
SYNC
MUX ANALOG
SCLKOUT1 DELAY
FUNDAMENTAL MODE TO LEAF DIVIDERS
COARSE DIVIDER CYCLE CYCLE DIVIDER COARSE
DIGITAL SLIP/ SLIP/ DIGITAL
(1 TO 4094) (1 TO 4094) DELAY
DELAY SYNC SYNC
CLKOUT2 ANALOG ANALOG CLKOUT8
MUX DELAY DELAY MUX
CLKOUT2 FUNDAMENTAL MODE FUNDAMENTAL MODE CLKOUT8

COARSE DIVIDER CYCLE CYCLE DIVIDER COARSE

DIGITAL SLIP/ SLIP/ DIGITAL
SCLKOUT3 (1 TO 4094) (1 TO 4094) DELAY SCLKOUT9
DELAY SYNC SYNC
MUX ANALOG ANALOG MUX
SCLKOUT3 DELAY DELAY SCLKOUT9
FUNDAMENTAL MODE FUNDAMENTAL MODE

COARSE DIVIDER CYCLE CYCLE DIVIDER COARSE

DIGITAL SLIP/ SLIP/ (1 TO 4094) DIGITAL
DELAY (1 TO 4094) SYNC DELAY
CLKOUT4 SYNC CLKOUT10
ANALOG ANALOG
MUX DELAY DELAY MUX
CLKOUT4 FUNDAMENTAL MODE FUNDAMENTAL MODE CLKOUT10

COARSE DIVIDER CYCLE CYCLE DIVIDER COARSE

DIGITAL SLIP/ SLIP/ DIGITAL
SCLKOUT5 (1 TO 4094) (1 TO 4094) DELAY SCLKOUT11
DELAY SYNC SYNC
MUX ANALOG ANALOG MUX
SCLKOUT5 DELAY DELAY SCLKOUT11
FUNDAMENTAL MODE FUNDAMENTAL MODE

COARSE DIVIDER CYCLE CYCLE DIVIDER COARSE

DIGITAL SLIP/ SLIP/ DIGITAL
(1 TO 4094) (1 TO 4094) DELAY
DELAY SYNC SYNC
CLKOUT6 ANALOG ANALOG CLKOUT12
MUX DELAY DELAY MUX
CLKOUT6 FUNDAMENTAL MODE FUNDAMENTAL MODE CLKOUT12

COARSE DIVIDER CYCLE CYCLE DIVIDER COARSE

DIGITAL SLIP/ SLIP/ DIGITAL
SCLKOUT7 (1 TO 4094) (1 TO 4094) DELAY SCLKOUT13
DELAY SYNC SYNC
MUX ANALOG ANALOG MUX
SCLKOUT7 DELAY DELAY SCLKOUT13
FUNDAMENTAL MODE FUNDAMENTAL MODE

DEVICE
LDOs SPI ALARM GENERATION CONTROL

13114-022
BGABYP1 LDOBYP2 SDATA SCLK SLEN GPIO RESET

Figure 23. Detailed Block Diagram

CLOCK INPUT NETWORK 2.8V

50Ω,
Input Termination Network—Common for All Input Buffers 100Ω,
4kΩ 1kΩ
The two clock and RFSYNC input buffers share similar architecture
and control features. The input termination network is configurable 5kΩ 1pF
50Ω,
to 100 Ω, 200 Ω, and 2 kΩ differentially. It is typically ac-coupled 100Ω,
50Ω 1kΩ
on the board, and uses the on-chip resistive divider to set the
13033-045

internal common-mode voltage, VCM, to 2.1 V.

Figure 24. On-Chip Termination Network for Clock and RFSYNC Buffers
By closing the 50 Ω termination switch (see Figure 24), the network
also can serve as the termination system for an LVPECL driver. Recommendations for Normal Use
Although the input termination network for the two clock and For both buffer types, unless there are extenuating circumstances
RFSYNC input buffers is identical, the buffer behind the in the application, use 100 Ω differential termination resistors
network is different. to control reflections, to use the on-chip dc bias network to set
the common mode level, and to externally ac couple the input
signals in. Do not use a receiver side dc termination of the
LVPECL signal.

Rev. B | Page 16 of 43
Data Sheet HMC7043
Single-Ended Operation • Fine phase control of synchronization channels with
The buffers can support a single-ended signal with slightly reduced respect to the DCLK channel
input sensitivity and bandwidth. If driving any of the buffers • Frequency coverage to satisfy typical clock rates in systems
single-ended, ac couple the unused leg of the buffer to ground • Skew between SYSREF and DCLK channels that is much
at the input of the die. less than a DCLK period
Maximum Signal Swing Considerations • Spur and crosstalk performance that does not impact
system budgets
The internal supplies to these input buffers are supplied directly
from 3.3 V. The ESD network and parasitic diodes can generally The HMC7043 output network supports the following recom-
shunt away excess power and protect the internal circuits mended features, which are sometimes critical in user applications:
(withstanding reference powers above 13 dBm). Nevertheless, • Deterministic synchronization of the output channels with
to protect from latch-up concerns, the signals on the reference respect to an external signal (RFSYNC), which allows
inputs must not exceed the 3.3 V internal supply. For a 2.1 V multichip synchronization and clean expansion to larger
common mode, 50 Ω single-ended source, this allows ~1200 mV systems
of amplitude, or 11 dBm maximum reference power. • Pulse generator behavior to temporarily generate a
CLOCK OUTPUT NETWORK synchronization pulse stream at a user request
The HMC7043 is a high performance clock buffer, is appropriate • The flexibility to define unused JESD204B SYSREF and
for JESD204B data converters, and much of the uniqueness of a DCLK channels for other purposes
JESD204B clock generation chip relates to the array of output • Glitchless phase control of signals relative to each other
channels. In this device, the output network requirements include • 50% duty cycle clocks with odd division ratios
• Multimode output buffers with a variety of swings and
• A large number of device clock (DCLK) and synchronization
termination options
(SYSREF) channels
• Skew between all channels is much less than a DCLK period
• Very good phase noise floor of the DCLK channels that can
be connected to critical data converter sample clock inputs • Adjustable performance vs. power consumption for less
sensitive clock channels
• Deterministic phase alignment between all output channels
relative to one another
SYSREF INPUT NETWORK

RF
SYNC

D Q

RESET

SYSREF TIMER
CLKIN PATH
SYNC/PULSE GENERATOR PULSE GENERATOR REQUEST (FROM SPI OR GPI PIN)
CONTROL SYNC REQUEST (FROM SPI OR GPI PIN)

SYNC_FSM_STATE OUTPUT CHANNEL ×14

LEAF CONTROLLER

CLOCK DIGITAL
GATING DIVIDER DELAY AND
RETIME
13114-023

Figure 25. Clock Output Network Simplified Diagram

Rev. B | Page 17 of 43
HMC7043 Data Sheet
Each of the 14 output channels are logically identical. The only To support divider synchronization, arbitrary phase slips, and
distinction between the SYSREF and DCLK channels is in the pulse generator modes, the following blocks are included:
SPI configuration, and in how they are used. Each channel
• A clock gating stage pauses the clock for synchronization
contains independent dividers, phase adjustment, and analog
or slip operations
delay circuits. This combination provides the ultimate flexibility,
• An output channel leaf (×14) controller that manages slip,
cleanly accommodating nonJESD204B devices in the system.
synchronization, and pulse generators with information
In addition to the 14 output channel dividers, an internal SYSREF from the SYSREF finite state machine (FSM)
timer continually operates, and the synchronization of the output
channel dividers occurs deterministically with respect to this Each channel has an array of control signals. Some of the
timer, which the user can rephased deterministically by the user controls are described in Table 10.
through GPI or SPI or deterministically by using the RFSYNCIN/ System wide broadcast signals can be triggered from the SPI or
RFSYNCIN differential pins. general-purpose input (GPI) port to issue a SYNC command
(to align dividers to the system internal SYSREF timer), issue a
The pulse generator functionality of the JESD204B standard
pulse generator stream, (temporarily exporting SYSREF signals to
involves temporarily generating SYSREF output pulses, with
receivers), or to cause the dividers to slip a number of clock
appropriate phasing, to downstream devices. The centralized
input cycles to adjust their phases.
SYSREF timer and the associated SYNC/pulse generator control
manage the process of enabling the intended SYSREF channels, Individual dividers can be made sensitive to these events by
phasing them, and then disabling them for signal integrity and adjusting their slip enable, SYNC enable, and Start-Up Mode[1:0]
power saving advantages. configuration, as described in Table 11.
Basic Output Divider Channel When output buffers are configured in CMOS mode and phase
alignment is required among the outputs, additional multislip
Each of the 14 output channels are logically identical, and support
delays must be issued for Channel 0, Channel 3, Channel 5,
divide ratios from 1 to 4094. The supported odd divide ratios
Channel 6, Channel 9, Channel 10, and Channel 13. The value
(1, 3, or 5) have 50.0% duty cycle. The only distinction between
of the delay must be as large as half of the selected divider ratio.
a SYSREF channel and a device clock channel is in the SPI
Note that this requirement of having additional multislip delays
configuration and the typical usage of a given channel.
is not needed when the channels are used in LVPECL, CML, or
For basic functionality and phase control, each output path LVDS mode.
consists of the following:
If a channel is configured to behave as a pulse generator, to
• Divider—generates the logic signal of the appropriate temporarily power up and power down according to the GPI
frequency and phase and SPI pulse generator commands; additional controls define the
• Digital phase adjust—adjusts the phase of each channel in behavior outside of the pulse generator chain (see Table 12).
increments of ½ clock input cycles
Each divider has an additional phase offset register that adjusts
• Retimer—a low noise flip flop to retime the channel,
the start phase or influences the behavior of slip events sent via
removing any accumulated jitter
the SPI (see Table 13).
• Analog fine delay—provides a number of ~25 ps delay steps
Table 14 outlines the typical configuration combinations for a
• Selection mux—selects the fundamental, divider, analog
DCLK channel relative to a SYSREF synchronization channel.
delay, or an alternate path
Note that other combinations are possible. Synchronization of
• Multimode output buffer—low noise LVDS, CML, CMOS,
downstream devices can be managed manually, or by using the
or LVPECL
pulse generator functionality of the HMC7043. See the Typical
The digital phase adjuster and retimer launch on either clock Programming Sequence section for more information about the
phase of the clock input, depending on the digital phase adjust differences between the two methods.
setpoint (Coarse Digital Delay[4:0]).

Rev. B | Page 18 of 43
Data Sheet HMC7043
Table 10. Basic Divider Controls
Bit Name Description
Channel Enable Channel enable. If set to 0, the channel is disabled. If set to 1, the channel can be enabled depending on the
settings of the Start-Up Mode[1:0], Seven Pairs of 14-Channel Outputs Enable[6:0], and sleep mode bits.
12-Bit Channel Divider[11:0] Divide ratio.12-bit divide ratio, split across two words (MSB and LSB). Set to 0 if not using the channel divider
(Output Mux Selection[1:0] = 2 or 3)
High Performance Mode High performance mode. Adjusts the divider and buffer bias to improve swing/phase noise slightly at the expense of
power. The performance advantage is about 1 dB, and the current penalty depends on whether the divider is enabled.
Coarse Digital Delay[4:0] Digital delay. Adjusts the phase of the divider signal by up to 17 ½ cycles of the clock input. This circuit is
practically noiseless; however, note that a low amount of additional current is consumed.
Fine Analog Delay[4:0] Analog delay. Adjusts the delay of the divider signal in increments of ~25 ps. Set Output Mux Selection[1:0] = 1
to expose this channel. Exposing this channel causes phase noise degradation of up to 12 dB; therefore, do not use
on noise sensitive DCLK channels.
Output Mux Selection[1:0] Output mux selection. 00 = divider channel, 01 = analog delay, 10 = other channel of pair, 11 = input clock.
Fundamental mode can be generated with the divider (12-Bit Channel Divider[11:0] = 1), or via Output Mux
Selection[1:0] = 10 and 12-Bit Channel Divider[11:0] = 0. Because the divider path consumes power and degrades
phase noise slightly, the fundamental mux path is recommended, but at a cost of a deterministic skew vs. a path
that is divider-based. Such skew can be compensated for with delay (digital and analog) on the divider-based
path.
Force Mute[1] Force mute. If 1, and the channel enable is true (channel enable = 1) and Force Mute[0] = 0, the signal just
before the output buffer is asynchronously forced to Logic 0. To see the effect of this, the output buffer must
be enabled, which is dependent on the dynamic driver enable and Start-Up Mode[1:0] controls.

Table 11. Channel Features

Bit Name Description
Slip Enable Slip enable. A channel processes slip requests broadcast from the SPI or GPI (or, if multislip enable = 1, initiated
following a recognized SYNC or pulse generator startup).
SYNC Enable SYNC enable. A channel processes synchronization events broadcast from the SPI or GPI or due to SYNC/RF SYNC (via
the SYSREF FSM) to reset the phase. This signal can be safely toggled on and off to adjust SYNC sensitivity without
risking the state of the divider.
Start-Up Mode[1:0] 00 = asynchronous (normal mode). The divider starts with uncontrolled phase. It is rephased by SYNC events if SYNC
enable = 1.
11 = dynamic (pulse generator mode). The divider monitors pulse generator events broadcast from the SYSREF
controller. It is powered up just before a pulse generator chain, rephased at the start, and powered down after the
pulse generator chain. This mode is only supported for divide ratios > 31.

Table 12. Pulse Generator Mode Behavior Options

Bit Name Description
Dynamic Driver Enable Dynamic output buffer enable (pulse generator mode only).
0 = the output buffer is simply enabled/disabled with the main channel enable.
1 = the output buffer enable is controlled together with the channel divider, which allows it to dynamically power
down outside pulse generator events.
Force Mute[0] Idle at Logic 0 (pulse generator mode only).
1 = if the buffer remains on outside of the pulse generator chain, drive to Logic 0.
0 = if the buffer remains on outside of the pulse generator chain, allow the outputs to float naturally to
approximately VCM.

Rev. B | Page 19 of 43
HMC7043 Data Sheet
Table 13. Multislip Configuration
Bit Name Description
Multislip Enable Allow multislip. This bit determines whether the 12-Bit Multislip Digital Delay[11:0] parameter is used
for multislip operations. Note that a multislip operation is automatically started following a SYNC or
pulse generator initiation if multislip enable = 1.
12-Bit Multislip Digital Delay[11:0] Multislip amount. If multislip enable = 1, any slip events (caused by GPI, SPI, SYNC, or pulse generator
events) repeat the number of times set by 12-Bit Multislip Digital Delay[11:0] to adjust the phase by the
multislip amount × clock input cycles. A value of 0 is not supported if multislip enable = 1. Note that
phase slips are free from a noise and current perspective, that is, no additional power is needed and
with no noise degradation, but they take some time to occur. Each slip operation takes a number of
nanoseconds to complete, and thus the phases do not necessarily stabilize immediately. An alarm is
available for the user to indicate when all phase operations are complete.

Table 14. Typical Configuration Combinations

Bit Name DCLK Pulse Generator SYSREF Manual SYSREF NonJESD204B
12-Bit Channel Divider[11:0] Small Big Big Any
Start-Up Mode-Bit Normal Pulse generator Normal Normal
Fine Analog Delay[4:0] Off Optional Optional Off
Coarse Digital Delay[4:0] Optional Optional Optional Optional
Slip Enable Optional Optional Optional Optional
Multislip Enable Optional Off Optional Optional
High Performance Mode Optional Off Off Optional
Sync Enable On On On Optional
Dynamic Driver Enable Don’t care On Don’t care Don’t care
Force Mute[1:0] Don’t care On Don’t care Don’t care

Synchronization FSM/Pulse Generator Timing Figure 27 shows the start-up behavior of an example divider
Figure 25 show a block diagram of the interface of the SYNC/ that is configured as a pulse generator, with a period matching
pulse generator control to the divider channels and the internal the internal SYSREF period.
SYSREF timer. The startup of the pulse stream occurs a fixed number of clock
The SYSREF timer counts in periods defined by SYSREF input cycles after the FSM transitions to the start phase. Disabling
Timer[11:0], a 12-bit setting from the SPI. The SYSREF the pulse generator stream where the logic path is forced to zero
timer sequences the enable, reset, and startup, and disables comes from a combinational path directly from the FSM.
the downstream dividers in the event of sync or pulse generator Because the divider has the option for nearly arbitrary phase
requests. Program the SYSREF timer count to a submultiple of adjustment, the stop condition can arrive when the pulse stream
the lowest output frequency in the clock network, and never is a Logic 1 and create a runt pulse.
faster than 4 MHz. To synchronize the divider channels, it is
For phase offsets of zero to (50% − 8) clock input cycles, and at
recommended, though not required, that the SYSREF Timer[11:0] clock input frequencies <3 GHz, this condition is met naturally
bits be set to a related frequency that is either a factor or
within the design. For clock input frequencies >3 GHz, it is
multiple of other frequencies on the IC.
recommended to use digital delay or slip offsets to increase the
The pulse generator is defined with respect to the periods of natural phase offset and avoid the stress conditions.
this SYSREF timer, not with respect to the output period. This The situation is avoided by never applying phase offset more
behavior of the pulse generator leads to a timing constraint that than (50% − 8) clock input cycles to an output channel
must be considered to prevent any runt pulses from affecting
configured as a pulse generator.
the pulse generator stream.

Rev. B | Page 20 of 43
Data Sheet HMC7043
RF_SYNC

RESET

NOTIFY CHANNEL FSM

PULSE
SYNC GENERATOR WHAT TYPE OF EVENT
SETUP SETUP IS COMING

CLEAR POWER DIVIDERS/SYNC BLOCKS,

PAUSE BLOCKS, RESET LATCHES

WAIT REMOVE LATCH RESET,

PREPARE TO START CLOCKS
SYNC
REQUEST START CLOCKS,
STARTUP WITH CLEAN TIMING,
SMALL PIPELINE DELAY

PULSE WAIT UNTIL THE NUMBER OF

GENERATOR PULSE GENERATOR CYCLES
TIMEOUT?
EXPIRES

DONE REMOVE POWER

13114-125
PULSE
GENERATOR
REQUEST

Figure 26. Synchronization FSM Flowchart

FSM STATE STARTUP PULSE GENERATOR = 2 DONE

DIVIDER CHANNEL

IF MUTE SIGNAL ARRIVES QUICKLY

RELATIVE TO SIGNAL TRAIN,
FIXED NUMBER OF CLOCK INPUT CYCLES NO RUNT PULSE
FROM STATE CHANGE TO STARTUP, AND
ANY INTENTIONAL DIGITAL/ANALOG OFFSET

FSM STATE STARTUP PULSE GENERATOR = 2 DONE

DIVIDER CHANNEL
13114-126

IF CONTROL IS TOO LATE

RELATIVE TO SIGNAL TRAIN,
THERE IS A RUNT PULSE

Figure 27. Start-Up Behavior of an Example Divider Configured as a Pulse Generator

Rev. B | Page 21 of 43
HMC7043 Data Sheet
Clock Grouping, Skew, and Crosstalk Table 15. Supply Pin Clock Grouping by Location
Although the output channels are logically independent, for Supply Pin Location Clock Group Channel
physical reasons, they are first grouped into pairs, called clock VCC2_OUT Southwest 1 2
groups. Each clock group shares a reference, an input buffer, 3
and a SYNC retime flip flop originating from the clock VCC3_OUT South 2 4
distribution network. 5
The second level of grouping is according to the supply pin. Clock 3 6
Group 1 (Channel 2 and Channel 3) is on an independent supply, 7
and the other supply pins are each responsible for two clock groups. VCC6_OUT Northeast 4 8
9
As the output channels are more tightly coupled (by sharing a
5 10
clock group or by sharing a supply pin), the skew is minimized.
11
However, the isolation between those channels suffers.
VCC7_OUT Northwest 6 12
Table 15 shows the clock grouping by location, and Table 16 13
show the typical skew and isolation that can be expected and how 0 0
it scales with distance between output channels. 1
Isolation improves as either the aggressor or the affected
frequencies decrease. Nevertheless, for particularly important
Table 16. Typical Skew and Isolation vs. Distance
clock channels where spurious tones must be minimized, carefully
Typical 1 GHz Isolation,
consider their frequency and channel configurations to isolate Distance Skew (ps) Differential (dB)
continuously running frequencies onto different supply domains. Distant Supply Group ±20 90 to 100
Channels configured as pulse generators are normally not an
Closest Neighbor on ±15 70
issue, because they are disabled during normal operation. Different Supply Group
Shared Supply ±10 60
Same Clock Group ±10 45

Rev. B | Page 22 of 43
Data Sheet HMC7043
Output Buffer Details
NORTHWEST NORTHEAST

SCLKOUT13
SCLKOUT13

SCLKOUT11
SCLKOUT11
CLKOUT12
CLKOUT12

CLKOUT10
CLKOUT10

VCC6_OUT
VCC7_OUT

CLKOUT8
CLKOUT8
CLKOUT0 SCLKOUT9
CLKOUT0 SCLKOUT9

SCLKOUT1
GPIO
SCLKOUT1

RESET SPI

VCC5_
BGAPBYP1
SYSREF

LDOBYP2 RFSYNCIN
RFSYNCIN

VCC1_
CLKDIST
VCC4_
CLKIN
SCLKOUT3
SCLKOUT3

CLKOUT2 CLKIN
CLKOUT2 CLKIN
SCLKOUT5
SCLKOUT5

SCLKOUT7
SCLKOUT7
VCC2_OUT

VCC3_OUT
CLKOUT4
CLKOUT4

CLKOUT6
CLKOUT6

13114-026
SOUTHWEST SOUTH

Figure 28. Clock Grouping

Figure 28 shows the clock groups by supply pin location on the the user to identify quickly that the desired SYSREF and device
package. With appropriate supply pin bypassing, the spurious clock states are presented at the outputs of the HMC7043.
noise of the outputs is improved. The user has the flexibility to assign the SYSREF valid interrupt to
Table 15 describes how the supply pins of each of the 14 clock a GPO pin or to use a software flag, set via Register 0x007D, Bit 2,
channels are connected within the seven clock groups. Clock which the user may poll as necessary. The flag notifies the user
channels that are closest to each other have the best channel to when the system is configured and operating in the desired
channel skew performance, but they also have the lowest isolation state, or conversely when it is not ready.
from each other. Select critical signals that require high isolation
TYPICAL PROGRAMMING SEQUENCE
from each other from groups with distant supply pin locations.
An example of the expected isolation and channel to channel To initialize the HMC7043 to an operational state, use the
skew performance of the HMC7043 at 1 GHz is provided in following programming procedure:
Table 16. 1. Connect the HMC7043 to the rated power supplies. No
SYSREF Valid Interrupt specific power supply sequencing is necessary.
2. Release the hardware reset by switching from Logic 1 to
One of the challenges in a JESD204B system is to control and
Logic 0 when all supplies are stable.
minimize the latency from the primary system controller IC,
3. Load the configuration updates (provided by Analog
typically an ASIC or FPGA, to the data converters. To estimate
Devices, Inc.) to specific registers (see Table 40).
the correct amount of latency in the system, the designer must
4. Program the SYSREF timer. Set the divide ratio (a submultiple
know the time required for a master clock generator like the
of the lower output channel frequency). Set the pulse
HMC7043 to provide the correct output phases at each output
generator mode configuration, for example, selecting the
channel after receiving the synchronization request. Typically, a
level sensitivity option and the number of pulses desired.
period of time is required on the device to implement the
5. Program the output channels. Set the output buffer modes
change requests on the outputs due to internal state machine
(for example, LVPECL, CML, and LVDS). Set the divide
cycles, data transfers, and any propagation delays. The SYSREF
ratio, channel start-up mode, coarse/analog delays, and
valid interrupt is a function to notify the user that the correct
performance modes.
output settings and phase relationships are established, allowing
6. Ensure the clock input signal are provided to CLKIN.

Rev. B | Page 23 of 43
HMC7043 Data Sheet
7. Issue a software restart to reset the system and initiate To resynchronize one or more of the JESD204B slaves, use the
calibration. Toggle the restart dividers/FSMs bit to 1 and following procedure:
then back to 0. 1. Set the channel enable and SYNC enable bit of the SYSREF
8. Send a sync request via the SPI (set the reseed request bit) channel of interest.
to align the divider phases and send any initial pulse 2. To prevent an output channel from responding to a sync
generator stream. request, disable the SYNC enable mask of each channel so
9. Wait six SYSREF periods (6 × SYSREF Timer[11:0]) to that it continues to run normally without a phase adjustment.
allow the outputs to phase appropriately (~3 μs in typical 3. Issue a reseed request to phase the SYSREF channel
configurations). properly with respect to the DCLK.
10. Confirm that the outputs have all reached their phases by 4. Enable the JESD204B slave sensitivity to the SYSREF channel.
checking that the clock outputs phases status bit = 1. 5. If the SYSREF channel is in pulse generator mode, wait at
11. At this time, initialize any other devices in the system. least 20 SYSREF periods from Step 3, and issue a pulse
Configure the slave JESD204B devices in the system to generator request.
operate with the SYSREF signal outputs from the HMC7043.
The SYSREF channels from the HMC7043 can be on either POWER SUPPLY CONSIDERATIONS
asynchronously or dynamically, and may temporarily turn The output buffers are susceptible to supply with a certain
on for a pulse generator stream. extent. The output buffers are also susceptible to supply noise,
12. Slave JESD204B devices in the system must be configured but to a lesser extent. A noise tone of −60 dBV at a 40 MHz
to monitor the input SYSREF signal exported from the offset results in a −90 dBc tone at the output of the buffers in
HMC7043. At this point, SYSREF channels from the CML mode and −85 dBc in LVPECL mode. This result is a
HMC7043 can either be on asynchronously (running) or on relatively flat frequency response, and these numbers are
dynamically (temporarily turn on for a pulse generator train). measured differentially. Phase noise/spurs caused by supply
13. When all JESD204B slaves are powered and ready, send a noise on the output buffers do not scale with output frequency.
pulse generator request to send out a pulse generator chain on
Table 17 lists the supply network of the HMC7043 by pin, showing
any SYSREF channels programmed for pulse generator mode.
the relevant functional blocks. Three different usage profiles are
The system is initialized. defined for the network, not including the output channel
For power savings and the reduction of the cross coupling of supplies, which are accounted for separately.
frequencies on the HMC7043, shut down the SYSREF channels. The values listed under Profile 0 to Profile 2 in Table 17 and
1. Program each JESD204B slave to ignore the SYSREF input Table 18 are the typical currents of that block or feature. If a
channel. number is not listed in a profile column, a typical profile does
2. On the HMC7043, disable the individual channel enable bits not exist for that block or feature, but the user can mix and
of each SYSREF channel. match features outside of the profile list, and can determine
what the power consumption is going to be given the current
listings per feature.

Rev. B | Page 24 of 43
Data Sheet HMC7043
Table 17. Supply Network of the HMC7043 by Pin for VCC1_CLKDIST, VCC4_CLKIN, and VCC5_SYSREF
Profile 1
Circuit Block Comment Typical Current (mA) 0 1 2
VCC1_CLKDIST
Regulator to 1.8 V, Bypassed on LDOBYP2 2 2 2 2
SYSREF Timer 1 1
GPO Driver in High Speed Mode 2
Clock Input Distribution Network Minimum possible value 84 8 84 34
Sync Retiming Network Minimum possible value 3 8
Subtotal for VCC1_CLKDIST 10 87 36
VCC4_CLKIN
CLKIN/CLKIN Buffer 16 16 16
CLKIN/CLKIN Path Extra current for divide by 2 7
RFSYNCIN/RFSYNCIN 4 Retimer 3
RFSYNCIN/RFSYNCIN Buffer 9
Subtotal or VCC4_CLKIN 0 16 16
VCC5_SYSREF
SYSREF Input Network 11 11
SYSREF Counter Base 12 12
SYSREF Counter, SYNC Network 4
Subtotal for VCC5_SYSREF 27 0 23 0
Subtotal (Without Output Paths) 10 126 52

1
Profile 0 is sleep mode; Profile 1 is power-up defaults, SYSREF timer running and RFSYNC buffer is disabled; Profile2 is only one clock output enabled, SYSREF timer is
not running and RFSYNC buffer is disabled.
2
The current is highly dependent on rate of input/output and load of input/output traces. For heavily loaded traces, it is recommended to use a series resistance of
~100 Ωto minimize the IR drop on the internal regulator during transitions.
3
A temporary current only.
4
Transient current in synchronization mode, can be temporarily enabled when using external synchronization.

Rev. B | Page 25 of 43
HMC7043 Data Sheet

Table 18. Supply Network of the HMC7043 by Pin for the Clock Output Network
Profile 1
Per Output Channel Comment Typical Current (mA) 0 1 2 3 4
Digital Regulator and Other Sources 2.5 0.5 2.5 2.5 2.5 2.5
Buffer
LVPECL Including term currents 43 43 43 43
CML100
High Power Including term currents 31
Low Power 24
LVDS
High Power At 307 MHz 10 10
Low Power 8
CMOS At 100 MHz, both sections 25
Channel Mux Included 2
Different Power Modes Deleted 2 2 2 2
Digital Delay
Off Included2
Setpoint > 1 3 3 3
Analog Delay
Off Included2 0
Minimum Setting Glitchless mode enabled 9 9
Maximum Setting 9 9
Divider Logic
0 Not using divider path Included2 0 0
÷1 27
÷2 24
÷3 31
÷4 28
÷5 30
÷6 26
÷8 28
÷16 29 29
÷32 29
÷2044 29 29
SYNC Logic 3 4
Slip Logic3 4
Subtotal 2.5 48 87 13 89
1
Profile 0 is sleep mode; Profile 1 is fundamental mode; Profile 2 is SYSREF channel matched to fundamental mode; Profile 3 is LVDS—high power signal source from
other channel; and Profile 4 is worst case configuration for power consumption of a channel.
2
The base current consumption of the circuit (for example, mux) is included in the buffer typical current.
3
Currents only occur temporarily during a synchronization event.

Rev. B | Page 26 of 43
Data Sheet HMC7043

SERIAL CONTROL PORT

SERIAL PORT INTERFACE (SPI) CONTROL Typical Write Cycle
The HMC7043 can be controlled via the SPI using 24-bit A typical write cycle is shown in Figure 30 and occurs as follows:
registers and three pins: serial port enable (SLEN) serial data 1. The master (host) asserts both SLEN and SDATA to
input/output (SDATA), and serial clock (SCLK). indicate a read, followed by a rising edge SCLK. The slave
The 24-bit register, shown in Table 19, consists of the following: (HMC7043) reads SDIO on the first rising edge of SCLK
after SLEN. Setting SDATA low initiates a write.
• 1-bit read/write command
2. The host places the 2-bit multibyte field to be written to
• 2-bit multibyte field (W1, W0)
low (0) on the next two falling edges of SCLK. The
• 13-bit address field (A12 to A0) HMC7043 registers the 2-bit multibyte field on the next
• 8-bit data field (D7 to D0) two rising edges of SCLK.
Table 19. SPI Bit Map 3. The host places the13-bit address field (A12 to A0), MSB
first, on SDATA on the next 13 falling edges of SCLK. The
MSB LSB
HMC7043 registers the 13-bit address field (MSB first) on
Bit 23 Bit 22 Bit 21 Bits[20:8] Bits[7:0]
SDIO over the next 13 rising edges of SCLK.
R/W W1 W0 A12 to A0 D7 to D0
4. The host places the 8-bit data (D7 to D0) MSB first on the
next eight falling edges of SCLK. The HMC7043 register
Typical Read Cycle
the 8-bit data (D7 to D0) MSB first on the next eight rising
A typical read cycle is shown in Figure 29 and occurs as follows: edges of SCLK.
1. The master (host) asserts both SLEN and SDATA to 5. The final rising edge of SCLK performs the internal data
indicate a read, followed by a rising edge SCLK. The slave transfer into the register file, updating the configuration of
(HMC7043) reads SDATA on the first rising edge of SCLK the device.
after SLEN. Setting SDATA high initiates a read. 6. Deassertion of SLEN completes the register write cycle.
2. The host places the 2-bit multibyte field to be written to
low (0) on the next two falling edges of SCLK. The
HMC7043 registers the 2-bit multibyte field on the next
two rising edges of SCLK.
3. The host places the 13-bit address field (A12 to A0) MSB
first on SDATA on the next 13 falling edges of SCLK. The
HMC7043 registers the 13-bit address field (MSB first) on
SDATA over the next 13 rising edges of SCLK.
4. The host registers the 8-bit data on the next eight rising
edges of SCLK. The HMC7043 places 8-bit data (D7 to D0)
MSB first on the next eight falling edges of SCLK.
5. Deassertion of SLEN completes the register read cycle.

SCLK 1 2 3 4 5 16 17 18 24

SDATA X READ W1 W0 A12 A11 A0 D7 D6 D0

13114-128

SLEN

Figure 29. SPI Timing Diagram, Read Operation

1 2 3 4 5 16 17 18 24
SCLK

WRITE
SDATA X W1 W0 A12 A11 A0 D7 D6 D0
13114-129

SLEN

Figure 30. SPI Timing Diagram, Write Operation

Rev. B | Page 27 of 43
HMC7043 Data Sheet

CONTROL REGISTERS
CONTROL REGISTER MAP
Table 20. Control Register Map
Default
Address Value
(Hex) Register Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) (Hex)
Global Control
0x0000 Global soft reset Reserved Soft reset 0x00
control
0x0001 Global request Reseed High performance Reserved Reserved Mute output Pulse Restart Sleep mode 0x00
and mode request distribution path drivers generator dividers/
control request FSMs
0x0002 Reserved Multislip Reserved 0x00
request
0x0003 Global enable Reserved RF Reserved SYSREF Reserved Reserved 0x34
control reseeder timer
enable enable
0x0004 Reserved Seven Pairs of 14-Channel Outputs Enable[6:0] 0x7F
0x0005 Global mode Reserved 0x0F
and enable
control
0x0006 Global clear Reserved Clear alarms 0x00
alarms
0x0007 Global Reserved 0x00
0x0008 miscellaneous Reserved (scratchpad) 0x00
control
0x0009 Reserved 0x00
Input Buffer
0x000A CLKIN0/CLKIN0 Reserved Input Buffer Mode[3:0] Buffer enable 0x07
input buffer
control
0x000B CLKIN1/CLKIN1 Reserved Input Buffer Mode[3:0] Buffer enable 0x07
input buffer
control
GPIO/SDATA Control
0x0046 GPI control Reserved GPI Selection [2:0] GPI enable 0x00
0x0050 GPO control Reserved GPO Selection[4:0] GPO GPO enable 0x37
mode
0x0054 SDATA control Reserved SDATA SDATA enable 0x03
mode
SYSREF/SYNC
0x005A Pulse generator Reserved Pulse Generator Mode Selection[2:0] 0x00
control
0x005B SYNC control Reserved SYNC Reserved SYNC invert 0x04
retime polarity
0x005C SYSREF timer SYSREF Timer[7:0] (LSB) 0x00
0x005D control Reserved SYSREF Timer[11:8](MSB) 0x01
Clock Distribution Network
0x0064 Clock input Reserved Divide Low 0x00
control by 2 on frequency
clock clock input
input
0x0065 Analog delay Reserved Analog delay 0x00
common low power
control mode
Alarm Masks Register
0x0071 Alarm mask Reserved Sync Reserved Clock SYSREF Reserved 0x10
control request outputs sync
mask phase status
status mask
mask
Product ID Registers
0x0078 Product ID Product ID Value[7:0] (LSB)
0x0079 Product ID Value[15:8] (Mid)
0x007A Product ID Value[23:16] (MSB)

Rev. B | Page 28 of 43
Data Sheet HMC7043
Default
Address Value
(Hex) Register Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) (Hex)
Alarm Readback Status Registers
0x007B Readback Reserved Alarm signal
register
0x007D Alarm readback Reserved Sync Reserved Clock SYSREF Reserved
request outputs sync
status phases status
status
0x007F Alarm readback Reserved
SYSREF Status Register
0x0091 SYSREF status Reserved Channel SYSREF FSM State[3:0] 0x00
register outputs
FSM busy
Other Controls
0x0098 Reserved Reserved 0x00
0x0099 Reserved Reserved 0x00
0x009D Reserved Reserved 0xAA
0x009E Reserved Reserved 0xAA
0x009F Reserved Reserved 0x55
0x00A0 Reserved Reserved 0x56
0x00A2 Reserved Reserved 0x03
0x00A3 Reserved Reserved 0x00
0x00A4 Reserved Reserved 0x00
0x00AD Reserved Reserved 0x00
0x00B5 Reserved Reserved 0x00
0x00B6 Reserved Reserved 0x00
0x00B7 Reserved Reserved 0x00
0x00B8 Reserved Reserved 0x00
Clock Distribution
0x00C8 Channel High SYNC enable Slip enable Reserved Start-Up Mode[1:0] Multislip Channel 0xF3
Output 0 performance enable enable
control mode
0x00C9 12-Bit Channel Divider[7:0] (LSB) 0x04
0x00CA Reserved 12-Bit Channel Divider[11:8] (MSB) 0x00
0x00CB Reserved Fine Analog Delay[4:0] 0x00
0x00CC Reserved Coarse Digital Delay[4:0] 0x00
0x00CD 12-Bit Multislip Digital Delay[7:0] (LSB) 0x00
0x00CE Reserved 12-Bit Multislip Digital Delay[11:8] (MSB) 0x00
0x00CF Reserved Output Mux Selection[1:0] 0x00
0x00D0 Idle at Zero[1:0] Dynamic Driver Mode[1:0] Reserved Driver Impedance[1:0] 0x01
driver
enable
0x00D2 Channel High SYNC enable Slip enable Reserved Start-Up Mode[1:0] Multislip Channel 0xFD
Output 1 performance enable enable
control mode
0x00D3 12-Bit Channel Divider[7:0] (LSB) 0x00
0x00D4 Reserved 12-Bit Channel Divider[11:8] (MSB) 0x01
0x00D5 Reserved Fine Analog Delay[4:0] 0x00
0x00D6 Reserved Coarse Digital Delay[4:0] 0x00
0x00D7 12-Bit Multislip Digital Delay[7:0] (LSB) 0x00
0x00D8 Reserved 12-Bit Multislip Digital Delay[11:8] (MSB) 0x00
0x00D9 Reserved Output Mux Selection[1:0] 0x00
0x00DA Idle at Zero[1:0] Dynamic Driver Mode[1:0] Reserved Driver Impedance[1:0] 0x30
driver
enable

Rev. B | Page 29 of 43
HMC7043 Data Sheet
Default
Address Value
(Hex) Register Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) (Hex)
0x00DC Channel High SYNC enable Slip enable Reserved Start-Up Mode[1:0] Multislip Channel 0xF3
Output 2 performance enable enable
control mode
0x00DD 12-Bit Channel Divider[7:0] (LSB) 0x08
0x00DE Reserved 12-Bit Channel Divider[11:8] (MSB) 0x00
0x00DF Reserved Fine Analog Delay[4:0] 0x00
0x00E0 Reserved Coarse Digital Delay[4:0] 0x0
0x00E1 12-Bit Multislip Digital Delay[7:0] (LSB) 0x00
0x00E2 Reserved 12-Bit Multislip Digital Delay[11:8] (MSB) 0x00
0x00E3 Reserved Output Mux Selection[1:0] 0x00
0x00E4 Idle at Zero[1:0] Dynamic Driver Mode[1:0] Reserved Driver Impedance[1:0] 0x01
driver
enable
0x00E6 Channel High SYNC enable Slip enable Reserved Start-Up Mode[1:0] Multislip Channel 0xFD
Output 3 performance enable enable
control mode
0x00E7 12-Bit Channel Divider[7:0] (LSB) 0x00
0x00E8 Reserved 12-Bit Channel Divider[11:8] (MSB) 0x01
0x00E9 Reserved Fine Analog Delay[4:0] 0x00
0x00EA Reserved Coarse Digital Delay[4:0] 0x00
0x00EB 12-Bit Multislip Digital Delay[7:0] (LSB) 0x00
0x00EC Reserved 12-Bit Multislip Digital Delay[11:8] (MSB) 0x00
0x00ED Reserved Output Mux Selection[1:0] 0x00
0x00EE Idle at Zero[1:0] Dynamic Driver Mode[1:0] Reserved Driver Impedance[1:0] 0x30
driver
enable
0x00F0 Channel High SYNC enable Slip enable Reserved Start-Up Mode[1:0] Multislip Channel 0xF3
Output 4 performance enable enable
control mode
0x00F1 12-Bit Channel Divider[7:0] (LSB) 0x02
0x00F2 Reserved 12-Bit Channel Divider[11:8] (MSB) 0x00
0x00F3 Reserved Fine Analog Delay[4:0] 0x00
0x00F4 Reserved Coarse Digital Delay[4:0] 0x00
0x00F5 12-Bit Multislip Digital Delay[7:0] (LSB) 0x00
0x00F6 Reserved 12-Bit Multislip Digital Delay[11:8] (MSB) 0x00
0x00F7 Reserved Output Mux Selection[1:0] 0x00
0x00F8 Idle at Zero[1:0] Dynamic Driver Mode[1:0] Reserved Driver Impedance[1:0] 0x01
driver
enable
0x00FA Channel High SYNC enable Slip enable Reserved Start-Up Mode[1:0] Multislip Channel 0xFD
Output 5 performance enable enable
control mode
0x00FB 12-Bit Channel Divider[7:0] (LSB) 0x00
0x00FC Reserved 12-Bit Channel Divider[11:8] (MSB) 0x01
0x00FD Reserved Fine Analog Delay[4:0] 0x00
0x00FE Reserved Coarse Digital Delay[4:0] 0x00
0x00FF 12-Bit Multislip Digital Delay[7:0] (LSB) 0x00
0x0100 Reserved 12-Bit Multislip Digital Delay[11:8] (MSB) 0x00
0x0101 Reserved Output Mux Selection[1:0] 0x00
0x0102 Idle at Zero[1:0] Dynamic Driver Mode[1:0] Reserved Driver Impedance[1:0] 0x30
driver
enable

Rev. B | Page 30 of 43
Data Sheet HMC7043
Default
Address Value
(Hex) Register Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) (Hex)
0x0104 Channel High SYNC enable Slip enable Reserved Start-Up Mode[1:0] Multislip Channel 0xF3
Output 6 performance enable enable
control mode
0x0105 12-Bit Channel Divider[7:0] (LSB) 0x02
0x0106 Reserved 12-Bit Channel Divider[11:8] (MSB) 0x00
0x0107 Reserved Fine Analog Delay[4:0] 0x00
0x0108 Reserved Coarse Digital Delay[4:0] 0x00
0x0109 12-Bit Multislip Digital Delay[7:0] (LSB) 0x00
0x010A Reserved 12-Bit Multislip Digital Delay[11:8] (MSB) 0x00
0x010B Reserved Output Mux Selection[1:0] 0x00
0x010C Idle at Zero[1:0] Dynamic Driver Mode[1:0] Reserved Driver Impedance[1:0] 0x01
driver
enable
0x010E Channel High SYNC enable Slip enable Reserved Start-Up Mode[1:0] Multislip Channel 0xFD
Output 7 performance enable enable
control mode
0x010F 12-Bit Channel Divider[7:0] (LSB) 0x00
0x0110 Reserved 12-Bit Channel Divider[11:8] (MSB) 0x01
0x0111 Reserved Fine Analog Delay[4:0] 0x00
0x0112 Reserved Coarse Digital Delay[4:0] 0x00
0x0113 12-Bit Multislip Digital Delay[7:0] (LSB) 0x00
0x0114 Reserved 12-Bit Multislip Digital Delay[11:8] (MSB) 0x00
0x0115 Reserved Output Mux Selection[1:0] 0x00
0x0116 Idle at Zero[1:0] Dynamic Driver Mode[1:0] Reserved Driver Impedance[1:0] 0x30
driver
enable
0x0118 Channel High SYNC enable Slip enable Reserved Start-Up Mode[1:0] Multislip Channel 0xF3
Output 8 performance enable enable
control mode
0x0119 12-Bit Channel Divider[7:0] (LSB) 0x02
0x011A Reserved 12-Bit Channel Divider[11:8] (MSB) 0x00
0x011B Reserved Fine Analog Delay[4:0] 0x00
0x011C Reserved Coarse Digital Delay[4:0] 0x00
0x011D 12-Bit Multislip Digital Delay[7:0] (LSB) 0x00
0x011E Reserved 12-Bit Multislip Digital Delay[11:8] (MSB) 0x00
0x011F Reserved Output Mux Selection[1:0] 0x00
0x0120 Idle at Zero[1:0] Dynamic Driver Mode[1:0] Reserved Driver Impedance[1:0] 0x01
driver
enable
0x0122 Channel High SYNC enable Slip enable Reserved Start-Up Mode[1:0] Multislip Channel 0xFD
Output 9 performance enable enable
control mode
0x0123 12-Bit Channel Divider[7:0] (LSB) 0x00
0x0124 Reserved 12-Bit Channel Divider[11:8] (MSB) 0x01
0x0125 Reserved Fine Analog Delay[4:0] 0x00
0x0126 Reserved Coarse Digital Delay[4:0] 0x00
0x0127 12-Bit Multislip Digital Delay[7:0] (LSB) 0x00
0x0128 Reserved 12-Bit Multislip Digital Delay[11:8] (MSB) 0x00
0x0129 Reserved Output Mux Selection[1:0] 0x00
0x012A Idle at Zero[1:0] Dynamic Driver Mode[1:0] Reserved Driver Impedance[1:0] 0x30
driver
enable

Rev. B | Page 31 of 43
HMC7043 Data Sheet
Default
Address Value
(Hex) Register Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) (Hex)
0x012C Channel High SYNC enable Slip enable Reserved Start-Up Mode[1:0] Multislip Channel 0xF3
Output 10 performance enable enable
control mode
0x012D 12-Bit Channel Divider[7:0] (LSB) 0x02
0x012E Reserved 12-Bit Channel Divider[11:8] (MSB) 0x00
0x012F Reserved Fine Analog Delay[4:0] 0x00
0x0130 Reserved Coarse Digital Delay[4:0] 0x00
0x0131 12-Bit Multislip Digital Delay[7:0] (LSB) 0x00
0x0132 Reserved 12-Bit Multislip Digital Delay[11:8] (MSB) 0x00
0x0133 Reserved Output Mux Selection[1:0] 0x00
0x0134 Idle at Zero[1:0] Dynamic Driver Mode[1:0] Reserved Driver Impedance[1:0] 0x01
driver
enable
0x0136 Channel High SYNC enable Slip enable Reserved Start-Up Mode[1:0] Multislip Channel 0xFD
Output 11 performance enable enable
control mode
0x0137 12-Bit Channel Divider[7:0] (LSB) 0x00
0x0138 Reserved 12-Bit Channel Divider[11:8] (MSB) 0x01
0x0139 Reserved Fine Analog Delay[4:0] 0x00
0x013A Reserved Coarse Digital Delay[4:0] 0x00
0x013B 12-Bit Multislip Digital Delay[7:0] (LSB) 0x00
0x013C Reserved 12-Bit Multislip Digital Delay[11:8] (MSB) 0x00
0x013D Reserved Output Mux Selection[1:0] 0x00
0x013E Idle at Zero[1:0] Dynamic Driver Mode[1:0] Reserved Driver Impedance[1:0] 0x30
driver
enable
0x0140 Channel High SYNC enable Slip enable Reserved Start-Up Mode[1:0] Multislip Channel 0xF3
Output 12 performance enable enable
control mode
0x0141 12-Bit Channel Divider[7:0] (LSB) 0x10
0x0142 Reserved 12-Bit Channel Divider[11:8] (MSB) 0x00
0x0143 Reserved Fine Analog Delay[4:0] 0x00
0x0144 Reserved Coarse Digital Delay[4:0] 0x00
0x0145 12-Bit Multi-Slip Digital Delay[7:0] (LSB) 0x00
0x0146 Reserved 12-Bit Multislip Digital Delay[11:8] (MSB) 0x00
0x0147 Reserved Output Mux Selection[1:0] 0x00
0x0148 Idle at Zero[1:0] Dynamic Driver Mode[1:0] Reserved Driver Impedance[1:0] 0x01
driver
enable
0x014A Channel High SYNC enable Slip enable Reserved Start-Up Mode [1:0] Multislip Channel 0xFD
Output 13 performance enable enable
control mode
0x014B 12-Bit Channel Divider[7:0] (LSB) 0x00
0x014C Reserved 12-Bit Channel Divider[11:8] (MSB) 0x01
0x014D Reserved Fine Analog Delay[4:0] 0x00
0x014E Reserved Coarse Digital Delay[4:0] 0x00
0x014F 12-Bit Multislip Digital Delay[7:0] (LSB) 0x00
0x0150 Reserved 12-Bit Multislip Digital Delay[11:8] (MSB) 0x00
0x0151 Reserved Output Mux Selection[1:0] 0x00
0x0152 Idle at Zero[1:0] Dynamic Driver Mode[1:0] Reserved Driver Impedance[1:0] 0x30
driver
enable

Rev. B | Page 32 of 43
Data Sheet HMC7043
CONTROL REGISTER MAP BIT DESCRIPTIONS
Global Control (Register 0x0000 to Register 0x0009)
Table 21. Global Soft Reset Control
Address Bits Bit Name Settings Description Access
0x0000 [7:1] Reserved Reserved RW
0 Soft reset Resets all registers, dividers, and FSMs to default values

Table 22. Global Request and Mode Control

Address Bits Bit Name Settings Description Access
0x0001 7 Reseed request Requests the centralized resync timer and FSM to reseed any of the output RW
dividers that are programmed to pay attention to sync events. This signal is
rising edge sensitive, and is only acknowledged if the resync FSM has
completed all events (has finished any previous pulse generator and/or
sync events, and is in the done state (SYSREF FSM State[3:0] = 0010).
6 High performance High performance distribution path select. The clock distribution path
distribution path has two modes.
0 Power priority.
1 Noise priority. Provides the option for better noise floors on the divided
output signals.
5 Reserved Reserved.
4 Reserved Reserved.
3 Mute output drivers Mutes the output drivers (dividers still run in the background).
2 Pulse generator request Asks for a pulse stream (see the Typical Programming Sequence section).
1 Restart dividers/FSMs Resets all dividers and FSMs. Does not affect configuration registers.
0 Sleep mode Forces shutdown. Output network, and I/O buffers are disabled.
0x0002 [7:2] Reserved Reserved. RW
1 Multislip request Requests a slip or multislip event from all divider channels that are
sensitive to slip or multislip commands. The dividers are rising edge
sensitive and take some time to process the request, after which the
phase synchronization alarm is asserted.
0 Reserved Reserved.

Table 23. Global Enable Control

Address Bits Bit Name Settings Description Access
0x0003 [7:6] Reserved Reserved RW
5 RF reseeder enable Enable RF reseed for SYSREF
[4:3] Reserved Reserved
2 SYSREF timer enable Enable internal SYSREF time reference
1 Reserved Reserved
0 Reserved Reserved
0x0004 7 Reserved Reserved RW
[6:0] Seven Pairs of 14-Channel Outputs Enable[6:0] [0] Enable Channel 0 and 1
[1] Enable Channel 2 and 3
[2] Enable Channel 4 and 5
[3] Enable Channel 6 and 7
[4] Enable Channel 8 and 9
[5] Enable Channel 10 and 11
[6] Enable Channel 12 and 13

Table 24. Global Mode and Enable Control

Address Bits Bit Name Settings Description Access
0x0005 [7:0] Reserved Reserved RW

Rev. B | Page 33 of 43
HMC7043 Data Sheet
Table 25. Global Clear Alarms
Address Bits Bit Name Settings Description Access
0x0006 [7:1] Reserved Reserved RW
0 Clear alarms Clear latched alarms

Table 26. Global Miscellaneous Control

Address Bits Bit Name Settings Description Access
0x0007 [7:0] Reserved Reserved. RW
0x0008 [7:0] Reserved (scratchpad) Reserved. The user can write/read to this register to confirm input/outputs RW
to the HMC7043. This register does not affect device operation.
0x0009 [7:0] Reserved Reserved. RW

Input Buffer (Register 0x000A to Register 0x000B)

Table 27. CLKIN/CLKIN and RFSYNCIN/RFSYNCIN Input Buffer Control

Address Bits Bit Name Settings Description Access
0x000A, 0x000B [7:5] Reserved Reserved RW
[4:1] Input Buffer Mode[3:0] Input buffer control
[0] Enable internal 100 Ω termination
[1] Enable ac coupling input mode
[2] Enable LVPECL input mode
[3] High-Z input enable
0 Buffer enable Enable input buffer

GPIO/SDATA Control (Register 0x0046 to Register 0x0054)

Table 28. GPI Control
Address Bits Bit Name Settings Description Access
0x0046 [7:4] Reserved Reserved RW
[3:1] GPI Selection[2:0] Select the GPI functionality, Bits[2:0]
0000 Select the GPI functionality, Bits[2:0]
0001 Reserved
0010 Put the chip into sleep mode
0011 Issue a mute
0100 Issue a pulse generator request
0101 Issue a reseed request
0110 Issue a restart request
0111 Reserved
1000 Issue a slip request
1001 Reserved
1010 Reserved
1011 Reserved
1100 Reserved
1101 Reserved.
1110 Reserved
1111 Reserved.
0 GPI enable GPI function enable. Before changing the function of the pin, disable it first,
and then reenable it after the function change. 1
1
Note that it is possible to have a GPIO delete pin configured as both an output and an input.

Rev. B | Page 34 of 43
Data Sheet HMC7043
Table 29. GPO Control
Address Bits Bit Name Settings Description Access
0x0050 7 Reserved Reserved RW
[6:2] GPO Selection[4:0] Select the GPO functionality, Bits[4:0]
00000 Alarm signal
00001 SDATA from SPI communication
00010 SYSREF sync status has not synchronized since reset
00011 Clock outputs phase status
00100 Sync request status signal
00101 Channel outputs FSM busy
00110 SYSREF FSM State 0
00111 SYSREF FSM State 1
01000 SYSREF FSM State 2
01001 SYSREF FSM State 3
01010 Force Logic 1 to GPO
01011 Force Logic 0 to GPO
01100 Reserved
01101 Reserved
01110 Reserved
01111 Reserved
10000 Reserved
10001 Reserved
10010 Reserved
10011 Reserved
10100 Reserved
10101 Reserved
10110 Reserved
10111 Reserved
11000 Reserved
11001 Pulse generator request status signal
11010 Reserved
11011 Reserved
11100 Reserved
11101 Reserved
11110 Reserved
11111 Reserved
1 GPO mode Selects the mode of GPO driver
0 Open-drain mode
1 CMOS mode
0 GPO enable GPO driver enable

Table 30. SDATA Control

Address Bits Bit Name Settings Description Access
0x0054 [7:2] Reserved Reserved RW
1 SDATA mode Selects the mode of SDATA driver
0 Open-drain mode
1 CMOS mode
0 SDATA enable SDATA driver enable

Rev. B | Page 35 of 43
HMC7043 Data Sheet
SYSREF/SYNC (Register 0x005A to Register 0x005D)
Table 31. Pulse Generator Control
Address Bits Bit Name Settings Description Access
0x005A [7:3] Reserved Reserved. RW
[2:0] Pulse Generator SYSREF output enable with pulse generator.
Mode 000 Level sensitive. When the GPI is configured to issue a pulse generator
Selection[2:0] request (GPI Selection[2:0] = 100), or a pulse generator request is issued
through the SPI or as a SYNC pin-based pulse generator, run the pulse
generator. Otherwise, stop the pulse generator.
001 1 pulse.
010 2 pulses.
011 4 pulses.
100 8 pulses.
101 16 pulses.
110 16 pulses.
111 Continuous mode (50% duty cycle).

Table 32. SYNC Control

Address Bits Bit Name Settings Description Access
0x005B [7:3] Reserved Reserved RW
2 SYNC retime
0 Bypass the retime (non-deterministic SYNC event condition)
1 Retime the external SYNC (deterministic SYNC event condition)
1 Reserved Reserved
0 SYNC polarity SYNC polarity (must be 0 if not using CLKIN/CLKIN as the input)
0 Positive
1 Negative

Table 33. SYSREF Timer Control

Address Bits Bit Name Settings Description Access
0x005C [7:0] SYSREF Timer[7:0] 12-bit SYSREF timer setpoint LSB. This sets the internal beat frequency of RW
(LSB) the master timer, which controls synchronization and pulse generator
events. Set the 12-bit timer to a submultiple of the lowest output SYSREF
frequency, and program it to be no faster than 4 MHz.
0x005D [7:4] Reserved Reserved. RW
[3:0] SYSREF Timer[11:8] 12-bit SYSREF timer setpoint MSB.
(MSB)

Clock Distribution Network (Register 0x0064 to Register 0x0065)

Table 34. Clock Input Control
Address Bits Bit Name Settings Description Access
0x0064 [7:2] Reserved Reserved RW
1 Divide by 2 on clock input Use divide by 2 on clock input path
0 Low frequency clock input Changes bias to Class A for low frequency clock input

Table 35. Analog Delay Common Control

Address Bits Bit Name Settings Description Access
0x0065 [7:1] Reserved Reserved. RW
0 Analog delay low Analog delay is low power mode. Can save power for low settings of analog
power mode delay, but is not glitchless between setpoints.

Rev. B | Page 36 of 43
Data Sheet HMC7043
Alarm Masks Register (Register 0x0071)
Table 36. Alarm Mask Control Register
Address Bits Bit Name Settings Description Access
0x0071 [7:5] Reserved Reserved RW
4 Sync request mask If set, allow sync request signals to generate an alarm signal
3 Reserved Reserved
2 Clock outputs phase status If set, allow clock output phases status signal to generate an alarm
mask signal
1 SYSREF sync status mask If set, allow SYSREF sync status signal to generate an alarm signal
0 Reserved Reserved

Product ID Registers (Register 0x0078 to 0x007A)

Table 37. Product ID Registers
Address Bits Bit Name Settings Description Access
0x0078 [7:0] Product ID Value[7:0] (LSB) 24-bit product ID value low R
0x0079 [7:0] Product ID Value[15:8] (Mid) 24-bit product ID value mid R
0x007A [7:0] Product ID Value[23:16] (MSB) 24-bit product ID value high R

Alarm Readback Status Registers (Register 0x007B to 0x007F)

Table 38. Alarm Readback Status Registers
Address Bits Bit Name Settings Description Access
0x007B [7:1] Reserved Reserved. R
0 Alarm signal Readback alarm status from SPI.
0x007D [7:5] Reserved Reserved. R
4 Sync request status Unsynchronized.
3 Reserved Reserved.
2 Clock outputs phases SYSREF alarm.
status 0 SYSREF of the HMC7043 is not valid; that is, the phase output is not stable.
1 SYSREF of the HMC7043 is valid; that is, the phase output is stable.
1 SYSREF sync status SYSREF SYNC status alarm.
0 The HMC7043 has been synchronized with an external sync pulse or a
sync request from the SPI.
1 The HMC7043 never synchronized with an external sync pulse or a sync
request from the SPI.
0 Reserved 1 Reserved.
0x007F [7:0] Reserved Reserved. R

Rev. B | Page 37 of 43
HMC7043 Data Sheet
SYSREF Status Register (Register 0x0091)
Table 39. SYSREF Status
Address Bits Bit Name Settings Description Access
0x0091 [7:5] Reserved Reserved. R
4 Channel outputs One of clock outputs FSM requested clock, and it is running.
FSM busy
[3:0] SYSREF FSM Indicates the current step of the SYSREF reseed process. Note that the three
State[3:0] different progressions are caused by different trigger events (reseed, pulse
generator, reserved).
0000 Reset.
0010 Done.
0100 Get ready.
0101 Get ready.
0110 Get ready.
1010 Running (pulse generator).
1011 Start.
1100 Power up.
1101 Power up.
1110 Power up.
1111 Clear reset.

Bias Settings (Register 0x0096 to Register 0x00B8)

For optimum performance of the chip, Register 0x0098 to Register 0x00B8 must be programmed to a different value than their default value.

Table 40. Reserved Registers

Address Bits Bit Name Settings Description Access
0x0098 [7:0] Reserved Reserved RW
0x0099 [7:0] Reserved Reserved RW
0x009D [7:0] Reserved Reserved RW
0x009E [7:0] Reserved Reserved RW
0x009F [7:0] Reserved Clock output driver low power setting (set to 0x4D instead of default value) RW
0x00A0 [7:0] Reserved Clock output driver high power setting (set to 0xDF instead of default value) RW
0x00A2 [7:0] Reserved Reserved RW
0x00A3 [7:0] Reserved Reserved RW
0x00A4 [7:0] Reserved Reserved RW
0x00AD [7:0] Reserved Reserved RW
0x00B5 [7:0] Reserved Reserved RW
0x00B6 [7:0] Reserved Reserved RW
0x00B7 [7:0] Reserved Reserved RW
0x00B8 [7:0] Reserved Reserved RW

Rev. B | Page 38 of 43
Data Sheet HMC7043
Clock Distribution (Register 0x00C8 to Register 0x0152)
The bit descriptions in Table 41 apply to all 14 channels.

Table 41. Channel 0 to Channel 13 Control

Address Bits Bit Name Settings 1 Description Access
0x00C8, 0x00D2, 0x00DC, 7 High performance High performance mode. Adjusts the divider and buffer RW
0x00E6, 0x00F0, 0x00FA, mode bias to improve swing/phase noise at the expense of
0x0104, 0x010E, 0x0118, power.
0x0122, 0x012C, 0x0136, 6 SYNC enable Susceptible to SYNC event. The channel can process a
0x0140, 0x014A SYNC event to reset the phase.
5 Slip enable Susceptible to slip event. The channel can process a slip
request from SPI or GPI. Note that if slip enable is true,
but multislip is off, a channel slips by 1 clock input cycle
on an explicit slip request broadcast from the SPI/GPI.
4 Reserved Reserved.
[3:2] Start-Up Configures the channel to normal mode with
Mode[1:0] asynchronous startup, or to a pulse generator mode with
dynamic start-up. Note that this must be set to
asynchronous mode if the channel is unused.
00 Asynchronous.
01 Reserved.
10 Reserved.
11 Dynamic.
1 Multislip enable Allow multislip operation (default = 0 for SYSREF, 1 for
DCLK).
0 Do not engage automatic multislip on channel startup.
1 Multislip events after SYNC or pulse generator request, if
the slip enable bit = 1.
0 Channel enable Channel enable. If this bit is 0, channel is disabled.
0x00C9, 0x00D3, 0x00DD, [7:0] 12-Bit Channel 12-bit channel divider setpoint LSB. The divider supports RW
0x00E7, 0x00F1, 0x00FB, Divider[7:0] (LSB) even divide ratios from 2 to 4094. The supported odd
0x0105, 0x010F, 0x0119, divide ratios are 1, 3, and 5. All even and odd divide ratios
0x0123, 0x012D, 0x0137, have 50.0% duty cycle.
0x0141, 0x014B
0x00CA, 0x00D4, 0x00DE, [7:4] Reserved Reserved. RW
0x00E8, 0x00F2, 0x00FC, [3:0] 12-Bit Channel 12-bit channel divider setpoint MSB.
0x0106, 0x0110, 0x011A, Divider[11:8]
0x0124, 0x012E, 0x0138, (MSB)
0x0142, 0x014C
0x00CB, 0x00D5, 0x00DF, [7:5] Reserved Reserved. RW
0x00E9, 0x00F3, 0x00FD, [4:0] Fine Analog 24 fine delay steps. Step size = 25 ps. Values bigger than
0x0107, 0x0111, 0x011B, Delay[4:0] 23 has no effect on analog delay.
0x0125, 0x012F, 0x0139,
0x0143, 0x014D
0x00CC, 0x00D6, 0x00E0, [7:5] Reserved Reserved. RW
0x00EA, 0x00F4, 0x00FE, [4:0] Coarse Digital 17 coarse delay steps. Step size = ½ input clock cycle. This
0x0108, 0x0112, 0x011C, Delay[4:0] flip flop (FF)-based digital delay does not increase noise
0x0126, 0x0130, 0x013A, level at the expense of power. Values bigger than 17 have
0x0144, 0x014E no effect on coarse delay.
0x00CD, 0x00D7, 0x00E1, [7:0] 12-Bit Multislip 12-bit multislip digital delay amount LSB. Step size = RW
0x00EB, 0x00F5, 0x00FF, Digital Delay[7:0] (delay amount: MSB + LSB) × input clock cycles. If
0x0109, 0x0113, 0x011D, (LSB) multislip enable bit = 1, any slip events (caused by GPI,
0x0127, 0x0131, 0x013B, SPI, SYNC, or pulse generator events) repeat the number
0x0145, 0x014F of times set by 12-Bit Multislip Digital Delay[11:0] to
adjust the phase by step size.

Rev. B | Page 39 of 43
HMC7043 Data Sheet
Address Bits Bit Name Settings 1 Description Access
0x00CE, 0x00D8, 0x00E2, [7:4] Reserved Reserved. RW
0x00EC, 0x00F6, 0x0100, [3:0] 12-Bit Multislip 12-bit multislip digital delay amount MSB.
0x010A, 0x0114, 0x011E, Digital Delay[11:8]
0x0128, 0x0132, 0x013C, (MSB)
0x0146, 0x0150
0x00CF, 0x00D9, 0x00E3, [7:2] Reserved Reserved. RW
0x00ED, 0x00F7, 0x0101, [1:0] Output Mux Channel output mux selection.
0x010B, 0x0115, 0x011F, Selection[1:0] 00 Channel divider output.
0x0129, 0x0133, 0x013D,
0x0147, 0x0151 01 Analog delay output.
10 Other channel of the clock group pair.
11 Input clock (fundamental). Fundamental can also be
generated with 12-bit channel divider ratio = 1.
0x00D0, 0x00DA, 0x00E4, [7:6] Idle at Zero[1:0] Idle at Logic 0 selection (pulse generator mode only). RW
0x00EE, 0x00F8, 0x0102, Force to Logic 0 or VCM.
0x010C, 0x0116, 0x0120, 00 Normal mode (selection for DCLK).
0x012A, 0x0134, 0x013E,
01 Reserved.
0x0148, 0x0152
10 Force to Logic 0.
11 Force outputs to float, goes naturally to VCM.
5 Dynamic driver Dynamic driver enable (pulse generator mode only).
enable 0 Driver is enabled/disabled with channel enable bit.
1 Driver is dynamically disabled with pulse generator events.
[4:3] Driver Mode[1:0] Output driver mode selection.
00 CML mode.
01 LVPECL mode.
10 LVDS mode.
11 CMOS mode.
2 Reserved Reserved.
[1:0] Driver Output driver impedance selection for CML mode.
Impedance[1:0] 00 Internal resistor disable.
01 Internal 100 Ω resistor enable per output pin.
10 Reserved.
11 Internal 50 Ω resistor enable per output pin.
1
X means don’t care.

Rev. B | Page 40 of 43
Data Sheet HMC7043

APPLICATIONS INFORMATION
EVALUATION PCB AND SCHEMATIC RAMP UP
3°C/SECOND MAX
60 TO 150
SECONDS

For the circuit board in this application, use RF circuit design 260 – 5/0°C

TEMPERATURE (°C)
techniques. Ensure that signal lines have 50 Ω impedance. 217°C

Connect the package ground leads and exposed paddle directly 150°C TO 200°C
RAMP DOWN
to the ground plane similar to that shown in Figure 32 and 6°C/SECOND MAX
Figure 33. Use a sufficient number of via holes to connect the
top and bottom ground planes. The evaluation circuit board is
60 TO 180 TIME (Second)
available from Analog Devices, Inc., upon request. SECONDS

13114-031
20 TO 40
The typical Pb-free reflow solder profile shown in Figure 31 is 480 SECONDS MAX SECONDS

based on JEDEC J-STD-20C. Figure 31. Pb-Free Reflow Solder Profile

13114-029

Figure 32. Evaluation PCB Layout, Top Side

Rev. B | Page 41 of 43
HMC7043 Data Sheet

13114-030
Figure 33. Evaluation PCB Layout, Bottom Side

Rev. B | Page 42 of 43
Data Sheet HMC7043

OUTLINE DIMENSIONS
7.10 0.31
7.00 SQ 0.25
PIN 1 6.90 0.19 PIN 1
INDICATOR INDICATOR
37 48
36 1

0.50
BSC 5.66
EXPOSED
PAD 5.60 SQ
5.54

25
12
13
0.45 24
0.20 MIN
TOP VIEW 0.40 BOTTOM VIEW
0.35 5.50 REF
0.90
0.85 FOR PROPER CONNECTION OF
0.05 MAX THE EXPOSED PAD, REFER TO
0.80
0.02 NOM THE PIN CONFIGURATION AND
COPLANARITY FUNCTION DESCRIPTIONS
0.08 SECTION OF THIS DATA SHEET.
SEATING 0.20 REF
PLANE

11-20-2015-B
PKG-000000

Figure 34. 48-Lead Lead Frame Chip Scale Package [LFCSP]

7 mm × 7 mm Body and 0.85 mm Package Height
(HCP-48-1)
Dimensions shown in millimeters
NOTE 1
NOTE 6 4.10
2.10 4.00 12.10
1.85 2.00 3.90 12.00
1.75 1.90 11.90 0.35
A Ø 1.5 ~ 1.6 0.30
1.65
0.25
16.30 7.60
16.00 7.50
7.35 7.40
15.70 7.25 NOTE 6
7.15
NOTE 4

TOP VIEW Ø 1.5 MIN 1.20

7.35 A DETAIL A
1.10
7.25
1.00 NOTE 5
7.15 DIRECTION OF FEED
NOTE 4 SECTION A-A

0.25
NOTES:
1. 10 SPROCKET HOLE PITCH CUMUL ATIVE TOLERANCE ± 0.20
2. CAMBER IN COMPLIANCE WITH EIA 481
3. MATERIAL: CONDUCTIVE BLACK PO LYSTYRENE DETAIL A R 0.25
4. MEASURED ON A PLANE 0.30 mm ABOVE THE BOTTOM OF
THE POCKET
12-10-2015-A

5. MEASURED FROM A PLANE ON THE INSIDE BOTTOM OF

THE POCKET TO THE TOP SURFACE OF THE CARRIER
6. POCKET POSITION RELATIVE TO SPROCKET HOLE MEASURED
AS TRUE POSITION OF POCKET, NOT POCKET HOLE

Figure 35. LFCSP Tape and Reel Outline Dimensions

Dimensions shown in millimeters

ORDERING GUIDE
Model 1 Temperature Range Lead Finish MSL Rating 2 Package Description Package Option Branding 3
HMC7043LP7FE −40oC to +85°C NiPdAu MSL-3 48-Lead Lead Frame Chip HCP-48-1 7043
Scale Package [LFCSP] XXXX
HMC7043LP7FETR −40oC to +85°C NiPdAu MSL-3 48-Lead Lead Frame Chip HCP-48-1 7043
Scale Package [LFCSP] XXXX
EK1HMC7043LP7F −40°C to +85°C Evaluation Kit
1
E = RoHS Compliant Part.
2
The maximum peak reflow temperature is 260°C for the HMC7043LP7FE.
3
Four-digit lot number represented by XXXX.

©2015–2016 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D13114-0-7/16(B)

Rev. B | Page 43 of 43