Program : B.

Tech
Subject Name: CMOS Design
Subject Code: EC-603
Semester: 6th
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Unit- II : Specification of sequential systems: Characterizing equation & definition of synchronous sequential
machines. Realization of state diagram and state table from verbal description, Mealy and Moore model
machines state table and transition diagram. Minimization of the state table of completely and incompletely
specified sequential machines

Sequential Systems:
A sequential system consists of a combinational circuit with the feedback circuit. The general block diagram of
the sequential system is as shown in Fig.2.1. The feedback circuit consists of memory elements which are
capable of storing binary information. The output of the combinational circuit ‘Y’ is called as next state and the
output of the feedback circuit ‘y’ is called as present state. Thus a sequential circuit is specified by a present
state, input information and the output information.

Input Combinational Output

Circuit
Y Feedback Circuit

Fig. 2.1: Block Diagram of a Sequential Circuit

Sequential circuits are classified as Asynchronous sequential circuit and Synchronous sequential circuits.

Basic Definitions of Sequential Machine Design:

(i) State : The binary output information of the memory component is defined as state of the sequential
circuit.
(ii) Present State: It is the state of sequential circuit at time ‘t’, which is before the occurrence of next clock
pulse.
(iii) Next State: It is the state of sequential circuit at time ‘t+1’, which is after the occurrence of next clock
pulse.
(iv) State Equations: It is the characteristic equation of the sequential machine also called as next state
equation.
(v) State Table: The state table provides in the information regarding the possible next state and output based
on the behavior of the system for present state and input. It consists of three sections namely, present
state, next state and output.
(vi) State Assignment: The state variables are assigned with binary coded values. The unused states are treated
as don’t care condition during the design.
(vii) Transition Table: In the transition table the state variable value is assigned. If the state variables in the
state table are assigned with binary coded value then the table is called as transition table.
(viii) State Diagram: The state diagram represent the flow of operation of sequential machine for the applied
input values. It is the graphical representation of the behavior of the sequential machine. In this diagram
the circle represents the state, and the transition between the state is represented by directed line. The
line is labeled with two binary information input / output information.

Realization Of State Diagram And State Table From Verbal Description:

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The design of sequential circuit is referred as synthesis of sequential circuit. Following are the design steps
involved in the verbal description.
(i) Construct a state graph with the help of specifications for the sequential circuit to be designed.
(ii) Translate the state graph into state table
(iii) Number of redundant states may be reduced.
(iv) Each of the state is assigned with the binary code using state assignment procedure.
(v) Construct the translation table and output table.
(vi) Derive an excitation table for the selected flip flop.
(vii) Find flip flop input and output equation
(viii) Draw the logic diagram using the logic equations obtained.

Mealy Model Machines: The Mealy machine output depends on both the present state and the input value.
The block diagram of the Mealy machine is as shown in the Fig. 2.2.

Next State Memory Output Logic

Input Output
Logic Element

Fig. 2.2: Mealy Machine

Moore Model Machines: The Moore machine output is dependent only on the present state. The block
diagram of Moore machine is as shown in the Fig. 2.3.

Next State Memory Output Logic

Input Output
Logic Element

Fig. 2.3: Moore Machine

Sl. No. Mealy Machine Moore Machine

1 The output is a function of both the present The output is a function of the present state only
state and input
2 One state may have more than one output One state is associated with only one output
3 Designer has more flexibility in designing Designer has less flexibility in designing these
these machines machines

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4 Output may change either when input The output will only change when the state change.
changes or when the flip flop change state
5 Output is observed after each input appear Output is observed after the entire input sequence
appear
6 The output may have momentary false No false output appear as the output is not a function
values. of input, it is only the function of state.

Example: Construct a mealy state diagram that will detect sequence of 10110 from the stream of data.

0/1
S0 1/0

1/0
S4 S1
1/0
0/0
0/0
1/0 0/0
S3
S2

1/0
Fig. 2.4 : State Diagram

Example : Design a sequence detector which detects a sequence of “1010” in a stream of data.

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0/0 0/0

S0 S0
0/1 1/0 1/0

S3 1/0 S3 1/0
S1 1/0 S1 1/0
0/0 0/0
0/1

1/0 S2 0/0 1/0 S2 0/0

Fig.2.5 : State Diagram to detect sequence Fig.2.6 : State Diagram to detect sequence
“1010” (Non- Overlapping Sequence) “1010” (Overlapping Sequence)

State Table : State Table :

Present Next State, Output Present Next State, Output
State X=0 X=1 State X=0 X=1
S0 S0,0 S1,0 S0 S0,0 S1,0
S1 S2,0 S1,0 S1 S2,0 S1,0
S2 S0,0 S3,0 S2 S0,0 S3,0
S3 S0,1 S1,0 S3 S2,1 S1,0

Example : Design a sequence detector which detects a sequence of “0101” in a stream of data.

1/0 1/0

S0 S0
1/1 0/0 0/0

S3 0/0 S3 0/0
S1 0/0 S1 0/0
1/0 1/0
1/1

0/0 S2 1/0 0/0 S2 1/0

Fig. 2.7: State Diagram to detect sequence Fig.2.8: State Diagram to detect sequence
“0101” (Non- Overlapping Sequence) “0101” (Overlapping Sequence)

State Table :

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Present Next State, Output State Table :

State X=0 X=1
Present Next State, Output
S0 S1,0 S0,0
State X=0 X=1
S1 S1,0 S2,0
S0 S1,0 S0,0
S2 S3,0 S0,0
S1 S1,0 S2,0
S3 S1,0 S0,1
S2 S3,0 S0,0
S3 S1,0 S2,1

Example : Design a sequence detector which detects a sequence of “1001” in a stream of data.

0/0 0/0

S0 0/0 S0
1/1 1/0 1/0
0/0

S3 S3 1/1
S1 1/0 S1 1/0
1/0 1/0

0/0 S2 0/0 0/0 S2 0/0

Fig.2.9: State Diagram to detect sequence Fig.2.10: State Diagram to detect sequence
“1001” (Non- Overlapping Sequence) “1001” (Overlapping Sequence)

State Table : State Table :

Present Next State, Output Present Next State, Output
State X=0 X=1 State X=0 X=1
S0 S1,0 S0,0 S0 S1,0 S0,0
S1 S1,0 S2,0 S1 S1,0 S2,0
S2 S3,0 S0,0 S2 S3,0 S0,0
S3 S1,0 S0,1 S3 S1,0 S2,1

Example : A sequential circuit has two JK flip flops A and B, two input x and y, and one output z. The flip flop
input equations and circuit output equation are:
JA = Bx + B’y’ KA = B’xy’
JB = A’x KB = A + xy’
Z = Ax’y’ + Bx’y’
(i) Draw the logic diagram of the circuit (ii) Derive the state equations A(t+1) and B(t+1).
(iii) List the state table for the sequential circuit. (iv) Draw the corresponding state diagram

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x
JA A
y

KA A’

JB B x' Z=(A+B)x’y’
y' Z=Ax’y’+Bx’y’

KB B’

Fig.2.11: Logic Diagram

A(t+1) = JA A’ + KA’ A = (Bx + B’y’) A’ + (B’xy’)’ A B(t+1) = JB B’ + KB’ B = (A’x) B’ + (A + xy’)’ B

= A’Bx + A’B’y’ + (B + x’ + y)A = A’B’x + (A’(x’+y))B
= A’Bx + A’B’y’ + AB + Ax’ + Ay = A’B’x + A’Bx’ + A’By
xy xy 00 xy 00
00 01 11 10 01 11 10 01 11 10
AB AB AB
00 1 0 0 1 00 0 0 1 1 00 0 0 0 0

01 0 0 1 1 01 1 1 1 0 01 1 0 0 0

11 1 1 1 1 11 0 0 0 0 11 1 0 0 0

10 1 1 1 0 10 0 0 0 0 10 1 0 0 0
K-Map for A(t+1) K-Map for B(t+1) K-Map for Z

Present State Next State, Output

AB A(t+1) B(t+1) , Z
xy = 00 xy=01 xy=11 xy=10

00 10,0 00,0 01,0 11,0

01 01,1 01,0 11,0 10,0
11 10,1 10,0 10,0 10,0
10 10,1 10,0 10,0 00,0

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01/0
Present State Next State, Output
00/0 S0
xy = 00 xy=01 xy=11 xy=10 11/0

S0 S3,0 S0,0 S1,0 S2,0 00/1 10/0 00/1

S1 S1,1 S1,0 S2,0 S3,0 01/0 01/0
S3 10/0
S2 S3,1 S3,0 S3,0 S3,0 11/0 S1
S3 S3,1 S3,0 S3,0 S0,0 00/1
01/0 11/0
11/0 S2
10/0
10/0

State Diagram

Minimisation of the State table of completely specified machine

Rules for state minimization – Partition Method:
(i) The first partition P0 corresponding to 0-distinguishability, and it defines our initial “ignorance” regarding
the response of the various states, prior to the application of any input.
(ii) Obtain P1: The classes of 1-equivalent states are obtained directly from the state table by placing those
state having the same outputs, under all inputs, in the same block.
(iii) Obtain Pi+1 : The next step is to obtain the Pi+1 partition from Pi partition. To obtain Pi+1 it is only possible to
break down classes from Pi but not to recombine states that are in different classes of Pi. In general, the
Pi+1 partition is obtained from Pi by placing in the same block of Pi+1 those state which are in the same
block of Pi and whose Xi – successors for every possible Xi are also in a common block of Pi.
(iv) The procedure stops when partition Pi+1 is the same as partition Pi.
(v) Write the reduced table.

Example (i) Determine the minimal state table equivalent to the following

Present Next State, Output

State X=0 X=1
A F,0 C,0
B H,1 A,1

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C H,0 D,1
D B,0 H,0
E G,0 C,0
F C,1 E,1
G H,1 E,1
H C,0 A,1

Solution :
 The first partition P0 corresponds to 0-distinguishability,
∴ P0 = (ABCDEFGH)

 The second step is to obtain the partition P1, from the output values.

Present Output
State X=0 X=1
A 0 0
B 1 1 The states are 1-equivalent if they have the same row
C 0 1 pattern.
D 0 0 ∴ P1 = (ADE)(BFG)(CH)
E 0 0
F 1 1
G 1 1
H 0 1

 P2 is obtained by inspecting the next states of (ADE), (BFG), and (CH). The states are placed in the same block of
P2 if and only if they are in the same block of P1.

Present Next State Present Next State Present Next State

State X=0 X=1 State X=0 X=1 State X=0 X=1
A F C B H A C H D
D B H F C E H C A
E G C G H E

 For the block (ADE), the next states (FBG) and (CHC) are in the same block of P 1 . Therefore (ADE) are
2-equivalent. Similarly block (BFG) and (CH) are also have next states in the same block of P 1 and they are
2-equivalent .
∴ P2 = (ADE)(BFG)(CH)
Since P1 = P2 , stop the partition process.
The blocks of the equivalent partition P2 are denoted as (ADE)--- A, (BFG)---B and (CH) --- C respectively.
Therefore the minimal table is given as

Present Next State, Output

State X=0 X=1
A B,0 C,0
B C,1 A,1
C C,0 A,1

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Rules for state minimization – Merger Table (Implication Table):

(i) Construct a chart which contains a square for each pair of states.
(ii) Place ‘X’ in the square where the outputs are different. These state are not equivalent.
(iii) Place ‘√’(check) in the square where the outputs and next states are same, indicates that S i ≡ Sj
(iv) If the next state Si and Sj are Sm and Sn respectively for some input x, then Si ≡ Sj if and only if Sm ≡ Sn
(v) If square i-j contains the implied pari Sm and Sn and square m-n contains ‘X’ , then Si ≠ Sj and a ‘X’ should be
placed in square i-j.
(vi) For each square i-j which does not contain an ‘X’ S i ≡ Sj
(vii) Construct the reduced state table based on the state equivalence obtained.

Example (ii) Draw the state diagram for reduced state table for the given state table using merger table

Present Next State, Output

State X=0 X=1
A F,0 B,0
B D,0 C,0
C F,0 F,0
D G,1 A,0
E D,0 C,0
F F,1 B,1
G G,0 H,1
H G,1 A,0

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The squares are evaluated that contain implied state

D-F equivalencies gives the following condition.
B
D-F  A ≠ B, because D ≠ F
C B-F
 A ≠ C, because B ≠ F
 A ≠ E, because D ≠ F
D
 B ≠ C, because D ≠ F and C ≠ F
D-F D-F  B ≡ E, because the outputs & next states are same
E
 C ≠ E, because D ≠ F and C ≠ F
F  D ≡ H, because the outputs & next states are same

H Since square B-E and D-H does not contain an X, we

conclude that B ≡ E and D ≡ H. All other squares contain X,
A B C D E F G so there are no other equivalent state pairs. The reduced
state table is

Present Next State, Output

B State X=0 X=1
A F,0 B,0
C B D,0 C,0
C F,0 F,0
D
D G,1 A,0
E F F,1 B,1
G G,0 D,1
F

A B C D E F G

Example (iii) Draw the state diagram for reduced state table for the given state table using merger table

Present Next State

Output
State X=0 X=1
A D C 0
B F H 0
C E D 1
D A E 0
E C A 1
F F B 1
G B H 0
H C G 1

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The squares are evaluated that contain implied state

D-F equivalencies gives the following condition.
B
 A ≠ B, because D ≠ F
C
 B ≠ D, because A ≠ F
A-F  B ≠ G, because B ≠ F
D C-E
 C ≠ F, because B ≠ D
A-D  D ≠ G, because A ≠ B
E
 C ≠ H, because D ≠ G
F
E-F C-F  E ≠ F, because C ≠ F
 H ≠ F, because C ≠ F
B-D A-B A-B
G
B-D
B-F  A ≠ G, because B ≠ D
 E ≠ H, because A ≠ G
C-H C-E E-H C-F
H A-G
Since the square A-D contains the pair (C-E) and C-E
D-G B-G
A B C D E F G contains the pair (A-D), they are equivalent states.
Therefore A ≡ D and C ≡ E. The reduced state table is

Present Next State

B Output
State X=0 X=1
C A A C 0
B F H 0
D C-E C C A 1
F F B 1
E A-D G B H 0
H C G 1
F

A B C D E F G

Example (iv) Determine the minimal state equivalent of the following state table using merger table.

Present Next State , Output

State X=0 X=1
A F,0 C,0
B H,1 A,1
C H,0 D,1
D B,0 H,0
E G,0 C,0
F C,1 E,1
G H,1 E,1
H C,0 A,1

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The squares are evaluated that contain implied state

equivalencies gives the following condition.
B
 A ≡ D, because B ≡ F & C ≡ H
C
 A ≡ E, because F ≡ G
B-F  B ≡ F, because C ≡ H & A ≡ E
D
 B ≡ G, because A ≡ E
C-H
F-G
B-G  C ≡ H, because A ≡ D
E
 D ≡ E, because B ≡ G & C ≡ H
F
C-H  F ≡ G, because C ≡ H

C-H All the cells with (x) are not equivalent to each other.
G A-E
The reduced state table is
H A-D
Present Next State
A B C D E F G Output
State X=0 X=1
A A C 0
B F H 0
B C C A 1
F F B 1
C G B H 0
H C G 1
D C-E

E A-D

A B C D E F G

Minimization of Incompletely Specified Machines:

Example (v) Find a minimum state table of the given machine state table using merger graph.

Present Next State, Z

State I1 I2 I3
A C,0 E,1 -,-
B C,0 E,- -,-
C B,- C,0 A,-
D B,0 C,- E,-
E -,- E,0 A,-

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A The merger graph indicates the compatible and implied

B compatible pairs as shown in Fig. Each of the incompatible
(BC)
state pairs is crossed off, leaving only those that are
(CE) compatible.
(BC) Compatible pairs are (AB) , (AD), (BC), (BD), (BE), and (CE)
(EC) Maximum Compatible pairs are (ABD) and (BCE)
(CE)
E C Assign new state variables for the closed set of maximum
(CE) (AE) compatible pairs as

(AE) D ABD = α
BCE = β
A
B The Simplified state table is given as
Present Next State, Z
State I1 I2 I3
α β,0 β,1 β,-
β β,0 β,0 α,-

E C

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