THE 8085
MICROPROCESSOR
INSTRUCTION SET
1
Salient features of 8085 microprocessor
▪ 8 bit microprocessor introduced in 1977
▪ Von Neumann architecture
▪ 16 bit address bus and hence can
address up to 216 = 65536 bytes (64KB)
memory locations through A0-A15.
▪ First 8 lines of address bus and 8 lines
of data bus are multiplexed AD0 – AD7.
▪ Data bus is a group of 8 lines D0 – D7.
▪ It supports 5 hardware interrupts and 8
software interrupts.
2
Salient features of 8085 microprocessor
▪ 16 bit program counter (PC)
▪ 16 bit stack pointer (SP)
▪ Accumulator (A)
▪ 8-bit Flag Register (F)
▪ Six 8-bit general purpose registers
arranged in pairs: B-C, D-E, H-L.
▪ Requires a single +5V power supply
▪ Maximum Clock Frequency is 3 MHz
and Minimum Clock Frequency is
500 kHz
3
Flag Register
The following status flags have been provided in Intel 8085:
1. CARRY (CY)
2. ZERO (Z)
3. SIGN (S) a 16-bit register
4. PARITY (P)
5. AUXILIARY CARRY (AC)
Accumulator and Flag Register together (A-F) is considered as a 16-bit register
PSW (Program Status Word) as the result or status of all arithmetic/logical
operations can be found in it.
4
Von Neumann and Harvard Architecture
5
Block Diagram
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8085 INSTRUCTION SET
❖An ‘instruction’ is a specific 8-bit pattern carrying a pre-
defined meaning and is designed to make electronic
logic circuits behave in a specific manner.
❖Instructions may be 1/2/3 bytes long
❖8085 has 246 instructions
❖Each instruction has two parts – Op code and Operand
(some instructions may not have operand, though)
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ADDRESSING MODES
Addressing modes are the ways in which data used in the
instructions are procured.
➢ Immediate Addressing: Raw data appears in the
instruction itself – MVI A, 05H
➢ Register Addressing: Data handled are in registers –
MOV B, A
➢ Direct Addressing: Data used in the instruction is in
specified memory location/s – LDA 2000H
➢ (Register) Indirect Addressing: Data handled are in
memory locations which are indirectly pointed at by
registers – LDAX B
➢ Implied/Implicit/Inherent: The source of data is implicitly
mentioned in the instruction - CMA
8
Classification of Instructions
▪ Data Transfer Instructions: Copying data from register to
register / register to memory location or the reverse
▪ Arithmetic Instructions: Addition / subtraction of two
quantities which may be contents of registers or
immediate data.
▪ Logical Instructions: Logic operations on two quantities
which may be contents of registers, immediate data or
status flags.
▪ Branching Instructions: Altering the normal sequential
flow of the program, conditionally or unconditionally.
▪ Machine Control Instructions: Control of CPU functions –
no data movement or memory access.
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Data Transfer Instructions
Opcode Operand Function
MOV Rd, Rs / M, Rs / Rd, M Copy from source to destination
MVI Rd, Data / M, Data Move immediate 8-bit data
LDA 16 bit address Load data from memory into A
STA 16 bit address Load data from A into memory
LXI Reg. pair, 16 bit address Load Reg. pair with immediate data
LDAX Reg. pair Load A indirectly from memory location
STAX Reg. pair Load memory location indirectly from A
LHLD 16 bit address Load HL register direct from two
consecutive memory locations
SHLD 16 bit address Store HL register direct into two
consecutive memory locations
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Data Transfer Instructions (continued)
Opcode Operand Function
XCHG None Exchange D-E with H-L
SPHL None Copy H-L to Stack Pointer (SP)
PCHL None Copy H-L to Program Counter (PC)
XTHL None Exchange H-L with top of Stack
PUSH Register pair Copy register pair to two top stack positions
POP Register pair Copy two top stack positions to register pair
IN 8 bit port Copy data from input port to A
address
OUT 8 bit port Copy data from A to output port
address
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Data Transfer Instructions (continued)
NO DATA TRANSFER
INSTRUCTION AFFECTS THE
STATUS FLAGS
12
Arithmetic Instructions
Opcode Operand Function Flags affected
ADD R/M Adds the content of a register or All
a memory location (specified by
H-L) with A. Result in A.
SUB R/M Subtracts the content of a All
register or a memory location
(specified by H-L) from A. Result
in A.
ADC R/M Adds the content of a register or All
a memory location and the CY
flag (specified by H-L) with A.
Result in A.
SBB R/M Subtracts the content of a All
register or a memory location
and the CY flag (specified by H-L)
from A. Result in A.
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Arithmetic Instructions (continued)
Opcode Operand Function Flags affected
ADI 8-bit data Adds an immediate data to A. All
Result in A.
ACI 8-bit data Adds an immediate data and All
the CY flag to A. Result in A.
SUI 8-bit data Subtracts an immediate data All
from A. Result in A.
SBI 8-bit data Subtracts an immediate data All
and the CY flag from A. Result in
A.
INR A/R/M Increment register or memory All except CY
content by 1
DCR A/R/M Decrement register or memory All except CY
content by 1
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Arithmetic Instructions (continued)
Opcode Operand Function Flags affected
DAD Register pair Add the content of a register pair CY
with content of H-L. Result in H-L.
INX Register pair Increments content of register None
pair by 1
DCX Register pair Decrements content of register None
pair by 1
DAA None Decimal Adjust Accumulator All
(If any digit in A is more than 09,
adds 06 to it).
15
Logical Instructions
Opcode Operand Function Flags affected
CMP R/M Compare content of register or CY set (if A is less)
memory with that of A. Result is Z set (if A is equal)
not retained. CY and Z reset (if
A is more)
CPI 8-bit data Compare immediate data with Same as above
A. Result is not retained.
ANA R/M Logical ANDing of the content S, Z, P
of register or memory with A CY reset, AC set
ANI 8-bit data Logical ANDing of immediate S, Z, P
data with A CY reset, AC set
ORA R/M Logical ORing of the content of S, Z, P
register or memory with A CY and AC reset
ORI 8-bit data Logical ORing of immediate data S, Z, P
with A CY and AC reset
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Logical Instructions (continued)
Opcode Operand Function Flags affected
XRA R/M Logical XORing of the content of S, Z, P
register or memory with A CY and AC reset
XRI 8-bit data Logical XORing of immediate S, Z, P
data with A CY and AC reset
RAL None Rotate A left through CY flag Only CY
RLC None Rotate A left Only CY
RAR None Rotate A right through CY flag Only CY
RRC None Rotate A right Only CY
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Logical Instructions (continued)
RAL RLC
RRC
RAR
18
Logical Instructions (continued)
Opcode Operand Function Flags affected
CMA None Complement A None
CMC None Complement CY flag None
STC None Set CY flag None
19
Branching Instructions
Opcode Operand Function Flags affected
JMP 16 bit address Unconditional branching None
JC 16 bit address Jump if CY = 1 None
JNC 16 bit address Jump if CY = 0 None
JZ 16 bit address Jump if Z = 1 None
JNZ 16 bit address Jump if Z = 0 None
JP 16 bit address Jump if S = 0 None
JM 16 bit address Jump if S = 1 None
JPE 16 bit address Jump if P = 1 None
JPO 16 bit address Jump if P = 0 None
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Branching Instructions (continued)
Opcode Operand Function Flags affected
CALL 16 bit address Call unconditionally None
CC 16 bit address Call if CY = 1 None
CNC 16 bit address Call if CY = 0 None
CZ 16 bit address Call if Z = 1 None
CNZ 16 bit address Call if Z = 0 None
CP 16 bit address Call if S = 0 None
CM 16 bit address Call if S = 1 None
CPE 16 bit address Call if P = 1 None
CPO 16 bit address Call if P = 0 None
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Branching Instructions (continued)
Opcode Operand Function Flags affected
RET 16 bit address Return (from subroutine) None
unconditionally
RC 16 bit address Return if CY = 1 None
RNC 16 bit address Return if CY = 0 None
RZ 16 bit address Return if Z = 1 None
RNZ 16 bit address Return if Z = 0 None
RP 16 bit address Return if S = 0 None
RM 16 bit address Return if S = 1 None
RPE 16 bit address Return if P = 1 None
RPO 16 bit address Return if P = 0 None
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Machine Control Instructions
Opcode Operand Function Flags affected
NOP None No Operation (used to introduce None
time delay)
HLT None Processor execution halted after None
executing current instruction
DI None Disable all interrupts (except TRAP) None
EI None Enable all interrupts None
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