SPECIFICATION

FOR
APPROVAL

( ) Preliminary Specification
( ) Final Specification

Title TFT-LCD Timing Controller

BUYER SUPPLIER LG.Philips LCD Co., Ltd.

MODEL BULL_REV(HS353149) *MODEL BULL_REV(HS353149)

LG Part Number 0IHYL-0045A

SIGNATURE DATE SIGNATURE DATE

S.H. Kang / G.Manager

/ C.H.Kyung / G.Manager
REVIEWED BY
J.S.Baek / Manager
/ J.D.Kim / Manager
PREPARED BY
Suny Kwon / Engineer
/ S.G.Kim / Engineer

Please return 1 copy for your confirmation with Products Engineering Dept.
your signature and comments. LG. Philips LCD Co., Ltd

Ver. 4.0 AUG. 11. 2003

 TFT-LCD Timing Controller
P/N : 0IHYL-0045A

Contents

No. ITEM Page

- COVER -

- Contents 1

- RECORD OF REVISIONS 2-1~2-2

1 General description 3

2 Function 3

3 Feature 4

4 Pin Diagram 4

5 Block Diagram 5

6 Main Function Description 6

7 Pin Configuration 7

8 Signal Description 8~10

9 Electrical Specification 11

10 Screen display Range 12

11 MODE Setting 13,14

12 DIV,HSY,HSYSC Generation 15

13 Horizontal Display Position 16

14 Vertical Display Method(NTSC) 17-1~17-3

15 Vertical Display Method(PAL) 18-1~18-3

16 Control Option 19

17 Package 20,21

18 Application Circuit , Notes & Component List 22~30

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RECORD OF REVISIONS 1/2

Revision No Revision Date Page Description

1.0 Apr. 21. 2003 - First Draft (Preliminary)

8 1. Option change : No signal Selection “H” Must be “L”

15 2. GOE Waveform Change
2.0 May. 20. 2003
19 3. Application Circuit Change : PLL Block Application
Analog Decoder IC parts delete

3 1. Function Change 2. 10
2. Output Pin Change : VSY NP_O (pin10)
4,7,8
3. Option Pin Change :
3.0 May. 20. 2003 8
- FSEL : Add to No Signal Black Function( pin21)
- ATMN : Add to NTSC/PAL Auto Detection Function (Pin39)
19 4. Application Circuit Change

16,19 1. TQFP 48pin Package Drawing Change

3.1 May. 28. 2003
18~20 2. Application Circuit Change

8,9 1. Signal description Change (Page 8 Page8,9)

3.2 June. 03. 2003
15,16 2. Add to Vertical Display Method (Page 15,16)

3.3 June. 09. 2003 10 Signal description Change : MP15 ( L H)

1 1. Contents item change

2. Application Circuit Change*1
22 - Add to SIGNAL IN/OUT BLOCK,
Add to –5V circuit in DC-DC CONVERTER BLOCK,
VCOM BLOCK change all,
Capacitance(C75, C80) & resistance(R127,R133) change in
VGL BLOCK.
23 - Add to VCO circuit & C90(100pF 150pF) change in PLL BLOCK,
3.4 July. 18. 2003 HPOSI circuit change in TIMING CONTROLLER BLOCK,
Resistance(R170, R173) change in VSM BLOCK.
24 - Reset resistance R177(68K 10K ) change, Some ports(NP,
MODE1, MODE2,MODE3) delete.
[*1] Reference number of resistance & capacitor base on Ver. 3.4
circuit diagrams. For more detail changed description,
please refer to the application notes and Ver.3.3 circuit diagrams.
25~28 3. Add to Application Circuit Notes
29~30 4. Add to Component List

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RECORD OF REVISIONS 2/2

Revision No Revision Date Page Description

- 1. TCON Model name & LG Part Number change .

- - Model name : BULL(HS353146) BULL_REV(HS353149)
- - Part number : 0IHYL-0041A 0IHYL-0045A
- 2. Input clock change. (20MHz 19.4MHz)
15 3. HSY width & HSYSC timing change.
16 4. Normal mode SSP position change.
19 5. SOE & internal signal GSS timing change.
23 6. “PLL block” circuit change(refer to [NOTE 4-3] in page 26,27 )
4.0 Aug. 11. 2003
- 1st proposal : C92 100pF 220pF
- 2nd proposal : L3 (3.9uH 4.7uH), R160 (open 0 ),
R163 (0 open).
24 7. “Timing controller setting block” setting change(refer to page 10,24).
- ATMN “Low” “High”
26~27 8. Add to application circuit [NOTE 4-3].
29~30 9. Component list change.
- Component list for circuit used 1st proposal of PLL block

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1. General description
BULL_REV IC, which is developed by LG.Philips LCD is timing controller for controlling 7” wide
TFT-LCD Module. It is improved LG first ASIC version BULL(0IHYL-0041A) of minor problem.

2. Function
It is using 19.4MHz input clock, and create the divide signal for comparing PLL phase.

(1) Outside of Controller IC, it is composed PLL circuit with additional VCO, LPF,
pulls the sync signal of PAL, NTSC into CSY pin and it is used for creating MCLK
by PDP signal with DIV signal which is created inside of IC.
(2) It creates signal for driving Source drive IC, Gate drive IC by using Horizontal Sync ‘HSY’,
Vertical Sync ‘VSY’, input signal.
1) The signal for Source Drive IC : SSPL, SSPR, LRO, SRESET, SOE, SSC, SSC1, SSC2
2) The signal for Gate Drive IC : UDO, GSP, GSC, GOE
3) The signal for driving VCOM : VCAC
4) The signal for controlling polarity change of display : FRP
(3) MODE1, MODE2, MODE3 is for selecting of display mode.
(4) It is for controlling the reverse of signal, left/right, up/down by using LRS, UDS.
(5) Synchronous, Successive Data Sampling is possible by controlling MP15.
(6) It is shown the start of Horizontal Line over ODD, EVEN input signal by STRN controlling.
(7) It can be changed a position of horizontal Start Pulse by SSP_S1, SSP_S2.
(8) It can be changed the vertical Start Pulse as 1H by GSP_S.
(9) At NTSC Vertical wide mode 2nd GSC controlled by GSS_S
(10) Use input signal N_P it can be controlled NTSC/PAL Mode.
If you set NTSC/PAL auto detection selection ATMN “H”, it operates internal detection
signal. If ATMN is “L”, NTSC/PAL selected by N_P input Signal.

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3. Feature
(1) Process : CMOS(0.35 )
(2) Package : TQFP: 48pin, Height: 1.0 , Pitch: 0.5 , refer to Fig. 9,10

4. Pin Diagram

Fig. 1 Pin Diagram

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5. Block Diagram

Fig. 2 Block Diagram

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6. Main function description

It makes all of control signal which is needed at external input signal MCLK that is from external
PLL Block.

CNT0 : Set up the timing of output signal(GOE, SOE,GSC,GSS) which is based on Hsync.
input signal of each control is GOE_S, SOE_S,GSC_E,GSS_S, it is based on ‘H’, ‘L’
setting.

CNT1 : Set up the timing as taking the signal value which is set up at CNT0(GOE_R,GOE_F,
SOE_R, SOE_F, GSC_R,GSS_F), set up Vertical Reset signal.

CNT2N : Block of setting the vertical control signal when input NTSC signal.
Set up the Vertical control signal by taking MODE1,2,3 signal from outside and
GSC_VW, GOE_IN,SOE_IN, GSS_IN from CNT1.

CNT2P : Block of setting the vertical control signal when input PAL signal.
Set up the Vertical control signal by taking MODE1,2,3 signal from outside and
GSC_VW, GOE_IN,SOE_IN, GSS_IN from CNT1.

CNT3N : Set up Source Start Pulse(SSP) and Source Sampling Clock(SSC) of Normal mode
by taking HSY from CNT 5 Block.

CNT3F : Set up Source Start Pulse(SSP) and Source Sampling Clock(SSC) of Full mode
by taking HSY from CNT 5 Block.

CNT3C : Set up Source Start Pulse(SSP) and Source Sampling Clock(SSC) of wide mode
by taking HSY from CNT 5 Block.

CNT4 : Change Gate Output Enable(GOE) at NTPASEL to ‘L’ by taking RESET at power on
and FVSY

CNT6 : Make several clock delayed FRP ,which is from NTPASEL.

NTPASEL : Choose Vertical Control Signal of NTSC/PAL Mode

MODH : Choose Horizontal Control Signal of each MODE

Delay : Make SSC1, SSC2 output signal delay certain timing as following MP15

CNT5 : Set up the output signal to meet the synchronous of PLL.

The block of sensing NTSC/PAL signal and sensing of no-signal.

L/R SEL : Decide the SSPL and SSPR by the external input L/R signal.

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7. Pin Configuration
Table 1. Pin Configuration

Pin No. Name Type I/O Pad Pin No. Name Type I/O Pad

1 CSY In Normal 25 GOE Out 4

2 VSM In Normal 26 SSPL Out Tri-state(4 )

3 VDD Power - 27 GND GND -

4 LRS In Pull Down 28 LRO Out 4

5 UDS In Pull Down 29 SRESET Out 4

6 MODE3 In Pull Up 30 SOE Out 4

7 MODE2 In Pull Up 31 SSC Out 8

8 MODE1 In Pull Up 32 SSC1 Out 8

9 HSY Out 4 33 SSC2 Out 8

10 NP_O Out 4 34 SSPR Out Tri-state(4 )

11 GND GND - 35 VDD Power -

12 DIV Out 4 36 GSP_S In Pull Down

13 DIV_RC In Normal 37 STRN In Pull Up

14 PDP Out Tri-state(4 ) 38 N_P In Pull Up

15 RESET In Normal 39 ATMN In Pull Up

16 SOE_S In Pull Down 40 SSP_S2 In Pull Down

17 SOE_E In Pull Down 41 SSP_S1 In Pull Down

18 MCLK In Normal 42 GOE_S In Pull Down

19 VDD Power - 43 GND GND -

20 MCLKO Out 4 44 GSS_S In Pull Down

21 FSEL In Pull Up 45 VCAC Out 4

22 UDO Out 4 46 HSYSC Out 4

23 GSP Out 4 47 FRP Out 4

24 GSC Out 4 48 MP15 In Pull Down

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8. Signal Description

Table 2. Signal Description

No. Name PIN Function Description

Composite Sync Signal or Horizontal Sync Signal Input

1 CSY I Sync Signal Input
(Synchronization Period : Hi time)

Vertical Modulated Signal from Composite Signal or Vertical Sync Signal Input
2 VSM I Sync Signal Input
(Synchronization Period : Hi time)

3 VDD - Power 3.3V DC Voltage ( 10%)

When LRS “H” : SSPL”Enable”, SSPR “Hi-Z”, LRO”L”

( Right Left Direction Scan )
4 LRS I Horizontal Scanning Direction Select
When LRS “L” : SSPL”Hi-Z”, SSPR “Enable”, LRO”H”
( Left Right Direction Scan )

When UDS “H” : UDO=”L” ( Down Up Direction Scan )

5 UDS I Vertical Scanning Direction Select
When UDS “L” : UDO=”H” ( Up Down Direction Scan )

6 MODE3 I Screen Display Mode Selection 3 Refer to table 5, fig 3-1 ~ 3-5

7 MODE2 I Screen Display Mode Selection 2 Refer to table 5, fig 3-1 ~ 3-5

8 MODE1 I Screen Display Mode Selection 1 Refer to table 5, fig 3-1 ~ 3-5

9 HSY O Horizontal sync Output(Negative) Horizontal sync Output(Negative)

When ATMN “H” : NP_O = ”H” at NTSC, NP_O = ”L” at PAL input
(Auto detect mode)
10 NP_O O NTSC/PAL Selection output
When ATMN “L” : NP_O output depends on input NTSC/PAL select signal N_P.
[ N_P=”H” (NTSC), N_P=”L” (PAL) ]

11 GND - Ground Ground

Horizontal Display Position is controlled by DIV. PDP signal synchronized DIV.

12 DIV O Horizontal Display Position Control
PLL Circuit block makes MCLK. (refer to application circuit Fig.12 )

For external horizontal display position control. DIV output adopted external
13 DIV_RC I Horizontal Display Position Control Input
circuit and DIV_RC synchronized PDP Signal. (refer to application circuit Fig.12)

It is made by CSY and DIV. External PLL circuit was synchronized by PDP Signal.
14 PDP O Phase detect Pulse
(refer to Fig.4, Fig.12 )

15 RESET I Reset Logic Initial Reset

16 SOE_S I SOE Rising Selection SOE(INH) Rising position Control. Refer to Fig.8, Table 4.

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No. Name PIN Function Description

17 SOE_E I SOE Falling Selection SOE(INH) falling position selected by this pin. Refer to Fig.8, Table4.

It’s a synchronized Clock which is made by PLL circuit. It is used timing

18 MCLK I Main Clock
controller main clock.(typ : 19.4 ) Refer to circuit diagram Fig.12.

19 VDD - Power 3.3V DC Voltage ( 10%)

For synchronizing PLL MCLKO inverted output MCLK (typ : 19.4 )

20 MCLKO O Clock output
Refer to circuit diagram Fig.12.

FSEL”H” : Black Screen Display when No Signal.

21 FSEL I No Signal Detect Selection Pin
FSEL”L” : none use

When UDS “H” : UDO=”L” ( Down Up Direction Scan )

22 UDO O Gate Drive IC Up/Down Selection Output
When UDS “L” : UDO=”H” ( Up Down Direction Scan )

It is synchronized GSC falling edge which is 1 Horizontal High time Period width
23 GSP O Gate Drive IC Start Pulse
and 1 Vertical Frequency. The wave form refer to Fig.6-1~Fig.7-3 .

24 GSC O Gate Drive IC Shift Clock It’s used Gate Drive IC Shift Clock. Timing Diagram refer to Fig.8.

Gate Drive IC Output is disabled when GOE Low time.

25 GOE O Gate Drive IC Output Enable
Timing Diagram refer to Fig.8.

When LRS “H” : SSPL”Enable”, SSPR “Hi-Z”, LRO”L”

( Right Left Direction Scan )
26 SSPL O Horizontal Start Pulse(Left)
When LRS “L” : SSPL”Hi-Z”, SSPR “Enable”, LRO”H”
( Left Right Direction Scan )

27 GND - Ground Ground

When LRS “H” : SSPL”Enable”, SSPR “Hi-Z”, LRO”L”

Horizontal Scanning Direction Output ( Right Left Direction Scan )
28 LRO O
(Source Drive IC Input) When LRS “L” : SSPL”Hi-Z”, SSPR “Enable”, LRO”H”
( Left Right Direction Scan )

It is used for reset of Source Driver IC which is generated the same as positive
29 SRESET O Source Drive IC Reset
Vsync. If you need Vsync you can use SRESET signal.

Image Data enter into Liquid Crystal Panel data line from Source Drive IC
when SOE rising and falling time.
30 SOE O Source Drive IC Output Enable
Source Drive IC output moves to Hi-Z When SOE High Period.
The wave form refer to Refer to Fig.6-1~Fig.7-3 and Fig.8.

31 SSC O Source D-IC Shift Clock It is used for Source Drive IC Shift Clock which is differ from Image Display Mode.

SSC1 is delayed Clock from SSC which delay time is 17 (typ)

32 SSC1 O Source D-IC Shift Clock 1
It’s used for successive sampling mode when MP15= “H” .

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No. Name PIN Function Description

SSC2 is delayed Clock from SSC1 which delay time is 17 (typ)

33 SSC2 O Source D-IC Shift Clock 2
It’s used for successive sampling mode when MP15= “H” .

When LRS “H” : SSPL “Enable”, SSPR “Hi-Z”, LRO “L”

( Right Left Direction Scan )
34 SSPR O Horizontal Start Pulse(Right)
When LRS “L” : SSPL “Hi-Z”, SSPR “Enable”, LRO “H”
( Left Right Direction Scan )

35 VDD - Power 3.3V DC Voltage ( 10%)

GSP Signal outputs referred to page 17-1~18-3 timing Diagram when GSP_S is “L”
36 GSP_S I GSP Position Control
If GSP_S is “H” above GSP shifted 1 Horizontal Period.

37 STRN I ODD/EVEN GSP Position Control Referred to Fig.6-1~ Fig.7-3.

When ATMN “H” : NP_O = “H” at NTSC, NP_O = “L” at PAL input
(Auto detect mode)
38 N_P I Manual NTSC/PAL Selection
When ATMN “L” : NP_O output depends on input NTSC/PAL select signal N_P.
[ N_P= “H” (NTSC), N_P= “L” (PAL) ]

When ATMN “H” : NTSC/PAL Automatically detect.

39 ATMN I NTSC/PAL Auto Selection
When ATMN “L” : NTSC/PAL manually detect.

Horizontal Screen Display Position controlled by SSP_S2, SSP_S1 which is change

40 SSP_S2 I SSP Start Position Control
SSPL,SSPR position. Refer to Fig.5.

Horizontal Screen Display Position controlled by SSP_S2, SSP_S1 which is change

41 SSP_S1 I SSP Start Position Control
SSPL,SSPR position. Refer to Fig.5.

This option control GOE Width which is control Gate Drive IC Output High Period.
42 GOE_S I GOE Width Control
Refer to Fig.8.

43 GND - Ground Ground

It is Control GSC output when NTSC Vertical expand mode(Cinema,Wide2),

44 GSS_S I GSC(GSS) Control at NTSC Mode
which is refer to Fig6-2~6-3 and page 19.

It’s used for Liquid Crystal Panel Common Voltage Control Signal.
45 VCAC O Common Voltage Control Signal
Refer to Fig.6-1~ Fig.7-3.

46 HSYSC O Hsync Output for IR3Y29B (Negative) It’s used for CHROMA IC Hsync Input.

47 FRP O Video Signal Polarity Control It’s used for Video image Signal Polarity Control input.

Selection of Source Driver IC Data Sampling Mode.

48 MP15 I Sampling Mode selection MP15 “H” : Successive Mode ( sampling clock : SSC,SSC1,SSC2 )
MP15 “L” : Simultaneous Mode ( sampling clock : SSC ), (SSC1,SSC2 = “L” )

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9. Electrical SPECIFICATION
(1) Absolute Maximum Rating

Item Parameter Min Typ Max Unit Notes

VDD Input Voltage -0.3 - 3.8 V

VI CMOS input Signal Voltage -0.3 - VDD+0.3 V

VO CMOS output Signal Voltage -0.3 - VDD+0.3 V

TSTG Storage temperature -40 - +125

TLSTG Lead Temperature(Soldering, 4sec) - - +260

Notes : This can be destroyed over the maximum rating, LPL didn’t assure the secure
of component. All function of this component must be operated under normal
operating condition

(2) Normal Operating Condition

Item Parameter Min Typ Max Unit Notes

VDD Input Voltage 3.0 3.3 3.6 V

VIH CMOS Input Signal Voltage 2.0 - VDD V

VIL CMOS Output Signal Voltage 0 - 0.8 V

TOPR Operating Temperature -30 25 85

TREOPR Reliability Operating Temperature -10 25 85

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10. Screen Display range

1) NTSC (N_T = ‘H’, ATMN = ‘L’)

(1) Horizontal Direction (Refer to Fig.5)
a1) FULL Display MODE : Display 480 Pixel
a2) Normal Display MODE : Display 376 Pixel
a3) WIDE Display MODE : Display 480 Pixel

(2) Vertical Direction (Refer to page 17-1~17-3)

b1) FULL Display MODE : Display 23H ~ 256H
b2) CINEMA Display MODE : Display 54H ~ 229H
b3) WIDE2 Display MODE : Display 50H ~ 236H

2) PAL (N_T = ‘L’, ATMN = ‘L’)

(1) Horizontal Direction (Refer to Fig.5)
a1) FULL Display MODE : Display 480 Pixel
a2) Normal Display MODE : Display 376 Pixel
a3) WIDE Display MODE : Display 480 Pixel

(2) Vertical Direction (Refer to page 18-1~18-3)

b1) FULL Display MODE : Display 28H ~300H [eliminate (14n +1, 14n + 7)].
b2) CINEMA Display MODE : Display 47H ~ 280H
b3) WIDE2 Display MODE : Display 35H ~303H [eliminate (22n +1. 22n +16)].

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11. MODE Setting

Table 3. Mode Setting
MODE3 MODE2 MODE1 MODE Description Source Notes

Display evenly by controlling frequency

evenly of whole display under vertical,
FULL
H H H horizontal range of input signal. It uses 16:9 image Fig. 3-1
MODE
16:9 wide input. Display wide horizontally
in case of the display ratio 4:3.

Change horizontal Clock to make image

WIDE output of center display similar with image
H H L 16:9 image Fig. 3-2
MODE input to loose incompatibility with center
display under 4:3 Full mode.

Display to make same with real display

NORMAL
L H H size under input 4:3 display signal, which 4:3 Image Fig. 3-3
MODE
Left/right side displayed black.

The main display area of wide signal(16:9)

CINEMA such like Letter focus size.Use Full mode Letter Focus
H L L Fig. 3-4
MODE horizontally, use more wide than usual Wide Input
vertically to make similar with real image

Make the display same with WIDE

WIDE2 horizontally and use CINEMA vertically
L L H 16:9 image Fig. 3-5
MODE to control center display under 4:3 display
mode. Sort of vertical signal can’t be seen.

L L L test Test mode test test

L H L test Test mode test test

H L H test Test mode test test

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Fig. 3-1 FULL Display MODE

Fig. 3-2 WIDE Display MODE

Fig. 3-3 NORMAL Display MODE

Fig. 3-4 CINEMA Display MODE

Fig. 3-5 WIDE2 Display MODE

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12. DIV, HSY, HSYSC Generation

Fig. 4 DIV, HSY,HSYSC Generation

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13. Horizontal Display Position

Fig. 5 Horizontal Display Position

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14. Vertical Display Method(NTSC)

Fig. 6-1 Vertical Display Position1 (NTSC)

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14. Vertical Display Method(NTSC)

Fig. 6-2 Vertical Display Position2 (NTSC)

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14. Vertical Display Method(NTSC)

Fig. 6-3 Vertical Display Position3 (NTSC)

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15. Vertical Display Method(PAL)

Fig.7-1 Vertical Display Position1 (PAL)

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15. Vertical Display Method(PAL)

Fig.7-2 Vertical Display Position2 (PAL)

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15. Vertical Display Method(PAL)

Fig.7-3 Vertical Display Position3 (PAL)

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16. Control Option

Fig. 8 Control Option

Table 4. Control Option

GOE_S L H Unit Notes

A 15 25 MCLK -
B 30 50 MCLK -

GSS_S L H Unit Notes

C 950 970 MCLK 1)
D 1150 1150 MCLK -

SOE_S L H Unit Notes

E 85 85 MCLK 2)

SOE_E L H Unit Notes

F 100 100 MCLK 2)

Notes : 1) This value used at UDS “L”. Internal modulated GSS rising time used at UDS”H”.
2) SOE rising and falling time is set appropriate timing so fix it at SOE_S, SOE_E “H” “L” .
Others)
- “X : 1/4H”, “Y : 1/2H”, “ Z : 36tMCLK”
- Above Timing Control option is normal conditional control option.
- SSP_S2, SSP_S1 refer to page 16.
- GSP_S “L”refer to page 17-1~18-3, if GSP_S “H”when this case GSP runs 1H shift.

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17. Package

Fig. 9 Package

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[Our Package Dimension ]

Fig. 10 Package

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18. Application Circuit

L G. P h i l i p s L C D C O. , L t d .

Fig. 11 Application Circuit 1/3

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L G. P h i l i p s L C D C O. , L t d .

Fig. 12 Application Circuit 2/3

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L G. P h i l i p s L C D C O. , L t d .

Fig. 13 Application Circuit 3/3

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Application Notes

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