ECS Transactions, 90 (1) 139-146 (2019)

10.1149/09001.0139ecst ©The Electrochemical Society

Embedded DRAM Using C-Axis-Aligned Crystalline In-Ga-Zn Oxide FET

with 1.8V-Power-Supply Voltage

Eri Yamamoto, Seiya Saito, Keita Sato, Kazuma Furutani, Yuto Yakubo, Tatsuya Onuki,
Takanori Matsuzaki, Tomoaki Atsumi, Yoshinori Ando, Tsutomu Murakawa,
Kiyoshi Kato and Shunpei Yamazaki

Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa, Japan

This paper reports the validation of our prototyped memory

operating with 1.8-V power supply and low stand-by power, using
60-nm c-axis-aligned crystalline In-Ga-Zn oxide (CAAC-IGZO)
field-effect transistors (FETs). Its operation evaluation verified that
a reduction in driving voltage is enabled by application of a
negative voltage as a low voltage (VSSL) of a word line. A
negative-voltage generator uses CAAC-IGZO FETs in a
comparator circuit. The total stand-by power including power
consumed by the additional negative-voltage generator is as small
as 120 nW, which is revealed by simulation of a 1Mb-memory
operating at 100 MHz.

Introduction

The progress of IoT system has rapidly increased in the number of sensor nodes, which
causes an issue of an exponential increase in power consumed by data transmission from
the sensors to a server. In addition, prompt access to stored data is required. To solve this
issue, there has been a rising demand for memory as edge devices closer to sensor
terminals (edge-computing memory). The edge-computing memory that stores data
requires low stand-by power (1).
Typical low-power memory includes memories using c-axis aligned crystalline In-
Ga-Zn Oxide (CAAC-IGZO) field-effect transistors (FETs) (214) that have been widely
adopted for the display field (1517). The CAAC-IGZO FETs have an extremely low
off-state current on the order of yoctoamperes per micrometer (yAm) (yocto- is a
metric prefix denoting a factor of 10-24) (2, 17, 1824), and their back gates enable the
control of threshold voltage (25). Scaled CAAC-IGZO FETs to 20 nm have been reported
(26, 27). A dynamic oxide semiconductor random access memory (DOSRAM), where
CAAC-IGZO FETs are used as access transistors in DRAM cells (37), enables long data
retention and long intervals between refresh operations, resulting in low stand-by power
(4, 5).
This work shows the power-supply voltage of DOSRAM for edge computing, which
enables low stand-by power, based on measurement results of 64-kb DOSRAM
fabricated with a process combined with 60-nm CAAC-IGZO FETs and 65-nm Si CMOS
and simulation results of DOSRAM and a negative-voltage generator that uses CAAC-
IGZO FETs and supplies a negative voltage to a word line.

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 ECS Transactions, 90 (1) 139-146 (2019)

60-nm CAAC-IGZO FET Performance

Figure 1 shows back-gate voltage (Vbg) dependence of top gate-drain current (Vg-Ids)
performance of 60-nm CAAC-IGZO FETs, and their Vbg dependence of threshold voltage
(Vth) is shown in Fig. 2. The threshold voltage (Vth) of the CAAC-IGZO FET is
controlled by changing a level of Vbg, whereas Vth of the Si FET is controlled by channel
doping. As shown in Fig. 2, Vth can be controlled to range from 0 to 1.6 V with Vbg
ranging from 0 to 12 V. One of features of the CAAC-IGZO FET is an extremely low
off-state current which allows a high ratio between on-state current (Ion) and off-state
current (Ioff).

0.0001-4
10
L = 60nm
0.0000
10-5 W = 60nm
0.0000-6
10 Vd = 1.2V
T = R.T.
0.0000-7
10
Ids [A]

0.0000-8
10 Vbg = 0 V -12 V
0.0000-9
10
0.0000
-10
10
0.0000
10-11
0.0000
10-12
-2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 3 3.5
Vg [V]

Figure 1. Vbg dependence of Vg-Ids performance.

1.8
1.6
1.4
1.2
1
Vth [V]

0.8
0.6
0.4 L = 60nm
W = 60nm
0.2
Vd = 1.2V
0 T = R.T.
-0.2
-12-11-10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0
Vbg [V]

Figure 2. Vbg dependence of Vth.

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 ECS Transactions, 90 (1) 139-146 (2019)

64-Kb DOSRAM Prototype and its Measurement Results

Our prototyped 64-Kb DOSRAM is composed of four 16-Kb subarrays each consisting
of 16 1-Kb local arrays as shown in Fig. 3. As each local array, a DOSRAM cell array
with open bit line architecture, where 8 DOSRAM cells are connected to a bit line and
128 DOSRAM cells are connected to one word line, is located on a sense amplifier array.
The cell capacitance is 3.5 fF, and the cell size is 3.696 m2. The high voltage and low
voltage (VDD and VSS) for a logic circuit such as a sense amplifier are respectively 1.2 V
and 0.0 V. The high voltage and low voltage for the word line (VDDH and VSSL) are
variable.

Figure 3 Block diagram of 64-Kb DOSRAM.

Dependence of 64-Kb DORAM operation on Vbg and a combination of VDDH and

VSSL was measured (Fig. 4). The voltage width of the word line was fixed to 3.3 V
utilizing a high ratio of IonIoff of CAAC-IGZO FET. Measurement conditions were room
temperature, a write time of 200 ns, a read time of 150 ns, and a retention time of 1 s. In
validation of the memory operation, 10 types of test patterns such checkered and vertical
stripe were written to the memory cells.
The following three conditions were set for a power-supply voltage: VDDHVSSLVbg 
1.8 V1.5 V0 V (Condition 1), 2.5 V0.8 V3 V (Condition 2) and 3.3 V0 V7 V
(Condition 3). Under Condition 1, a negative-voltage generator need not be provided for
the back gate, whereas VSSL needs to be reduced and accordingly VDDH is also lowered.
Under Condition 3, a negative-voltage generator need not be provided for the word line,
whereas the values of VDDH and Vbg are increased. Under Condition 2, which is an
intermediate condition between Condition 1 and Condition 3, both the word line and the
back gate need respective negative-voltage generators, but the absolute values of the
negative voltages are small.

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 ECS Transactions, 90 (1) 139-146 (2019)

VDDH / VSSL [V]

1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3
-1.5 -1.4 -1.3 -1.2 -1.1 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
0.0
Condition1 FAIL
-1.0

-2.0
Vbg [V]

-3.0
Condition2
-4.0
PASS
-5.0

-6.0
FAIL Condition3
-7.0

*Pass means the existence of bit (at a rate less than 1) where write data and read data do not match
each other (NGbit) even for one out of ten types of test patterns.

Figure 4. Memory operation dependence on word line voltages (VDDHVSSL) and Vbg.

Simulation and Results of Negative-voltage Generation Block and DOSRAM

Power consumption of the negative-voltage generator was estimated with the following
two conditions: VDDHVSSLVbg  1.8 V-1.5 V0 V (Condition 1) and 2.5 V0.8 V3 V
(Condition 2). The conditions were set in terms of a reduction in power-supply voltage.
Figure 5 shows a block diagram of a negative-voltage generator used for simulation.
Each of the negative-voltage generators for the word line and the back gate are composed
of a ring oscillator, a charge pump, and a comparator. The ring oscillator and the charge
pump operate intermittently in accordance with output from the comparator.

Figure 5. Block diagram of negative-voltage generator used for simulation.

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 ECS Transactions, 90 (1) 139-146 (2019)

The comparator is fabricated with advantages of CAAC-IGZO FETs used in a

differential pair as shown in Fig. 6. To compare a negative voltage VIN (VSSL or Vbg) and a
reference voltage (Vref), Vref is applied to a top gate of one of CAAC-IGZO FETs, while
the VIN (VSSL or Vbg) is applied to a back gate of the other of the CAAC-IGZO FETs. In
other words, direct input of the negative voltage into the FET is possible, which is a
major feature of this comparator.
Figure 7 shows actual measurement results of the comparator. With voltage
conditions where VDD  1.2 V, VSS  0 V and Vbias  0.7 V, a value of VIN  1.5 V was
detected when Vref  1.18 V is applied.

Figure 6. Comparator using CAAC-IGZO FET.

Figure 7. Actual measurement result of comparator using CAAC-IGZO FET.

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 ECS Transactions, 90 (1) 139-146 (2019)

Table 1 shows estimates of power consumption of a memory and the negative-voltage

generator, on the assumption that 1-Mb memory and the negative-voltage generator were
driven at room temperature with typical conditions, both for Condition 1 and Condition 2
(Table 1). In an active mode, the frequency of memory operation cycle was set to 100
MHz, and the negative-voltage generator was under the intermittent operation. In a stand-
by mode, the memory conducted power gating, and the negative-voltage generator was
under the intermittent operation. With the above conditions, operations of the memory
and the negative-voltage generator in the active and stand-by modes were simulated to
calculate the power consumed by the memory and the negative-voltage generator.
As the simulation results, Condition 1 causes lower stand-by power than Condition 2.
In the stand-by mode, the amount of power for the memory is reduced by power gating;
the main power consumption is derived from the negative-voltage generator. In the
negative-voltage generator, the power amount needed to generate a negative voltage is
very small due to the intermittent operation of the negative-voltage generator, and the
power is largely consumed by the comparator. Thus, the stand-by power is low under
Condition 1 for which generation of Vbg is not necessary. In the active mode, the ratio
of negative-voltage generation power to the total power consumption is small in either
Condition 1 or Condition 2. In addition, the area of negative-voltage generator just
occupies 0.2 of that of 1-Mb DOSRAM.
Furthermore, on the assumption of IoT usage, power consumption in the intermittent
operation was estimated with Condition 1 and Condition 2. In this estimation, the stand-
by period was set to 1 day, and the active-mode periods were set to 8 seconds, 0.8
seconds, and 0.08 seconds. Power consumption was lower by 16, 42, and 49% in the
respective active-mode periods with Condition 1 than that with Condition 2.

Table 1. Estimate of power consumption.

Conclusion

DOSRAM using CAAC-IGZO FETs, which is the next-generation memory, achieves a

reduction in driving voltage by control of Vbg, VDDH and VSSL of the word line. The
power-supply voltage of the word line (VDDH) can be reduced to 1.8 V while VSSL is 1.5
V and Vbg is 0 V. The negative-voltage generators for the word line and the back gate
each employ a comparator using CAAC-IGZO FETs to which a negative voltage can be
directly input, and are driven intermittently. The simulation reveals that such a DOSRAM
just needs 120-nW stand-by power. From the above validation, DOSRAM is an edge-
computing memory enabling low power-supply voltage and low stand-by power.

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 ECS Transactions, 90 (1) 139-146 (2019)

467 μm

811 μm
16Kb

64 Kb

Photo1. Micrograph of 64-Kb memory macro prototyped with hybrid process of 60-nm
CAAC-IGZO FET and 65-nm Si CMOS.

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