HDL LAB RECORD

EXPERIMENT RECORD

NOVEMBER 26, 2020

NAME: P. SAIKIRAN
Dept/sec: ECE A
ROLL No. : AP18110020025
TABLE OF CONTENTS:
Experiment No. Name of experiment Page No.
Combinational Circuits Design:
1 Design and test a Half adder and design a Full adder using half
adder modules with structural modeling. 1
2 Design and test a full adder using data flow modelling. 3
3 Design and test a 2x1 MUX using data flow modelling and design 5
a 4x1 MUX using structural modelling and 2x1 MUX.
4 Design and test a 2x4 Decoder circuit and then design a 3x8 9
decoder using above designed 2x4 decoder modules.
5 Use Data flow modelling to design and test a 4-bit magnitude 12
comparator circuit in Verilog HDL.
6 Design and test a 4x2 priority encoder circuit in HDL. 14
Obtain the Verilog HDL design and test for a logic circuit that will 16
7 generate a logic 1 on output z1 if a 4-bit unsigned binary number
N = x 1 x 2 x 3 x 4 satisfies the following criteria, where x4 is the
low-order bit. Use HDL operators.

Experiment No. Name of Experiment Page No.

Sequential Circuits Design:
Design and write Test bench for a positive D latch, negative D
1 latch using behavioral modelling of Verilog HDL. Design and test a 18
master-slave positive edge triggered D FF using above D latches
and structural modeling of Verilog HDL.
Design and write Test bench for a negative edge triggered D Flip- 23
2 flop with asynchronous reset using behavioral modelling of
Verilog HDL.
3 Design and write Test bench for a positive edge triggered JK Flip- 24
flop using case statement of Verilog HDL.
4 Design and write Test bench for a 8-bit universal shift register 27
using behavioral modelling of Verilog HDL.
5 Design and write Test bench for a 4-bit binary synchronous 30
up/down counter using behavioral modelling of Verilog HDL.
6 Design and write Test bench for a FSM to detect 3 and more 32
consecutive 1’s of an incoming serial input data input line.
7 Design and write Test bench for a vending machine FSM which 35
will take 5Rs and 10 Rs coins as inputs and release an item of
value 15 Rs. Assume only one coin is inserted at a time and no
change is given back if extra amount is inserted for a given item.
8 Design Verilog HDL module of FSM to Build an electronic 38
combination lock with a reset button, two number buttons (0 and
1), and an unlock output. The combination should be 01011.
Experiment No. Name of the experiment Page No.
Arithmetic Circuits Design:
1 Design and write Test bench for 4-bit adder, subtractor circuit in 41
Verilog- HDL.
2 Design and write Test bench for a 4-bit Fixed point Multiplier 45
circuit.
3 Design and write Test bench for a 8-function arithmetic and logic 48
unit.
4 Design and write Test bench for a floating point adder circuit in 51
Verilog HDL.
5 Design and write Test bench for a floating point multiplier circuit in 55
Verilog HDL.
 Combinational Circuit Design:
Experiment No. 1:
Design and test a Half adder and design a Full adder using half adder modules with
structural modelling.

Aim: To design and test a Half adder and design a Full adder using half adder modules with structural
modelling.
Objective: The main objective of this experiment is to design a half adder and full adder using half adder
module which is been designed in structural modelling which is a lowest level of abstraction obtained
using logic gates.

Structural modelling Module Code:

module half_adder(s, c, x, y); //module name and sensitivity list
output s,c; //outputs
input x,y; //inputs
xor (s,x,y); //for sum
and (c,x,y); //for carry
endmodule
// By using half adder module creating a full adder.
module full_adder (sum, cout, x, y, z); //module name and sensitivity list
output sum,cout; //outputs
input x,y,z; //inputs
wire sl,cl,c2;
half_adder Bl(sl,cl,x,y);
half_adder B2 (sum,c2, sl, z) ; //for sum
or (cout, cl, c2) ; //for carry
endmodule

1
Testbench code:
module adder_tb(); //module name
reg x,y,z; //inputs are registers

wire s,c,sum,cout; //outputs are wires

initial begin : apply_stimulus

reg [3:0] invect; //take a temporary register for test cases

for(invect=0;invect<9;invect=invect+1) //initialization of the for loop

begin
{x,y,z}=invect[3:0]; //concatenate the testcases
#10 $display("x,y,z=%b,s=%b,c=%b,sum=%b,cout=%b",{x,y,z},s,c,sum,cout); //display statement

end
end

half_adder inst1(s, c, x, y); //instantiation of half adder module

full_adder inst2(sum, cout, x, y, z); //instantiation of full adder module

endmodule

Output Waveform:

Conclusion: Therefore in this experiment we came to know and analyzed the simulation about half adder
and full adder with half adder modules with structural modelling.

2
Experiment No. 2:

Design and test a full adder using data flow modelling.

Aim: To design and test a full adder using data flow modelling.

Objective: The main objective of this experiment is to design and test the full adder with data flowing
where a full adder Full Adder is the adder which adds three inputs and produces two outputs. The first
two inputs are A and B and the third input is an input carry as C-IN. Here the reason of using dataflow
modelling is Dataflow modelling provides the means of describing combinational circuits by their
function rather than by their gate structure. In this model “assign” is the main statement used.

Data Flow modelling Module Code:

module full_adder( A, B, Cin, S, Cout); //module name and sensitivity list
input wire A, B, Cin; //inputs

output reg S, Cout; //outputs

always @(A or B or Cin) //procedural statement

begin
S = A ^ B ^ Cin; //sum

Cout = A&B | (A^B) & Cin; //carry

end
endmodule

3
Testbench code:
module full_adder__tb(); //module name

reg A,B,Cin; //inputs as registers

wire S, Cout; //outputs as wire

initial begin : apply_stimulus

reg [3:0] invect; //temporary register
for(invect=0;invect<9;invect=invect+1) //for loop initialization

begin
{A,B,Cin}=invect[3:0]; //concatenation

#10 $display("A,B,Cin=%b,S=%b,Cout=%b",{A,B,Cin},S,Cout); //display statement

end
end
full_adder inst1(A,B,Cin,S,Cout); //instantiation of verilog module

endmodule
Output Waveform:

Conclusion: Therefore in this experiment we came to know and analyzed the simulation about full adder
with data flow modelling.

4
Experiment No. 3:
Design and test a 2x1 MUX using data flow modelling and design a 4x1 MUX using
structural modelling and 2x1 MUX.
Aim: To design and test a 2x1 MUX using data flow modelling and design a 4x1 MUX using structural
modelling and 2x1 MUX.
Objective: The main objective of this experiment is to design a 2*1 MUX using data flow and a 4*1
MUX and 2*1 using structural modelling. Here in 2*1 MUX consists of two inputs D0 and D1, one select
input S and one output Y. Depends on the select signal, the output is connected to either of the inputs and
a 4*1 MUX consists four data input lines as D0 to D3, two select lines as S0 and S1 and a single output
line Y.

2*1 MUX data flow modelling Module Code:

//2:1 mux using data flow modelling
module two_to_one_mux(D0, D1, S, Y1);
output Y1; // output port
input D0, D1, S; // input declaration
assign Y1=(S)?D1:D0; // port declaration using data flow modelling
endmodule
Testbench code:
module two_to_one_mux_tb();
reg D0, D1, S;

wire Y1;
mux_2_1_dfm inst1(D0, D1, S, Y1);

initial begin
D0=0;D1=1;S=0;

#10 D0=0;D1=1;S=1;
end
initial begin

$monitor("D0=%b,D1=%b,S=%b,Y1=%b",D0,D1,S,Y1);

5
end

endmodule

Output Waveform:

2*1 MUX structural flow modelling Module Code:

//2:1 mux using structural modelling

module two_to_one_mux(Y2, D0, D1, S);

output Y2;

input D0, D1, S;

wire T1, T2, T3;
and u1(T1, D1, S);

not u2(T2, S);

and u3(T3, D0, T2);

or u4(Y2, T1, T3);

endmodule

Testbench code:
module two_to_one_mux_tb();

reg D0, D1, S;

wire Y2;

mux_2_1_sm inst2(Y2, D0, D1, S);

initial begin
D0=0;D1=1;S=0;
#10 D0=0;D1=1;S=1;

6
end

initial begin
$monitor("D0=%b,D1=%b,S=%b,Y2=%b",D0,D1,S,Y2);

end
endmodule

Output Waveform:

4*1 MUX structural flow modelling Module Code:

module four_to_one_mux (out, a, b, c, d, s0, s1);
output out;

input a, b, c, d, s0, s1;

wire w,x,y,z;

and and1(w,~s1,~s0,a);
and and2(x,s1,~s0,b);

and and3(y,~s1,s0,c);
and and4(z,s0,s1,d);
or or1(out,w,x,y,z);

endmodule

7
Testbench code:
module four_to_one_mux_tb();
reg a,b,c,d,s0,s1;

wire out;
m41 inst3(out, a, b, c, d, s0, s1);

initial begin
a=1;b=0;c=0;d=0;s0=0;s1=0;

#10 a=0;b=1;c=0;d=0;s0=0;s1=1;
#10 a=0;b=0;c=1;d=0;s0=1;s1=0;

#10 a=0;b=0;c=0;d=1;s0=1;s1=1;
end
initial begin

$monitor("a=%b,b=%b,c=%b,d=%b,s0=%b,s1=%b,out=%b",a,b,c,d,s0,s1,out);
end

endmodule

Output Waveform:

Conclusion: Therefore in this experiment we have executed and simulating the waveform of 2*1 MUX in
data flow and structural modelling and 4*1 MUX using structural modelling.

8
Experiment No. 4:

Design and test a 2x4 Decoder circuit and then design a 3x8 decoder using above designed 2x4
decoder modules.
Aim: To Design and test a 2x4 Decoder circuit and then design a 3x8 decoder using above designed 2x4
decoder modules.
Objective: The main object of this experiment is to Design a 2x4 Decoder circuit and then design a 3x8
decoder using above designed 2x4 decoder modules where a 2 binary inputs labelled A and B are decoded
into one of 4 outputs, hence the description of 2-to-4 binary decoder and a 3*8 decoder circuit gives 8 logic
outputs for 3 inputs and has a enable pin. The circuit is designed with AND and NAND logic gates .

Module Code for 2*4 Decoder:

module two_to_four_dec(output [3:0]y, input e, input [1:0]a);

assign y[0]=~a[1] & ~a[0] & e;

assign y[1]=~a[1] & a[0] & e;

assign y[2]= a[1] & ~a[0] & e;

assign y[3]= a[1] & a[0] & e;

endmodule

Testbench code:
module two_to_four_dec_tb();

reg [1:0]a, e;
wire [3:0]y;

dec2x4 inst3(.y(y),.e(e), .a(a));

initial begin

e=0;a=3'b00;
#10 e=0;a=3'b01;

#10 e=0;a=3'b10;

9
#10 e=0;a=3'b11;

#10 e=1;a=3'b00;
#10 e=1;a=3'b01;

#10 e=1;a=3'b10;
#10 e=1;a=3'b11;

#10 $finish;
end

initial begin
$display("a=%b,e=%b,y=%b",a,e,{y[3],y[2],y[1],y[0]});

end
endmodule

Output Waveform:

Module code for 3*8 decoder with 2*4 module:

module two_to_four_dec(output [3:0]y, input e, input [1:0]a);
assign y[0]=~a[1] & ~a[0] & e;

assign y[1]=~a[1] & a[0] & e;

assign y[2]= a[1] & ~a[0] & e;

assign y[3]= a[1] & a[0] & e;

endmodule

module three_to_eight_dec(output [7:0]y, input[2:0] a);

dec2x4 inst1(y[3:0], ~a[2], a[1:0]);
dec2x4 inst2(y[7:4], a[2], a[1:0]);
endmodule

10
Testbench Code:
module three_to_eight_dec_tb();
reg [2:0]a;

wire [7:0]y;
dec3x8 inst3(.y(y), .a(a));

initial begin
a=3'b000;

#10 a=3'b001;
#10 a=3'b010;

#10 a=3'b011;
#10 a=3'b100;
#10 a=3'b101;

#10 a=3'b110;
#10 a=3'b111;

#10 $finish;
end

initial begin
$display("a=%b,y=%b",a,{y[7],y[6],y[5],y[4],y[3],y[2],y[1],y[0]});

end
endmodule

Output Waveform:

Conclusion: Therefore by this experiment we have executed and simulated 2x4 Decoder circuit and then
design a 3x8 decoder using above designed 2x4 decoder modules.

11
Experiment No. 5:

Use Data flow modelling to design and test a 4-bit magnitude comparator circuit in Verilog
HDL.
Aim: To design a 4-bit magnitude comparator circuit in Verilog HDL by using data flow modelling.

Objective: The main objective of this experiment is to design and simulate a 4-bit magnitude comparator
circuit in Verilog HDL by using data flow modelling. Where a 4-bit comparator is A comparator used to
compare two binary numbers each of four bits is called a 4-bit magnitude comparator.

Module code for 4-bit magnitude comparator:

module four_bit_comparator(A,B,less,equal,greater);
input [3:0] A;
input [3:0] B;

output less, equal, greater;

reg less, equal, greater;

always @(A or B)
begin
if(A > B)
begin

assign
less = 0;

equal = 0;
greater = 1;
end

else if(A == B)
begin
assign
less = 0;

12
 equal = 1;

greater = 0;
end

else
begin

assign
less = 1;

equal = 0;
greater =0;

end
end
endmodule

Testbench Code:
module four_bit_comparator_tb ();

reg [3:0]A,B;
verilog inst1(A,B,less,equal,greater);

initial begin
A=1;B=0;

#10 A=1;B=1;
#10 A=0;B=1;

end
initial begin
$monitor("A=%b,B=%b,less=%b,equal=%b,greater=%b",A,B,less,equal,greater);

end
endmodule

Output Waveform:

13
Experiment No. 6:

Design and test a 4x2 priority encoder circuit in HDL.

Aim: To design and simulate a 4x2 priority encoder circuit in HDL.

Objective: The main objective of this experiment is to design and simulate the waveform of 4*2 priority
encoder

Module code for 4*2 priority encoder:

module four_to_two_priority_encoder(A, Y);
input [3:0]Y; // inputs with 0 to 3 sec

output reg [1:0]A; // outputs

always@(Y) // non blocking statement

begin
case(Y)

4'b0001:A = 2'b00;
4'b001x:A = 2'b01;

4'b01xx:A = 2'b10;
4'b1xxx:A = 2'b11;
default:$display("Error!");

endcase
end

endmodule

14
Testbench code:
module four_to_two_priority_encoder _tb();
reg [3:0]Y;

wire [1:0]A;
priority_encoder inst1(A, Y);

initial begin
Y=4'b0001;

#10 Y=4'b001x;
#10 Y=4'b01xx;

#10 Y=4'b1xxx;
end
initial begin

$display("Y=%b,A=%b",{Y[3],Y[2],Y[1],Y[0]},{A[0],A[1]});
end

endmodule

Output Waveform:

Conclusion: Therefore in this experiment we have executed and simulated the 4*2 priority encoder using
Verilog hdl.

15
Experiment No. 7:

Obtain the Verilog HDL design and test for a logic circuit that will generate a logic 1 on output
z1 if a 4-bit unsigned binary number N = x 1 x 2 x 3 x 4 satisfies the following criteria, where
x4 is the low-order bit. Use HDL operators.
Aim: To design and implement a logic circuit that will generate a logic 1 on output Z1 if a 4-bit unsigned
binary number N = x 1 x 2 x 3 x 4 satisfies the following criteria, where x4 is the low-order bit. Use HDL
operators.
Objective: The main objective of this experiment and simulate a logic circuit that will generate a logic 1
on output Z1 if a 4-bit unsigned binary number N = x 1 x 2 x 3 x 4 satisfies the following criteria, where
x4 is the low-order bit. Use HDL operators.

Module code:
module logic_circuit(input x1, x2, x3, x4,output z, z1);

wire net1, net2, net3, net4, net5, net6, net7;

nor(net1, x2, x2);

nor(net2, x1, net1, x4);

nor(net3, x3, x3);
nor(net4, x4, x4);

nor(net5, x2, net3, net4);

nor(net6, x2, x2);

nor(net7, net6, x3);

nor(z, net2, net5, net7);

nor(z1, z, z);
endmodule

16
Testbench code:
module logic_circuit _tb();

reg x1, x2, x3, x4;

wire z, z1;

initial
begin : apply_stimulus

reg [4:0] invect;

for(invect=0;invect<16;invect=invect+1)

begin
{x1, x2, x3, x4}=invect [4:0];
#10 $display("x1 x2 x3 x4= %b, z1= %b",{x1, x2, x3, x4},z1);

end
end

question_3 inst1(x1, x2, x3, x4, z, z1);

endmodule

Output Waveform:

Conclusion: Therefore in this experiment we have executed and simulated a logic circuit that will generate
a logic 1 on output Z1 if a 4-bit unsigned binary number N = x 1 x 2 x 3 x 4 satisfies the following criteria,
where x4 is the low-order bit. Use HDL operators.

17
 Sequential Circuits Design:

Experiment No. 1:
Design and write Test bench for a positive D latch, negative D latch using behavioural
modelling of Verilog HDL. Design and test a master-slave positive edge triggered D FF using
above D latches and structural modelling of Verilog HDL.
Aim: To design and simulate a positive D latch, negative D latch using behavioural modelling of Verilog
HDL. Design and test a master-slave positive edge triggered D FF using above D latches and structural
modelling of Verilog HDL.

Objective: The main objective of this experiment The D flip-flop described here is positive edge-
triggered which means that the input which is stored is that input which is seen when the input clock
transitions from 0 to 1. This flip-flop is built from two gated latches one a master D latch, and the other a
slave SR latch. The master takes the flip-flops inputs.

Module code for positive D latch:

module dl(d,en,q);
input d,en;
output q;
reg q;
always @ (*)
begin
if (en)
q <= d;
end
endmodule
Testbench Code:
module p2_tb();
reg d,en;
wire q;
initial begin

18
d=1'b0;en=1'b0;
#5 en=1'b1;
#10 d=1'b1;en=1'b0;
#5 en=1'b1;
#10 d=1'b0;en=1'b0;
#20 d=1'b1;en=1'b1;
#10 d=1'b0;en=1'b0;
end
dl ins1(d,en,q);
endmodule
Output Waveform:

Module code for Negative D-Latch:

module dl(d,en,q);
input d,en
;
output q;
reg q;
always @ (*)
begin
if (!en)
q <= d;
end
endmodule

19
Testbench code:
module p2_tb();
reg d,en
;
wire q;
initial begin
d=1'b0;en=1'b0;
#5 en=1'b1;
#10 d=1'b1;en=1'b0;
#5 en=1'b1;
#10 d=1'b0;en=1'b0;
#20 d=1'b1;en=1'b1;
#10 d=1'b0;en=1'b0;
end
dl ins1(d,en,q);
endmodule
Output Waveform:

Module code for positive edge triggered D FF:

module pos_d_latch(
input en,
input d,
output q,
output qb
);
reg q

20
wire qb;
always @(en or d)
begin
if(en==1'b0) q<=q;
else q<=d;
end
assign qb=~q;
endmodule
module neg_d_latch(
input en,
input d,
output q,
output qb
);
reg q;
wire qb;
always @(en or d)
begin
if(en==1'b1) q<=q;
else q<=d;
end
assign qb=~q;
endmodule
module a2_q3(
input clk,
input d,
output q,
output qb
);
wire q1,q2;
pos_d_latch p(clk,d,q1,q2);
neg_d_latch n(~clk,q1,q,qb);
endmodule

21
Testbench code:
module tb_a2_q3(
);
reg clk,d;
wire q, qb;
initial
begin
clk = 1'b0;
forever #5 clk =~clk;
end
initial
begin
d = 1'b1;
#20 d = 1'b0;
#20 d = 1'b1;
#20 d = 1'b0;
#20 d = 1'b1;
#20 d = 1'b0;
end
a2_q3 w (clk,d,q,qb);
endmodule

Output Waveform:

Conclusion: Therefore in this experiment we have executed and simulated positive negative D-ff and
positive and negative edge triggered D-ff.

22
Experiment No.2:

Design and write Test bench for a negative edge triggered D Flip-flop with asynchronous reset
using behavioral modelling of Verilog HDL.
Aim: To execute and simulate and design of a negative edge triggered D Flip-flop with asynchronous reset
using behavioral modelling.
Objective: The main objective of this experiment is to Design and write Test bench for a negative edge
triggered D Flip-flop with asynchronous reset using behavioral modelling of Verilog HDL.

Module Code:
Module async_dff(d,clk,reset,q);
input d,clk,reset;
output reg q;
always @ (negedge clk or
posedge reset)
if(reset)
q <= 1'b0;
else
q <= d;
endmodule
Testbench code:
module async_dff_tb();
reg d,clk,reset;
wire q;
initial begin
clk = 1'b0;

23
forever #5 clk = ~clk;
end
initial begin
d = 1'b1;reset =1'b1;
#10 d = 1'b0;
#10 d = 1'b1;reset =1'b0;
#25 d = 1'b1;
#10 reset =1'b1;
#10 reset=1'b0;
#20 d=1'b0;
end
async_dff ad(d,clk,reset,q);
endmodule
Output Waveform:

Conclusion: Therefore in this experiment we have executed and simulated design of a negative edge
triggered D Flip-flop with asynchronous reset using behavioral modelling.

24
Experiment No. 3:
Design and write Test bench for a positive edge triggered JK Flip-flop using case statement
of Verilog HDL.
Aim: To execute and simulate and design a positive edge triggered JK Flip-flop using case statement of
Verilog HDL.
Objective: The main objective of the experiment is Design to and write Test bench for a positive edge
triggered JK Flip-flop using case statement of Verilog HDL

Module Code:
module pet_jk_ff(j,k,clk,q);
input j,k,clk;
output q;

reg q;
always @ (posedge clk)

case ({j,k})
2'b00: q<=q;
2'b01: q<=0;

2'b10: q<=1;
2'b11: q<=~q;

endcase
endmodule

Testbench:
module pet_jk_ff_tb();

reg j,k,clk;
wire q;
initial begin

clk=1'b0;
forever #5 clk = ~clk;

25
end

Initial begin
j<=1'b0;k<=1'b0;

#10 j<=1'b0;k<=1'b1;
#10 j<=1'b1;k<=1'b0;

#10 j<=1'b1;k<=1'b1;
end

jk j1(j,k,clk,q);
endmodule

Output Waveform:

Conclusion: Therefore in this experiment we have executed and simulated and observed a positive edge
triggered JK-FF using case statement.

26
Experiment No.4:

Design and write Test bench for a 8-bit universal shift register using behavioural modelling
of Verilog HDL.
Aim: To execute and simulate and design 8-bit universal shift register using behavioural modelling of
Verilog HDL.
Objective: The main objective of this experiment is to implement and simulate a 8-bit universal shift
register using behavioural modelling.

Module code:
module a2_q9(
input [1:0] s,
input rin,
input lin,
input clk,
input clr,
input [3:0] pin,
output [3:0] q
);
reg [3:0] q;
always@(posedge clk or posedge clr)
begin
if (clr ==1'b1)
begin
q<=4'b0000;
end
else if(clr == 1'b0)

27
begin
case(s)
2'b00: q<=q;
2'b01:q<={rin,q[3:1]};
2'b10:q<={q[2:0],lin};
2'b11:q<=pin;// PARALLEL LOADING(8Q)
endcase
end
end
endmodule
Testbench Code:
module tb_a2_q9_tb(
);
reg [1:0] s;
reg rin,lin,clk,clr;
reg [3:0] pin;
wire [3:0] q;
initial
begin
clk = 1'b1;
forever #10 clk = ~clk;
end
initial
begin
#50 clr = 1'b1;
#80 clr = 1'b0;s = 2'b01; rin = 1'b1;
#80 clr = 1'b0;s = 2'b10; lin = 1'b0;
#90 clr = 1'b0;s = 2'b11; pin = 4'b1111;
end
a2_q9 x(s,rin,lin,clk,clr,pin,q);
endmodule

28
Output Waveform:

Conclusion: Therefore in this experiment we observed the simulated waveform of 8-bit universal shift
register.

29
Experiment No. 5:
Design and write Test bench for a 4-bit binary synchronous up/down counter using
behavioural modelling of Verilog HDL.
Aim: To execute and simulate the 4-bit binary synchronous up/down counter using behavioural
modelling.
Objective: The main objective of the experiment is to implement and simulate a 4-bit binary synchronous
up/down counter using behavioural modelling of Verilog HDL.

Module Code:
module a2_q12(
input din,
input [3:0] l,
input clk,
input clr,
output [3:0] q
);
reg [3:0] q;
always @ (posedge clk or posedge clr)
begin
if (clr == 1'b1)
begin
q<=4'b0000;
end
else if((din==1'b0)&&(l!==1111))//upcounter(10Q)
begin
q<=q+1;
end
else if((din==1'b1)&&(l!==0000))//down counter(11Q)
begin

30
q<=q-1;
end
end
endmodule
Testbench Code:
module tb_a2_q12(
);
reg din;
reg [3:0] l;
reg clk,clr;
wire [3:0] q;
initial
begin
clk = 1'b1;
forever #10 clk = ~clk;
end
initial
begin
clr = 1'b1;din = 1'b0; l=4'b0000;
#200 clr = 1'b0;din = 1'b0; l=4'b0000;
#200 clr = 1'b0;din = 1'b1; l = 4'b1111;
end
a2_q12 w(din,l,clk,clr,q);
endmodule
Output Waveform:

31
Experiment No. 6:
Design and write Test bench for a FSM to detect 3 and more consecutive 1’s of an incoming
serial input data input line.
Aim: To design and execute an FSM to detect 3 and more consecutive 1’s of an incoming serial input
data input line.
Objective: The objective of this experiment is to simulate and implement an FSM to detect 3 and more
consecutive 1’s of an incoming serial input data input line here FSM uses mealy and moore model.
Module code:
module a2_q14(

input x,

input clk,

input reset,

input y

);

parameter [1:0] s0 = 2'b00,s1 = 2'b01, s2 = 2'b10,s3=2'b11;

reg[1:0] state_next, state_reg;

always @ (posedge clk or negedge reset)

begin

if(!reset) state_reg = s0;

else state_reg <= state_next;

end

always @(*)

begin

case(state_reg)

s0: if(x==1'b0) state_next =s0;

else if(x ==1'b1) state_next = s1;

s1: if(x==1'b0) state_next =s1;

else if(x ==1'b1) state_next = s2;

s2: if(x==1'b0) state_next =s2;

else if(x ==1'b1) state_next = s3;

s3: if(x==1'b0) state_next =s0;

else if(x ==1'b1) state_next = s3;

endcase

end

32
assign y = (state_reg ==s3);

endmodule

Testbench code:
module tb_a2_q14(
);
reg x,clk,reset;
wire y;
initial
begin
clk = 1'b1;
forever #10 clk = ~clk;
end
initial
begin
reset = 1'b0; x = 1'b0;
#30 reset = 1'b1; x = 1'b0;
#30 reset = 1'b1; x = 1'b1;
#30 reset = 1'b1; x = 1'b0;
#30 reset = 1'b1; x = 1'b1;
#30 reset = 1'b1; x = 1'b1;
#30 reset = 1'b1; x = 1'b1;
#30 reset = 1'b1; x = 1'b1;
#30 reset = 1'b1; x = 1'b0;
#30 reset = 1'b1; x = 1'b0;
#30 reset = 1'b1; x = 1'b0;
end
a2_q14 w(x,clk,reset,y);
endmodule

33
Output Waveform:

Conclusion: therefore in this experiment we have observed consecutive 1’s of an incoming serial input
data input line through an FSM.

34
Experiment No. 7:
Design and write Test bench for a vending machine FSM which will take 5Rs and 10 Rs
coins as inputs and release an item of value 15 Rs. Assume only one coin is inserted at a time
and no change is given back if extra amount is inserted for a given item.
Aim: To design Test bench for a vending machine FSM which will take 5Rs and 10 Rs coins as inputs
and release an item of value 15 Rs.
Objective: The main objective of this experiment is to design a vending machine which will take 5Rs and
10 Rs coins as inputs and release an item of value 15 Rs.
Module Code:
module a2_q16(
input [3:0] x,
input reset,
input clk,
input y
);
parameter [1:0] s0 = 4'b0000, s1 = 4'b0101, s2 = 4'b1010, s3 =
4'b1111;
reg[1:0] state_next, state_reg;
always @ (posedge clk or posedge reset)
begin
if(reset) state_reg<=s0;
else state_reg<= state_next;
end
always@(*)
begin
case(state_reg)
s0:if(x ==4'b0101) state_next =s1;
else if (x== 4'b1010) state_next = s2;
s1:if(x ==4'b0101) state_next =s2;
else if (x== 4'b1010) state_next = s3;
s2:if(x ==4'b0101) state_next =s3;
else if (x== 4'b1010) state_next = s3;
s3:if(x ==4'b0101) state_next =s0;

35
else if (x== 4'b1010) state_next = s0;
endcase
end
assign y=(state_reg==s2);
endmodule
Testbench code:
module tb_a2_q16(
);
reg [3:0] x;
reg reset,clk;
wire y;
initial
begin
clk = 1'b1;
forever #5 clk = ~clk;
end
initial
begin
reset = 1'b1;
#40 reset = 1'b0; x = 4'b0101;
#40 reset = 1'b0; x = 4'b0101;
#40 reset = 1'b0; x = 4'b0101;
#40 reset = 1'b0; x = 4'b0101;
#40 reset = 1'b0; x = 4'b1010;
#40 reset = 1'b0; x = 4'b1010;
#40 reset = 1'b0; x = 4'b1010;
end
a2_q16 w(x,reset,clk,y);
endmodule

36
Output Waveform:

Conclusion: Therefore from this experiment we observed the simulated output of vending machine FSM
which will take 5Rs and 10 Rs coins as inputs and release an item of value 15 Rs.

37
Experiment No.8:
Design Verilog HDL module of FSM to Build an electronic combination lock with a reset
button, two number buttons (0 and 1), and an unlock output. The combination should be
01011.
Aim: To implement and execute Verilog HDL module of FSM to Build an electronic combination lock
with a reset button, two number buttons (0 and 1), and an unlock output. The combination should be
01011.
Objective: The main objective of this experiment is to build an electronic combinational lock with a reset
button, two number buttons (0 and 1), and an unlock output. The combination should be 01011 by using
FSM.
Module Code:
module fsm_lock(x,clk,reset,y);

input x,clk,reset;
output y;
parameter [2:0]

s0=3'b000,s1=3'b001,s2=3'b010,s3=3'b011,s4=3'b100,s5=3'b101;
reg [2:0] state_reg,next_state;

always @ (posedge clk)

begin

if(reset)
state_reg<= 3'b000;

else
state_reg<=next_state;
end

always@(*)
begin

case(state_reg)
s0: if(x==1'b0) next_state=s1;

else if(x==1'b1)
next_state=s0;
s1: if(x==1'b0) next_state=s1;

38
else if(x==1'b1)

next_state=s2;
s2: if(x==1'b0) next_state=s3;

else if(x==1'b1)
next_state=s0;

s3: if(x==1'b0) next_state=s1;

else if(x==1'b1)

next_state=s4;
s4: if(x==1'b0) next_state=s3;

else if(x==1'b1)
next_state=s5;
s5: if(x==1'b0) next_state=s1;

else if(x==1'b1)
next_state=s0;

default: next_state=s0;
endcase

end
assign y=(state_reg==s5);

endmodule

Testbench code:
module fsm_lock_tb();

reg x,clk,reset;
wire y;

initial
begin

clk=1'b0;
forever #5 clk=~clk;

end
initial
begin
reset=1'b1; x=1'b1;

39
#10 reset=0; x=1'b0;

#10 x=1'b1;
#10 x=1'b0;

#10 x=1'b1;
#10 x=1'b1;

#10 x=1'b1;

#10 x=1'b0;

#10 x=1'b1;

#10 x=1'b1;

#10 x=1'b0;

#10 x=1'b1;

#10 x=1'b0;

#10 x=1'b1;

#10 x=1'b1;

end

q_18 inst1(x,clk,reset,y);

endmodule

Output Waveform:

40
 Arithmetic Circuits Design:
Experiment No.1:
Design and write Test bench for 4-bit adder, subtractor circuit in Verilog- HDL.
Aim: To design and simulate and test a 4-bit adder, subtractor circuit in Verilog- HDL
Objective: The main objective of this experiment is to simulate and observe the waveform of a a 4-bit
adder, subtractor.
Module code for 4-bit adder:
module adder4 (a, b, cin, sum, cout);
//define inputs and outputs
input [3:0] a, b;
input cin;
output [3:0] sum;
output cout;
//variables are reg in always
reg [3:0] sum;
reg cout;
//perform the sum and carry-out operations
always @ (a or b or cin)
begin
sum = a + b + cin;
cout = (a[3] & b[3]) |
((a[3] | b[3]) & (a[2] & b[2])) |
((a[3] | b[3]) & (a[2] | b[2]) & (a[1] & b[1])) |
((a[3] | b[3]) & (a[2] | b[2]) & (a[1] | b[1])
& (a[0] & b[0])) |
((a[3] | b[3]) & (a[2] | b[2]) & (a[1] | b[1])
& (a[0] | b[0]) & cin);
end
endmodule

Testbench Code:
module adder4_tb;
//inputs are reg for test bench
//outputs are wire for test bench
reg [3:0] a, b;
reg cin;
wire [3:0] sum;
wire cout;
//display variables
initial
$monitor ("a=%b, b=%b, cin=%b, cout=%b, sum=%b",
a, b, cin, cout, sum);
//apply input vectors
initial
begin
#0 a=4'b0000; b=4'b0000; cin=1'b0;

41
#10 a=4'b0001; b=4'b0001; cin=1'b0;
#10 a=4'b0001; b=4'b0011; cin=1'b0;
#10 a=4'b0101; b=4'b0001; cin=1'b0;
#10 a=4'b0111; b=4'b0001; cin=1'b0;
#10 a=4'b0101; b=4'b0101; cin=1'b0;
#10 a=4'b1001; b=4'b0101; cin=1'b1;
#10 a=4'b1000; b=4'b1000; cin=1'b1;
#10 a=4'b1011; b=4'b1110; cin=1'b1;
#10 a=4'b1111; b=4'b1111; cin=1'b1;
#10 $stop;
end
//instantiate the module into the test bench
adder4 inst1_adder4 (a, b, cin, sum, cout);
endmodule

Output Waveform:

Module code for 4-bit subtractor:

module sub_4bit_bip (a, b, cin, rslt, cout);
//define inputs and outputs
input [3:0] a, b;
input cin;
output [3:0] rslt, cout;
//define internal nets
wire net0, net1, net2, net3;
//design the logic for stage 0
not (net0, b[0]);
full_adder_bip inst0 (a[0], net0, cin, rslt[0], cout[0]);
//design the logic for stage 1

42
not (net1, b[1]);
full_adder_bip inst1 (a[1], net1, cout[0], rslt[1], cout[1]);
//design the logic for stage 2
not (net2, b[2]);
full_adder_bip inst2 (a[2], net2, cout[1], rslt[2],
cout[2]);
//design the logic for stage 3
not (net3, b[3]);
full_adder_bip inst3 (a[3], net3, cout[2], rslt[3],
cout[3]);
endmodule
Testbench code:
module sub_4bit_bip_tb;
//inputs are reg for test bench
//outputs are wire for test bench
reg [3:0] a, b;
reg cin;
wire [3:0] rslt, cout;
//display variables
initial
$monitor ("a = %b, b = %b, cin = %b, rslt = %b, cout = %b",a, b, cin, rslt, cout);
//apply input vectors
initial
begin
#0 a = 4'b0110; b = 4'b0010; cin = 1'b1;
#10 a = 4'b1100; b = 4'b0110; cin = 1'b1;
#10 a = 4'b1110; b = 4'b1010; cin = 1'b1;
#10 a = 4'b1110; b = 4'b0011; cin = 1'b1;
#10 a = 4'b1111; b = 4'b0010; cin = 1'b1;
#10 a = 4'b1110; b = 4'b0110; cin = 1'b1;
#10 a = 4'b1110; b = 4'b1111; cin = 1'b1;
#10 a = 4'b1111; b = 4'b0011; cin = 1'b1;

43
#10 a = 4'b0001; b = 4'b0010; cin = 1'b1;
#10 a = 4'b0001; b = 4'b0001; cin = 1'b1;
#10 a = 4'b1000; b = 4'b0111; cin = 1'b1;
#10 a = 4'b1001; b = 4'b0011; cin = 1'b1;
#10 $stop;
end
//instantiate the module into the test bench
sub_4bit_bip inst1 (a, b, cin, rslt, cout);
endmodule
Output Waveform:

Conclusion: Therefore in this experiment we observed the simulated waveforms of both 4-bit adder and
subtractor.

44
Experiment No. 2:
Design and write Test bench for a 4-bit Fixed point Multiplier circuit.
Aim: To implement and design a 4-bit Fixed point Multiplier circuit.
Objective: The main objective of this experiment is to implement a bit Fixed point Multiplier circuit.

Module Code:
module mul_add_shift3 (a, b, prod, start);
//define inputs and outputs
input [3:0] a, b;
input start;
output [7:0] prod;
//variables are declared as reg in always
reg [7:0] prod;
reg [3:0] b_reg;
reg [3:0] count;
always @ (posedge start)
begin
b_reg = b;
prod = 0;
count = 4'b0100;
if ((a!=0) && (b!=0))
while (count)
begin
prod = {(({4{b_reg[0]}} & a) + prod[7:4]),
prod[3:1]};
b_reg = b_reg >> 1;
count = count - 1;
end
end
endmodule

45
Testbench Code:
module mul_add_shift3_tb;
//inputs are reg for test bench
//outputs are wire for test bench
reg [3:0] a, b;
reg start;
wire [7:0] prod;
//display variables
initial
$monitor ("a = %b, b = %b, prod = %b", a, b, prod);
//apply input vectors
initial
begin
#0 start = 1'b0; a = 4'b0110; b = 4'b0110;
#10 start = 1'b1; #10 start = 1'b0;
#10 a = 4'b0010; b = 4'b0110;
#10 start = 1'b1; #10 start = 1'b0;
#10 a = 4'b0111; b = 4'b0101;
#10 start = 1'b1; #10 start = 1'b0;
#10 a = 4'b0111; b = 4'b0111;
#10 start = 1'b1; #10 start = 1'b0;
#10 a = 4'b0101; b = 4'b0101;
#10 start = 1'b1; #10 start = 1'b0;
#10 a = 4'b0111; b = 4'b0011;
#10 start = 1'b1; #10 start = 1'b0;
#10 a = 4'b0100; b = 4'b0110;
#10 start = 1'b1; #10 start = 1'b0;
#10 $stop;
end
//instantiate the module into the test bench
mul_add_shift3 inst1 (a, b, prod, start);
endmodule

46
Output Waveform:

Conclusion: Therefore in this experiment we have seen the wave form and execution of a 4-bit Fixed point
Multiplier circuit.

47
Experiment No.3:

Design and write Test bench for a 8-function arithmetic and logic unit.
Aim: To design and implement and simulate 8-function arithmetic and logic unit.

Objective: The main objective of the experiment is to design and simulate 8-function arithmetic and logic
unit.

Module code:
module alu_8_bh (a, b, opcode, rslt);
//define inputs and output
input [3:0] a, b;
input [2:0] opcode;
output [7:0] rslt;
//the rslt is left-hand side target in always
//and is declared as type reg
reg [7:0] rslt;
//define operation codes
//parameter defines a constant
parameter add_op = 3'b000,
sub_op = 3'b001,
mul_op = 3'b010,
and_op = 3'b011,
or_op = 3'b100,
not_op = 3'b101, //negation
xor_op = 3'b110,
xnor_op = 3'b111;
//perform the operations
always @ (a or b or opcode)
begin
case (opcode)
add_op: rslt = a + b;
sub_op: rslt = a - b;
mul_op: rslt = a * b;
and_op: rslt = a & b; //also ab

48
or_op: rslt = a | b;
not_op: rslt = ~a; //also ~b
xor_op: rslt = a ^ b;
xnor_op: rslt = ~(a ^ b);
endcase
end
endmodule
Testbench code:
module alu_8_bh_tb;
//inputs are reg for test bench
//outputs are wire for test bench
reg [3:0] a, b;
reg [2:0] opcode;
wire [7:0] rslt;
initial //display variables
$monitor ("a = %b, b = %b, opcode = %b, result = %b",
a, b, opcode, rslt);
initial //apply input vectors
begin
//add operation 1 + 2 and 6 + 6
#0 a = 4'b0001; b = 4'b0010; opcode = 3'b000;
#10 a = 4'b0110; b = 4'b0110; opcode = 3'b000;
//subtract operation 12 – 3 and 13 – 10
#10 a = 4'b1100; b = 4'b0011; opcode = 3'b001;
#10 a = 4'b1101; b = 4'b1010; opcode = 3'b001;
//multiply operation 12 x 7 and 15 x 3
#10 a = 4'b1100; b = 4'b0111; opcode = 3'b010;
#10 a = 4'b1111; b = 4'b0011; opcode = 3'b010;
//AND operation
#10 a = 4'b1100; b = 4'b0111; opcode = 3'b011;
#10 a = 4'b1101; b = 4'b1011; opcode = 3'b011;
//OR operation

49
#10 a = 4'b0101; b = 4'b1011; opcode = 3'b100;
#10 a = 4'b1001; b = 4'b1010; opcode = 3'b100;
//NOT operation
#10 a = 4'b1001; opcode = 3'b101;
#10 a = 4'b0011; opcode = 3'b101;
//exclusive-OR operation
#10 a = 4'b0111; b = 4'b1011; opcode = 3'b110;
#10 a = 4'b1010; b = 4'b0101; opcode = 3'b110;
//exclusive-NOR operation
#10 a = 4'b0110; b = 4'b0110; opcode = 3'b111;
#10 a = 4'b0011; b = 4'b1110; opcode = 3'b111;
#20 $stop;
end
//instantiate the module into the test bench
alu_8_bh inst1 (a, b, opcode, rslt);
endmodule

Output Waveform:

50
Experiment No.4:
Design and write Test bench for a floating point adder circuit in Verilog HDL.
Aim: To design and implement the floating point adder circuit.
Objective: To main objective of this experiment is to implement a floating point adder circuit in Verilog
HDL.
Module Code:
module add_flp5 (flp_a, flp_b, sign, exponent, sum);
//define inputs and outputs
input [31:0] flp_a, flp_b;
output [22:0] sum;
output sign;
output [7:0] exponent;
//variables used in always block
//are declared as registers
reg sign_a, sign_b;
reg [7:0] exp_a, exp_b;
reg [7:0] exp_a_bias, exp_b_bias;
reg [22:0] fract_a, fract_b;
reg [7:0] ctr_align;
reg [22:0] sum;
reg sign;
reg [7:0] exponent;
reg cout;
//define operand signs, exponents, and fractions
always @ (flp_a or flp_b)
begin
sign_a = flp_a [31];
sign_b = flp_b [31];
exp_a = flp_a [30:23];
exp_b = flp_b [30:23];
fract_a = flp_a [22:0];
fract_b = flp_b [22:0];

51
//shift implied 1 into high-order fraction bit position
fract_a = fract_a >> 1;
fract_a[22] = 1'b1;
fract_b = fract_b >> 1;
fract_b[22] = 1'b1;
//bias exponents
exp_a_bias = exp_a + 8'b0111_1111;
exp_b_bias = exp_b + 8'b0111_1111;
//align fractions
if (exp_a_bias < exp_b_bias)
ctr_align = exp_b_bias - exp_a_bias;
while (ctr_align)
begin
fract_a = fract_a >> 1;
exp_a_bias = exp_a_bias + 1;
ctr_align = ctr_align - 1;
end
if (exp_b_bias < exp_a_bias)
ctr_align = exp_a_bias - exp_b_bias;
while (ctr_align)
begin
fract_b = fract_b >> 1;
exp_b_bias = exp_b_bias + 1;
ctr_align = ctr_align - 1;
end
//obtain result
{cout, sum} = fract_a + fract_b;
//normalize result
if (cout == 1)
{cout, sum} = {cout, sum} >> 1;
sign = sign_a;
exponent = exp_b_bias;

52
end
endmodule
Testbench Code:
module add_flp5_tb;
reg [31:0] flp_a, flp_b; //inputs are reg for test bench
wire sign; //outputs are wire for test bench
wire [7:0] exponent;
wire [22:0] sum;
//display variables
initial
$monitor ("sign = %b, exp_biased = %b, sum = %b",
sign, exponent, sum);
//apply input vectors
initial
begin
//+12 + +35 = +47
// s ----e---- --------------f-------------
#0 flp_a = 32'b0_0000_0100_1000_0000_0000_0000_0000_000;
flp_b = 32'b0_0000_0110_0001_1000_0000_0000_0000_000;
//+26.5 + +4.375 = +30.875
// s ----e---- --------------f-------------
#10 flp_a = 32'b0_0000_0101_1010_1000_0000_0000_0000_000;
flp_b = 32'b0_0000_0011_0001_1000_0000_0000_0000_000;
//+11 + +34 = +45
// s ----e---- --------------f-------------
#10 flp_a = 32'b0_0000_0100_0110_0000_0000_0000_0000_000;
flp_b = 32'b0_0000_0110_0001_0000_0000_0000_0000_000;
//+23.75 + +87.125 = +110.875
// s ----e---- --------------f-------------
#10 flp_a = 32'b0_0000_0101_0111_1100_0000_0000_0000_000;
flp_b = 32'b0_0000_0111_0101_1100_1000_0000_0000_000;
#10 $stop;

53
end
//instantiate the module into the test bench
add_flp5 inst1 (flp_a, flp_b, sign, exponent, sum);
endmodule

Output Waveform:

54
Experiment No.5:
Design and write Test bench for a floating point multiplier circuit in Verilog HDL.
Aim: To design and implement the floating point multiplier circuit in Verilog HDL.
Module code:
module mul_flp4 (flp_a , flp_b, start, sign, exponent,
exp_unbiased, cout, prod);
//define inputs and outputs
input [13:0] flp_a, flp_b;
input start;
output sign;
output [4:0] exponent, exp_unbiased;
output cout;
output [15:0] prod;
//variables used in an always block are declared as registers
reg sign_a, sign_b;
reg [4:0] exp_a, exp_b;
reg [4:0] exp_a_bias, exp_b_bias;
reg [4:0] exp_sum;
reg [7:0] fract_a, fract_b;
reg [7:0] fract_b_reg;
reg sign;
reg [4:0] exponent, exp_unbiased;
reg cout;
reg [15:0] prod;
reg [3:0] count;
//define sign, exponent, and fraction
always @ (flp_a or flp_b)
begin
sign_a = flp_a[13];
sign_b = flp_b[13];
exp_a = flp_a[12:8];
exp_b = flp_b[12:8];
fract_a = flp_a[7:0];
fract_b = flp_b[7:0];
//bias exponents
exp_a_bias = exp_a + 5'b01111;
exp_b_bias = exp_b + 5'b01111;
//add exponents
exp_sum = exp_a_bias + exp_b_bias;
//remove one bias
exponent = exp_sum - 5'b01111;
exp_unbiased = exponent - 5'b01111;
end
//multiply fractions
always @ (posedge start)
begin
fract_b_reg = fract_b;

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prod = 0;
count = 4'b1000;
if ((fract_a != 0) && (fract_b != 0))
while (count)
begin
{cout, prod[15:8]} = (({8{fract_b_reg[0]}}
& fract_a) + prod[15:8]);
prod = {cout, prod[15:8], prod[7:1]};
fract_b_reg = fract_b_reg >> 1;
count = count - 1;
end
//postnormalize result
while (prod[15] == 0)
begin
prod = prod << 1;
exp_unbiased = exp_unbiased - 1;
end
sign = sign_a ^ sign_b;
end
endmodule

Testbench code:
module mul_flp4_tb;
//inputs are reg for test bench
//outputs are wire for test bench
reg [13:0] flp_a, flp_b;
reg start;
wire sign;
wire [4:0] exponent, exp_unbiased;
wire [4:0] exp_sum;
wire [15:0] prod;
//display variables
initial
$monitor ("sign = %b, exp_unbiased = %b, prod = %b",
sign, exp_unbiased, prod);
//apply input vectors
initial
begin
#0 start = 1'b0;
//+5 x +3 = +15
// s e f
flp_a = 14'b0_00011_1010_0000;
flp_b = 14'b0_00010_1100_0000;
#10 start = 1'b1;
#10 start = 1'b0;
//+7 x -5 = -35
// s e f
#0 flp_a = 14'b0_00011_1110_0000;
flp_b = 14'b1_00011_1010_0000;
#10 start = 1'b1;

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#10 start = 1'b0;
//+25 x +25 = +625
// s e f
#0 flp_a = 14'b0_00101_1100_1000;
flp_b = 14'b0_00101_1100_1000;
#10 start = 1'b1;
#10 start = 1'b0;
//-7 x -15 = +105
// s e f
#0 flp_a = 14'b1_00011_1110_0000;
flp_b = 14'b1_00100_1111_0000;
#10 start = 1'b1;
#10 start = 1'b0;
//-35 x +72 = -2520
// s e f
#0 flp_a = 14'b1_00110_1000_1100;
flp_b = 14'b0_00111_1001_0000;
#10 start = 1'b1;
#10 start = 1'b0;
//+80 x +37 = +2960
// s e f
#0 flp_a = 14'b0_00111_1010_0000;
flp_b = 14'b0_00110_1001_0100;
#10 start = 1'b1;
#10 start = 1'b0;
//+34 x -68 = -2312
// s e f
#0 flp_a = 14'b0_00110_1000_1000;
flp_b = 14'b1_00111_1000_1000;
#10 start = 1'b1;
#10 start = 1'b0;
//+27 x +25 = +675
// s e f
#0 flp_a = 14'b0_00101_1101_1000;
flp_b = 14'b1_00101_1100_1000;
#10 start = 1'b1;
#10 start = 1'b0;
#10 $stop;
end
//instantiate the module into the test bench
mul_flp4 inst1 (flp_a , flp_b, start, sign, exponent,
exp_unbiased, cout, prod);
endmodule

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Output Waveform:

Declaration: I hear by declare that I have practiced and implemented all the experiments
above.

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