VLSI & Microelectronics
SEMESTER – 7th
SREAM- ECE CODE- EC-702
Group A
Module I:
1. The advantage of IC over discrete component-based circuits is
(a) low power
(b) small size
(c) low cost
(d) all of these
2. With the advancement of technology
(a) channel length is reduced
(b) gate oxide thickness is reduced
(c) power supply voltage is reduced
(d) all of these
3. FPGA-based design is more suitable for
(a) prototype development
(b) large scale product development
(c) low power application
(d) high speed application
4. The interconnect delay is
(a) always less than the gate delay
(b) always more than the gate delay
(c) always equal to the gate delay
(d) can be more or less than the gate delay, depending on the technology used
5. According to Moore’s law, the number of components doubles in every
(a) 10 months
(b) 20 months
(c) 22 months
(d) 18 months
6. Delay __________ with the increase in the power supply voltage.
(a) increases
(b) decreases
(c) remains constant
(d) none of these
7. Delay __________ with the increase in the operating temperature.
(a) increases
(b) decreases
(c) remains constant
(d) none of these
8. VLSI design is __________
(a) a sequential process with feedback loops
(b) a parallel process with no feedback loops
(c) both a sequential and parallel process with feedback loops
(d) sequential process with no feedback loops
9. CAD tools __________ the VLSI design.
(a) automate
(b) reduce design cycle time
(c) reduce the chance of errors
(d) all of these
10. Standard cell-based design takes __________ time as FPGA-based design.
(a) more
(b) less
(c) equal
(d) same
11. In constant voltage scaling, the doping density
(a) remains unchanged
(b) increases by a factor s
(c) increases by a factor s2
(d) increases by a factor s3
12. In full scaling, the power dissipation
(a) decreases by a factor s
(b) decreases by a factor s2
(c) remain unchanged
(d) increases by a factor s
13. In constant voltage scaling, the power dissipation
(a) increases by a factor s
(b) remain unchanged
(c) decreases by a factor s2
(d) decreases by a factor s3
14. Si is preferred over Ge because
(a) Si is cheaper
(b) Si band gap is large
(c) Si technology is matured
(d) All of the above
15. Polysilicon is used for gate in MOSFET because
(a) it is semi-metal
(b) it has lattice matching with Si
(c) it is easy to fabricate
(d) none of these
16. The threshold voltage of an enhancement nMOS transistor is
(a) greater than 0 V
(b) less than 0 V
(c) equal to 0 V
(d) none of these
17. Main advantage of depletion load nMOS inverter circuit over enhancement-type
nMOS load is
(a) fabrication process is easier
(b) sharp VTC transitions and better noise margins
(c) less power dissipation
(d) none of these
18. Which one is not second order effect?
(a) body effect
(b) channel length modulation
(c) subthreshold conduction
(d) hot carrier effect
Module II:
1. A MOS inverter can be implemented using
(a) One nMOS transistor and a resistor
(b) Two pMOS transistors
(c) One pMOS transistors and a resistor
(d) Two resistors
2. The threshold voltage (Vth) of a CMOS inverter is defined
(a) When Vin ≠ Vout
(b) When Vin = Vout
(c) When Vin = 0.5Vout
(d) When Vin = 2Vout
3. In order to achieve the same performance as that of the nMOS transistor, a pMOS
transistor requires
(a) More area
(b) Less area
(c) Same area
(d) None of these
4. Dynamic power dissipation of a CMOS inverter depends on the
(a) Power supply voltage
(b) Channel width of the nMOS
(c) Channel width of the pMOS
(d) All of these
5. The VTC curve of a CMOS inverter determines
(a) Noise margin of the gate
(b) Threshold voltage
(c) VOL, VOH, VIL, VIH
(d) All of these
6. Minimum number of transistors required to design a XOR gate is
(a) six
(b) eight
(c) twelve
(d) ten
7. Which of the following has minimum propagation delay?
(a) ECL
(b) TTL
(c) RTL
(d) DTL
8. Which of the following is/are advantages of CMOS?
(a) Wide range of supply voltage
(b) Greater noise margin
(c) Large packing density
(d) All of these
9. Compared to bipolar technology, output drive current in CMOS is
(a) lower
(b) higher
(c) same
(d) dependent upon use
10. Pseudo-nMOS logic provides which of the following advantages?
(a) Static power dissipation is less compared to CMOS logic.
(b) It is much faster compared to other logics.
(c) It requires a smaller number of transistors compared to CMOS logic.
(d) It is more noise immune.
11. __________ can pass a logic 1 perfectly, but cannot pass a logic 0 perfectly.
(a) nMOS transistor
(b) pMOS transistor
(c) CMOS transistor
(d) none of these
12. __________ can pass a logic 0 perfectly, but cannot pass a logic 1 perfectly.
(a) nMOS transistor
(b) pMOS transistor
(c) CMOS transistor
(d) none of these
13. Pull-up network (PUN) connects output node to __________ .
(a) VDD
(b) ground
(c) input
(d) all of these
14. Pull-down network (PDN) connects output node to __________ .
(a) VDD
(b) ground
(c) input
(d) all of these
15. AND terms are realized by __________ connections of nMOS in PDN.
(a) series
(b) parallel
(c) cascade
(d) anti-parallel
16. Switching speed of a MOS device depends on
(a) gate voltage above threshold
(b) carrier mobility
(c) length channel
(d) all of the mentioned
17. The MOS transistor is non conducting when
(a) zero source bias
(b) zero threshold voltage
(c) zero gate bias
(d) zero drain bias
18. In basic inverter circuit, ______ is connected to ground
(a) source
(b) gates
(c) drain
(d) resistance
19. If p-transistor is conducting and has small voltage between source and drain, then
the it is said to work in
(a) linear region
(b) saturation region
(c) non saturation resistive region
(d) cut-off region
20. If βn = βp, then Vin is equal to
(a) Vdd
(b) Vss
(c) 2Vdd
(d) 0.5Vdd
21. In the region where inverter exhibits gain, the two transistors are in _______ region
(a) linear
(b) cut-off
(c) non saturation
(d) saturation
22. In dynamic CMOS logic _____ is used.
(a) two phase clock
(b) three phase clock
(c) one phase clock
(d) four phase clock
23. CMOS domino logic is same as ______ with inverter at the output line
(a) clocked CMOS logic
(b) dynamic CMOS logic
(c) gate logic
(d) switch logic
24. In Pseudo-nMOS logic, n transistor operates in
(a) cut off region
(b) saturation region
(c) resistive region
(d) non saturation region
25. When Pull Down and Pull Up are parallel, they form
(a)OR gate
(b)NOT gate
(c)AND gate
(d)NAND gate
26. In the VTC curve of an inverter, critical voltages are obtained where the shape of
the curve (d Vout/d Vin) is
(a)1
(b)-1
(c)0
(d)none of these.
27.The switching threshold voltage of CMOS inverter is obtained when
(a)Vin= Vout
(b)VT,n= -- VT,p
(c) Vin= 2Vout
(d) none of these.
28. In CMOS static logic design, total number of transistors required for the Boolean
function F = A + (B + CD) is
(a) 10
(b) 8
(c) 5
(d) none of these.
29. For 0·25 µm process what is the value of λ ?
(a) 0·5 µm
(b) 0·125 µm
(c) 0·75 µm
(d) 1 µm.
Module III:
1. The ON-resistance of a MOSFET ____________________ .
(a) linearly increases with Vgs
(b) linearly decreases with Vgs
(c) exponentially increases with Vgs
(d) non-linearly decreases with Vgs
2. Transconductance of a differential amplifier ____________________ .
(a) increases with W/L ratio
(b) decreases with W/L ratio
(c) does not depend upon W/L ratio
(d) none of these
3. CMOS comparator is a ____________________ .
(a) compensated CMOS OPAMP
(b) uncompensated CMOS OPAMP
(c) partially compensated CMOS OPAMP
(d) none of these
4. The equivalent resistance of a switched capacitor is ____________________ .
(a) proportional to clock frequency
(b) inversely proportional to clock frequency
(c) proportional to the square of the clock frequency
(d) inversely proportional to the square of the clock frequency
5. The equivalent resistance of a switched capacitor is ____________________ .
(a) proportional to capacitance
(b) proportional to the square of the capacitance
(c) inversely proportional to the capacitance
(d) inversely proportional to the square of the capacitance
6. An ideal current source is a two-terminal element who’s current
(a) is constant for any voltage across the source
(b) is monotonically decreased with the increase of voltage across the source
(c) is monotonically increased with the increase of voltage across the source
(d) none of these
7. Which one effect does not cause any deviation of a current mirror circuit from the
ideal situation?
(a) channel length modulation
(b) threshold offset between the two transistors
(c) imperfect geometrical matching
(d) DIBL effects
8. The sensitivity of the BJT voltage reference is
(a) smaller than the MOS voltage reference
(b) equal to the MOS voltage reference
(c) greater than the MOS voltage reference
(d) none of these
9. Diffusion current dominates at
(a) strong inversion
(b) weak inversion
(c) strong and weak inversion both
(d) cannot be determined
10. Drift current dominates at
(a) strong inversion
(b) weak inversion
(c) strong and weak inversion both
(d) cannot be determined
Module IV:
1. The smallest feature size (lambda or λ) used to measure an IC is __________ .
(a) half the length of the smallest transistor
(b) two-thirds the length of the smallest transistor
(c) one-fourth the length of the smallest transistor
(d) none of the above
2. For a 0.5 μm process technology __________.
(a) λ = 0.25 μm
(b) λ = 0.5 μm
(c) λ = 1 μm
(d) λ = 0.125 μm
3. Technology that is used to manufacture IC in much greater volume is___________ .
(a) bipolar technology
(b) MOS technology
(c) CMOS technology
(d) BiCMOS technology
4. In IC technology, dry oxidation (using dry oxygen) as compared to wet oxidation
(using steam or water vapour) produces
(a) Superior quality oxide with a higher growth rate
(b)Inferior quality oxide with a higher growth rate
(c) Inferior quality oxide with a lower growth rate
(d)Superior quality oxide with a lower growth rate
5. In CMOS technology, shallow P – well or N – well regions can be formed using
(a) Low pressure chemical vapour deposition
(b)Low energy sputtering
(c) Low temperature dry oxidation
(d)Low energy ion – implantation
6. In MOSFET fabrication, the channel length is defined during the process of
(a) Isolation oxide growth
(b)Channel stop implantation
(c) Poly – silicon gate patterning
(d)Lithography step leading to the contact pads
7. Which one of the following processes is preferred to from the gate dielectric (SiO 2) of
MOSFETs?
(a) Sputtering
(b)Molecular beam epitaxy
(c) Wet oxidation
(d)Dry oxidation
8. Higher level metal layers have ____________ thickness compared to lower level
metal layers.
(a) larger
(b) equal
(c) smaller
(d) all of these
9. Unit of sheet resistance is ____________ .
(a) ohm/square
(b) ohm
(c) ohm m
(d) ohm/m
10. Four probe technique is used to measure ____________ .
(a) resistivity of semiconducting material
(b) mobility of carriers
(c) carrier concentration
(d) all of these
11. In photolithography, higher the radiation wavelength ____________ .
(a) smaller is the minimum feature size
(b) larger is the minimum feature size
(c) feature size is independent of it
(d) none of these
12. In metallurgical grade semiconductor, the impurity level is in the range of
(a) ppm (parts per million)
(b) ppb (parts per billion)
(c) ppt (parts per trillion)
(d) none of these
13. If the value of segregation coefficient is greater than one, it signifies that the
(a) dopant concentration is more in solid than liquid
(b) dopant concentration is less in solid than liquid
(c) dopant concentration is equal in solid and liquid
(d) dopant concentration is zero in solid than liquid
Module V:
1. Critical path delay is the __________ .
(a) longest path delay
(b) smallest path delay
(c) optimum path delay
(d) none of these
2. A timing analyser finds out __________ .
(a) shortest delay in a circuit
(b) longest delay in a circuit
(c) nominal delay in circuit
(d) all of the above
3. Lowest propagation delay through a gate is due to
(a) strong transistor, low temperature, high voltage
(b) weak transistor, high temperature, high voltage
(c) strong transistor, high temperature, high voltage
(d) weak transistor, low temperature, low voltage
4. What is the fix mechanism for slower circuit operation than predicted?
(a) slow clock
(b) raise VDD
(c) either (a) or (b) or both
(d) none of these
5. The critical path in a design refers to
(a) the path having maximum delay
(b) a path with minimum delay
(c) the path having optimum delay
(d) a path with no delay
6. A pin-to-pin delay refers to
(a) delay through the logic cell including net delay
(b) delay through the logic cell excluding net delay
(c) net delay excluding the logic cell delay
(d) net delay including the logic cell delay
7. Slack is defined as the time difference between
(a) the earliest required time and the latest arrival time at any node
(b) the latest required time and the earliest arrival time at any node
(c) the latest required time and the latest arrival time at any node
(d) the earliest required time and the earliest arrival time at any node
Group –B
(Short Answer Type Questions)
Module I:
1)What are the different types of integrated circuits?
2)Draw the Y-chart and explain the VLSI design process.
3)What do you mean by the hierarchical abstraction? Explain the concepts of
regularity, modularity, and locality.
4)Explain how the cost of IC is calculated.
5)What do you mean by MOSFET scaling? What are the different types of scaling
techniques?
6)Derive an expression for saturated drain current considering channel length
modulation.
7)What do you mean by drain-induced barrier lowering (DIBL)?
8)Show that the subthreshold slope is 60 mV/decade for an ideal transistor at room
temperature.
9)A chip fabricated with 180 nm process technology has a power density of 1 μW.
Calculate the same if the chip is fabricated with 90 nm technology node. Assume
constant voltage scaling.
10)What is the sub-threshold slope of an ideal transistor at 100°C?
11)Calculate the saturated drain current of an nMOS considering the velocity
saturation effect. Given W = 1.2 μm, tox = 100Â, εSiO2 = 3.9, VDS,sat = 1.0 V, VD,Sat = 107
cm/s.
Module II:
1)Derive the expression for VIL in a resistive load inverter.
2)What is dynamic power dissipation in CMOS circuits? Does it depend on the power
supply voltage? If so, explain how.
3)Show that for a symmetric inverter, the W/L ratio of pMOS and nMOS transistors is
equal to the ratio of the mobility of electrons and holes.
4)Explain why a pMOS transistor is used in the pull-up network and the nMOS
transistor is used in the pull-down network in CMOS circuits.
5)Define noise margins. Explain how a greater noise margin helps in reducing the
effect of external noise in digital circuits.
6)What is Miller effect in transient characteristics of a CMOS inverter? Explain.
7)Show that for a symmetric inverter the two-noise margin are same and are equal to
VIL. Also show that for an ideal inverter (W/L)P=2.5(W/L)N.
8)Consider a resistive load MOS inverter circuit with Vdd=5V, Kn/=20μA/V2, Vto=0.8V,
RL=200Kohm, W/L=2. Calculate Critical voltages VIL, VOL, VIH, VOH, on the VTC and
find noise margin of the circuit.
9) Design the 4:1 MUX using TG.
10)Design a CMOS half-adder circuit.
11)Draw the circuit of a CMOS full-adder circuit and explain its operation.
12)Design a 3:2 decoder circuit using static CMOS logic.
13)Design a binary-to-grey code converter circuit using static CMOS logic.
14)Write a short note on NORA Logic & Domino Logic
15)Design an XOR Gate using DCVSL technique.
16)Design XOR/XNOR, AND/NAND and OR/NOR using CPT Logic.
18)Design a 4-bit Comparator using TG.
19)Design a CMOS Master Slave D flip- flop and describe its operation.
20)Design of CMOS S-R & J-K Latch (Clocked & without Clock)
21)Propagation delay time (ΓPHL) for CMOS inverter.
22)What is the effect of variation in W/L ratio on the VTC characteristics of CMOS
inverter?
23)Discuss constructional features and performance characteristic of Pseudo-NMOS
logic.
24)Discuss about NMOS transistor as a switch and PMOS transistor as a switch.
25)Describe the cascading problem in Dynamic CMOS logic? How it is solved in
Domino?
26)Implement Z= using NORA logic.
27)Write the Boolean equations for outputs F and G. What function does this circuit
implement?
28)Implement F = + CD (and ) in DCVSL. Assume A, B, C, D, and their
complements are available as inputs. Use the minimum number of transistors.
29)Consider a CMOS inverter circuit with the following parameters:
VDD =3 .3 V
VTo,n = 0.6 V
VTO,P= -0.7 V
kn= 200 µA/V2
kp = 80 µA/V2
Calculate the noise margins of the circuit. Notice that the CMOS inverter being
considered here has kR = 2.5 and VTo,n VTo.p hence, it is not a symmetric inverter
Module III:
1)What are the effects that cause a practical current mirror to behave differently from
an ideal one? Discuss any one of them.
2)Explain how the combination of switches and a capacitor can emulate a resistor.
3)Prove that for a bilinear-switched capacitor realization of the resistor, the equivalent
resistance is T/(4C), where T is the clock period and C is the capacitance of the
circuit.
4)What are the basic advantages and limitations of a switched capacitor?
5)Explain the working of switched capacitor first-order high-pass filter with circuit
diagram.
6)Explain the working of switched capacitor first-order low-pass filter with circuit
diagram.
7)What are current sources and current sinks?
8)Define CMRR of CMOS OPAMP.
9)What is ICMR of CMOS OPAMP?
10)What is Miller effect?
11)What is Miller compensation in CMOS OPAMP circuit?
12)Explain the operation of the MOS voltage reference circuit with circuit diagram.
13)Explain the operation of the MOS current reference circuit with circuit diagram.
14)Draw the CMOS differential amplifier circuit and explain how it works as a
differential amplifier.
15)What are the purposes of an output amplifier and what are its implementation
schemes?
16)Draw the circuit of source follower using CMOS. Explain the operation.
17)What are the basic building blocks of CMOS OPAMP? Draw & Explain them.
18)What is compensation of CMOS OPAMP and why is it used?
19)What do you mean by Series-Parallel switched capacitor circuit? Describe Briefly.
Module IV:
1)Discuss the layout design rules.
2)What do you mean by DRC, LVS, and extraction?
3)Draw a stick diagram of CMOS NAND gate.
4)Draw a stick diagram of CMOS XOR gate.
5)What is the suitable material for the VLSI interconnect? What is the natural source
of Si?
6)Explain the fabrication of SiO2 using the wet oxidation technique. Discuss its
relative merits and demerits over the dry one.
7)Write Fick’s law of diffusion for a 3D isotropic medium. Write down Fick’s equations
for one dimension for diffusion. Explain its significance in integrated circuit
processing.
8)Compare wet etching and dry etching. What do you mean by anisotropic etching?
9)Describe the RCA cleaning steps commonly used for removing various contaminants
of a silicon wafer.
10)What do you mean by isotropic and anisotropic etching in IC technology? Name the
commonly used isotropic and anisotropic etchants for Si.
9)What are the uses of poly-Si? What are differences between the thick film and thin
film technology?
10)List the processes for fabrication of VLSI circuits.
11)What is meant by impurity profile? How is the profile controlled during fabrication?
13. How is metallization done in VLSI fabrication?
14)Write the Short Notes on:
(a) CVD Techniques,
(b) Twin Tub Fabrication Process,
(c) Ion Implantation Process for MOSFET Fabrication.
(d) Wafer Preparation-Cz Method
(e) Oxidation Process
(f) Photolithography
(g) CMOS-n well & p well fabrication process
(h) sputtering
(i) pattern generation
Module V:
1)What is crosstalk delay in VLSI? Discuss the origin of crosstalk delay and how does
it affect the performance of an IC.
2)Find out the interconnect delay using the Elmore delay model for the following
network:
3)What do you mean by set-up time and hold time of a flip-flop? How can these
problems occur in a design?
4)What do you mean by Critical path, Arrival time, Slack, Clock Skew & Jitter?
5)
Group –C
(Long Answer Questions)
Module 1:
1)Classify the different types of ASIC design.
2)Design the following circuit using PAL, PLA and PROM.
Y1=AB+A/C+ABC/, Y2= AB/C, Y3= BC+ABC/
3)What are the short channel effects? Discuss them in detail.
Module II:
1)Explain the working principle of a resistive load inverter circuit. Derive the
expressions for noise margins of a resistive load inverter.
2)Discuss how the scaling of power supply voltage affects the voltage transfer
characteristics of a CMOS inverter. What is the minimum power supply voltage that
can be used to operate a CMOS inverter?
3)Derive the expression for dynamic power dissipation in a CMOS inverter. Explain
how the switching activity affects the dynamic power dissipation.
4)Describe the Logic ‘0’ and Logic ‘1’ transfer through a Pass Transistor.
5)Describe the Read/Write operation of 6T SRAM Cell.
6)Describe the Read/Write operation of 3T DRAM Cell.
Module III:
1)Define a current sink/source. Obtain the expressions for small signal output
resistance of an n-channel MOSFET. Show how the output resistance of a current
sink can be increased. Explain how a current mirror can be used as a current
amplifier.
2)Explain with a circuit diagram the operation of a differential amplifier and draw its
voltage characteristics. What does CMMR mean for a differential amplifier?
3)Draw different configuration of differential amplifier depending on the active load
configuration.
4)Draw the CMOS differential amplifier circuit. Find out the expression for
transconductance gain of the CMOS differential amplifier. Draw the transconductance
characteristics.
5)Draw the two-stage CMOS OPAMP circuit and explain its working principle.
6)What is compensation of CMOS OPAMP and why is it used? Draw the two-stage
CMOS OPAMP circuit with compensation.
7)Describe the Different types of Switched Capacitor Integrator Circuit. Describe the
draw backs of Discrete time integrator and how do you solve this drawback?
Module IV:
1)What do you mean by ‘Lambda Rule’ & ‘Micron Rule’? Draw the Layout & Schematic
diagram of a Static CMOS NAND&NOR gate with identifying the corresponding
components in the two drawing.
2)Describe the different types of lithography process-Photolithography, Electron beam
lithography, X ray beam lithography, Ion beam lithography.
3)What is meant by etching? What are the different types of etching? Discuss the
plasma etching process. Why is etching technique preferred over lift-off technique?
What is antenna effect?
4)What are the purposes of metallization in IC fabrication? What are the desired
properties of the metallization process integrated circuits? What are the materials
used for metallization?
5)Describe different metallization techniques. What is electromigration in VLSI circuits
and how is it solved? Draw a multilevel metallization structure.
6)Describe how a nMOS device is fabricated. Use diagrams to show the steps.
7)Describe the Si oxidation mechanisms. What are the uses of SiO2 in VLSI circuits?
Classify the SiO2 layer formation techniques and discuss them in brief.
8)What are the effects of impurities and damage on the oxidation rate? What do you
mean by thick and thin oxides, and discuss their properties.
Module V:
1)Explain the process, temperature, and voltage dependency of propagation delay.
2)Derive the expression for logical effort. Explain why NAND is preferred over NOR
gate using the concept of logical effort.
3)Explain the timing models. Define critical path. What is meant by timing driven logic
synthesis. What is inverter buffer chain?
4)Derive the expressions for rise and fall time of an inverter circuit.
5)Describe Set-up time and hold time of a flip-flop
