Department of Electrical Engineering

National University of Computer and

Emerging Sciences,
Chiniot-Faisalabad Campus

EL-1005: DIGITAL LOGIC DESIGN

LABORATORY MANUAL
Spring 2023

Name:
Roll No:
Section:

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 Lab Manual of ‘Digital Logic Design’

 Created by: Mr. M. Umair Akram Butt

Mr. Soban Ahmad
Date: January, 2019

 Revised by: Mr. M. Umair Akram Butt

Mr. Soban Ahmad
Mr. M. Arslan

Date: January, 2020

 Last Updated by: Mr. Mujahid Hussain

Mr. Faizan Ahmad

 Last Updated by: Mr. Faisal Hayat

Mr. Mubeen Tariq
Ms. Amna shahbaz
Ms. Ansa Mubarik

Date: January, 2023

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 Lab Manual of ‘Digital Logic Design’

Table of Contents
Sr. No. Description Page No.

1 List of Equipment 4

2 List of Experiments 5
Introduction to Trainer Board and Logic Probe
3 6
Introduction to Integrated Circuit (IC’s)
4 12
Boolean Expression Implementation
5 19
Universal Gates NAND/NOR Implementation
6 22
Half Adder and Subtractor using Logic Gates
7 25
Boolean Expression Simplification with K Map
8 27
Two Bit Magnitude Comparator
9 30
Encoder & Decoder
10 32
Multiplexer and De-multiplexer
11 36
7 segment Display & sequential Circuits
12 40
Universal Shift Register
13 45

14 Counters 48

15 Appendix A: Lab Evaluation Criteria 54

16 Appendix B: Safety around Electricity 55

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 Lab Manual of ‘Digital Logic Design’

List of Equipment
Sr. No. Description

1 Digital Logic Design Trainer Board

2 Bread Board

3 74XX Logic Gate ICs

4 Logic Probe

5 2N2222 Transistors

6 Jumper Wires

7 Wire Cutters

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 Lab Manual of ‘Digital Logic Design’

List of Experiments
Sr. # Title of Experiment
01 Introduction to Trainer Board and Logic Probe
02 Introduction to Integrated Circuit (IC’s)
03 Boolean Expression Implementation
04 Boolean Expression Simplification with K Map
05 Universal Gates NAND/NOR Implementation
06 Half Adder and Subtractor using Logic Gates
07 Two Bit Magnitude Comparator
08 Encoder & Decoder
09 Multiplexer and De-multiplexer
10 7 segment Display & sequential Circuits
11 Universal Shift Register
12 Counters

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EXPERIMENT 1 Date Perform: ________________

Introduction to Trainer Board and Logic Probe

1.1 OBJECTIVE:
 To become familiar with the components of the trainer board used in the digital experiments
 To become familiar with configuration of Bread Board
 To become familiar with the Logic Probe.

1.2 EQUIPMENT:
 Trainer Board
 Bread Board
 Logic Probe
1.3 BACKGROUND:
Trainer Board:

Fig. 1: Trainer Board

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Fig. 1: Trainer Board

1. Power Switches: For On/Off purpose
2. DC power supply: + 5V, -5V (fixed), +15V and - 15V (variable). We will be using +5V in
most of our experiments.
3. Potentiometers (VR2 = 100k ohms)
4. Potentiometers (VR2 = 100k ohms)
5. Frequency variable
6. Waveform Amplitude variable
7. Frequency range
8. Frequency selector
9. Data Switches and Status LEDs: 8 switches with logic indicators have been made
available on the trainer. Depending on the switch position, a logic high or logic low
becomes available on the corresponding output socket from where it can be extended
through jumper wire to any digital circuit input. Status LED lights ON with a logic high
value and lights OFF with logic low value. The output of switch is output from the trainer
and input to the circuit and the output of the circuit is input to the trainer board.
10. Panel voltmeter display
11. LEDs for output. See point 9

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12. Two 7-segment displays with BCD input sockets are provided on the trainer board. When
binary inputs are provided at the input sockets below each display, the decimal equivalent
of the BCD input is displayed. The Lamp Test (! LT) input socket is for checking the
display: when this input is low (0) all the segments of the display will glow indicating that
the display is functioning properly.
13. Adopter
14. Two pulse switches
15. Removable breadboard for patching digital circuits is provided on the trainer board. As
each
16. circuit has to be implemented on the breadboard, so a detail description of the breadboard
structure is given below.
17. Speakers

Breadboard:
In general, the breadboard consists of two terminal strips and two bus strips (often broken in the
center). Each bus strip has two rows of contacts. Each of the two rows of contacts is a node. That
is, each contact along a row on a bus strip is connected together (inside the breadboard). Bus
strips are used primarily for power supply connections, but are also used for any node requiring a
large number of connections. Each terminal strip has 60 rows and 5 columns of contacts on each
side of the center gap. Each row of 5 contacts is a node.
You will build your circuits on the terminal strips by inserting the leads of circuit components
into the contact receptacles and making connections with wire. It is a good practice to wire +5V
and 0V power supply connections to separate bus strips.

Fig. 1.1: Bread Board

The internal connections are as shown below:

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 Lab Manual of ‘Digital Logic Design’

Fig. 1.2: Internal Structure of Bread Board

The points in ABCDE (and FGHIJ) grid are vertically connected as indicated by red circle. So all
5 points on are actually the same point. It makes No difference whether you connect a wire on
any one of these points. The next vertical strip is a different point and so on.
It should be noted that upper and lower grids are horizontally connected indicated below. Each
grid consists of 4 such separate horizontal strips:

Fig 1.3: Bread Board

In Fig 1.3 the shaded lines indicate connected holes.
Introduction of Logic Probe:

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 Lab Manual of ‘Digital Logic Design’

A logic probe can be very handy for troubleshooting and analysis of a digital logic circuit. As
compared to a DC voltmeter or an oscilloscope, it needs to distinguish between the states of LOW
and HIGH, and so it can be very simple and inexpensive. Its features include two LED indicators:
HI (red LED) and LO (green LED).

Fig 3.1: Logic Probe

Specifications:
Model:
GLP-1A Logic Probe (50MHz Frequency Displayable)

Operation:
1. Connect the black alligator clip to ground or common of the circuit under test.
2. Connect the red alligator clip to Vcc (4V DC minimum to 18V DC maximum) of the
circuit under test.
3. Touch the probe tip to the circuit point under test. The probe’s LEDs indicate the
logic level or signals present when the circuit node is probed.
The LED response is noted below:
Input signal LEDs

Logic “1” HI (Red) ON

Logic “0” LOW (Green) ON
Bad Logic Level or Open circuit None
Square Wave < 200kHz HI and LOW blinking at frequency rate
Square Wave > 200kHz HI and LOW blinking at frequency rate

Task 1:

Make connections of logic probe and verify if all the switches are working Properly.
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Task 2:

Connect input switches with LEDs and verify their proper operation.

Task 3:

Connect Logic Probe with Pulse switches and observe their operation.

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EXPERIMENT 2 Date Perform: ________________

Introduction to Integrated Circuit (IC’s)

2.1OBJECTIVE:
 To become familiar with the different types of Integrated Circuits (ICs), their use and pin
number reading.
 Familiarize with different logic families.
 Identify ICs by series number as well as their functional behavior and pin numbers.
 Carry out best wiring practices in digital design.
2.2 EQUIPMENT:
 Trainer Board
 Wires
 Wires Cutter
 IC Clipper
 7400 quad 2-input NAND gate IC
 7402 quad 2-input NOR gate IC
 7404 hex NOT (Inverter) gate IC
 7408 quad 2-input AND gate IC
 7432 quad 2-input OR gate IC
 7486 quad 2-input XOR gate IC
 4077 quad 2-input XNOR gate IC
2.3BACKGROUND:
An integrated circuit (IC) is a group of components which may include resistors, low value
capacitors and transistors printed on a silicon chip. The individual components of the I.C make up
a commonly used circuit. The circuits can range from simple voltage regulators to audio chips for
a head unit to a microprocessor for a computer. The chip is packaged in a plastic holder with pins
spaced on a 0.1" (2.54mm) grid which will fit the holes on breadboards. Very fine wires inside the
package link the chip to the pins.
Pin Numbers:
The pins are numbered anti-clockwise around the IC (chip) starting near the notch or dot. The
diagram shows the numbering for 14-pin ICs, but the principle is the same for all sizes. Sometimes
the chip manufacturer may denote the first pin by a small indented circle above the first pin of the
chip. Remember that you must connect power to the chips to get them to work.

Fig. 1: HEX Inverter

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 Lab Manual of ‘Digital Logic Design’

Datasheets:
Datasheets are available for most ICs giving detailed information about their ratings and functions.

Logic ICs (Chips):

Logic chips process digital signals and there are many devices, including logic gates, flip-flops, shift
registers, counters and display drivers. They can be split into two groups according to their pin
arrangements: the 4000 series and the 74 series which consists of various families such as the 74HC,
74HCT and 74LS. The table below summarizes the important properties of the most popular logic
families:
74 Series 74 Series 74 Series
Property 4000 Series
74HC 74HCT 74LS
High-speed CMOS TTL Low-power
Technology CMOS High-speed CMOS
TTL compatible Schottky
Power Supply
3 to 15V 2 to 6V 5V ±0.5V 5V ±0.25V

Very high 'Float' high to

Very high impedance. Unused inputs
impedance. logic 1 if
must be connected to +Vs or 0V. Unused inputs must unconnected.
Inputs Inputs cannot be reliably driven by be connected to 1mA must be
74LS outputs unless a 'pull-up' +Vs or 0V. drawn out to hold
resistor is used (see below). Compatible with them at logic 0.
74LS (TTL)
outputs.
Can sink and Can sink and Can sink and Can sink up to
source about 5mA source about source about 16mA (enough to
(10mA with 9V 20mA, enough 20mA, enough to light an LED), but
supply), enough to light an LED. light an LED. To source only about
to light an LED. To switch larger switch larger 2mA. To switch
Outputs
To switch larger currents use a currents, us a larger currents use
currents, use a transistor. transistor a transistor.
transistor.

One output can

drive up to 50 One output can
One output can drive up to 50 CMOS,
CMOS, 74HC or drive up to 10
Fan-out 74HCT inputs, but 74HC or 74HCT inputs, but only 10 74LS inputs or 50
only one 74LS inputs.
74HCT inputs.
74LS input.
Maximum
about 1MHz about 25MHz about 25MHz about 35MHz
Frequency
Power A few µW. A few µW. A few µW. A few mW
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consumption
IC Placement on Breadboard
A typical 14 pin IC placement on such a bread board is shown below: The upper and lower
horizontal strips are normally served for power (+5V) and ground (0V) respectively. But it is not
necessary to do so.

Note:
Never place any IC such that its opposite pins are within (connected to) the same Node on the same
grid.

Removing a chip from its holder:

If you need to remove a chip it can be gently ejected out of the holder with a small flat-blade
screwdriver. Carefully lever up each end by inserting the screwdriver blade between the chip
and its holder and gently twisting the screwdriver. Take care to start lifting at both ends before
you attempt to remove the chip, otherwise you will bend and possibly break the pins.
3.4 Lab Task:
Throughout these experiments we will use TTL chips to build circuits. The steps for wiring a
circuit should be completed in the order described below:
 Turn the power off before you build anything!
 Connect the +5V and ground (GND) leads of the power supply to the power and ground
bus strips on your breadboard.

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 Lab Manual of ‘Digital Logic Design’

 Plug the chips you will be using into the breadboard. Point all the chips in the same
direction with pin 1 at the lower-left corner. (Pin 1 is often identified by a dot or a notch
next to it on the chip package)
 Connect +5V and GND pins of each chip to the power and ground bus strips on the
bread board.
 Select a connection on your schematic and place a piece of hook-up wire between
corresponding pins of the chips on your breadboard. It is better to make the short
connections before the longer ones. Mark each connection on your schematic as you go,
so as not to try to make the same connection again at a later stage.
 Get one of your group members to check the connections, before you turn the power on.
 If an error is made and is not spotted before you turn the power on. Turn the power off
immediately before you begin to rewire the circuit.
 At the end of the laboratory session, collect hook-up wires, chips and all equipment and
return them.
Tidy the area that you were working in and leave it in the same condition as it was before you
started.

Gates, Their IC Pin Configuration & Truth Tables:

Gate NOT Gate

Symbol

Input (x) Output (y)

Truth Table 0
1

IC Pin Configuration

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Gate AND Gate

Symbol

X Y Output (Z)
0 0
0 1
Truth Table
1 0
1 1

IC Pin Configuration

Gate NAND Gate

Symbol

X Y Output (Z)
0 0
0 1
Truth Table
1 0
1 1

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 Lab Manual of ‘Digital Logic Design’

IC Pin Configuration

Gate OR Gate

Symbol

X Y Output (Z)
0 0
0 1
Truth Table
1 0
1 1

IC Pin Configuration

Gate NOR Gate

Symbol

X Y Output (Z)
0 0
0 1
Truth Table
1 0
1 1
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 Lab Manual of ‘Digital Logic Design’

IC Pin Configuration

Gate XOR Gate

Symbol

X Y Output (Z)
0 0
0 1
Truth Table
1 0
1 1

IC Pin Configuration

Gate XNOR Gate

Symbol

X Y Output (Z)
0 0
0 1
Truth Table
1 0
1 1

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IC Pin Configuration

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 Lab Manual of ‘Digital Logic Design’

EXPERIMENT 3 Date Perform: ________________

Boolean Expression Implementation

3.1OBJECTIVE:
 To become familiar with the realization of Boolean expression through ICs.
 To derive the Boolean Expression from a diagram.
 Learn to draw the equivalent diagram of a given Boolean Expression
3.2EQUIPMENT:
 Trainer Board
 7404 hex NOT (Inverter) gate IC ,
 7432 quad 2-input OR gate IC
 7408 quad 2-input AND gate IC
 Wires
 Wires Cutter
 IC Clipper
3.3BACKGROUND:
In the last lab you studied the gates implementation through ICs. The gate operations are
represented mathematically as well, as shown in the table below:
Name Symbol Boolean Representation
Y = X or X’
NOT Gate

AND Gate Z = X•Y

Z= X  Y or XY
NAND Gate

OR Gate Z=X+Y

Z=X+Y
NOR Gate

XOR Gate Z=XY

Z=XY
XNOR Gate

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 Lab Manual of ‘Digital Logic Design’

Any digital circuit can be implemented using basic gates and can be represented as a mathematical
equation. For example,
Z = A + B. C’
Will be implemented as follows:

3.4 LAB TASKS:

1) For the given diagram, derive the equivalent Boolean expression, and then draw the truth
table and verify it.

F=
A B C F

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2) For the given function, draw equivalent circuit diagram, draw the truth tables and verify the
output.
F = X + (Y’+ Z) . Z’

Circuit Diagram:

A B C F

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 Lab Manual of ‘Digital Logic Design’

EXPERIMENT 4 Date Perform: ________________

Boolean Expression Simplification with K Map

4.1OBJECTIVES:
 To become familiar with two standard forms of logic functions: SOP and POS.
 To become familiar that how a Boolean function can be minimized with the k-map and
then can be expressed in gates
4.2EQUIPMENT:
 Trainer Board
 74XX quad 2-input gate IC
 Wires
 Wires Cutter
 IC Clipper
4.3INTRODUCTION:
When a Boolean expression is implemented with logic gates, each term requires a gate, and each
variable within the term designates an input to the gate. We define a literal as a single variable
within the term that may or may not be complemented. By reducing the number of terms, the
number of literals, or both in a Boolean expression, it is often possible to obtain a simpler circuit.
Boolean algebra or K-map is applied to reduce an expression for the purpose of obtaining a
simpler circuit. A Boolean function can be written in a variety of ways when expressed
algebraically. There are, however, a few ways of writing algebraic expressions that are considered
to be standard forms. The standard forms facilitate the simplification procedures for Boolean
expressions and frequently result in more desirable logic circuits.
The standard forms contain product terms and sum terms. An example of a product term is XYZ.
This is a logical product consisting of an AND operation among three literals. An example of a
sum term is X+Y+Z. This is a logical sum consisting of OR operation among the literals.
In the sum of min-terms canonical form, every product term includes a literal of every variable of
the function. Product terms of the SOP form which do not include a literal of a variable, say
variable B, should be augmented by,

• AND-ing the product term which misses a literal of B with ( + 𝐵̅ )

• Subsequently applying the distributive property to eliminate the parenthesis.

In the product of max-terms canonical form, every sum term includes a literal of every variable of
the function. Sum terms of the POS form which do not include a literal of a variable, say variable
B, ought to be augmented by,
• OR-ing the sum term with 𝐵. 𝐵̅
• Subsequently applying postulate a+b·c = (a+b) · (a+c) to distribute the product 𝐵. 𝐵̅

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Steps to Implement the Function:

1. Write the truth table for the function given above
2. Fill the k-map cells from the truth table
3. Simplify and minimize the function with k-map.
1. Write the simplified function from k-map.
2. Draw the circuit diagram and construct the circuit on the Trainer Board.
4.4LAB EXERCISE:
Task 1: Simplify following function using K map and implement simplified function
F (X, Y, Z) = ∑ (1,2,4,6,7)
K-Map Simplification:

Simplified Expression:
F=
Circuit Diagram:
Draw the circuit diagram above mentioned function.

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 Lab Manual of ‘Digital Logic Design’

Task 2: Simplify following function using K map and implement simplified function
F (A, B, C, D) = ∑ (2,3,6,9,10,11,14)

K-Map Simplification:

Simplified Expression:
F=
Circuit Diagram:
Draw the circuit diagram above mentioned function.

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 Lab Manual of ‘Digital Logic Design’

EXPERIMENT 5 Date Perform: ________________

Universal Gates NAND/NOR Implementation

5.1OBJECTIVES:
 To become familiar with the universal gates.
 To implement different logics using universal gates.
5.2EQUIPMENT:
 Trainer Board
 Wires & Wires Cutter
 7400 quad 2-input NAND gate IC
 7402 quad 2-input NOR gate IC
5.3INTRODUCTION:
Digital circuits are frequently constructed with NAND or NOR gates rather than with AND and OR
gates. NAND and NOR gates are easier to fabricate with electronic components and are the basic
gates used in all IC digital logic families. Because of the prominence of NAND and NOR gates in
the design of digital circuits, rules and procedures have been developed for the conversion from
Boolean functions given in terms of AND, OR, and NOT into equivalent NAND and NOR logic
diagrams.

5.4LAB TASKS
Task 1: XOR gate implementation using NAND Gate
XOR gate Boolean Function: F=
Step # 1: Draw and implement the given logic function with AND, OR and NOT gates

Step # 2: Replace AND, OR and NOT gates with equivalent NAND gate circuit

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 Lab Manual of ‘Digital Logic Design’

Step # 3: Simplify the circuit to get the final NAND equivalent circuit and implement using NAND
gate.

Task 2: XNOR gate implementation using NOR Gate

XNOR gate Boolean Function: F=
Step # 1: Dram and Implement the given logic function with AND, OR and NOT gates.

Step # 2: Replace AND, OR and NOT gates with equivalent NOR gate circuit.

Step # 3: Simplify the circuit to get the final NOR equivalent circuit and implement using NOR
gate.

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 Lab Manual of ‘Digital Logic Design’

EXPERIMENT 6 Date Perform: ________________

Half Adder and Subtractor using Logic Gates

6.1OBJECTIVES:
 Design of Half Adder
 Design of Half Subtractor
6.2EQUIPMENT:
 Trainer Board
 74XX quad 2-input gate IC
 Wires
 Wires Cutter
 IC Clipper
6.3INTRODUCTION:
In this lab, we will design arithmetic circuits that are combinational circuits. An arithmetic circuit
performs arithmetic operations such as addition, multiplication, subtraction, and division with
binary numbers or with decimal numbers in a binary code. Adder/subtractor is a very important
component of digital system, ALU and Processor (CPU). A combinational circuit that performs the
addition of two bits is called half adder. The circuit of half adder has two outputs, one sum(s) and
other carry (c). For multi bit addition the carry obtained from the addition of two least significant
bits is added to the next higher order pair of significant bits. A combinational circuit that performs
the subtraction of two bits is called half subtractor. One that performs the subtraction of three bits
(two significant bits and a previous borrow) is called full subtractor. The circuits of half subtractor
have two outputs, one subtraction and other borrow.
6.4PROCEDURE
(Half Adder and Half Subtractor):
1. Connect the trainer with the power supply.
2. Install the ICs on the trainer board.
3. Wire according to the diagram.
4. Use the logic switches for input and connect output of Half Adder (Sum and Carry) and
Subtractor (Difference and Bout) to the LEDs of trainer board.
5. Supply the VCC and GND to the pin 14 and 7 respectively.
6. Test all the possible combination of inputs and fill out the table.

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Half Adder Truth Table:

Input Output
A B Sum Carry

Boolean Functions of Output:

Sum =

Carry =

Circuit Diagram:
Draw the circuit diagram for Half adder using Boolean equations of Sum and Carry.

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Half Subtractor Truth Table:

Input Output
A B diff Borrow

Boolean Functions of Output:

Sum =

Carry =

Circuit Diagram:
Draw the circuit diagram and truth table of Half subtractor using Boolean equations of Difference
and Borrow.

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EXPERIMENT 7 Date Perform: ________________

Two Bit Magnitude Comparator

7.1OBJECTIVES:
 To become familiar with the operation of Magnitude Comparator
7.2EQUIPMENT REQUIRED:
 Trainer Board
 74LS85 (4 Bit Magnitude Comparator)
 Basic Gates.
 Wires & Wire Cutter
7.3INTRODUCTION:
The comparison of two numbers is an operation that determines if one number is greater than, equal
to or less than the other number. A magnitude comparator is a combinational circuit that compares
two numbers A and B and determines their relative magnitudes. The outcome of the comparison is
specified by three binary variables that indicate whether A > B, A = B, or A < B.
Pin Configuration of 74LS85:

Fig. 1: Pin Configuration of 74LS85.

7.4LAB TASK:
1. Mount 4-bit magnitude comparator IC on trainer board.
2. Connect Pin 16 to 5V and Pin 8 to ground point
3. Connect toggle switches to the number inputs of IC.
4. Connect the IC output to the LED indicators on the trainer and observe the outputs.

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Comparing Inputs Outputs

A3, B3 A2, B2 A1, B1 A0, B0 A>B A=B A<B
A3>B X X X
A3<B X X X
A3=B A2>B2 X X
A3=B A2<B2 X X
A3=B A2=B2 A1>B1 X
A3=B A2=B2 A1<B1 X
A3=B A2=B2 A1=B1 A0>B0
A3=B A2=B2 A1=B1 A0<B0
A3=B A2=B2 A1=B1 A0=B0

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EXPERIMENT 8 Date Perform: ________________

Decoder and Priority Encoder

8.1OBJECTIVES:
 Practicing the implementation of logic functions using MSI level functional blocks.
 Gaining experience with MSI level functional blocks/components whose outputs are active
low.
 Gaining a close insight into the functioning and properties of encoder/decoder circuits
 Developing skills in the design and testing of combinational logic circuits.
8.2EQUIPMENT:
 Trainer Board
 74LS138 (3-to-8 Decoder)
 74LS148 (8-bit Priority Binary Encoder)
8.3INTRODUCTION:
Decoder
Decoder is a multiple input, multiple output logic circuit that converts coded input into coded
output, where the input and output codes are different. The input code generally has fewer bits than
the output code, and there is one-to-one mapping, each input code word produces a different output
code word. The most used input code is an n-bit binary code, where an n-bit word represents one of
2n different coded values, i.e. n-to-2n decoder or binary decoder.
Encoder
Encoder is a logic circuit that has fewer output bits than the input code. The encoder takes 2 n inputs
bits and generates n-bit output. Only one of the inputs can be 1, and the corresponding binary will
display on the output bits. But when more than one input bits become 1 at the same time then what
should be the output then? So we give priority to inputs and the input with high priority will freeze
the output with its binary value. Such an encoder is called priority encoder.
Pin Configuration of 74LS138 (3-to-8 Decoder):
Proper value at the enable lines (E1 = 0, E2 = 0, E3 = 1) will enable the decoder, all other
combination of enable lines will keep the output lines high. These multiple enable lines are for
building large decoders.

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74 LS 138

Fig 1: 3×8 Decoder IC

Circuit Diagram of 3-to-8 Decoder:

A2 A1 A0

D0

D1

D2

D3

D4

D5

D6

D7

Fig 2: 3×8 Decoder Internal Structure

Outputs are active low. The binary value on A2, A1, A0 will drive the corresponding output (Di) to
0 all other will remain at 1.

INPUTS OUTPUTS
A0 A1 A2 D0 D1 D2 D3 D4 D5 D6 D7
0 0 0
1 0 0

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0 1 0
1 1 0
0 0 1
1 0 1
0 1 1
1 1 1

Pin Configuration of 74LS148 (8-to-3 Priority Encoder):

74LS 148

Fig 3: 8×3 Priority Encoder

Circuit Diagram of 8-to-3 Priority Encoder:

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Fig 4: 8×3 Priority Encoder Internal Structure

Truth Table:
Inputs Outputs

EI I0 I1 I2 I3 I4 I5 I6 I7 GS A2 A1 A0 EO
1 X X X X X X X X
0 1 1 1 1 1 1 1 1
0 X X X X X X X 0
0 X X X X X X 0 1
0 X X X X X 0 1 1
0 X X X X 0 1 1 1
0 X X X 0 1 1 1 1

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0 X X 0 1 1 1 1 1
0 X 0 1 1 1 1 1 1
0 0 1 1 1 1 1 1 1

EXPERIMENT 9 Date Perform: ________________

Multiplexer and De-multiplexer

9.1OBJECTIVES:
 To become familiar with the operation of MUX and De-MUX
 Practicing the implementation of logic functions using MSI level functional blocks
 Gaining a close insight into the functioning and properties of multiplexer (MUX) circuits.
 Practicing the implementation of logic functions using MSI level functional blocks.
9.2EQUIPMENT:
 Trainer Board
 Bread Board
 74LS138 (1-to-8 De-multiplexer)
 74LS151 (8-to-1 Multiplexer)
 Wires
 Wires Cutter
 IC Clipper

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9.3INTRODUCTION:
A multiplexer is a combinational circuit that selects binary information from one of many input lines
and directs the information to a single output line. The selection of a input line is controlled by a set
of input variables, called selection input. Normally, there are 2n input lines and n selection inputs
whose bit combination determines which input is selected.
A de-multiplexer is doing the opposite function of multiplexer. It takes input on a single input line
and the select lines determines one of the 2 n output lines and the input contents is visible on that
output.
Pin Configuration of 74LS151 (8 to 1 Mux):

74LS 151

Fig 1: 8 × 1 Multiplexer IC

Circuit Diagram of 8 × 1 Multiplexer:

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Fig 2: 8×1 Multiplexer Internal Structure

Truth Table:
Inputs Outputs
E S2 S1 S0 Y
1 X X X
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1

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Pin Configuration of 74LS138 (1×8 De multiplexer):

74 LS 138

Fig 3: 1×8 DEMUX

Here any two of these should be hard wired i.e. E2 = 0 and E3 = 1, so the third enable pin (E1) will
act as input A2, A1, A0 are acting as select lines of de-mux.

Circuit Diagram of 1-to-8 DEMUX:

Fig 4: 8×1 DEMUX Internal Structure

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Truth Table:
Inputs Outputs

D S0 S1 S2 O0 O1 O2 O3 O4 O5 O6 O7

0 X X X

1 0 0 0

1 1 0 0

1 0 1 0

1 1 1 0

1 0 0 1

1 1 0 1

1 0 1 1

1 1 1 1

EXPERIMENT 10 Date Perform: ________________

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7 segment Display & sequential Circuits

10.1 OBJECTIVES:
 To become familiar with the operation of 7-segment display.
 Developing skills in the composition and testing of sequential logic circuits.
 Gaining a close insight into the functioning and properties of basic static memory circuits.
10.2 EQUIPMENT:
 Trainer Board
 7448 BCD to 7-segment (common-cathode) decoder
 Common-cathode 7-segment LED Display
 7400 NAND Gate IC
 7474 Dual +ve edge triggered D-Flip Flop
 74112 Dual –ve edge triggered JK-Flip Flop
10.3 INTRODUCTION:
7 segment Display:
The numbers from 0 to 9 can be shown using a 7–segment LED display unit. This unit shows one
decimal digit using 7 LED segments to form the numbers from 0 to 9. These 7-segments are a, b, c,
d, e, f, g.

Figure 1: 7-Segment Display

The pin connections of the common-cathode and common anode 7-segment single digit display are
below.

Figure 2: Common Cathode and Common Anode 7-segments

A 7448 chip can be used to construct the pattern of segments for each state of the counter’s 4 lines or
bits. Thus, the 7448 inputs are the 4 lines from the binary counter or from the input switches of
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Trainer board and its outputs are the 7 lines to the 7-segment LED Display showing the state of the
segments. The 7448 is a BCD decoder so it only works for counter states between 0000 and 1001,
i.e. decimal numbers 0 through 9.
Pin Configuration of 74LS48(BCD to 7-Segment Decoder):

Figure 3: BCD to 7-Segment Decoder

Sequential Circuit:
A sequential circuit consists of a combinational circuit to which storage elements are connected to
form a feedback path. The storage elements are devices capable of storing binary information. The
binary information stored in these elements at any given time defines the state of the sequential
circuit at that time. There are two main types of sequential circuits: Synchronous sequential circuit
and Asynchronous sequential circuit.

Latches and Flip Flops:

Latches and Flip Flops are used to store binary information in sequential circuits. Storage element
can maintain a binary state indefinitely if power is delivered to the circuit. The major differences
among various types of storage elements are in the number of inputs they possess and in the way the
inputs affect the binary state. Storage element that operates with signal levels (rather than signal
transitions) are referred to as latch and those controlled by a clock transition are flip-flops. Latches
are said to be level sensitive devices; flip-flops are edge-sensitive devices. The two types of storage
elements are related because latches are the basic circuits from which all flip-flops are constructed
by latches.
Latches and Flip Flops have different operating modes. For Latches, operating modes are “SET
MODE, RESET MODE, NO CHANGE MODE, FORBIDDEN MODE”. In case of Flip Flops,
operating modes are “SET MODE, RESET MODE, NO CHANGE MODE, COMPLEMENT
MODE”.
“NO CHANGE MODE” sometimes is considered as “MEMORY MODE”.

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Pin Configuration of 74112 (JK-FFP):

Figure 4: Dual JK-Flip Flop IC & Logic Symbol

Pin Configuration of 7474 (D-FFP):

Figure 5: Dual D-Flip Flop IC & Logic Symbol

Task 1:
Connect Common-cathode 7-segment LED Display with 7448 BCD to 7-segment and show different
digits. Also connect BCD display and show Hexadecimal digits.

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Task 2:
Construct a SR latch using NAND Gates and fill the given table.

Table 10.1: SR-Latch Function Table

S R Q Q’ MODE OF OPERATION
0 1
1 1
1 0
0 0

Task 3:
Connect a JK Flip Flop IC and Record observations and given table.
Inputs Outputs
Operating Mode
SD RD CP J K Q Q’
0 1 X X X
1 0 X X X
0 0 X X X

1 1 ↓ 1 1
1 1 ↓ 0 1
1 1 ↓ 1 0
1 1 ↓ 0 0
1 1 1 X X

Task 4:

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Connect D Flip Flop IC and Record observations in following Table.

Inputs Outputs
Operating Mode
SD RD CP D Q Q’
0 1 X X
1 0 X X
0 0 X X
1 1 ↑ 1
1 1 ↑ 0
1 1 1 X

EXPERIMENT 11 Date Perform: ________________

Universal Shift Register

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11.1 OBJECTIVES:
 Getting familiar with the design of sequential circuits on the register transfer level.
 Gaining a close insight into the functioning and properties of the universal shift register.
 Developing skills in the composition and testing of sequential logic circuits.
11.2 EQUIPMENT:
 Trainer Board
 74194 4-bit Universal Shift Register
 Function Generator
11.3 INTRODUCTION:
Registers:
A register is used to store n-bits of information, where n is number of flip-flops. A register consists
of a set of flip-flops, together with gates that perform data processing tasks. The flip-flops hold data,
and the gates determine the new or transformed data to be transferred into the flip-flops. The
registers have two types, one simple register and other register with parallel load. The register with
parallel load is the register in which we can easily store the value of our own choice. This ability of
register is controlled by a control input, if control input is 1 then the data which we want to enter is
stored on the register, and when the value is 0 then the data which was stored in the register remain
stored in the register.
Shift Registers:
Another type of register is known as shift register. The shift register is capable of shifting its stored
bits laterally in one or both direction. The logical configuration of a shift register consists of a chain
of flip-flops in cascade, with the output of one flip-flop connected to the input of the next flip flop.
All flip-flops receive a common clock pulse, which activates the shift from each stage to the next.

Figure 1: Shift Register

Circuit Diagram for 4-bit shift register:

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Figure 2: 4-bit Shift Register Internal Structure

Pin Configuration of 74LS194:

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Figure 3: 4-bit Shift Register IC

The shift register is to be operated according to the following function table.

Mode Selection
Register Operations
S1 S0
0 0 No Change
0 1 Shift Right
1 0 Shift Left
1 1 Parallel Load Data
Table 1: 4-bit Universal Shift Register Mode Selection

Procedure:
 Connect the trainer with the power supply
 For clock, connect function generator with the power supply. Keep frequency knob on
minimum, press the button for function of square wave and keep the frequency range on
minimum, rotate the amplitude knob to max and get the output from it. Connect the red
alligator clip with the CP pin of the IC and ground the black alligator clip.
 Mount the IC 74LS194 on the trainer board
 Supply the VCC and GND to the pin 16 and 8 respectively
 Wire the pins of IC, refer to the pin configuration.
 Drive the D’s, Dsr, Dsl, S0 & S1 inputs with input switches on the trainer board and CP input
from the clock on the trainer board. Connect output Q’s to LEDs.
 Connect the Mater Reset (MR) to input switch. When low will reset the register.
 Apply different combinations on S1, S0 and verify the corresponding function.
 Observe and record the output on the LEDs.

Task:
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Connect 4-bit Shift Register IC and verify the operations of Shift Register.

EXPERIMENT 12 Date Perform: ________________

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Counters
12.1 OBJECTIVES:
 To become familiar with the operation of Dual 4-bit Counter IC 74393.
 To understand the difference between Synchronous and Asynchronous Counters.
 To become familiar with the State Excitation Table.
 To develop skills of constructing Counters with JK Flip Flops.
12.2 EQUIPMENT:
 Trainer Board.
 7 segment BCD Display.
 74XX gate ICs.
 74112 –ve edge triggered JK-Flip Flop.
 Dual 4-bit Counter IC 74393.
12.3 INTRODUCTION:
A register that goes through a prescribed sequence of states upon the application of input pulses is
called a counter. The input pulses may be clock pulses or may originate from some other source, and
they may occur at fixed intervals of time or random intervals. The sequence of states may follow the
binary number sequence or any other sequence of states: A counter that follows the binary number
sequence is called a binary counter.
Counters are available in two categories: ripple counters and synchronous counters. In a ripple
counter, the flip-flop output transition serves as a source for triggering other flip-flops. In other
words, the clock inputs of some or all the flip-flops are triggered not by the common clock pulses,
but rather by the transition that occurs in other flip-flop outputs. In a synchronous counter, the clock
inputs of all of the flip-flops receive the common clock pulse, and the change of state is determined
from the present state of the counter.
Pin Configuration of 74393:

Figure 1: Dual 4-bit Synchronous Counter

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Pin Configuration of 74112 (JK-FFP):

Figure 2: Dual JK-Flip Flop IC & Logic Symbol

Procedure:
 Connect the trainer with the power supply.
 For clock, connect function generator with the power supply. Keep frequency knob on
minimum, press the button for function of square wave and keep the frequency range on
minimum, rotate the amplitude knob to max and get the output from it.
 Connect the red wire with the CP pin of the IC and ground the Black pin.
 Mount the ICs on the trainer board.
 Supply the VCC and GND to the respective pins.
 Wire the pins of IC according to the diagram, refer to the pin configuration of ICs.
 Drive Up/Down with the input switch on the trainer board and CP input from the clock on
the trainer board. Connect output Q’s to LEDs
 Connect reset input to the switch. When high will reset the counter.
 Observe and record the output on the LEDs
Task 1: Construct 3-bit ripple/asynchronous up counter using JK flipflop.
Circuit Diagram

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Draw state diagram

Task 2: Construct 3-bit synchronous up counter using JK flipflop (Attach Handwritten

Solutions of your Design).
1. How many Flip Flops are required?

2. Fill the excitation table of J K Flip Flop

Qn Qn+1 J K

3. Draw excitation table of the circuit.

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4. K-map simplification of circuit

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5. Draw circuit diagram of your design

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Appendix A: Lab Evaluation Criteria

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Labs with Project/Case Study/With Open Ended lab:

1. Labs 50%

2. Project (Design Project) or Case Study 20%

Project:
a. Project Hardware or Software Implementation 15%
b. Project Report/ Viva 5%

3. Final Exam 30%

Total 100%
Copying and plagiarism of lab manuals is a serious academic
misconduct. First instance of copying may entail ZERO in that
experiment. Second instance of copying may be reported to DC. This
may result in awarding FAIL in the lab course.

Appendix B: Safety around Electricity

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In all the Electrical Engineering (EE) labs, with an aim to prevent any unforeseen accidents during
conduct of lab experiments, following preventive measures and safe practices shall be adopted:

 Remember that the voltage of the electricity and the available electrical current in EE labs
has enough power to cause death/injury by electrocution. It is around 50V/10 mA that the
“cannot let go” level is reached. “The key to survival is to decrease our exposure to energized
circuits.”
 If a person touches an energized bare wire or faulty equipment while grounded, electricity
will instantly pass through the body to the ground, causing a harmful, potentially fatal, shock.
 Each circuit must be protected by a fuse or circuit breaker that will blow or “trip” when its
safe carrying capacity is surpassed. If a fuse blows or circuit breaker trips repeatedly while in
normal use (not overloaded), check for shorts and other faults in the line or devices. Do not
resume use until the trouble is fixed.
 It is hazardous to overload electrical circuits by using extension cords and multi-plug outlets.
Use extension cords only when necessary and make sure they are heavy enough for the job.
Avoid creating an “octopus” by inserting several plugs into a multi-plug outlet connected to a
single wall outlet. Extension cords should ONLY be used on a temporary basis in situations
where fixed wiring is not feasible.
 Dimmed lights, reduced output from heaters and poor monitor pictures are all symptoms of
an overloaded circuit. Keep the total load at any one time safely below maximum capacity.
 If wires are exposed, they may cause a shock to a person who comes into contact with them.
Cords should not be hung on nails, run over or wrapped around objects, knotted or twisted.
This may break the wire or insulation. Short circuits are usually caused by bare wires
touching due to breakdown of insulation. Electrical tape or any other kind of tape is not
adequate for insulation!
 Electrical cords should be examined visually before use for external defects such as: Fraying
(worn out) and exposed wiring, loose parts, deformed or missing parts, damage to outer
jacket or insulation, evidence of internal damage such as pinched or crushed outer jacket. If
any defects are found the electric cords should be removed from service immediately.
 Pull the plug not the cord. Pulling the cord could break a wire, causing a short circuit.
 Plug your heavy current consuming or any other large appliances into an outlet that is not
shared with other appliances. Do not tamper with fuses as this is a potential fire hazard. Do
not overload circuits as this may cause the wires to heat and ignite insulation or other
combustibles.
 Keep lab equipment properly cleaned and maintained.
 Ensure lamps are free from contact with flammable material. Always use lights bulbs with
the recommended wattage for your lamp and equipment.
 Be aware of the odor of burning plastic or wire.
 ALWAYS follow the manufacturer recommendations when using or installing new lab
equipment. Wiring installations should always be made by a licensed electrician or other
qualified person. All electrical lab equipment should have the label of a testing laboratory.
 Be aware of missing ground prong and outlet cover, pinched wires, damaged casings on
electrical outlets.
 Inform Lab engineer / Lab assistant of any failure of safety preventive measures and safe
practices as soon you notice it. Be alert and proceed with caution at all times in the
laboratory.
 Conduct yourself in a responsible manner at all times in the EE Labs.

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 Follow all written and verbal instructions carefully. If you do not understand a direction or
part of a procedure, ASK YOUR LAB ENGINEER / LAB ASSISTANT BEFORE
PROCEEDING WITH THE ACTIVITY.
 Never work alone in the laboratory. No student may work in EE Labs without the presence
of the Lab engineer / Lab assistant.
 Perform only those experiments authorized by your teacher. Carefully follow all
instructions, both written and oral. Unauthorized experiments are not allowed.
 Be prepared for your work in the EE Labs. Read all procedures thoroughly before entering
the laboratory. Never fool around in the laboratory. Horseplay, practical jokes, and pranks
are dangerous and prohibited.
 Always work in a well-ventilated area.
 Observe good housekeeping practices. Work areas should be kept clean and tidy at all times.
 Experiments must be personally monitored at all times. Do not wander around the room,
distract other students, startle other students or interfere with the laboratory experiments of
others.
 Dress properly during a laboratory activity. Long hair, dangling jewelry, and loose or baggy
clothing are a hazard in the laboratory. Long hair must be tied back, and dangling jewelry
and baggy clothing must be secured. Shoes must completely cover the foot.
 Know the locations and operating procedures of all safety equipment including fire
extinguisher. Know what to do if there is a fire during a lab period; “Turn off equipment, if
possible and exit EE lab immediately.”

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