VISVESVARAYA TECHNOLOGICAL UNIVERSITY

JNANA SANGAMA, MACHCHE, BELAGAVI - 590014

A dissertation Report on

“THE DESIGN AND IMPLEMENTATION OF VGA

CONTROLLER ON FPGA WITH THE RESOLUTION OF
800X600”

Submitted in the partial fulfillment for the award of the degree of

Master of Technology
In
VLSI DESIGN AND EMBEDDED SYSTEMS

Submitted by

LEELA RANI JANDHYAM

USN: 1NH14LVS61

Under the Guidance of

Ms. NAYANA G H
Assistant Professor, Dept of ECE,
New Horizon College of Engineering.

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

NEW HORIZON COLLEGE OF ENGINEERING, BENGALURU – 560037
2016- 2017
 DECLARATION

I, Leela Rani J student of fourth semester M.Tech, Department of Electronics and

Communication Engineering, New Horizon College of Engineering, Bengaluru declare
that the project entitled “THE DESIGN AND IMPLEMENTATION OF VGA
CONTROLLER ON FPGA WITH THE RESOLUTION OF 800X600” has been
carried out by me and submitted in partial fulfillment of the course requirements for the
award of degree of Master of Technology in VLSI Design and Embedded Systems of
Visvesvaraya Technological University, Belagavi during the academic year 2016-2017.
The work reported in this dissertation has not been submitted to any other university or
institution for the award of any other degree or diploma.

I also declare that, to the best of my knowledge and belief, the work reported herein does
not form part of any other report or dissertation on the basis of which a degree or award
was conferred on an earlier occasion on this by any student.

Place: BENGALURU LEELA RANI J

Date: 1NH14LVS61
 ABSTRACT

Basically, VGA is used for implementing basic characters/Symbols and images that

can be either used in advertisements that deals with real-time applications. So, using VGA as

a standard for this implementation as it is the basic graphics array and compatible with other

graphical arrays. This project describes about the design of VGA (Video Graphic Array)

Controller using combination of three bit input data to control eight different colors to display

text or image on monitor. The three color signals referred to collectively as R (Red), G

(Green) and B (Blue) signal (i.e. RGB). The VGA monitor using resolution of 800X600 to

display Characters/Text/Images in different colors. Here, we used Verilog HDL on Xilinx

ISE software for interfacing the required peripheral to the Xilinx FPGA Spartan Series.

Where, implementing the application of VGA with the help of Verilog HDL on Xilinx

FPGA, that will contain the logic part.

 ACKNOWLEDGEMENT

The satisfaction and exhilaration that accompany the successful completion of any
task would be incomplete without the mention of people who made it possible, whose
consistent guidance and encouragement crowned our efforts with success.

I consider it as my privilege to express the gratitude to all those who guided in the
completion of my internship.

First and foremost, I wish to express my profound gratitude to our respected Principal
Dr. Manjunatha, New Horizon College of Engineering, Bengaluru, for providing us with a
congenial environment to work in.

I would like to express my sincere thanks to Dr. Sanjay Jain, the HOD of Electronics
and Communication, New Horizon College of Engineering, Bengaluru, for his continuous
support and encouragement.

I am greatly indebted to my guide Ms. Nayana G H, Assistant Professor, Department

of Electronics & Communication, New Horizon College of Engineering who took great
interest in my project work. He motivated and guided me throughout the accomplishment of
this goal. I express my profound thanks for his meticulous guidance.

Last but not the least, heartfelt thanks to my parents, and friends for their direct and
indirect support.

Above all, I thank the Lord Almighty for his grace on us to succeed in this endeavour.

LEELA RANI J
 TABLE OF CONTENTS
CHAPTERS PAGE NO’S

1 INTRODUCTION 1
1.1. Introduction 2
1.2. Objective 3
1.3. Problem Formulation 3

2 LITERATURE SURVEY 5
2.1. Literature survey 6

3 PROPOSED WORK 8
3.1. Introduction 9
3.2. Description of the proposed work 10
3.2.1. Horizontal Synchronous Block 11
3.2.2. Vertical Synchronous Block 12
3.2.3. Color Code Generation Block 13
3.2.4. Top Module of VGA Controller 13
3.3. VGA Standard Details 14
3.4. VGA Controller 15
3.5. VGA Color Signal 17
3.6. Flow Charts 18
3.6.1. Horizontal Synchronization 18
3.6.2. Vertical Synchronization 20
3.6.3. Color Code Generation 21
3.7. System Requirements 22
3.7.1. Software Requirements 22
3.7.2. Hardware Requirements 22

4 SOFTWARE REQUIREMENTS 23
4.1. Xilinx ISE Design Suite 13.2 24
4.2. Hardware Description Language(verilog) 26
5 HARDWARE REQUIREMENTS 28
5.1. Xilinx Spartan 3 FPGA 29
5.2. VGA Monitor 30
5.3. VGA Display Port 31

6 PROCEDURE FOR CREATING A NEW PROJECT 32

7 SNAPSHORTS 38
7.1. Horizontal Synchronization 39
7.2. Vertical Synchronization 39
7.3. Color Code Generation 40
7.4. Top Module of VGA Controller 40

8 IMPLEMENTATION OF VGA CONTROLLER ON FPGA

WITH THE RESOLUTION OF 800X600
& FINAL OUTPUT IMAGE 42
8.1. Connections b/w FPGA and VGA 43
8.2. Setup 43
8.3. Final Output Image 44

9 SYNTHESIS REPORT 45
9.1. RTL Schematic of Hsync Block 46
9.2. RTL Schematic of Vsync Block 46
9.3. RTL Schematic of Color Code Generation Block 47
9.4. RTL Schematic of Top Module VGA Controller Block 47
9.5. RTL Schematic of Overall Internal Diagram 48
9.6. Technology Diagram 48
9.7. Device Utilization Summary 49

10 ADVANTAGES AND APPLICATIONS 50

10.1. Advantages 51
10.2. Applications 51
11 CONCLUSION & FUTURE ENHANCEMENTS 52
11.1. Conclusion 53
11.2. Future Enhancements 53

REFERNCES 55

NATIONAL CONFERENCE CERTIFICATE

APPENDEX 58

APPENDEX A 59

Horizontal Synchronous Verilog Code 59

Vertical Synchronous Verilog Code 60

Color generation Verilog Code 61

Top Module of VGA Controller Verilog Code 61

APPENDEX B 62

Synthesis Report 62

LIST OF TABLES
Tale 3.1. VGA Color Combinations 17

Table 5.1. Comparision b/w Different members of the Sparta-3 Family 29

Table 5.2. Types of Spartan-3 FPGA Devices 30

Table 6.1. Pin Configuration 37

LIST OF FIGURES

Figure 3.1. Overall Block Diagram of VGA Controller 9

Figure 3.2. Internal Block Diagram of VGA Controller 10

Figure 3.3. Horizontal Synchronous Block 11

Figure 3.4. Vertical Synchronous Block 12

Figure 3.5. Color Code Generation Block 13

Figure 3.6. Top Module of VGA Controller Block 13

Figure 3.7. Progressive Scan 14

Figure3.8. Sync Signal Waveform 15

Figure 3.9. Horizontal Timing 17

Figure 3.10. Vertical Timing 17

Figure 4.1. ISE Design Flow 24

Figure 4.2. Behavioral, Structural and Physical 26

Figure 5.1. Xilinx Spartan3 Chip 29

Figure 5.3. VGA Monitor 800X600 Resolution 31

Figure 5.4. VGA Display Port 31

Figure 6.1. Specify Project Location and Type 33

Figure 6.2. Device Specifications and Project Properties Window 33

Figure 6.3.Project Summary Window 34

Figure 6.4. Empty View Window 34

Figure 6.5. Typed Program Window 34

Figure 6.6. Adding Source File Window 35

Figure 6.7. Running Isim Simulator Window 35

Figure 6.8. Define Clock Window 36

Figure 6.9. Simulation Waveforms Generated Window 36

The Design and Implementation of VGA Controller on FPGA with the Resolution of 800X600 1

CHAPTER 1
INTRODUCTION

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CHAPTER 1
INTRODUCTION

1.1 INTRODUCTION

As embedded devices grow in their processing capabilities and complex use cases
that they handle which also involves a fair bit of image processing there is an ever-
increasing need to improve the efficiency in displaying complex graphical content in real
time to align hand in hand with the developments on the high-speed image processing
arena. It is undeniable that there is a need to implement associated display interface
controllers and associated timing logic in a low-cost enablement platform using a design
model that helps in emulations / synthesis and validations early on with low turnaround
times and low overall implementation cost.

VGA (Video Graphics Array) is one of the very widely used video display
standards that enables an easy interfacing to a display device like monitor for displaying
graphical images / information. VGA has gained a lot of popularity and acceptance in the
embedded space with and is widely being used as display interface for video conferencing
devices, portable video players, ATM machines etc. The quality and performance
requirements widely vary across a spectrum of these devices. While some systems
demand high performance, some may be resources constrained with basic display
capability demands.

It is important to ensure that the controller implementation should be generic and

flexible enough to scale across the varying spectrum of needs. As the scope of embedded
systems range from industrial automation to hand held personal gaming devices, there is a
need to have a built-in flexibility in the controller design approach to scale the solution to
meet varying needs of the market / embedded industry. Usage of FPGA is one approach
where the low cost and high flexibility constraints of the display controller can be easily
met. In addition, low power consumption on FPGAs will be a great value add on power
constrained Embedded platforms.

This project aims at designing a VGA (Video Graphic Array) Controller using an
FPGA hardware platform keeping in consideration the ever-increasing needs to

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effectively control the image and synchronization signaling as constrained by the VGA
standard. The image data inputs (RGB Signals) and the synchronization signals are
effectively controlled by the FPGA based VGA controller to interface with a standard
monitor that supports 800 x 600 pixel resolution. This platform shall have the capability
to display Characters, Text, Images in different colors. Verilog Hardware description
language with Xilinx ISE software is used for VGA controller design and enabling the
same on a Xilinx Spartan Series FPGA.

1.2 OBJECTIVE

The objective of this work is to Design and Implement a VGA controller on an

FPGA to interface with a standard display of 800x600 resolution for the purpose of
displaying information or images. The primary goal of this work is to construct the VGA
controller on Xilinx Spartan FPGA using Xilinx ISE Design suite 13.2 software Platform
using Verilog HDL coding. And to achieve a proper and efficient timing and
synchronization signaling.

“THE MAIN INTENSION OF THIS PROJECT IS TO GET COLOR PATTERNS

ON THE VGA MONITOR SCREEN”

1.3 PROBLEM FORMULATION

Real time display with minimum delay:

Problems:

As we move towards higher display density (resolutions), timing issues on FPGAs will be
more prominent.

Desired:

Processing time constraints need to be met so that the Display timing constraints and
VGA standard display requirements are not violated.

Solution:

 Hardware logic resources overhead shall be kept minimal. This ensures efficient
Hardware description which eventually leads to efficient HDL code. Unnecessary
and redundant code will be avoided to ensure that the hardware resources are
optimally utilized.

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 “Blanking” period shall be effectively handled. Timing of Blanking periods shall

be finely controlled, during retrace of the signal from right edge of the screen to
left for new line or from bottom right corner to top left corner during new frame
initiation. This improvement in blanking period handling shall be achieved by
closely controlling the timing signals (but still adhering to the permissible limits
set by VGA standards without deviations / any compromises.

Proper display pattern:

Desired:

 Proper / smooth display mode with no flickers

Solution:

 Fine and smooth display can be achieved by precisely tuning the electron beam
modulated frequency. This frequency is determined by the VGA controller which
produces relevance signals. By accurately generating these signals electron beam
can be properly controlled.
 By ensuring proper signal timings for H_Sync, V_Sync and “Blanking” any
undesired effects due to timing violations can be totally avoided. In addition,
display refresh timing constraints shall be properly adhered to.

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CHAPTER 2
LITERATURE SURVEY

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CHAPTER 2
LITERATURE SURVEY
As part of literature survey several research papers and publications are thoroughly
reviewed and analyzed. The key publications that are relevant for current project are
indicated in this section.

In the paper reference #1, the authors Nagarjuna et al. have proposed a solution to
implement VGA controller on FPGA with focus on geometrical shape generation which
can be set into motion. Usage of Finite State machine approach is very well presented.
Usage of File out operations is a good approach that enables pre-verification of the
functionality without a need for additional FIFO storage.

In another paper reference #2, the authors Radi et al. have emphasized the
advantages of using FPGAs for implementing the VGA controller. The adaptability,
power and the low-cost solutions that can be achieved with the usage of FPGAs are
elaborated in detail. The up sides of using the abstract VHDL language are very well
presented. With easy to modify and make relevant corrections, usage of VHDL is a very
attractive proposition as it reduces the turn-around time for any subsequent churn in the
design.

Usage of CPLD was considered in another research activity reference #3, by

Patrikar et al. Logic Analyzer that is based on CPLD is used for display controller and
memory controller combination. Frame buffers for video that are created are stored in the
static memory for relaying the graphical content to the display there by eliminating the
processing unit from having to handle the data.

Multiple research papers point out the flexibility in using FPGA based
approaches. For example, Ying et al. from reference #4, presented an implementation of
display controller on Altera FPGA with a focus on simulating the timing signals. This
paper also emphasized the portability that is achievable by having the timing logic
implemented in abstract hardware description languages. Presented results indicated the
advantages in processing efficiency, optimized resource utilization and very low power
consumption.

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In another paper reference #5, Kannadasan et al. indicated the value that can be
derived through FPGA and VHDL based approaches that enable us to achieve high
resolution displays with very low storage needs / foot print. Concerns with inadequate
bandwidth can be effectively tackled with these approaches. Usage of a software library
for handling text is well presented and demonstrated through real applications.

In another work Reference #6, Nivedita et al. have indicated the advantages of
using VHDL language in implementing a controller on Altera DE2-115 board.
Programming convenience and flexibility stand out as a note-worthy benefits of this
approach.

Based on various research papers and publications it is turning out to be an

intelligent choice to use FPGA hardware platform and use Verilog HDL for implementing
the logic design.

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CHAPTER 3
PROPOSED WORK

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CHAPTER 3
PROPOSED WORK
3.1 INTRODUCTION

The proposed block diagram is represented below. The top model of the VGA
controller block diagram consists of three internal block diagrams. One is horizontal
synchronization block, vertical synchronization block and color code generation block.

Blue_out
Clk50
0 Green_out

VGA Block Red_out

Hsync_out

Vsync_out

Figure 3.1 Overall block diagram of VGA controller

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The video Graphics Array is mostly used for computer screens, with a high quality
resolution video standard. It has a good ability to transmit a accurate detailed image.

Blue_out
Color code Green_out
generation
Block Red_out

Hsync_out
Clk50
0 Hsync Block Line_out
Vsync_out

Blank_out Vsync Block

Blank_out
Blank

Figure 3.2 Internal block diagram of VGA controller

The 50MHz of clock frequency is input signal, it is given to the horizontal

synchronous block, vertical synchronous block and color code generation block. Here
blue_out, green_out, red_out are output signals and two synchronous signals.

3.2 DESCRIPTION OF THE PROPOSED WORK

Consists of three modules
 Horizontal Synchronous Block
 Vertical Synchronous Block
 Color Code Generation Block
 Top module of VGA controller

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3.2.1 HORIZONTAL SYNCHRONOUS BLOCK

Blank_out

Clk50
HSYNC BLOCK Hsync_out

Newline_out

Figure 3.3 Horizontal synchronous block diagram

For generating horizontal synchronization signal, a 11bit counter is used. The

input for the Hsync block is the clock pulsation signal and outputs are blanking signal,
Horizontal Sync signal and newline indication signal.

Horizontal synchronous signal is a signal pulse, which indicates to the display

device that the end of the line is reached and the control needs to trace back to the start of
next line.

This signal helps to adjust the display control to the next the horizontal line in of
the displayed image. From counter values ranging from 0 to 799, RGB signals are
conveyed, following which Hsync signal will sent.

It is a short signal pulse with front and back porches adhering to the timing
requirements of the display. A new line indication is also generated as an output from the
Hsync block and this will be used as an input to the Vsync block.

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3.2.2 VERTICAL SYNCHRONOUS BLOCK

Blank_out

Line_Clk
VSYNC BLOCK

Vsync_out

Figure 3.4 Vertical synchronous block diagram

In the Vertical synchronous signal generation block a 11bit counter is used.

The input of this block is Line_Clk signal and outputs are blanking signal, Vertical
synchronous signal. The line clock signal is the output generated by Hsync block (which
occurs on every retrace back to start of screen for displaying the next line).

Vertical synchronous signal helps to indicate to the display that a frame

completion is reached and the control needs to retrace back to the beginning (top left) of
the display. In the current case, after 600 rows are displayed a Vsync signal is generated.
It is ensured that at the end of every frame a Vsync signal is generated.

Blanking signal too is asserted during the VSync pulse active time. This ensures
that the pixel data is not conveyed / sampled during the sync signal active time periods.
Vsync signal along with Hsync signal helps to properly control the display position to get
the complete picture properly displayed on the display.

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3.2.3 COLOR CODE GENERATION BLOCK

Blank Blue_out

COLOR BLOCK Green_out

Clk Red_out

Figure 3.5 Color code generation block diagram

The combination of the three primary colors, Blue, Green, Red color can generate
different colors. In this work 800x600 screen resolution is chosen and the color of each of
these pixels on the display are decided by the RGB Output signals from this color
module. These signals are present only in the active region. During horizontal and
Vertical synchronization, these Signals are blanked out.

3.2.4 TOP MODULE OF VGA CONTROLLER

The VGA block generates the Hsync signal, Vsync signal and three color signals

Figure 3.6 Top module of VGA controller

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3.3 VGA Standard Details

On a cathode ray monitor display, an image is displayed by an electron beam from
a cathode ray tube hitting a specific spot on the fluorescent screen. The beam starts from
the top left corner and moves to the right edge to display one row worth of information.
Once it reaches the right edge it retraces back to the left edge and moves one row down
and continues to display the second row.
During this retrace no active image information signal is conveyed to the monitor
and the display monitor is busy in retracing back to the beginning of the new line. During
this retrace period the electron beam is blanked out by the cathode ray tube. This
synchronization signaling to the monitor is achieved by a Horizontal Sync signaling pulse
fed into the monitor. This process repeats itself after each line is displayed.
Once all the lines / rows in the display are covered, the electron beam now has to
not only retrace back to the left edge but to the top row as well. During this retrace period
as well the electron beam is blanked out by the cathode ray tube. This synchronization
signaling to the monitor is achieved by a Vertical Sync signaling pulse fed into the
monitor. This process repeats itself after each frame is displayed.

800

600

Figure 3.7 Progressive Scan

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3.4 VGA CONTROLLER

Computer monitors, which need high-definition resolution use Video Graphics
Array (VGA) video standard. VGA standard defines the three RGB signals for carrying
the image information and two synchronization signals Hsync and Vsync signal for
generating the horizontal and vertical synchronization pulses during the end of the line
and end of frame. Apart from this there are few Ground signals for common grounding
between the display monitor and host side VGA controller.
For a monitor of 800x600 resolution, there are 800 columns of pixels on 600 rows.
These individual pixels are turned ON and the color is determined by the RGB signals
which correspond to the three primary colors Red, Green and Blue. A group of such
pixels when controlled appropriately can display an entire image frame. The scanning
process indicated above is repeated at a very high rate by the monitor and that ensures
that the human eye can see a proper image on the screen. The rapid refresh of these pixels
ensures that we perceive a complete image together though individual pixels and
controlled and updated one at a time at a rapid pace.
As the VGA monitor receives the three RGB signals and the two synchronization
signals, the display VGA controller needs to ensure that it properly generates these
signals as per the expectations of the VGA standards of the display monitor. During
active phase the RGB signals are generated by the controller to display the pixel
information and during end of line and end of frames the Horizontal and Vertical
Synchronization signals (HS and VS) are appropriately generated. HS Sync pulses are
more frequent and occur once for every line while the VS Sync signals occur once all the
lines are written and an end of frame is reached.

Figure 3.8 Sync Signal Waveform

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Both the horizontal and vertical sync pulses are of the same format as indicated in
the figure above. They start with a front porch followed by an active pulse followed by a
back porch. These three segments together make up a Hsync or a Vsync signal. While
these signals are active the RGB data lines are ignored by the monitor as this corresponds
to a blanking interval.
For clocking out the pixel data and for conveying the Hsync and Vsync pulses a
clock of 50MHz frequency is used. These clock rates are generally in proportion to the
screen resolution. Higher resolutions may demand higher clock frequencies so that we
can still perceive all the pixel updates as a single image displayed on the screen. Time
period for each pulse on the 50MHz clock corresponds to 20ns. And this time period
determines the pulse widths of front and back porches and the active pulse width of the
Hsync and Vsync signals.

T = 1 = 20ns
50MHZ

While the front porch, back porch and active Sync pulses are conveyed, the actual
pixel information is not conveyed on the RGB signals. These signals must be set to zero.
These periods of active Hsync and Vsync signals is a blank out duration from RGB
signals perspective. Typically the horizontal timing is controlled by a counter clocked
accordingly. Both the pixel location and the timing information and duration of the
synchronization pulses is computed based on these clocked counters.
For vertical timing a similar counter is used. However, this counter needs to count
the number of new lines and once all the rows are scanned, when the end of the frame is
reached, the Vertical Synchronization signaling is initiated. The counter for Vsync thus
increments for every new line switch that happens (which in turn aligns with every Hsync
signal generation).

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Figure 3.9 Horizontal Timing

Figure 3.10 Vertical Timing

3.5 VGA COLOR SIGNAL

VGA displays are based on additive color principles. The three signals that are
generated (Red, Green and Blue) determine the overall color based on which of these
three components are present and to what extent. All colors are derivatives of these three
primary colors added in different proportions. If each of these primary colors are
indicated by a single bit value, then the 8 different color combinations that are possible
are indicated in the table below.

Table 3.1 VGA Color Combinations

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3.6 FLOW CHARTS

3.6.1 HORIZONTAL SYNCHRONIZATION

Start Hsync Module

Initialize count [10:0] = 0

Initialize hsync = 0
Initialize blank = 0
Initialize newline = 0

Read Input signal

clk50

if (clk50 rising No
edge)

Yes

Yes No
if (count < 1040)

Increment count by 1 Reset count to 0

count = count +1 count = 0

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No Yes
if (count == 0)

newline = 0 newline = 1

No Yes
if (count > 800)

Generate the pixel data Blank out pixel data

blank = 0 blank = 1

Check range of
count

0 to 855 856 to 975 976 to 1039

Pixel data + Front Porch Hsync pulse Back porch

hsync = 1 hsync = 0 hsync = 1

Output the relevant signals

newline_out = newline
blank_out = blank
hsync_out = hsync

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3.6.2 VERTICAL SYNCHRONIZATION

Start Vsync Module

Initialize count [10:0] = 0

Initialize vsync = 0
Initialize blank = 0

Read Input signal

line_clk

if (line_clk No
rising edge)

Yes

Yes No
if (count < 666)

Increment count by 1 Reset count to 0

count = count +1 count = 0

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3.6.3 COLOR CODE GENERATION

Start Color Module

Initialize count [8:0] = 0

Read Input signals

blank & clk50

if (clk50 rising No
edge)

Yes

if (blank == 1)

No Yes

Increment count by 1 Reset count to 0

count = count +1 count = 0

RGB out_ signals

red_output = count [8]
green_output = count [7]
blue_output = count [6]

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3.7 SYSTEM REQUIREMENTS

The system designed in our project need basically two things:
 Software requirements
 Hardware requirements

3.7.1 SOFTWARE REQUIREMENTS

 Xilinx ISE design suite 13.2 or Modelsim
 Hardware description language(Verilog)

3.7.2 HARDWARE REQUIREMENTS

 Xilinx Spartan3 FPGA
 VGA display port
 VGA monitor
 Serial port
 Power supply
 Host computer

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CHAPTER 4
SOFTWARE
REQUIREMENTS

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CHAPTER 4
SOFTWARE REQUIREMENTS

4.1 XILINX ISE DESIGN SUITE 13.2

Xilinx ISE design suite package version 13.2 is used for the development of the
hardware design. This package offers plethora of capabilities that are needed for
designing, Synthesis, implementation, Analysis and programming phases of the
development cycle. The different phases in the development phase and the flow of the
development process is detailed below.

Design creation

Synthesize the Design

Improve the
Implementation
Simulate the Design Enter the Constraints Results

Implementation of Design

Analyize the
Implementation Results

Program the device

Figure 4.1 ISE design Flow

The Creation of design
During the creation of design, we can create an ISE design suite project and also
create and add source files to that project.

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Synthesize the design

During the phase of synthesizing the design, the synthesis machine compiles the
design to transform Verilog HDL sources into an architecture-specific design netlist. The
ISE design suite 13.2 assists the use of Xilinx synthesis.

Simulate the design

During simulating the design, we can observe the functionality of the design using
the simulation result given by the simulation tool.

Enter the constraints

Using constraints file we can define placement, timing and additional design
requirements. In this entry field we can able to enter timing constraints, I/O pins and
Layout constraints.

Implementation of the design

After Synthesis the design, we have to do implementation of the design. It
converts the logical design into a physical file. That file can be downloaded to the
selected target device.

Analysis of implementation Results

After Implementation of the design we can check our design performances ie
device resource utilization, timing, power utilization.

Improve the implementation Results

By considering the Analysis Results we do modifications in design sources,
design constraints etc.

Program the device & device configuration

After creating program file, we can configure our device, generate the
configuration file and download the programming files from the computer to a Xilinx
Spartan 3 device.

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4.2 HARDWARE DESCRIPTION LANGUAGE (VERILOG)

Verilog HDL is a hardware description language used to describe both the structural and
behavioral aspects of the hardware platform under design. Designers use this language to
design the hardware at various levels of abstraction. Verilog is mostly used HDL.

LEVELS OF REPRESENTATION & ABSTRACTION

The design aspects of a hardware platform can be looked at in two different
perspectives: Structural and Behavioral. By separating the structural and behavioral views
the design of complex hardware platforms can be easily modularized and managed.

Figure 4.2 Behavioral, Structural and Physical

BEHAVIORAL LEVEL

This aspect of the design abstraction deals with the behavior of the system (like
what the system does, behaves in response to different inputs, state transitions, changes in
outputs etc.). This abstraction does not deal with the components and how they
communicate with each other. Rather it establishes the relationship between inputs and
outputs if the system. This relationship can be deduced to a Boolean expression or it can
be a much more abstract description or an algorithmic relation.

STRUCTURAL LEVEL

While the behavioral aspects talk about the relation between inputs and outputs,
the structural level of abstraction gives a view of the components that make up the
platform. At structural level of abstraction, the system can be viewed as an

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interconnection of logic gates and components to achieve a desired function. This

schematic view of the interconnection between the involved components is usually closer
to the physical realization of a system.

Verilog HDL that is chosen as the description language for the design here as it
allows well for describing the system both from structural and from behavioral aspects. In
addition, it offers capabilities to represent the behavioral aspects both in Data flow style
and in Algorithmic style. Such multiple views enable and equip the developers with a
much greater insight into the physical interconnections as well as the flow of data and
dynamic behavior of the system. With both concurrent and sequential flows that can be
easily handled Verilog HDL offers itself to be a good choice for hardware design.

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CHAPTER 5
HARDWARE
REQUIREMENTS

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CHAPTER 5
HARDWARE REQUIREMENTS
5.1 XILINX SPARTAN3 FPGA
For this project Spartan3 FPGA is chosen as it offers all the relevant capabilities
both from the logic cells and from the performance point of view. Various FPGAs that
are available in Spartan3 family are indicated below. We have chosen XC3S200 for the
purpose of this project.

Figure 5.1 Xilinx Spartan3 chip

Table 5.1 Comparison b/w different members of the Spartan-3 family

With very good reconfigurability the Spartan3 FPGAs turned out to be a very
good option for prototype building. Being standard programmable parts these units offer
good capability to quickly program any synthesized design and be ready with a usable
chip. The turnaround time for any changes is very low and this greatly helps in faster
design freezes and very short sprints from prototype to product.

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Table 5.2 Types of Spartan-3 FPGA Devices

Design and programming flow

For FPGA behavior definition, the designer can provide a design either in the
form of a hardware description language (HDL) or in a schematic design format. For
large structures the description language is preferable as is easy to describe the behavior
in the form of a logical steps that can be easily coded. Schematic design approach on the
other hand empowers the designer with easier visualization.
Subsequent to the design by either schematic or by HDL approach, and EDA tool
can be used to generate a netlist. The place-and-route capabilities of the associated
software aids in achieving the same. Once the FPGA is programmed the validation
process can be taken up to uncover any design issues by meticulously going through
various validation criteria for timing analysis, simulation checks for wave forms and other
related approaches. The associated packages also enable the developer to simulate the
behavior at various phases to get a deep insight into the dynamic behavior of the design in
action.

5.2 VGA MONITOR

Design of the VGA controller needs a very good understanding of VGA display
standard. In addition, it is also very important to have a good understanding of the
Monitor device and its input requirements and constraints. An important attribute of the
display device is the resolution that it supports. In this project a monitor that supports
800X600-pixel resolution is chosen. In addition to this any specific requirements /
constraints on Vsync and Hsync signals timings needs to be considered.

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800

600

Figure 5.3 VGA monitor of 800 x 600 Resolution

5.3 VGA DISPLAY PORT

The following diagram shows the VGA interface connector and its signals. This
DB-15 linker connector connects the host VGA controller to the monitor Display unit.
Prominent signals from this connector are pointed out below.

Figure 5.4 VGA display port

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CHAPTER 6
PROCEDURE
FOR CREATING A NEW
PROJECT

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CHAPTER 6
PROCEDURE FOR CREATING A NEW PROJECT
Step1: Create a folder in any one of the drive. Double click on ISE Design suite
13.2. ISE project Navigator window will open. In this window click file and
select New project. New project wizard window will open. Give project name,
browse location, automatically working Directory field occur and the press
Next.

Figure 6.1 Specify project location and type Window

Step 2: Select Device specifications according to the project requirements. press Next

and Finish.

Figure 6.2 Device specifications and project properties window

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Figure 6.3 Project summary window

Step 3: Press New Text File Ok. Empty file opened, where we have to type the

Program

Figure 6.4 Empty view window

Step 4: We have to type the program in the Empty view file. After typing save the

Program

Figure 6.5 Typed program window

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Step 5: Select the project in the left top corner (project Hierarchy).Right Click on Project

select Add SourceSelect Project file OpenOk. Added Source file that

particular project.

Figure 6.6 Adding Source file window

Step 6: Select main program fileSelect SimulationIn the Isim simulator Press

Behavioral check syntax after doing this Press Simulate Behavioral Model

Figure 6.7 Running Isim Simulator Window

Step7: Isim window opened in that press Restartto give clk Right click on Value

FieldDefine clock window opened. Enter Leading edge value:1, Trailing edge

value:0,Period:100Applyok. Select run for the time specified on the

toolbarRun allZoom out

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Figure 6.8 Define clock Window

Figure 6.9 Simulation Waveforms Generated Window

Step 8: Select ImplementationSelect Main Project fileRight click on main project

file Add Source …. Browse ucf file Ok. Ucf file added to the Main

Project file.

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Table 6.1 Pin configuration

Step9: Go to Synthesize-XST double click on itDouble click on Implement

DesignConnect the FPGA Spartan3 board Double click Generate Program

Folder Press two times on Configure target deviceOk

Step10: Press two times on Boundary Scan double click  On top of ISE IMPACT

Window Right click Add Xilinx device and browse bit fileRight click on

TD1 wire Select Initialize

chainBrowse bit file openBypassRight click on require device ie is 1st

device(XC3S200)Select ProgramOk.

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CHAPTER 7
SNAPSHOTS

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CHAPTER 7

SNAPSHOTS

7.1 HORIZONTAL SYNCHRONIZATION

7.2 VERTICAL SYNCHRONIZATION

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7.3 COLOR CODE GENERATION

7.4 TOP MODULE OF VGA CONTROLLER

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CHAPTER 8
IMPLEMENTATION OF
VGA CONTROLLER ON
FPGA WITH THE
RESOLUTION OF
800X600
&
FINAL OUTPUT IMAGE

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CHAPTER 8
IMPLEMENTATION OF VGA CONTROLLER ON FPGA
WITH THE RESOLUTION OF 800X600

8.1 CONNECTIONS BETWEEN FPGA AND VGA

8.2 SETUP

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8.3 FINAL OUTPUT IMAGE

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CHAPTER 9
SYNTHESIS REPORT

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CHAPTER 9
SYNTHESIS REPORT
9.1 RTL SCHEMATIC OF HSYNC BLOCK

9.2 RTL SCHEMATIC OF VSYNC BLOCK

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9.3 RTL SCHEMATIC OF COLOR CODE GENERATION BLOCK

9.4 RTL SCHEMATIC OF TOPMODULE VGA CONTROLLER

BLOCK

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9.5 RTL SCHEMATIC OF OVER ALL INTERNAL DIAGRAM

9.6 TECHNOLOGY DIAGRAM

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9.7 DEVICE UTILIZATION SUMMARY

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CHAPTER 10
ADVANTAGES
AND
APPLICATIONS

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CHAPTER 10
ADVANTAGES AND APPLICATIONS
10.1 ADVANTAGES
 The VGA controller system accurately generates the patterns with the help of
RGB signals.
 In order to generate the patterns on the VGA monitor there is no need of direct
line of vision.
 The system is easy to setup.
 The system is easy to understand.
 Low cost.

10.2 APPLICATIONS
Usually, this VGA controller system can be used for standard display interface. The VGA
finds applications in the areas such as

 Rapid growth of embedded systems

 Growth of fast-moving image processing

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CHAPTER 11
CONCLUSION
&
FUTURE
ENHANCEMENTS

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CHAPTER 11

CONCLUSION & FUTURE ENHANCEMENTS

11.1 CONCLUSION
The implementation of VGA controller with the resolution of 800x600 on
FPGA using the ISE design suite 13.2 software tool is an efficient work. With Verilog
hardware description language on FPGA, we could construct VGA Controller manually.
Based on the logic flows Verilog Code is written, and the circuits are simulated and
synthesized. With properly controlled timing for both RGB data and for Synchronization
signal generation a smooth display is achieved on the monitor.

11.2 FUTURE ENHANCEMENTS

In addition to generating the stripes on the VGA monitor, future works can
consider extending this for displaying much more complex images / text output with
different resolutions.

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REFERENCES

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REFERENCES
[1] Ila.Nagarjuna, Pillem. Ramesh, “An FSM Based VGA Controller with 640×480
Resolutions”, International Journal of Engineering and Advanced Technology (IJEAT),
Vol. 2, Issue – 4, pp. 881-885, April 2013.

[2] M.Bharathi and A.Yogananth, “Design of VGA monitor control using Altera FPGA
based system” ,International Journal of VLSI and Embedded Systems (IJVES), Vol. 5,
pp. 866-870, March 2014.

[3] Anand k. Pathrikar , Pooja m.bhangale, “Design of VGA Display System Based On
CPLD And SRAM”, in 2013

[4] Fangqin Ying, Xiaoqing Feng,” Design and Implementation of VGA Controller Using
FPGA” in 2012

[5] S. Sivasathya, K. Kannadasan, “Design of VGA Monitor Controller In Fpga Using On

Chip Embedded Array Ram” in 2014

[6] Niveditha Yadav M, Yaseen Basha,” Algorithm to Design VGA Controller on FPGA
Board” in 2016

[7] E. Hwang, “Build a VGA Monitor Controller”, Nov. 2004, [Online].

[8] Guohui Wang, Yong Guan and Yan Zhang, “Designing of VGA Character String
Display Module Based on FPGA”, International Symposium on Intelligent Ubiquitous
Computing and Education, Chengdu, China 2009.

[9] Khan HumaAftab and MonauwerAlam, “Design of VGA Controller using VHDL for
LCD Display using FPGA”, Vol. 4, Issue – 6, pp. 43-49, June 2014.

[10] Altera Corporation, “What is an FPGA?” Oct. 26- 2011, [Online].

Available:http://www.altera.com/products/fpga.html.

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[11] Altera Corporation, “Introduction to Quartus II”, Feb. 2013, [Online]. Available:
http://www.altera.com/education/univ/software/quartus2/ unvquartus-2.html.

[12] Wayne Wolf, “FPGA-Based System Design”, Pearson Education Inc., India, 2004.

[13] SamirPalnitkar, Verilog HDL: A Guide to Digital Design and Synthesis”, Sun
Microsystems, Inc., USA, 2003.

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The Design and Implementation of VGA Controller on FPGA with the Resolution of 800X600

NATIONAL CONFERENCE
CERTIFICATE

The following paper entitled “The Design and Implementation of VGA Controller on
FPGA with the Resolution of 800X600” is presented at the national conference held at
New Horizon College of Engineering.

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APPENDEX

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APPENDEX A
HORIZONTAL SYNCHRONOUS VERILOG CODE

module hsync(clk50, hsync_out, blank_out, newline_out);

input clk50;
output hsync_out, blank_out, newline_out;

reg [10:0] count = 10'b0000000000;

reg hsync = 0;
reg blank = 0;
reg newline = 0;

always @(posedge clk50)

begin
if (count < 1040)
count <= count + 1;
else
count <= 0;
end

always @(posedge clk50)

begin
if (count == 0)
newline <= 1;
else
newline <= 0;
end

always @(posedge clk50)

begin
if (count >= 800)
blank <= 1;
else
blank <= 0;
end

always @(posedge clk50)

begin

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if (count < 856) // pixel data plus front porch

hsync <= 1;
else if (count >= 856 && count < 976)
hsync <= 0;
else if (count >= 976)
hsync <= 1;
end // always @ (posedge clk50)

assign hsync_out = hsync;

assign blank_out = blank;
assign newline_out = newline;

endmodule

VERTICAL SYNCHRONOUS VERILOG CODE

module vsync(line_clk, vsync_out, blank_out);

input line_clk;
output vsync_out;
output blank_out;

reg [10:0] count = 10'b0000000000;

reg vsync = 0;
reg blank = 0;

always @(posedge line_clk)

if (count < 666)
count <= count + 1;
else
count <= 0;

always @(posedge line_clk)

if (count < 600)
blank <= 0;
else
blank <= 1;

always @(posedge line_clk)

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begin
if (count < 637)
vsync <= 1;
else if (count >= 637 && count < 643)
vsync <= 0;
else if (count >= 643)
vsync <= 1;
end

assign vsync_out = vsync;

assign blank_out = blank;

endmodule // vsync

COLOR GENERATION VERILOG CODE

module color(clk, blank, red_out, green_out, blue_out);

input clk, blank;
output red_out, green_out, blue_out;

reg [8:0] count;

always @(posedge clk)

begin
if (blank)
count <= 0;
else
count <= count + 1;
end

assign red_out = count[8];

assign green_out = count[7];
assign blue_out = count[6];

endmodule // color

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13.4 TOP MODULE OF VGA CONTROLLER VERILOG CODE

module top(clk50, hsync_out, vsync_out, red_out, blue_out, green_out);
input clk50;
output hsync_out, vsync_out, red_out, blue_out, green_out;
wire line_clk, blank, hblank, vblank;

hsync hs(clk50, hsync_out, hblank, line_clk);

vsync vs(line_clk, vsync_out, vblank);
color cg(clk50, blank, red_out, green_out, blue_out);

assign blank = hblank || vblank;

endmodule // top

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APPENDIX B
SYNTHESIS REPORT:

==============================================

* Final Report *

==============================================

Final Results

RTL Top Level Output File Name : top.ngr

Top Level Output File Name : top

Output Format : NGC

Optimization Goal : Speed

Keep Hierarchy : NO

Design Statistics

# IOs :6

Cell Usage :

# BELS : 137

# GND :1

# INV :8

# LUT1 : 33

# LUT2 :4

# LUT3 :3

# LUT3_L :1

# LUT4 : 10

# LUT4_L :5
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# MUXCY : 42

# MUXF5 :1

# VCC :1

# XORCY : 28

# FlipFlops/Latches : 36

# FDR : 34

# FDS :2

# Clock Buffers :1

# BUFGP :1

# IO Buffers :5

# OBUF :5

============================================

Device utilization summary:

-----------------------------------------------------------------------

Selected Device : 3s200tq144-4

Number of Slices: 39 out of 1920 2%

Number of Slice Flip Flops: 36 out of 3840 0%

Number of 4 input LUTs: 64 out of 3840 1%

Number of IOs: 6

Number of bonded IOBs: 6 out of 97 6%

Number of GCLKs: 1 out of 8 12%

------------------------------------------------------------------------

Partition Resource Summary:

--------------------------------------------------------------------------

No Partitions were found in this design.

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--------------------------------------------------------------------------

TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE

REPORT GENERATED AFTER PLACE-and-ROUTE.

Clock Information:

-------------------------------------------------------------------------

-----------------------------------+------------------------+-------+

Clock Signal | Clock buffer(FF name) | Load |

-----------------------------------+------------------------+-------+

clk50 | BUFGP | 23 |

hs/newline | NONE(vs/count_2) | 13 |

-----------------------------------+------------------------+-------+

INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered
by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to
insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:

-------------------------------------------------------------------------------

No asynchronous control signals found in this design

Timing Summary:

--------------------------------------------------------------------------------

Speed Grade: -4

Minimum period: 7.158ns (Maximum Frequency: 139.704MHz)

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Minimum input arrival time before clock: No path found

Maximum output required time after clock: 7.241ns

Maximum combinational path delay: No path found

Timing Detail:

-------------------------------------------------------------------------------------

All values displayed in nanoseconds (ns)

==================================================

Timing constraint: Default period analysis for Clock 'clk50'

Clock period: 5.861ns (frequency: 170.619MHz)

Total number of paths / destination ports: 223 / 43

-------------------------------------------------------------------------------------

Delay: 5.861ns (Levels of Logic = 2)

Source: hs/count_1 (FF)

Destination: hs/newline (FF)

Source Clock: clk50 rising

Destination Clock: clk50 rising

Data Path: hs/count_1 to hs/newline

Gate Net

Cell:in->out fanout Delay Delay Logical Name (Net Name)

-------------------------------------------------------------------------------------

FDR:C->Q 2 0.720 1.216 hs/count_1 (hs/count_1)

LUT3:I0->O 1 0.551 0.996 hs/newline_not00017

(hs/newline_not0001_map4)

LUT3:I1->O 1 0.551 0.801 hs/newline_not000120 (hs/newline_not0001)

FDR:R 1.026 hs/newline

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---------------------------------------------------------------------------------------

Total 5.861ns (2.848ns logic, 3.013ns route)

(48.6% logic, 51.4% route)

=====================================================

Timing constraint: Default period analysis for Clock 'hs/newline'

Clock period: 7.158ns (frequency: 139.704MHz)

Total number of paths / destination ports: 261 / 24

----------------------------------------------------------------------------------------

Delay: 7.158ns (Levels of Logic = 9)

Source: vs/count_0 (FF)

Destination: vs/vsync (FF)

Source Clock: hs/newline rising

Destination Clock: hs/newline rising

Data Path: vs/count_0 to vs/vsync

Gate Net

Cell:in->out fanout Delay Delay Logical Name (Net Name)

---------------------------------------------------------------------------------------

FDR:C->Q 3 0.720 1.246 vs/count_0 (vs/count_0)

LUT1:I0->O 1 0.551 0.000 vs/Mcompar_vsync_cmp_lt0000_cy<0>_rt

(vs/Mcompar_vsync_cmp_lt0000_cy<0>_rt)

MUXCY:S->O 1 0.500 0.000 vs/Mcompar_vsync_cmp_lt0000_cy<0>

(vs/Mcompar_vsync_cmp_lt0000_cy<0>)

MUXCY:CI->O 1 0.064 0.000 vs/Mcompar_vsync_cmp_lt0000_cy<1>

(vs/Mcompar_vsync_cmp_lt0000_cy<1>)

MUXCY:CI->O 1 0.064 0.000 vs/Mcompar_vsync_cmp_lt0000_cy<2>

(vs/Mcompar_vsync_cmp_lt0000_cy<2>)

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MUXCY:CI->O 1 0.064 0.000 vs/Mcompar_vsync_cmp_lt0000_cy<3>

(vs/Mcompar_vsync_cmp_lt0000_cy<3>)

MUXCY:CI->O 1 0.064 0.000 vs/Mcompar_vsync_cmp_lt0000_cy<4>

(vs/Mcompar_vsync_cmp_lt0000_cy<4>)

MUXCY:CI->O 1 0.064 0.000 vs/Mcompar_vsync_cmp_lt0000_cy<5>

(vs/Mcompar_vsync_cmp_lt0000_cy<5>)

MUXCY:CI->O 1 0.303 1.140 vs/Mcompar_vsync_cmp_lt0000_cy<6>

(vs/Mcompar_vsync_cmp_lt0000_cy<6>)

LUT2:I0->O 1 0.551 0.801 vs/vsync_or00001 (vs/vsync_or0000)

FDS:S 1.026 vs/vsync

---------------------------------------------------------------------------------

Total 7.158ns (3.971ns logic, 3.187ns route)

(55.5% logic, 44.5% route)

==================================================

Timing constraint: Default OFFSET OUT AFTER for Clock 'hs/newline'

Total number of paths / destination ports: 1 / 1

------------------------------------------------------------------------------------

Offset: 7.165ns (Levels of Logic = 1)

Source: vs/vsync (FF)

Destination: vsync_out (PAD)

Source Clock: hs/newline rising

Data Path: vs/vsync to vsync_out

Gate Net

Cell:in->out fanout Delay Delay Logical Name (Net Name)

----------------------------------------------------------------------------------

FDS:C->Q 1 0.720 0.801 vs/vsync (vs/vsync)

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OBUF:I->O 5.644 vsync_out_OBUF (vsync_out)

----------------------------------------------------------------------------------

Total 7.165ns (6.364ns logic, 0.801ns route)

(88.8% logic, 11.2% route)

==================================================

Timing constraint: Default OFFSET OUT AFTER for Clock 'clk50'

Total number of paths / destination ports: 4 / 4

-------------------------------------------------------------------------------------

Offset: 7.241ns (Levels of Logic = 1)

Source: cg/count_6 (FF)

Destination: blue_out (PAD)

Source Clock: clk50 rising

Data Path: cg/count_6 to blue_out

Gate Net

Cell:in->out fanout Delay Delay Logical Name (Net Name)

--------------------------------------------------------------------------

FDR:C->Q 2 0.720 0.877 cg/count_6 (cg/count_6)

OBUF:I->O 5.644 blue_out_OBUF (blue_out)

---------------------------------------------------------------------------

Total 7.241ns (6.364ns logic, 0.877ns route)

(87.9% logic, 12.1% route)

==============================================

CPU : 5.20 / 5.56 s | Elapsed : 5.00 / 6.00 s

Total memory usage is 176656 kilobytes

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Number of errors : 0 ( 0 filtered)

Number of warnings : 0 ( 0 filtered)

Number of infos : 1 ( 0 filtered)

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