Low Power, Five Electrode

Electrocardiogram (ECG) Analog Front End

Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2
FEATURES The ADAS1000 is a full-featured, 5-channel ECG including
Biopotential signals in; digitized signals out respiration and pace detection, while the ADAS1000-1 offers
5 acquisition (ECG) channels and one driven lead only ECG channels with no respiration or pace features. Similarly,
Parallel ICs for up to 10+ electrode measurements the ADAS1000-2 is a subset of the main device and is configured
Master ADAS1000 or ADAS1000-1 used with slave for gang purposes with only the ECG channels enabled (no
ADAS1000-2 respiration, pace, or right leg drive).
AC and dc lead-off detection The ADAS1000/ADAS1000-1/ADAS1000-2 are designed to
Internal pace detection algorithm on 3 leads simplify the task of acquiring and ensuring quality ECG signals.
Support for user’s own pace They provide a low power, small data acquisition system for
Thoracic impedance measurement (internal/external path) biopotential applications. Auxiliary features that aid in better
Selectable reference lead quality ECG signal acquisition include multichannel averaged
Scalable noise vs. power control, power-down modes driven lead, selectable reference drive, fast overload recovery,
Low power operation from flexible respiration circuitry returning magnitude and phase
11 mW (1 lead), 15 mW (3 leads), 21 mW (all electrodes) information, internal pace detection algorithm operating on
Lead or electrode data available three leads, and the option of ac or dc lead-off detection. Several
Supports AAMI EC11:1991/(R)2001/(R)2007, AAMI EC38 digital output options ensure flexibility when monitoring and
R2007, EC13:2002/(R)2007, IEC60601-1 ed. 3.0 b:2005, analyzing signals. Value-added cardiac post processing is
IEC60601-2-25 ed. 2.0 :2011, IEC60601-2-27 ed. 2.0 executed externally on a DSP, microprocessor, or FPGA.
b:2005, IEC60601-2-51 ed. 1.0 b: 2005
Because ECG systems span different applications, the
Fast overload recovery
ADAS1000/ADAS1000-1/ADAS1000-2 feature a power/noise
Low or high speed data output rates
scaling architecture where the noise can be reduced at the
Serial interface SPI-/QSPI™-/DSP-compatible
expense of increasing power consumption. Signal acquisition
56-lead LFCSP package (9 mm × 9 mm)
channels can be shut down to save power. Data rates can be
64-lead LQFP package (10 mm × 10 mm body size)
reduced to save power.
APPLICATIONS To ease manufacturing tests and development as well as offer
ECG: monitor and diagnostic holistic power-up testing, the ADAS1000/ADAS1000-1/
Bedside patient monitoring, portable telemetry, Holter, ADAS1000-2 offer a suite of features, such as dc and ac test
AED, cardiac defibrillators, ambulatory monitors, pace excitation via the calibration DAC and cyclic redundancy check
maker programmer, patient transport, stress testing
(CRC) redundancy testing, in addition to readback of all
GENERAL DESCRIPTION relevant register address space.
The ADAS1000/ADAS1000-1/ADAS1000-2 measure electro The input structure is a differential amplifier input, thereby
cardiac (ECG) signals, thoracic impedance, pacing artifacts, allowing users a variety of configuration options to best suit
and lead-on/lead-off status and output this information in the their application.
form of a data frame supplying either lead/vector or electrode The ADAS1000/ADAS1000-1/ADAS1000-2 are available in two
data at programmable data rates. Its low power and small size package options, a 56-lead LFCSP package and a 64-lead LQFP
make it suitable for portable, battery-powered applications. package. Both packages are specified over a −40°C to +85°C
The high performance also makes it suitable for higher end temperature range.
diagnostic machines.

Rev. C Document Feedback

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ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 Pacing Artifact Detection Function (ADAS1000 Only) ....... 45
Applications ....................................................................................... 1 Biventricular Pacers ................................................................... 48
General Description ......................................................................... 1 Pace Detection Measurements ................................................. 48
Revision History ............................................................................... 3 Evaluating Pace Detection Performance ................................. 48
Functional Block Diagram .............................................................. 4 Pace Width .................................................................................. 48
Specifications..................................................................................... 5 Pace Latency ................................................................................ 48
Noise Performance ..................................................................... 10 Pace Detection via Secondary Serial Interface (ADAS1000
Timing Characteristics .............................................................. 11 and ADAS1000-1 Only) ............................................................ 48

Absolute Maximum Ratings.......................................................... 14 Filtering........................................................................................ 49

Thermal Resistance .................................................................... 14 Voltage Reference ....................................................................... 50

ESD Caution ................................................................................ 14 Gang Mode Operation ............................................................... 50

Pin Configurations and Function Descriptions ......................... 15 Interfacing in Gang Mode ......................................................... 52

Typical Performance Characteristics ........................................... 19 Serial Interfaces............................................................................... 54

Applications Information .............................................................. 26 Standard Serial Interface ........................................................... 54

Overview...................................................................................... 26 SPI Interface Resync .................................................................. 56

ECG Inputs—Electrodes/Leads ................................................ 29 Secondary Serial Interface......................................................... 58

ECG Channel .............................................................................. 30 RESET .......................................................................................... 58

Electrode/Lead Formation and Input Stage Configuration .. 31 PD Function ................................................................................ 58

Defibrillator Protection ............................................................. 35 SPI Output Frame Structure (ECG and Status Data) ................ 59
ESIS Filtering............................................................................... 35 SPI Register Definitions and Memory Map ................................ 60
ECG Path Input Multiplexing ................................................... 35 Control Registers Details ............................................................... 61
Common-Mode Selection and Averaging .............................. 36 Examples of Interfacing to the ADAS1000 ............................. 79
Wilson Central Terminal (WCT) ............................................. 37 Software Flowchart .................................................................... 82
Right Leg Drive/Reference Drive ............................................. 37 Power Supply, Grounding, and Decoupling Strategy ............ 83
Calibration DAC ......................................................................... 38 AVDD .......................................................................................... 83
Gain Calibration ......................................................................... 38 ADCVDD and DVDD Supplies ............................................... 83
Lead-Off Detection .................................................................... 38 Unused Pins/Paths ..................................................................... 83
AC Lead-Off Detection ............................................................... 39 Layout Recommendations ........................................................ 83
Shield Driver ............................................................................... 40 Outline Dimensions ....................................................................... 84
Respiration (ADAS1000 Model Only)..................................... 40 Ordering Guide .......................................................................... 85
Evaluating Respiration Performance ....................................... 43
Extend Switch On Respiration Paths ....................................... 44

Rev. C | Page 2 of 85
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2
REVISION HISTORY
11/2018—Rev. B to Rev. C Deleted Figure 63, Figure 64, and Figure 65; Renumbered
Changes to Table 2 ............................................................................ 5 Sequentially ...................................................................................... 35
Changes to Table 9 ..........................................................................17 Change to Figure 65, Figure 66, and Figure 67 ........................... 35
Changes to Figure 35 ......................................................................22 Changes to Lead-Off Detection Section, Added Figure 68;
Changes to Figure 36 Through Figure 41 ........................................23 Renumbered Sequentially .............................................................. 37
Change to Figure 53 ........................................................................26 Changes to Respiration (ADAS1000 Model Only) Section and
Change to Figure 54 ........................................................................27 Figure 69, Figure 70, and Figure 71; Added Table 13 and
Changes to DC Lead-Off and High Gains Section .....................38 Table 14; Renumbered Sequentially ............................................. 39
Added DC Lead-Off Debounce Timer Section ..........................39 Changes to Pacing Artifact Detection Function (ADAS1000
Changes to AC Lead-Off Detection Section ................................39 Only) Section ................................................................................... 42
Added ACLO and Common-Mode Configuration Section ......40 Changes to Evaluating Pace Detection Performance Section ... 45
Changes to Figure 69 ......................................................................41 Added Pace Width Section ............................................................ 45
Changes to Figure 71, Table 13, and Table 14 ..............................43 Changes to Standard Serial Interface Section ............................. 50
Changes to Pace Amplitude Threshold Section ..........................47 Changes to Data Ready (DRDY) Section..................................... 52
Changes to Synchronizing Devices Section and Figure 76 ........50 Changes to Secondary Serial Interface Section and Table 25.... 54
Changes to Sequencing Devices into Gang Mode Section ........51 Change to Bit 3, Table 28 ................................................................ 57
Added Number of Devices in Gang Mode Section ....................51 Changes to Table 43 ........................................................................ 67
Added SPI Interface Resync Section .............................................56 Change to Table 45 .......................................................................... 68
Changes to CRC Word Section, Clocks Section, and Changes to Table 50 ........................................................................ 70
Figure 80 ...........................................................................................57 Changes to Table 52 ........................................................................ 71
Changes to Table 28 ........................................................................61 Changes to Table 53 ........................................................................ 72
Change to Table 32 ..........................................................................66
Changes to Table 43 ........................................................................72 1/2013—Rev. 0 to Rev. A
Changes to Table 44 ........................................................................73 Changes to Features Section ............................................................ 1
Changes to Table 47 ........................................................................74 Changes to Table 1 ............................................................................ 3
Changes to Table 48 ........................................................................75 Changes to Excitation Current, Test Conditions/Comments,
Changes to Table 52 ........................................................................77 Table 2 ................................................................................................. 5
Changes to Example 6: Writing to Master and Slave Devices and Added Table 3; Renumbered Sequentially ..................................... 9
Streaming Conversion Data Section, and Table 61.....................81 Changes to Respiration (ADAS1000 Model Only) Section,
Changes to Power Supply, Grounding, and Decoupling Strategy Figure 66, and Internal Respiration Capacitors Section ............ 37
Section ...............................................................................................83 Changes to Figure 67 ...................................................................... 38
Changes to Figure 68 ...................................................................... 39
6/2014—Rev. A to Rev. B Added Evaluating Pace Detection Performance Section ........... 43
Moved Revision History ................................................................... 3 Added Table 15 ................................................................................ 47
Change to AC Lead-Off, Frequency Range Parameter, Table 2 .. 7 Changes to Clocks Section ............................................................. 51
Changes to Figure 17 ......................................................................18 Changes to RESPAMP Name, Function, Table 28 ...................... 57
Changes to Figure 40 and Figure 41 .............................................22 Changes to Bits[14:9], Function, Table 30 ................................... 59
Changes to ECG Channel Section ................................................29 Changes to Ordering Guide ........................................................... 78
Replaced Figure 57 ..........................................................................30
Added Figure 58, Figure 59, Figure 60, Figure 61, and Figure 62; 8/2012—Revision 0: Initial Version
Renumbered Sequentially ..............................................................31

Rev. C | Page 3 of 85
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet
FUNCTIONAL BLOCK DIAGRAM
REFIN REFOUT CAL_DAC_IO RLD_SJ RLD_OUT CM_IN CM_OUT/WCT SHIELD AVDD IOVDD

DRIVEN
LEAD
AMP SHIELD
VREF DRIVE ADCVDD
– ADCVDD, DVDD
AMP 1.8V
CALIBRATION REGULATORS DVDD
DAC
+
VCM_REF
(1.3V)
RESPIRATION
DAC
COMMON-
MODE AMP
AC
LEAD-OFF
DAC
AC
LEAD-OFF
10kΩ DETECTION

BUFFER PACE CS
MUXES DETECTION

5× ECG PATH SCLK

ELECTRODES SDI
×5 FILTERS,
AMP ADC CONTROL, SDO
AND
INTERFACE DRDY
LOGIC GPIO0/MCS
GPIO1/MSCLK
GPIO2/MSDO
EXT_RESP_LA GPIO3
EXT_RESP_LL AMP ADC
EXT_RESP_RA
CLOCK GEN/OSC/
RESPIRATION PATH EXTERNAL CLK CLK_IO
ADAS1000 SOURCE

09660-001
XTAL1 XTAL2

Figure 1. ADAS1000 Full Featured Model

Table 1. Overview of Features Available from ADAS1000 Generics

Pace Shield Master Package
Generic 1 ECG Operation Right Leg Drive Respiration Detection Driver Interface 2 Option
ADAS1000 5 ECG channels Master/slave Yes Yes Yes Yes Yes LFCSP, LQFP
ADAS1000-1 5 ECG channels Master/slave Yes Yes Yes LFCSP
ADAS1000-2 5 ECG channels Slave LFCSP, LQFP
ADAS1000-3 3 ECG channels Master/slave Yes Yes Yes LFCSP, LQFP
ADAS1000-4 3 ECG channels Master/slave Yes Yes Yes Yes Yes LFCSP, LQFP

1
The ADAS1000-2 is a companion device for increased channel count purposes. It has a subset of features and is not intended for standalone use. It can be used in
conjunction with any master device.
2
Master interface is provided for users wishing to utilize their own digital pace algorithm; see the Secondary Serial Interface section.

Rev. C | Page 4 of 85
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2

SPECIFICATIONS
AVDD = 3.3 V ± 5%, IOVDD = 1.65 V to 3.6 V, AGND = DGND = 0 V, REFIN tied to REFOUT, externally supplied crystal/clock =
8.192 MHz. Decoupling for reference and supplies as noted in the Power Supply, Grounding, and Decoupling Strategy section. TA =
−40°C to +85°C, unless otherwise noted. Typical specifications are mean values at TA = 25°C.
For specified performance, internal ADCVDD and DVDD linear regulators have been used. They may be supplied from external
regulators. ADCVDD = 1.8 V ± 5%, DVDD = 1.8 V ± 5%.
Front-end gain settings: GAIN 0 = ×1.4, GAIN 1 = ×2.1, GAIN 2 = ×2.8, GAIN 3 = ×4.2.

Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
ECG CHANNEL These specifications apply to the following pins:
ECG1_LA, ECG2_LL, ECG3_RA, ECG4_V1, ECG5_V2,
CM_IN (CE mode), EXT_RESP_xx pins when used in
extend switch mode
Electrode Input Range Independent of supply
0.3 1.3 2.3 V GAIN 0 (gain setting ×1.4)
0.63 1.3 1.97 V GAIN 1 (gain setting ×2.1)
0.8 1.3 1.8 V GAIN 2 (gain setting ×2.8)
0.97 1.3 1.63 V GAIN 3 (gain setting ×4.2)
Input Bias Current −10 ±1 +10 nA Relates to each electrode input; over specified
electrode input range; dc and ac lead-off are disabled,
applies at ambient temperature, TA = 25°C
−20 ±1 +20 nA Relates to each electrode input; over specified
electrode input range; dc and ac lead-off are disabled,
applies across full temperature range, TA = −40°C to
+85°C
−200 +200 nA Over full AGND to AVDD input range
Input Offset −7 mV Electrode/vector mode with VCM = VCM_REF GAIN 3
−7 mV GAIN 2
−15 mV GAIN 1
−22 mV GAIN 0
Input Offset Tempco 1 ±2 μV/°C
Input Amplifier Input 1||10 GΩ||pF At 10 Hz
Impedance 2
CMRR2 105 110 dB 51 kΩ imbalance, 60 Hz with ±300 mV differential dc
offset; per AAMI/IEC standards; with driven leg loop closed
Crosstalk1 80 dB Between channels
Resolution2 19 Bits Electrode/vector mode, 2 kHz data rate, 24-bit data-word
18 Bits Electrode/vector mode, 16 kHz data rate, 24-bit data-word
16 Bits Electrode/analog lead mode, 128 kHz data rate, 16-bit
data-word
Integral Nonlinearity Error 30 ppm GAIN 0; all data rates
Differential Nonlinearity Error 5 ppm GAIN 0
Gain2 Referred to input. (2 × VREF)/Gain/(2N − 1); applies after
factory calibration; user calibration adjusts this number
GAIN 0 (×1.4) 4.9 µV/LSB At 19-bit level in 2 kHz data rate
9.81 μV/LSB At 18-bit level in 16 kHz data rate
39.24 μV/LSB At 16-bit level in 128 kHz data rate
GAIN 1 (×2.1) 3.27 μV/LSB At 19-bit level in 2 kHz data rate
6.54 μV/LSB At 18-bit level in 16 kHz data rate
26.15 μV/LSB At 16-bit level in 128 kHz data rate
GAIN 2 (×2.8) 2.45 μV/LSB At 19-bit level in 2 kHz data rate
4.9 μV/LSB At 18-bit level in 16 kHz data rate
19.62 μV/LSB At 16-bit level in 128 kHz data rate
GAIN 3 (×4.2) 1.63 μV/LSB No factory calibration for this gain setting
At 19-bit level in 2 kHz data rate
3.27 μV/LSB At 18-bit level in 16 kHz data rate
13.08 μV/LSB At 16-bit level in 128 kHz data rate

Rev. C | Page 5 of 85
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet
Parameter Min Typ Max Unit Test Conditions/Comments
Gain Error −1 +0.01 +1 % GAIN 0 to GAIN 2, factory calibrated; programmable
user or factory calibration option enables; factory gain
calibration applies only to standard ECG interface
−2 +0.1 +2 % GAIN 3 setting, no factory calibration for this gain
Gain Matching −0.1 +0.02 +0.1 % GAIN 0 to GAIN 2
−0.5 +0.1 +0.5 % GAIN 3
Gain Tempco1 25 ppm/°C
Input Referred Noise1 GAIN 2, 2 kHz data rate, see Table 4
Analog Lead Mode 6 μV p-p 0.5 Hz to 40 Hz; high performance mode
10 μV p-p 0.05 Hz to 150 Hz; high performance mode
12 μV p-p 0.05 Hz to 150 Hz; low power mode
Electrode Mode 11 μV p-p 0.05 Hz to 150 Hz; high performance mode
12 μV p-p 0.05 Hz to 150 Hz; low power mode
Digital Lead Mode 14 μV p-p 0.05 Hz to 150 Hz; high performance mode
16 μV p-p 0.05 Hz to 150 Hz; low power mode
Power Supply Sensitivity2 100 dB At 120 Hz
Analog Channel Bandwidth1 65 kHz
Dynamic Range1 104 dB GAIN 0, 2 kHz data rate, −0.5 dBFS input signal, 10 Hz
Signal-to-Noise Ratio1 100 dB −0.5 dB FS input signal
COMMON-MODE INPUT CM_IN pin
Input Voltage Range 0.3 2.3 V
Input Impedance2 1||10 GΩ||pF
Input Bias Current −40 ±1 +40 nA Over operating range; dc and ac lead-off disabled
−200 +200 nA AGND to AVDD
COMMON-MODE OUTPUT CM_OUT pin
VCM_REF 1.28 1.3 1.32 V Internal voltage; independent of supply
Output Voltage, VCM 0.3 1.3 2.3 V No dc load
Output Impedance1 0.75 kΩ Not intended to drive current
Short Circuit Current1 4 mA
Electrode Summation 1 % Resistor matching error
Weighting Error2
RESPIRATION FUNCTION These specifications apply to the following pins:
(ADAS1000 ONLY) EXT_RESP_LA, EXT_RESP_LL, EXT_RESP_RA and selected
internal respiration paths (Lead I, Lead II, Lead III)
Input Voltage Range 0.3 2.3 V AC-coupled, independent of supply
Input Voltage Range (Linear 1.8/gain V p-p Programmable gain (10 states)
Operation)
Input Bias Current −10 ±1 +10 nA Applies to EXT_RESP_xx pins over AGND to AVDD
Input Referred Noise1 0.85 μV rms
Frequency2 46.5 to 64 kHz Programmable frequency, see Table 30
Excitation Current Respiration drive current corresponding to differential
voltage programmed by RESPAMP bits in RESPCTL
register. Internal respiration mode, cable 5 kΩ/200 pF,
1.2 kΩ chest impedance
64 μA p-p Drive Range A
32 μA p-p Drive Range B2
16 μA p-p Drive Range C2
8 μA p-p Drive Range D2
Resolution2 24 bits Update rate 125 Hz
Measurement Resolution1 0.2 Ω Cable <5 kΩ/200 pF per electrode, body resistance
modeled as 1.2 kΩ
0.02 Ω No cable impedance, body resistance modeled as 1.2 kΩ
In-Amp Gain1 1 to 10 Digitally programmable in steps of 1
Gain Error 1 % LSB weight for GAIN 0 setting
Gain Tempco1 25 ppm/C

Rev. C | Page 6 of 85
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2
Parameter Min Typ Max Unit Test Conditions/Comments
RIGHT LEG DRIVE/DRIVEN LEAD
(ADAS1000/ADAS1000-1 ONLY)
Output Voltage Range 0.2 AVDD − 0.2 V
RLD_OUT Short Circuit Current −5 ±2 +5 mA External protection resistor required to meet regulatory
patient current limits; output shorted to AVDD/AGND
Closed-Loop Gain Range2 25 V/V
Slew Rate2 200 mV/ms
Input Referred Noise1 8 μV p-p 0.05 Hz to 150 Hz
Amplifier GBP2 1.5 MHz
DC LEAD-OFF Internal current source, pulls up open ECG pins;
programmable in 10 nA steps: 10 nA to 70 nA
Lead-Off Current Accuracy ±10 % Of programmed value
High Threshold Level1 2.4 V Inputs are compared to threshold levels; if inputs
exceed levels, lead-off flag is raised
Low Threshold Level1 0.2 V
Threshold Accuracy 25 mV
AC LEAD-OFF Programmable in 4 steps: 12.5 nA rms, 25 nA rms,
50 nA rms, 100 nA rms
Frequency Range 2.039 kHz Fixed frequency
Lead-Off Current Accuracy ±10 % Of programmed value, measured into low impedance
REFIN
Input Range2 1.76 1.8 1.84 V Channel gain scales directly with REFIN
Input Current 113 μA Per active ADC
450 675 950 μA 5 ECG channels and respiration enabled
REFOUT On-chip reference voltage for ADC; not intended to
drive other components reference inputs directly,
must be buffered externally
Output Voltage, VREF 1.785 1.8 1.815 V
Reference Tempco1 ±10 ppm/°C
Output Impedance2 0.1 Ω
Short Circuit Current1 4.5 mA Short circuit to ground
Voltage Noise1 33 μV p-p 0.05 Hz to 150 Hz (ECG band)
17 μV p-p 0.05 Hz to 5 Hz (respiration)
CALIBRATION DAC Available on CAL_DAC_IO (output for master, input
for slave)
DAC Resolution 10 Bits
Full-Scale Output Voltage 2.64 2.7 2.76 V No load, nominal FS output is 1.5 × REFOUT
Zero-Scale Output Voltage 0.24 0.3 0.36 V No load
DNL −1 +1 LSB
Output Series Resistance2 10 kΩ Not intended to drive low impedance load, used for
slave CAL_DAC_IO configured as an input
Input Current ±5 nA When used as input
CALIBRATION DAC TEST TONE
Output Voltage 0.9 1 1.1 mV p-p Rides on common-mode voltage, VCM_REF = 1.3 V
Square Wave 1 Hz
Low Frequency Sine Wave 10 Hz
High Frequency Sine Wave 150 Hz
SHIELD DRIVER (ADAS1000/
ADAS1000-1 ONLY)
Output Voltage Range 0.3 2.3 V Rides on common-mode voltage, VCM
Gain 1 V/V
Offset Voltage −20 +20 mV
Short Circuit Current 15 25 μA Output current limited by internal series resistance
Stable Capacitive Load2 10 nF
CRYSTAL OSCILLATOR Applied to XTAL1 and XTAL2
Frequency2 8.192 MHz
Start-Up Time2 15 ms Internal startup

Rev. C | Page 7 of 85
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet
Parameter Min Typ Max Unit Test Conditions/Comments
CLOCK_IO External clock source supplied to CLK_IO; this pin
is configured as an input when the device is
programmed as a slave
Operating Frequency2 8.192 MHz
Input Duty Cycle2 20 80 %
Output Duty Cycle2 50 %
DIGITAL INPUTS Applies to all digital inputs
Input Low Voltage, VIL 0.3 × IOVDD V
Input High Voltage, VIH 0.7 × IOVDD V
Input Current, IIH, IIL −1 +1 μA
−20 +20 μA RESET has an internal pull-up
Pin Capacitance2 3 pF
DIGITAL OUTPUTS
Output Low Voltage, VOL 0.4 V ISINK = 1 mA
Output High Voltage, VOH IOVDD − 0.4 V ISOURCE = −1 mA
Output Rise/Fall Time 4 ns Capacitive load = 15 pF, 20% to 80%
DVDD REGULATOR Internal 1.8 V regulator for DVDD
Output Voltage 1.75 1.8 1.85 V
Available Current1 1 mA Droop < 10 mV; for external device loading purposes
Short Circuit Current limit 40 mA
ADCVDD REGULATOR Internal 1.8 V regulator for ADCVDD; not
recommended as a supply for other circuitry
Output Voltage 1.75 1.8 1.85 V
Short Circuit Current Limit 40 mA
POWER SUPPLY RANGES2
AVDD 3.15 3.3 5.5 V
IOVDD 1.65 3.6 V
ADCVDD 1.71 1.8 1.89 V If applied by external 1.8 V regulator
DVDD 1.71 1.8 1.89 V If applied by external 1.8 V regulator
POWER SUPPLY CURRENTS
AVDD Standby Current 785 975 μA
IOVDD Standby Current 1 60 μA
EXTERNALLY SUPPLIED ADCVDD All 5 channels enabled, RLD enabled, pace enabled
AND DVDD
AVDD Current 3.4 6.25 mA High performance mode
3.1 5.3 mA Low performance mode
4.25 6.3 mA High performance mode, respiration enabled
ADCVDD Current 6.2 9 mA High performance mode
4.7 6.5 mA Low performance mode
7 9 mA High performance mode, respiration enabled
DVDD Current 2.7 5 mA High performance mode
1.4 3.5 mA Low performance mode
3.4 5.5 mA High performance mode, respiration enabled
INTERNALLY SUPPLIED ADCVDD All 5 channels enabled, RLD enabled, pace enabled
AND DVDD
AVDD Current 12.5 15.3 mA High performance mode
9.4 12.4 mA Low performance mode
14.8 17.3 mA High performance mode, respiration enabled
POWER DISSIPATION All 5 channels enabled, RLD enabled, pace enabled
Externally Supplied ADCVDD
and DVDD 3
All 5 Input Channels and RLD 27 mW High performance (low noise)
21 mW Low power mode
Internally Supplied ADCVDD All 5 channels enabled, RLD enabled, pace enabled
and DVDD
All 5 Input Channels and RLD 41 mW High performance (low noise)
31 mW Low power mode

Rev. C | Page 8 of 85
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2
Parameter Min Typ Max Unit Test Conditions/Comments
OTHER FUNCTIONS 4
Power Dissipation
Respiration 7.6 mW
Shield Driver 150 μW

1
Guaranteed by characterization, not production tested.
2
Guaranteed by design, not production tested.
3
ADCVDD and DVDD can be powered from an internal LDO or, alternatively, can be powered from external 1.8 V rail, which may result in a lower power solution.
4
Pace is a digital function and incurs no power penalty.

Rev. C | Page 9 of 85
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet
NOISE PERFORMANCE
Table 3. Typical Input Referred Noise over 0.5 Second Window (µV p-p) 1
GAIN 0 (×1.4) GAIN 1 (×2.1) GAIN 2 (×2.8) GAIN 3 (×4.2)
Mode Data Rate 2 ±1 VCM ±0.67 VCM ±0.5 VCM ±0.3 VCM
Analog Lead Mode 3
High Performance Mode 2 kHz (0.5 Hz to 40 Hz) 8 6 5 4
2 kHz (0.05 Hz to 150 Hz) 14 11 9 7.5
1
Typical values measured at 25°C, not subject to production test.
2
Data gathered using the 2 kHz packet/frame rate is measured over 0.5 seconds. The ADAS1000 internal programmable low-pass filter is configured for either 40 Hz or
150 Hz bandwidth. The data is gathered and post processed using a digital filter of either 0.05 Hz or 0.5 Hz to provide data over noted frequency bands.
3
Analog lead mode as shown in Figure 58.

Table 4. Typical Input Referred Noise (μV p-p) 1

GAIN 0 (×1.4) GAIN 1 (×2.1) GAIN 2 (×2.8) GAIN 3 (×4.2)
Mode Data Rate 2 ±1 VCM ±0.67 VCM ±0.5 VCM ±0.3 VCM
Analog Lead Mode 3
High Performance Mode 2 kHz (0.5 Hz to 40 Hz) 12 8.5 6 5
2 kHz (0.05 Hz to 150 Hz) 20 14.5 10 8.5
2 kHz (0.05 Hz to 250 Hz) 27 18 14.5 10.5
2 kHz (0.05 Hz to 450 Hz) 33.5 24 19 13.5
16 kHz 95 65 50 39
128 kHz 180 130 105 80
Low Power Mode 2 kHz (0.5 Hz to 40 Hz) 13 9.5 7.5 5.5
2 kHz (0.05 Hz to 150 Hz) 22 15.5 12 9
16 kHz 110 75 59 45
128 kHz 215 145 116 85
Electrode Mode 4
High Performance Mode 2 kHz (0.5 Hz to 40 Hz) 13 9.5 8 5.5
2 kHz (0.05 Hz to 150 Hz) 21 15 11 9
2 kHz (0.05 Hz to 250 Hz) 26 19 15.5 11.5
2 kHz (0.05 Hz to 450 Hz) 34.5 25 20.5 14.5
16 kHz 100 70 57 41
128 kHz 190 139 110 85
Low Power Mode 2 kHz (0.5 Hz to 40 Hz) 14 9.5 7.5 5.5
2 kHz (0.05 Hz to 150 Hz) 22 15.5 12 9.5
16 kHz 110 75 60 45
128 kHz 218 145 120 88
Digital Lead Mode 5, 6
High Performance Mode 2 kHz (0.5 Hz to 40 Hz) 16 11 9 6.5
2 kHz (0.05 Hz to 150 Hz) 25 19 15 10
2 kHz (0.05 Hz to 250 Hz) 34 23 18 13
2 kHz (0.05 Hz to 450 Hz) 46 31 24 17.5
16 kHz 130 90 70 50
Low Power Mode 2 kHz (0.5 Hz to 40 Hz) 18 12.5 10 7
2 kHz (0.05 Hz to 150 Hz) 30 21 16 11
16 kHz 145 100 80 58
1
Typical values measured at 25°C, not subject to production test.
2
Data gathered using the 2 kHz packet/frame rate is measured over 20 seconds. The ADAS1000 internal programmable low-pass filter is configured for either 40 Hz or
150 Hz bandwidth. The data is gathered and post processed using a digital filter of either 0.05 Hz or 0.5 Hz to provide data over noted frequency bands.
3
Analog lead mode as shown in Figure 58.
4
Single-ended input electrode mode as shown in Figure 61. Electrode mode refers to common electrode A, common electrode B, and single-ended input electrode
configurations. See Electrode/Lead Formation and Input Stage Configuration section.
5
Digital lead mode as shown in Figure 59.
6
Digital lead mode is available in 2 kHz and 16 kHz data rates.

Rev. C | Page 10 of 85
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2
TIMING CHARACTERISTICS
Standard Serial Interface
AVDD = 3.3 V ± 5%, IOVDD = 1.65 V to 3.6 V, AGND = DGND = 0 V, REFIN tied to REFOUT, externally supplied crystal/clock =
8.192 MHz. TA = −40°C to +85°C, unless otherwise noted. Typical specifications are mean values at TA = 25°C.

Table 5.
IOVDD
Parameter 1 3.3 V 2.5 V 1.8 V Unit Description
Output Rate 2 2 128 kHz Across specified IOVDD supply range; three programmable output data
rates available as configured in FRMCTL register (see Table 37) 2 kHz,
16 kHz, 128 kHz; use skip mode for slower rates
SCLK Cycle Time 25 40 50 ns min See Table 21 for details on SCLK vs. packet data rates
tCSSA 8.5 9.5 12 ns min CS valid setup time to rising SCLK
tCSHA 3 3 3 ns min CS valid hold time to rising SCLK
tCH 8 8 8 ns min SCLK high time
tCL 8 8 8 ns min SCLK low time
tDO 8.5 11.5 20 ns typ SCLK falling edge to SDO valid delay; SDO capacitance of 15 pF
11 19 24 ns max
tDS 2 2 2 ns min SDI valid setup time from SCLK rising edge
tDH 2 2 2 ns min SDI valid hold time from SCLK rising edge
tCSSD 2 2 2 ns min CS valid setup time from SCLK rising edge
tCSHD 2 2 2 ns min CS valid hold time from SCLK rising edge
tCSW 25 40 50 ns min CS high time between writes (if used). Note that CS is an optional input,
it may be tied permanently low. See a full description in the Serial
Interfaces section.
tDRDY_CS2 0 0 0 ns min DRDY to CS setup time
tCSO 6 7 9 ns typ Delay from CS assert to SDO active
RESET Low Time2 20 20 20 ns min Minimum pulse width; RESET is edge triggered
1
Guaranteed by characterization, not production tested.
2
Guaranteed by design, not production tested.

SCLK

tCSSA tCSSD
tCH tCL
tCSHA tCSHD

CS
tCSW
tDS tDH

MSB LSB

SDI DB[31] DB[30] DB[29] DB[25] DB[24] DB[23] DB[1] DB[0]

R/W ADDRESS DATA

tCSO
MSB LSB

SDO DRDV DO_31LAST DO_30LAST DO_29LAST DO_25LAST DO_1LAST DO_0LAST

09660-002

tDO

Figure 2. Data Read and Write Timing Diagram (CPHA = 1, CPOL = 1)

Rev. C | Page 11 of 85
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet
tDRDY_CS

DRDY

tCH
SCLK

tCSSA tCL
tCSSD
tCSHD
tCSHA

CS

tCSW
tDS
tDH
MSB LSB MSB LSB

DB[31] DB[30] DB[29] DB[25] DB[24] DB[31] DB[30] DB[1] DB[0]

SDI DB[23] DB[1] DB[0] N+1 N+1
N N N N N N+1 N+1
N

DATA = NOP or 0x40

R/W ADDRESS = 0x40 (FRAMES) DATA
tCSO
MSB LSB MSB LSB

SDO DB[31] DB[30] DB[25] DB[24] DB[23] DB[1] DB[0] DB[31] DB[30] DB[1] DB[0]
DRDY N–1
N–1 N–1 N–1 N–1 N–1 N–1 N N N N

09660-003
tDO
HEADER (FIRST WORD OF FRAME)
PREVIOUS DATA

Figure 3. Starting Read Frame Data (CPHA = 1, CPOL = 1)

tCH

SCLK

tCSSD
tCSSA tCL
tCSHA
tCSHD

CS

tCSW
tDH
tDS
MSB LSB

SDI DB[31] DB[30] DB[29] DB[28] DB[24] DB[2] DB[1] DB[0]

R/W ADDRESS DATA

tDO
MSB LSB

SDO DO_31LAST DO_30LAST DO_29LAST DO_28LAST DO_1LAST DO_0LAST

09660-004

tDO

Figure 4. Data Read and Write Timing Diagram (CPHA = 0, CPOL = 0)

Rev. C | Page 12 of 85
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2
Secondary Serial Interface (Master Interface for Customer-Based Digital Pace Algorithm) ADAS1000/ADAS1000-1 Only
AVDD = 3.3 V ± 5%, IOVDD = 1.65 V to 3.6 V, AGND = DGND = 0 V, REFIN tied to REFOUT, externally supplied crystal/clock =
8.192 MHz. TA = −40°C to +85°C, unless otherwise noted. Typical specifications are mean values at TA = 25°C. The following timing
specifications apply for the master interface when ECGCTL register is configured for high performance mode (ECGCTL[3] = 1), see
Table 28.

Table 6.
Parameter 1 Min Typ Max Unit Description
Output Frame Rate 2 128 kHz All five 16-bit ECG data-words are available at frame rate of 128 kHz only
fSCLK2 2.5 × crystal MHz Crystal frequency = 8.192 MHz
frequency
tMCSSA 24.4 ns MCS valid setup time
tMDO 0 ns MSCLK rising edge to MSDO valid delay
tMCSHD 48.8 ns MCS valid hold time from MSCLK falling edge
tMCSW 2173 ns MCS high time, SPIFW = 0, MCS asserted for entire frame as shown in
Figure 5, and configured in Table 33
2026 ns MCS high time, SPIFW = 1, MCS asserted for each word in frame as shown in
Figure 6 and configured in Table 33
1
Guaranteed by characterization, not production tested.
2
Guaranteed by design, not production tested.

tMSCLK
2

tMSCLK

MSCLK

tMCSSA

tMCSHD

MCS
SPIFW = 0* tMCSW

MSB LSB MSB LSB MSB LSB

MSDO D0_15 D0_14 D0_1 D0_0 D1_15 D1_14 D5_0 D6_15 D6_14 D6_0

tMDO

HEADER: 0xF AND 12-BIT COUNTER 16-BIT CRC WORD

09660-105
5 × 16-BIT ECG DATA

*SPIFW = 0 PROVIDES MCS FOR EACH FRAME, SCLK STAYS HIGH FOR 1/2 MSCLK CYCLE BETWEEN EACH WORD.

Figure 5. Data Read and Write Timing Diagram for SPIFW = 0, Showing Entire Packet of Data (Header, 5 ECG Words, and CRC Word)

tMSCLK

MSCLK

tMCSSA
tMSCLK tMCSHD

MCS
SPIFW = 1* tMCSW

MSB LSB MSB LSB MSB LSB

MSDO D0_15 D0_14 D0_1 D0_0 D1_15 D1_14 D5_0 D6_15 D6_14 D6_0

tMDO
09660-005

HEADER: 0xF AND 12-BIT COUNTER 5 × 16-BIT ECG DATA 16-BIT CRC WORD

*SPIFW = 1 PROVIDES MCS FOR EACH FRAME, SCLK STAYS HIGH FOR 1 MSCLK CYCLE BETWEEN EACH WORD.

Figure 6. Data Read and Write Timing Diagram for SPIFW = 1, Showing Entire Packet of Data (Header, 5 ECG Words, and CRC Word)

Rev. C | Page 13 of 85
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE
Table 7.
Parameter Rating θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
AVDD to AGND −0.3 V to +6 V
IOVDD to DGND −0.3 V to +6 V Table 8. Thermal Resistance1
ADCVDD to AGND −0.3 V to +2.5 V Package Type θJA Unit
DVDD to DGND −0.3 V to +2.5 V 56-Lead LFCSP 35 °C/W
REFIN/REFOUT to REFGND −0.3 V to +2.1 V 64-Lead LQFP 42.5 °C/W
ECG and Analog Inputs to AGND −0.3 V to AVDD + 0.3 V
Digital Inputs to DGND −0.3 V to IOVDD + 0.3 V 1
Based on JEDEC standard 4-layer (2S2P) high effective thermal conductivity
test board (JESD51-7) and natural convection.
REFIN to ADCVDD ADCVDD + 0.3 V
AGND to DGND −0.3 V to + 0.3 V
ESD CAUTION
REFGND to AGND −0.3 V to + 0.3 V
ECG Input Continuous Current ±10 mA
Storage Temperature Range −65°C to +125°C
Operating Junction Temperature Range −40°C to +85°C
Reflow Profile J-STD 20 (JEDEC)
Junction Temperature 150°C max
ESD
HBM 2500 V
FICDM 1000 V
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.

Rev. C | Page 14 of 85
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

SHIELD/RESPDAC_LA

CM_OUT/WCT
RLD_OUT

ADCVDD
RLD_SJ

CLK_IO
XTAL1
XTAL2
CM_IN
RESPDAC_LL

AGND
AGND

DGND
AVDD

AVDD

DVDD
CAL_DAC_IO

SYNC_GANG
VREG_EN

ADCVDD
RESET

56
55
54
53
52
51
50
49
48
47
46
45
44
43
AGND
AGND

DGND
AVDD

AVDD

DVDD
NC

NC
PD
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AGND 1 PIN 1 42 DGND
ECG5_V2 2 INDICATOR 41 IOVDD
NC 1 48 NC ECG4_V1 3 40 GPIO0/MCS
PIN 1 ECG3_RA 4 39 GPIO1/MSCLK
AGND 2 47 DGND
ECG2_LL 5 ADAS1000 38 GPIO2/MSDO
RESPDAC_RA 3 46 IOVDD ECG1_LA 6 37 GPIO3
56-LEAD LFCSP
EXT_RESP_RA 4 45 SDO REFIN 7 36 DGND
REFOUT 8 TOP VIEW 35 CS
EXT_RESP_LL 5 44 SCLK
REFGND 9 (Not to Scale) 34 DRDY
EXT_RESP_LA 6 43 SDI EXT_RESP_LA 10 33 SDI
EXT_RESP_LL 11 32 SCLK
REFGND 7 ADAS1000 42 DRDY
SDO
64-LEAD LQFP EXT_RESP_RA 12 31
REFOUT 8 41 CS
RESPDAC_RA 13 30 IOVDD
REFIN 9 TOP VIEW 40 DGND AGND 14 29 DGND
(Not to Scale)
ECG1_LA 10 39 GPIO3

15
16
17
18
19
20
21
22
23
24
25
26
27
28
ECG2_LL 11 38 GPIO2/MSDO

PD
VREG_EN

AGND
AGND

RESET

DGND
AVDD

AVDD

DVDD
SHIELD/RESPDAC_LA
RESPDAC_LL

ADCVDD

SYNC_GANG
CAL_DAC_IO
ECG3_RA 12 37 GPIO1/MSCLK
ECG4_V1 13 36 GPIO0/MCS

ECG5_V2 14 35 IOVDD

AGND 15 34 DGND

NC 16 33 NC

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
CM_OUT/WCT

XTAL1
XTAL2
RLD_OUT
NC

CM_IN

AGND
AGND

CLK_IO

DGND
NC
AVDD

RLD_SJ

AVDD

DVDD
ADCVDD

09660-006
NOTES
1. THE EXPOSED PADDLE IS ON THE TOP OF THE PACKAGE;
IT IS CONNECTED TO THE MOST NEGATIVE POTENTIAL, AGND.
09660-007

NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.

Figure 7. ADAS1000 64-Lead LQFP Pin Configuration Figure 8. ADAS1000 56-Lead LFCSP Pin Configuration
CM_OUT/WCT
RLD_OUT

ADCVDD
RLD_SJ

CLK_IO
XTAL1
XTAL2
CM_IN

AGND
AGND

DGND
AVDD

AVDD

DVDD
56
55
54
53
52
51
50
49
48
47
46
45
44
43

AGND 1 PIN 1 42 DGND

ECG5_V2 2 INDICATOR 41 IOVDD
ECG4_V1 3 40 GPIO0/MCS
ECG3_RA 4 39 GPIO1/MSCLK
ECG2_LL 5 38 GPIO2/MSDO
ECG1_LA 6 ADAS1000-1 37 GPIO3
REFIN 7 56-LEAD LFCSP 36 DGND
REFOUT 8 35 CS
TOP VIEW
REFGND 9 (Not to Scale) 34 DRDY
NC 10 33 SDI
NC 11 32 SCLK
NC 12 31 SDO
NC 13 30 IOVDD
AGND 14 29 DGND
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SHIELD

PD
NC

VREG_EN

AGND
AGND

RESET

DGND
AVDD

AVDD

DVDD
ADCVDD

SYNC_GANG
CAL_DAC_IO

09660-008

NOTES
1. THE EXPOSED PADDLE IS ON THE TOP OF THE PACKAGE;
IT IS CONNECTED TO THE MOST NEGATIVE POTENTIAL, AGND.

Figure 9. ADAS1000-1 56-Lead LFCSP Pin Configuration

Rev. C | Page 15 of 85
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet

SYNC_GANG
CAL_DAC_IN

VREG_EN

ADCVDD

ADCVDD
RESET
AGND
AGND

DGND

RLD_SJ
AVDD

AVDD

DVDD

CLK_IN
CM_IN

AGND
AGND

DGND
AVDD

AVDD

DVDD
NC

NC

NC

NC
PD

NC

NC

NC
NC
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

56
55
54
53
52
51
50
49
48
47
46
45
44
43
NC 1 48 NC
PIN 1
AGND 2 47 DGND
42 DGND
AGND 1 PIN 1
NC 3 46 IOVDD ECG5 2 INDICATOR 41 IOVDD
NC 4 45 SDO ECG4 3 40 GPIO0
ECG3 4 39 GPIO1
NC 5 44 SCLK
ECG2 5 38 GPIO2
NC 6 43 SDI ADAS1000-2 37 GPIO3
ECG1 6 56-LEAD LFCSP
REFGND 7 ADAS1000-2 42 DRDY REFIN 7 36 DGND
REFOUT 8 64-LEAD LQFP 41 CS REFOUT 8 35 CS
TOP VIEW
REFGND 9 (Not to Scale) 34 DRDY
REFIN 9 TOP VIEW 40 DGND
(Not to Scale) NC 10 33 SDI
ECG1 10 39 GPIO3 NC 11 32 SCLK
ECG2 11 38 GPIO2 NC 12 31 SDO
ECG3 12 37 GPIO1
NC 13 30 IOVDD
AGND 14 29 DGND
ECG4 13 36 GPIO0

ECG5 14 35 IOVDD

15
16
17
18
19
20
21
22
23
24
25
26
27
28
AGND 15 34 DGND

PD
NC

NC
VREG_EN

AGND
AGND

RESET

DGND
AVDD

AVDD

DVDD
ADCVDD

SYNC_GANG
CAL_DAC_IN
NC 16 33 NC

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NC

CM_IN
NC

NC

AGND
AGND

NC
NC
CLK_IN

DGND
NC
AVDD

RLD_SJ

AVDD

DVDD
ADCVDD

NOTES

09660-009
1. THE EXPOSED PADDLE IS ON THE TOP OF THE PACKAGE;
09660-010

NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. IT IS CONNECTED TO THE MOST NEGATIVE POTENTIAL, AGND.
2. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.

Figure 10. ADAS1000-2 Companion 64-Lead LQFP Pin Configuration Figure 11. ADAS1000-2 Companion 56-Lead LFCSP Pin Configuration

Table 9. Pin Function Descriptions

ADAS1000 ADAS1000-1 ADAS1000-2
LQFP LFCSP LFCSP LQFP LFCSP Mnemonic Description
18, 23, 15, 20, 15, 20, 51, 56 18, 23, 15, 20, AVDD Analog Supply. See recommendations for bypass capacitors in the Power
58, 63 51, 56 58, 63 51, 56 Supply, Grounding, and Decoupling Strategy section.
35, 46 30, 41 30, 41 35, 46 30, 41 IOVDD Digital Supply for Digital Input/Output Voltage Levels. See recommendations
for bypass capacitors in the Power Supply, Grounding, and Decoupling
Strategy section.
26, 55 23, 48 23, 48 26, 55 23, 48 ADCVDD Analog Supply for ADC. There is an on-chip linear regulator providing the
supply voltage for the ADCs. This pin is primarily provided for decoupling
purposes; however, the pin may also be supplied by an external 1.8 V supply if
the user wants to use a more efficient supply to minimize power dissipation.
In this case, use the VREG_EN pin tied to ground to disable the ADCVDD
and DVDD regulators. Do not use the ADCVDD to supply other functions.
See recommendations for bypass capacitors in the Power Supply,
Grounding, and Decoupling Strategy section.
30, 51 27, 44 27, 44 30, 51 27, 44 DVDD Digital Supply. There is an on-chip linear regulator providing the supply
voltage for the digital core. This pin is primarily provided for decoupling
purposes; however, the pin can also be overdriven, supplied by an
external 1.8 V supply if the user wants to use a more efficient supply to
minimize power dissipation. In this case, use the VREG_EN pin tied to
ground to disable the ADCVDD and DVDD regulators. See recommendations
for bypass capacitors in the Power Supply, Grounding, and Decoupling
Strategy section.
2, 15, 1, 14, 1, 14, 21, 22, 2, 15, 1, 14, 21, AGND Analog Ground.
24, 25, 21, 22, 49, 50 24, 25, 22, 49,
56, 57 49, 50 56, 57 50
31, 34, 28, 29, 28, 29, 36, 42, 31, 34, 28, 29, DGND Digital Ground.
40, 47, 36, 42, 43 40, 47, 36, 42,
50 43 50 43
59 19 19 59 19 VREG_EN Enables or disables the internal voltage regulators used for ADCVDD and
DVDD. Tie this pin to AVDD to enable or tie this pin to ground to disable
the internal voltage regulators.
10 6 6 ECG1_LA Analog Input, Left Arm (LA).
11 5 5 ECG2_LL Analog Input, Left Leg (LL).
12 4 4 ECG3_RA Analog Input, Right Arm (RA).
13 3 3 ECG4_V1 Analog Input, Chest Electrode 1 or Auxiliary Biopotential Input (V1).
14 2 2 ECG5_V2 Analog Input, Chest Electrode 2 or Auxiliary Biopotential Input (V2).

Rev. C | Page 16 of 85
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2
ADAS1000 ADAS1000-1 ADAS1000-2
LQFP LFCSP LFCSP LQFP LFCSP Mnemonic Description
10 6 ECG1 Analog Input 1.
11 5 ECG2 Analog Input 2.
12 4 ECG3 Analog Input 3.
13 3 ECG4 Analog Input 4.
14 2 ECG5 Analog Input 5.
4 12 EXT_RESP_RA Optional External Respiration Input.
5 11 EXT_RESP_LL Optional External Respiration Input.
6 10 EXT_RESP_LA Optional External Respiration Input.
62 16 RESPDAC_LL Optional path for higher performance respiration resolution, respiration
DAC drive, Negative Side 0.
60 18 SHIELD/ Shared Pin (User-Configured).
RESPDAC_LA Output of Shield Driver (SHIELD).
Optional Path for Higher Performance Respiration Resolution, Respiration
DAC Drive, Negative Side 1 (RESPDAC_LA).
3 13 RESPDAC_RA Optional Path for Higher Performance Respiration Resolution, Respiration
DAC Drive, Positive Side.
22 52 52 CM_OUT/WCT Common-Mode Output Voltage (Average of Selected Electrodes). Not
intended to drive current.
19 55 55 19 55 CM_IN Common-Mode Input.
21 53 53 21 53 RLD_SJ Summing Junction for Right Leg Drive Amplifier.
20 54 54 RLD_OUT Output and Feedback Junction for Right Leg Drive Amplifier.
61 17 17 CAL_DAC_IO Calibration DAC Input/Output. Output for a master device, input for a
slave. Not intended to drive current.
9 7 7 9 7 REFIN Reference Input. For standalone mode, use REFOUT connected to REFIN.
External 10 μF with ESR < 0.2 Ω in parallel with 0.1 μF bypass capacitors to
GND are required and must be placed as close to the pin as possible. An
external reference can be connected to REFIN.
8 8 8 8 8 REFOUT Reference Output.
7 9 9 7 9 REFGND Reference Ground. Connect to a clean ground.
27, 28 47, 46 47, 46 XTAL1, XTAL2 External crystal connects between these two pins; apply external clock
drive to CLK_IO. Each XTAL pin requires a capacitor to ground. It is
recommended that this capacitor be in the range of 6 pF to 10 pF,
depending on the crystal. Where the chosen crystal has a high ESR and
large solder footprint, a lower capacitance ensures a reliable startup.
29 45 45 CLK_IO Buffered Clock Input/Output. In normal operation, this pin is an output for
a master device; input for a slave when configured for gang mode. The
CLK_IO pin can also be driven by an external clock as configured through
the ECGCTL register. The CLK_IO pin powers up in high impedance.
41 35 35 41 35 CS Chip Select and Frame Sync, Active Low. CS can be used to frame each
word or to frame the entire suite of data in framing mode.
44 32 32 44 32 SCLK Clock Input. Data is clocked into the shift register on a rising edge and
clocked out on a falling edge.
43 33 33 43 33 SDI Serial Data Input.
53 25 25 53 25 PD Power-Down, Active Low.
45 31 31 45 31 SDO Serial Data Output. This pin is used for reading back register configuration
data and for the data frames.
42 34 34 42 34 DRDY Digital Output. This pin indicates that conversion data is ready to be read
back when low, busy when high. When reading packet data, the entire
packet must be read to allow DRDY to return high.
54 24 24 54 24 RESET Digital Input. This pin has an internal pull-up. This pin resets all internal
nodes to their power-on reset values.
52 26 26 52 26 SYNC_GANG Digital Input/Output (Output on Master, Input on Slave). Used for
synchronization control where multiple devices are connected together.
Powers up in high impedance.
36 40 40 GPIO0/MCS General-Purpose I/O or Master 128 kHz SPI CS.
37 39 39 GPIO1/MSCLK General-Purpose I/O or Master 128 kHz SPI SCLK.
38 38 38 GPIO2/MSDO General-Purpose I/O or Master 128 kHz SPI SDO.
39 37 37 GPIO3 General-Purpose I/O.

Rev. C | Page 17 of 85
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet
ADAS1000 ADAS1000-1 ADAS1000-2
LQFP LFCSP LFCSP LQFP LFCSP Mnemonic Description
1, 16, 10, 11, 12, 1, 3, 4, 10, 11, NC No connect. Do not connect to these pins (see Figure 7, Figure 9,
17, 32, 13, 16 5, 6, 16, 12, 13, Figure 10, and Figure 11).
33, 48, 17, 20, 16, 18,
49, 64 22, 27, 46, 47,
28, 32, 52, 54
33, 48,
49, 60,
62, 64
36 40 GPIO0 General-Purpose I/O.
37 39 GPIO1 General-Purpose I/O.
38 38 GPIO2 General-Purpose I/O.
39 37 GPIO3 General-Purpose I/O.
18 SHIELD Output of Shield Driver.
61 17 CAL_DAC_IN Calibration DAC Input. Input for companion device. Calibration signal
comes from the master.
29 45 CLK_IN Buffered Clock Input. Drive this pin from the master CLK_IO pin.
57 57 57 EPAD Exposed Pad. The exposed paddle is on the top of the package; it is
connected to the most negative potential, AGND.

Rev. C | Page 18 of 85
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2

TYPICAL PERFORMANCE CHARACTERISTICS

8 15
0.5Hz TO 40Hz
GAIN SETTING 0 = 1.4
DATA RATE = 2kHz
6 10 SECONDS OF DATA
10
INPUT REFERRED NOISE (µV)

INPUT REFERRED NOISE (µV)

4
5

2
0
0

–5
–2

–4 –10 0.5Hz TO 150Hz

GAIN SETTING 3 = 4.2
DATA RATE = 2kHz
10 SECONDS OF DATA
–6 –15

09660-039

09660-042
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10
TIME (Seconds) TIME (Seconds)

Figure 12. Input Referred Noise for 0.5 Hz to 40 Hz Bandwidth, 2 kHz Data Figure 15. Input Referred Noise for 0.5 Hz to 150 Hz Bandwidth, 2 kHz Data
Rate, GAIN 0 (1.4) Rate, GAIN 3 (4.2)
8 25
0.5Hz TO 40Hz LA 150Hz
GAIN SETTING 3 = 4.2 LA 40Hz
DATA RATE = 2kHz
6 10 SECONDS OF DATA
20
INPUT REFERRED NOISE (µV)

INPUT REFERRED NOISE (µV)

4

15
2

0
10

–2

5
–4

–6 0

09660-043
09660-040

0 1 2 3 4 5 6 7 8 9 10 GAIN 0 GAIN 1 GAIN 2 GAIN 3

TIME (Seconds) GAIN SETTING

Figure 13. Input Referred noise for 0.5 Hz to 40 Hz Bandwidth, 2 kHz Data Figure 16. ECG Channel Noise Performance over a 0.5 Hz to 40 Hz or 0.5 Hz to
Rate, GAIN 3 (4.2) 150 Hz Bandwidth vs. Gain Setting
15 0.020
AVDD = 3.3V
GAIN SETTING 0 = 1.4
10
0.018
INPUT REFERRED NOISE (µV)

5
GAIN ERROR (%)

0.016

0.014
–5

0.012
–10 0.5Hz TO 150Hz
GAIN SETTING 0 = 1.4
DATA RATE = 2kHz
09660-044

10 SECONDS OF DATA
–15 0.010
09660-041

0 1 2 3 4 5 6 7 8 9 10 LA LL RA V1 V2
TIME (Seconds) ELECTRODE INPUT

Figure 14. Input Referred Noise for 0.5 Hz to 150 Hz Bandwidth, Figure 17. Typical Gain Error Across Channels
2 kHz Data Rate, GAIN 0 (1.4)

Rev. C | Page 19 of 85
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet
0.121 0.215
AVDD = 3.3V AVDD = 3.3V

0.210
0.101

0.205
0.081
GAIN ERROR (%)

THRESHOLD (V)
0.200
0.061
0.195

0.041
0.190

0.021
0.185
ECG DC LEAD-OFF THRESHOLD

09660-045
RLD DC LEAD-OFF THRESHOLD
0.001 0.180

09660-048
GAIN 0 GAIN 1 GAIN 2 GAIN 3 –40 –20 0 20 40 60 80
GAIN SETTING TEMPERATURE (°C)

Figure 18. Typical Gain Error vs. Gain Figure 21. DC Lead-Off Comparator Low Threshold vs. Temperature

0.15 2.420
AVDD = 3.3V AVDD = 3.3V
GAIN SETTING 0 = 1.4
0.10 GAIN SETTING 1 = 2.1 2.415
GAIN SETTING 2 = 2.8
0.05 GAIN SETTING 3 = 4.2
2.410
0 HIGH THRESHOLD (V)
2.405
GAIN ERROR (%)

–0.05
2.400
–0.10
2.395
–0.15
2.390
–0.20

–0.25 2.385
GAIN ERROR G0
–0.30 GAIN ERROR G1 2.380
GAIN ERROR G2 ECG DC LEAD-OFF THRESHOLD
GAIN ERROR G3 RLD DC LEAD-OFF THRESHOLD
–0.35 2.375
09660-046

09660-049
–40 –20 0 20 40 60 80 –40 –20 0 20 40 60 80
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 19. Typical Gain Error for All Gain Settings Across Temperature Figure 22. DC Lead-Off Comparator High Threshold vs. Temperature

5 0
+85°C AVDD = 3.3V AVDD = 3.3V
+55°C GAIN SETTING 0 = 1.4
4 –1
+25°C
–5°C
3 –40°C –2

2 –3
LEAKAGE (nA)

1 –4
GAIN (dB)

0 –5

–1 –6

–2 –7

–3 –8

–4 –9

–5 –10
09660-047

09660-050

0.3 0.8 1.3 1.8 2.3 1 10 100 1k

VOLTAGE (V) FREQUENCY (Hz)

Figure 20. Typical ECG Channel Leakage Current over Input Voltage Range vs. Figure 23. Filter Response with 40 Hz Filter Enabled, 2 kHz Data Rate; See
Temperature Figure 75 for Digital Filter Overview

Rev. C | Page 20 of 85
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2
0 0
AVDD = 3.3V
–1
–1
–2

–3
–2
–4

GAIN (dB)
GAIN (dB)

–5 –3

–6
–4
–7

–8
–5
–9
AVDD = 3.3V
–10 –6

09660-054
09660-051
1 10 100 1k 1 10 100 1k 10k 100k
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 24. Filter Response with 150 Hz Filter Enabled, 2 kHz Data Rate; Figure 27. Analog Channel Bandwidth
See Figure 75 for Digital Filter Overview
0 0
AVDD = 3.3V
–1 –1

–2 –2
–3
–3
–4
GAIN (dB)
GAIN (dB)

–4
–5
–5
–6
–6
–7
–7
–8

–9 –8

–10 –9

09660-055
09660-052

1 10 100 1k 1 10 100 1k 10k 100k

FREQUENCY (Hz) FREQUENCY (Hz)

Figure 25. Filter Response with 250 Hz Filter Enabled, 2 kHz Data Rate; Figure 28. Filter Response Running at 128 kHz Data Rate; See Figure 75 for
See Figure 75 for Digital Filter Overview Digital Filter Overview
0 1.8010
AVDD = 3.3V
–1 1.8005

–2
1.8000
–3
1.7995
VOLTAGE (V)

–4
GAIN (dB)

1.7990
–5
1.7985
–6
1.7980
–7
1.7975
–8

–9 1.7970

–10 1.7965
09660-053

09660-056

1 10 100 1k –40 –20 0 20 40 60 80

FREQUENCY (Hz) TEMPERATURE (°C)

Figure 26. Filter Response with 450 Hz Filter Enabled, 2 kHz Data Rate; Figure 29. Typical Internal VREF vs. Temperature
See Figure 75 for Digital Filter Overview

Rev. C | Page 21 of 85
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet
1.3010 805
AVDD = 3.3V AVDD = 3.3V
1.3005 800

AVDD SUPPLY CURRENT (µA)

1.3000 795

1.2995 790
VOLTAGE (V)

1.2990 785

1.2985 780

1.2980 775

1.2975 770

1.2970 765

09660-069
09660-057
–40 –20 0 20 40 60 80 –40 –20 0 20 40 60 80

TEMPERATURE (°C) TEMPERATURE (°C)

Figure 30. VCM_REF vs. Temperature Figure 33. Typical AVDD Supply Current vs. Temperature in Standby Mode

12.50 12.65
AVDD = 3.3V LOW NOISE/HIGH
5 ECG CHANNELS ENABLED PERFORMANCE MODE
INTERNAL LDO UTILIZED
12.45 HIGH PERFORMANCE/LOW NOISE MODE 12.60
AVDD SUPPLY CURRENT (mA)

12.40 12.55
CURRENT (mA)

12.35 12.50

12.30 12.45

12.25 12.40

12.20 12.35

09660-059
09660-060

–40 –20 0 20 40 60 80 3.0 3.5 4.0 4.5 5.0 5.5 6.0

TEMPERATURE (°C) VOLTAGE (V)

Figure 31. Typical AVDD Supply Current vs. Temperature, Using Internal Figure 34. Typical AVDD Supply Current vs. AVDD Supply Voltage
ADVCDD/DVDD Supplies
3.430 0.28591
AVDD = 3.3V AVDD = 3.3V
5 ECG CHANNELS ENABLED ECG PATH/DEFIB/CABLE IMPEDANCE = 0 Ω
PATIENT IMPEDANCE = 1k Ω
3.425 ADCVDD AND DVDD SUPPLIED EXTERNALLY RESPIRATION RATE = 10RESPPM
HIGH PERFORMANCE/LOW NOISE MODE 0.28590 RESPAMP = 11 = 64µA p-p
RESPGAIN = 0011 = 4
AVDD SUPPLY CURRENT (mA)

RESPIRATION MAGNITUDE (V)

3.420
0.28589

3.415
0.28588
3.410 25µV

0.28587
3.405
DELTA = VOLTAGE/CURRENT/GAIN
0.28586 BASELINE = VOLTAGE/CURRENT/GAIN = 25µV/32µA/4
3.400 = 0.2Ω
= 0.28588V/32µA/4
= 2.2kΩ (1kΩ PATIENT IMPEDANCE
AND 1kΩ INTERNAL SWITCH
IMPEDANCE AND SOME ERROR)
3.395 0.28525
09660-058

09660-062

–40 –20 0 20 40 60 80 0 5 10 15 20 25 30
TEMPERATURE (°C) TIME (Seconds)

Figure 32. Typical AVDD Supply Current vs. Temperature, Using Externally Figure 35. Respiration with 200 mΩ Impedance Variation, Using Internal
Supplied ADVCDD/DVDD Respiration Paths and Measured with a 0 Ω Patient Cable

Rev. C | Page 22 of 85
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2
0.24229 0.517390
AVDD = 3.3V AVDD = 3.3V
ECG PATH/DEFIB/CABLE IMPEDANCE = 0Ω ECG PATH/DEFIB/CABLE IMPEDANCE = 5k Ω/250pF
PATIENT IMPEDANCE = 1k Ω
PATIENT IMPEDANCE = 1kΩ EXTCAP = 100pF
0.24228 RESPIRATION RATE = 10RESPPM 0.517385 RESPIRATION RATE = 10RESPPM
RESPAMP = 11 = 64µA p-p

RESPIRATION MAGNITUDE (V)

RESPIRATION MAGNITUDE (V)

RESPGAIN = 0011 = 4

0.24227 0.517380

0.24226 0.517375

12µV

0.24225 0.517370
BASELINE = VOLTAGE/CURRENT/GAIN
= 0.24226V/32µA/4
= 1.9kΩ (1kΩ PATIENT IMPEDANCE
0.24224 AND 1kΩ INTERNAL SWITCH 0.517365
IMPEDANCE AND SOME ERROR)
DELTA = VOLTAGE/CURRENT/GAIN
= 12µV/32µA/4 RESPAMP = 11 = 60µA p-p
= 0.094Ω RESPGAIN = 0011 = 4
0.24223 0.517360

09660-067
09660-063
0 5 10 15 20 25 30 0 5 10 15 20 25 30
TIME (Seconds) TIME (Seconds)

Figure 36. Respiration with 100 mΩ Impedance Variation, Using Internal Figure 39. Respiration with 200 mΩ Impedance Variation, Using External
Respiration Paths and Measured with a 0 Ω Patient Cable Respiration DAC Driving 100 pF External Capacitor and Measured with a
5 kΩ Patient Cable
1.32632 0.159775
AVDD = 3.3V AVDD = 3.3V
ECG PATH/DEFIB/CABLE IMPEDANCE = 5k Ω, 250pF ECG PATH/DEFIB/CABLE IMPEDANCE = 1k Ω/560pF
PATIENT IMPEDANCE = 1k Ω PATIENT IMPEDANCE = 1k Ω
RESPIRATION RATE = 10RESPPM EXTCAP = 1nF
1.32631 RESPAMP = 11 = 55.4µA p-p 0.159770 RESPIRATION RATE = 10RESPPM
RESPIRATION MAGNITUDE (V)

RESPIRATION MAGNITUDE (V)

RESPGAIN = 0011 = 4 RESPAMP = 11
RESPGAIN = 0001 = 1
DELTA = VOLTAGE/CURRENT/GAIN
= 25µV/27.7µA/4
1.32630 = 0.22Ω 0.159765

1.32629 0.159760

1.32628 0.159755

25µV
1.32627 0.159750
BASELINE = VOLTAGE/CURRENT/GAIN
= 1.326285V/27.7µA/4
= 11.97kΩ (1kΩ PATIENT IMPEDANCE,
2 × 5kΩ CABLE IMPEDANCE)
1.32626 0.159745

09660-066
09660-064

0 5 10 15 20 25 30 0 5 10 15 20 25 30
TIME (Seconds) TIME (Seconds)

Figure 37. Respiration with 200 mΩ Impedance Variation, Using Internal Figure 40. Respiration with 200 mΩ Impedance Variation, Using External
Respiration Paths and Measured with a 5 kΩ Patient Cable Respiration DAC Driving 1 nF External Capacitor and Measured with a 1 kΩ
Patient Cable
0.26835 0.159126
BASELINE = 0.24226V/32 µA/4 = 794Ω AVDD = 3.3V
DELTA = 40µV/305µA = 0.131Ω ECG PATH/DEFIB/CABLE IMPEDANCE = 1k Ω/560pF
PATIENT IMPEDANCE = 1k Ω
0.159125
0.26834
RESPIRATION MAGNITUDE (V)
RESPIRATION MAGNITUDE (V)

0.159124

0.26833
0.159123

0.26832 0.159122

40µV
0.159121
0.26831
0.159120

0.26830 AVDD = 3.3V

ECG PATH/DEFIB/ 0.159119 EXTCAP= 1nF
CABLE IMPEDANCE = 0Ω RESPIRATION RATE = 10RESPPM RESPIRATION RATE = 10RESPPM
PATIENT IMPEDANCE = 1kΩ RESPAMP = 11 = 64µA p-p RESPAMP = 11
EXTCAP = 100pF RESPGAIN = 4 RESPGAIN = 0001 = 1
0.26829 0.159118
09660-068
09660-065

0 5 10 15 20 25 30 0 5 10 15 20 25 30

TIME (Seconds) TIME (Seconds)

Figure 38. Respiration with 200 mΩ Impedance Variation, Using External Figure 41. Respiration with 100 mΩ Impedance Variation, Using External
Respiration DAC Driving 100 pF External Capacitor and Measured with a 0 Ω Respiration DAC Driving 1 nF External Capacitor and Measured with a 1 kΩ
Patient Cable Patient Cable

Rev. C | Page 23 of 85
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet
50 150
AVDD = 3.3V LA AVDD = 3.3V LA
LL LL
40 RA RA
V1 100 V1
30 V2 V2

20
DNL ERROR (µV RTI)

50
10

INL (µV/RTI)
0 0

–10
–50
–20

–30
–100
–40

–50 –150

09660-070

09660-074
0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3
INPUT VOLTAGE (V) INPUT VOLTAGE (V)

Figure 42. DNL vs. Input Voltage Range Across Electrodes at 25°C Figure 45. INL vs. Input Voltage Across Electrode Channel for 2 kHz Data Rate

50 150
AVDD = 3.3V –40°C AVDD = 3.3V GAIN0
–5°C GAIN1
40 +25°C GAIN2
+55°C GAIN3
30 +85°C 100

20
DNL ERROR (µV RTI)

50
INL (µV/RTI)
10

–10 0

–20

–30 –50

–40

–50 –100

09660-075
09660-071

0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3
INPUT VOLTAGE (V) INPUT VOLTAGE (V)

Figure 43. DNL vs. Input Voltage Range Across Temperature Figure 46. INL vs. Input Voltage Across Gain Setting for 16 kHz Data Rate

150 150
AVDD = 3.3V GAIN0 AVDD = 3.3V GAIN0
GAIN1 GAIN1
GAIN2 GAIN2
100 GAIN3 100 GAIN3

50 50
INL (µV/RTI)
INL (µV/RTI)

0 0

–50 –50

–100 –100

–150 –150
09660-076
09660-073

0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3
INPUT VOLTAGE (V) INPUT VOLTAGE (V)

Figure 44. INL vs. Input Voltage Across Gain Setting for 2 kHz Data Rate Figure 47. INL vs. Input Voltage Across Gain Setting for 128 kHz Data Rate

Rev. C | Page 24 of 85
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2
0 120
AVDD = 3.3V
–20 GAIN 0 100
DATA RATE = 2kHz
FILTER SETTING = 150Hz 80
–40
60
AMPLITUDE (dBFS)

–60

LOOP GAIN (dB)

40
–80
20
–100
0
–120
–20
–140 –40

–160 –60

–180 –80

09660-080
09660-077
0 50 100 150 200 250 300 350 400 450 500 100m 1 10 100 1k 10k 100k 1M 10M 100M 1G
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 48. FFT with 60 Hz Input Signal Figure 51. Open-Loop Gain Response of ADAS1000 Right Leg Drive Amplifier
Without Loading

150 0
AVDD = 3.3V
–0.5dBFS
10Hz INPUT SIGNAL
–50
100
SNR
–100

LOOP GAIN (Phase)

AMPLITUDE (dB)

50
–150

0 –200

–250
–50
–300
THD

–100 –350
09660-078

09660-081
GAIN 0 GAIN 1 GAIN 2 GAIN 3 100m 1 10 100 1k 10k 100k 1M 10M 100M 1G
GAIN SETTING FREQUENCY (Hz)

Figure 49. SNR and THD Across Gain Settings Figure 52. Open-Loop Phase Response of ADAS1000 Right Leg Drive Amplifier
Without Loading

AVDD = 3.3V

DRDY
2

AVDD

1
09660-079

CH1 2.00V CH2 1.00V M1.00ms A CH1 2.48V

T 22.1%

Figure 50. Power Up AVDD Line to DRDY Going Low (Ready)

Rev. C | Page 25 of 85
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet

APPLICATIONS INFORMATION
OVERVIEW monitor and diagnostic applications. Value-added cardiac post
The ADAS1000/ADAS1000-1/ADAS1000-2 are electro cardiac processing can be executed externally on a DSP, microprocessor,
(ECG) front-end solutions targeted at a variety of medical or FPGA. The ADAS1000/ADAS1000-1/ADAS1000-2 are
applications. In addition to ECG measurements, the ADAS1000 designed for operation in both low power, portable telemetry
version also measures thoracic impedance (respiration) and applications and line powered systems; therefore, the parts offer
detects pacing artifacts, providing all the measured information power/noise scaling to ensure suitability to these varying
to the host controller in the form of a data frame supplying requirements.
either lead/vector or electrode data at programmable data rates. The devices also offer a suite of dc and ac test excitation via
The ADAS1000/ADAS1000-1/ADAS1000-2 are designed to a calibration DAC feature and CRC redundancy checks in
simplify the task of acquiring ECG signals for use in both addition to readback of all relevant register address space.

REFIN REFOUT CAL_DAC_IO RLD_SJ RLD_OUT CM_IN CM_OUT/WCT SHIELD AVDD IOVDD

DRIVEN
LEAD
VREF AMP SHIELD ADCVDD, DVDD ADCVDD
– DRIVE 1.8V
AMP REGULATORS DVDD
CALIBRATION +
DAC +
VCM_REF –
(1.3V)
RESPIRATION ADAS1000
DAC
COMMON-
MODE AMP VCM AC
AC
LEAD-OFF LEAD-OFF
10kΩ

DAC DETECTION
10kΩ

VREF
PACE
DETECTION
DC LEAD- ECG PATH
OFF/MUXES
ECG1_LA
AMP ADC

CS

ECG2_LL SCLK
AMP ADC
SDI

SDO
FILTERS,
ECG3_RA CONTROL,
AMP ADC DRDY
AND
INTERFACE
LOGIC PD
RESET
ECG4_V1 SYNC_GANG
AMP ADC

ECG5_V2 GPIO0/MCS
AMP ADC GPIO1/MSCLK
GPIO2/MSDO
GPIO3
EXT_RESP_LA

EXT_RESP_LL
AMP ADC
EXT_RESP_RA MUX
RESPDAC_LA CLOCK GEN/OSC/ CLK_IO
RESPDAC_LL RESPIRATION PATH EXTERNAL CLK
SOURCE
RESPDAC_RA
09660-011

REFGND AGND DGND XTAL1 XTAL2

Figure 53. ADAS1000 Simplified Block Diagram

Rev. C | Page 26 of 85
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2
REFIN REFOUT CAL_DAC_IO RLD_SJ RLD_OUT CM_IN CM_OUT/WCT SHIELD AVDD IOVDD

DRIVEN
LEAD
VREF AMP SHIELD ADCVDD, DVDD ADCVDD
DRIVE 1.8V
AMP REGULATORS DVDD

CALIBRATION VCM_REF
DAC (1.3V)
ADAS1000-1

COMMON-
MODE AMP VCM
AC
LEAD-OFF

10kΩ
DAC
10kΩ VREF AC
LEAD-OFF
DETECTION
ECG PATH

ECG1_LA
AMP ADC

CS

ECG2_LL SCLK
AMP ADC
SDI

SDO
DC LEAD- FILTERS,
ECG3_RA OFF/MUXES CONTROL, DRDY
AMP ADC AND
INTERFACE
LOGIC PD
RESET
ECG4_V1
AMP ADC SYNC_GANG

GPIO0/MCS
GPIO1/MSCLK
ECG5_V2
GPIO2/MSDO
AMP ADC
GPIO3

CLOCK GEN/OSC/ CLK_IO

EXTERNAL CLK
SOURCE

09660-012
REFGND AGND DGND XTAL1 XTAL2

Figure 54. ADAS1000-1 Simplified Block Diagram

Rev. C | Page 27 of 85
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet
REFIN REFOUT CAL_DAC_IN RLD_SJ CM_IN AVDD IOVDD

VREF ADCVDD, DVDD ADCVDD

1.8V
REGULATORS DVDD

COMMON-
AC MODE AMP ADAS1000-2
LEAD-OFF

10kΩ
DAC

10kΩ
VREF AC
LEAD-OFF
DETECTION
ECG PATH

ECG1
AMP ADC

CS

ECG2 SCLK
AMP ADC
SDI

SDO
FILTERS,
ECG3 DC LEAD- CONTROL,
OFF/MUXES AMP ADC DRDY
AND
INTERFACE
LOGIC PD
RESET
ECG4
AMP ADC SYNC_GANG

ECG5 GPIO0
AMP ADC GPIO1
GPIO2
GPIO3

09660-013
REFGND AGND DGND

Figure 55. ADAS1000-2 Slave Device Simplified Block Diagram

Rev. C | Page 28 of 85
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2
ECG INPUTS—ELECTRODES/LEADS ADAS1000-1/ADAS1000-2. Note that in 128 kHz data rate, lead
The ADAS1000/ADAS1000-1/ADAS1000-2 ECG product consists data is only available when configured in analog lead mode, as
of 5 ECG inputs and a reference drive, RLD (right leg drive). In a shown in Figure 58. Digital lead mode is not available for this
typical 5-lead/vector application, four of the ECG inputs data rate.
(ECG3_RA, ECG1_LA, ECG2_LL, ECG4_V1) are used in addition A 12-lead (10-electrode) system can be achieved using one
to the RLD path. This leaves one spare ECG path (which can be ADAS1000 or ADAS1000-1 device ganged together with one
used for other purposes, such as calibration or temperature ADAS1000-2 slave device as described in the Gang Mode
measurement). Both V1 and V2 input channels can be used for Operation section. Here, 9 ECG electrodes and one RLD
alternative measurements, if desired. When used in this way, the electrode achieve the 10 electrode system, again leaving one
negative terminal of the input stage can be switched to the fixed spare ECG channel that can be used for alternate purposes as
internal VCM_REF = 1.3 V; see details in Table 50. suggested previously. In such a system, having nine dedicated
In a 5-lead system, the ADAS1000/ADAS1000-1/ADAS1000-2 electrodes benefits the user by delivering lead information
can provide Lead I, Lead II, and Lead III data or electrode data based on electrode measurements and calculations rather
directly via the serial interface at all frame rates. The other ECG than deriving leads from other lead measurements.
leads can be calculated by the user’s software from either the Table 10 outlines the calculation of the leads (vector) from the
lead data or the electrode data provided by the ADAS1000/ individual electrode measurements.

Table 10. Lead Composition 1

Lead Name Composition Equivalent
ADAS1000 or ADAS1000-1 I LA – RA
II LL – RA
III LL – LA
aVR 2 RA – 0.5 × (LA + LL) −0.5 × (I + II)
aVL2 LA – 0.5 × (LL + RA) 0.5 × (I − III)
aVF2 LL – 0.5 × (LA + RA) 0.5 × (II + III)
V1’ V1 – 0.333 × (LA + RA + LL)
V2’ V2 – 0.333 × (LA + RA + LL)
12 Leads Achieved by Adding ADAS1000-2 Slave V3’ V3 – 0.333 × (LA + RA + LL)
V4’ V4 – 0.333 × (LA + RA + LL)
V5’ V5 – 0.333 × (LA + RA + LL)
V6’ V6 – 0.333 × (LA + RA + LL)
1
These lead compositions apply when the master ADAS1000 device is configured into lead mode (analog lead mode or digital lead mode) with VCM = WCT = (RA + LA
+ LL)/3. When configured for 12-lead operation with a master and slave device, the VCM signal derived on the master device (CM_OUT) is applied to the CM_IN of the
slave device. For correct operation of the slave device, the device must be configured in electrode mode (see the FRMCTL register in Table 37).
2
These augmented leads are not calculated within the ADAS1000, but can be derived in the host DSP/microcontroller/FPGA.

Rev. C | Page 29 of 85
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet
ECG CHANNEL selected electrodes to the internal 1.3 V level, VCM_REF,
maximizing each channel’s available signal range.
The ECG channel consists of a programmable gain, low noise,
differential preamplifier; a fixed gain anti-aliasing filter; buffers; All ECG channel amplifiers use chopping to minimize 1/f noise
and an ADC (see Figure 56). Each electrode input is routed to contributions in the ECG band. The chopping frequency of
its PGA noninverting input. Internal switches allow the inverting ~250 kHz is well above the bandwidth of any signals of interest.
inputs of the PGA to be connected to other electrodes and/or The 2-pole anti-aliasing filter has ~65 kHz bandwidth to support
the Wilson central terminal (WCT) to provide differential digital pace detection while still providing greater than 80 dB of
analog processing (analog lead mode), to a computed average of attenuation at the ADC’s sample rate. The ADC itself is a 14-bit,
some or all electrodes, or the internal 1.3 V common-mode 2 MHz SAR converter; 1024 × oversampling helps achieve the
reference (VCM_REF). The latter two modes support digital required system performance. The full-scale input range of the
lead mode (leads computed on-chip) and electrode mode (leads ADC is 2 × VREF, or 3.6 V, although the analog portion of the
calculated off-chip). In all cases, the internal reference level is ECG channel limits the useful signal swing to about 2.8 V. The
removed from the final lead data. ADAS1000 contains flags to indicate whether the ADC data is
out of range, indicating a hard electrode off state. Programmable
The ADAS1000/ADAS1000-1/ADAS1000-2 implementation overrange and underrange thresholds are shown in the LOFFUTH
uses a dc-coupled approach, which requires that the front end and LOFFLTH registers (see Table 39 and Table 40, respectively).
be biased to operate within the limited dynamic range imposed The ADC out of range flag is contained in the header word (see
by the relatively low supply voltage. The right leg drive loop Table 54).
performs this function by forcing the electrical average of all

ADAS1000
TO COMMON-MODE AMPLIFIER
FOR DRIVEN LEG AND
SHIELD DRIVER

AVDD PREAMP
PATIENT G = 1, 1.5, 2, 3 DIFF AMP fS VREF
CABLE BUFFER
EXTERNAL FILTER G = 1.4
ELECTRODE RFI AND DEFIB +
PROTECTION ADC
–
14

EXTERNAL ELECTRODE
ELECTRODE RFI AND DEFIB
PROTECTION
VCM

09660-014
SHIELD DRIVER

Figure 56. Simplified Schematic of a Single ECG Channel

Rev. C | Page 30 of 85
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2
ELECTRODE/LEAD FORMATION AND INPUT Digital Lead Mode and Calculation
STAGE CONFIGURATION When the ADAS1000/ADAS1000-1/ADAS1000-2 are configured
for digital lead mode (see the FRMCTL register, Register 0x0A[4],
The input stage of the ADAS1000/ADAS1000-1/ADAS1000-2
can be arranged in several different manners. The input Table 37), the digital core calculates each lead from the electrode
amplifiers are differential amplifiers and can be configured to signals. This is straightforward for Lead I/ Lead II/Lead III.
Calculating V1’ and V2’ requires WCT, which is also computed
generate the leads in the analog domain, before the ADCs. In
internally for this purpose. This mode ignores the common-
addition to this, the digital data can be configured to provide
mode configuration specified in the CMREFCTL register
either electrode or lead format under user control as described
in Table 37. This allows maximum flexibility of the input stage (Register 0x05). Digital lead calculation is only available in
for a variety of applications. 2 kHz and 16k Hz data rates (see Figure 59).

Analog Lead Mode and Calculation Electrode Mode: Single-Ended Input Electrode
Configuration
Leads are configured in the analog input stage when
In this mode, the electrode data are digitized relative to the
CHCONFIG = 1, as shown in Figure 58. This uses a traditional in-
common-mode signal, VCM, which can be arranged to be any
amp structure where lead formation is performed prior to
combination of the contributing ECG electrodes. Common-
digitization, with WCT created using the common-mode
mode generation is controlled by the CMREFCTL register as
amplifier. While this results in the inversion of Lead II in the
described in Table 32 (see Figure 61).
analog domain, this is digitally corrected so output data have
the proper polarity. Electrode Mode: Common Electrode A and Electrode B
Configurations
In this mode, all electrodes are digitized relative to a common
electrode, for example, RA. Standard leads must be calculated by
post processing the output data of the ADAS1000/ADAS1000-1/
ADAS1000-2 (see Figure 60 and Figure 62).

0x0A 0x01 0x05

MODE COMMENT WORD1 WORD2 WORD3 WORD4 WORD5 [4]1 [10]2 [8]3

ANALOG LEAD ANALOG LEAD LEAD I LEAD II LEAD III V1’ V2’ 0 1 0
(LA − RA) (LL − RA) (LL − LA) (V1 − VCM) (V2 − VCM)

DIGITAL LEAD SINGLE-ENDED LEAD I LEAD II LEAD III V1’ V2’ 0 0 0

INPUT, DIGITALLY
CALCULATED LEADS (LA − RA) (LL − RA) (LL − LA) (V1 − WCT4) (V2 − WCT4)

COMMON COMMON LEAD I LEAD II V3’ V1’ V2’ 0 0 1

ELECTRODE A ELECTRODE (CE)
LEADS (HERE RA (LA − RA) (LL − RA) (V3 – RA) − (LA − RA) − (LL − RA) (V1 − RA) − (LA − RA) + (LL − RA) (V2 − RA) − (LA − RA) + (LL − RA)
ELECTRODE IS
CONNECTED TO THE 3 3 3
CE ELECTRODE
(CM_IN) AND V3 IS ON
ECG3 INPUT)

SINGLE-ENDED SINGLE-ENDED LA − VCM LL − VCM RA − VCM V1 − VCM V2 − VCM 1 0 0

INPUT INPUT ELECTRODE
ELECTRODE RELATIVE TO VCM

COMMON LEADS FORMED LA − CE LL − CE V1 − CE V2 − CE V3 − CE 1 0 1

ELECTRODE B RELATIVE TO A
COMMON
ELECTRODE (CE)

1REGISTER
09660-061
FRMCTL, BIT DATAFMT: 0 = LEAD/VECTOR MODE; 1 = ELECTRODE MODE.
2REGISTER ECGCTL, BIT CHCONFIG: 0 = SINGLE ENDED INPUT (DIGITAL LEAD MODE OR ELECTRODE MODE); 1 = DIFFERENTIAL IN PUT (ANALOG LEAD MODE).
3REGISTER CMREFCTL, BIT CEREFEN: 0 = CE DISABLED; 1 = CE ENABLED.
4WILSON CENTRAL TERMINAL (WCT) = (RA + LA + LL)/3, THIS IS A DIGITALLY CALCULATED WCT BASED ON THE RA, LA, LL MEASUREMENTS.

Figure 57. Electrode and Lead Configurations

Rev. C | Page 31 of 85
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet
VCM = WCT = (LA + LL + RA)/3
CM_OUT/WCT
COMMON-
MODE AMP

LEAD I
ECG1_LA + (LA – RA)
AMP ADC
–

LEAD III
ECG2_LL + (LL – LA)
AMP ADC
–

LEAD II
ECG3_RA + (LL – RA)*
AMP ADC
–
*GETS MULITPLED
BY –1 IN DIGITAL

ECG4_V1 + V1’ = V1 – WCT

AMP ADC
–

WCT = (LA + LL + RA)/3

ECG5_V2 + V2’ = V2 – WCT

AMP ADC
–

CM_IN WCT = (LA + LL + RA)/3

FOR EXAMPLE RA COMMON
ELECTRODE CE IN

0x0A 0x01 0x05

MODE COMMENT WORD1 WORD2 WORD3 WORD4 WORD5 [4]1 [10]2 [8]3

ANALOG LEAD ANALOG LEAD LEAD I LEAD II LEAD III V1’ V2’ 0 1 0
(LA − RA) (LL − RA) (LL − LA) (V1 − VCM) (V2 − VCM)

09660-015
1REGISTER FRMCTL, BIT DATAFMT: 0 = LEAD/VECTOR MODE; 1 = ELECTRODE MODE.
2REGISTER ECGCTL, BIT CHCONFIG: 0 = SINGLE ENDED INPUT (DIGITAL LEAD MODE OR ELECTRODE MODE); 1 = DIFFERENTIAL IN PUT (ANALOG LEAD MODE).
3REGISTER CMREFCTL, BIT CEREFEN: 0 = CE DISABLED; 1 = CE ENABLED.

Figure 58. Electrode and Lead Configurations, Analog Lead Mode

VCM = WCT = (LA + LL + RA)/3

CM_OUT/WCT
COMMON-
MODE AMP

LEAD I
ECG1_LA + LA – RA
AMP ADC
–

LEAD II
ECG 2_LL + LL – RA
AMP ADC
–

LEAD III
ECG3_RA + DIGITAL DOMAIN LL – LA
AMP ADC CALCULATIONS
–

ECG4_V1 + V1 – WCT
AMP ADC
–

ECG5_V2 + V2 – WCT
AMP ADC
–

CM_IN
FOR EXAMPLE, RA
COMMON
ELECTRODE CE IN

0x0A 0x01 0x05

MODE COMMENT WORD1 WORD2 WORD3 WORD4 WORD5 [4]1 [10]2 [8]3

DIGITAL LEAD SINGLE-ENDED LEAD I LEAD II LEAD III V1’ V2’ 0 0 0

INPUT, DIGITALLY (LA − RA) (LL − RA) (LL − LA) (V1 − WCT4) (V2 − WCT4)
CALCULATED LEADS

1REGISTER FRMCTL, BIT DATAFMT: 0 = LEAD/VECTOR MODE; 1 = ELECTRODE MODE.

09660-016

2REGISTER ECGCTL, BIT CHCONFIG: 0 = SINGLE ENDED INPUT (DIGITAL LEAD MODE OR ELECTRODE MODE); 1 = DIFFERENTIAL IN PUT (ANALOG LEAD MODE).
3REGISTER CMREFCTL, BIT CEREFEN: 0 = CE DISABLED; 1 = CE ENABLED.
4WILSON CENTRAL TERMINAL (WCT) = (RA + LA + LL)/3, THIS IS A DIGITALLY CALCULATED WCT BASED ON THE RA, LA, LL MEASUREMENTS.

Figure 59. Electrode and Lead Configurations, Digital Lead Mode

Rev. C | Page 32 of 85
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2
VCM = RA
CM_OUT/WCT
COMMON-
MODE AMP

ECG1_LA + LEAD I
AMP ADC
–

ECG2_LL + LEAD II
AMP ADC
–

ECG3_RA = V3 + DIGITAL DOMAIN V3’

AMP ADC CALCULATIONS
–

ECG4_V1 + V1’
AMP ADC
–

ECG5_V2 + V2’
AMP ADC
–

CM_IN = RA
COMMON
ELECTRODE CE IN

0x0A 0x01 0x05

MODE COMMENT WORD1 WORD2 WORD3 WORD4 WORD5 [4]1 [10]2 [8]3

COMMON COMMON LEAD I LEAD II V3’ V1’ V2’ 0 0 1

ELECTRODE A ELECTRODE (CE)
LEADS (HERE RA (LA − RA) (LL − RA) (V3 – RA) − (LA − RA) − (LL − RA) (V1 − RA) − (LA − RA) + (LL − RA) (V2 − RA) − (LA − RA) + (LL − RA)
ELECTRODE IS
CONNECTED TO THE 3 3 3
CE ELECTRODE
(CM_IN) AND V3 IS ON
ECG3 INPUT)

09660-017
1REGISTER FRMCTL, BIT DATAFMT: 0 = LEAD/VECTOR MODE; 1 = ELECTRODE MODE.
2REGISTER ECGCTL, BIT CHCONFIG: 0 = SINGLE ENDED INPUT (DIGITAL LEAD MODE OR ELECTRODE MODE); 1 = DIFFERENTIAL IN PUT (ANALOG LEAD MODE).
3REGISTER CMREFCTL, BIT CEREFEN: 0 = CE DISABLED; 1 = CE ENABLED.

Figure 60. Electrode and Lead Configurations, Common Electrode A

VCM = ( LA+ LL + RA + V1)/
4 IN THIS CASE
CM_OUT/WCT VCM COMMON MODE
CAN BE ANY COMBINATION
COMMON- OF ELECTRODES
MODE AMP

ECG1_LA + LA – VCM
AMP ADC
–

ECG 2_LL + LL – VCM

AMP ADC
–

ECG3_RA + RA – VCM
AMP ADC
–

ECG4_V1 + V1 – VCM
AMP ADC
–

ECG5_V2 + V2 – VCM
AMP ADC
–

CM_IN
FOR EXAMPLE, RA
COMMON
ELECTRODE CE IN

0x0A 0x01 0x05

MODE COMMENT WORD1 WORD2 WORD3 WORD4 WORD5 [4]1 [10]2 [8]3

SINGLE-ENDED SINGLE-ENDED LA − VCM LL − VCM RA − VCM V1 − VCM V2 − VCM 1 0 0

INPUT INPUT ELECTRODE
ELECTRODE RELATIVE TO VCM
09660-118

1REGISTER FRMCTL, BIT DATAFMT: 0 = LEAD/VECTOR MODE; 1 = ELECTRODE MODE.

2REGISTER ECGCTL, BIT CHCONFIG: 0 = SINGLE ENDED INPUT (DIGITAL LEAD MODE OR ELECTRODE MODE); 1 = DIFFERENTIAL IN PUT (ANALOG LEAD MODE).
3REGISTER CMREFCTL, BIT CEREFEN: 0 = CE DISABLED; 1 = CE ENABLED.

Figure 61. Electrode and Lead Configurations, Single-Ended Input Electrode

Rev. C | Page 33 of 85
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet
VCM = CE = RA
CM_OUT/WCT
COMMON-
MODE AMP

ECG1_LA + LA – RA
AMP ADC
–

ECG2_LL + LL – RA
AMP ADC
–

ECG3_RA = V3 + V3 – RA
AMP ADC
–

ECG4_V1 + V1 – RA
AMP ADC
–

ECG5_V2 + V2 – RA
AMP ADC
–

CM_IN = RA
COMMON
ELECTRODE CE IN

0x0A 0x01 0x05

MODE COMMENT WORD1 WORD2 WORD3 WORD4 WORD5 [4]1 [10]2 [8]3

COMMON LEADS FORMED LA − CE LL − CE V1 − CE V2 − CE V3 − CE 1 0 1

ELECTRODE B RELATIVE TO A
COMMON
ELECTRODE (CE)

09660-119
1REGISTER FRMCTL, BIT DATAFMT: 0 = LEAD/VECTOR MODE; 1 = ELECTRODE MODE.
2REGISTER ECGCTL, BIT CHCONFIG: 0 = SINGLE ENDED INPUT (DIGITAL LEAD MODE OR ELECTRODE MODE); 1 = DIFFERENTIAL IN PUT (ANALOG LEAD MODE).
3REGISTER CMREFCTL, BIT CEREFEN: 0 = CE DISABLED; 1 = CE ENABLED.

Figure 62. Electrode and Lead Configurations, Common Electrode B

Rev. C | Page 34 of 85
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2
DEFIBRILLATOR PROTECTION ESIS FILTERING
The ADAS1000/ADAS1000-1/ADAS1000-2 do not include The ADAS1000/ADAS1000-1/ADAS1000-2 do not include
defibrillation protection on chip. Any defibrillation protection electrosurgical interference suppression (ESIS) protection on
required by the application requires external components. chip. Any ESIS protection required by the application requires
Figure 63 and Figure 64 show examples of external defibrillator external components.
protection, which is required on each ECG channel, in
ECG PATH INPUT MULTIPLEXING
the RLD path and in the CM_IN path if using the CE input
mode. Note that, in both cases, the total ECG path resistance is As shown in Figure 65, signal paths for numerous functions are
assumed to be 5 kΩ. The 22 MΩ resistors shown connected to provided on each ECG channel (except respiration, which only
RLD are optional and used to provide a safe termination voltage connect to the ECG1_LA, ECG2_LL, and ECG3_RA pins).
for an open ECG electrode; they may be larger in value. Note Note that the channel enable switch occurs after the RLD
that, if using these resistors, the dc lead-off feature works best amplifier connection, thus allowing the RLD to be connected
with the highest current setting. (re-directed into any one of the ECG paths). The CM_IN path
is treated the same as the ECG signals.

PATIENT
CABLE 4kΩ 500Ω 500Ω
ELECTRODE ECG1
AVDD
ARGON/NEON 22MΩ1
BULB ADAS1000/
RLD ADAS1000-1/
SP724
PATIENT 22MΩ1 ADAS1000-2
CABLE 4kΩ 500Ω 500Ω
ELECTRODE ECG2
AVDD
ARGON/NEON
BULB

09660-018
SP724
1OPTIONAL.

Figure 63. Possible Defibrillation Protection on ECG Paths Using Neon Bulbs
PATIENT
CABLE 4.5kΩ 500Ω
ELECTRODE ECG1
AVDD
22MΩ1
SP7242 ADAS1000/
RLD
ADAS1000-1/
ADAS1000-2
PATIENT 22MΩ1
CABLE 4.5kΩ 500Ω
ELECTRODE ECG2
AVDD

SP7242
09660-019

1OPTIONAL.
2TWO LITTELFUSESP724 CHANNELS PER ELECTRODE MAY PROVIDE
BEST PROTECTION.

Figure 64. Possible Defibrillation Protection on ECG Paths Using Diode Protection

ACLO
CURRENT
RESPIRATION DCLO
RLD AMP INPUT CURRENT 11.3pF CALDAC

INPUT AMPLIFIER
ECG PIN +
CHANNEL –
ENABLE TO
FILTERING
MUX FOR LEAD CONFIG,
ANALOG COMMON ELECTRODE
LEAD
(RA/LA/LL)
+
1.3V VCM_REF VCM
–

FROM CM
09660-020

AVERAGING
TO CM
ADAS1000 AVERAGING

Figure 65. Typical ECG Channel Input Multiplexing

Rev. C | Page 35 of 85
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet
COMMON-MODE SELECTION AND AVERAGING common-mode block. If the physical connection to each
electrode is buffered, these buffers are omitted for clarity.
The common-mode signal can be derived from any combina-
tion of one or more electrode channel inputs, the fixed internal There are several restrictions on the use of the switches:
common-mode voltage reference, VCM_REF, or an external  If SW1 is closed, SW7 must be open.
source connected to the CM_IN pin. One use of the latter  If SW1 is open, at least one electrode switch (SW2 to SW7)
arrangement is in gang mode where the master device creates must be closed.
the Wilson central terminal for the slave device or devices. The  SW7 can be closed only when SW2 to SW6 are open, so
fixed reference option is useful when measuring the calibration that the 1.3 V VCM_REF gets summed in only when all
DAC test tone signals or while attaching electrodes to the patient, ECG channels are disconnected.
where it allows a usable signal to be obtained from just two
electrodes. The CM_OUT output is not intended to supply current or drive
resistive loads, and its accuracy is degraded if it is used to drive
The flexible common-mode generation allows complete
anything other than the slave ADAS1000-2 devices. An external
user control over the contributing channels. It is similar to,
buffer is required if there is any loading on the CM_OUT pin.
but independent of, circuitry that creates the right leg
drive (RLD) signal. Figure 66 shows a simplified version of the

ADAS1000
CM_IN
SW1

+ VCM
SW2 CM_OUT
ECG1_LA –
SW3
ECG2_LL
SW4
ECG3_RA
SW5
ECG4_V1
SW6
ECG5_V2
SW7
VCM_REF = 1.3V
09660-021

(WHEN SELECTED, IT GETS

SUMMED IN ON EACH ECG CHANNEL)

Figure 66. Common-Mode Generation Block

Table 11. Truth Table for Common-Mode Selection

ECGCTL
Address
0x011 CMREFCTL Address 0x052
PWREN DRVCM EXTCM LACM LLCM RACM V1CM V2CM On Switch Description
0 X X X X X X X Powered down, paths disconnected
1 X 0 0 0 0 0 0 SW7 Internal VCM_REF = 1.3 V is selected
1 0 0 1 0 0 0 0 SW2 Internal CM selection: LA contributes to VCM
1 0 0 1 1 0 0 0 SW2, SW3 Internal CM selection: LA and LL contribute to VCM
1 0 0 1 1 1 0 0 SW2, SW3, Internal CM selection: LA, LL, and RA contribute to
SW4 VCM (WCT)
. . . . . . . . . .
1 X 1 X X X X X SW1 External VCM selected
1
See Table 28.
2
See Table 32.

Rev. C | Page 36 of 85
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2
WILSON CENTRAL TERMINAL (WCT) compensation proves necessary, while in others, lag compensation
is more appropriate. The summing junction of the RLD amplifier is
The flexibility of the common-mode selection averaging allows brought out to a package pin (RLD_SJ) to facilitate compensation.
the user to achieve a Wilson central terminal voltage from the
ECG1_LA, ECG2_LL, ECG3_RA electrodes. The short circuit current capability of the RLD amplifier
exceeds regulatory limits. A patient protection resistor is
RIGHT LEG DRIVE/REFERENCE DRIVE required to achieve compliance.
The right leg drive amplifier or reference amplifier is used as Within the RLD block, there is lead-off comparator circuitry
part of a feedback loop to force the patient’s common-mode that monitors the RLD amplifier output to determine whether
voltage close to the internal 1.3 V reference level (VCM_REF) the patient feedback loop is closed. An open-loop condition,
of the ADAS1000/ADAS1000-1/ADAS1000-2. This centers all typically the result of the right leg electrode (RLD_OUT) becoming
the electrode inputs relative to the input span, providing detached, tends to drive the output of the amplifier low. This type
maximum input dynamic range. It also helps to reject noise of fault is flagged in the header word (see Table 54), allowing the
and interference from external sources such as fluorescent system software to take action by notifying the user, redirecting the
lights or other patient-connected instruments, and absorbs reference drive to another electrode via the internal switches of
the dc or ac lead-off currents injected on the ECG electrodes. the ADAS1000/ADAS1000-1/ADAS1000-2, or both. The
The RLD amplifier can be used in a variety of ways as shown in detection circuitry is local to the RLD amplifier and remains
Figure 67. Its input can be taken from the CM_OUT signal functional with a redirected reference drive. Table 32 provides
using an external resistor. Alternatively, some or all of the details on reference drive redirection.
electrode signals can be combined using the internal switches. While reference drive redirection can be useful in the event that
The DC gain of the RLD amplifier is set by the ratio of the external the right leg electrode cannot be reattached, some precautions
feedback resistor (RFB) to the effective input resistor, which can be must be observed. Most important is the need for a patient
set by an external resistor, or alternatively, a function of the number protection resistor. Because this is an external resistor, it does
of selected electrodes as configured in the CMREFCTL register (see not follow the redirected reference drive; some provision for
Table 32). In a typical case, using the internal resistors for RIN, all continued patient protection is needed external to the
active electrodes are used to derive the right leg drive, resulting in a ADAS1000/ADAS1000-1/ADAS1000-2. Any additional
2 kΩ effective input resistor. Achieving a typical dc gain of 40 dB resistance in the ECG paths certainly interferes with respiration
thus requires a 200 kΩ feedback resistor. measurement and may also result in an increase in noise and
The dynamics and stability of the RLD loop depend on the chosen decrease in CMRR.
dc gain and the resistance and capacitance of the patient cabling. The RLD amplifier is designed to stably drive a maximum
In general, loop compensation using external components is capacitance of 5 nF based on the gain configuration (see
required, and must be determined experimentally for any given Figure 67) and assuming a 330 kΩ patient protection resistor.
instrument design and cable set. In some cases, adding lead
EXTERNALLY SUPPLIED COMPONENTS
TO SET RLD LOOP GAIN CZ 100kΩ
2nF RZ
40kΩ 4MΩ
RIN* RFB*

RLD_SJ RLD_OUT
CM_OUT/WCT

ADAS1000 –
SW1 10kΩ
ELECTRODE LA +
SW2 10kΩ
ELECTRODE LL
SW3 10kΩ
ELECTRODE RA
SW4 10kΩ
ELECTRODE V1
SW5 10kΩ
ELECTRODE V2
SW6
CM_IN OR 10kΩ
CM BUFFER OUT
VCM_REF
(1.3V)
RLD_INT_REDIRECT

*EXTERNAL RESISTOR RIN IS OPTIONAL. IF DRIVING RLD FROM

THE ELECTRODE PATHS, THEN THE SERIES RESISTANCE WILL
CONTRIBUTE TO THE RIN IMPEDANCE. WHERE SW1 TO SW5
09660-022

ARE CLOSED, RIN = 2kΩ. RFB SHOULD BE CHOSEN

ACCORDINGLY FOR DESIRED RLD LOOP GAIN.

Figure 67. Right Leg Drive—Possible External Component Configuration

Rev. C | Page 37 of 85
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet
CALIBRATION DAC In a typical ECG configuration, the electrodes RA, LA, and LL
are used to generate a common mode of Wilson Central
Within the ADAS1000/ADAS1000-1, there are a number of Terminal (WCT). If one of these electrodes is off, this affects the
calibration features. WCT signal and any lead measurements that it contributes to.
The 10-bit calibration DAC can be used to correct channel gain As a result, the ECG measurements on these signals are
errors (to ensure channel matching) or to provide several test expected to degrade. The user has full control over the common
tones. The options are as follows: mode amplifier and can adjust the common-mode
• DC voltage output (range: 0.3 V to 2.7 V). The DAC configuration to remove that electrode from the common-mode
transfer function for dc voltage output is generation. In this way, the user can continue to make
measurements on the remaining connected leads.
 code 
0.3 V +  2.4 V× 10 
 (2 − 1)  DC Lead-Off Detection
• 1 mV p-p sine wave of 10 Hz or 150 Hz This method injects a small programmable dc current into each
• 1 mV 1 Hz square wave input electrode. When an electrode is properly connected, the
current flows into the right leg (RLD_OUT) and produces a
Internal switching allows the calibration DAC signals to be minimal voltage shift. If an electrode is off, the current charges
routed to the input of each ECG channel (see Figure 65). the capacitance of that pin, causing the voltage at the pin to float
Alternatively, it can be driven out from the CAL_DAC_IO pin, positive and create a large voltage change that is detected by the
enabling measurement and correction for external error comparators in each channel. These comparators use fixed,
sources in the entire ECG signal chain and/or for use as an gain-independent upper and lower threshold voltages of 2.4 V
input to the ADAS1000-2 companion chip calibration input. and 0.2 V, respectively. If the input exceeds either of these levels,
To ensure a successful update of the calibration DAC (see the lead-off flag is raised. The lower threshold is included in the
Table 36), the host controller must issue four additional event that something pulls the electrode down to ground.
SCLK cycles after writing the new calibration DAC register The dc lead-off detection current can be programmed via the
word. serial interface. Typical currents range from 10 nA to 70 nA in
GAIN CALIBRATION 10 nA steps. All input pins (RA, LA, LL, V1, V2, and CM_IN)
use identical dc lead-off detection circuitry.
The gain for each ECG channel can be adjusted to correct for
gain mismatches between channels. Factory trimmed gain Detecting if the right-leg electrode has fallen off is necessarily
correction coefficients are stored in nonvolatile memory different as RLD_OUT is a low impedance amplifier output. A
on-chip for GAIN 0, GAIN 1, and GAIN 2; there is no factory pair of fixed threshold comparators monitor the output voltage
calibration for GAIN 3. The default gain values can be to detect amplifier saturation that would indicate a lead-off
overwritten by user gain correction coefficients, which are condition. This information is available in the DCLEAD-OFF
stored in volatile memory and available by addressing the register (Register 0x1E) along with the lead-off status of all the
appropriate gain control registers (see Table 51). The gain input pins.
calibration applies to the ECG data available on the standard The propagation delay for detecting a dc lead-off event depends
interface and applies to all data rates. on the cable capacitance and the programmed current. It is
LEAD-OFF DETECTION approximately

An ECG system must be able to detect if an electrode is no Delay = Voltage × Cable Capacitance/Programmed Current
longer connected to the patient. The ADAS1000/ADAS1000-1/ For example:
ADAS1000-2 support two methods of lead-off detection, ac
Delay = 1.2 V × (200 pF/70 nA) = 3.43 ms
lead-off detection and dc lead-off detection. The two systems
are independent and can be used singly or together under the DC Lead-Off and High Gains
control of the serial interface (see Table 29). Using dc lead-off at high gains can result in failure of the circuit
A lead-off event sets a flag in the frame header word (see Table 54). to flag a lead-off condition. The chopping nature of the input
Identification of which electrode is off is available as part of the amplifier stage contributes to this situation. When the electrode
data frame or as a register read from the lead-off status register is off, the electrode is pulled up; however, in this gain setting,
(Register LOFF, see Table 47). In the case of ac lead-off, infor- the first stage amplifier goes into saturation before the input
mation about the amplitude of the lead-off signal or signals can signal crosses the dc lead-off (DCLO) upper threshold, resulting
be read back through the serial interface (see Table 52). in no lead-off flag. This affects the gain setting GAIN 3 (4.2)
and partially GAIN 2 (2.8).
Increasing the AVDD voltage raises the voltage at which the input
amplifiers saturate, allowing the off electrode voltage to rise high
enough to trip the DCLO comparator (fixed upper threshold of
Rev. C | Page 38 of 85
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2
2.4 V). The ADAS1000 operates over a voltage range of 3.15 V to these programmed thresholds voltage vary with the ECG channel
5.5 V. If using GAIN 2/GAIN 3 and dc lead-off, an increased gain. The threshold voltages are not affected by the current level
AVDD supply voltage (minimum 3.6 V) allows dc lead-off to flag that is programmed. All active channels use the same detection
correctly at higher gains. thresholds.
When using dc lead-off, it is recommended to also use the ADC A properly connected electrode has a very small signal as the drive
out of range feature because this function provides additional current flows into the right leg (RL), whereas a disconnected
information (see the ADC Out of Range section). electrode has a larger signal as determined by a capacitive voltage
DC Lead-Off Debounce Timer divider (source and cable capacitance).

The DCLO circuit has a debounce timer that uses an 8-bit If the signal measured is larger than the upper threshold, then the
saturating up/down counter clocked at 2 kHz. The debounce timer impedance is high, so a wire is probably off. Selecting the
counts up when one of the analog comparator trip signals an open appropriate threshold setting depends on the particular cable/
electrode. Otherwise, the debounce timer counts down. The output electrode/protection scheme, as these parameters are typically
of the timer only flags a lead-off event when the output reaches unique for the specific use case. This can take the form of starting
(and saturates at) all ones. The total amount of time that is required with a high threshold and ratcheting it down until a lead-off is
from the time an open electrode is detected internally until the user detected, then increasing the threshold by some safety margin. This
receives a signal is 125 ms. After an open electrode is detected and gives simple dynamic thresholding that automatically compensates
resolved, the debounce does not signal an on lead condition until for many of the circuit variables.
the debounce timer counts down to (and saturates at) all zeros. The lower threshold is added for cases where only ac lead-off is in
The debounce time is fixed. The debounce function is always use and for situations where an electrode cable has been off for a
enabled. long time. In this case, the dc voltage has saturated to a rail, or the
electrode cable has somehow shorted to a supply. In either case,
AC LEAD-OFF DETECTION there is no ac signal present, yet the electrode may not be
The alternative method of sensing if the electrodes are connected to connected. The lower threshold checks for a minimum signal level.
the patient is based on injecting ac currents into each channel and In addition to the lead-off flag, the user can also read back the
measuring the amplitudes of the resulting voltages. The system uses resulting voltage measurement available on a per channel basis. The
a fixed carrier frequency at 2.039 kHz, which is high enough to be measured amplitude for each of the individual channels is available
removed by the ADAS1000/ADAS1000-1/ADAS1000-2 on-chip in Register 0x31 through Register 0x35 (LOAMxx registers, see
digital filters without introducing phase or amplitude artifacts into Table 52). The ac lead-off (ACLO) measurement depends on the
the ECG signal. operating mode. If the device is configured for electrode mode, the
AC LO amplitude result for the measured electrode is returned. If the
DAC
device is configured for lead mode, the result is for a pair or
combination of electrodes that contributes to the channel. Channel
gain also applies to the ACLO result because channel gain is applied
2.039kHz to the ECG measurement. Higher channel gains result in higher
11kΩ 11kΩ 11kΩ 11kΩ 11kΩ 11kΩ 12.5nA TO
codes in the ac lead-off results.
09660-166

100nA rms

LA LL RA V1 V2 CM When an electrode is completely disconnected (and no dc lead-off

Figure 68. Simplified AC Lead-Off Configuration is enabled), the ECG input may float and, depending on leakage
currents, the ECG input may float towards either supply rail. If the
The amplitude of the signal is nominally 2 V p-p and is centered on
ECG input floats to the supply rail, the ECG channel saturates and
1.3 V relative to the chip AGND level. It is ac-coupled into each
the ACLO amplitude result then returns 0 or close to 0, appearing
electrode. The polarity of the ac lead-off signal can be configured
as though the electrode is connected. Therefore, in addition to
on a per-electrode basis through Bits[23:18] of the
monitoring the ACLO flag, it is recommended that the user also
LOFFCTL register (see Table 29). All electrodes can be driven in
monitors the ADC out of range flags. It is recommended that the
phase, and some can be driven with reversed polarity to minimize
electrode is considered off when either the ADC is flagging out of
the total injected ac current. Drive amplitude is also programmable.
range or the ac lead-off flag is set.
AC lead-off detection functions only on the input pins (LA, LL,
RA, V1, V2, and CM_IN) and is not supported for the RLD_OUT The ESIS protection network and defibrillation protection load the
pin. circuit and have a direct effect on the sensitivity of the ac lead-off
circuit.
The resulting analog input signal applied to the ECG channels is
I/Q demodulated and amplitude detected. The resulting amplitude The propagation delay for detecting an ac lead-off event is <10 ms.
is low pass filtered and sent to the digital threshold detectors. Note that the ac lead-off function is disabled when the calibration
AC lead-off detection offers user programmable dedicated upper DAC is enabled.
and lower threshold voltages (see Table 39 and Table 40). Note that
Rev. C | Page 39 of 85
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet
ACLO and Common-Mode Configuration user is required to further process it to extract the envelope and
One electrode having an off or poor connection affects the ac perform the peak detection needed to establish breathing (or lack
lead-off results of the other channels to which the electrode thereof).
contributes (directly or via RLD/common mode). In this Respiration measurement is available on one of the leads (Lead I,
situation, it is recommended that the user identifies and Lead II, or Lead III) or on an external path via a pair of dedicated
removes the electrode from the RLD contribution and the pins (EXT_RESP_LA, EXT_RESP_RA, or EXT_RESP_LL).
common mode contribution. This procedure requires careful Only one lead measurement can be made at one time. The
detection threshold setting and intelligence in the management respiration measurement path is not suited for use as additional
of the electrode off information to determine which electrode ECG measurements because the internal configuration and
degraded or fell off. demodulation do not align with an ECG measurement; however,
ADC Out of Range the EXT_RESP_LA, EXT_RESP_RA, or EXT_RESP_LL paths
can be multiplexed into one of the ECG ADC paths, if required,
When multiple leads are off, the input amplifiers may run into
as discussed in the Extend Switch On Respiration Paths section.
saturation. This results in the ADC outputting out of range data
with no carrier to the leads off algorithm. The ac lead-off algorithm The respiration signal processing path is not reconfigurable for
then reports little or no ac amplitude. The ADAS1000 contains ECG measurements, as it is specifically designed for the respiration
flags to indicate if the ADC data is out of range, indicating a hard signal measurement.
electrode off state. There are programmable overrange and under-
Table 12. Maximum Allowable Cable and Thoracic Loading
range thresholds that can be seen in the LOFFUTH and LOFFLTH
Cable Resistance Cable Capacitance
registers (see Table 39 and Table 40, respectively). The ADC out
R < 1 kΩ C < 1200 pF
of range flag is contained in the header word (see Table 54).
1 kΩ < R < 2.5 kΩ C < 400 pF
SHIELD DRIVER 2.5 kΩ < R < 5 kΩ C < 200 pF
The shield drive amplifier is a unity gain amplifier. Its purpose RTHORACIC < 2 kΩ
is to drive the shield of the ECG cables. For power consumption
Internal Respiration Capacitors
purposes, it can be disabled if not in use. Note that the
SHIELD pin is shared with the respiration pin function, where The internal respiration function uses an internal RC network
it can be muxed to be one of the pins for external capacitor (5 kΩ/100 pF), and this circuit is capable of 200 mΩ resolution
connection. If the pin is being used for the respiration feature, (with up to 5 kΩ total path and cable impedance). The current
the shield function is not available. In this case, if the is ac-coupled onto the same pins that the measurement is sensed
application requires a shield drive, an external amplifier back on. Figure 69 shows the measurement on Lead I, but,
connected to the CM_OUT pin can be used. similarly, the measurement can be configured to measure on
either Lead II or Lead III. The internal capacitor mode requires
RESPIRATION (ADAS1000 MODEL ONLY) no external capacitors and produces currents of ~64 µA p-p
The respiration measurement is performed by driving a high amplitude when configured for maximum amplitude setting
frequency (programmable from 46.5 kHz to 64 kHz) differential (±1V) through the RESPCTRL register (see Table 30).
current into two electrodes; the resulting impedance variation
External Respiration Path
caused by breathing causes the differential voltage to vary at the
respiration rate. The signal is ac-coupled onto the patient. The The EXT_RESP_xx pins are provided for use either with the
acquired signal is AM, with a carrier at the driving frequency ECG electrode cables or, alternatively, with a dedicated external
and a shallow modulation envelope at the respiration frequency. sensor independent of the ECG electrode path. Additionally, the
The modulation depth is greatly reduced by the resistance of the EXT_RESP_xx pins are provided so the user can measure the
customer-supplied RFI and ESIS protection filters, in addition respiration signal at the patient side of any input filtering on the
to the impedance of the cable and the electrode to skin interface front end. In this case, the user must continue to take precautions
(see Table 12). The goal is to measure small ohm variation to sub to protect the EXT_RESP_xx pins from any signals applied that
ohm resolution in the presence of large series resistance. The are in excess of the operating voltage range (for example, ESIS
circuit itself consists of a respiration DAC that drives the ac- or defibrillator signals).
coupled current at a programmable frequency onto the chosen
pair of electrodes. The resulting variation in voltage is amplified,
filtered, and synchronously demodulated in the digital domain;
the result is a digital signal that represents the total thoracic or
respiration impedance, including cable and electrode
contributions. While it is heavily low-pass filtered on-chip, the

Rev. C | Page 40 of 85
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2
±1V
46.5kHz TO RESPIRATION DAC
64kHz DRIVE + ADAS1000

5kΩ
100pF
SWITCH
RESISTANCE = 1kΩ

CABLE AND ELECTRODE

IMPEDANCE < 5kΩ RESPIRATION
MEASURE
ECG1_LA
LA CABLE FILTER
EXT_RESP_LA
IN-AMP AND
ANTI-ALIASING OVERSAMPLED
ECG2_LL HPF
LL CABLE FILTER SAR MAGNITUDE
EXT_RESP_LL ADC AND
LPF PHASE
ECG3_RA
RA CABLE FILTER fc=150kHz fc=10kHz 7Hz
EXT_RESP_RA

SWITCH
RESISTANCE = 1kΩ
100pF
5kΩ

46.5kHz TO RESPIRATION DAC

09660-023
64kHz DRIVE–
±1V

Figure 69. Simplified Respiration Block Diagram

External Respiration Capacitors one lead (at one time); therefore, only one pair of external
If necessary, the ADAS1000 allows the user to connect external respiration paths (and external capacitors) is required.
capacitors into the respiration circuit to achieve higher resolution If required, further improvements in respiration performance may
(<200 mΩ). This level of resolution requires that the cable be possible with the use of an instrumentation amplifier and op
impedance be ≤1 kΩ. The diagram in Figure 70 shows the amp external to the ADAS1000. The instrumentation amplifier
connections at RESPDAC_xx paths for the extended respiration must have sufficiently low noise performance to meet the target
configuration. Again, the EXT_RESP_xx paths can be connected at performance levels. This mode uses the external capacitor mode
the patient side of any filtering circuit; however, the user must configuration and is shown in Figure 71. Bit 14 of the
provide protection for these pins. While this external capacitor RESPCTL register (Address 0x03; see Table 30) allows the user to
mode requires external components, it can deliver a larger signal- bypass the on-chip amplifier when using an external
to-noise ratio. Note again that respiration can be measured on only instrumentation amplifier.

Rev. C | Page 41 of 85
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet
±1V
46.5kHz TO RESPIRATION DAC
64kHz DRIVE + ADAS1000
1nF TO 10nF
RESPDAC_LA 1kΩ
RESPDAC_LL
1kΩ
5kΩ
100pF
MUTUALLY
EXCLUSIVE

CABLE AND ELECTRODE

IMPEDANCE < 1kΩ RESPIRATION
MEASURE
ECG1_LA
LA CABLE FILTER
EXT_RESP_LA
IN-AMP AND
ANTI-ALIASING OVERSAMPLED
ECG2_LL HPF
LL CABLE FILTER SAR MAGNITUDE
EXT_RESP_LL ADC AND
LPF PHASE
ECG3_RA
RA CABLE FILTER fc=150kHz fc=10kHz 7Hz
EXT_RESP_RA

MUTUALLY
EXCLUSIVE 100pF

5kΩ
1nF TO 10nF
RESPDAC_RA 1kΩ
RESPIRATION DAC
46.5kHz TO DRIVE –

09660-024
64kHz
±1V

Figure 70. Respiration Measurement Using External Capacitor

Rev. C | Page 42 of 85
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2
46.5kHz TO ADAS1000
64kHz
1nF TO 10nF RESPDAC_LA 1kΩ 100Ω
±1V
RESPIRATION DAC
DRIVE + ve
CABLE AND ELECTRODE
IMPEDANCE < 1kΩ RESPIRATION
MEASURE
LA CABLE EXT_RESP_LA IN-AMP AND
ANTI-ALIASING OVERSAMPLED
10kΩ HPF
RA CABLE MAGNITUDE
SAR
ADC AND
10kΩ LPF PHASE
fc=150kHz fc=10kHz 7Hz
EXT_RESP_RA
1/2 OF AD8606

10kΩ REFOUT = 1.8V

46.5kHz TO
0.9V 64kHz
10kΩ 1nF TO 10nF RESPDAC_RA 1kΩ 100Ω
±1V

09660-025
1/2 OF AD8606 RESPIRATION DAC
DRIVE – ve

Figure 71. Respiration Using External Capacitor and External Amplifiers

Respiration Carrier Frequency Table 14. Control of Respiration Carrier Frequency

The frequency of the respiration carrier is programmable and Available on GPIO3
can be varied through the RESPCTL register (Address 0x03, see RESPALT- RESPEXT- RESP- Respiration Carrier
Table 30). The status of the HP bit in the ECGCTL register also FREQ1 SYNC1 HP2 FREQ1 Frequency on GPIO3
has an influence on the carrier frequency as shown in Table 13. 0 1 X3 XX3 64
1 1 1 00 64
Table 13. Control of Respiration Carrier Frequencies. 1 1 1 01 56
Respiration 1 1 1 10 51.2
RESP- Carrier
1 1 1 11 46.5
RESPALTFREQ1 RESPEXTSYNC1 HP2 FREQ1 Frequency
1 1 0 00 32
0 X3 1 00 56
1 1 0 01 28
0 0 1 01 54
1 1 0 10 25.5
0 0 1 10 52
1 1 0 11 23
0 0 1 11 50
0 0 0 00 56 1
Control bits from RESPCTL (Register 0x03).
0 0 0 01 54
2
Control bit from ECGCTL (Register 0x01).
3
X means don’t care.
0 0 0 10 52
0 0 0 11 50 EVALUATING RESPIRATION PERFORMANCE
1 0 1 00 64 ECG simulators offer a convenient means of studying the
1 0 1 01 56.9 performance of the ADAS1000. While many simulators offer a
1 0 1 10 51.2 variable-resistance respiration capability, care must be taken
1 0 1 11 46.5 when using this feature.
1 X 0 00 32 Some simulators use electrically programmable resistors, often
1 X 0 01 28 referred to as digiPOTs, to create the time-varying resistance to
1 X 0 10 25.5 be measured by the respiration function. The capacitances at the
1 X 0 11 23 terminals of the digiPOT are often unequal and code-dependent,
1
Control bits from RESPCTL (Register 0x03). and these unbalanced capacitances can give rise to unexpectedly
2
Control bit from ECGCTL (Register 0x01). large or small results on different leads for the same programmed
3
X means don’t care.
resistance variation. Best results are obtained with a purpose-
In applications where an external signal generator is used to built fixture that carefully balances the capacitance presented to
develop a respiration carrier signal, that external signal source each ECG electrode.
can be synchronized to the internal carrier using the signal
available on GPIO3 when Bit 7, RESPEXTSEL, is enabled in
the respiration control register (see Table 30).

Rev. C | Page 43 of 85
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet
EXTEND SWITCH ON RESPIRATION PATHS
There is additional multiplexing on the external respiration inputs
to allow them to serve as additional electrode inputs to the existing
five ECG ADC channels. This approach allows a user to configure
eight electrode inputs; however, it is not intended as a true
8-channel/12-lead solution. Time overheads are required to
reconfigure the multiplexer arrangement using the serial interface
in addition to filter the latency as described in Table 16.
The user has full control over the SW1/SW2/SW3 configuration
as outlined in Table 50.
SW1a
TO ECG1_LA CHANNEL
SW2a
SW3a

SW1b
TO ECG2_LL CHANNEL
SW2b
SW3b

SW1c
TO ECG3_RA CHANNEL
SW2c
SW3c

SW1d
TO ECG4_V1 CHANNEL
SW2d
SW3d

SW1e
TO ECG5_V2 CHANNEL
SW2e
SW3e

TO RESPIRATION CIRCUITRY
09660-032

EXT_RESP_RA EXT_RESP_LA
EXT_RESP_LL

Figure 72. Alternative Use of the Respiration Paths

Rev. C | Page 44 of 85
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2
PACING ARTIFACT DETECTION FUNCTION The on-chip filtering contributes some delay to the pace signal
(ADAS1000 ONLY) (see the Pace Latency section).
The pacing artifact validation function qualifies potential Choice of Leads
pacing artifacts and measures the width and amplitude of valid Three identical and independent state machines are available
pulses. These parameters are stored in and available from any of and can be configured to run on up to three of four possible
the pace data registers (Address 0x1A, and Address 0x3A to leads (Lead I, Lead II, Lead III, and aVF) for pacing artifact
Address 0x3C). This function runs in parallel with the ECG detection. Any necessary lead calculations are performed
channels. Digital detection is performed using a state machine internally and are independent of ECG channel settings for
operating on the 128 kHz 16-bit data from the ECG decimation output data rate, low-pass filter cutoff, and mode (electrode,
chain. The main ECG signals are further decimated before analog lead, common electrode). These calculations take into
appearing in the 2 kHz output stream so that detected pace account the available front-end configurations as detailed in
signals are not perfectly time-aligned with fully-filtered ECG Table 15.
data. This time difference is deterministic and can be
The pace detection algorithm searches for pulses by analyzing
compensated for.
samples in the 128 kHz ECG data stream. The algorithm
The pacing artifact validation function can detect and searches for a leading edge, a peak, and a trailing edge as
measure pacing artifacts with widths from 100 μs to 2 ms defined by values in the PACEEDGETH, PACEAMPTH, and
and with amplitudes of <400 μV to >1000 mV. Its filters are PACELVLTH registers, along with fixed width qualifiers. The
designed to reject heartbeat, noise, and minute ventilation post-reset default register values can be overwritten via the SPI
pulses. The flowchart for the pace detection algorithm is bus, and different values can be used for each of the three pace
shown in Figure 74. detection state machines.
The ADAS1000 pace algorithm can operate with the ac lead-off Some users may not want to use three pace leads for detection.
and respiration impedance measurement circuitry enabled. In this case, Lead II is the vector of choice, because this lead is
Once a valid pace is detected in the assigned leads, the pace- likely to display the best pacing artifact. The other two pace
detected flags appear in the header word (see Table 54) at the instances can be disabled if not in use.
start of the packet of ECG words. These bits indicate that a pace The first step in pace detection is to search the data stream for a
is qualified. Further information on height and width of pace is valid leading edge. Once a candidate edge is detected, the algorithm
available by reading the contents of Address 0x1A begins searching for a second, opposite-polarity edge that meets
(PACEDATA register, see Table 44). This word can be included with pulse width criteria and passes the (optional) noise filters.
in the ECG data packet/frame as dictated by the frame control Only those pulses meeting all the criteria are flagged as valid pace
register (see Table 37). The data available in the PACEDATA pulses. Detection of a valid pace pulse sets the flag or flags in the
register is limited to seven bits total for width and height frame header register and stores amplitude and width information
information; therefore, if more resolution is required on the in the PACEDATA register (Address 0x1A; see Table 44). The pace
pace height and width, this is available by issuing read algorithm looks for a negative or positive pulse.
commands of the PACExDATA registers (Address 0x3A to
Address 0x3C) as shown in Table 53.

Table 15. Pace Lead Calculation

0x04 [8:3] 3
00 01 10 11
Lead I Lead II Lead III aVF
0x01 [10] 1 0x05 [8] 2 Configuration (LA − RA) (LL − RA) (LL − LA) (Lead II + Lead III)/2
0 0 Digital leads LA – RA LL – RA LL – LA LL − (LA + RA)/2
CH1 − CH3 CH2 − CH3 CH2 − CH1 CH2 − (CH1 + CH3)/2
0 1 Common Lead I Lead II Lead II – Lead I Lead II − 0.5 × Lead I
electrode lead A CH1 CH2 CH2 − CH1 CH2 − 0.5 × CH1
1 X Analog leads Lead I Lead II Lead III Lead II − 0.5 × Lead I − CH3 − 0.5 × CH1
CH1 −CH3 CH2
1
Register ECGCTL, Bit CHCONFIG, see Table 28.
2
Register CMREFCTL, Bit CEREFEN, see Table 32.
3
Register PACECTL, Bit PACExSEL [1:0], see Table 31.

Rev. C | Page 45 of 85
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet
Detection Algorithm Overview START

The pace pulse amplitude and width varies over a wide range, ENABLE PACE DETECTION
SELECT LEADS
while its shape is affected by both the internal filtering arising
from the decimation process and the low pass nature of the START PACE DETECTION
ALGORITHM
electrodes, cabling, and components used for defibrillation and
ESIS protection. The ADAS1000 provides user programmable
FIND
variables to optimize the performance of the algorithm within LEADING EDGE NO
A > PACEEDGETH?
the ECG system, given all these limiting elements. The default
parameter values are probably not optimal for any particular YES
system design; experimentation and evaluation are needed to START PULSE
WIDTH TIMER
ensure robust performance.
PACE
PULSE FIND
END OF NO
LEADING EDGE
B < PACELVL

PACELVLTH
YES

START NOISE
FILTERS (if enabled)
LEADING EDGE YES

PACEAMPTH LEADING EDGE STOP

TRAILING
EDGE NO
DETECTED?
PACEEDGETH
PACE WIDTH YES

PACE AMPLITUDE NO
> PACEAMPTH

RECHARGE
09660-027

PULSE YES

Figure 73. Typical Pace Signal NOISE FILTER NO

PASSED?
The first step in pace detection is to search the data stream for a
valid leading edge. Once a candidate edge is detected, the algorithm YES

verifies that the signal looks like a pulse and then begins searching
PULSE WIDTH NO
for a second, opposite polarity edge that meets the pulse width > 100µs AND <2ms
and amplitude criteria and passes the optional noise filters. Only
the pulses meeting all requirements are flagged as valid pace pulses. YES

Detection of a valid pace pulse sets the flag or flags in the frame FLAG PACE DETECTED
header register and stores amplitude and width information in 09660-026

the PACEDATA register (Address 0x1A; see Table 34). UPDATE REGISTERS WITH
WIDTH AND HEIGHT
The pace algorithm detects pulses of both negative and positive
Figure 74. Overview of Pace Algorithm
polarity using a single set of parameters by tracking the slope of
the leading edge and making the necessary adjustments to internal The three user controlled parameters for the pace detection
parameter signs. This frees the user to concentrate on determining algorithm are Pace Amplitude Threshold (PACEAMPTH), Pace
appropriate threshold values based on pulse shape without Level Threshold (PACELVLTH), and Pace Edge Threshold
concern for pulse polarity. (PACEEDGETH).

Rev. C | Page 46 of 85
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2
Pace Edge Threshold Pace Amplitude Threshold
This programmable level (Address 0x0E, see Table 41) is used to This register (Address 0x07, see Table 34) sets the minimum
find a leading edge, signifying the start of a potential pace pulse. A valid pace pulse amplitude. PACEAMPTH is an unsigned 8-bit
candidate edge is one in which the leading edge crosses a threshold number. The programmed height is given by:
PACEEDGETH from the recent baseline. PACEEDGETH can 2 × N × VREF
PACEAMPTH setting = ,
be assigned any value between 0 and 255. Setting PACEEDGETH GAIN × 216
to 0 forces it to the value PACEAMPTH/2 (see equation).
where:
Non-zero values give the following:
N is the 8-bit programmed PACEAMPTH value (1 ≤ N ≤ 255).
N × VREF VREF is the ADAS1000 reference voltage of 1.8 V.
PACEEDGETH setting =
GAIN × 216 GAIN is the programmed gain of the ECG channel.
where: The minimum threshold for ×1.4 gain is 19.6 µV, while the
N is the 8-bit programmed PACEEDGETH value (1 ≤ N ≤ 255). maximum for the same gain setting is 5.00 mV. PACEAMPTH
VREF is the ADAS1000 reference voltage of 1.8 V. is typically set to the minimum expected pace amplitude and
GAIN is the programmed gain of the ECG channel. must be larger than the value of PACEEDGETH.
The minimum threshold for ×1.4 gain is 19.6 µV, while the The default register setting of N = 0x24 results in 1.4 mV for a
maximum for the same gain setting is 5.00 mV. gain = 1 setting. An initial PACEAMPTH setting between
Pace Level Threshold 1.4 mV and 2 mV provides a good starting point for both
unipolar and biventricular pacing detection. Values below
This programmable level (Address 0x0F, see Table 42) is used to
250 µV are not recommended because they greatly increase
detect when the leading edge of a candidate pulse ends. In general,
sensitivity to ambient noise from the patient. The amplitude
a pace pulse is not perfectly square, and the top, meaning the
may need to be adjusted much higher than 1 mV when other
portion after the leading edge, may continue to increase slightly
medical devices are connected to the patient.
or droop back towards the baseline. PACELVLTH defines an
allowable slope for this portion of the candidate pulse, where Pace Validation Filters
the slope is defined as the change in value over an internally- A candidate pulse that successfully passes the combined tests of
fixed interval after the pace edge is qualified. PACEEDGETH, PACELVLTH, and PACEAMPTH is next passed
PACELVLTH is an 8-bit, twos complement number. Positive through two optional validation filters. These filters are used to
values represent movement away from the baseline (pulse reject sub-threshold pulses such as minute ventilation (MV) pulse
amplitude is still increasing) while negative values represent and signals from inductively coupled implantable telemetry
droop back towards the baseline. systems. These filters perform different tests of pulse shape
using a number of samples. Both filters are enabled by default;
N × VREF
PACELVLTH setting = Filter 1 is controlled by Bit 9 in the PACECTL register (see
GAIN × 216 Table 31) and Filter 2 is controlled by Bit 10 in the same register.
where: These filters are not available on a lead by lead basis; if enabled,
N is the 8-bit programmed PACELVLTH value (−128 ≤ N ≤ 127). they are applied to all leads being used for pace detection.
VREF is the ADAS1000 reference voltage of 1.8 V.
Pace Width Filter
GAIN is the programmed gain of the ECG channel.
A candidate pulse that successfully passes the edge, amplitude, and
The minimum value for ×1.4 gain is 9.8 µV, while the maximum noise filters is finally checked for width. When this final filter is
for the same gain setting is 2.50 mV. enabled, it checks that the candidate pulse is between 100 μs
An additional qualification step, performed after PACELVLTH and 2 ms wide. When a valid pace width is detected, the width
is satisfied, rejects pulses with a leading edge transition time greater is stored. Disabling this filter affects only the minimum width
than about 156 µs. This filter improves immunity to motion and (100 µs) determination; the maximum width detection portion
other artifacts and cannot be disabled. Overly aggressive ESIS of the filter is always active. This filter is controlled by the
filtering causes this filter to disqualify valid pace pulses. In such PACECTL register, Bit 11 (see Table 31).
cases, increasing the value of PACEEDGETH provides more
robust pace pulse detection. Although counterintuitive, this
change forces a larger initial deviation from the recent baseline
before the pace detection algorithm starts, reducing the time
until PACELVLTH comes into play and shortening the apparent
leading edge transition. Increasing the value of PACEEDGETH
may require a reduction in PACEAMPTH.

Rev. C | Page 47 of 85
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet
BIVENTRICULAR PACERS PACE WIDTH
As described previously, the pace algorithm expects the pace pulse The ADAS1000 is capable of measuring pace widths of 100 μs
to be less than 2 ms wide. In a pacer where both ventricles are to 2.00 ms. The measured pace width is available through the
paced, they can be paced simultaneously. Where they fall within PACExDATA registers. These registers have limited resolution.
the width and height limits programmed into the algorithm, a The minimum pace width is 101.56 μs and the maximum is
valid pace is flagged, but only one pace pulse may be visible. 2.00 ms. The pace detection algorithm always returns a width
With the pace width filter enabled, the pace algorithm seeks greater than what is measured at the 50% point, ensuring that
pace pulse widths within a 100 μs to 2 ms window. Assuming the algorithm is capable of measuring a narrow 100 μs pulse. A
that this filter is enabled and in a scenario where two ventricle valid pulse width of 100 μs is reported as 101.56 μs. Any valid
pacer pulses fire at slightly different times, resulting in the pulse pace pulses ≥ 2.00 ms and ≤ 2.25 ms are reported as 2.00 ms.
showing in the lead as one large, wider pulse, a valid pace is PACE LATENCY
flagged so long as the total width does not exceed 2 ms. The pace algorithm always examines 128 kHz, 16-bit ECG data,
PACE DETECTION MEASUREMENTS regardless of the selected frame rate and ECG filter setting. A
Design verification of the ADAS1000 digital pace algorithm pace pulse is qualified when a valid trailing edge is detected and
includes detection of a range of simulated pace signals in is flagged in the next available frame header. Pace and ECG data
addition to using the ADAS1000 and evaluation board with is always correctly time-aligned at the 128 kHz frame rate, but
one pacemaker device connected to various simulated loads the additional filtering inherent in the slower frame rates delays
(approximately 200 Ω to over 2 kΩ) and covering the following the ECG data of the frame relative to the pace pulse flag. These
4 waveform corners. delays are summarized in Table 16 and must be taken into account
to enable correct positioning of the pace event relative to the
• Minimum pulse width (100 μs), minimum height (to ECG data.
<300 μV)
There is an inherent one-frame-period uncertainty in the exact
• Minimum pulse width (100 μs), maximum height (up to
location of the pace trailing edge.
1.0 V)
• Maximum pulse width (2 ms), minimum height (to <300 μV) PACE DETECTION VIA SECONDARY SERIAL
• Maximum pulse width (2 ms), maximum height (up to 1.0 V) INTERFACE (ADAS1000 AND ADAS1000-1 ONLY)
These scenarios passed with acceptable results. The use of the The ADAS1000/ADAS1000-1 provide a second serial interface
ac lead-off function had no obvious impact on the recorded for users who want to implement their own pace detection
pace height, width, or the ability of the pace detection algorithm schemes. This interface is configured as a master interface. It
to identify a pace pulse. The pace algorithm was also evaluated provides ECG data at the 128 kHz data rate only. The purpose
with the respiration carrier enabled; again, no differences in the of this interface is to allow the user to access the ECG data at a
threshold or pacer detect were noted from the carrier. rate sufficient to allow them to run their own pace algorithm,
while maintaining all the filtering and decimation of the ECG
While these experiments validate the pace algorithm over a data that the ADAS1000/ADAS1000-1 offer on the standard
confined set of circumstances and conditions, they do not serial interface (2 kHz and 16 kHz data rates). This dedicated
replace end system verification of the pacer algorithm. This pace interface uses three of the four GPIO pins, leaving one
can be performed in only the end system, using the system GPIO pin available even when the secondary serial interface
manufacturer’s specified cables and validation data set. is enabled. Note that the on-chip digital calibration to ensure
EVALUATING PACE DETECTION PERFORMANCE channel gain matching does not apply to data that is available
on this interface. This interface is discussed in more detail in
ECG simulators offer a convenient means of studying the perfor-
the Secondary Serial Interface section.
mance and ability of the ADAS1000 to capture pace signals over
the range of widths and heights defined by the various regulatory
standards. While the pace detection algorithm of the ADAS1000
is designed to conform to medical instrument standards (pace
widths of 100 μs to 2.00 ms and with amplitudes of <400 μV to
>1000 mV), some simulators put out signals wider or narrower
than called for in the standards. The pace detection algorithm
has been designed to measure a maximum pace widths of 2 ms
with a margin of 0.25 ms to allow for simulator variations.

Rev. C | Page 48 of 85
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2
FILTERING The amount of decimation depends on the selected data rate,
Figure 75 shows the ECG digital signal processing. The ADC with more decimation for the lower data rates.
sample rate is programmable. In high performance mode, it Four selectable low-pass filter corners are available at the 2 kHz
is 2.048 MHz; in low power mode, the sampling rate is reduced data rate.
to 1.024 MHz. The user can tap off framing data at one of three Filters are cleared by a reset. Table 16 shows the filter latencies
data rates, 128 kHz, 16 kHz, or 2 kHz. Note that although the at the different data rates.
data-word width is 24 bits for the 2 kHz and 16 kHz data rate,
the usable bits are 19 and 18, respectively.
AC LEAD-OFF
DETECTION

ADC DATA 2.048MHz

14-BITS PACE
2.048MHz 128kHz DETECTION AVAILABLE DATA RATE
–3dB AT 13kHz CHOICE OF 1:
128kHz DATA RATE
ACLO 16-BITS WIDE
CARRIER
NOTCH 128kHz
2kHz 16kHz DATA RATE
16kHz 24-BITS WIDE
–3dB AT 3.5kHz 18 USABLE BITS
16kHz
2kHz DATA RATE
2kHz
24-BITS WIDE
–3dB AT 450Hz 19 USABLE BITS
40Hz
150Hz CALIBRATION
250Hz 31.25Hz DATA RATE

09660-028
(PROGRAMMABLE BESSEL ) 24-BITS WIDE
~22 USABLE BITS
~7Hz

Figure 75. ECG Channel Filter Signal Flow

Table 16. Relationship of ECG Waveform to Pace Indication1, 2, 3

Data Rate Conditions Apparent Delay of ECG Data Relative to Pace Event4
2 kHz 450 Hz ECG bandwidth 0.984 ms
250 Hz ECG bandwidth 1.915 ms
150 Hz ECG bandwidth 2.695 ms
40 Hz ECG bandwidth 7.641 ms
16 kHz 109 μs
128 kHz 0
1
ECG waveform delay is the time required to reach 50% of final value following a step input.
2
Guaranteed by design, not subject to production test.
3
There is an unavoidable residual uncertainty of 8 μs in determining the pace pulse trailing edge.
4
Add 38 μs to obtain the absolute delay for any setting.

Rev. C | Page 49 of 85
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet
VOLTAGE REFERENCE When a device is configured as a slave (ADAS1000-2), the
The ADAS1000/ADAS1000-1/ADAS1000-2 have a high SYNC_GANG and CLK_IO pins are set as inputs.
performance, low noise, on-chip 1.8 V reference for use in Synchronizing Devices
the ADC and DAC circuits. The REFOUT of one device is The ganged devices need to share a common clock to ensure
intended to drive the REFIN of the same device. The internal that conversions are synchronized. One approach is to drive
reference is not intended to drive significant external current; the slave CLK_IO pins from the master CLK_IO pin. Alter-
for optimum performance in gang operation with multiple natively, an external 8.192 MHz clock can be used to drive
devices, each device should use its own internal reference. the CLK_IO pins of all devices. The CLK_IO powers up high
An external 1.8 V reference can be used to provide the impedance until configured in gang mode.
required VREF. In such cases, there is an internal buffer pro- In addition, the SYNC_GANG pin is used to synchronize
vided for use with external reference. The REFIN pin is a the start of the ADC conversion across multiple devices. The
dynamic load with an average input current of approximately SYNC_GANG pin is automatically driven by the master and
100 μA per enabled channel, including respiration. When is an input to all the slaves. SYNC_GANG is in high
the internal reference is used, the REFOUT pin requires impedance until enabled via gang mode.
decoupling with a10 μF capacitor with low ESR (0.2 Ω
When connecting devices in gang mode, the SYNC_GANG
maximum) in parallel with 0.01 μF capacitor to REFGND,
output is triggered once when the master device starts to convert.
these capacitors should be placed as close to the device pins
Therefore, to ensure that the slave device or devices receive this
as possible and on the same side of the PCB as the device.
synchronization signal, configure the slave device first for
GANG MODE OPERATION operation and enable conversions, followed by issuing the
While a single ADAS1000 or ADAS1000-1 provides the ECG conversion signal to the ECGCTL register in the master
channels to support a five-electrode and one-RLD electrode device. SYNC_GANG is active high.
(or up to 8-lead) system, the device has also been designed so
MASTER SLAVE 0
that it can easily extend to larger systems by paralleling up
multiple devices. In this mode of operation, an ADAS1000 or CLK_IO CLK_IO
ADAS1000-1 master device can easily be operated with one SYNC_GANG SYNC_GANG
or more ADAS1000-2 slave devices. In such a configuration, CM_OUT CM_IN

one of the devices (ADAS1000 or ADAS1000-1) is designated CAL_DAC_IO CAL_DAC_IO

as master, and any others are designated as slaves. It is SLAVE 1

important that the multiple devices operate well together;
with this in mind, the pertinent inputs/outputs to interface CLK_IO
between master and slave devices have been made available. SYNC_GANG

09660-029
CM_IN
Note that when using multiple devices, the user must collect the CAL_DAC_IO
ECG data directly from each device. If using a traditional 12-lead
Figure 76. Master/Slave Connections in Gang Mode, Using Multiple
arrangement where the Vx leads are measured relative to WCT, ADAS1000/ADAS1000-1/ADAS1000-2 Devices
the user must configure the ADAS1000 or ADAS1000-1 master
device in lead mode with the slave ADAS1000-2 device Calibration
configured for electrode mode. The LSB size for electrode and The calibration DAC signal from one device (master) can be
lead data differs (see Table 43 for details). output on the CAL_DAC_IO pin and used as the calibration
In gang mode, all devices must be operated in the same input for other devices (slaves) when used in the gang mode
power mode (either high performance or low power) and of operation. This ensures that they are all being calibrated
the same data rate. using the same signal which results in better matching across
channels. This does not happen automatically in gang mode
Master/Slave but, rather, must be configured via Table 36.
The ADAS1000 or ADAS1000-1 can be configured as a
master or slave, while the ADAS1000-2 can only be config-
ured as a slave. A device is selected as a master or slave using
Bit 5, master, in the ECGCTL register (see Table 28). Gang
mode is enabled by setting Bit 4, gang, in the same register.
When a device is configured as a master, the
SYNC_GANG pin is automatically set as an output.

Rev. C | Page 50 of 85
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2
Common Mode enable other settings in the slave prior to enabling conversion
The ADAS1000/ADAS1000-1 have a dedicated CM_OUT pin (the CNVEN bit in the ECGCTL register) on the master. The
serving as an output and a CM_IN pin as an input. In gang SYNC pulse is generated by the master, but if the slave is not
mode, the master device determines the common-mode voltage powered up with the PLL clock running and locked, the slave
based on the selected input electrodes. This common-mode may miss the SYNC pulse. When the master device
signal (on CM_OUT) can then be used by subsequent slave conversion signal is set, the master device generates one edge
devices (applied to CM_IN) as the common-mode reference. on the SYNC_GANG pin. This configuration applies to any
All electrodes within the slave device are then measured with slave SYNC_GANG inputs, allowing the devices to
respect to the CM_IN signal from the master device. See the synchronize ADC conversions.
CMREFCTL register in Table 32 for more details on the control Number of Devices in Gang Mode
via the serial interface. Figure 77 shows the connections Traditional ECG applications extend to 12-lead or 15-lead
between a master and slave device using multiple measurements (using two or three ADAS1000 devices).
ADAS1000/ADAS1000-2 devices. Although gang mode supports multiple ADAS1000 devices
Right Leg Drive connected in a master and slave configuration, there is a limit
The right leg drive comes from the master device. If the internal to how many slave devices can be connected to one master.
RLD resistors of the slave device are to contribute to the RLD Using the CLK_IO pin and the SYNC_GANG pin as extra
loop, tie the RLD_SJ pins of master and slave together. devices and routing increases capacitance and introduces
jitter and noise. It is recommended that applications
Sequencing Devices into Gang Mode requiring larger electrode counts externally buffer any signals
When entering gang mode with multiple devices, it is shared from master to slave (including buffering the common
recommended to enable power (the PWREN bit in the mode if it is shared from master to slaves).
ECGCTL register) to the slave and wait for the PLL to lock
(visible in the OPSTAT register). Subsequently, the user can

Rev. C | Page 51 of 85
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet

RLD_SJ
CM_IN
CM_OUT/
REFIN REFOUT CAL_DAC_IO RLD_OUT SHIELD AVDD IOVDD
WCT
DRIVEN
LEAD AMP
VREF ADCVDD
ADCVDD, DVDD (optional)
CALIBRATION
1.8V
SHIELD REGULATORS DVDD
DAC DRIVE
VCM_REF AMP
(optional)
RESPIRATION (1.3V)
DAC ADAS1000
AC COMMON-
LEAD-OFF MODE AMP
DAC
LEAD-OFF
DETECTION
10kΩ
PACE CS
MUXES DETECTION

SCLK
5 × ECG PATH
SDI TAKE LEAD
ELECTRODES FILTERS,
×5 CONTROL, SDO DATA
AMP ADC
AND DRDY
INTERFACE
LOGIC SYNC_GANG

EXT RESP_LA AMP ADC

EXT RESP LL CLK_IO
CLOCK GEN/OSC/
EXT RESP_RA RESPIRATION PATH EXTERNAL CLK
SOURCE

XTAL1 XTAL2

REFIN REFOUT CAL_DAC_IN RLD_SJ CM_IN AVDD IOVDD

ADCVDD
VREF ADCVDD, DVDD (optional)
1.8V
REGULATORS DVDD
VCM_REF (optional)
(1.3V)
ADAS1000-2
SLAVE
AC COMMON-
LEAD-OFF MODE AMP
DAC
LEAD-OFF
DETECTION

PACE
MUXES DETECTION CS

SCLK
5 × ECG PATH TAKE
SDI ELECTRODE
ELECTRODES FILTERS,
×5 CONTROL, SDO DATA
AMP ADC
AND DRDY
INTERFACE
LOGIC SYNC_GANG

CLOCK GEN/OSC/ CLK_IO

EXTERNAL CLK
SOURCE

09660-030
Figure 77. Configuring Multiple Devices to Extend Number of Electrodes/Leads
(This Example Uses ADAS1000 as Master and ADAS1000-2 as Slave. Similarly the ADAS1000-1 Could be Used as Master.)

INTERFACING IN GANG MODE data to maintain the chosen data rate and ensure they have
As shown in Figure 77, when using multiple devices, the the relevant synchronized data. Alternative methods might use
user must collect the ECG data directly from each device. individual controllers for each device or separate SDO paths.
The example shown in Figure 78 illustrates one possibility For some applications, digital isolation is required between
of how to approach interfacing to a master and slave device. the host and the ADAS1000. The example shown illustrates a
Note that SCLK, SDO, and SDI are shared here with individual means to ensure that the number of lines requiring isolation
CS lines. This requires the user to read the data on both is minimized.
devices twice as fast to ensure that they can capture all the

Rev. C | Page 52 of 85
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2
Table 17. Some Possible Arrangements for Gang Operation
Master Slave 1 Slave 2 Features Number of Electrodes Number of Leads
ADAS1000 ADAS1000-2 ECG, respiration, pace 10 ECG, CM_IN, RLD 12-lead + spare ADC channel
ADAS1000 ADAS1000-2 ADAS1000-2 ECG, respiration, pace 15 ECG, CM_IN, RLD 15-lead + 3 spare ADC channels
ADAS1000 ADAS1000-3 ECG, respiration, pace 8 ECG, CM_IN, RLD 12-lead (derived leads)
ADAS1000-1 ADAS1000-2 ECG 10 ECG, CM_IN, RLD 12-lead + spare ADC channel
ADAS1000-3 ADAS1000-2 ECG 8 ECG, CM_IN, RLD 12-lead (derived leads)
ADAS1000-4 ADAS1000-2 ECG, respiration, pace 8 ECG, CM_IN, RLD 12-lead (derived leads)

SCLK
SDI
MICROCRONTROLLER/
DSP CS1
CS2
SDO

MASTER SLAVE

SCLK SCLK
SDI SDI
CS CS

09660-031
DRDY (OPTIONAL) DRDY (OPTIONAL)
SDO SDO

Figure 78. One Method of Interfacing to Multiple Devices

Rev. C | Page 53 of 85
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet

SERIAL INTERFACES
The ADAS1000/ADAS1000-1/ADAS1000-2 are controlled via MICROCONTROLLER/ ADAS1000
DSP
a standard serial interface allowing configuration of registers SCLK SCLK
and readback of ECG data. This is an SPI-compatible interface CS CS
that can operate at SCLK frequencies up to 40 MHz. MOSI SDI
MISO SDO

09660-033
The ADAS1000/ADAS1000-1 also provide an optional secondary GPIO DRDY

serial interface that is capable of providing ECG data at the

128 kHz data rate for users wishing to apply their own digital Figure 79. Serial Interface

pace detection algorithm. This is a master interface that Write Mode

operates with an SCLK of 20.48 MHz. The serial word for a write is 32 bits long, MSB first. The
STANDARD SERIAL INTERFACE serial interface works with both a continuous and a burst
The standard serial interface is LVTTL-compatible when operating (gated) serial clock. The falling edge of CS starts the write
from a 2.3 V to 3.6 V IOVDD supply. This is the primary interface cycle. Serial data applied to SDI is clocked into the ADAS1000/
for controlling the ADAS1000/ADAS1000-1/ADAS1000-2, ADAS1000-1/ADAS1000-2 on rising SCLK edges. At least 32
reading and writing registers, and reading frame data containing rising clock edges must be applied to SCLK to clock in 32 bits of
all the ECG data-words and other status functions within the data before CS is taken high again. The addressed input register
device. is updated on the rising edge of CS. For another serial transfer
to take place, CS must be taken low again. Register writes are used
The SPI is controlled by the following five pins:
to configure the device. Once the device is configured and enabled
• CS (frame synchronization input). Asserting CS low selects for conversions, frame data can be initiated to start clocking out
the device. When CS is high, data on the SDI pin is ignored. If ECG data on SDO at the programmed data rate. Normal operation
CS is inactive, the SDO output driver is disabled, so that for the device is to send out frames of ECG data. Typically, register
multiple SPI devices can share a common SDO pin. The CS reads and writes are needed only during start-up configuration.
pin can be tied low to reduce the number of isolated paths However, it is possible to write new configuration data to the
required. When CS is tied low, there is no frame around device while in framing mode. A new write command is accepted
the data-words; therefore, the user must be aware of where within the frame and, depending on the nature of the command,
they are within the frame. All data-words with 2 kHz and there may be a need to flush out the internal filters (wait periods)
16 kHz data rates contain register addresses at the start of before seeing usable framing data again.
each word within the frame. Users can resynchronize the Write/Read Data Format
interface by holding SDI high for 64 SCLK cycles, followed
Address, data, and the read/write bits are all in the same word.
by a read of any register so that SDI is brought low for the
Data is updated on the rising edge of CS or the first cycle of the
first bit of the following word.
following word. For all write commands to the ADAS1000/
• SDI (serial data input pin): Data on SDI is clocked into the
ADAS1000-1/ADAS1000-2, the data-word is 32 bits, as shown
device on the rising edges of SCLK.
in Table 18. Similarly, when using data rates of 2 kHz and
• SCLK (clocks data in and out of the device). SCLK should
16 kHz, each word is 32 bits (address bits and data bits).
idle high when CS is high.
• SDO (serial data output pin for data readback). Data is Table 18. Serial Bit Assignment (Applies to All Register
shifted out on SDO on the falling edges of SCLK. The Writes, 2 kHz and 16 kHz Reads)
SDO output driver is high-Z when CS is high. B31 [B30:B24] [B23:B0]
• DRDY (data ready, optional). Data ready when low, busy R/W Address bits[6:0] Data bits [23:0] (MSB first)
when high. Indicates the internal status of the ADAS1000/ For register reads, data is shifted out during the next word, as
ADAS1000-1/ADAS1000-2 digital logic. It is driven shown in Table 19.
high/busy during reset. If data frames are enabled and the
frame buffer is empty, this pin is driven busy/high. If the Table 19. Write/Read Data Stream
frame buffer is full, this pin is driven low/ready. If data frames Digital
are not enabled, this pin is driven low to indicate that the Pin Command 1 Command 2 Command 2
device is ready to accept register read/write commands. SDI Read Address 1 Read Address 2 Write Address 3
When reading packet data, the entire packet must be read SDO Address 1 Address 2
to allow the DRDY return back high. The host controller Read Data 1 Read Data 2
must treat the DRDY signal as a level sensitive input.

Rev. C | Page 54 of 85
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2
In the 128 kHz data rate, all write words are still 32-bit writes Read Mode
but the read words in the data packet are now 16 bits (upper Although the primary reading function within the ADAS1000/
16 bits of register). There are no address bits, only data bits. ADAS1000-1/ADAS1000-2 is the output of the ECG frame
Register space that is larger than 16 bits spans across 2 × data, the devices also allow reading of all configuration regis-
16-bit words (for example, pace and respiration). ters. To read a register, the user must first address the device
Data Frames/Packets with a read command containing the particular register address.
The general data packet structure is shown in Table 18. Data If the device is already in data framing mode, the read register
can be received in two different frame formats. For the 2 kHz command can be interleaved between the frames by issuing a
and 16 kHz data rates, a 32-bit data format is used (where the read register command during the last word of frame data. Data
register address is encapsulated in the upper byte, identifying shifted out during the next word is the register read data. To
the word within the frame) (see Table 22). For the 128 kHz data return to framing mode, the user must re-enable framing by
rate, words are provided in 16-bit data format (see Table 23). issuing a read of the frame header register (Address 0x40; see
Table 54). This register write can be used to flush out the
When the configuration is complete, the user can begin reading register contents from the previous read command.
frames by issuing a read command to the frame header register
(see Table 54). The ADAS1000/ADAS1000-1/ADAS1000-2 Table 20. Example of Reading Registers and Frames
continue to make frames available until another register address SDI ….. NOP Read Read NOP NOP …..
is written (read or write command). To continue reading frame Address frames
N
data, continue to write all zeros on SDI, which is a write of the
SDO ….. Frame Frame Register Frame Frame …..
NOP register (Address 0x00). A frame is interrupted only when data CRC Data N header data
another read or write command is issued.
Regular register reads are always 32 bits long and MSB first.
Each frame can be a large amount of data plus status words. CS
Serial Clock Rate
can toggle between each word of data within a frame, or it can
be held constantly low during the entire frame. The SCLK can be up to 40 MHz, depending on the IOVDD
voltage level as shown in Table 5. The minimum SCLK
By default, a frame contains 11 × 32-bit words when reading at frequency is set by the requirement that all frame data be
2 kHz or 16 kHz data rates; similarly, a frame contains 13 × 16-bit clocked out before the next frame becomes available.
words when reading at 128 kHz. The default frame configuration
does not include the optional respiration phase word; however, SCLK (min) = frame_rate × words_per_frame ×
this word can be included as needed. Additionally any words bits_per_word
not required can be excluded from the frame. To arrange the The minimum SCLK for the various frame rates is shown in
frame with the words of interest, configure the appropriate bits Table 21.
in the frame control register (see Table 37). The complete set of
words per frame are 12 × 32-bit words for the 2 kHz or 16 kHz Table 21. SCLK Clock Frequency vs. Packet Data/Frame Rates
data rates, or 15 × 16-bit words at 128 kHz. Frame Word Maximum Minimum
Rate Size Words/Frame 1 SCLK
Any data not available within the frame can be read between 128 kHz 16 bits 15 words 30.72 MHz
frames. Reading a register interrupts the frame and requires the 16 kHz 32 bits 12 words 6.14 MHz
user to issue a new read command of Address 0x40 (see 2 kHz 32 bits 12 words 768 kHz
Table 54) to start framing again.
1
This is the full set of words that a frame contains. It is programmable and can
be configured to provide only the words of interest. See Table 37.

Table 22. Default 2 kHz and 16 kHz Data Rate: 32-Bit Frame Word Format
Register Header Lead I/LA Lead II/LL Lead III/RA V1’/V1 V2’/V2 PACE RESPM RESPPH LOFF GPIO CRC
Address 0x40 0x11 0x12 0x13 0x14 0x15 0x1A 0x1B 0x1C 0x1D 0x06 0x41

Table 23. Default 128 kHz Data Rate: 16-Bit Frame Word Format 1
Register Header Lead I/LA Lead II/LL Lead III/RA V1’/V1 V2’/V2 PACE1 PACE2 RESPM1 RESPM2 LOFF GPIO CRC
Address 0x40 0x11 0x12 0x13 0x14 0x15 0x1A 0x1B 0x1D 0x06 0x41
1
Respiration phase words (2 × 16-bit words) are not shown in this frame, but can be included.

Rev. C | Page 55 of 85
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet
Internal operations are synchronized to the internal master • One of the first bits of valid data in the header word
clock at either 2.048 MHz or 1.024 MHz (ECGCTL[3]: HP = 1 available on SDO is a data ready status bit (see Table 43).
and HP = 0, respectively, see Table 28). Because there is no Within the configuration of the ADAS1000/ADAS1000-1/
guaranteed relationship between the internal clock and the ADAS1000-2, the user can set the header to repeat until
SCLK signal of the SPI, an internal handshaking scheme is used the data is ready. See Bit 6 (RDYRPT) in the frame control
to ensure safe data transfer between the two clock domains. A register in Table 37.
full handshake requires three internal clock cycles and imposes
an upper speed limit on the SCLK frequency when reading The host controller must read the entire frame to ensure DRDY
frames with small word counts. This is true for all data frame returns low and ready. If the host controller treats the DRDY as
rates. an edge triggered signal and then misses a frame or underruns,
the DRDY remains high because there is still data available to
SCLK (max) = (1.024 MHz × (1 + HP) × words_per_frame
read. The host controller must treat the DRDY signal as level
× bits_per_word)/3; or 40 MHz, whichever is lower.
triggered, ensuring that whenever it goes low, it generates an
Exceeding the maximum SCLK frequency for a particular interrupt which can initiate a SPI frame transfer. On completion
operating mode causes erratic behavior in the DRDY signal of the transfer the DRDY returns high.
and results in the loss of data.
Detecting Missed Conversion Data
Data Rate and Skip Mode
To ensure that the current data is valid, the entire frame must
Although the standard frame rates available are 2 kHz, 16 kHz, be read at the selected data rate. If a read of the entire frame
and 128 kHz, there is also a provision to skip frames to further takes longer than the selected data rate allows, the internal
reduce the data rate. This can be configured in the frame buffer is not loaded with the latest conversion data. The frame
control register (see Table 37). header register (see Table 54) provides four settings to indicate
Data Ready (DRDY) an overflow of frame data. The settings of Bits[29:28] report
how many frames have been missed since the last valid frame
The DRDY pin is used to indicate that a frame composed of
read. A missed frame may occur as a result of the last read
decimated data at the selected data rate is available to read. It is
taking too long. The data in the current frame is valid data, but
high when busy and low when ready. Send commands only when
it is not the current data. It is the calculation made directly after
the status of DRDY is low or ready. During power-on, the status
the last valid read.
of DRDY is high (busy) while the device initializes itself. When
To clear such an overflow, the user must read the entire frame.
initialization is complete, DRDY goes low and the user can start
configuring the device for operation. When the device is SPI INTERFACE RESYNC
configured and enabled for conversions by writing to the The ADAS1000 interface supports frame mode and accepts
conversion bit (CNVEN) in the ECGCTL register, the ADCs commands to reconfigure the device during frame reads. In the
start to convert and the digital interface starts to make data event of communication issues when interrupting frame reads,
available, loading them into the buffer when ready. it is possible to resync the interface by keeping SDI high for
If conversions are enabled and the buffer is empty, the device is 64 SCLK cycles, followed by a read of any register so that SDI is
not ready and DRDY goes high. Once the buffer is full, DRDY brought low for the first bit of the following word.
goes low to indicate that data is ready to be read out of the
device. If the device is not enabled for conversions, the DRDY
ignores the state of the buffer full status.
When reading packets of data, the entire data packet must be
read; otherwise, DRDY stays low.
There are three methods of detecting DRDY status.
• DRDY pin. This is an output pin from the ADAS1000/
ADAS1000-1/ADAS1000-2 that indicates the device read
or busy status. No data is valid while this pin is high. The
DRDY signals that data is ready to be read by driving low
and remaining low until the entire frame has been read. It
is cleared when the last bit of the last word in the frame is
clocked onto SDO. The use of this pin is optional.
• SDO pin. The user can monitor the voltage level of the
SDO pin by bringing CS low. If SDO is low, data is ready;
if high, busy. This does not require clocking the SCLK
input. (CPHA = CPOL = 1 only).
Rev. C | Page 56 of 85
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2
CRC Word ADAS1000 are a function of the frequency of the externally
Framed data integrity is provided by CRCs. For the 128 kHz applied clock.
frame rates, the 16-bit CRC-CCITT polynomial is used. For the Using a frequency other than the 8.192 MHz previously noted
2 kHz and 16 kHz frame rates, the 24-bit CRC polynomial used. causes scaling of the data rates, filter corners, ac lead off
In both cases, the CRC residue is preset to all 1s and inverted frequency, respiration frequency, and pace algorithm corners
before being transmitted. The CRC parameters are summarized accordingly.
in Table 24. To verify that data is correctly received, software Each XTAL pin requires a capacitor to ground. The
computes a CRC on both the data and the received checksum. If recommended capacitor value is in the range of 6 pF to 10 pF,
data and checksum are received correctly, the resulting CRC depending on the crystal. It is recommended that the chosen
residue equals the check constant shown in Table 24. Note that crystal has a high ESR and large solder footprint, as a lower
data is shifted through the generator polynomial MSB first, the capacitance ensures a reliable startup.
same order that it is shifted out serially. The bit and byte order
ADAS1000
of the CRC that is appended to the frame is such that the MSB
of the CRC is shifted through the generator polynomial first in XTAL2

the same order as the data so that the CRC residue XOR’d with
the inverted CRC at the end of the frame is all 1s, which is why
XTAL1
the check constant is identical for all messages. The CRC is

09660-034
based only on the data that is sent out. CLK_IO

For more details on the CRC, refer to the AN-1251 Application Figure 80. Input Clock
Note.
The crystal oscillator circuit expects the total capacitance at the
Clocks pin to be <20 pF (ideally 15 pF) to ensure reliable startup across
The ADAS1000/ADAS1000-1/ADAS1000-2 run from an operating conditions. Some crystal pad footprints can be large
external crystal or clock input frequency of 8.192 MHz. and if the crystal is not located right up against the XTAL pins,
When a device is configured as a master, CLK_IO can be used the extra capacitance may cause issues with startup.
as an input or output if in gang mode. The external clock input When choosing crystals, choose one with low ESR, <70 Ω
is provided for use in gang mode so conversions between two maximum. Review the board layout to ensure crystal and
devices are synchronized. capacitors are located as close to the pin as possible. Use a
In gang mode, the CLK_IO pin is an output from the master crystal load capacitor value of 5.6 pF to 10 pF. Using a smaller
and an input to the slave. To reduce power, CLK_IO is disabled crystal capacitor value causes a pulling effect on the frequency.
when not in gang mode. The user can also drive both master The recommended frequency error is <500 ppm.
and slave devices from an external clock when in gang mode by
configuring the CLKEXT bit accordingly. All features within the
Table 24. CRC Polynomials
Polynomial
Frame Rate CRC Size Polynomial in Hex Check Constant
2 kHz, 16 kHz 24 bits x24 + x22 + x20 + x19 + x18 + x16 + x14 + x13 + x11 + x10 + x8 + x7 + x6 + x3 + x1 + x0 0x15D6DCB 0x15A0BA
128 kHz 16 bits x16 + x12 + x5 + x0 0x11021 0x1D0F

Rev. C | Page 57 of 85
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet
SECONDARY SERIAL INTERFACE available on MSDO on the falling edge of MSCLK. MSCLK
This second serial interface is an optional interface that can idles high when MCS is deasserted.
be used for the user’s own pace detection purposes. This The data format for this interface is fixed and not influenced by
interface contains ECG data at 128 kHz data rate only. If using the FRMCTL register settings. All seven words are output, even
this interface, the ECG data is still available on the standard if the individual channels are not enabled.
interface discussed previously at lower rates with all the The header word consists of four bits of all 1s followed by a
decimation and filtering applied. If this interface is inactive, 12-bit sequence counter. This sequence counter increments
it draws no power. after every frame is sent, thereby allowing the user to tell if
Data is available in 16-bit words, MSB first. any frames have been missed and how many.
This interface is a master interface, with the ADAS1000/ RESET
ADAS1000-1 providing the SCLK, CS, SDO. Is it shared
There are two methods of resetting the ADAS1000/ADAS1000-1/
across some of the existing GPIO pins as follows:
ADAS1000-2 to power-on default. Bringing the RESET line low
 GPIO1/MSCLK or setting the SWRST bit in the ECGCTL register (Table 28)
 GPIO0/MCS resets the contents of all internal registers to their power-on
 GPIO2/MSDO reset state. The falling edge of the RESET pin initiates the reset
process; DRDY goes high for the duration, returning low when
This interface can be enabled via the GPIO register (see
Table 33). the RESET process is complete. This sequence takes 1.5 ms
maximum. Do not write to the serial interface while DRDY is
MICROCONTROLLER/ ADAS1000
DSP
MASTER SPI high handling a RESET command. When DRDY returns low,
SCLK MSCLK/GPIO1 normal operation resumes and the status of the RESET pin is
CS MCS/GPIO0 ignored until it goes low again. Software reset using the
09660-035

MISO/GPIO MSDO/GPIO2 SWRST bit (see Table 28) requires that a NOP (no operation)
command be issued to complete the reset cycle.
Figure 81. Master SPI Interface for External Pace Detection Purposes

The data format of the frame starts with a header word and five PD FUNCTION
ECG data-words, as shown in Table 25, and completes with the The PD pin powers down all functions in low power mode.
same CRC word as documented in Table 24 for the 128 kHz The digital registers maintain their contents. The power-down
rate. All words are 16 bits. MSCLK runs at approximately function is also available via the serial interface (ECG control
20 MHz and MCS is asserted for the entire frame with the data register, see Table 28).
Table 25. Master SPI Frame Format; All Words are 16 Bits
Mode/Word 1 2 3 4 5 6 7
Electrode mode1 Header ECG1_LA ECG2_LL ECG3_RA ECG4_V1 ECG5_V2 CRC
Analog lead mode1 Header LEAD I LEAD III -LEAD II (RA-LL) V1’ V2’ CRC
1
As set by the FRMCTL register data DATAFMT, Bit [4], see Table 37.

Rev. C | Page 58 of 85
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2

SPI OUTPUT FRAME STRUCTURE (ECG AND STATUS DATA)

Three data rates are offered for reading ECG data: low speed 2 kHz/16 kHz rates for electrode/lead data (32-bit words) and a high speed
128 kHz for electrode/lead data (16-bit words).

DRDY

CS1

EACH SCLK WORD IS 32 CLOCK CYCLES

1 2 3 4 5 6 7 8 9 10 11

SCLK

DRIVEN OUTPUT DATA STREAM

SDO2

GPIO
NITU N

F
TION

ORD
DER

RA

ANOTHER FRAME OF DATA

1

2
L

D-OF
DE
MAG IRATIO
V1’/V

V2’/V
D I/L

D II/L

D III/
HEA

W
TEC

LEA
LEA

CRC
LEA

LEA

P
E DE

RES
PAC

32-BIT
DATA WORDS

1 CS MAY BE USED IN ONE OF THE FOLLOWING WAYS:

A) HELD LOW ALL THE TIME.
B) USED TO FRAME THE ENTIRE PACKET OF DATA.

09660-036
C) USED TO FRAME EACH INDIVIDUAL 32-BIT WORD.
2 SUPER SET OF FRAME DATA, WORDS MAY BE EXCLUDED.

Figure 82. Output Frame Structure for 2 kHz and 16 kHz Data Rates with SDO Data Configured for Electrode or Lead Data

DRDY

CS1

EACH SCLK WORD IS 16 CLOCK CYCLES

1 2 3 4 5 6 7 8 9 10 11 12 13

SCLK

DRIVEN OUTPUT DATA STREAM

SDO2

ANOTHER FRAME
LL

GPIO
DER

LA

V1

V2
RA

ORD
E

F
NITU N
PAC

D-OF
DE
MAG IRATIO
HEA

W
LEA

CRC
P
RES

16-BIT
DATA WORDS

1 CS MAY BE USED IN ONE OF THE FOLLOWING WAYS:

A) HELD LOW ALL THE TIME.
B) USED TO FRAME THE ENTIRE PACKET OF DATA.
09660-037

C) USED TO FRAME EACH INDIVIDUAL 16-BIT WORD.

2 SUPER SET OF FRAME DATA, WORDS MAY BE EXCLUDED.

Figure 83. Output Frame Structure for 128 kHz Data Rate with SDO Data Configured for Electrode Data
(The 128 kHz Data Rate Can Provide Single-Ended Electrode Data or Analog Lead Mode Data Only. Digital Lead Mode Is Not Available at 128 kHz Data Rate.)

Rev. C | Page 59 of 85
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet

SPI REGISTER DEFINITIONS AND MEMORY MAP

In 2 kHz and 16 kHz data rates, data takes the form of 32-bit words. Bit A6 to Bit A0 serve as word identifiers. Each 32-bit word has
24 bits of data. A third high speed data rate is also offered: 128 kHz with data in the form of 16-bit words (all 16 bits as data).

Table 26. SPI Register Memory Map

R/W 1 A[6:0] D[23:0] Register Name Table Register Description Reset Value
R 0x00 XXXXXX NOP NOP (no operation) 0x000000
R/W 0x01 dddddd ECGCTL Table 28 ECG control 0x000000
R/W 0x02 dddddd LOFFCTL Table 29 Lead-off control 0x000000
R/W 0x03 dddddd RESPCTL Table 30 Respiration control 2 0x000000
R/W 0x04 dddddd PACECTL Table 31 Pace detection control 0x000F88
R/W 0x05 dddddd CMREFCTL Table 32 Common-mode, reference, and shield drive control 0xE00000
R/W 0x06 dddddd GPIOCTL Table 33 GPIO control 0x000000
R/W 0x07 dddddd PACEAMPTH Table 34 Pace amplitude threshold2 0x242424
R/W 0x08 dddddd TESTTONE Table 35 Test tone 0x000000
R/W 0x09 dddddd CALDAC Table 36 Calibration DAC 0x002000
R/W 0x0A dddddd FRMCTL Table 37 Frame control 0x079000
R/W 0x0B dddddd FILTCTL Table 38 Filter control 0x000000
R/W 0x0C dddddd LOFFUTH Table 39 AC lead-off upper threshold 0x00FFFF
R/W 0x0D dddddd LOFFLTH Table 40 AC lead-off lower threshold 0x000000
R/W 0x0E dddddd PACEEDGETH Table 41 Pace edge threshold2 0x000000
R/W 0x0F dddddd PACELVLTH Table 42 Pace level threshold2 0x000000
R 0x11 XXXXXX LADATA Table 43 LA or Lead I data 0x000000
R 0x12 XXXXXX LLDATA Table 43 LL or Lead II data 0x000000
R 0x13 XXXXXX RADATA Table 43 RA or Lead III data 0x000000
R 0x14 XXXXXX V1DATA Table 43 V1 or V1’ data 0x000000
R 0x15 XXXXXX V2DATA Table 43 V2 or V2’ data 0x000000
R 0x1A XXXXXX PACEDATA Table 44 Read pace detection data/status2 0x000000
R 0x1B XXXXXX RESPMAG Table 45 Read respiration data—magnitude2 0x000000
R 0x1C XXXXXX RESPPH Table 46 Read respiration data—phase2 0x000000
R 0x1D XXXXXX LOFF Table 47 Lead-off status 0x000000
R 0x1E XXXXXX DCLEAD-OFF Table 48 DC lead-off 0x000000
R 0x1F XXXXXX OPSTAT Table 49 Operating state 0x000000
R/W 0x20 dddddd EXTENDSW Table 50 Extended switch for respiration inputs 0x000000
R/W 0x21 dddddd CALLA Table 51 User gain calibration LA 0x000000
R/W 0x22 dddddd CALLL Table 51 User gain calibration LL 0x000000
R/W 0x23 dddddd CALRA Table 51 User gain calibration RA 0x000000
R/W 0x24 dddddd CALV1 Table 51 User gain calibration V1 0x000000
R/W 0x25 dddddd CALV2 Table 51 User gain calibration V2 0x000000
R 0x31 dddddd LOAMLA Table 52 Lead-off amplitude for LA 0x000000
R 0x32 dddddd LOAMLL Table 52 Lead-off amplitude for LL 0x000000
R 0x33 dddddd LOAMRA Table 52 Lead-off amplitude for RA 0x000000
R 0x34 dddddd LOAMV1 Table 52 Lead-off amplitude for V1 0x000000
R 0x35 dddddd LOAMV2 Table 52 Lead-off amplitude for V2 0x000000
R 0x3A dddddd PACE1DATA Table 53 Pace1 width and amplitude2 0x000000
R 0x3B dddddd PACE2DATA Table 53 Pace2 width and amplitude2 0x000000
R 0x3C dddddd PACE3DATA Table 53 Pace3 width and amplitude2 0x000000
R 0x40 dddddd FRAMES Table 54 Frame header 0x800000
R 0x41 XXXXXX CRC Table 55 Frame CRC 0xFFFFFF
x Other XXXXXX Reserved 3 Reserved XXXXXX
1
R/W = register both readable and writable; R = read only.
2
ADAS1000 model only, ADAS1000-1/ADAS1000-2 models do not contain these features.
3
Reserved bits in any register are undefined. In some cases a physical (but unused) memory bit may be present—in other cases not. Do not issue commands to
reserved registers/space. Read operations of unassigned bits are undefined.

Rev. C | Page 60 of 85
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2

CONTROL REGISTERS DETAILS

For each register address, the default setting is noted in a default column in addition to being noted in the function column by “(default)”;
this format applies throughout the register map.

Table 27. Serial Bit Assignment

B31 [B30:B24] [B23:B0]
R/W Address bits Data bits (MSB first)

Table 28. ECG Control Register (ECGCTL) Address 0x01, Reset Value = 0x000000
R/W Default Bit Name Function
R/W 0 23 LAEN ECG channel enable; shuts down power to the channel; the input becomes high-Z.
R/W 0 22 LLEN 0 (default) = disables ECG channel. When disabled, the entire ECG channel is shut down and
R/W 0 21 RAEN dissipating minimal power.
R/W 0 20 V1EN 1 = enables ECG channel.
R/W 0 19 V2EN
R 0 [18:11] Reserved Reserved, set to 0.
R/W 0 10 CHCONFIG Setting this bit selects the differential analog front end (AFE) input. See Figure 58.
0 (default) = single-ended input (digital lead mode or electrode mode).
1 = differential input (analog lead mode).
R/W 00 [9:8] GAIN [1:0] Preamplifier and anti-aliasing filter overall gain.
00 (default) = GAIN 0 = ×1.4.
01 = GAIN 1 = ×2.1.
10 = GAIN 2 = ×2.8.
11 = GAIN 3 = ×4.2 (user gain calibration is required for this gain setting).
R/W 0 7 VREFBUF VREF buffer enable.
0 (default) = disabled.
1 = enabled (when using the internal VREF, VREFBUF must be enabled).
R/W 0 6 CLKEXT Use external clock instead of crystal oscillator. When a device is configured as a master, the user can
choose between an external crystal supplying the clock or an external clock source applied to the
CLK_IO pin. The crystal oscillator is automatically disabled if configured as a slave in gang mode, and
the slave device receives the clock from the master device. Note that the device powers up by default
using an internal clock and switches to the appropriate clock (XTAL or CLK_IO) when configured on the
first write to the CLKEXT bit.
0 (default) = XTAL is clock source.
1 = CLK_IO is clock source.
R/W 0 5 Master In gang mode, this bit selects the master (SYNC_GANG pin is configured as an output). When in single
channel mode (gang = 0), this bit is ignored. ADAS1000-2 cannot be configured as a master device.
0 (default) = slave.
1 = master.
R/W 0 4 Gang Enable gang mode. Setting this bit causes CLK_IO and SYNC_GANG to be activated.
0 (default) = single channel mode.
1 = gang mode.
R/W 0 3 HP Selects the noise/power performance. This bit controls the ADC sampling frequency. See the
Specifications section for further details. This bit also affects the respiration carrier frequency as
discussed in the Respiration Carrier Frequency section.
0 (default) = 1 MSPS, low power.
1 = 2 MSPS, high performance/low noise.
R/W 0 2 CNVEN Conversion enable. Setting this bit enables the ADC conversion and filters.
0 (default) = idle.
1 = conversion enable.
R/W 0 1 PWREN Power enable. Clearing this bit powers down the device. All analog blocks are powered down and the
external crystal is disabled. The register contents are retained during power down as long as DVDD is
not removed.
0 (default) = power down.
1 = power enable.

Rev. C | Page 61 of 85
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet
R/W Default Bit Name Function
R/W 0 0 SWRST Software reset. Setting this bit clears all registers to their reset value. This bit automatically clears itself.
The software reset requires a NOP command to complete the reset.
0 (default) = NOP.
1 = reset.

Rev. C | Page 62 of 85
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2

Table 29. Lead-Off Control Register (LOFFCTL) Address 0x02, Reset Value = 0x000000
R/W Default Bit Name Function
R/W 0 23 LAPH AC lead-off phase.
R/W 0 22 LLPH 0 (default) = in phase.
R/W 0 21 RAPH 1 = 180° out of phase.
R/W 0 20 V1PH
R/W 0 19 V2PH
R/W 0 18 CEPH
R/W 0 17 LAACLOEN Individual electrode ac lead-off enable. AC lead-off enables are the OR of ACSEL and the
R/W 0 16 LLACLOEN individual ac lead-off channel enables.
R/W 0 15 RAACLOEN 0 (default) = ac lead-off disabled.
R/W 0 14 V1ACLOEN 1 = ac lead-off enabled.
R/W 0 13 V2ACLOEN
R/W 0 12 CEACLOEN
R 0 [11:9] Reserved Reserved, set to 0.
R/W 00 [8:7] ACCURRENT Set current level for ac lead-off.
00 (default) = 12.5 nA rms.
01 = 25 nA rms.
10 = 50 nA rms.
11 = 100 nA rms.
00 [6:5] Reserved Reserved, set to 0.
R/W 000 [4:2] DCCURRENT Set current level for dc lead-off (active only for ACSEL = 0).
000 (default) = 0 nA.
001 = 10 nA.
010 = 20 nA.
011 = 30 nA.
100 = 40 nA.
101 = 50 nA.
110 = 60 nA.
111 = 70 nA.
R/W 0 1 ACSEL DC or AC (out-of-band) lead-off detection.
ACSEL acts as a global ac lead-off enable for RA, LL, LA, V1, V2 electrodes (CE ac lead-off is not
enabled using ACSEL). AC lead-off enables are the OR of ACSEL and the individual ac lead-off
channel enables.
If LOFFEN = 0, this bit is don’t care.
If LOFFEN = 1,
0 (default) = dc lead-off detection enabled (individual ac lead-off can be enabled through
Bits[17:12]).
1 = dc lead-off detection disabled. AC lead-off detection enabled (all electrodes except CE
electrode).
When the calibration DAC is enabled, ac lead-off is disabled.
R/W 0 0 LOFFEN Enable lead-off detection.
0 (default) = lead-off disabled.
1 = lead-off enabled.

Rev. C | Page 63 of 85
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet
Table 30. Respiration Control Register (RESPCTL) Address 0x03, Reset Value = 0x000000 1
R/W Default Bit Name Function
[23:17] Reserved Reserved, set to 0.
R/W 0 16 RESPALTFREQ Setting this bit to 1 makes the respiration waveform on the GPIO3 pin periodic every cycle. Use in
conjunction with RESFREQ to select drive frequency.
0 (default) = periodic every N cycles (default).
1 = periodic every cycle.
R/W 0 15 RESPEXTSYNC Set this bit to 1 to drive the MSB of the respiration DAC out onto the GPIO3 pin. This signal can be
used to synchronize an external generator to the respiration carrier. It is a constant period only
when RESPALTFREQ = 1.
0 (default) = normal GPIO3 function.
1 = MSB of RESPDAC driven onto GPIO3 pin.
R/W 0 14 RESPEXTAMP For use with an external instrumentation amplifier with respiration circuit. Bypasses the on-chip
amplifier stage and input directly to the ADC. See Figure 71.
0 (default) = disabled.
1 = enabled.
R/W 0 13 RESPOUT Selects external respiration drive output. RESPDAC_RA is automatically selected when RESPCAP = 1
0 (default) = RESPDAC_LL and RESPDAC_RA.
1 = RESPDAC_LA and RESPDAC_RA.
R/W 0 12 RESPCAP Selects source of respiration capacitors.
0 (default) = use internal capacitors.
1 = use external capacitors.
R/W 0000 [11:8] RESPGAIN [3:0] Respiration in amp gain (saturates at 10).
0000 (default) = ×1 gain.
0001 = ×2 gain.
0010 = ×3 gain.
…
1000 = ×9 gain.
1001 = ×10 gain.
11xx = ×10 gain.
R/W 0 7 RESPEXTSEL Selects between EXT_RESP_LA or EXT_RESP_LL paths. Applies only if the external respiration is
selected in RESPSEL. EXT_RESP_RA is automatically enabled.
0 (default) = EXT_RESP_LL.
1 = EXT_RESP_LA.
R/W 00 [6:5] RESPSEL [1:0] Set leads for respiration measurement.
00 (default) = Lead I.
01 = Lead II.
10 = Lead III.
11 = external respiration path.
R/W 00 [4:3] RESPAMP Set the test tone amplitude for respiration drive signal.
00 (default) = amplitude/8.
01 = amplitude/4.
10 = amplitude/2.
11 = amplitude.
R/W 00 [2:1] RESPFREQ Set frequency for respiration.
RESPFREQ RESPALTFREQ = 0 RESPALTFREQ = 1 (periodic)
00 (default) 56 kHz 64 kHz
01 54 kHz 56.9 kHz
10 52 kHz 51.2 kHz
11 50 kHz 46.5 kHz
R/W 0 0 RESPEN Enable respiration.
0 (default) = respiration disabled.
1 = respiration enabled.
1
ADAS1000 model only, ADAS1000-1/ADAS1000-2 models do not contain these features.

Rev. C | Page 64 of 85
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2
Table 31. Pace Detection Control Register (PACECTL) Address 0x04, Reset Value = 0x000F88 1
R/W Default Bit Name Function
[23:12] Reserved Reserved, set to 0
R/W 1 11 PACEFILTW Pace width filter
0 = filter disabled
1 (default) = filter enabled
R/W 1 10 PACETFILT2 Pace Validation Filter 2
0 = filter disabled
1 (default) = filter enabled
R/W 1 9 PACETFILT1 Pace Validation Filter 1
0 = filter disabled
1 (default) = filter enabled
R/W 11 [8:7] PACE3SEL [1:0] Set lead for pace detection measurement
R/W 00 [6:5] PACE2SEL [1:0] 00 = Lead I
R/W 01 [4:3] PACE1SEL [1:0] 01 = Lead II
10 = Lead III
11 = Lead aVF
R/W 0 2 PACE3EN Enable pace detection algorithm
R/W 0 1 PACE2EN 0 (default) = pace detection disabled
R/W 0 0 PACE1EN 1 = pace detection enabled
1
ADAS1000 model only, ADAS1000-1/ADAS1000-2 models do not contain these features.

Rev. C | Page 65 of 85
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet

Table 32. Common-Mode, Reference, and Shield Drive Control Register (CMREFCTL) Address 0x05, Reset Value = 0xE00000
R/W Default Bit Name Function
R/W 1 23 LACM Common-mode electrode select.
R/W 1 22 LLCM Any combination of the five input electrodes can be used to create the common-mode
R/W 1 21 RACM signal, VCM. Bits[23:19] are ignored when Bit 2 is selected. Common mode is the average of
R/W 0 20 V1CM the selected electrodes. When a single electrode is selected, common mode is the signal
level of that electrode alone. The common-mode signal can be driven from the internal
R/W 0 19 V2CM VCM_REF (1.3 V) when Bits [23:19] = 0.
0 = does not contribute to the common mode.
1 = contributes to the common mode.
0 [18:15] Reserved Reserved, set to 0.
R/W 0 14 LARLD RLD summing junction. Note that if the RLD amplifier is disabled (using RLDSEL), these
R/W 0 13 LLRLD switches are not automatically forced open, and the user must disable them using Bits[9:14].
R/W 0 12 RARLD 0 (default) = does not contribute to RLD input.
R/W 0 11 V1RLD 1 = contributes to RLD input.
R/W 0 10 V2RLD
R/W 0 9 CERLD
R/W 0 8 CEREFEN Common electrode (CE) reference, see Figure 58.
0 (default) = common electrode disabled.
1 = common electrode enabled.
R/W 0000 [7:4] RLDSEL [3:0]1 Select electrode for reference drive.
0000 (default) = RLD_OUT.
0001 = LA.
0010 = LL.
0011 = RA.
0100 = V1.
0101 = V2.
0110 to 1111 = reserved.
R/W 0 3 DRVCM Common-mode output. When set, the internally derived common-mode signal is driven out
of the common-mode pin. This bit has no effect if an external common mode is selected.
0 (default) = common mode is not driven out.
1 = common mode is driven out of the external common-mode pin.
R/W 0 2 EXTCM Select the source of common mode (use when operating multiple devices together).
0 (default) = internal common mode selected.
1 = external common mode selected (all the internal common-mode switches are off ).
R/W 0 1 RLDEN1 Enable right leg drive reference electrode.
0 (default) = disabled.
1 = enabled.
R/W 0 0 SHLDEN 1 Enable shield drive.
0 (default) = shield drive disabled.
1 = shield drive enabled.
1
ADAS1000 and ADAS1000-1 models only, ADAS1000-2 models does not contain these features.

Rev. C | Page 66 of 85
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2
Table 33. GPIO Control Register (GPIOCTL) Address 0x06, Reset Value = 0x000000
R/W Default Bit Name Function
0 [23:19] Reserved Reserved, set to 0
R/W 0 18 SPIFW Frame secondary SPI words with chip select
0 (default) = MCS asserted for entire frame
1 = MCS asserted for individual word
R/W 0 17 Reserved Reserved, set to 0
R/W 0 16 SPIEN Secondary SPI enable (ADAS1000 and ADAS1000-1 only); SPI interface providing ECG data at
128 kHz data rate for external digital pace algorithm detection, uses GPIO0, GPIO1, GPIO2 pins
0 (default) = disabled
1 = enabled; he individual control bits for GPIO0, GPIO1, GPIO2 are ignored; GPIO3 is not affected by SPIEN
R/W 00 [15:14] G3CTL [1:0] State of GPIO3 pin
00 (default) = high impedance
01 = input
10 = output
11 = open drain
R/W 0 13 G3OUT Output value to be written to GPIO3 when the pin is configured as an output or open drain
0 (default) = low value
1 = high value
R 0 12 G3IN Read only; input value read from GPIO3 when the pin is configured as an input
0 (default) = low value
1 = high value
R/W 00 [11:10] G2CTL [1:0] State of GPIO2 pin
00 (default) = high impedance
01 = input
10 = output
11 = open drain
R/W 0 9 G2OUT Output value to be written to GPIO2 when the pin is configured as an output or open drain
0 (default) = low value
1 = high value
R 0 8 G2IN Read only Input value read from GPIO2 when the pin is configured as an input
0 (default) = low value
1 = high value
R/W 00 [7:6] G1CTL [1:0] State of GPIO1 pin
00 (default) = high impedance
01 = input
10 = output
11 = open drain
R/W 0 5 G1OUT Output value to be written to GPIO1 when the pin is configured as an output or open drain
0 (default) = low value
1 = high value
R 0 4 G1IN Read only; input value read from GPIO1 when the pin is configured as an input
0 (default) = low value
1 = high value
R/W 00 [3:2] G0CTL [1:0] State of the GPIO0 pin
00 (default) = high impedance
01 = input
10 = output
11 = open drain
R/W 0 1 G0OUT Output value to be written to GPIO0 when pin is configured as an output or open drain
0 (default) = low value
1 = high value
R 0 0 G0IN (Read only) input value read from GPIO0 when pin is configured as an input
0 (default) = low value
1 = high value

Rev. C | Page 67 of 85
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet
Table 34. Pace Amplitude Threshold Register (PACEAMPTH) Address 0x07, Reset Value = 0x242424 1
R/W Default Bit Name Function
R/W 0010 0100 [23:16] PACE3AMPTH Pace amplitude threshold
R/W 0010 0100 [15:8] PACE2AMPTH Threshold = N × 2 × VREF/GAIN/216
R/W 0010 0100 [7:0] PACE1AMPTH
1
ADAS1000 model only, ADAS1000-1/ADAS1000-2 models do not contain these features.

Table 35. Test Tone Register (TESTTONE) Address 0x08, Reset Value = 0x000000
R/W Default Bit Name Function
R/W 0 23 TONLA Tone select
R/W 0 22 TONLL 0 (default) = 1.3 V VCM_REF
R/W 0 21 TONRA 1 = 1 mV sine wave or square wave for TONINT = 1, no connect for TONINT = 0
R/W 0 20 TONV1
R/W 0 19 TONV2
R/W 0 [18:5] Reserved Reserved, set to 0
R/W 00 [4:3] TONTYPE 00 (default) = 10 Hz sine wave
01 = 150 Hz sine wave
1× = 1 Hz, 1 mV square wave
R/W 0 2 TONINT Test tone internal or external
0 (default) = external test tone; test tone to be sent out through CAL_DAC_IO and
applied externally to enabled channels
1 = internal test tone; disconnects external switches for all ECG channels and
connects the calibration DAC test tone internally to all ECG channels; in gang
mode, the CAL_DAC_IO is connected, and the slave disables the calibration DAC
R/W 0 1 TONOUT Test tone out enable
0 (default) = disconnects test tone from CAL_DAC_IO during internal mode only
1 = connects CAL_DAC_IO to test tone during internal mode
R/W 0 0 TONEN Enables an internal test tone to drive entire signal chain, from preamplifier to SPI
interface; this tone comes from the calibration DAC and goes to the preamplifier
through the internal mux; when TONEN (calibration DAC) is enabled, ac lead-off is
disabled
0 (default) = disable the test tone
1 = enable the 1 mV sine wave test tone (calibration mode has priority)

Rev. C | Page 68 of 85
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2
Table 36. Calibration DAC Register (CALDAC) Address 0x09, Reset Value = 0x002000 1
R/W Default Bit Name Function
0 [23:14] Reserved Reserved, set to 0.
R/W 1 13 CALCHPEN Calibration chop clock enable. The calibration DAC output (CAL_DAC_IO) can be
chopped to lower 1/f noise. Chopping is performed at 256 kHz.
0 = disabled.
1 (default) = enabled.
R/W 0 12 CALMODEEN Calibration mode enable.
0 (default) = disable calibration mode.
1 = enable calibration mode; connect CAL DAC_IO, begin data acquisition on ECG channels.
R/W 0 11 CALINT Calibration internal or external.
0 (default) = external calibration to be performed externally by looping CAL_DAC_IO
around into ECG channels.
1 = internal calibration; disconnects external switches for all ECG channels and
connects calibration DAC signal internally to all ECG channels.
R/W 0 10 CALDACEN Enable 10-bit calibration DAC for calibration mode or external use.
0 (default) = disable calibration DAC.
1 = enable calibration DAC. If a master device and not in calibration mode, also connects
the calibration DAC signal out to the CAL_DAC_IO pin for external use. If in slave mode,
the calibration DAC is disabled to allow master to drive the slave CAL_DAC_IO pin. When
the calibration DAC is enabled, ac lead-off is disabled.
R/W 0000000000 [9:0] CALDATA[9:0] Set the calibration DAC value.
1
To ensure successful update of the calibration DAC, the serial interface must issue four additional SCLK cycles after writing the new calibration DAC register word.

Rev. C | Page 69 of 85
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet

Table 37. Frame Control Register (FRMCTL) Address 0x0A, Reset Value = 0x079000
R/W Default Bit Name Function
R/W 0 23 LEAD I/LADIS Include/exclude word from ECG data frame. If the electrode/lead is included in the data-
R/W 0 22 LEADII/LLDIS word and the electrode falls off, the data-word is undefined.
R/W 0 21 LEADIII/RADIS 0 (default) = included in frame.
R/W 0 20 V1DIS 1 = exclude from frame.
R/W 0 19 V2DIS
R/W 1111 [18:15] Reserved Reserved, set to 1111.
R/W 0 14 PACEDIS1 Pace detection.
0 (default) = included in frame.
1 = exclude from frame.
R/W 0 13 RESPMDIS 1 Respiration magnitude.
0 (default) = included in frame.
1 = exclude from frame.
R/W 1 12 RESPPHDIS1 Respiration phase.
0 = included in frame.
1 (default) = exclude from frame.
R/W 0 11 LOFFDIS Lead-off status.
0 (default) = included in frame.
1 = exclude from frame.
R/W 0 10 GPIODIS GPIO word disable.
0 (default) = included in frame.
1 = exclude from frame.
R/W 0 9 CRCDIS CRC word disable.
0 (default) = included in frame.
1 = exclude from frame.
R/W 0 8 RESERVED Reserved, set to 0.
R/W 0 7 ADIS Automatically excludes PACEDIS[14], RESPMDIS[13], LOFFDIS[11] words if their flags are
not set in the header.
0 (default) = fixed frame format.
1 = autodisable words (words per frame changes).
R/W 0 6 RDYRPT Ready repeat. If this bit is set and the frame header indicates data is not ready, the frame
header is continuously sent until data is ready.
0 (default) = always send entire frame.
1 = repeat frame header until ready.
R/W 0 5 Reserved Reserved, set to 0 .
R/W 0 4 DATAFMT Sets the output data format, see Figure 58.
0 (default) = digital lead/vector format (available only in 2 kHz and 16 kHz data rates).
1 = electrode format.
R/W 00 [3:2] SKIP[1:0] Skip interval. This field provides a way to decimate the data.
00 (default) = output every frame.
01 = output every other frame.
1× = output every 4th frame.
R/W 00 [1:0] FRMRATE[1:0] Sets the output data rate.
00 (default) = 2 kHz output data rate.
01 = 16 kHz output data rate.
10 = 128 kHz output data rate (DATAFMT must be set to 1).
11 = 31.25 Hz.
1
ADAS1000 model only, ADAS1000-1/ADAS1000-2 models do not contain these features.

Rev. C | Page 70 of 85
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2
Table 38. Filter Control Register (FILTCTL) Address 0x0B, Reset Value = 0x000000
R/W Default Bit Name Function
R/W 0 [23:6] Reserved Reserved, set to 0
R/W 0 5 MN2K 2 kHz notch bypass for SPI master
0 (default) = notch filter bypassed
1 = notch filter present
R/W 0 4 N2KBP 2 kHz notch bypass
0 (default) = notch filter present
1 = notch filter bypassed
R/W 00 [3:2] LPF[1:0] 00 (default) = 40 Hz
01 = 150 Hz
10 = 250 Hz
11 = 450 Hz
R/W 00 [1:0] Reserved Reserved, set to 0

Table 39. AC Lead-Off Upper Threshold Register (LOFFUTH) Address 0x0C, Reset Value = 0x00FFFF
R/W Default Bit Name Function
0 [23:20] Reserved Reserved, set to 0
R/W 0 [19:16] ADCOVER[3:0] ADC overrange threshold
An ADC out-of-range error is flagged if the ADC output is greater than the overrange
threshold; the overrange threshold is offset from the maximum value
Threshold = max_value – ADCOVER × 26
0000 = maximum value (disabled)
0001 = max_value – 64
0010 = max_value – 128
…
1111 = max_value − 960
R/W 0xFFFF [15:0] LOFFUTH[15:0] Applies to ac lead-off upper threshold only; lead-off is detected if the output is ≥ N ×
2 × VREF/GAIN/216
0=0V

Table 40. AC Lead-Off Lower Threshold Register (LOFFLTH) Address 0x0D, Reset Value = 0x000000
R/W Default Bit Name Function
0 [23:20] Reserved Reserved, set to 0
R/W 0 [19:16] ADCUNDR[3:0] ADC underrange threshold
An ADC out-of-range error is flagged if the ADC output is less than the underrange
threshold
Threshold = min_value + ADCUNDR × 26
0000 = minimum value (disabled)
0001 = min_value + 64
0010 = min_value + 128
…
1111 = min_value + 960
R/W 0 [15:0] LOFFLTH[15:0] Applies to ac lead-off lower threshold only; lead-off is detected if the output is ≤ N ×
2 × VREF/GAIN/216
0=0V

Rev. C | Page 71 of 85
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet
Table 41. Pace Edge Threshold Register (PACEEDGETH) Address 0x0E, Reset Value = 0x000000 1
R/W Default Bit Name Function
R/W 0 [23:16] PACE3EDGTH Pace edge trigger threshold
R/W 0 [15:8] PACE2EDGTH 0 = PACEAMPTH/2
R/W 0 [7:0] PACE1EDGTH 1 = VREF/GAIN/216
N = N × VREF/GAIN/216
1
ADAS1000 model only, ADAS1000-1/ADAS1000-2 models do not contain these features.

Table 42. Pace Level Threshold Register (PACELVLTH) Address 0x0F, Reset Value = 0x000000 1
R/W Default Bit Name Function
R/W 0 [23:16] PACE3LVLTH[7:0] Pace level threshold; this is a signed value
R/W 0 [15:8] PACE2LVLTH[7:0] −1 = 0xFF = −VREF/GAIN/216
R/W 0 [7:0] PACE1LVLTH[7:0] 0 = 0x00 = 0 V
+1 = 0x01 = +VREF/GAIN/216
N = N × VREF/GAIN/216
1
ADAS1000 model only, ADAS1000-1/ADAS1000-2 models do not contain these features.

Table 43. Read Electrode/Lead Data Registers (Electrode/Lead) Address 0x11 to 0x15, Reset Value = 0x000000 1
R/W Default Bit Name Function
[31:24] Address [7:0] 0x11: LA or Lead I.
0x12: LL or Lead II.
0x13: RA or Lead III.
0x14: V1 or V1’.
0x15: V2 or V2’.
R 0 [23:0] ECG data Channel data value. Data left justified (MSB) irrespective of data rate.
The input stage can be configured into different modes (electrode, analog lead, or digital
lead) as shown in Table 11. In electrode mode and analog lead mode, the digital result
value is an unsigned integer.
Electrode mode and analog lead mode:
Minimum value (000…) = 0 V
Maximum value (1111….) = 2 × VREF/GAIN
LSB = (2 × VREF/GAIN)/(2N – 1)
ECG (voltage) = ECG Data × (2 × VREF/GAIN)/(2N – 1)
In digital lead/vector mode, the value is a signed twos complement integer format and has
a 2× range compared to electrode format because it can swing from +VREF to –VREF.
Therefore, the LSB size is doubled.
Digital lead mode:
Minimum value (1000…) = −(2 VREF/GAIN)
Maximum value (0111….) = +(2 VREF/GAIN)
LSB = (4 × VREF/GAIN)/(2N – 1)
ECG (voltage) = ECG Data × (4 × VREF/GAIN)/(2N – 1)
where N = number of data bits: 16 for 128 kHz data rate or 24 for 2 kHz/16 kHz data rate.
1
If using 128 kHz data rate in frame mode, only the upper 16 bits are sent. If using the 128 kHz data rate in regular read/write mode, all 32 bits are sent.

Rev. C | Page 72 of 85
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2
Table 44. Read Pace Detection Data/Status Register (PACEDATA) Address 0x1A, Reset Value = 0x000000 1, 2, 3
R/W Default Bit Name Function
R 0 23 Pace 3 detected Pace 3 detected. This bit is set once a pace pulse is detected. This bit is set on the
trailing edge of the pace pulse.
0 = pace pulse not detected in current frame.
1 = pace pulse detected in this frame.
R 000 [22:20] Pace Channel 3 width This bit is log2 (width) − 1 of the pace pulse.
Width = 2N + 1/128 kHz.
R 0000 [19:16] Pace Channel 3 height This bit is the log2 (height) of the pace pulse.
Height = 2N × 2 VREF/GAIN/216.
R 0 15 Pace 2 detected Pace 2 detected. This bit is set once a pace pulse is detected. This bit is set on the
trailing edge of the pace pulse.
0 = pace pulse not detected in current frame.
1 = pace pulse detected in this frame.
R 000 [14:12] Pace Channel 2 width This bit is log2 (width) − 1 of the pace pulse.
Width = 2N + 1/128 kHz.
R 0000 [11:8] Pace Channel 2 height This bit is the log2 (height) of the pace pulse.
Height = 2N × 2 VREF/GAIN/216.
R 0 7 Pace 1 detected Pace 1 detected. This bit is set once a pace pulse is detected. This bit is set on the
trailing edge of the pace pulse.
0 = pace pulse not detected in current frame.
1 = pace pulse detected in this frame.
R 000 [6:4] Pace Channel 1 width This bit is log2 (width) − 1 of the pace pulse.
Width = 2N + 1/128 kHz.
R 0000 [3:0] Pace Channel 1 height This bit is the log2 (height) of the pace pulse.
Height = 2N × 2 VREF/GAIN/216.
1
If using 128 kHz data rate in frame mode, this word is stretched over two 16-bit words. If using the 128 kHz data rate in regular read/write mode, all 32 bits are sent.
2
Log data for width and height is provided here to ensure that it fits in one full 32-bit data-word. As a result there may be some amount of error in the resulting value.
For more accurate reading, read Register 0x3A, Register 0x3B, and Register 0x3C (see Table 53).
3
ADAS1000 model only, ADAS1000-1/ADAS1000-2 models do not contain these features.

Table 45. Read Respiration Data—Magnitude Register (RESPMAG) Address 0x1B, Reset Value = 0x000000 1, 2
R/W Default Bit Name Function
R 0 [23:0] Respiration magnitude[23:0] Magnitude of respiration signal. This is an unsigned value.
4 × (VREF/(1.6468 × respiration gain))/(224 – 1).
1
If using 128 kHz data rate in frame mode, this word is stretched over two 16-bit words. If using the 128 kHz data rate in regular read/write mode, all 32 bits are sent.
2
ADAS1000 model only, ADAS1000-1/ADAS1000-2 models do not contain these features.

Table 46. Read Respiration Data—Phase Register (RESPPH) Address 0x1C, Reset Value = 0x000000 1, 2
R/W Default Bit Name Function
R 0 [23:0] Respiration Phase of respiration signal. Can be interpreted as either signed or unsigned value. If
phase[23:0] unsigned, the range is from 0 to 2π. If signed, the range is from – π to +π.
0x000000 = 0.
0x000001 = 2π/224.
0x400000 = π/2.
0x800000 = +π = − π.
0xC00000 = +3π/2 = − π/2.
0xFFFFFF = +2π(1 − 2−24) = −2π/224.
1
This register is not part of framing data, but may be read by issuing a register read command of this address.
2
ADAS1000 model only, ADAS1000-1/ADAS1000-2 models do not contain these features.

Rev. C | Page 73 of 85
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet
Table 47. Lead-Off Status Register (LOFF) Address 0x1D, Reset Value = 0x000000
R/W Default Bit Name Function
R 0 23 RLD lead-off status Electrode connection status.
22 LA lead-off status If either dc or ac lead-off is enabled, these bits are the corresponding lead-off status. If both dc
21 LL lead-off status and ac lead-off are enabled, these bits reflect only the ac lead-off status. DC lead-off is
available in the DCLEAD-OFF register (see Table 48).
20 RA lead-off status
19 V1 lead-off status The common electrodes have only dc lead-off detection.
18 V2 lead-off status An ac lead-off signal can be injected into the common electrode, but there is no ADC input to
13 CE lead-off status measure its amplitude. If the common electrode is off, it affects the ac lead-off amplitude of
the other electrodes.
These bits accumulate in the frame buffer and are cleared when the frame buffer is loaded
into the SPI buffer.
0 = electrode is connected.
1 = electrode is disconnected.
RLD lead-off is not detected in ac lead-off.
R 0 [17:14] Reserved Reserved.
R 0 12 LAADCOR ADC out of range error for each ADC channel.
11 LLADCOR These status bits indicate the resulting ADC code is out of range.
10 RAADCOR These bits accumulate in the frame buffer and are cleared when the frame buffer is loaded
9 V1ADCOR into the SPI buffer.
8 V2ADCOR These bits report which ADC channel is out of range. If in electrode mode, the bits indicate
which of the electrodes is out of range. If the device is configured in lead mode (analog or
digital lead mode), the out of range bits indicate the channel and/or lead combination is out
of range. The ADC out of range feature requires the upper and lower threshold levels to be set
at a value that is not the default. The appropriate thresholds are programmed using the
ADCOVER bits in the LOFFUTH register and the ADCUNDR bits in the LOFFLTH register.
R 0 [7:0] Reserved Reserved.

Rev. C | Page 74 of 85
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2
Table 48. DC Lead-Off Register (DCLEAD-OFF) Address 0x1E, Reset Value = 0x000000 1
R/W Default Bit Name Function
R 0 23 RLD input The dc lead-off detection is comparator based and compares to a fixed level. Individual
overrange electrode bits flag indicate if the dc lead-off comparator threshold level has been exceeded.
22 LA input overrange 0 = electrode < overrange threshold, 2.4 V.
21 LL input overrange 1 = electrode > overrange threshold, 2.4 V.
20 RA input
overrange
19 V1 input overrange
18 V2 input overrange
13 CE input overrange
R 0 [17:14] Reserved Reserved.
[6:3]
R 0 12 RLD input The dc lead-off detection is comparator based and compares to a fixed level. Individual
underrange electrode bits indicate if the dc lead-off comparator threshold level has been exceeded.
11 LA input 0 = electrode > underrange threshold, 0.2 V.
underrange
10 LL input 1 = electrode < underrange threshold, 0.2 V.
underrange
9 RA input
underrange
8 V1 input
underrange
7 V2 input
underrange
2 CE input
underrange
R 0 [1:0] Reserved
1
This register is not part of framing data, but can be read by issuing a register read command of this address.

Table 49. Operating State Register (OPSTAT) Address 0x1F, Reset Value = 0x000000 1
R/W Default Bit Name Function
R 0 [23:4] Reserved Reserved.
R 0 3 Internal error Internal digital failure. This is set if an error is detected in the digital core.
R 0 2 Configuration status This bit is set after a reset indicating that the configuration has not been read yet.
Once the configuration is set, this bit is ready.
0 = ready.
1 = busy.
R 0 1 PLL lock PLL lock lost. This bit is set if the internal PLL loses lock after it is enabled and locked.
This bit is cleared once this register is read or the PWREN bit (Address 0x01[1]) is cleared.
0 = PLL locked.
1 = PLL lost lock.
R 0 0 PLL locked status This bit indicates the current state of the PLL locked status.
0 = PLL not locked.
1 = PLL locked.
1
This register is not part of framing data, but can be read by issuing a register read command of this address. This register assists support efforts giving insight into
potential areas of malfunction within a failing device.

Rev. C | Page 75 of 85
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet
Table 50. Extended Switch for Respiration Inputs Register (EXTENDSW) Address 0x20, Reset Value = 0x000000
R/W Default Bit Name Switch Function
R/W 0 23 EXT_RESP_RA to ECG1_LA SW1a External respiration electrode input switch to channel electrode input (see
22 EXT_RESP_RA to ECG2_LL SW1b Figure 72). 1
21 EXT_RESP_RA to ECG3_RA SW1c 0 = switch open.
20 EXT_RESP_RA to ECG4_V1 SW1d 1 = switch closed.
19 EXT_RESP_RA to ECG5_V2 SW1e
18 EXT_RESP_LL to ECG1_LA SW2a
17 EXT_RESP_LL to ECG2_LL SW2b
16 EXT_RESP_LL to ECG3_RA SW2c
15 EXT_RESP_LL to ECG4_V1 SW2d
14 EXT_RESP_LL to ECG5_V2 SW2e
13 EXT_RESP_LA to ECG1_LA SW3a
12 EXT_RESP_LA to ECG2_LL SW3b
11 EXT_RESP_LA to ECG3_RA SW3c
10 EXT_RESP_LA to ECG4_V1 SW3d
9 EXT_RESP_LA to ECG5_V2 SW3e
R/W 0 8 AUX_V1 V1 and V2 electrodes can be used for measurement purposes other than ECG.
R/W 0 7 AUX_V2 To achieve this, they must be disconnected from the patient VCM voltage
provided from the internal common-mode buffer and, instead, connected to
the internal VCM_REF level of 1.3 V.
Setting the AUX_Vx bits high connects the negative input of the V1 and V2
channel amplifier to internal VCM_REF level. This allows the user to make
alternative measurements on V1 and V2 relative to the VCM_REF level.
Note that the V1 and V2 measurements are now being made outside of the
right leg drive loop, therefore there is increased noise on the measurement
as a result.
R/W 0 [6:0] Reserved Reserved, set to 0.
1
ADAS1000 model only, ADAS1000-1/ADAS1000-2 models do not contain these EXT_RESP_xx pins.

Table 51. User Gain Calibration Registers (CALxx) Address 0x21 to Address 0x25, Reset Value = 0x000000
R/W Default Bit Name Function
[31:24] Address [7:0] 0x21: calibration LA.
0x22: calibration LL.
0x23: calibration RA.
0x24: calibration V1.
0x25: calibration V2.
R/W 0 23 USRCAL User can choose between default calibration values or user calibration values for GAIN 0,
GAIN 1, GAIN 2.
Note that for GAIN 3, there is no factory calibration.
0 = default calibration values (factory calibration).
1 = user calibration values.
R/W 0 [22:12] Reserved Reserved, set to 0
R/W 0 [11:0] CALVALUE Gain calibration value.
Result = data × (1 + GAIN × 2−17).
The value read from this register is the current gain calibration value. If the USRCAL bit is set
to 0, this register returns the default value for the current gain setting.
0x7FF (+2047) = ×1.00000011111111111b.
0x001 (+1) = ×1.00000000000000001b.
0x000 (0) = ×1.00000000000000000b.
0xFFF (−1) = ×0.11111111111111111b.
0x800 (−2048) = ×0.11111100000000000b.

Rev. C | Page 76 of 85
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2
Table 52. Read AC Lead-Off Amplitude Registers (LOAMxx) Address 0x31 to Address 0x35, Reset Value = 0x000000 1
R/W Default Bit Name Function
[31:24] Address [7:0] These registers report the measured ac lead-off amplitude for each ECG channel.
0x31: LA or Lead I ac lead-off amplitude.
0x32: LL or Lead II ac lead-off amplitude.
0x33: RA or Lead III ac lead-off amplitude.
0x34: V1 ac lead-off amplitude.
0x35: V2 ac lead-off amplitude.
R/W 0 [23:16] Reserved Reserved.
R 0 [15:0] LOFFAM Measured amplitude.
When ac lead-off is selected, the data is the average of the rectified 2 kHz band-pass filter
with an update rate of 8 Hz and cutoff frequency at 2 Hz. The output is the amplitude of the
2 kHz signal scaled by 2/π approximately = 0.6 (average of rectified sine wave). To convert to
RMS, scale the output by π/(2√2).
Lead-off (unsigned).
Minimum 0x0000 = 0 V.
LSB 0x0001= VREF/GAIN/216.
Maximum 0xFFFF = VREF/GAIN.
RMS = [π/(2√2)] × [(Code × VREF)/(GAIN × 216)]
Peak-to-peak = π × [(Code × VREF)/(GAIN × 216)]
1
This register is not part of framing data, but can be read by issuing a register read command of this address.

Table 53. Pace Width and Amplitude Registers (PACExDATA) Address 0x3A to Address 0x3C, Reset Value = 0x000000 1,2
R/W Default Bit Name Function
[31:24] Address [7:0] 0x3A: PACE1DATA
0x3B: PACE2DATA
0x3C: PACE3DATA
R 0 [23:8] Pace height Measured pace height in signed two’s complement value
0=0
1 = VREF/GAIN/216
N = 2 × N × VREF/GAIN/216
R 0 [7:0] Pace width Measured pace width in 128 kHz samples
N: (N + 1)/128 kHz = width
12: (12 + 1)/128 kHz = 101.56 µs (minimum when pace width filter enabled)
255: (255 + 1)/128 kHz = 2.0 ms
Disabling the pace width filter allows the pace measurement system to
return values of N < 12, that is, pulses narrower than 101.56 μs.
1
These registers are not part of framing data but can be read by issuing a register read command of these addresses.
2
ADAS1000 model only, ADAS1000-1/ADAS1000-2 models do not contain these features.

Table 54. Frame Header (FRAMES) Address 0x40, Reset Value = 0x800000 1
R/W Default Bit Name Function
R 1 31 Marker Header marker, set to 1 for the header.
R 0 30 Ready bit Ready bit indicates if ECG frame data is calculated and ready for reading.
0 = ready, data frame follows.
1 = busy.
R 0 [29:28] Overflow [1:0] Overflow bits indicate that since the last frame read, a number of frames have
been missed. This field saturates at the maximum count. The data in the frame
including this header word is valid but old if the overflow bits are >0.
When using skip mode (FRMCTL register (0x0A), Bits[3:2]), the overflow bit acts as a
flag, where a nonzero value indicates an overflow.
00 = 0 missed.

Rev. C | Page 77 of 85
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet
R/W Default Bit Name Function
01 = 1 frame missed.
10 = 2 frames missed.
11 = 3 or more frames missed.
R 0 27 Fault Internal device error detected.
0 = normal operation.
1 = error condition.
R 0 26 Pace 3 detected Pace 3 indicates pacing artifact was qualified at most recent point.
0 = no pacing artifact.
1 = pacing artifact present.
R 0 25 Pace 2 detected Pace 2 indicates pacing artifact was qualified at most recent point.
0 = no pacing artifact.
1 = pacing artifact present.
R 0 24 Pace 1 detected Pace 1 indicates pacing artifact was qualified at most recent point.
0 = no pacing artifact.
1 = pacing artifact present.
R 0 23 Respiration 0 = no new respiration data.
1 = respiration data updated.
R 0 22 Lead-off detected If both dc and ac lead-off are enabled, this bit is the OR of all the ac lead-off detect
flags. If only ac or dc lead-off is enabled, this bit reflects the OR of all dc and ac
lead-off flags.
0 = all leads connected.
1 = one or more lead-off detected.
R 0 21 DC lead-off detected 0 = all leads connected.
1 = one or more lead-off detected.
R 0 20 ADC out of range 0 = ADC within range.
1 = ADC out of range.
0 [19:0] Reserved Reserved
1
If using 128 kHz data rate in frame mode, only the upper 16 bits are sent. If using the 128 kHz data rate in regular read/write mode, all 32 bits are sent.

Table 55. Frame CRC Register (CRC) Address 0x41, Reset Value = 0xFFFFFF 1
R/W Bit Name Function
R [23:0] CRC Cyclic redundancy check
1
The CRC register is a 32-bit word for 2 kHz and 16 kHz data rate and a 16-bit word for 128 kHz rate. See Table 24 for more details.

Rev. C | Page 78 of 85
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2
EXAMPLES OF INTERFACING TO THE ADAS1000
The following examples shows register commands required to Example 2: Enable Respiration and Stream Conversion
configure the ADAS1000 device into particular modes of Data
operation and to start framing ECG data. 1. Write 1 configures the RESPCTL register with a 56 kHz
Example 1: Initialize the ADAS1000 for ECG Capture and respiration drive signal, gain = 1, driving out through
Start Streaming Data the respiration capacitors and measuring on Lead I.
1. Write 1 configures the CMREFCTL register for CM = 2. Write 2 issues the read command to start putting the
WCT = (LA + LL + RA)/3; RLD is enabled onto the converted data out on the SDO pin.
RLD_OUT electrode. The shield amplifier is enabled. 3. Continue to issue SCLK cycles to read the converted data
2. Write 2 configures the FRMCTL register to output nine at the configured packet data rate.
words per frame/packet. The frame/packet of words 4. Note that this example assumes that the FRMCTL register
consist of the header, five ECG words, pace, respiration has already been configured such that the respiration
magnitude, and lead-off. The frame is configured to magnitude is available in the data frame, as arranged in
always send, irrespective of ready status. The ADAS1000 Write 2 of Example 1.
is in analog lead format mode with a data rate of 2 kHz. Example 3: DC Lead-Off and Stream Conversion Data
3. Write 3 addresses the ECGCTL register, enabling all
1. Write 1 configures the LOFFCTL register with a dc lead-off
channels into a gain of 1.4, low noise mode, and differen-
enabled for a lead-off current of 50 nA.
tial input, which configures the device for analog lead
2. Write 2 issues the read command to start putting the
mode. This register also configures the device as a master,
converted data out on the SDO pin.
using the external crystal as the input source to the
3. Continue to issue SCLK cycles to read the converted
XTALx pins. The ADAS1000 is also put into conversion
data at the configured packet data rate.
mode in this write.
4. Note that this example assumes that the FRMCTL register
4. Write 4 issues the read command to start putting the
has already been configured such that the dc lead-off word
converted data out on the SDO pin.
is available in the data frame, as arranged in Write 2 of
5. Continue to issue SCLK cycles to read the converted data
Example 1.
at the configured packet data rate (2 kHz). The SDI input
must be held low when reading back the conversion data
because any commands issued to the interface during read
of frame/packet are understood to be a change of configu-
ration data and stop the ADC conversions to allow the
interface to process the new command.

Table 56. Example 1: Initialize the ADAS1000 for ECG Capture and Start Streaming Data
Write Command Register Addressed Read/Write Bit Register Address Data 32-Bit Write Command
Write 1 CMREFCTL 1 000 0101 1110 0000 0000 0000 0000 1011 0x85E0000B
Write 2 FRMCTL 1 000 1010 0000 0111 1001 0110 0000 0000 0x8A079600
Write 3 ECGCTL 1 000 0001 1111 1000 0000 0100 1010 1110 0x81F804AE
Write 4 FRAMES 0 100 0000 0000 0000 0000 0000 0000 0000 0x40000000

Table 57. Example 2: Enable Respiration and Stream Conversion Data

Write Command Register Addressed Read/Write Bit Register Address Data 32-Bit Write Command
Write 1 RESPCTL 1 000 0011 0000 0000 0010 0000 1001 1001 0x83002099
Write 2 FRAMES 0 100 0000 0000 0000 0000 0000 0000 0000 0x40000000

Table 58. Example 3: Enable DC Lead-Off and Stream Conversion Data

Write Command Register addressed Read/Write Bit Register Address Data 32-Bit Write Command
Write 1 LOFFCTL 1 000 0010 0000 0000 0000 0000 0001 0101 0x82000015
Write 2 FRAMES 0 100 0000 0000 0000 0000 0000 0000 0000 0x40000000

Rev. C | Page 79 of 85
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet
Example 4: Configure 150 Hz Test Tone Sine Wave on Example 5: Enable Pace Detection and Stream
Each ECG Channel and Stream Conversion Data Conversion Data
1. Write 1 configures the CMREFCTL register to 1. Write 1 configures the PACECTL register with all three
VCM_REF = 1.3 V (no electrodes contribute to VCM). pace detection instances enabled, PACE1EN detecting on
RLD is enabled to RLD_OUT, and the shield amplifier Lead II, PACE2EN detecting on Lead I, and PACE3EN
enabled. detecting on Lead aVF. The pace width filter and validation
2. Write 2 addresses the TESTTONE register to enable the filters are also enabled.
150 Hz sine wave onto all electrode channels. 2. Write 2 issues the read command to start putting the
3. Write 3 addresses the FILTCTL register to change the internal converted data out on the SDO pin.
low-pass filter to 250 Hz to ensure that the 150 Hz sine 3. Continue to issue SCLK cycles to read the converted data
wave can pass through. at the configured packet data rate. When a valid pace is
4. Write 4 configures the FRMCTL register to output nine words detected, the detection flags are confirmed in the header
per frame/packet. The frame/packet of words consists of the word and the PACEDATA register contains information
header and five ECG words, pace, respiration magnitude, on the width and height of the measured pulse from each
and lead-off. The frame is configured to always send, measured lead.
irrespective of ready status. The ADAS1000 is in electrode 4. Note that the PACEAMPTH register default setting is
format mode with a data rate of 2 kHz. Electrode format is 0x242424, setting the amplitude of each of the pace
required to see the test tone signal correctly on each instances to 1.98 mV/gain.
electrode channel. 5. Note that this example assumes that the FRMCTL register
5. Write 5 addresses the ECGCTL register, enabling all has already been configured such that the PACEDATA
channels into a gain of 1.4, low noise mode. It configures word is available in the data frame, as arranged in Write 2
the device as a master and driven from the XTAL input of Example 1.
source. The ADAS1000 is also put into conversion mode
in this write.
6. Write 6 issues the read command to start putting the
converted data out on the SDO pin.
7. Continue to issue SCLK cycles to read the converted data
at the configured packet data rate.

Table 59. Example 4: Configure 150 Hz Test Tone Sine Wave on Each ECG Channel and Stream Conversion Data
Write Command Register Addressed Read/Write Bit Register Address Data 32-Bit Write Command
Write 1 CMREFCTL 1 000 0101 0000 0000 0000 0000 0000 1011 0x8500000B
Write 2 TESTTONE 1 000 1000 1111 1000 0000 0000 0000 1101 0x88F8000D
Write 3 FILTCTL 1 000 1011 0000 0000 0000 0000 0000 1000 0x8B000008
Write 4 FRMCTL 1 000 1010 0000 0111 1001 0110 0001 0000 0x8A079610
Write 5 ECGCTL 1 000 0001 1111 1000 0000 0000 1010 1110 0x81F800AE
Write 6 FRAMES 0 100 0000 0000 0000 0000 0000 0000 0000 0x40000000

Table 60. Example 5: Enable Pace Detection and Stream Conversion Data
Write Command Register Addressed Read/Write Bit Register Address Data 32-Bit Write Command
Write 1 PACECTL 1 000 0100 0000 0000 0000 1111 1000 1111 0x84000F8F
Write 2 FRAMES 0 100 0000 0000 0000 0000 0000 0000 0000 0x40000000

Rev. C | Page 80 of 85
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2
Example 6: Writing to Master and Slave Devices and In this example, the frame is configured to always send
Streaming Conversion Data irrespective of ready status. The master, ADAS1000, is in
vector mode format with a data rate of 2 kHz. Similar
Slave Configuration
to the slave device, the master may be configured for
1. Write 1 configures the FRMCTL register to output seven electrode mode; the host controller would then be required
words per frame/packet. The frame/packet of words consist to make the lead calculations.
of the header, five ECG words, and lead-off. The frame is 2. Write 6 configures the CMREFCTL register for CM =
configured to always send, irrespective of ready status. The WCT = (LA + LL + RA)/3; RLD is enabled onto
slave ADAS1000-2 is in electrode mode format with a data RLD_OUT electrode. The shield amplifier is enabled.
rate of 2 kHz. The CM = WCT signal is driven out of the master device
2. Write 2 configures the CMREFCTL register to receive an (CM_OUT) into the slave device (CM_IN).
external common mode from the master. 3. Write 7 addresses the ECGCTL register, powering up the
3. Write 3 addresses the ECGCTL register, which powers up device, enabling all channels into a gain of 1.4, low noise
the device and enables all channels to a gain of 1.4 in low mode. It configures the device as a master in gang mode
noise mode. This action configures the device as a slave in and driven from the XTAL input source. The ADAS1000
gang mode, driven from the CLK_IN input source (derived master is set to differential input, which places it in analog
from the master device, ADAS1000). The ECGCTL register lead mode.
write also enables conversions in the slave. This write 4. Write 8 is a read of the contents of the OPSTAT register to
operation can be broken into two steps, for example, assess if the PLL is locked. The PLL must be confirmed
power-up and configure in one write, followed by another locked prior to initiating conversions in the master device,
write to enable conversions. otherwise the slave device may not be fully powered on
4. Write 4 is a read of the contents of the OPSTAT register to and may miss the sync pulse from the master device.
assess if the PLL is locked. The PLL must be confirmed 5. If the OPSTAT register confirms the PLL is locked, then
locked prior to initiating conversions in the master device. Write 9 addresses the ECGCTL register, keeping the
Otherwise, the slave device may not be fully powered on configuration from Write 7 and initiating the master into
and may miss the sync pulse from the master device. conversion mode, where the master device sends an edge
Master Configuration on the SYNC_GANG pin to the slave device to trigger the
simultaneous conversions of both devices.
1. Write 5 configures the FRMCTL register to output nine 6. Write 10 issues the read command to start putting the
words per frame/packet (note that this differs from the converted and decimated data out on the SDO pin.
number of words in a frame available from the slave 7. Continue to issue SCLK cycles to read the converted data
device). The frame/packet of words consists of the header, at the configured packet data rate.
five ECG words, pace, respiration magnitude, and lead-off.
Table 61. Example 6: Writing to Master and Slave Devices and Streaming Conversion Data
Device Command Register Addressed R/W Register Address Data 32-Bit Write Command
Slave Write 1 FRMCTL 1 000 1010 0000 0111 1111 0110 0001 0000 0x8A07F610
Write 2 CMREFCTL 1 000 0101 0000 0000 0000 0000 0000 0100 0x85000004
Write 3 ECGCTL 1 000 0001 1111 1000 0000 0000 1101 1110 0x81F800DE
Read 4 OPSTAT 0 001 1111 0000 0000 0000 0000 0000 0000 0x1F000000
Master Write 5 FRMCTL 1 000 1010 0000 0111 1001 0110 0000 0000 0x8A079600
Write 6 CMREFCTL 1 000 0101 1110 0000 0000 0000 0000 1011 0x85E0000B
Write 7 ECGCTL 1 000 0001 1111 1000 0000 0100 1011 1010 0x81F804BA
Read 8 OPSTAT 0 001 1111 0000 0000 0000 0000 0000 0000 0x1F000000
Write 9 ECGCTL 1 000 0001 1111 1000 0000 0100 1011 1110 0x81F804BE
Read 10 FRAMES 0 100 0000 0000 0000 0000 0000 0000 0000 0x40000000

Rev. C | Page 81 of 85
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet
SOFTWARE FLOWCHART
Figure 84 shows a suggested sequence of steps to be taken to interface to multiple ADAS1000/ADAS1000-1/ADAS1000-2 devices.
POWER UP ADAS1000
DEVICES

WAIT FOR POR ROUTINE

TO COMPLETE, 1.5ms

INITIALIZE SLAVE
DEVICES

INITIALIZE MASTER DEVICE

ENABLING CONVERSION

ISSUE READ FRAME

COMMAND (WRITE TO 0x40)

NO DRDY
LOW?

YES

ISSUE SCLK CYCLES (SDI = 0)

TO CLOCK FRAME DATA OUT
AT PROGRAMMED DATA RATE

IS CRC NO DISCARD
CORRECT? FRAME DATA

YES

NO ACTIVITY
ON
SDI?

YES

ADAS1000 STOPS CONVERTING,

SDI WORD USED TO
RECONFIGURE DEVICE

RETURN NO
TO ECG
CAPTURE?

YES

ISSUE READ FRAME

COMMAND (WRITE TO 0x40)

NO
POWER-DOWN?

YES

ECG CAPTURE COMPLETE

POWER-DOWN ADAS1000
ECGCTL = 0x0
09660-038

ADAS1000 GOES INTO

POWER-DOWN MODE

Figure 84. Suggested Software Flowchart for Interfacing to Multiple ADAS1000/ADAS1000-1/ADAS1000-2 Devices

Rev. C | Page 82 of 85
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2
POWER SUPPLY, GROUNDING, AND DECOUPLING ADCVDD AND DVDD SUPPLIES
STRATEGY The AVDD supply rail powers the analog blocks in addition to
The ADAS1000/ADAS1000-1/ADAS1000-2 must have ample the internal 1.8 V regulators for the ADC and the digital core.
supply decoupling of 0.1 μF on each supply pin located as close If using the internal regulators, connect the VREG_EN pin to
to the device pin as possible, ideally right up against the device. AVDD and then use the ADCVDD and DVDD pins for
In addition, there must be one 4.7 μF capacitor for each of the decoupling purposes.
power domains, AVDD and IOVDD, again located as close to The DVDD regulator can be used to drive other external digital
the device as possible. IOVDD is best split from AVDD due to circuitry as required; however, the ADCVDD pin is purely
its noisy nature. provided for bypassing purposes and does not have available
Similarly, the ADCVDD and DVDD power domains each current for other components.
require one 2.2 μF capacitor with ESR in the range of 0.5 Ω to Where overall power consumption must be minimized, using
2 Ω. The ideal location for each 2.2 μF capacitor is dependent external 1.8 V supply rails for both ADCVDD and DVDD
on package type. For the LQFP package and DVDD decoupling, would provide a more efficient solution. The ADCVDD and
the 2.2 μF capacitor is best placed between Pin 30 and Pin 31, DVDD inputs have been designed to be driven externally and
while for ADCVDD, place the 2.2 μF capacitor between Pin 55 the internal regulators can be disabled by tying VREG_EN pin
and Pin 56. Similarly, for the LFCSP package, the DVDD 2.2 μF directly to ground.
capacitor is ideal between Pin 43 and Pin 44, and between Pin 22
and Pin 23 for ADCVDD. A 0.1 μF capacitor is recommended UNUSED PINS/PATHS
for high frequency decoupling at each pin. The 0.1 μF capacitors In applications where not all ECG paths or functions might be
must have low effective series resistance (ESR) and effective series used, the preferred method of biasing the different functions is
inductance (ESL), such as the common ceramic capacitors that as follows:
provide a low impedance path to ground at high frequencies to
• Unused ECG paths power up disabled. For low power
handle transient currents due to internal logic switching.
operation, keep them disabled throughout operation.
Avoid digital lines running under the device because these Ideally, connect these pins to RLD_OUT if not being used.
couple noise onto the device. Allow the analog ground plane to • Unused external respiration inputs can be tied to ground if
run under the device to avoid noise coupling. The power supply not in use.
lines must use as large a trace as possible to provide low impedance • If unused, the shield driver can be disabled and output left
paths and reduce the effects of glitches on the power supply line. to float.
Shield fast switching digital signals with digital ground to avoid • CM_OUT, CAL_DAC_IO, DRDY, GPIOx, CLK_IO,
radiating noise to other parts of the board and never run them SYNC_GANG can be left open.
near the reference inputs. It is essential to minimize noise on
VREF lines. Avoid crossover of digital and analog signals. LAYOUT RECOMMENDATIONS
Traces on opposite sides of the board must run at right angles to To maximize CMRR performance, pay careful attention to
each other. This reduces the effects of feedthrough throughout the ECG path layout for each channel. All channels must be
the board. As is the case for all thin packages, take care to avoid identical to minimize difference in capacitance across the paths.
flexing the package and to avoid a point load on the surface of
Place all decoupling as close to the ADAS1000/ADAS1000-1/
this package during the assembly process.
ADAS1000-2 devices as possible, with an emphasis on ensuring
During layout of board, ensure that bypass capacitors are placed that the VREF decoupling be prioritized, with VREF decoupling
as close to the relevant pin as possible, with short, wide traces on the same side as the ADAS1000/ADAS1000-1/ADAS1000-2
ideally on the topside. devices, where possible.
AVDD
While the ADAS1000/ADAS1000-1/ADAS1000-2 are
designed to operate from a wide supply rail, 3.15 V to 5.5 V,
the performance is similar over the full range, but overall
power increases with increasing voltage.

Rev. C | Page 83 of 85
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet

OUTLINE DIMENSIONS
9.10 0.60
9.00 SQ 0.275
0.60 0.42
8.90 0.24
0.42
0.24
0.150
43 56
42 1
PIN 1
INDICATOR
8.75
BSC SQ 0.50
BSC
*EXPOSED PAD 6.05
5.95 SQ
5.85

0.75
29 14
0.65
28 15
0.55
TOP VIEW BOTTOM VIEW

6.50 REF
0.70 MAX
0.90 12° MAX 0.65 NOM
0.85
0.80 0.05 MAX
0.01 NOM
SEATING 0.30
PLANE 0.20 REF
0.23
0.18

06-20-2012-A
*FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.

Figure 85. 56-Lead, Lead Frame Chip Scale Package [LFCSP_VQ]

9 mm × 9 mm Body, Very Thin Quad
(CP-56-7)
Dimensions shown in millimeters

12.20
0.75 12.00 SQ
0.60 1.60 11.80
0.45 MAX
64 49
1 48

PIN 1

10.20
TOP VIEW 10.00 SQ
(PINS DOWN)
9.80
1.45
0.20
1.40
0.09
1.35
7°
3.5°
0.15 16 33
0°
0.05 SEATING 17 32
PLANE 0.08
COPLANARITY VIEW A 0.27
0.50
BSC 0.22
VIEW A LEAD PITCH 0.17
ROTATED 90° CCW
051706-A

COMPLIANT TO JEDEC STANDARDS MS-026-BCD

Figure 86. 64-Lead Low Profile Quad Flat Package [LQFP]

(ST-64-2)
Dimensions shown in millimeters

Rev. C | Page 84 of 85
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2
ORDERING GUIDE
Temperature Package
Model 1 Description Range Package Description Option
ADAS1000BSTZ 5 ECG Channels, Pace Algorithm, Respiration Circuit −40°C to +85°C 64-Lead LQFP ST-64-2
ADAS1000BSTZ-RL 5 ECG Channels, Pace Algorithm, Respiration Circuit −40°C to +85°C 64-Lead LQFP ST-64-2
ADAS1000BCPZ 5 ECG Channels, Pace Algorithm, Respiration Circuit −40°C to +85°C 56-Lead LFCSP_VQ CP-56-7
ADAS1000BCPZ-RL 5 ECG Channels, Pace Algorithm, Respiration Circuit −40°C to +85°C 56-Lead LFCSP_VQ CP-56-7
ADAS1000-1BCPZ 5 ECG Channels −40°C to +85°C 56-Lead LFCSP_VQ CP-56-7
ADAS1000-1BCPZ-RL 5 ECG Channels −40°C to +85°C 56-Lead LFCSP_VQ CP-56-7
ADAS1000-2BSTZ Companion for Gang Mode −40°C to +85°C 64-Lead LQFP ST-64-2
ADAS1000-2BSTZ-RL Companion for Gang Mode −40°C to +85°C 64-Lead LQFP ST-64-2
ADAS1000-2BCPZ Companion for Gang Mode −40°C to +85°C 56-Lead LFCSP_VQ CP-56-7
ADAS1000-2BCPZ-RL Companion for Gang Mode −40°C to +85°C 56-Lead LFCSP_VQ CP-56-7
EVAL-ADAS1000SDZ ADAS1000 Evaluation Board Evaluation Kit 2
EVAL-SDP-CB1Z System Demonstration Board (SDP), used as a controller Controller Board 3
board for data transfer via USB interface to PC
1
Z = RoHS Compliant Part.
2
This evaluation kit consists of ADAS1000BSTZ × 2 for up to 12-lead configuration. Because the ADAS1000 contains all features, it is the evaluation vehicle for all
ADAS1000 variants.
3
This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the SD designator.

©2012–2018 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D09660-0-11/18(C)

Rev. C | Page 85 of 85