CC317 Digital System Design

Spring 2022
Lecture 9

http://www.free-powerpoint-templates-design.com
Agenda 01 Introduction

02 Entity

03 Library

04 Architecture
Introduction
 Overview
Designing with Boolean Equations

Boolean equations are impractical for large design containing hundreds of flip flops because it could
result in a huge number of logical equations.
B
D Q A 0 0 1 0
x
A 0 1 1 0
Q x
y DA (A, B, x) = A x + B x

DB (A, B, x) = A x + B’ x
D Q B
y (A, B, x) = A B
CLK Q
 Overview
Schematic based design

-Schematic based design expanded the capabilities of

Boolean equations.

-The major drawback of traditional design methods is the

manual translation of design description into a set of
logical equations.

-This step can be entirely eliminated with hardware

description languages (HDLs).
 Overview
Hardware Description Language [HDL]
Question:
How do we know that we have not made a mistake when
we manually draw a schematic and connect components
to implement a function?
Answer:
By describing the design in a high-level [such as (c, basic…)]
language, we can simulate our design before we manufacture it.
This allows us to catch design errors, i.e., that the design does not
work as we thought it would.
• Simulation guarantees that the design behaves as it should.
HDL is short for Hardware Description Language
 Overview
• HDL – Hardware Description Language
• A language that allows description of hardware for documentation, simulation, synthesis, verification, …

• Why an HDL program, why not schematics ?

• Real life circuits are too complex to be designed (described) by schematics

• Why hardware language , why not software language?

• In software everything is sequential
• Sequence of statements is significant, since they are executed in that order
• In hardware events are concurrent, so a software language cannot be used for describing and simulating
hardware.
 Overview
VHDL Language Scope
There is two types of tools that deal with VHDL

-Simulation
to test the logic design using simulation models

-Synthesis
to convert codes to hardware
VHDL Modules
 VHDL Statement Terminator
• Each VHDL Statements is terminated using a semicolon ;

• To include a comment in VHDL, use the comment operator

➢ -- This is a comment

• To assign a value to a signal data object in VHDL, we use the

➢ signal assignment operator <=
➢ To assign a value in std_logic or bit type
➢ X <= `0`;

➢ To assign a value in std_logic_vector or bit_vector type

➢ X <=``0011``;
 VHDL design units
• Configuration
• Package
• Entity
• Describes Interface
• Describes how the circuit appears form the outside.
• Similar to a schematic symbol.
• Architecture
• Specifies function
• Describes how the circuit does what it does.
• RTL
• Behavioral
• Structural
• Initially we will focus on the Entity and Architecture.
• Both are always necessary the others are optional.
Entity
 VHDL Details : Entity Syntax
• A “BLACK BOX”
• The ENTITY describes the periphery of the black box (i.e., the design I/O)
• Syntax :
entity entity-name is
BLACK_BOX
port (signal-names : mode signal-type ;
signal-names : mode signal-type ; rst
q[7:0]
…. d[7:0]
signal-names : mode signal-type); co
clk
end entity-name ;
Last port has no semicolon ;
-Comma , can separate ports with the same type and mode
 VHDL entity
 entity my_ckt is
▪ Name of the circuit
port ( ▪ User-defined
A: in bit; ▪ Filename same as circuit
B: in bit; name recommended
▪ Example.
Example:
S: in bit; ▪ Circuit name: my_ckt
X: out bit; ▪ Filename: my_ckt.vhd
Y: out bit
);
A
end my_ckt; X
B my_ckt
Port names or Y
Signal names S
 Name
Any legal VHDL identifier

• Only letters, digits, and underscores can be used

• The first character must be a letter
• The last character cannot be an underscore
• Two underscore in succession are not allowed
• case insensitive: COUNT, count, Count, counT are all the same
• Keywords can not be used as basic identifiers

Legal names Illegal names

rs_clk _rs_clk
ab08B signal#1
A_1023 A__1023
rs_clk_
 Port Declaration
* PORT declaration establishes the interface of the object to the outside world

* Three parts of the PORT declaration

o Name
o Mode
o Data type
ENTITY test IS
PORT (<name> : <mode> <data_type>);
END test;
 VHDL entity
 entity my_ckt is
port ( A
A: in bit; X
B: in bit; B my_ckt
Y
S: in bit; S
X: out bit;
Y: out bit
); Direction of port
end my_ckt; 3 main types:
▪ in: Input
▪ out: Output
▪ inout: Bidirectional
 PORT modes
A port’s MODE is the direction data is transferred:
• IN Data goes into the entity but not out
• OUT Data goes out of the entity but not in (and is not used internally)
• INOUT Data is bi-directional (goes into and out of the entity)
• BUFFER Data that goes out of the entity and is also fed-back internally
within the entity
• Linkage Data flow direction is unknown
 VHDL entity
 entity my_ckt is Datatypes:
port ( ▪ In-built
▪ User-defined
A: in bit;
B: in bit;
S: in bit;
X: out bit; A
Y: out bit X
B my_ckt
);
Y
end my_ckt; S
 VHDL Details : Types
• Types are required for every
• Signal
• Variable
• Function parameter
• Function result
• Type specifies a set/range of values for an object and a set of operators associated
with it
➢ For example data object of type bit can assume a value of either ‘0’ or ‘1’, and can support operators such as “and”, “or”, “xor”,
“nand”, etc.
• Predefined types
• User defined types
• Types must match in
• Assignment statements
• Comparisons
• Function calls
 VHDL Details : Types
Basic data types

BIT STD_LOGIC

0 1 0 1 H L U

Default X W Z - Default
value value

BIT_VECTOR : STD_LOGIC_VECTOR :
1D-array each element of the BIT type 1D-array each element of the STD_LOGIC type

Example: Example:
a : in BIT; a : in STD_LOGIC;
b : in BIT_VECTOR (3 downto 0); b : in STD_LOGIC_VECTOR(3 downto 0);
c : in BIT_VECTOR (0 to 3); c : in STD_LOGIC_VECTOR(0 to 3);
 VHDL Details : Types
Basic data types

X Z 0 1 U

Unknown Strong Unitialized

High Strong
Zero Default value
Impedance One

W - H L

Weak Don‘t Weak Weak

Unknown care One Zero

To define std_logic data type

LIBRARY ieee;
USE ieee.std_logic_1164 .all;
 VHDL entity
Datatypes:
▪ In-built
▪ User-defined
 entity my_ckt is
▪ Name of the circuit
port ( ▪ User-defined
A: in bit; ▪ Filename same as circuit
A B: in bit; name recommended
X ▪ Example:
Example.
S: in bit; ▪ Circuit name: my_ckt
B my_ckt
Y X: out bit; ▪ Filename: my_ckt.vhd
S Y: out bit
Direction of port
); 3 main types:
end my_ckt; ▪ in: Input
▪ out: Output
Port names or ▪ inout: Bidirectional
Signal names
Note the absence of semicolon
“;” at the end of the last signal
and the presence at the end of
the closing bracket
 VHDL entity
 entity my_ckt is
port (
A , B, S: in bit;
X: out bit;
Y: out bit
);
end my_ckt;

Note that:
Last port has no semicolon ;
Comma , can separate ports with the same type and mode
 Example
Write the entity that describes the shown circuit
Library
 Libraries

❖There are two pre-defined libraries in VHDL:

• STD The standard IEEE library that holds many predefined types such as BIT.
Many of these types are used almost like a reserved word because they are already
predefined in the STD library.

•WORK This is the working library, where we store our currently analysed design
entities
 Standard Libraries
• Include library ieee; before entity declaration.

• ieee.std_logic_1164 defines a standard for designers to use in describing

interconnection data types used in VHDL modeling.

• ieee.std_logic_arith provides a set of arithmetic, conversion, comparison

functions for signed, unsigned, std_ulogic, std_logic, std_logic_vector.

• ieee.std_logic_unsigned provides a set of unsigned arithmetic, conversion, and

comparison functions for std_logic_vector.

• See all available packages at http://www.cs.umbc.edu/portal/help/VHDL/stdpkg.html

Architecture
 Data Flow Syntax
Architecture description
entity latch is describes the architecture is of the
port (s,r: in bit; method data flow description and
q, nq: out bit); belongs to the entity latch
end latch;
architecture dataflow of latch is Logical Data Assignment
begin
q<= r nor nq; } Shows that the value of the
output pins are derived from a
nq<= s nor q; logical function of the input
end dataflow; pins
r

q
“<=” is used for a signal assignment
which describes how the data on the right
nq hand side of the operator to the left hand
s
side.
 VHDL Details : Types
•VHDL has concurrent statements and sequential statements
•Concurrent statements are executed in parallel w.r.t each other.
With – select
When – else
Process statement
Assign statement
•Sequential statements are executed in sequence w.r.t each other.
If statement
loop statement
Case statement
Wait and Null statement
 Concurrent Statements

Three types of concurrent statements

used in dataflow descriptions

Boolean Equations with-select-when when-else

For concurrent For selective For conditional

signal assignments signal assignments signal assignments
 Built-In Operators

Miscellanies operators ** abs not

Multiplying operators * / Mod rem
unary operator + -
Adding operator + - & (concatenation)
Shift operator sll srl sla sra
rol ror
Relational operation = /= < <=
> >=
Logical operator and or nand
nor xor xnor

33
VHDL Modules
 my EXOR gate
Library : Collection of design
library IEEE; elements, type declarations,sub
use IEEE.std_logic_1164.all; programs, etc.

entity my_exor is entity - defines the

port (ip1 : in std_logic; interface.
ip2 : in std_logic;
op1 : out std_logic std_logic is the type of the port
); It is defined in the IEEE library.
end my_exor; Mode of the port :
Any node of type std_logic can take
It can be
9 different values.
in, out or inout
‘0’ , ’1’ , ’H’ , ’L’ , ’Z’ , ’U’ , ’X’ , ’W’ , ’-’
architecture my_exor_beh of my_exor is
begin
op1 <= (ip1 and (not ip2)) or
The architecture describes the
(ip2 and (not ip1));
end my_exor_beh; behaviour (function),
interconnections and the
relationship between different
inputs and outputs of the entity.
 Example
Write VHDL code that describes the shown circuit
 Concurrent Statements

Three types of concurrent statements

used in dataflow descriptions

Boolean Equations with-select-when when-else

For concurrent For selective For conditional

signal assignments signal assignments signal assignments
 Conditional Signal Assignment:
when-else
• Signal is assigned a value based on conditions
• Any simple expression can be a condition
• Only one reference to the signal, only one assignment operator (<=)
• Use a final ELSE to avoid latches

signal_name <= value_1 WHEN condition1 ELSE

value_2 WHEN condition2 ELSE
...
value_n WHEN conditionn ELSE
value_x ;
 Concurrent Statements
when-else
architecture mux_arch of mux is
begin
x <= a when (s = "00") else
b when (s = "01") else
c when (s = "10") else
d;
end mux_arch;
 Selective Signal Assignment:
with-select-when
• Assignment based on a selection signal
• WHEN clauses must be mutually exclusive
• Use a WHEN OTHERS to avoid latches
• Only one reference to the signal, only one assignment operator (<=)

WITH selection_signal SELECT

signal_name <= value_1 WHEN value_1 of selection_signal,
value_2 WHEN value_2 of selection_signal,
...
value_n WHEN value_n of selection_signal,
value_x WHEN OTHERS;
Selective Signal Assignment:
with-select-when

architecture my_mux_A of my_mux is

begin
with sel select
x <= a when “00” ,
b when “01” ,
c when “10” ,
d when others;
end my_mux_A;
THANK YOU