Scribd
Upload
59 views19 pages

CALab - Jalish Buktawar

The document contains the index page of a student's lab report for their Computer Architecture lab course. The index lists 16 experiments completed by the student involving designing basic digital logic gates and circuits using VHDL code. For each experiment, it provides the problem statement, date of experiment, date of submission, and space for marks and signature. The document provides an overview of the various digital logic experiments completed by a student for their Computer Architecture lab course, as evidenced by the index listing 16 experiments involving designing gates and basic circuits in VHDL.

Uploaded by

Souvik Pal
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
59 views19 pages

CALab - Jalish Buktawar

The document contains the index page of a student's lab report for their Computer Architecture lab course. The index lists 16 experiments completed by the student involving designing basic digital logic gates and circuits using VHDL code. For each experiment, it provides the problem statement, date of experiment, date of submission, and space for marks and signature. The document provides an overview of the various digital logic experiments completed by a student for their Computer Architecture lab course, as evidenced by the index listing 16 experiments involving designing gates and basic circuits in VHDL.

Uploaded by

Souvik Pal
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 19

Netaji Subhash Engineering College

Computer Architecture Lab


PCC-CS492

Name : Jalish Buktawar


Class Roll Number : 59
Department : CSE-2A
University Roll : 10900121063
Netaji Subhash Engineering College
Department of Computer Science & Engineering

INDEX
Course Name: Computer Architecture Lab Student Name: Jalish Buktawar

Course Code: PCC-CS492 University Roll No. : 10900121063


Marks Signature
Sl. Exp. of the Remarks
Problem Statement D.O.E D.O.S
No. No. 5 15 20 Faculty ( if any)
with Date
Design an AND Gate Using
1 1 VHDL Code in ISE Design
Suite.
Design an OR Gate Using
2 2 VHDL Code in ISE Design
Suite.
Design an XOR Gate Using
3 3 VHDL Code in ISE Design
Suite.
Design a Half Adder Gate Using
4 4 VHDL Code in ISE Design
Suite.
Design a Full Adder Gate Using
5 5 VHDL Code in ISE Design
Suite.
Design a Full Adder using Half
6 6 Adder Using VHDL Code in ISE
Design Suite.
Design a 4-bit Ripple Carry
7 7 Adder Using VHDL Code in ISE
Design Suite.
Design a 4-bit Adder Subtractor
8 8 Using VHDL Code in ISE
Design Suite.
Design a 4-bit Decrementer
9 9 Using VHDL Code in ISE
Design Suite.
Design a 4-bit Incrementer
10 10 Using VHDL Code in ISE
Design Suite.
Design a Multiplexer Using
11 11 VHDL Code in ISE Design
Suite.
Design a Demultiplexer Using
12 12 VHDL Code in ISE Design
Suite.
Design a Decoder Using VHDL
13 13
Code in ISE Design Suite.

Design a Full Adder(Behavioral


14 14 Design) Using VHDL Code in
ISE Design Suite.
Design a 4 bit Binary Multiplier
15 15 Using VHDL Code in ISE
Design Suite.
Design a 4 bit Restoring
16 16 Division Using VHDL Code in
ISE Design Suite.
1. Design an AND Gate Using VHDL Code in ISE Desi gn Suite.

Code :
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
entity AndGate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end AndGate;

architecture Behavioral of AndGate is


begin
c <= a AND b;
end Behavioral;

Output :
2. Design an OR Gate Using VHDL Code in ISE Desig n Suite.

Code :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity OrGate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end OrGate;

architecture Behavioral of OrGate is


begin
c <= a OR b;
end Behavioral;

Output :
3. Design an XOR Gate Using VHDL Code in ISE Design Suite.

Code:
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
entity XorGate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end XorGate;

architecture Behavioral of XorGate is


begin
c <= a XOR b;
end Behavioral;

Output :
4. Design a Half Adder Gate Using VHDL Code in ISE Design Suite.

Code:
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
entity HA is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : out STD_LOGIC;
cout : out STD_LOGIC);
end HA;

architecture Behavioral of HA is
begin
s <= a XOR b;
cout <= a AND b;
end Behavioral;

Output :
5. Design a Full Adder Gate Using VHDL Code in ISE Design Suite.

Code :
library IEEE;

use IEEE.STD_LOGIC_1164.ALL; entity FA is


Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
s : out STD_LOGIC;
cout : out STD_LOGIC);
end FA;

architecture Behavioral of FA is
begin
s <= a XOR b XOR cin;
cout <= (a AND b) OR ((a XOR b) AND cin);
end Behavioral;

Output :
6. Design a Full Adder using Half Adder Using VHD L Code in ISE Desig n Suite.

Code :
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
entity FAusingHA is
Port( af : in STD_LOGIC;
bf : in STD_LOGIC;
cin : in STD_LOGIC;
sf : out STD_LOGIC;
cfout : out STD_LOGIC);
end FAusingHA;
architecture Behavioral of FAusingHA is component HA is
Port( a : in STD_LOGIC;
b : in STD_LOGIC;
s : out STD_LOGIC;
cout : outSTD_LOGIC);
end component;
signal sig0, sig1, sig2 : STD_LOGIC;
begin
HA1 : HA port map(af, bf, sig0, sig1);
HA2 : HA port map(sig0, cin, sf, sig2);
cfout <= sig1 OR sig2;
end Behavioral;

Output :
7. Design a 4-bit Ripple Carry Adder Using VHDL Code in ISE Design S uite.
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity RippleCarry is
Port(a : in STD_LOGIC_VECTOR(3 downto 0);
b : in STD_LOGIC_VECTOR(3 downto 0);
cin : in STD_LOGIC;
s : out STD_LOGIC_VECTOR(3 downto 0);
cout: out STD_LOGIC);
end RippleCarry;
architecture Behavioral of RippleCarry is component FA is
Port(a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
s : out STD_LOGIC;
cout : out STD_LOGIC);
end component;
signal sig0, sig1, sig2 : STD_LOGIC;
begin
FA1 : FA port map(a(0), b(0), cin, s(0), sig0);
FA2 : FA port map(a(1), b(1), sig0, s(1), sig1);
FA3 : FA port map(a(2), b(2), sig1, s(2), sig2);
FA4 : FA port map(a(3), b(3), sig2, s(3), cout);
end Behavioral

Output :
8. Design a 4-bit Adder Subtractor Using VHDL Code in ISE Design Suite.
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity AddSub is
Port(a : in STD_LOGIC_VECTOR(3 downto 0);
b : in STD_LOGIC_VECTOR(3 downto 0);
sw : in STD_LOGIC;
s : out STD_LOGIC_VECTOR(3 downto 0);
cout : out STD_LOGIC);
end AddSub;
architecture Behavioral of AddSub is component FA is
Port(a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
s : out STD_LOGIC;
cout : out STD_LOGIC);
end component;
signal sig : STD_LOGIC_VECTOR(2 downto 0);
signal temp : STD_LOGIC_VECTOR(3 downto 0);
begin
temp(0) <= sw XOR b(0);
temp(1) <= sw XOR b(1);
temp(2) <= sw XOR b(2);
temp(3) <= sw XOR b(3);
FA1 : FA port map(a(0), temp(0), sw, s(0), sig(0));
FA2 : FA port map(a(1), temp(1), sig(0), s(1), sig(1));
FA3 : FA port map(a(2), temp(2), sig(1), s(2), sig(2));
FA4 : FA port map(a(3), temp(3), sig(2), s(3), cout);
end Behavioral;

Output :
9. Design a 4-bit Decre menter Using VHDL Code in ISE Desig n Suite.
Code:
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
entity Decrementer is
Port(a: in STD_LOGIC_VECTOR(3 downto 0);
cin: in STD_LOGIC;
s: out STD_LOGIC_VECTOR(3 downto 0);
cout: out STD_LOGIC);
end Decrementer;
architecture Behavioral of Decrementer is component FA is
Port(a: in STD_LOGIC;
b: in STD_LOGIC;
cin: in STD_LOGIC;
s: out STD_LOGIC;
cout: out STD_LOGIC);
end component;
signal sig : STD_LOGIC_VECTOR(2 downto 0);
begin
FA1 : FA port map(a(0), '1', cin, s(0), sig(0));
FA2 : FA port map(a(1), '1', sig(0), s(1), sig(1));
FA3 : FA port map(a(2), '1', sig(1), s(2), sig(2));
FA4 : FA port map(a(3), '1', sig(2), s(3), cout);
end Behavioral

Output :
10. Design a 4-bit Incrementer Using VHDL Code in ISE Desig n Suite.
Code :
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
entity Incrementer is
Port(a: in STD_LOGIC_VECTOR(3 downto 0);
s: out STD_LOGIC_VECTOR(3 downto 0);
cout: out STD_LOGIC);
end Incrementer;
architecture Behavioral of Incrementer is component HA is
Port(a: in STD_LOGIC;
b: in STD_LOGIC;
s: out STD_LOGIC;
c: out STD_LOGIC);
end component;
signal sig : STD_LOGIC_VECTOR(2 downto 0);
begin
HA1 : HA port map(a(0), '1', s(0), sig(0));
HA2 : HA port map(a(1), sig(0), s(1), sig(1));
HA3 : HA port map(a(2), sig(1), s(2), sig(2));
HA4 : HA port map(a(3), sig(2), s(3), cout);
end Behavioral

Output :
11. Design a Multiplexer Using VHDL Code in ISE Design Suite.
Code :
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
entity Multiplexer is
Port(I: in STD_LOGIC_VECTOR(3 downto 0);
S: in STD_LOGIC_VECTOR(1 downto 0);
O: out STD_LOGIC);
end Multiplexer;
architecture Behavioral of Multiplexer is
begin
Process(I, S)
begin case S is
when "00" = > O <= I(0);
when "01" = > O <= I(1);
when "10" = > O <= I(2);
when "11" = > O <= I(3);
when Others = > O <= 'U';
end case;
end Process;
end Behavioral;

Output :
12. Design a Demultiplexer Using VHDL Code in ISE Design Suite.

Code:
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
entity demux is
Port(I: in STD_LOGIC;
S: in STD_LOGIC_VECTOR(1 downto 0);
O: out STD_LOGIC_VECTOR(3 downto 0));
end demux;
architecture Behavioral of demux is begin

process(I, S)
begin
O <= "UUUU";
case S is
when "00" = > O(0) <= I;
when "01" = > O(1) <= I;
when "10" = > O(2) <= I;
when others = > O(3) <= I;
end case;
end process;
end Behavioral

Output :
13. Design a Decoder Using VHDL Code in ISE Desig n Suite.

Code:
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
entity decoder is
Port(a: in STD_LOGIC;
b: in STD_LOGIC;
enable: in STD_LOGIC;
z: out STD_LOGIC_VECTOR(3 downto 0));
end decoder;
architecture Behavioral of decoder is begin
process(a, b, enable)
variable abar, bbar : STD_LOGIC;
begin
abar : = NOT a;
bbar : = NOT b;
if enable = '1' then
z(0) <= abar AND bbar;
z(1) <= abar AND b;
z(2) <= a AND bbar;
z(3) <= a AND b;
else z <= "UUUU";
end if;
end process;
end Behavioral;

Output :
14. D esign a Full Adder(Behavioral Design) Using VHDL Code in ISE D esign
Suite.
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fulbehaviour is
Port(a: in STD_LOGIC;
b: in STD_LOGIC;
cin: in STD_LOGIC;
s: out STD_LOGIC;
cout: out STD_LOGIC);
end fulbehaviour;
architecture Behavioral of fulbehaviour is
begin
process(a, b, cin)
variable sw : std_logic_vector(2 downto 0);
begin
sw(0) : = cin;
sw(1) : = b;
sw(2) : = a;
case sw is
when "000" = > s <= '0';
cout <= '0';
when "001" = > s <= '1'; cout <= '0';
when "010" = > s <= '1'; cout <= '0';
when "011" = > s <= '0'; cout <= '1';
when "100" = > s <= '1'; cout <= '0';
when "101" = > s <= '0'; cout <= '1';
when "110" = > s <= '0'; cout <= '1';
when others = > s <= '1'; cout <= '1';
end case;
end process;
end Behavioral;
Output :
15. Design a 4 bit Binary Multiplier Using VHDL Code in ISE Design Suite.

Code:
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity binary_multiplier is
Port(m: in STD_LOGIC_VECTOR(3 downto 0);
q: in STD_LOGIC_VECTOR(3 downto 0);
r: out STD_LOGIC_VECTOR(7 downto 0));
end entity;
architecture multiplier of binary_multiplier is begin
process(m, q)
variable acc : std_logic_vector(8 downto 0);
variable multiplicand : std_logic_vector(4 downto 0);
begin
acc(8 downto 4) : = "00000";
acc(3 downto 0) : = q;
multiplicand : = '0' & m; for
i in 1 to 4 loop if acc (0) = '1' then
acc(8 downto 4) : = acc(8 downto 4) + multiplicand;
end if;
acc : = '0' & acc(8 downto 1);
end loop;
r <= acc(7 downto 0);
end process;
end multiplier;

Output :
16. Design a 4 bit R estoring Division Using VHD L Code in ISE Design Suite.
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity division is
Port(d: in STD_LOGIC_VECTOR(3 downto 0);
m: in STD_LOGIC_VECTOR(3 downto 0);
q: out STD_LOGIC_VECTOR(3 downto 0);
r: out STD_LOGIC_VECTOR(3 downto 0));
end division;
architecture Behavioral of division is begin
process(d, m)
variable ac : std_logic_vector(7 downto 0);
variable Mbar : std_logic_vector(3 downto 0);
begin
Mbar : = not m;
ac : = "0000" & d; for
i in 1 to 4 loop
ac(7 downto 0) : = ac(6 downto 0) & 'U';
ac(7 downto 4) : = ac(7 downto 4) + Mbar + "0001";
if ac (7) = '1' then
ac(0) : = '0';
ac(7 downto 4) : = ac(7 downto 4) + m;
else ac(0) : = '1';
end if;
end loop;
q <= ac(3 downto 0);
r <= ac(7 downto 4);
end process;
end Behavioral;
Output:

You might also like