Introduction

Hello to who so ever is reading this, Myself Pradhi Kumar, I got

a rank of 292 in GATE-2020 and took admission as a M.Tech.
Student in the specialization Solid State Devices at IIT Bombay. I
have a current CPI of 8.62 ( It was 9.07 in my resume as it was
not updated during the placement season), I have got placed in
TSMC(Taiwan Semiconductor Manufacturing Company) as Chip
Design Engineer and here I will try to put across my whole
placement journey.

Profiles I prepared for: Digital VLSI only

Reason: I am not very good with analog hence didn’t prepare
for it, and there aren’t a lot of companies recruiting for device
profile hence didn’t go for that also (also I didn’t had much
interest in Devices)

Preparation:There is no bad time to start preparing, but the

sooner the better.
I Started my preparation from May 2021 with verilog and
Digital IC design by J. Rabaey. Following are the topics I studied
and corresponding sources:
Verilog Programming- Indranil Sengupta IIT KGP lectures and
practiced on HDL Bits (Highly
recommended)
Digital design: Digital IC design Book by J.Rabaey (Ch-5,6,10 are
very very important)
Physical Design Flow- took a course on Udemy by Kunal Ghosh
(around 400rs), not necessary, you can get the info on google
as well but if you have the money, it is not a bad place to spend
it.
ASIC Design Flow: https://www.einfochips.com/blog/asic-
design-flow-in-vlsi-engineering-services-a-quick-guide/ (Good
enough if you want just the idea of every step. As I had already
done the physical design course and known about verification
and rtl design it felt easy to understand)
Static timing analysis- http://www.vlsi-
expert.com/2011/03/static-timing-analysis-sta-basic-
timing.html (Highly Recommended)

Metastablity- there is a pdf on Clock domain crossing from

sunburst, that explains this very well.

Synchronizers-
https://www.youtube.com/playlist?list=PLdcY8Cf-O1Zon-
8c9NDhgY2F8r_O7oeC4 (the explaination is not perfect but it is
the easiest and enough to get an idea, which is needed)

Concepts related to testing and verification-

https://www.youtube.com/playlist?list=PLyWAP9QBe16qiSMk
BcAnUMxFagLIJzmv1 (quite a hidden playlist, but highly
recommended, this channel has playlist on most of the topics
and they are good)

Processor Design/Computer Architecture- Modern processor

design fundamentals of superscalar processors (ch 2-5) by M.
Lipasti (probably the best book I have read, there will be topics
that you will find difficult to understand but you don’t have to
go very deep into everything for placements )

Verilog (other concepts) - Concepts like delay modeling in

verilog and Event queue model (VERY IMPORTANT), I did these
from sunburst pdfs, you can search for them online.

Digital circuits like clock divider -

https://www.youtube.com/playlist?list=PLPmSCnkkX4qtFcm8F
ZpwHEawvq5eULxwf
There were topics like Reset synchronizer, Recovery and
Removal time, Edge detector circuit (positive, negative, dual)
etc which can be easily found on the internet.

FSM- one of the key concepts in the interviews, practice hard

for these (DigiQS will be the perfect material to practice these
from)

DigiQS- Question bank for all the topics you will need for
placements, if you are not doing this, then it is a mistake
(Cannot recommend it more)

C programming - You just need to practice the MCQs from

geeksforgeeks (set 71-89), but obviously it is better if know
how to code also.

FIFO Depth-
https://hardwaregeeksblog.files.wordpress.com/2016/12/fifo
depthcalculationmadeeasy2.pdf

FIFO Synchronizer- http://www.sunburst-

design.com/papers/CummingsSNUG2002SJ_FIFO1.pdf

Ground bounce and voltage droop- you can easily find this on
google

Low power VLSI (Clock gating, power gating etc)- Very

Important if you are going for Google Hardware
https://www.youtube.com/playlist?list=PLTEh-62_zAfHmJE-
pcjgREKiKyPSgjkxj (lecture-17 to lecture-36)
Highly Recommended

Puzzles- geeksforgeeks

Clock domain crossing- sunburst PDF (its better to watch the

syncronizers playlist I have attached above before reading this).
http://www.sunburst-
design.com/papers/CummingsSNUG2008Boston_CDC.pdf

Aptitude- I practiced it from the previous year questions, or the

department and institute placement tests.

Resume
My resume was of 2 pages, I had put my mtech seminar and
project, area of interest, important courses, skills, 3
certifications(Matlab, physical design, layout) the layout one
was kind of gap filling as there shouldn’t be blank spaces on
your resume. I had 8 course/self project 6 related to digital and
2 to devices, 2 PoR(Position of responsibility), 4 extracurricular
activities, and 2 hobbies on my resume.
Projects that I had on my resume are as follows:
1-LUT optimization for memory based computation
2-RISC-V processor
3-brent Kung adder
4-booth multiplier
5-zipper logic and domino logic
6-parasitic delay and transistor width ratio
7-pao sah and brews implementation on MATLAB
8-Characteriszation of MOSCAP

How important is your resume:

Very important for the following companies: Qualcomm,Google
(silicon engineer), Mediatek, TSMC, and some startups
For the rest it is not that important
NOTE- KEEP IN MIND I AM SAYING THE ABOVE IN ACCORDANCE
WITH CAMPUS PLACEMENT, FOR OFF-CAMPUS RESUME IS
VERY IMPORTANT

If I had to give marks to my resume, it would be 6.5-7/10

Did the certificates helped me in my interviews: yes they did,
the first thing that the interviewer said was that you have done
this certification so tell me about that (it was related to the
profile), also I guess the MATLAB one helped in Mathwork’s
shortlisting.
But I must say that I got lucky with the certificates as the
interview I appeared for was of the same profile as my
certificate, in rest of the companies it didn’t really help (judging
from other’s experience)

Placement tests
I will try to describe the pattern of every test that I have given
in this placement season:
Companies I was shortlisted for: TSMC, Intel, Micron, Enphase
Energy, Rhambus, Mathworks, Samsung Semiconductor,
Mediatek
I was there in the first shortlist of these companies, I was not
involved in the placement process after 1st day so no point of
the 2nd , 3rd shortlist.

Cirel system (only for Analog Profile)- total 10 question, 1.5hr

test, theoretical test,
8 questions of analog, 2 of digital (related to STA)

Qualcomm-1.5hr, 3 sections, 20 question each(aptitude

(lookout for the arrangement question in logical reasoning, this
is where students mostly lose their time), programming mcq
(c,data structure, operating system), Hardware) [they tend to
look onto your resume also for first shortlist]

Enphase Energy-55 questions around 1hr, 35 ques of

aptitude+20 technical, expect some questions related to
communication also. (it has a criteria of throughout 80% in your
academic years)
Texas instruments- Aptitude compulsory, 20 ques in 30min,
depending on profile you can give analog,digital or both,20
questions, 45 minutes each [this time shortlisted more for
analog profile] (Analog questions are very conceptual)

Intel- 50 questions [20 question aptitude, 30 minutes, rest 30

hardware, 45 minutes] (Level was intermediate, again look out
for arrangement question in aptitude)

Micron- same pattern as qualcomm but programming section

consist of python as well (quite difficult programming section)

Mathworks- mostly will be related to a particular programming

language (mcq+2 coding question) with a bonus section for
matlab, only 15 out of 42 questions were related to hardware.
You have to chose between c, c++ and java only (Still don’t
know how I got shortlisted)

Rambus- Theoretical exam with moderate questions, had to

prioritize our profile first (20 questions 1.5hr, 9 of digital 11 of
analog approximately)

Cadence- Probably the most interesting exam, lengthy but

interesting (made a very silly mistake in a FSM question which
cost me at that time) 70 questions and 100 minutes as far as I
can remember (sections for digital, computer architecture and
aptitude)

Xilinx- the toughest exam of the season for me, practice

aptitude really hard before this exam, don’t remember the
exact pattern sorry ( I was too disappointed to remember
anything after the exam)

Ceremorphic- moderate exam not too difficult, not too easy

Samsung semiconductor- 48 questions, 69 minutes mostly
based on questions asked previously, has 2-3 sections in which
the marks per questions are different so look out for that.

I might have missed some tests, so sorry for those.

TSMC, Mediatek, Google(Silicon engineer), Quasistatic, Silabs
shortlisted directly on the basis of resume.

Interview experience: (ONLINE)

I was shortlisted for only one interview on day 1 of placement,
it was TSMC, following is the whole conversation

Company:TSMC
Profile: Chip Design Engineer/Physical design engineer
Job location: Hshinchu, Taiwan
CTC: cannot reveal, but highest for digital VLSI if we convert
NTD to INR
First question: what do you play?
I was as surprised as you are, but this question was asked due
to the fact that I had my jerseys hanging on my wall. Maybe this
is not very relevant, but they take notice of your surroundings

Introduce yourself with regards to what you have done in the

field of physical design
I started with my name and place I was born, told my degree
and specialization, and then told my area of interest as Physical
Design and RTL design, and then went onto say that I have
done a course in physical design flow from which I learnt about
the steps and what we do in each, obviously explaining a little
more, then ended my intro by introducing them to my PoRs I.e.
Department coordinator and department placement
coordinator
Okay so we see that you have written in your resume that you
have done a course in physical design flow, can you explain
the steps involved in it
I started with floorplanning and what we do in that step as I
went onto placement and Clock tree synthesis, they stopped
me in the middle and explained that they want to know what is
the thing that we want after each step as which thing is
optimized after each step
I again started with floorplanning and explained the aim of the
step, I continued and finished the whole design flow steps and
they were satisfied with the answer(actually they just wanted
to screen whether they can get into more depth with the
concepts or not)

They asked that I had used a word static timing analysis, what
is that
I explained the concept, and as the keywords came along they
kept asking for the keywords.(setup time, hold time,
metastability etc )

Then they asked that, assume a circuit with two flops and
suppose there is a setup violation, so what would you do:
I answered that we can decrease the delay in the combinational
path or put a series of buffer in the clock path so as to remove
the setup violation, then they asked a counter question saying
that you said that we do clock tree synthesis to not induce
skew but the clock buffer idea that you have given will induce
skew, I answer to that saying the whole purpose of not having
any skew and CTS was done just so that we don’t have any
violations but as there is violation beforehand we would need
to tweak something.
They asked lets us want to take the first option I.e. to reduce
the combinational path, how can you do that?
I answered this by giving two solution:
1) Using optimized combinational circuitry for example brent
kung adder in place of nomal adder, they said that suppose we
only have buffers, then what?
2) I said that we can use a faster design style, again they said
they wanted something else, I told them I was not able to think
anything else so if they could give me any hint |

They answered me saying that its okay, we know that this is not
in your curriculum so we just wanted to know the approach
(according to me the answer they were looking for was to use a
latch in between the flip flop and using the concept of time
borrowing)

Then the other panelist asked questions about power and

how we can know that we have a power violation just in the
floorplanning stage as that is where the power tree is formed,
I told him all about power tree and all I knew but was not
exactly to the point
(the answer I think was that, we go through cycles from
floorplanning to placement and route to cts and again back to
floorplanning if there is any violation), I was close but not exact
to the solution.

Then they asked me about IR drop and how is it significant

I answered it confidently, but then came the main question, if
there is IR drop then how do we solve this issue, I talked about
decoupling caps first, but after thinking a while I answered that
we can take the supply lines to be just above what we want it
to be and then he was satisfied and told me that we always
take a tolerance level to every thing.
I think this answer was very key to me getting selected

Time- around 45 minutes

Got the result the next morning