Lect 06 VHDL INTRO
Lect 06 VHDL INTRO
digitale
Luca Di Nunzio
[email protected]
0672597810
http://dspvlsi.uniroma2.it
VHDL
• Vhsic Hardware Description Language
• VHSIC Very High Speed Integrated Circuit
• Developed im 1980’s by DOD, Departement Of Defence
• Born as description language for documentation
• 1987 Viewlogic Systems release ViewLogic WorkView a logic synthesizer
that supported the VHDL
• VHDL is used to
– Implement digital circuits inside FPGA,
– Front-end phase of ASIC (Application Specific Integrated Circuit) design flow
VHDL
VHDL is NOT a programming language
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entity my_circuit is
port ( Libraries and packages used comment
In1:in std_logic; in the project
In2,In3:in std_logic;
out1:out std_logic
Entity declaration
);
end my_circuit;
The assignment
a<=b and c;
d<=e or f;
is equal to
d<=e or f;
a<=b and c;
VHDL DATAFLOW level
• Gate level description is the lowest level
of abstraction allowed by the VHDL.
• In the architecture body the entity is
described using boolean or math …
equation. f <= (v and b) and a;
• Complex systems cannot be easily Z <= not a;
…
described at gate level.
– Intel I7 processor is composed by 731.000.000
transistors
VHDL Behavioral VHDL
• The behavioral description describes the
behavior of an entity without considering
how the design is implemented in terms if sel = '1' then
of logic gates. f <= a;
• Behavioral descriptions are supported else f <= b;
with the process statement and use end if;
syntax statements similar to the ones
used in software (if, case,for…)
Process 1/2
The process statement is inside the
architecture body and consists of a my_process : process (sel, a, b)
number of parts: VARIABLE var_name: bit;
begin
• Process name (optional) if sel = '1' then
• Sensitivity list: This list enumerates f <= a;
exactly which signals cause the process.
else f <= b;
• Process declarative part (optional):
contains variables used in the process. end if;
• Process body: contains the operations end process;
performed once the process starts.
• A process starts when at least a signal in
the sensitivity list changes the value NOTE: SYSTEMS CAN BE DESCRIBED WITHOUT
USING VARIABLES. WE’LL NOT USE VARIABLES
IN THIS COURSE
Process 2/2
• Processes are concurrent each …
…
others.
Process_1:process (a, b)
– Different processes will be synthetized
in hardware blocks that usually will begin
work simultaneously. …
end process;
NOTE: IF THE Sensitivity is empty :
Process_2:process (c, d)
• The process starts with no initial conditions
begin
• Once finished the process restart
…
An empty Sensitivity list is useful only for
end process;
simulations
…
EXAMPLE
out1
in1 in3
0 0 out2
in2 in4
1 1
sel1
EXAMPLE
entity example_circuit is
port (
In1,in2,in3,in4:in std_logic;
sel:in std_logic;
Out1,out2:out std_logic
);
end example_circuit ;
EXAMPLE
PORTs
A port is the interface between the entity and the external environment
SIGNALs
In this example signals are used to connect entities together (wires or bus).
They can be also used to model registers in sequential systems
SIGNAL signal_name : signal_type [:= initial_value];
TYPE
Both Signal and ports can be scalar or vectors of different tipolosy
2 Input multiplexer design
GOAL ➔ VHDL DESCRIPTION OF A 2 INPUT MULTIPLEXER
– DATAFLOW/GATE LEVEL
– BEHAVIORAL LEVEL
IN_1
OUTPUT
IN_2
SEL
DATAFLOW solution
DATAFLOW LEVEL VHDL
library IEEE;
use IEEE.std_logic_1164.all;entity MUX is
port (
IN_1,IN_2,SEL: in std_logic;
OUTPUT: out std_logic
);
end MUX ;
A IN_1
OUTPUT
P IN_1 RES Z
MUX
COMB_LOGIC
B IN_2
SEL
C
VHDL quick start
Before the structural description the sub circuit (VHDL ENTITY 1 and VHDL ENTITY
2) must be described in VHDL and their VHDL files must be in the project
P IN_1 RES Z
COMB_LOGIC
B IN_2
SEL
C
VHDL quick start
-- Structural LEVEL VHDL
-- Top level
library IEEE;
use IEEE.std_logic_1164.all;
entity circuit is
port (
a,b,c: in std_logic;
z: out std_logic
);
end circuit ;
VHDL quick start
-- Structural LEVEL VHDL
Before the «begin» must be
architecture structural of circuit is defined:
signal p: std_logic; • signals (wires or bus) used
component MUX is
in the design to connect
port (
components
IN_1,IN_2,SEL: in std_logic;
OUTPUT: out std_logic);
• The components (VHDL
end component ;
entities) to be connect
component COMB_LOGIC is
port (
IN_1 : in std_logic;
RES: out std_logic);
end component ;
VHDL quick start
Structural LEVEL VHDL The entity are instanced
… and the ports are liked
end component ; to signals and to the
begin TOP LEVEL Entity
U1:MUX port map(
IN_1=>a, IN_2=>b, SEL=>c, OUTPUT=>p); GLOBAL PORT
U2:COMB_LOGIC
SIGNAL
port map (
LOCAL PORT
IN_1=>p,
RES=>z)
);
End structural
VHDL quick start
• Local ports of different entities cannot be connected
• Each local port can be connected to any signal and global port
• Each global port can be connected to any signal and local port
A IN_1
OUTPUT
IN_1 RES Z
MUX
P
COMB_LOGIC
B IN_2
SEL
C
VHDL quick start
• After the VHDL description and before the synthesis entities must be
simulated
• Test bench ➔ apply stimulus to the design and analyze results,
• A test bench is a VHDL structural entity
Test bench
1111
DUT 1001
STIMULUS
generator 1011 (Design Under Test)
VHDL quick start
• Stimulus can be generated in the test bench entity or , in case of complex
systems from files.
• They are defined in the architecture of the test bench entity
• There are two important VHDL statement for TB
– wait for (must be in a process)
– after
x<=‘0‘,’1’ after 10 ns,’0’after 30 ns;
…
process
begin
x<=‘0’;
wait for 10 ns;
x<=‘1’;
wait for 10 ns;
end process;
VHDL quick start
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY TEST_BENCH_EXAMPLE IS
END TEST_BENCH_EXAMPLE;
ARCHITECTURE behavior OF TEST_BENCH_EXAMPLE IS
COMPONENT circuit
PORT(
a,b,c : IN std_logic;
z : OUT std_logic);
END COMPONENT;
signal a,b,c,z: std_logic;
BEGIN
DUT: circuit PORT MAP (
a=> a,
b=> b,
c=> c,
z=> z);
a<='1','0' after 10 ns;
b<='1','0' after 20 ns;
c<='1','0' after 5 ns,'1'after 15 ns;
END;