SCHOOL OF ELECTRONICS ENGINEERING

Winter Semester 2022-2023

MVLD602L
LOW POWER IC DESIGN
Digital Assignment - II

PAPER TOPIC

ASIC implementation of fuzzy logic based automatic car-parking system

STUDENT DETAIL:
NAME : LOKESH DEWANGAN
REG. NO.: 22MVD0069

SUBMITTED TO:
Dr. SRI ADIBHATLA SRIDEVI
DEPARTMENT OF MICRO AND NANOELECTRONICS
VELLORE INSTITUTE OF TECHNOLOGY, VELLORE, TAMILNADU, INDIA.

RELATED DOCUMENT LINK:

https://drive.google.com/drive/folders/1a5DBzYPt7MMU8wkt17_fZF8Cl4TK-qH-?usp=sharing
AIM: Applying Low power Technique to a De-fuzzifier Module to reduce power
dissipation.

Topic: Under the Application of Artificial Intelligence – “ASIC implementation of fuzzy

logic based automatic car-parking system.”

De-fuzzifier Architecture

Fig. 1: Optimized resource-shared architecture of the de-fuzzifier for the proposed car-
parking system.

Working Description
Sensors Data is Fed to ADC controller using Multiplexer controller which is further
Fetched by Fuzzy Logic Controller and this FLC is controlled using FSM block.
FLC has two major components 1. Fuzzifier which is basically converts x direction and
y direction distance to fuzzy rule base set
The De-Fuzzifier uses a behaviour based crisp algorithm and generates crisp values
that is used to control the vehicle motion and direction.
 Fig. 2: Block diagram representing the complete working flow of the system

DEFUZZIFIER ARCHITECTURE DESCRIPTION

3:1 Multiplexer Fuzzifier 1 and Fuzzifier 2 inputs are given to two 3:1
Multiplexers.
9:1 Multiplexer Predefined Fuzzy Rule Base set is fed to 9:1 multiplexer.
Comparator Compares the input sets x and y and generates weights of
each code.
Multiplier The multiplication of Fuzzy Rule base and Weights are
happed here and result is fed to Adder 1.
Adder 1 Adder 1 adds present multiplier output with past multiplier
output to generate the ∑ (fi . wi) function.
Adder 2 Adder 2 adds present comparator output with past
comparator output to generate the ∑(wi) function.
D Flip-Flop 1 It is basically used to store the adder 1 output till next clock
cycle.
D Flip-Flop 2 It is basically used to store the adder 2 output till next clock
cycle.
Divider Finally, Adder 2 output is divided with Adder 1 output to
generate final De-fuzzifier Output.
 SOME KEY TERMS OF PROPOSED ARCHITECTURE

Fig. 3: Membership Function and Fuzzifier

1) FUZZIFIER: In real world applications,

inputs are fetched from sensors (crisp
values), which cannot be directly fed to the
rule base system. Therefore, a fuzzifier
maps real-valued point x 𝜖 U⊂𝑅 𝑛 to a
fuzzy set A’𝜖U. The range of inputs x and y
is mapped to sets NEG (𝑛1, 𝑛2), POS (𝑝1,
𝑝2) and ZERO (𝑧1, 𝑧2) by using
membership function, as shown in Fig. 3.

2) FUZZY RULE BASE: A fuzzy set is Fig. 4: Conventional Architecture of De-Fuzzifier

processed by a set of if-then rules, called
fuzzy rule, which is a knowledge base to
determine the behaviour of the output. 3) DE-FUZZIFIER: On the other hand, the
Fuzzy rules are collected from human de-fuzzifier converts behaviour-based output
experts and play a crucial role in obtained from fuzzy rule base back to a crisp
determining the output of a system. These value. Fig. 4.
rules need to be re-tuned on the basis of Subsequently, this crisp value is fed to the
experience, to get accurate output. For a actuator.
different combination of inputs, the fuzzy
rule base function is shown in TABLE I.

TABLE I. Fuzzy Rule Base

Defuzzification is performed using Below
Input X Input Y Output Z
ZERO ZERO F1
Function where fi is termed as Fuzzy rule
POS ZERO F2 base and wi is termed as weighting
NEG ZERO F3 parameter.
ZERO POS F4
POS POS F5
NEG POS F6
ZERO NEG F7
POS NEG F8
NEG NEG F9
 SYNTHESIZABLE RTL CODE

TOP MODULE : DEFUZZIFIER

module FLC (n1,z1,p1,f1,f2,f3,f4,f5,f6,f7,f8,f9,n2,z2,p2,flc_out, clock, enable);
input [8:0] n1,z1,p1,f1,f2,f3,f4,f5,f6,f7,f8,f9,n2,z2,p2;
input clock,enable;
output wire [9:0] flc_out;
wire [1:0] sel_1,sel_2;
wire [8:0] mux_out1, mux_out2;
wire [8:0] weight;
wire [3:0] sel_3;
wire [8:0] mux_out3;
wire [9:0] multi_out;
wire [9:0] add1_out,add2_out,Qout1,Qout2;

control_unit CONTROL_0069 (clock,enable,sel_1,sel_2,sel_3);

mux3x1 MUX1_0069 (z1,n1,p1,sel_1,mux_out1);

mux3x1 MUX2_0069 (z2,n2,p2,sel_2,mux_out2);

compare COMP_0069 (mux_out1,mux_out2,weight);

mux9x1 MUX3_0069 (f1,f2,f3,f4,f5,f6,f7,f8,f9,sel_3, mux_out3);

multiplier MULTI_0069(weight,mux_out3,multi_out);

adder1 adder1_0069 (multi_out,Qout1,add1_out);

dflip d1_0069 (add1_out,Qout1,clock);

adder2 adder2_0069 (weight,Qout2,add2_out);

dflip d2_0069 (add2_out,Qout2,clock);

divider DIV_0069 (add2_out,add1_out,flc_out);

endmodule
 SUB MODULE : D FLIP-FLOP
module dflip(Din,Qout,CLOCK);

input CLOCK;

input [9:0] Din;

output reg [9:0]Qout;

assign Qout = 10'd0;

always @ (posedge CLOCK)

begin

Qout <= Din;

end

endmodule

SUB Module : 3x1 MUX

module mux3x1 (A,B,C,mux_sel,mux_out);

input [8:0] A,B,C;
input [1:0]mux_sel;
output wire [8:0] mux_out;
reg [8:0] out;

always @(mux_sel)
begin
case(mux_sel)

2'b00: out <= A;

2'b01: out <= B;

2'b10: out <= C;

default: out <= 0;

endcase
end

assign mux_out = out;

endmodule
 SUB Module : 9x1 MUX

module mux9x1(A,B,C,D,E,F,G,H,I, mux_sel, mux_out);

input [8:0] A,B,C,D,E,F,G,H,I;

input [3:0]mux_sel;
output wire [8:0] mux_out;
reg [8:0] out;

always @(mux_sel)
begin
case(mux_sel)

4'b0000: out <= A;

4'b0001: out <= B;

4'b0010: out <= C;

4'b0011: out <= D;

4'b0100: out <= E;

4'b0101: out <= F;

4'b0110: out <= G;

4'b0111: out <= H;

4'b1000: out <= I;

default: out <= 0;

endcase

end

assign mux_out = out;

endmodule
 SUB MODULE : COMPARATOR

module compare(cmp_in1,cmp_in2,cmp_out);

input [8:0 ]cmp_in1,cmp_in2;

output wire [8:0 ]cmp_out;
reg [8:0] out;
always @ (cmp_in1 or cmp_in2)

if (cmp_in1<cmp_in2)
out <= cmp_in1;
else
out<=cmp_in2;

assign cmp_out = out;

endmodule

SUB Module : ADDER 1 and ADDER 2

module adder2 (A,B,ADD_OUT);

input [9:0] B;
input [8:0] A;
output wire [9:0] ADD_OUT;
assign ADD_OUT = A+B;

endmodule

module adder1 (A,B,ADD_OUT);

input [9:0] A,B;
output wire [9:0] ADD_OUT;
assign ADD_OUT = A+B;

endmodule
 SUB Module : MULTIPLIER

module multiplier(A,B,MULTI_OUT);
input [8:0] A,B;
output [9:0] MULTI_OUT;

reg [9:0]out;

always @ (A or B)
out<=A*B;

assign MULTI_OUT = out;

endmodule

SUB Module : DIVIDER

module divider(A,B,DIV_OUT);
input [9:0] A,B;
output [9:0] DIV_OUT;

reg [9:0] out;

always @ (A or B)
out<=B/A;

assign DIV_OUT = out;

endmodule
 SUB Module : CONTROLLER

module control_unit (clock,enable,sel_1,sel_2,sel_3);

input clock,enable;
output reg [1:0] sel_1,sel_2;
output reg [3:0] sel_3;

reg [1:0] i,j;

reg [3:0] k;
assign i=0,j=0,k=0;

always @ (posedge clock or enable)

begin
if(enable)
begin
if (j<3)
begin
sel_1 = i;
sel_2 = j;
j=j+1;
sel_3=k;
k=k+1;
end
else
begin
i=i+1;
j=0;
end
if (i == 3)
begin
i=0;
end
if (k == 9)
k= 0;
end

end

endmodule
 FUNCTIONAL VERIFICATION

TestBench Code
`timescale 1ns/1ns

module test_flc();
reg [8:0] n1, z1, p1, f1, f2, f3, f4, f5, f6, f7, f8, f9, n2, z2, p2;
reg clock, enable;
reg [1:9] fuzzy_logic;
wire [9:0] flc_out;

FLC DUT (n1,z1,p1,f1,f2,f3,f4,f5,f6,f7,f8,f9,n2,z2,p2,flc_out, clock, enable);

always #5 clock = ~clock;

initial
begin

clock = 0;
enable = 1;

n1= 1;
n2 =2;
p1 = 1;
p2 = 3;
z1 = 4;
z2 = 6;
f1 = 1;
f2 = 2;
f3 = 3;
f4 = 4;
f5 = 5;
f6 = 6;
f7 = 7;
f8 = 8;
f9 = 9;

$monitor (" fuzzier 1 Outputs: N1 = %d : Z1 = %d : P1 = %d \n

fuzzier 2 Outputs: N2 = %d : Z2 = %d : P2 = %d \n fuzzy Rule Base Functions [f1 to f9] =
{%d,%d,%d,%d,%d,%d,%d,%d,%d} \n Defuzzyfier Output = %d
\n----------------------------------------------------------------------\n",
n1, z1, p1, n2, z2, p2, f1, f2, f3, f4, f5, f6, f7, f8, f9, flc_out);

#170 $stop;

end

endmodule
SIMULATION WAVEFORM

TRANSCRIPT RESULT
 SYNOPSYS VCS VERIFICATION

Command Line to invoke Synopsys VCS:

filelist:
FLC.v
adder.v
comparator.v
controller.v
Dflip.v
divider.v
multi.v
mux3.v
mux9.v
test_flc.v

SCHEMATIC VIEW IN VCS

SILULATION WAVEFORM

TRANSCRIPT WINDOW
 SYNTHESIS OF THE DEFUZZIFIER USING SYNOPSYS DESIGN COMPILER

Design Compiler View

Schematic View in Design Compiler Before Synthesis

Synthesis Script Files:

set_svf "FLC.svf"
set DESIGN_REF_PATH "/home/userdata/22mvd0069/AsicLab69/tmp/ref"

set SEARCH_PATH "\

/home/userdata/22mvd0069/AsicLab69/tmp/ref/milkyway/saed32nm_lvt_1p9m \
/home/userdata/22mvd0069/AsicLab69/tmp/ref/milkyway/saed32nm_hvt_1p9m \
/home/userdata/22mvd0069/AsicLab69/tmp/ref/milkyway/saed32nm_rvt_1p9m \
/home/userdata/22mvd0069/AsicLab69/tmp/ref/milkyway/saed32sram_lp "

set TARGET_LIBRARY_FILES " \

${DESIGN_REF_PATH}/DBs/saed32hvt_ff0p95v125c.db \
${DESIGN_REF_PATH}/DBs/saed32hvt_ff0p95vn40c.db \
${DESIGN_REF_PATH}/DBs/saed32hvt_ff1p16v125c.db \
${DESIGN_REF_PATH}/DBs/saed32hvt_ff1p16vn40c.db \
${DESIGN_REF_PATH}/DBs/saed32rvt_ff0p95v125c.db \
${DESIGN_REF_PATH}/DBs/saed32rvt_ff0p95vn40c.db \
${DESIGN_REF_PATH}/DBs/saed32rvt_ff1p16v125c.db \
${DESIGN_REF_PATH}/DBs/saed32rvt_ff1p16vn40c.db \
${DESIGN_REF_PATH}/DBs/saed32lvt_ff0p95v125c.db \
${DESIGN_REF_PATH}/DBs/saed32lvt_ff0p95vn40c.db \
${DESIGN_REF_PATH}/DBs/saed32lvt_ff1p16v125c.db \
${DESIGN_REF_PATH}/DBs/saed32lvt_ff1p16vn40c.db \
${DESIGN_REF_PATH}/DBs/saed32hvt_ss0p75v125c.db \
${DESIGN_REF_PATH}/DBs/saed32hvt_ss0p75vn40c.db \
${DESIGN_REF_PATH}/DBs/saed32hvt_ss0p95v125c.db \
${DESIGN_REF_PATH}/DBs/saed32hvt_ss0p95vn40c.db \
${DESIGN_REF_PATH}/DBs/saed32rvt_ss0p75v125c.db \
${DESIGN_REF_PATH}/DBs/saed32rvt_ss0p75vn40c.db \
${DESIGN_REF_PATH}/DBs/saed32rvt_ss0p95v125c.db \
${DESIGN_REF_PATH}/DBs/saed32rvt_ss0p95vn40c.db \
${DESIGN_REF_PATH}/DBs/saed32lvt_ss0p75v125c.db \
${DESIGN_REF_PATH}/DBs/saed32lvt_ss0p75vn40c.db \
${DESIGN_REF_PATH}/DBs/saed32lvt_ss0p95v125c.db \
${DESIGN_REF_PATH}/DBs/saed32lvt_ss0p95vn40c.db \
${DESIGN_REF_PATH}/DBs/saed32sramlp_ff0p95v125c_i0p95v.db \
${DESIGN_REF_PATH}/DBs/saed32sramlp_ff0p95vn40c_i0p95v.db \
${DESIGN_REF_PATH}/DBs/saed32sramlp_ff1p16v125c_i1p16v.db \
${DESIGN_REF_PATH}/DBs/saed32sramlp_ff1p16vn40c_i1p16v.db \
${DESIGN_REF_PATH}/DBs/saed32sramlp_ss0p75v125c_i0p75v.db \
${DESIGN_REF_PATH}/DBs/saed32sramlp_ss0p75vn40c_i0p75v.db \
${DESIGN_REF_PATH}/DBs/saed32sramlp_ss0p95v125c_i0p95v.db \
${DESIGN_REF_PATH}/DBs/saed32sramlp_ss0p95vn40c_i0p95v.db "

set LINK_LIBRARY_FILES "* \

${DESIGN_REF_PATH}/DBs/saed32hvt_ff0p95v125c.db \
${DESIGN_REF_PATH}/DBs/saed32hvt_ff0p95vn40c.db \
${DESIGN_REF_PATH}/DBs/saed32hvt_ff1p16v125c.db \
${DESIGN_REF_PATH}/DBs/saed32hvt_ff1p16vn40c.db \
${DESIGN_REF_PATH}/DBs/saed32rvt_ff0p95v125c.db \
${DESIGN_REF_PATH}/DBs/saed32rvt_ff0p95vn40c.db \
${DESIGN_REF_PATH}/DBs/saed32rvt_ff1p16v125c.db \
${DESIGN_REF_PATH}/DBs/saed32rvt_ff1p16vn40c.db \
${DESIGN_REF_PATH}/DBs/saed32lvt_ff0p95v125c.db \
${DESIGN_REF_PATH}/DBs/saed32lvt_ff0p95vn40c.db \
${DESIGN_REF_PATH}/DBs/saed32lvt_ff1p16v125c.db \
${DESIGN_REF_PATH}/DBs/saed32lvt_ff1p16vn40c.db \
${DESIGN_REF_PATH}/DBs/saed32hvt_ss0p75v125c.db \
${DESIGN_REF_PATH}/DBs/saed32hvt_ss0p75vn40c.db \
${DESIGN_REF_PATH}/DBs/saed32hvt_ss0p95v125c.db \
${DESIGN_REF_PATH}/DBs/saed32hvt_ss0p95vn40c.db \
${DESIGN_REF_PATH}/DBs/saed32rvt_ss0p75v125c.db \
${DESIGN_REF_PATH}/DBs/saed32rvt_ss0p75vn40c.db \
${DESIGN_REF_PATH}/DBs/saed32rvt_ss0p95v125c.db \
${DESIGN_REF_PATH}/DBs/saed32rvt_ss0p95vn40c.db \
${DESIGN_REF_PATH}/DBs/saed32lvt_ss0p75v125c.db \
${DESIGN_REF_PATH}/DBs/saed32lvt_ss0p75vn40c.db \
${DESIGN_REF_PATH}/DBs/saed32lvt_ss0p95v125c.db \
${DESIGN_REF_PATH}/DBs/saed32lvt_ss0p95vn40c.db \
${DESIGN_REF_PATH}/DBs/saed32sramlp_ff0p95v125c_i0p95v.db \
${DESIGN_REF_PATH}/DBs/saed32sramlp_ff0p95vn40c_i0p95v.db \
${DESIGN_REF_PATH}/DBs/saed32sramlp_ff1p16v125c_i1p16v.db \
${DESIGN_REF_PATH}/DBs/saed32sramlp_ff1p16vn40c_i1p16v.db \
${DESIGN_REF_PATH}/DBs/saed32sramlp_ss0p75v125c_i0p75v.db \
${DESIGN_REF_PATH}/DBs/saed32sramlp_ss0p75vn40c_i0p75v.db \
${DESIGN_REF_PATH}/DBs/saed32sramlp_ss0p95v125c_i0p95v.db \
${DESIGN_REF_PATH}/DBs/saed32sramlp_ss0p95vn40c_i0p95v.db "

##########################################################################################
# User-defined variables for physical library setup in dc_setup.tcl
##########################################################################################

set MW_DESIGN_LIB MY_DESIGN_LIB ;# User-defined Milkyway design library name

# Milkyway reference libraries

set MW_REFERENCE_LIB_DIRS "${SEARCH_PATH} "

set TECH_FILE "${DESIGN_REF_PATH}/tech/saed32nm_1p9m.tf" ;# Milkyway technology file

set TLUPLUS_MAX_FILE "${DESIGN_REF_PATH}/tech/saed32nm_1p9m_Cmax.lv.tluplus" ;#Max TLUPlus file

set TLUPLUS_MIN_FILE "${DESIGN_REF_PATH}/tech/saed32nm_1p9m_Cmin.lv.tluplus" ;#Min TLUPlus file

set MAP_FILE "${DESIGN_REF_PATH}/tech/saed32nm_tf_itf_tluplus.map" ;# Mapping file for TLUplus

######################################################################
# Logical Library Settings
######################################################################
set_app_var search_path "$SEARCH_PATH"
set_app_var target_library "$TARGET_LIBRARY_FILES"
set_app_var link_library " $LINK_LIBRARY_FILES "

######################################################################
# Physical Library Settings
######################################################################

set_app_var mw_reference_library $MW_REFERENCE_LIB_DIRS

set_app_var mw_design_library $MW_DESIGN_LIB

# create new Milkyway design library

#create_mw_lib -technology $TECH_FILE \

# -mw_reference_library $mw_reference_library \
# $mw_design_library

# Only create new Milkyway design library if it doesn't already exist

if {![file isdirectory $mw_design_library ]} {
create_mw_lib -technology $TECH_FILE \
-mw_reference_library $mw_reference_library \
-hier_separator {/} \
-bus_naming_style {[%d]} \
$mw_design_library
} else {
# If Milkyway design library already exists, continue by opening the existing library
}

open_mw_lib $mw_design_library
check_library
set_tlu_plus_files -max_tluplus $TLUPLUS_MAX_FILE -min_tluplus $TLUPLUS_MIN_FILE \
-tech2itf_map $MAP_FILE

check_tlu_plus_files

analyze -library WORK -format verilog {./FLC.v \ ./adder.v \ ./comparator.v \ ./controller.v \ ./ Dflip.v\ ./divider.v \ ./multi.v \ ./mux3.v \ ./mux9.v \ }
read_file -format verilog {./FLC.v}

current_design FLC

link
check_design

source ./FLC_22mvd0069.sdc
check_timing

source ./physical_22mvd0069.tcl
#extract_physical_constraints ./floorplan/floorplan.def

#set_wire_load_model -name "8000"

#set_wire_load_mode segmented

compile_ultra -no_autoungroup
#-incremental -spg

file mkdir report_physical

report_area > ./report_physical/chiptop_area.log
report_power > ./report_physical/chiptop_power.log
report_timing > ./report_physical/chiptop_timing.log
report_timing -delay_type min > ./report_physical/chiptop_timing_delay_min.log
report_qor > ./report_physical/chiptop_qor.log

change_names -rule verilog -hier

write -hierarchy -format verilog -output ./chiptop_physical_netlist.v
write_sdc ./chiptop_phy.sdc

gui_start

Constraint File
Logical Constraints
create_clock -period 3.0 [get_ports clock]
set_clock_latency -source -max 1.0 [get_clocks clock]
set_clock_latency -source -min 0.5 [get_clocks clock]
set_clock_latency -max 1.0 [get_clocks clock]
set_clock_latency -min 0.5 [get_clocks clock]
set_clock_uncertainty -setup 0.15 [get_clocks clock]
set_clock_transition -max 0.5 [get_clocks clock]

Physical Constraints
set_placement_area -coordinate {0 0 400 450}
set_port_side [remove_from_collection [all_inputs] [get_ports "clock"]] -side right
set_port_side [get_ports [all_outputs]] -side left
set_port_side [get_ports "clock"] -side bottom
create_placement_blockage -name Blockage1 -coordinate {0 80 20 100}
create_placement_blockage -name Blockage2 -coordinate {120 0 150 30}
SIMULATION RESULTS
Before Clock Gating

Clock Gating Command

Compile_ultra -no_autoungroup -gate_clock
After Clock Gating
TABLE II. Result Analysis

Synthesis Technique Power Consumption

Normal Compilation 35.6240uW
With Clock Gating Compilation 2.8701uW

#% Reduction in power = 91.944%

CONCLUSION
In Synopsys Design Compiler the physical synthesis is performed in 32nm technology. Here,
I have used Clock gating method to reduce the power consumption and here I found that
91.95% power consumption is reduced.