Unit 4

Introduction to Microcontroller
8051
 Introduction to Microcontroller 8051
Microprocessors and Microcontrollers comparison, 8051 architecture, Pin description,
addressing modes, instruction set of 8051, concepts of Counters and Timers with the help
of status registers, Serial communication, Port Structure and Interrupts. Simple
programming examples – for addition, subtraction, multiplication.
Unit Objectives:
To understand the basics of Microprocessors & Microcontrollers.
To learn in depth concepts of hardware in Microcontroller.
To understand architecture and features of typical Microcontroller
To understand the programming details of Microcontroller.
Unit outcomes:
Able to select the microcontroller according to application
Able to learn use of hardware and software tools
Able to do programming using assembly
Reference Books:
1. Muhammad Mazidi, Janice Mazidi and Rolin McKinley, „The 8051 Microcontroller
and Embedded Systems using Assembly and C‟, Pearson Education, 2nd edition.
2. Kenneth J. Ayala, „The 8051 Microcontroller‟, Cengage Learning.
3. Myke Predko, „Programming and customizing the 8051 microcontroller‟, TMH.
Aspects of a microprocessor/controller

It is a Multifunctional , Reprogrammable logic device

Without memory and I/O---- Its Microprocessor

Single chip Microcomputer ---- Microcontroller

Hardware : Interface to the real world

Software: order how to deal with inputs
It is a Multifunctional , programmable, Clock driven, register based
electronic device that reads binary instruction from a storage device
called memory, accepts binary data as a input and process data
according to instruction and provide result as a output.
Microprocessor – Basic concept

ADDRESS BUS
16/32/ 64-bit wide

CPU contains

ALU CONTROL BUS

CCU Timing signals, ready
data registers signals,
and interrupts etc
pointer registers

DATA BUS – bidirectional

4bit/8-bit / 16-bit / 32-bit
/ 64bit/128-bit
Microprocessor, by-itself, completely useless – must have external
peripherals to Interact with outside world
ALU: Arithmetic logic unit, CCU: Clock Control Unit
 The Necessary Tools for MP/ MC

CPU: Central Processing Unit

I/O: Input / Output
Bus: Address bus & Data bus
Memory: RAM & ROM
Timer/Counter
Interrupt
Serial Port
Parallel Port
 Microprocessors and Microcontrollers
CPU Bus- Clock- Mem
bit MHz
4004 4

8085 8 3.07 64 K b

8086 16 5-10 1Mb

80286 16 6-12.5 16 Mb

80386 32 16-33 4 Gb

Pentiu 64 60-100 4 Gb
CPU for Computers, No RAM, ROM, I/O on CPU chip itself m
Example：Intel’s x86, Motorola’s 680x0
Pen- 64 150-200 4 Gb
Pro
Features 8031 8051 8052

ROM -- 4K 8K

RAM 128 128 256

(Bytes)
I/O Pins 32 32 32

Timers 2 2 3
• A smaller computer, On-chip RAM, ROM, I/O ports... Serial 1 1 1
• Example：Motorola’s 6811, Intel’s 8051, and PIC ports
16X Interrupts 6 6 8
 Microprocessor vs. Microcontroller
Microprocessor Microcontroller
 CPU is stand-alone, RAM, • CPU, RAM, ROM, I/O and timer
ROM, I/O, timer are external are all on a single chip
 Expensive and versatile for • Fixed amount of on-chip ROM,
design RAM, I/O ports
 General-purpose • Application Specific
 High power consumption • Low power consumption
 Instruction sets focus on • Instruction sets focus on control
processing-intensive operations and bit-level operations
 Typically 32/64 – bit • Typically 8/16 bit
• Typically single-cycle/two-stage
 Typically deep pipeline (5-20
stages) pipeline
• Clock speed range from 6-20 MHZ
 Clock speed range from 3.07 -
100 MHZ
 Has less no. of multifunctional • Ports used are multifunctional
pins
 Applications of Microcontroller
Home
Appliances, intercom, telephones, security systems, garage
door openers, answering machines, fax machines, home
computers, TVs, cable TV tuner, VCR, camcorder, remote
controls, video games, cellular phones, musical instruments,
sewing machines, lighting control, paging, camera, pinball
machines, toys, exercise equipment
Office
Telephones, computers, security systems, fax machines,
Microwave, copier, laser printer, colour printer, paging
Auto
Trip computer, engine control, air bag, ABS, instrumentation,
security system, transmission control, entertainment, climate
control, cellular phone, keyless entry.
 Three criteria in Choosing a Microcontroller

1. Meeting the computing needs of the task efficiently and cost

effectively
• Speed, the amount of ROM and RAM, the number of I/O
ports and timers, size, packaging, power consumption,
easy to upgrade, cost per unit
2. Availability of software development tools
• assemblers, debuggers, C compilers, emulator, simulator,
technical support.
3. wide availability and reliable sources of the microcontrollers.
 Architecture of MP and MC
Address
Address

Input Control CPU ALU Output

Data Data

Address Data
Von Neumann Architecture
Memory
(Program and Data)

Address
Address
Input Control CPU ALU Output

Data Data Data

Address Data Address Data

Harvard Architecture

Program Data
Memory Memory
 Comparison of Von Neumann and Harvard
Von Neumann architecture Harvard architecture

 Fetches Instruction and Data

– Fetches instructions and from two separate memory
data from a single memory spaces
space  Improved operating
– Limits operating bandwidth bandwidth
– Allows for fixed bus widths  Allows for different bus widths
– Architecture --- CISC  Architecture --- RISC
– Variable instruction format  Fixed instruction format
– Time multiplexing is used to  No Need of Time
Multiplexing due to separate
fetch data and program bus
 RISC vs CISC: Characteristics

RISC CISC

1. Simple Instruction taking 1 cycle 1. Complex Instruction taking multiple cycles

2. Only LOADs, STOREs access memory 2. Any Instruction. may access memory

3. Designed around pipeline 3. Designed around Instruction Set

4. Instruction executed by hardware 4. Instruction interpreted by micro program

5. Fixed format Instruction 5. Variable format Instruction

6. Few Instruction and modes 6. Many Instruction and modes

7. Complexity in the compiler 7. Complexity in the micro program

8. Multiple register sets 8. Single register set

9. Operates at 50-150 MHz 9. Operates at 33-50 MHz

 Limitation of 8 bit controller

 Data bus width limits speed of execution

 Addressable memory is limited for given application

 Very small RAM & Flash memory

 Does not have high performance interrupt system

 Does not have DMA & cache memory for faster

execution

 Can not implement RTOS which is current need of

embedded system
 FEATURES of 8051

 8-bit CPU optimized for control applications

 On chip clock oscillator 6-12 MHz
 4K bytes of on chip Program Memory
 128 bytes of on-chip Data RAM
 64K Program Memory address space
 64K Data Memory address space
 32 bidirectional and individually addressable 1/0 lines
 Can operate on Bits, Bytes, Words
 34- general purpose, 3- pointers , 21 SFRs
 Extensive Boolean processing (Single-bit logic) capabilities
 Two 16-bit timer/counters
 6-source/5-vector interrupt structure with two priority levels
 BLOCK DIAGRAM

INT0
INT1
T0
TF0
Interrupt Timer 0
TF1 4K 128
Control TI/RI
ROM RAM Timer 1
T1

CPU

OSC Bus Serial

4 I/O Ports
Control Port

TXD RXD
P0 P1 P2 P3
8051 Internal Block Diagram
8051
Foot Print
P1.0 1 40 Vcc
P1.1 2 39 P0.0(AD0)
P1.2 3 38 P0.1(AD1)
P1.3 4 37 P0.2(AD2)
EA- External P1.4 5 36 P0.3(AD3)
access P1.5 6 35 P0.4(AD4)
PSEN-Program P1.6 7 34 P0.5(AD5)
Store Enable. P1.7 8 33 P0.6(AD6)
used to read RST 9
8051 32 P0.7(AD7)
external (RXD)P3.0 10 (8031) 31 EA/VPP
memory. (TXD)P3.1 11 30 ALE/PROG
VPP-During (INT0)P3.2 12
(8751) 29 PSEN
Flash (INT1)P3.3 13 (8951) 28 P2.7(A15)
Programming, (T0)P3.4 14 27 P2.6(A14)
this Pin (T1)P3.5 15 26 P2.5(A13)
receives 12V (WR)P3.6 16 25 P2.4(A12)
Programming (RD)P3.7 17 24 P2.3(A11)
Enable XTAL2 18 23 P2.2(A10)
Voltage (VPP). XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)
 BLOCK DIAGRAM
 Accumulator A & B with 32 GPR, 21 SFRs
 Parallel Input/Output Ports
 Memory RAM/ROM
 System Clock Generator
 Serial Port
 Timers/counters
 Interrupt Control
 Registers

A PSW (8)

R0 SP (8)
R1

R2
DPH DPL DPTR (16)
R3

R4
PC PC (16)
R5

R6 Some 8051 16-bit Register hold

R7 addresses

Some 8-bitt Registers

of the 8051

34- general purpose, 3- pointers , 21 SFRs

 Map of SFRS (80-FF)
F8 FF
F0 B F7
E8 EF
E0 Acc E7
D8 DF
D0 PSW D7
C8 CF
C0 C7
B8 IP BF
B0 P3 B7
A8 IE AF
A0 P2 A7
98 SCON SBUF 9F
90 P1 97
88 TCON TMOD TL0 TL1 TH0 TH1 8F
80 P0 SP DPL DPH PCON 87
Programming Model of 8051
 Registers A, B , R0-7
Accumulator (A ,8 bit – 0E0 )
 It is a general-purpose register used for storing intermediate results obtained
during operation.
 Prior to executing an instruction upon any number or operand, it is necessary to
store it in the accumulator first.
 All results obtained from arithmetical operations performed by the ALU are stored
in the accumulator.
 Data to be moved from one register to another must go through the
accumulator.
 In other words, the „A‟ register is the most commonly used register in performing
operations on Data.
Accumulator (B ,8 bit - 0F0)
 It is a general-purpose register used for performing Multiplication and Division
operation with „A‟
 Multiplies 8 bit unsigned values in A and B and leaves the 16 bit result in A (low
byte) and B (high byte)
 Divided A by B, leaving the integer result in A and remainder in B
 It is bit-addressable
Registers (r0-r7 , 8 bit - 00-1F)
 These are general-purpose register available in Banks -- Total 32
 Out of that r0 & r1 act as pointers for internal memory related operations
 Program status word (PSW ,8 bit , 0D0)

Flags are 1-bit registers used to store the result of program instructions
Has 4 math flags (CY, AC, OV, P), 3 - General purpose flags set by User
It is Bit addressable
 Pointers SP, DPTR, PC

Stack Pointer (SP ,8 bit – 81)

 It contains the address of the data item currently on top of the stack.
 Stack operations include pushing data on the stack and popping data off the stack
 Pushing increments SP before writing the data and Popping from the stack reads the
data and decrements the SP
 8051 stack is kept in the internal RAM
 Depending on the initial value of the SP, stack can have different sizes
 power on reset gives contents of SP =07h address ( By default)
 On 8051 this would limit the stack to 32 bytes since the uppermost address of on chip
RAM is 7FH
Data Pointer (DPTR , 16 bit – DPH -83, DPL-82)
 It is used to access external data or code memory
 It can be used as 8 bit register as DPH and DPL separately

Program Counter (PC, 16 bit – 81)

 It Holds the address of next instruction to be executed
 Registers --- SFRS
 Special Function Registers (SFRs) are a sort of control table used for
running and monitoring the operation of the microcontroller.
 SFR has only 21 such registers.

 TH0-TL0 and TH1-TL1 ---16 bit timer registers

 P0-P3 – port latches
 SP, PSW, IP – Interrupt Priority, IE – enable
 TCON – Timer/Counter control reg
 Interrupt control flags for ext. interrupt like INT1 and
INT0
 TMOD – modes of operation of timer/counter
 SCON – serial port mode control reg
 SBUF – serial data buffer for transmit and receive
 PCON – Power control reg – power down bit, idle
bit
 PIN DETAILS

P1
P0

RESET
+
_
P3

P2

XTAL
 Important points
 Power On reset -- Restore initial setting – 2M/C(Machine cycle-Fetch,
decode and execute cycles)
 Clock circuit --- uses 11.0592 MHz clock- need to maintain std baud rate
T= [No. of M/c Cycles * 12]/Crystal frequency
Normally clock frequency for 8051 is chosen as 11.0592 MHz yield
921.6KHz which can be evenly divided by standard communication
baud rates 300,600 ,1200, 2400,4800,9600 and so on
 By default all I/O lines go high on Reset
 Ioh= 60 µA, -Current sinking capacity
 Iol =1.6 ma - current sourcing capacity
 EA & PSEN – used to access internal and External memory
 ALE - Differentiate Address and data on AD0- AD7 – port0
 Important pins

• PSEN (out): Program Store Enable, the read

signal for external program memory (active low).
• ALE (out): Address Latch Enable, to latch
address outputs at Port0 and Port2
• EA (in): External Access Enable, active low to
access external program memory locations 0 to
4K
• RXD,TXD: UART pins for serial I/O on Port 3
• XTAL1 & XTAL2: Crystal inputs for internal
oscillator.
• RST : clear all the content of register and set the
default values –two m/c cycles
PORT OPERATIONS
 PIN DETAILS

P1
P0

RESET
+
_
P3

P2

XTAL
 Port Operation
• One of the most useful features of the 8051 is that it contains
four I/O ports (P0 - P3)– By default all lines are HIGH

• Port 0 （pins 32-39）：P0（P0.0～P0.7）

– 8-bit R/W - General Purpose I/O
– Or acts as a multiplexed low byte address and data bus for external
memory design hence needs Pull up registers (10K)

• Port 1 （pins 1-8） ：P1（P1.0～P1.7）

– Only 8-bit R/W - General Purpose I/O

• Port 2 （pins 21-28）：P2（P2.0～P2.7）

– 8-bit R/W - General Purpose I/O
– Or high byte of the address bus for external memory design

• Port 3 （pins 10-17）：P3（P3.0～P3.7）

– General Purpose I/O
– if not using any of the internal peripherals (timers) or external interrupts.

• Each port can be used as input or output (bi-direction)

 Hardware Structure of I/O Pin
• Each pin of I/O ports
– Internally connected to CPU bus
– A D latch store the value of this pin
• Write to latch＝1：write data into the D latch
– 2 Tri-state buffer：
• TB1: controlled by “Read pin”
– Read pin＝1：really read the data present at
the pin
• TB2: controlled by “Read latch”
– Read latch＝1：read value from internal latch
– A transistor M1 gate
• Gate=0: open
• Gate=1: close
 Addressing Modes

The way of specifying operand of an instruction is called addressing modes

1. Register : mov a,b; mov a, r0

2. Direct : add a, 55h; mov@r0, 20h; mov 6,2; mov 56h,a

3. Register Indirect: mov a,@r0, mov@r1, a

4. Immediate : mov r0, #23h, add a, #1234h, mov @r0, #55h;

5. Implicit : CPL A; STB,C

6. Indexed Addressing: movc a, @a+dptr

7. Relative
 Short : SJMP with in 256 byes (-128 to +127)
 Absolute : ACAll, AJMP – with in 2Kb
 Long : LCALL, LJMP -- with in 64Kb
 Instruction Set

5 Groups
Data Transfer Group
Arithmetic Operation Group
Logical Operation Group
Boolean Variable Manipulation Group
Program Branching Group
 Data Transfer Group [ MOV, PUSH, POP,
XCHG]
 MOV A,Direct
 MOV @Ri, A  PUSH Direct
 MOV A,Rn  POP Direct
 MOV @Ri,#Data
 MOV A,@Ri  XCH A,Rn
 MOV @Ri, Direct
 MOV A,#Data  XCH A,Direct
 MOV Rn,Direct
 MOV DPTR, #DATA16  XCH A,@Ri
 MOV Rn,@Ri  MOVC A, @A+DPTR  XCHD A,@Ri
 MOV Rn,#Data  MOVC A, @A+PC
 MOV Direct, Direct  MOVX A, @Ri
 MOV Direct, Rn  MOVX @Ri, A
 MOV Direct, @Ri  MOVX @DPTR, A
 MOV Direct, #Data
 MOV Direct, A
Data Transfer Group [ MOV, PUSH, POP,
XCHG]
 Arithmetic Instructions
[Add, SUB, INC, DEC, Multi, Divide, Decimal

 SUBB A, Direct  INC A DEC A MUL AB

 ADD A,Direct  SUBB A, Rn  INC Direct DEC Direct DIV AB
DEC Rn DA A
 ADD A,Rn  SUBB A,@Ri  INC Rn
DEC @Ri
 ADD A,@Ri  SUBB A,#Data  INC @Ri
 ADD A,#Data  INC DPTR
 ADDC A,Direct
 ADDC A,Rn
 ADDC A,@Ri
 ADDC
A,#Data
 Logic Instructions
Logic operations, Clear, Rotate, Swap, Complement

 ANL A, Direct  ORL A, Direct

 ANL A, Rn  ORL A, Rn 00001111
00001111
 ORL A, @Ri ORL 10101100
 ANL A, @Ri ANL 10101100
 ORL A, #Data 10101111
 ANL A, #Data 00001100
 ORL Direct, A
 ANL Direct, A
 ORL Direct, #Data
 ANL Direct, #Data CLR ( Set all bits to 0)
 XRL A, Direct 10101100
00001111  CLR A CLR
XRL
 XRL A, Rn 10101100  CLR byte (direct mode) 00000000
 XRL A, @Ri 10100011  CLR Ri (register mode)
 XRL A, #Data  CLR @Ri(register
 XRL Direct, A indirect) 10101100
CPL
 XRL Direct, #Data CPL A 01010011

ANL C, bit; ORL C, bit; CLR C; CLR bit; CPL C; CPL bit; SETB C; SETB bit.
 Logical Operation Group - Rotate

Rotate instructions operate only on a RL a [D7--D0]

RL A Mov a,#0xF0 ;a 11110000

Rl a a 11100001
RLC A C
RLC a
RR A [D7-CY-D0]

RRC A RR a [D0-D7]

 SWAP A Mov a,#0xF0 ; a 11110000

RR a ; a 01111000

RRC a C
[D0-CY-D7]
 Logic Instructions
Logic operations, Clear, Rotate, Swap, Complement
 Boolean Variable Manipulation Group
 SETB C  JC rel
 SETB bit  JNC rel
 CLR C  JB
 CLR bit bit,re
 CPL C l
 CPL bit  JNB
bit,re
l
 MOV C,
bit  JBC
bit,re
 MOV bit,
l
C
 ANL C, bit
 ANL
C,/bit
 ORL C, bit
 ORL
C,/bit
 Program Branching Group
 ACALL addr11  JMP @A+DPTR  DJNZ Rn, rel
 LCALL addr16  JZ rel  DJNZ Direct, rel
 RET  JNZ rel  NOP
 RETI
 CJNE A, Direct,rel
 AJMP addr11
 CJNE A, #Data, rel
 LJMP addr16
 CJNE Rn, #Data, rel
 SJMP rel
 CJNE @Ri, #Data, rel
LJMP(long jump)
LJMP is an unconditional jump. It is a 3-byte instruction. It allows a jump to any memory
location from 0000 to FFFFH.

AJMP(absolute jump)
In this 2-byte instruction, It allows a jump to any memory location within the 2k block of
program memory.

SJMP(short jump)
In this 2-byte instruction. The relative address range of 00-FFH is divided into forward and
backward jumps, that is , within -128 to +127 bytes of memory relative to the address of the
current PC.
Program control group of instructions
 8051 Instruction Set
ACALL: Absolute Call
JC: Jump if Carry Set PUSH: Push Value Onto Stack
ADD, ADDC: Add Acc. (With
Carry)
JMP: Jump to Address RET: Return From Subroutine
AJMP: Absolute Jump
JNB: Jump if Bit Not Set RETI: Return From Interrupt
ANL: Bitwise AND
JNC: Jump if Carry Not Set RL: Rotate Accumulator Left
CJNE: Compare & Jump if Not
JNZ: Jump if Acc. Not Zero RLC: Rotate Acc. Left Through
Equal
Carry
JZ: Jump if Accumulator Zero
CLR: Clear Register
RR: Rotate Accumulator Right
LCALL: Long Call
CPL: Complement Register
RRC: Rotate Acc. Right Through
LJMP: Long Jump Carry
DA: Decimal Adjust
MOV: Move Memory SETB: Set Bit
DEC: Decrement Register
MOVC: Move Code Memory SJMP: Short Jump
DIV: Divide Accumulator by B
MOVX: Move Extended SUBB: Sub. From Acc. With Borrow
DJNZ: Dec. Reg. & Jump if Not
Memory
Zero
SWAP: Swap Accumulator Nibbles
MUL: Multiply Accumulator by B
INC: Increment Register
XCH: Exchange Bytes
NOP: No Operation
JB: Jump if Bit Set
XCHD: Exchange Digits
ORL: Bitwise OR
JBC: Jump if Bit Set and Clear Bit
XRL: Bitwise Exclusive OR
POP: Pop Value From Stack
Undefined: Undefined Instruction
TIMERS
SERIAL PORT
INTERRUPTS
 BLOCK DIAGRAM

INT0
INT1
T0
TF0
Interrupt Timer 0
TF1 4K 128
Control TI/RI
ROM RAM Timer 1
T1

CPU

OSC Bus Serial

4 I/O Ports
Control Port

TXD RXD
P0 P1 P2 P3
 Timer/ Counters

 Set the initial value of – Count the number of

registers events
 Start the timer and then – Show the number of events
the 8051 counts up. on registers
– External input from Tx input
 Input from internal system
pin.
clock (machine cycle)
– We use Tx to denote T0 or
 When the registers equal T1. for counter0 or 1
to 0 and the 8051 sets a
bit to denote time out
TH0
P1
8051 TL0
Set
Timer P2 P1 P3.4
a switch T0
8051
TH0

TL0 Counters
Timers
 Timer/Counters

8051 has two 16-bit Timer/Counter registers

Timer/Counter 0
Timer/Counter 1
These registers can be used as timers or as event
counters
When a register is in “Timer” state, it is incremented
every machine cycle
In “Counter” state, the register is incremented when
there is a 1-to-0 transition at its external input pin, pin
T0 (P 3.4) or T1 (P 3.5)
Both registers have additional four operating modes
Has Two SFRs TMOD & TCON
 PIN DETAILS

P1
P0

RESET
+
_
P3
Timer/Counter

P2

XTAL
 TIMER / COUNTER-- Summary
Parameter Internal External
Application Timer Counter
Purpose Delay Event Counting
Dependant On Oscillator External Pulses
Control Software Hardware
SFRS TMOD, Upper TMOD, Lower
Nibble of TCON Nibble of TCON

Flags used TF0, TF1 IE0, IE1

Control Signals C/T=0, G=0 C/T=1, G=1
55

INTERRUPTS

SKB's
 BLOCK DIAGRAM

INT0
INT1
T0
TF0
Interrupt Timer 0
TF1 4K 128
Control TI/RI
ROM RAM Timer 1
T1

CPU

OSC Bus Serial

4 I/O Ports
Control Port

TXD RXD
P0 P1 P2 P3
 PIN DETAILS

P1
P0

RESET
+
_
Hardwar
P3
eSoftware

P2

XTAL
 Interrupt
• Original 8051 provides 6 interrupt sources
 1 Reset
 2 external interrupts [ External Interrupt 0 -- INT0
External Interrupt 1 -- INT1]
 2 timer interrupts [ Timer 0 overflow- TF0;
Timer 1 overflow - TF1]
 1 Serial Port events (buffer full, buffer empty, etc [TI/RI] )

• They are controlled via two SFRs, IE and IP

• Each interrupt source can be individually enabled or disabled by
setting or clearing a bit in IE (Interrupt Enable). IE also exists a
global disable bit, which can be cleared to disable all interrupts at
once
• All interrupt are disabled after reset
 INTERRUPTS
The Interrupt structure has the following features:
• 6 sources / 5 vectored interrupts
• Each interrupts can be individually programmable
• Each interrupts can have two priority levels
• Priority levels can be programmed
• All interrupts can be masked by a single bit - EA
• External interrupt type can be programmed
 Edge triggered
 Level Triggered

What if two interrupt sources interrupt at the same time?

The interrupt with the highest PRIORITY gets serviced first.
All interrupts have a power on default priority order.
 Interrupt ISR (Vector)Address
Each interrupt has a specific place in code memory where
program execution (interrupt service routine) begins.
This internal priority structure determined by the polling
sequence and the vector addresses is shown in the following
table
Interrupt ISR Priority/pin Flag
address Clearing
System Reset 0000 /9 Auto
External INT0 0003 Highest/P3.2 Auto
(12)
Timer0 TF0 000B Auto
External INT1 0013 /P3.3 Auto
(13)
Timer1 TF1 001B Auto
Serial port 0023 Lowest Manual
RI/TI Programmer
Timer 2 overflow(8052+) 002bh

Note: that there are only 8 memory locations between vectors.

SERIAL PORT
 BLOCK DIAGRAM

INT0
INT1
T0
TF0
Interrupt Timer 0
TF1 4K 128
Control TI/RI
ROM RAM Timer 1
T1

CPU

OSC Bus Serial

4 I/O Ports
Control Port

TXD RXD
P0 P1 P2 P3
 Basics of serial communication

Parallel: expensive - short distance – fast – no modulation

Serial :cheaper– long (two different cities by modem)-slow
 Packaging Data- Asynchronous
In asynchronous transmission : each character is placed
between start and stop bits ( Framing Bits) , When there is
no transfer the signal is high. Transmission begins with a
start (low) bit –It is always one bit.
 Stop bit can be one or Two , Stop bit is high
 LSB is send out First
 Data transfer rate (baud rate) is stated in bps

Asynchronous serial transmission is widely used for the character oriented

Transmission Computer Baud Rates : 150, 300,600, 1200,2400, 4800, 9600, 19200
etc
 Pin out diagram
+
+
+
+
P1+
P0
+
RESET + +
Serial + _
P3
+

P2

XTAL
 Programming Examples
Programming Examples– Addition and Subtraction Programming – Mul and Div
.org 0000h --- Memory initialization
.org 0000h ---- Memory initialization mov r0, # 05h
mov a, # 05h ---- Store 1st no. in Acc mov b, #02
mov r0, # 04h ---- Store 2st no. in register mov a, r0
add a, r0 ---- Add the nos mul ab
mov b, a ---- store in b reg. mov r2, a
subb a, r0 ---- subtract here: sjmp here
mov r4, a ---- store in r4 reg.
here: sjmp here ---- Terminate the program

Programming Examples– port oprtation Programming – Div

.org 0000h ---- Memory initialization .org 0000h --- Memory initialization
mov p0,#0FFh ---- Configure port as input mov r0, # 05h
mov p1 , #00h ---- Configure port as output mov b, #02
mov a, # 05h ---- Store 1st no. in Acc mov a, r0
mov r0, # 04h ---- Store 2st no. in register div ab
add a, r0 ---- Add the nos mov r2, a
mov p0,a ---- store in b reg. here: sjmp here
here: sjmp here ---- Terminate the program
Thank You for Listening

Thank you