METHODS OF DATA TRANSFER AND INTERRUPT STRUCTURE IN 8085 165

for this signal and once the NDAC is high, the DAV signal is removed by the
talkers.
low logic with standard TTIL levels. For example, when
The GPIB uses active
devices send a TTL low level (50.8 V), and when DAV is
DAV is active, the
madeinactive, the line has a TiL high level(e2.0V).

5.7 INTERRUPT STRUCTURE

which the processor (CPU) is made to transfer control

Interrupt is a mechanism by
execution to another program of more importance or
from its current program
may be given to the processor by any external
higher priority. The interrupt signal
interrupts are generated by a variety of sources,
peripheral device. In general, CPU.
either internal or external,
to the Interrupts are the primary means by which
devices obtain the services of the CPU.
input and output called interrupt
routine that is executed upon interrupt is
The program or the
(ISR). The processor must temporarilystop its current task and
Service routine
event or device that issues
execute the ISR,
which relates specifically to the
must return to
execution of the ISR, the processor
the interrupt signal. After and proper
Processors have many interrupt signals
the interrupted program.
identification of interrupt signals
is done internally by the processor.
are as follows:
structure of any microprocessor
The key features in the interrupt
of interrupt signals available.
(i) The number and types
where the ISR is located for a particular interrupt
(ii) The address of the memory vector address.
signal. This address is called interrupt This feature
feature for the interrupt signals.
(i) The masking and unmasking when required.
execute the ISR only
allows the programmer to
are available
when more than one interrupt signals
iv) The priority of interrupts
(v) The timing of the interrupt signals program
of information about the interrupted
(vi) The handling and storing loaded into the CPU when
(status intormation). This information must be is
return instruction
is executed, control
the ISR is executed. When the
transferred back to the interrupted program.

5.8 TYPES OF INTERRUPTS

vector address, and
classified based on their maskability, interrupt
nterrupts are 5.8.1-5.8.3.
classifications are discussed in Sections
source. These

5.8.1 Vectored and Non-vectored Interrupts

are as follows:
The vectored and non-vectored interrupts address for ISRs of
vector
Non-vectored interrupts have fixed interrupt where there
are useful for small systems,
ditferent interrupt signals. They software structure is not
complicated.
the
are interrupt sources and
few vector address
to be supplied by
require the interrupt
) Vectored interrupts This technique, called
the interrupt signal.
the external device that gives
of ways.
in a number
vectoring, is implemented
 166 MICROPROCESSORS AND MICROCONTROLLERS

5.8.2 Maskable and Non-maskable Interrupts

The maskable and non-maskable interrupts are as follows:
) Maskable intemupts are interupts that can be blocked, the
corresponding
are not executed. The masking can be done by software or hardware meane
tso
ii) Non-maskable interrupts (NMIs) are interrupts that are always recognize
the corresponding ISRs are executed.

5.8.3 Software and Hardware Interrupts

The software and hardware interrupts are as follows:
() Software interrupts are special instructions, which after execution transfer
the control to a predefined ISR. These instructions are included in the
program by the programmer.
1i) Hardware interrupts are signals given to the
processor, for recognition as an
interrupt and execution of the corresponding ISR.

5.9 INTERRUPT HANDLING PROCEDURE

When an interrupt signal is
recognized, the processor will have to store information
about the current program before
executing the ISR. The processor checks for the
interrupt request signals at the end of every instruction execution. If the interrupt is
masked, it will not be recognized until interrupts are re-enabled. The CPU
to an interrupt responds
request by a transfer of control to another program, in a manner
similar to a subroutine call. This is shown
pictorially in Fig. 5.7. The sequence of
operations that take place when an interrupt signal is recognized is as follows:
) Save the program counter (PC) contents
(address of the next instruction)
and supplementary information about the current state
in the stack.
(flags, registers, etc.)
(ii) Load PC with the beginning address of an ISR and
start to execute it.
(ii) Finish ISR when the return instruction is executed.
(iv) Return to the point in the
interrupted program where execution was
interrupted.

ISR ISR
ISR

Main Main Main Main

Fig.5.7 Transfer of control from main memory to ISR

Interrupts and stack
memory Stack is a special memory organization tna
operates on the last-in, first-out (LIFO) principle. The data stored
retrieved first. Similarly, data stored first in the recently
stack are read last. Stack is
temporary storage memory in the RAM area. It is basically administered by
special register called stack pointer (SP). SP register always contains the address
of the top of the stack (ToS). Storing a data in the stack memory pointed to by the
 METHODS OF DATA
TRANSFER AND INTERRUPT STRUCTURE IN 8085
16
stack pointer is called push operation.
operation. Reading a data from the stack is called
pop
Stack is used by the interrupt
system of the
the subroutine call and retum
mechanism, passing microprocessor for
implementing
place from the parameters subroutines, etc.
When the transfer of control takes to
the program counter content is stored in
the stack,
interrupted program to the ISR,
the ISR, the control musí returm to the because after the execution of
program counter content. To facilitate
control transfer, the stack pointer must be this
properly initialized to a physically available
memory with sufficient memory range. In the
8085, the stack memory
lower addresses and so, the stack
pointer must be initialized with the grows towards
address allotted for the stack operation. highest memory
The stack can be accessed by the instructions
PUSH and POP. The ISRs
not disturb the return address stored should
by the processor in the stack.
should have equal number of PUSH and POP instructions. So, the ISRs
This condition ensures
that the return address stored in the stack is retrieved
properly by the processor.
5.10 INTERRUPT SOURCES AND VECTOR ADDRESSES IN
8085
Intel 8085 supports both software and hardware
interrupts. Software
are in the form of
instructions; hardware interrupts are applied as interrupts
from signals
external devices.

5.10.1 Software Interrupts

The Intel 8085 instruction set includes
eight software interrupt instructions
called Restart (RST) instructions. These are
one-byte instructions that make the
processor execute a subroutine at predefined locations. The eight software
instructions and their interrupt vector addresses are
interrupt
given in Table 5.3
Table 5.3 Software interrupts and their vector addresses

Instruction Machine hex code Interrupt vector address

RSTO C7 0000H
RST1 CF 0008H
RST 2 D7 0010H
RST 3 DF 0018H
RST 4 E7 0020H
RST 5 EF 0028H
RST 6 F7 0030H
RST 7 FF 0038H

ne software instructions can be treated as CALL instructions with default call

locations. The concept of priority does not apply to software interrupts as they are
nserted into the program as instructions by the programmer and executed by the
processor when the respective program lines are read.
 168 MICROPROCESSORS AND MICRoCONTROLLERS

5.10.2 Hardware Interrupts and Priorities

Intel 8085 has five hardware
interrupts-INTR, RST 5.5, RST 6.6, RST 7
Trap. The details of the five interrupts are given in Table 5.4. Five pins of h
are reserved for these
five hardware interrupts. All the five interrupts are
high signals. This means that to apply an interrupt, a logic T or high-leyel
should be applied at these pins. The
processor checks the voltage on theese pi
after the execution of
every instruction. If the signal level on any of these fiu
Is at logic 1 and the
corresponding interrupt is not masked, the
processor sus
current program and executes the corresponding ISR. RST 7.5 intemup
Is
Cdge-triggered. This means that a transition from logic 0 to logic I istrea
an
interrupt input on this line. The rising edge interrupt can be applied atanvytime
and this sets a flip-flop inside the processor. The processor checks this fin
while checking the signal level on the other hardware interrupts
Table 5.4 Hardware interrupts oi 8085

Interrupt vector Maskable or

Interrupt Edge or leve-triggered
address non-maskable Priority
Trap 0024H Non-maskable Level-triggered
RST 7.5 003CH Maskable Rising edge-triggered 2
RST 6.5 0034H Maskable Level-triggered
RST 5.5 002CH Maskable Level-triggered 4
Decided by
INTR Maskable Level-triggered
hardware

The interrupt vector addresses for the hardware interrupts are given in Table
5.4. It can be seen that the four interrupts Trap, RST 7.5, RST 6.5, and RST 55
have fixed interrupt vector addresses. However, INTR does not have a fxel
interrupt vector address, since Intel has designed the INTR interrupt in a differen
manner. When the INTR interrupt sent by an external device is recognized by te
processor, it gives an active low interrupt acknowledgement (INTA) signal. Upon
receiving this active low signal, the peripheral device that issued the INTR signa
should now place the machine code of the RST instruction to be executed by the
processor on the data bus of the processor. So the processor after issuing low
INTA signal, reads the instruction available on the data bus and places it in the
instruction register for decoding and executing.
Interrupt priority decides which interrupt must be serviced when more than one
interrupt is sensed by the processor. As there are five interrupts, it is possible tha
more than interrupt signal will be applied to the processor by the periphera
one

devices. The interrupt priority indicates the order in which the

interrupts must
serviced. From Table 5.4, it can be seen that
Trap is the highest priority interru
followed by RST 7.5, RST 6.5, and RST 5.5. INTR has the least
In addition to priorities, Intel has
priority. e
provided a feature using which a
program
can suppress the hardware interrupts. This can be done by masking the intemups
TRAP is the only NMI; the other four interrupts can be masked.
 METHODS OF DATA TRANSFER AND INTERRUPT STRUCTURE IN 8085 169

OF INTERRUPTS
5.11 MASKING
Masking can be done for the four hardware interrupts RST 7.5, RST 6.5,
DST 5.5, and INTR. The masking of 8085 interrupts is done at different levels.
Cioure 5.8 shows the organization of hardware interrupts in the 8085. The figure
arly shows that TRAP is an NMI. RST 7.5 interrupt alone has a flip-flop to
clearl
recognize its edge transition. 1 he masking of interrupts can be done using SIM
instpuction. In addition, a separate interrupt enable flip-flop is available to mask or
allow the interrupts. Figure 5.8 is explained in detail by the following five points.
a The maskable interrupts are, by default, masked by the Reset signal. So no
interrupt is recognized by the hardware reset.
(i) The interrupts can be enabled by the execution of the EI instruction. So to
enable the interrupts after resetting the processor, the El instruction must be
used.
three RST interrupts can be selectively masked by loading the
(ii) The
appropriate word in the accumulator and executing the SIM instruction.
This is called software masking.
iv) All the maskable interupts are disabled whenever an interrupt is recognized.
So, it is necessary to execute the El instruction every time the interrupts are
recognized and serviced by the processor.
(v) All the maskable interrupts can be disabled by executing the DI instruction.

Interrupt vector addresses

0024
Trap
Flip-flop
RST 7.5 F 003C

Mask

RST 6.5
0034

Mask

RST 55 002C

Mask

INTR Get opcode

from hardware

DI
E

RESET
Any inlerrupt R
Interrupt enable flip-fop
recognized

Fig.5.8 Interruptstructure of Intel 8085

 170 MICROPROCESSORS AND MICROCONTROLLERS

This instruction resets an interrupt enable flip-fiop in the process

the interrupts are disabled. To enable interrupts, El instruction has

executed.

5.11.1 SIM Instruction

The SIM instruction is used to mask or unmask the restart (RST) hart
ntemupts. The SIM instruction when executed reads the contents of the accumul
and accordingly masks or unmasks the interrupts. So the SIM instruction mu
executed after storing the appropriate control word in the accumulator. The for
of the control word to be stored in the accumulator before executing the St
instruction is shown in Table 5.5.

Accumulator bit pattern for SIM

instruction
Table 5.5

D4 D3 D2 D1 DO
Bit position D7 D6 D5

Name SOD SDE X R7.5 MSE M7.5 M6.5 MS5

Explanation Serial Serial Not Reset Mask set Set to Set to Set t
data data used RST 7.5 enable 1 to I to lto
to be enable- flip-flop Set to 1 mask mask mask
sent set to to mask RST RST RST
1 for interrupts 7.5 6.5 5.5
sending

The least significant three bits D2-DO are used to individually mask the
three RST interrupts, as shown in Table 5.5. These bits are made 0 to unmast
the interrupts and 1 to mask the interrupts. In addition, a master control is alo
provided in the D3 bit. This bit must also be set to I to make the least significant
three bits meaningful. Otherwise, the data in the least significant three bits ae
ignored by the processor.
As already discussed, the RST 7.5 is an edge-triggered interrupt and a separate
used to recognize it. This flip-fop can be reset, thereby ignoring te
fip-flop is
RST7.5 interrupt. This is done by making the D4 bit1.
In addition to masking interrupts, the SIM instruction has another function.ll
can send serial data on the SOD line of the
processor. The data to be sent is placeu
in the MSB of the accumulator and the serial data output is enabled by making e
D6 bit 1.

5.11.2 RIM Instruction

The RIM instruction is used to read the
status of the interrupt mask bits.
the RIM instruction is WI
executed, the accumulator is loaded with the current
ofthe interrupt masks and the pending sta
data stored in the interrupts. The format and meaning o
accumulator after execution of the RIM
Table 5.6. instruction is shoW
The least
significant three bits of the accumulator after executing RIM cti
indicate whether the RST
hardware interrupts are masked. The instrutne bit
1 indicates that the presence of
corresponding interrupt is masked.
 METHODS OF DATA TRANSFER AND INTERRUPT STRUCTURE IN 8085 171

Table 5.6 Accumulator bit pattern after execution of RIM instruction

Bit D7 D6 D5 D4 D3 02 01 DO
position
SID 17.5 16.5 15.5 IE M7.5 M6.5 M5.5
Name
Serial Set to I Set to 1 Set to 1 Set to Set to I Set to 1 Set to 1
Explanation
input if RST if RST ifRST 1if if RST if RST if RST
data 7.5 is 6.5 is 5.5 is
interrupts 7.5 is 6.5 is 5.5 is
in the pending pending pending are masked masked masked
SID enabled
pin

All the hardware interrupts can be masked by executing the DI instruction. To

check whether the interrupts are enabled or disabled, the programmer can check
the D3 bit of the accumulator after executing the RIM instruction. If the D3 bit is
set io 1, it means that the interrupts are enabled. The bits D4-D6 indicate whether
there are any RST intemupts pending. Logic I on these bits indicates that the
coresponding interrupts are pending.
In addition to reading the interrupt mask, the RIM instruction is also used to
read the serial data on the SID pin of the processor. The data on the SID pin is
stored in the MSB of the accumulator after execution of the RIM instruction.

Example:
Write the assembly language program lines to enable all the interrupts in the 8085
after reset.
After reset, all the interrupts are disabled as shown in Fig. 5.8. So, the EI
instruction must be executed. To enable all RST interrupts, the corresponding bits
in the accumulator pattern must be 0 and the Mask Set Enable bit must be 1 before
executing the SIM instruction.
:Enable interrupts.
VI A. 00001000B: Unmask the interrupts.
SIM Set the mask and unmask using SIM instruction.

5.12 TIMING OF INTERRUPTS

The interrupts are sensed by the processor one cycle before the end of execution

of each instruction. An signal must be applied long enough for it tobe

interrupt
recognized. The longest instruction of the 8085 takes 18 clock periods. So, the
interrupt signal must be applied for at least 17.5 clock periods. This decides the
minimum pulse width for the interrupt signals.
The maximum pulse width for the interrupt signals is decided by the condition
that the interrupt signal must not be recognized once again. This is under the
control of the programmer. Once an interrupt is recognized, all interrupts are
disabled. The re-enabling of interrupts is done by executing the instruction EI.
0, the maximum duration for the interrupts is decided by the execution of the
El instruction. The interrupt signal must be removed before the El instruction is
executed so that it will not be recognized once again.
172 MOROPROCESSORS AND
MICROCONTROLLERS

Any other interrupt issued to the microprocessor will be

recognized
instnieonce
o
EI
instruction is executed. If the programmer has written the El
the start of the ISR, the microprocessor can be interrupted once again becloretienath
completion of the ISR.

5.13 INTERFACING OF INTR INTERRUPT WITH 8085

INTR intemupt requires additional hardware for selecting the interrupt
vecte
address. This section explains how the hardware interrupt INTR is executod
how the intempt vector address is selected for the processor. Figure 5.9 show
interfacing of the INTR interrupt. When an external peripheral device issowsthe
INTR request to the 8085, the processor after sensing the INTR interrupt.iste
Issues a
active low INTA signal. It then reads the instruction available onthe data bus
places it in the instruction register for decoding and executing Thehardwar
and
Fig. 5.9 shows the instruction RST 7 with the machine code EF being givento
data bus when low INTA signal is given out by the processor. So, upon receivi
the opcode EF, the processor calls the subroutine at the address 0038H. eivim

5V

10K 10K
5V

D7
GND

D6

74LS244
p4

8085
DO
2G
Data EFh

INTA

Fig. 5.9 Hardware for INTR interrupts